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fpga/uart.git
2011-05-18 Vladimir BurianResets changed from asynchronous to synchronous. master commit | commitdiff | tree | snapshot
2011-05-18 Vladimir BurianEarly initialization of all relevant signals. commit | commitdiff | tree | snapshot
2011-02-04 Vladimir BurianReceiving capability added to the top component. commit | commitdiff | tree | snapshot
2011-02-04 Vladimir BurianRX modul synchronization changed to falling edges. commit | commitdiff | tree | snapshot
2011-02-04 Vladimir BurianBaud generator ClockEnable added. commit | commitdiff | tree | snapshot
2011-02-04 Vladimir BurianReceiver control FSM prototype. commit | commitdiff | tree | snapshot
2011-02-04 Vladimir BurianFirst prototype of receiver shift register. commit | commitdiff | tree | snapshot
2011-01-28 Vladimir BurianSome comments added. commit | commitdiff | tree | snapshot
2011-01-22 Vladimir BurianClear of FIFO overflow flag capability added. commit | commitdiff | tree | snapshot
2011-01-22 Vladimir BurianBaud_gen scale input width redefined as generic. Defaul... commit | commitdiff | tree | snapshot
2011-01-22 Vladimir BurianFirst working prototype of HW UART - TX part. commit | commitdiff | tree | snapshot
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