]> rtime.felk.cvut.cz Git - fpga/uart.git/commit
Receiving capability added to the top component.
authorVladimir Burian <buriavl2@fel.cvut.cz>
Fri, 4 Feb 2011 13:06:14 +0000 (14:06 +0100)
committerVladimir Burian <buriavl2@fel.cvut.cz>
Fri, 4 Feb 2011 13:06:14 +0000 (14:06 +0100)
commit81d30909cb24a0f382a045c90f11444dd35cc1cf
tree1ef0a7656f1a805c23ea3fde2fcaee7c25e736c9
parenta168a3efb68bc9daad5515401a94450b08689053
Receiving capability added to the top component.

Now receiving and transmitting works and is usable. In the USTAT
register there are flags of TX and RX FIFOs states. In the UIE
register coresponding interrupts can be enabled.
tb/tb_uart.vhd
uart.vhd