RX modul synchronization changed to falling edges.

diff --git a/rx.vhd b/rx.vhd
index 5a7bde6967a3670be4b2f4d238a941ae47f18a26..11dc9d9d478f5bdd034c0c50275d485706db98cd 100644 (file)
--- a/rx.vhd
+++ b/rx.vhd
@@ -12,13 +12,14 @@ use ieee.std_logic_unsigned.all;
 --
 -- Receiving is done by the following procedure:
 --      - wait until 'ready' = 1
---      - set 'en' and raise 'clk' positive edge (1st bit is sampled)
+--      - set 'en' and make 'clk' falling edge (1st bit is sampled)
 --      - 'ready' goes to 0
 --      - continue generating clock signal until 'ready' = 1 again
 --      - frame is received
 --
 -- All operations, 'rx' sampling, etc. (except for reset) are synchronous to
--- 'clk' rising egdes.
+-- 'clk' !!! FALLING !!! egdes. The reason is that sampling should occurs in the
+-- middle of period where usally clock signal is falling.
 --
 -- Invalid start bit is signalized at the begining of the frame, so the
 -- receiving can be immediately stopped by receiver reset.
@@ -58,7 +59,7 @@ begin
       bad_stop_bit  <= '0';
       bad_start_bit <= '0';
 
-    elsif clk'event and clk = '1' then
+    elsif clk'event and clk = '0' then
       -- Start receiving a new frame
       if rx_ready = '1' and en = '1' then
         rx_shift_reg <= rx & rx_shift_reg (9 downto 1);