]> rtime.felk.cvut.cz Git - fpga/uart.git/commit
Baud generator ClockEnable added.
authorVladimir Burian <buriavl2@fel.cvut.cz>
Fri, 4 Feb 2011 10:14:31 +0000 (11:14 +0100)
committerVladimir Burian <buriavl2@fel.cvut.cz>
Fri, 4 Feb 2011 11:04:02 +0000 (12:04 +0100)
commita1d94cc6bbfe56f8e7b90d1f870db3fed5a86dea
treeac038f0f81521cd590773a1d070dd440177c9e58
parent660aa732936779b9411182d719f5e38d9a81a3e8
Baud generator ClockEnable added.
baud_gen.vhd
tb/tb_baud_gen.vhd
uart.vhd