Resets changed from asynchronous to synchronous.

diff --git a/baud_gen.vhd b/baud_gen.vhd
index f3312f0c66cd0df1b75980ecbcc71339dc6ccc8b..b752d08a612acb81db515af8508790d274beaed1 100644 (file)
--- a/baud_gen.vhd
+++ b/baud_gen.vhd
@@ -56,22 +56,24 @@ begin
 
   process (clk, reset)
   begin
-    if (reset = '1') then
-      counter <= (others => '0');
-      clk_baud_s <= '0';
-      
-    elsif (rising_edge(clk)) then
-      if (clk_baud_s = '0' and ce = '0') then
+    if (rising_edge(clk)) then
+      if (reset = '1') then
         counter <= (others => '0');
+        clk_baud_s <= '0';
 
       else
-        if (counter = 0) then
-          counter    <= scale;
-          clk_baud_s <= not clk_baud_s;
+        if (clk_baud_s = '0' and ce = '0') then
+          counter <= (others => '0');
 
         else
-          counter <= counter - 1;
+          if (counter = 0) then
+            counter    <= scale;
+            clk_baud_s <= not clk_baud_s;
 
+          else
+            counter <= counter - 1;
+
+          end if;
         end if;
       end if;
     end if;

diff --git a/fifo.vhd b/fifo.vhd
index f59a43826c466a01176fe8b0d6be39d0c3158d27..84370e5d5fb6af33d6d7ba807d4c8d733c102d42 100644 (file)
--- a/fifo.vhd
+++ b/fifo.vhd
@@ -61,23 +61,25 @@ begin
   --   the number of occupied memory positions.
   process (clk, reset)
   begin
-    if (reset = '1') then
-      length <= (others => '0');
-      overflow <= '0';
-      
-    elsif (rising_edge(clk)) then
-      if ((re = '1') and (we = '0')) then
-        length <= length - 1;
-      elsif ((re = '0') and (we = '1')) then
-        if (full_s = '1') then
-          overflow <= '1';
-        else
-          length <= length + 1;
-        end if;
-      end if;
-      
-      if (clear_ow = '1') then
+    if (rising_edge(clk)) then
+      if (reset = '1') then
+        length <= (others => '0');
         overflow <= '0';
+
+      else
+        if ((re = '1') and (we = '0')) then
+          length <= length - 1;
+        elsif ((re = '0') and (we = '1')) then
+          if (full_s = '1') then
+            overflow <= '1';
+          else
+            length <= length + 1;
+          end if;
+        end if;
+        
+        if (clear_ow = '1') then
+          overflow <= '0';
+        end if;
       end if;
     end if;
   end process;

diff --git a/rx.vhd b/rx.vhd
index db1c13246b2516daa90266fe18bc65ae45661d20..214b6d9dd1dc03ea0734d4a904ab0bd9880235d0 100644 (file)
--- a/rx.vhd
+++ b/rx.vhd
@@ -52,38 +52,39 @@ begin
 
   process (clk, reset) is
   begin
-    if reset = '1' then
-      rx_ready   <= '1';
-      rx_running <= '0';
-      
-      bad_stop_bit  <= '0';
-      bad_start_bit <= '0';
+    if clk'event and clk = '0' then
+      if reset = '1' then
+        rx_ready   <= '1';
+        rx_running <= '0';
+        
+        bad_stop_bit  <= '0';
+        bad_start_bit <= '0';
 
-    elsif clk'event and clk = '0' then
-      -- Start receiving a new frame
-      if rx_ready = '1' and en = '1' then
-        rx_shift_reg <= rx & rx_shift_reg (9 downto 1);
-        rx_flag      <= "0100000000";
-        rx_ready     <= '0';
-        rx_running   <= '1';
+      else
+        -- Start receiving a new frame
+        if rx_ready = '1' and en = '1' then
+          rx_shift_reg <= rx & rx_shift_reg (9 downto 1);
+          rx_flag      <= "0100000000";
+          rx_ready     <= '0';
+          rx_running   <= '1';
 
-        bad_start_bit <= rx;
-        bad_stop_bit  <= '0';
+          bad_start_bit <= rx;
+          bad_stop_bit  <= '0';
 
-      -- Receiving of the 1st data bit and all its consequents
-      elsif rx_running = '1' then
-        rx_shift_reg <= rx & rx_shift_reg (9 downto 1);
-        rx_flag      <= '0' & rx_flag (9 downto 1);
+        -- Receiving of the 1st data bit and all its consequents
+        elsif rx_running = '1' then
+          rx_shift_reg <= rx & rx_shift_reg (9 downto 1);
+          rx_flag      <= '0' & rx_flag (9 downto 1);
 
-        -- End of the frame is comming
-        if rx_flag (0) = '1' then
-          rx_ready   <= '1';
-          rx_running <= '0';
+          -- End of the frame is comming
+          if rx_flag (0) = '1' then
+            rx_ready   <= '1';
+            rx_running <= '0';
 
-          bad_stop_bit <= not rx;
+            bad_stop_bit <= not rx;
+          end if;
         end if;
       end if;
-      
     end if;
   end process;
   

diff --git a/rx_control.vhd b/rx_control.vhd
index 80904fad877aa8be22a985717cf8191dc88c375f..2fb836f8acaade2cd01f09979a385fa1a37120e6 100644 (file)
--- a/rx_control.vhd
+++ b/rx_control.vhd
@@ -31,69 +31,71 @@ begin
 
   process (clk, reset) is
   begin
-    if reset = '1' then
-      state    <= waiting;
-      rx_reset <= '0';
-      rx_en    <= '0';
-      fifo_we  <= '0';
-      clk_en   <= '0';
-
-    elsif clk'event and clk = '1' then
-      case state is
-        when resetting =>
-          state    <= waiting;
-          rx_reset <= '0';
-          rx_en    <= '0';
-          fifo_we  <= '0';
-          clk_en   <= '0';
-
-
-        when waiting =>
-          rx_reset <= '0';
-          rx_en    <= '0';
-          fifo_we  <= '0';
-          clk_en   <= '0';
-
-          if rx = '0' then
-            state  <= next_frame;
-            rx_en  <= '1';
-            clk_en <= '1';
-          end if;
-
-
-        when next_frame =>
-          rx_reset <= '0';
-          rx_en    <= '1';
-          fifo_we  <= '0';
-          clk_en   <= '1';
-
-          if rx_ready = '0' then
-            if bad_start_bit = '1' then
-              state    <= resetting;
-              rx_reset <= '1';
-              rx_en    <= '0';
-              clk_en   <= '0';
-
-            else
-              state <= receiving;
-              rx_en <= '0';
+    if clk'event and clk = '1' then
+      if reset = '1' then
+        state    <= waiting;
+        rx_reset <= '0';
+        rx_en    <= '0';
+        fifo_we  <= '0';
+        clk_en   <= '0';
+
+      else
+        case state is
+          when resetting =>
+            state    <= waiting;
+            rx_reset <= '0';
+            rx_en    <= '0';
+            fifo_we  <= '0';
+            clk_en   <= '0';
+
+
+          when waiting =>
+            rx_reset <= '0';
+            rx_en    <= '0';
+            fifo_we  <= '0';
+            clk_en   <= '0';
+
+            if rx = '0' then
+              state  <= next_frame;
+              rx_en  <= '1';
+              clk_en <= '1';
             end if;
-          end if;
 
 
-        when receiving =>
-          rx_reset <= '0';
-          rx_en    <= '0';
-          fifo_we  <= '0';
-          clk_en   <= '1';
+          when next_frame =>
+            rx_reset <= '0';
+            rx_en    <= '1';
+            fifo_we  <= '0';
+            clk_en   <= '1';
 
-          if rx_ready = '1' then
-            state   <= waiting;
-            fifo_we <= '1';
-            clk_en  <= '0';
-          end if;
+            if rx_ready = '0' then
+              if bad_start_bit = '1' then
+                state    <= resetting;
+                rx_reset <= '1';
+                rx_en    <= '0';
+                clk_en   <= '0';
 
-      end case;
+              else
+                state <= receiving;
+                rx_en <= '0';
+              end if;
+            end if;
+
+
+          when receiving =>
+            rx_reset <= '0';
+            rx_en    <= '0';
+            fifo_we  <= '0';
+            clk_en   <= '1';
+
+            if rx_ready = '1' then
+              state   <= waiting;
+              fifo_we <= '1';
+              clk_en  <= '0';
+            end if;
+
+        end case;
+      end if;
     end if;
   end process;
 

diff --git a/tx.vhd b/tx.vhd
index 278d6b811761f543c6e3b1247e7ae1ec6a2f2185..9d777c78219d28a5414ab14841c130d8a9c08413 100644 (file)
--- a/tx.vhd
+++ b/tx.vhd
@@ -45,25 +45,27 @@ begin
 
   process (clk, reset)
   begin
-    if (reset = '1') then
-      tx_shift_reg <= "1111111111";
-      tx_flag <= "0000000000";
-      tx_ready <= '1';
+    if (rising_edge(clk)) then
+      if (reset = '1') then
+        tx_shift_reg <= "1111111111";
+        tx_flag <= "0000000000";
+        tx_ready <= '1';
       
-    elsif (rising_edge(clk)) then
-      if (we = '1') then
-        tx_shift_reg <= '1' & data & '0';
-        tx_flag <= "1000000000";
-        tx_ready <= '0';
-        
-      else
-        tx_shift_reg <= '1' & tx_shift_reg(9 downto 1);
-        tx_flag <= '0' & tx_flag(9 downto 1);
-        
-        if (tx_flag(1) = '1') then
-          tx_ready <= '1';
+      else  
+        if (we = '1') then
+          tx_shift_reg <= '1' & data & '0';
+          tx_flag <= "1000000000";
+          tx_ready <= '0';
+          
+        else
+          tx_shift_reg <= '1' & tx_shift_reg(9 downto 1);
+          tx_flag <= '0' & tx_flag(9 downto 1);
+          
+          if (tx_flag(1) = '1') then
+            tx_ready <= '1';
+          end if;
+          
         end if;
-        
       end if;
     end if;
   end process;

diff --git a/tx_control.vhd b/tx_control.vhd
index f3294c99dc44bbc53e55ebd4b094b59e93ab0763..b78f8160c3dfeb20efe004dbec7faeaaf44e3530 100644 (file)
--- a/tx_control.vhd
+++ b/tx_control.vhd
@@ -35,30 +35,32 @@ begin
 
   process (clk, reset)
   begin
-    if (reset = '1') then
-      state <= waiting;
-      
-    elsif (rising_edge(clk)) then
-      case state is
-        when waiting =>
-          if (fifo_empty = '0') then
-            state <= next_frame;
-          end if;
-        
-        when next_frame =>
-          if (tx_ready = '0') then
-            state <= transmitting;
-          end if;
-        
-        when transmitting =>
-          if (tx_ready = '1') then
+    if (rising_edge(clk)) then
+      if (reset = '1') then
+        state <= waiting;
+
+      else
+        case state is
+          when waiting =>
             if (fifo_empty = '0') then
               state <= next_frame;
-            else
-              state <= waiting;
             end if;
-          end if;
-      end case;
+          
+          when next_frame =>
+            if (tx_ready = '0') then
+              state <= transmitting;
+            end if;
+          
+          when transmitting =>
+            if (tx_ready = '1') then
+              if (fifo_empty = '0') then
+                state <= next_frame;
+              else
+                state <= waiting;
+              end if;
+            end if;
+        end case;
+      end if;
     end if;
   end process;
 

diff --git a/uart.vhd b/uart.vhd
index 09450f91f1bc0ada7428853220b7ad17ca45573b..da189c487fe6fd12e3d6f496011b35fbc79b79c6 100644 (file)
--- a/uart.vhd
+++ b/uart.vhd
@@ -284,21 +284,23 @@ begin
   
   process (mclk, puc) is
   begin
-    if puc = '1' then
-      reg_baud <= (others => '0');
-      reg_ie   <= (others => '0');
-      
-    elsif mclk'event and mclk = '1' then
-      if reg_we (UBAUD) = '1' then
-        reg_baud (7 downto 0) <= per_din_low;
-      end if;
+    if mclk'event and mclk = '1' then
+      if puc = '1' then
+        reg_baud <= (others => '0');
+        reg_ie   <= (others => '0');
+
+      else
+        if reg_we (UBAUD) = '1' then
+          reg_baud (7 downto 0) <= per_din_low;
+        end if;
 
-      if reg_we (UBAUD+1) = '1' then
-        reg_baud (15 downto 8) <= per_din_high;
-      end if;
+        if reg_we (UBAUD+1) = '1' then
+          reg_baud (15 downto 8) <= per_din_high;
+        end if;
 
-      if reg_we (USTAT) = '1' then
-        reg_ie <= per_din_low;
+        if reg_we (USTAT) = '1' then
+          reg_ie <= per_din_low;
+        end if;
       end if;
     end if;
   end process;