Baud_gen scale input width redefined as generic. Default value is 16.

diff --git a/baud_gen.vhd b/baud_gen.vhd
index ebe6b388787c0b9488aa4202ea2d7aebb64f300a..20f80100b09b9cf8b6b4c21cd8f94a3614aeee01 100644 (file)
--- a/baud_gen.vhd
+++ b/baud_gen.vhd
@@ -4,10 +4,13 @@ use ieee.std_logic_arith.all;
 use ieee.std_logic_unsigned.all;
 
 entity baud_gen is
+  generic (
+    SCALE_WIDTH : integer := 16
+  );
   port (
     clk      : in  std_logic;
     reset    : in  std_logic;
-    scale    : in  std_logic_vector (15 downto 0);
+    scale    : in  std_logic_vector (SCALE_WIDTH-1 downto 0);
     clk_baud : out std_logic
   );
 end baud_gen;
@@ -16,7 +19,7 @@ end baud_gen;
 
 architecture behavioral of baud_gen is
 
-  signal counter    : std_logic_vector (15 downto 0);
+  signal counter    : std_logic_vector (SCALE_WIDTH-1 downto 0);
   signal clk_baud_s : std_logic;
 
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