--
-- The divided clock signal has a duty cycle of 50%.
--
--- The reset input signal is asynchronous. When held active, the output is 0.
--- When released, the output starts a new period and goes high with the next
--- rising edge of the input clock signal.
+-- Change of 'scale' doesn't affect current half-period.
+--
+-- The reset input signal is asynchronous. All others are synchronous to clk
+-- rising egde. In default state (when stopped), output is low. When CE goes
+-- high, 'clk_baud' goes high with next clock rising edge. When CE goes low,
+-- eventual high half-period is finished and then generator stops with low
+-- output.
--
-- _ _ _ _ _ _ _ _ _ _ _ _
-- CLK _| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_
--- _________
--- RESET ____________| |__________________________
--- ___ __ ___ ___ ___
--- CLK_BAUD _| |___| |____________| |___| |___| |___
+-- _____
+-- RESET ________________| |__________________________
+-- _____________________________
+-- CE ____| |______________
+-- ___ __ ___ ___
+-- CLK_BAUD _____| |___| |________| |___| |___________
--
--------------------------------------------------------------------------------
);
port (
clk : in std_logic;
+ ce : in std_logic;
reset : in std_logic;
scale : in std_logic_vector (SCALE_WIDTH-1 downto 0);
clk_baud : out std_logic
clk_baud_s <= '0';
elsif (rising_edge(clk)) then
- if (counter = 0) then
- counter <= scale;
- clk_baud_s <= not clk_baud_s;
-
+ if (clk_baud_s = '0' and ce = '0') then
+ counter <= (others => '0');
+
else
- counter <= counter - 1;
+ if (counter = 0) then
+ counter <= scale;
+ clk_baud_s <= not clk_baud_s;
+
+ else
+ counter <= counter - 1;
+ end if;
end if;
end if;
end process;