]> rtime.felk.cvut.cz Git - fpga/uart.git/commit
Early initialization of all relevant signals.
authorVladimir Burian <buriavl2@fel.cvut.cz>
Wed, 18 May 2011 19:37:06 +0000 (21:37 +0200)
committerVladimir Burian <buriavl2@fel.cvut.cz>
Wed, 18 May 2011 19:37:06 +0000 (21:37 +0200)
commit6ce709d167d1e0f4b0ab62ad931b737ea781136a
tree5c20dcb012f0289b680591975d811efde323fd78
parent81d30909cb24a0f382a045c90f11444dd35cc1cf
Early initialization of all relevant signals.

Now it is not required to do reset after start-up.
baud_gen.vhd
fifo.vhd
rx.vhd
rx_control.vhd
tx.vhd
tx_control.vhd
uart.vhd