reset : in std_logic;
we : in std_logic;
re : in std_logic;
+ clear_ow : in std_logic;
d_in : in std_logic_vector (7 downto 0);
d_out : out std_logic_vector (7 downto 0);
full : out std_logic;
length <= length + 1;
end if;
end if;
+
+ if (clear_ow = '1') then
+ overflow <= '0';
+ end if;
end if;
end process;
reset : in std_logic;
we : in std_logic;
re : in std_logic;
+ clear_ow : in std_logic;
d_in : in std_logic_vector (7 downto 0);
d_out : out std_logic_vector (7 downto 0);
full : out std_logic;
reset => puc,
we => tx_fifo_we,
re => tx_fifo_re,
+ clear_ow => '0',
d_in => per_din (7 downto 0),
d_out => tx_data,
full => open,