rtime.felk.cvut.cz Git - fpga/uart.git/search

]> rtime.felk.cvut.cz Git - fpga/uart.git/search

2011-05-18	Vladimir Burian	Resets changed from asynchronous to synchronous.	commit \| commitdiff \| tree
2011-05-18	Vladimir Burian	Early initialization of all relevant signals.	commit \| commitdiff \| tree
2011-02-04	Vladimir Burian	Receiving capability added to the top component.	commit \| commitdiff \| tree
2011-02-04	Vladimir Burian	RX modul synchronization changed to falling edges.	commit \| commitdiff \| tree
2011-02-04	Vladimir Burian	Baud generator ClockEnable added.	commit \| commitdiff \| tree
2011-02-04	Vladimir Burian	Receiver control FSM prototype.	commit \| commitdiff \| tree
2011-02-04	Vladimir Burian	First prototype of receiver shift register.	commit \| commitdiff \| tree
2011-01-28	Vladimir Burian	Some comments added.	commit \| commitdiff \| tree
2011-01-22	Vladimir Burian	Clear of FIFO overflow flag capability added.	commit \| commitdiff \| tree
2011-01-22	Vladimir Burian	Baud_gen scale input width redefined as generic. Default...	commit \| commitdiff \| tree
2011-01-22	Vladimir Burian	First working prototype of HW UART - TX part.	commit \| commitdiff \| tree

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