rtime.felk.cvut.cz Git - fpga/lx-cpu1/lx-dad.git/history

]> rtime.felk.cvut.cz Git - fpga/lx-cpu1/lx-dad.git/history - hw/lx_dad_top.vhd

2015-11-03	Pavel Pisa	Re-implemented ADC start logic to enable multiple sampl...	blob \| commitdiff \| raw
2015-05-20	Jan Novotny	fixed FPGA buggs, added support for single shot measure...	blob \| commitdiff \| raw \| diff to current
2015-04-30	Jan Novotny	modified project files to support new features	blob \| commitdiff \| raw \| diff to current
2015-02-15	Pavel Pisa	Simplify FPGA design external CPU read logic.	blob \| commitdiff \| raw \| diff to current
2015-02-15	Pavel Pisa	Remove nonstandard ieee.std_logic_arith and ieee.std_lo...	blob \| commitdiff \| raw \| diff to current
2015-02-15	Pavel Pisa	Disable use of unisim library to allow simulation by...	blob \| commitdiff \| raw \| diff to current
2015-02-15	Pavel Pisa	Include hardware design of FPGA peripherals to external...	blob \| commitdiff \| raw \| diff to current