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(parent: 5c7e2fd) | patch
Include hardware design of FPGA peripherals to external LPC bus connection.
authorPavel Pisa <pisa@cmp.felk.cvut.cz>
Sun, 15 Feb 2015 00:36:19 +0000 (01:36 +0100)
committerPavel Pisa <pisa@cmp.felk.cvut.cz>
Sun, 15 Feb 2015 00:36:19 +0000 (01:36 +0100)
commit5b8016f69c749cef8cc64cbe5a43ffbf0200fef0
tree2bd9207e14f99fa77bd64738ddc1f8d272ed9178tree | snapshot
parent5c7e2fd61de5dd60f8b92fce2c0967bde37b38d0commit | diff
Include hardware design of FPGA peripherals to external LPC bus connection.

Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
15 files changed:
hw/Makefile [new file with mode: 0644] blob
hw/bus_example.vhd [new file with mode: 0644] blob
hw/bus_measurement.vhd [new file with mode: 0644] blob
hw/cnt_div.vhd [new file with mode: 0644] blob
hw/dff2.vhd [new file with mode: 0644] blob
hw/dff3.vhd [new file with mode: 0644] blob
hw/lx-dad.ucf [new file with mode: 0644] blob
hw/lx_crosdom_ser_fifo.vhd [new file with mode: 0644] blob
hw/lx_dad_pkg.vhd [new file with mode: 0644] blob
hw/lx_dad_top.prj [new file with mode: 0644] blob
hw/lx_dad_top.vhd [new file with mode: 0644] blob
hw/measurement_register.vhd [new file with mode: 0644] blob
hw/packager.c [new file with mode: 0644] blob
hw/util_pkg.vhd [new file with mode: 0644] blob
hw/xilinx_dualport_bram.vhd [new file with mode: 0644] blob