hw/lx_dad_top.vhd

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 -- Disable next libraries for simulation in GHDL
   6 --library unisim;
   7 --use unisim.vcomponents.all;
   8
   9 use work.lx_dad_pkg.all;
  10
  11 -- lx_dad_top - wires the modules with the outside world
  12
  13 -- ======================================================
  14 --  MASTER CPU EXTERNAL MEMORY BUS
  15 -- ======================================================
  16 --
  17 -- Master cpu memory bus has the following wires:
  18 --
  19 -- - address[15..0]          The address, used to mark chip enable
  20 -- - data_in[31..0]          The data coming to bus
  21 -- - data_out[31..0]         The data coming from bus, multiplexed
  22 -- - bls[3..0]               Write enable for respective bytes
  23
  24 entity lx_dad_top is
  25         port
  26         (
  27                 -- External
  28                 --clk_cpu     : in std_logic;
  29                 clk_50m     : in std_logic;
  30                 --
  31                 cs0_xc      : in std_logic;
  32                 --
  33                 rd          : in std_logic;
  34                 bls         : in std_logic_vector(3 downto 0);
  35                 address     : in std_logic_vector(15 downto 0);
  36                 data        : inout std_logic_vector(31 downto 0);
  37                 --
  38                 init        : in std_logic;
  39                 -- signal connected to external JK FF
  40                 event_jk_j  : out std_logic;
  41                 -- signals to image sensor
  42                 phi1        : out std_logic;
  43                 phi2        : out std_logic;
  44                 phi_rst     : out std_logic;
  45                 LED_1       : out std_logic;
  46                 sck_o           : out std_logic;
  47                 cnv_o           : out std_logic;
  48                 phist           : out std_logic;
  49                 sck_i           : in std_logic;
  50                 SDI             : in std_logic
  51
  52         );
  53 end lx_dad_top;
  54
  55 architecture Behavioral of lx_dad_top is
  56
  57         -- Reset signal
  58         signal reset_s                  : std_logic;
  59         signal init_s                   : std_logic;
  60         -- Peripherals on the memory buses
  61         -- Example memory
  62         signal example_out_s            : std_logic_vector(31 downto 0);
  63         signal example_ce_s             : std_logic;
  64         -- Measurement (Master)
  65         signal meas_out_s               : std_logic_vector(31 downto 0);
  66         signal meas_ce_s                : std_logic;
  67         -- Sensor timing
  68         signal sensor_ce_s                              : std_logic;
  69         signal sensor_out_s                     : std_logic_vector(31 downto 0);
  70         -- sensor memory if
  71         signal sens_mem_ce_s                    : std_logic;
  72         signal sens_mem_out_s                   : std_logic_vector(31 downto 0);
  73
  74         signal sens_adr_s                       : std_logic_vector(10 downto 0);
  75         signal sens_data_s                      : std_logic_vector(31 downto 0);
  76         signal sens_i_bls_s                     : std_logic_vector(3 downto 0);
  77         signal sens_mem_int_ce_s        : std_logic;
  78
  79         -- Signals for external bus transmission
  80         signal data_i_s                 : std_logic_vector(31 downto 0);
  81         signal data_o_s                 : std_logic_vector(31 downto 0);
  82         -- Signals for internal transaction
  83         signal last_address_s           : std_logic_vector(15 downto 0);
  84         signal next_last_address_s              : std_logic_vector(15 downto 0);
  85         signal next_address_hold_s              : std_logic;
  86         signal address_hold_s           : std_logic;
  87         signal last_rd_s                : std_logic;
  88         signal next_last_rd_s           : std_logic;
  89         signal last_bls_s               : std_logic_vector(3 downto 0); -- prev bls_f_s (active 1)
  90         signal next_last_bls_s          : std_logic_vector(3 downto 0);
  91
  92         -- Reading logic for Master CPU:
  93         -- Broadcast rd only till ta (transaction acknowledge)
  94         -- is received, then latch the data till the state of
  95         -- rd or address changes
  96         --
  97         -- Data latching is synchronous - it's purpose is to
  98         -- provide stable data for CPU on the bus
  99         signal cs0_xc_f_s          : std_logic;
 100         signal rd_f_s              : std_logic; -- Filtered RD
 101         signal i_rd_s              : std_logic; -- Internal bus RD (active 1)
 102         signal next_last_i_rd_s    : std_logic;
 103         signal last_i_rd_s         : std_logic; -- Delayed RD bus, used for latching
 104         --
 105         signal address_f_s         : std_logic_vector(15 downto 0); -- Filtered address
 106         --
 107         signal data_f_s            : std_logic_vector(31 downto 0); -- Filterred input data
 108         --
 109         signal data_read_s         : std_logic_vector(31 downto 0); -- Latched read data
 110         signal next_data_read_s    : std_logic_vector(31 downto 0);
 111
 112         -- Writing logic:
 113         signal bls_f_s             : std_logic_vector(3 downto 0); -- Filtered BLS (active 1)
 114         signal i_bls_s             : std_logic_vector(3 downto 0); -- Internal BLS (active 1)
 115         signal next_i_bls_s        : std_logic_vector(3 downto 0);
 116         --
 117         signal data_write_s        : std_logic_vector(31 downto 0); -- Data broadcasted to write
 118         signal next_data_write_s   : std_logic_vector(31 downto 0);
 119
 120         -- signal s0   : std_logic;
 121         -- signal s1   : std_logic;
 122         -- signal s2   : std_logic;
 123
 124         -- XST attributes
 125         attribute REGISTER_DUPLICATION : string;
 126         attribute REGISTER_DUPLICATION of rd : signal is "NO";
 127         attribute REGISTER_DUPLICATION of rd_f_s : signal is "NO";
 128         attribute REGISTER_DUPLICATION of bls : signal is "NO";
 129         attribute REGISTER_DUPLICATION of bls_f_s : signal is "NO";
 130         attribute REGISTER_DUPLICATION of address : signal is "NO";
 131         attribute REGISTER_DUPLICATION of address_f_s : signal is "NO";
 132         attribute REGISTER_DUPLICATION of cs0_xc : signal is "NO";
 133         attribute REGISTER_DUPLICATION of cs0_xc_f_s : signal is "NO";
 134
 135 begin
 136
 137 -- Example connection
 138 memory_bus_example: bus_example
 139         port map
 140         (
 141                 clk_i          => clk_50m,
 142                 reset_i        => reset_s,
 143                 ce_i           => example_ce_s,
 144                 bls_i          => i_bls_s,
 145                 address_i      => address_f_s(11 downto 0),
 146                 data_i         => data_i_s,
 147                 data_o         => example_out_s
 148                 --
 149                 --
 150                 -- additional externally connected signals goes there
 151         );
 152
 153
 154 --Sensor clock generator
 155 mytest: clockgen
 156         port map
 157         (
 158                 clk_i   => clk_50m,
 159                 reset_i => reset_s,
 160                 sck_i   => sck_i,
 161                 SDI     => SDI,
 162                 phi_st  => phist,
 163                 phi_1   => phi1,
 164                 phi_2   => phi2,
 165                 ph_rst  => phi_rst,
 166                 LED     => LED_1,
 167                 sck_o   => sck_o,
 168                 cnv_o   => cnv_o,
 169                 mem_o   => sens_data_s,
 170                 addr_o  => sens_adr_s,
 171                 bls_o   => sens_i_bls_s,
 172                 ce_o    => sens_mem_int_ce_s,
 173                 addr_i  => address_f_s(1 downto 0),
 174                 data_i  => data_i_s,
 175                 ce_i    => sensor_ce_s,
 176                 bls_i   => i_bls_s,
 177                 data_o  => sensor_out_s
 178
 179         );
 180
 181 --sensor memory connection
 182 memory_bus_sensormem: bus_sensor
 183         port map
 184         (
 185                 clk_i           => clk_50m,
 186                 ce_i            => sens_mem_ce_s,
 187                 reset_i         => reset_s,
 188                 bls_i           => i_bls_s,
 189                 address_i       => address_f_s(10 downto 0),
 190                 data_i          => data_i_s,
 191                 data_o          => sens_mem_out_s,
 192                 ce_a_i          => sens_mem_int_ce_s,
 193                 adr_a_i         => sens_adr_s,
 194                 bls_a_i         => sens_i_bls_s,
 195                 dat_a_i         => sens_data_s
 196                 );
 197
 198 -- Measurement
 199 memory_bus_measurement: bus_measurement
 200         port map
 201         (
 202                 clk_i     => clk_50m,
 203                 reset_i   => reset_s,
 204                 ce_i      => meas_ce_s,
 205                 address_i => address_f_s(1 downto 0),
 206                 bls_i     => i_bls_s,
 207                 data_i    => data_i_s,
 208                 data_o    => meas_out_s
 209         );
 210
 211 -- Reset
 212 dff_reset: dff2
 213         port map
 214         (
 215                 clk_i   => clk_50m,
 216                 d_i     => init_s,
 217                 q_o     => reset_s
 218         );
 219
 220         -- Reset
 221         init_s          <= not init;
 222
 223         -- Signalling
 224         data_i_s        <= data_write_s;
 225
 226
 227         event_jk_j <= '0';
 228
 229 -- Bus update
 230 memory_bus_logic:
 231         process(cs0_xc_f_s, rd_f_s, last_rd_s, last_i_rd_s,
 232                 bls_f_s, last_bls_s, data_f_s, data_write_s,
 233                 data_o_s, data_read_s, last_address_s, address_f_s)
 234         begin
 235                 -- Defaults
 236                 next_address_hold_s <= '0';
 237
 238                 -- Check if we have chip select
 239                 if cs0_xc_f_s = '1' then
 240
 241                         -- Reading
 242                         if rd_f_s = '1' then
 243                                 -- Internal read
 244                                 if last_rd_s = '0' or (last_address_s /= address_f_s) then
 245                                         i_rd_s <= '1';
 246                                         next_last_i_rd_s  <= '1';
 247                                 else
 248                                         i_rd_s <= '0';
 249                                         next_last_i_rd_s  <= '0';
 250                                 end if;
 251
 252                                 if last_i_rd_s = '1' then
 253                                         -- Latch data we just read - they are valid in this cycle
 254                                         next_data_read_s <= data_o_s;
 255                                 else
 256                                         next_data_read_s <= data_read_s;
 257                                 end if;
 258                         else
 259                         --      -- Not reading, anything goes
 260                         --      data_read_s       <= (others => 'X');
 261                                 next_data_read_s  <= data_read_s;
 262                                 i_rd_s            <= '0';
 263                                 next_last_i_rd_s  <= '0';
 264                         end if;
 265
 266                         next_last_rd_s            <= rd_f_s;
 267
 268                         -- Data for write are captured only when BLS signals are stable
 269                         if bls_f_s /= "0000" then
 270                                 next_data_write_s <= data_f_s;
 271                                 next_address_hold_s <= '1';
 272                         else
 273                                 next_data_write_s <= data_write_s;
 274                         end if;
 275
 276                         if (bls_f_s /= "0000") or (rd_f_s = '1') then
 277                                 next_last_address_s <= address_f_s;
 278                         else
 279                                 next_last_address_s <= last_address_s;
 280                         end if;
 281                 else
 282                         next_last_rd_s <= '0';
 283                         i_rd_s <= '0';
 284                         next_last_i_rd_s <= '0';
 285
 286                         next_i_bls_s <= "0000";
 287                         next_data_write_s <= data_write_s;
 288                         next_data_read_s  <= data_read_s;
 289                         next_last_address_s <= last_address_s;
 290                 end if;
 291
 292                 -- Data for write are captured at/before BLS signals are negated
 293                 -- and actual write cycle takes place exacly after BLS negation
 294                 if ((last_bls_s and not bls_f_s) /= "0000") or
 295                     ((last_bls_s /= "0000") and (cs0_xc_f_s = '0')) then
 296                         next_i_bls_s <= last_bls_s;
 297                         next_last_bls_s   <= "0000";
 298                         next_address_hold_s <= '1';
 299                 else
 300                         next_i_bls_s <= "0000";
 301                         if cs0_xc_f_s = '1' then
 302                                 next_last_bls_s <= bls_f_s;
 303                         else
 304                                 next_last_bls_s <= "0000" ;
 305                         end if;
 306                 end if;
 307
 308         end process;
 309
 310 -- Bus update
 311 memory_bus_update:
 312         process
 313         begin
 314
 315                 wait until clk_50m = '1' and clk_50m'event;
 316
 317                 address_hold_s <= next_address_hold_s;
 318
 319                 -- Synchronized external signals with main clock domain
 320                 cs0_xc_f_s     <= not cs0_xc;
 321                 bls_f_s        <= not bls;
 322                 rd_f_s         <= not rd;
 323                 data_f_s       <= data;
 324                 if address_hold_s = '0' then
 325                         address_f_s <= address;
 326                 else
 327                         address_f_s <= next_last_address_s;
 328                 end if;
 329
 330                 -- Synchronoust state andvance to next period
 331                 last_bls_s     <= next_last_bls_s;
 332                 last_rd_s      <= next_last_rd_s;
 333                 i_bls_s        <= next_i_bls_s;
 334                 last_i_rd_s    <= next_last_i_rd_s;
 335                 data_write_s   <= next_data_write_s;
 336                 last_address_s <= next_last_address_s;
 337                 data_read_s    <= next_data_read_s;
 338
 339         end process;
 340
 341 -- Do the actual wiring here
 342 memory_bus_wiring:
 343         process(cs0_xc_f_s, i_bls_s, address_f_s, example_out_s, meas_out_s, sensor_out_s, sens_mem_out_s, i_rd_s, last_i_rd_s)
 344         begin
 345
 346                 -- Inactive by default
 347                 example_ce_s           <= '0';
 348                 meas_ce_s              <= '0';
 349                 sensor_ce_s            <= '0';
 350                 sens_mem_ce_s           <= '0';
 351                 data_o_s               <= (others => '0');
 352
 353                 if i_rd_s = '1' or i_bls_s /= "0000" then
 354
 355                         -- Memory Map (16-bit address @ 32-bit each)
 356
 357                         -- Each address is seen as 32-bit entry now
 358                         -- 0x0000 - 0x0FFF: Example memory
 359                         -- 0x1000 - 0x1003: Sensor timing
 360                         -- 0x1FFC - 0x1FFF: Measurement
 361                         -- 0x2000 - 0x3FFF: sensor memory
 362                         -- 0x4000 - 0x8FFF: Free space
 363
 364                         if address_f_s < "0001000000000000" then                  -- Tumbl
 365                                 example_ce_s           <= '1';
 366                         elsif address_f_s(15 downto 2) = "00010000000000" then   -- Sensor timing
 367                                 sensor_ce_s            <= '1';
 368                         elsif address_f_s(15 downto 2) = "00011111111111" then    -- Measurement
 369                                 meas_ce_s              <= '1';
 370                         elsif address_f_s > "0001111111111111" and address_f_s < "0100000000000000" then  -- sensor data
 371                                 sens_mem_ce_s                           <= '1';
 372                         end if;
 373
 374                 end if;
 375
 376                 if last_i_rd_s = '1' then
 377                         if address_f_s < "0001000000000000" then                  -- Tumbl
 378                                 data_o_s               <= example_out_s;
 379                         elsif address_f_s(15 downto 2) = "00011111111111" then    -- Measurement
 380                                 data_o_s               <= meas_out_s;
 381                         elsif address_f_s(15 downto 2) = "00010000000000" then   -- Sensor timing
 382                                 data_o_s                   <= sensor_out_s;
 383                         elsif address_f_s > "0000111111111111" and address_f_s < "0100000000000000" then  -- sensor data
 384                                 data_o_s                       <= sens_mem_out_s;
 385                         end if;
 386                 end if;
 387
 388         end process;
 389
 390 -- If RD and BLS is not high, we must keep DATA at high impedance
 391 -- or the FPGA collides with SDRAM (damaging each other)
 392 memory_bus_out:
 393         process(cs0_xc, rd, data_read_s)
 394         begin
 395
 396                 -- CS0 / RD / BLS are active LOW
 397                 if cs0_xc = '0' and rd = '0' then
 398                         -- Don't risk flipping (between data_o_s and latched data_read_s, it's better to wait)
 399                         -- Maybe check this later.
 400                         -- if last_i_rd_s = '1' then
 401                         --   data <= data_o_s;
 402                         -- else
 403                         data <= data_read_s;
 404                         -- end if;
 405                 else
 406                         -- IMPORTANT!!!
 407                         data <= (others => 'Z');
 408                 end if;
 409
 410         end process;
 411
 412 end Behavioral;
 413