# Reset (active LOW)
NET INIT LOC = P39 | IOSTANDARD = LVCMOS33 | SLEW = SLOW;
+#vlastni vstupy vystupy
+
+NET LED_1 LOC = P1 | IOSTANDARD = LVCMOS33 | SLEW = FAST;
+
+NET phi1 LOC = P74 | IOSTANDARD = LVCMOS33 | SLEW = FAST;
+NET phi2 LOC = P75 | IOSTANDARD = LVCMOS33 | SLEW = FAST;
+NET phi_rst LOC = P78 | IOSTANDARD = LVCMOS33 | SLEW = FAST;
+NET phist LOC = P79 | IOSTANDARD = LVCMOS33 | SLEW = FAST;
+NET sck_o LOC = P80 | IOSTANDARD = LVCMOS33 | SLEW = FAST;
+NET sck_i CLOCK_DEDICATED_ROUTE = FALSE;
+NET sck_i LOC = P81 | IOSTANDARD = LVCMOS33 | SLEW = FAST | PULLUP;
+NET SDI LOC = P83 | IOSTANDARD = LVCMOS33 | SLEW = FAST | PULLUP;
+NET cnv_o LOC = P82 | IOSTANDARD = LVCMOS33 | SLEW = FAST;
+
+
+
+#konec vlastniho
+
# Memory peripheral
NET CS0_XC LOC = P64 | IOSTANDARD = LVCMOS33 | SLEW = FAST;
-#NET CS1_XC LOC = P1 | IOSTANDARD = LVCMOS33 | SLEW = FAST;
+
NET RD LOC = P60 | IOSTANDARD = LVCMOS33 | SLEW = FAST;
NET BLS<0> LOC = P70 | IOSTANDARD = LVCMOS33 | SLEW = FAST;
package lx_dad_pkg is
+ component clockgen
+ port
+ (
+ -- inputs
+ clk_i : in std_logic;
+ reset_i : in std_logic;
+ sck_i : in std_logic;
+ SDI : in std_logic;
+ -- outputs
+ phi_1 : out std_logic;
+ phi_2 : out std_logic;
+ phi_st : out std_logic;
+ ph_rst : out std_logic;
+ LED : out std_logic;
+ sck_o : out std_logic;
+ cnv_o : out std_logic;
+
+
+ mem_o : out std_logic_vector(31 downto 0);
+
+ --memory related outputs
+ addr_o : out std_logic_vector(10 downto 0);
+ bls_o : out std_logic_vector(3 downto 0);
+ ce_o : out std_logic;
+
+ -- mem related inputs
+
+ addr_i : in std_logic_vector(1 downto 0);
+ data_i : in std_logic_vector(31 downto 0);
+ ce_i : in std_logic;
+ bls_i : in std_logic_vector(3 downto 0);
+ data_o : out std_logic_vector(31 downto 0)
+
+
+ );
+ end component;
+
+ component bus_sensor is
+ port
+ (
+ -- Clock
+ clk_i : in std_logic;
+ -- Chip enable
+ ce_i : in std_logic;
+ -- Global Reset
+ reset_i : in std_logic;
+ -- Master CPU peripheral bus
+ bls_i : in std_logic_vector(3 downto 0);
+ address_i : in std_logic_vector(10 downto 0);
+ data_i : in std_logic_vector(31 downto 0);
+ data_o : out std_logic_vector(31 downto 0);
+
+
+ -- Memory wiring for internal state automata use
+ ce_a_i : in std_logic;
+ adr_a_i : in std_logic_vector(10 downto 0);
+ bls_a_i : in std_logic_vector(3 downto 0);
+ dat_a_i : in std_logic_vector(31 downto 0)
+ -- Non bus signals
+ --
+ -- Add there external component signals
+ );
+ end component;
+
+ component sensor_mem is
+ port
+ (
+ -- Memory wiring for internal state automata use
+ clk_i : in std_logic;
+ ce_i : in std_logic;
+ adr_i : in std_logic_vector(10 downto 0);
+ bls_i : in std_logic_vector(3 downto 0);
+ dat_i : in std_logic_vector(31 downto 0);
+ dat_o : out std_logic_vector(31 downto 0);
+ -- Memory wiring for Master CPU
+ clk_m : in std_logic;
+ en_m : in std_logic;
+ we_m : in std_logic_vector(3 downto 0);
+ addr_m : in std_logic_vector(10 downto 0);
+ din_m : in std_logic_vector(31 downto 0);
+ dout_m : out std_logic_vector(31 downto 0)
+ );
+ end component;
+
+ component lx_adc_if is
+ generic
+ (
+ adc_res : positive := 18;
+ conv_cycles : integer := 85
+ );
+ port
+ (
+ clk_i : in std_logic;
+ rst_i : in std_logic;
+ conv_start : in std_logic;
+
+ sck_o : out std_logic;
+ cnv_o : out std_logic;
+ data_o : out std_logic_vector((adc_res-1) downto 0);
+ drdy_o : out std_logic;
+
+ sck_i : in std_logic;
+ SDI : in std_logic
+ );
+ end component;
+
-- D sampler (filtered, 2 cycles)
component dff2
port
--
init : in std_logic;
-- signal connected to external JK FF
- event_jk_j : out std_logic
+ event_jk_j : out std_logic;
+ -- signals to image sensor
+ phi1 : out std_logic;
+ phi2 : out std_logic;
+ phi_rst : out std_logic;
+ LED_1 : out std_logic;
+ sck_o : out std_logic;
+ cnv_o : out std_logic;
+ phist : out std_logic;
+ sck_i : in std_logic;
+ SDI : in std_logic
+
);
end lx_dad_top;
-- Measurement (Master)
signal meas_out_s : std_logic_vector(31 downto 0);
signal meas_ce_s : std_logic;
+ -- Sensor timing
+ signal sensor_ce_s : std_logic;
+ signal sensor_out_s : std_logic_vector(31 downto 0);
+ -- sensor memory if
+ signal sens_mem_ce_s : std_logic;
+ signal sens_mem_out_s : std_logic_vector(31 downto 0);
+
+ signal sens_adr_s : std_logic_vector(10 downto 0);
+ signal sens_data_s : std_logic_vector(31 downto 0);
+ signal sens_i_bls_s : std_logic_vector(3 downto 0);
+ signal sens_mem_int_ce_s : std_logic;
+
-- Signals for external bus transmission
signal data_i_s : std_logic_vector(31 downto 0);
signal data_o_s : std_logic_vector(31 downto 0);
-- Signals for internal transaction
signal last_address_s : std_logic_vector(15 downto 0);
- signal next_last_address_s : std_logic_vector(15 downto 0);
- signal next_address_hold_s : std_logic;
+ signal next_last_address_s : std_logic_vector(15 downto 0);
+ signal next_address_hold_s : std_logic;
signal address_hold_s : std_logic;
signal last_rd_s : std_logic;
signal next_last_rd_s : std_logic;
-- additional externally connected signals goes there
);
+
+--Sensor clock generator
+mytest: clockgen
+ port map
+ (
+ clk_i => clk_50m,
+ reset_i => reset_s,
+ sck_i => sck_i,
+ SDI => SDI,
+ phi_st => phist,
+ phi_1 => phi1,
+ phi_2 => phi2,
+ ph_rst => phi_rst,
+ LED => LED_1,
+ sck_o => sck_o,
+ cnv_o => cnv_o,
+ mem_o => sens_data_s,
+ addr_o => sens_adr_s,
+ bls_o => sens_i_bls_s,
+ ce_o => sens_mem_int_ce_s,
+ addr_i => address_f_s(1 downto 0),
+ data_i => data_i_s,
+ ce_i => sensor_ce_s,
+ bls_i => i_bls_s,
+ data_o => sensor_out_s
+
+ );
+
+--sensor memory connection
+memory_bus_sensormem: bus_sensor
+ port map
+ (
+ clk_i => clk_50m,
+ ce_i => sens_mem_ce_s,
+ reset_i => reset_s,
+ bls_i => i_bls_s,
+ address_i => address_f_s(10 downto 0),
+ data_i => data_i_s,
+ data_o => sens_mem_out_s,
+ ce_a_i => sens_mem_int_ce_s,
+ adr_a_i => sens_adr_s,
+ bls_a_i => sens_i_bls_s,
+ dat_a_i => sens_data_s
+ );
+
-- Measurement
memory_bus_measurement: bus_measurement
port map
-- Do the actual wiring here
memory_bus_wiring:
- process(cs0_xc_f_s, i_bls_s, address_f_s, example_out_s, meas_out_s, i_rd_s, last_i_rd_s)
+ process(cs0_xc_f_s, i_bls_s, address_f_s, example_out_s, meas_out_s, sensor_out_s, sens_mem_out_s, i_rd_s, last_i_rd_s)
begin
-- Inactive by default
example_ce_s <= '0';
meas_ce_s <= '0';
+ sensor_ce_s <= '0';
+ sens_mem_ce_s <= '0';
data_o_s <= (others => '0');
if i_rd_s = '1' or i_bls_s /= "0000" then
-- Each address is seen as 32-bit entry now
-- 0x0000 - 0x0FFF: Example memory
+ -- 0x1000 - 0x1003: Sensor timing
-- 0x1FFC - 0x1FFF: Measurement
- -- 0x2000 - 0x8FFF: Free space
+ -- 0x2000 - 0x3FFF: sensor memory
+ -- 0x4000 - 0x8FFF: Free space
if address_f_s < "0001000000000000" then -- Tumbl
example_ce_s <= '1';
+ elsif address_f_s(15 downto 2) = "00010000000000" then -- Sensor timing
+ sensor_ce_s <= '1';
elsif address_f_s(15 downto 2) = "00011111111111" then -- Measurement
meas_ce_s <= '1';
+ elsif address_f_s > "0001111111111111" and address_f_s < "0100000000000000" then -- sensor data
+ sens_mem_ce_s <= '1';
end if;
end if;
data_o_s <= example_out_s;
elsif address_f_s(15 downto 2) = "00011111111111" then -- Measurement
data_o_s <= meas_out_s;
+ elsif address_f_s(15 downto 2) = "00010000000000" then -- Sensor timing
+ data_o_s <= sensor_out_s;
+ elsif address_f_s > "0000111111111111" and address_f_s < "0100000000000000" then -- sensor data
+ data_o_s <= sens_mem_out_s;
end if;
end if;
projects / fpga / lx-cpu1 / lx-dad.git / commitdiff