hw/lx_dad_top.vhd

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.std_logic_arith.all;
   4 use ieee.std_logic_unsigned.all;
   5 use ieee.numeric_std.all;
   6
   7 library unisim;
   8 use unisim.vcomponents.all;
   9
  10 use work.lx_dad_pkg.all;
  11
  12 -- lx_dad_top - wires the modules with the outside world
  13
  14 -- ======================================================
  15 --  MASTER CPU EXTERNAL MEMORY BUS
  16 -- ======================================================
  17 --
  18 -- Master cpu memory bus has the following wires:
  19 --
  20 -- - address[15..0]          The address, used to mark chip enable
  21 -- - data_in[31..0]          The data coming to bus
  22 -- - data_out[31..0]         The data coming from bus, multiplexed
  23 -- - bls[3..0]               Write enable for respective bytes
  24
  25 entity lx_dad_top is
  26         port
  27         (
  28                 -- External
  29                 --clk_cpu     : in std_logic;
  30                 clk_50m     : in std_logic;
  31                 --
  32                 cs0_xc      : in std_logic;
  33                 --
  34                 rd          : in std_logic;
  35                 bls         : in std_logic_vector(3 downto 0);
  36                 address     : in std_logic_vector(15 downto 0);
  37                 data        : inout std_logic_vector(31 downto 0);
  38                 --
  39                 init        : in std_logic;
  40                 -- signal connected to external JK FF
  41                 event_jk_j  : out std_logic
  42         );
  43 end lx_dad_top;
  44
  45 architecture Behavioral of lx_dad_top is
  46
  47         -- Reset signal
  48         signal reset_s                  : std_logic;
  49         signal init_s                   : std_logic;
  50         -- Peripherals on the memory buses
  51         -- Example memory
  52         signal example_out_s            : std_logic_vector(31 downto 0);
  53         signal example_ce_s             : std_logic;
  54         -- Measurement (Master)
  55         signal meas_out_s               : std_logic_vector(31 downto 0);
  56         signal meas_ce_s                : std_logic;
  57         -- Signals for external bus transmission
  58         signal data_i_s                 : std_logic_vector(31 downto 0);
  59         signal data_o_s                 : std_logic_vector(31 downto 0);
  60         -- Signals for internal transaction
  61         signal last_address_s           : std_logic_vector(15 downto 0);
  62         signal next_last_address_s      : std_logic_vector(15 downto 0);
  63         signal next_address_hold_s      : std_logic;
  64         signal address_hold_s           : std_logic;
  65         signal last_rd_s                : std_logic;
  66         signal next_last_rd_s           : std_logic;
  67         signal last_bls_s               : std_logic_vector(3 downto 0); -- prev bls_f_s (active 1)
  68         signal next_last_bls_s          : std_logic_vector(3 downto 0);
  69
  70         -- Reading logic for Master CPU:
  71         -- Broadcast rd only till ta (transaction acknowledge)
  72         -- is received, then latch the data till the state of
  73         -- rd or address changes
  74         --
  75         -- Data latching is synchronous - it's purpose is to
  76         -- provide stable data for CPU on the bus
  77         signal cs0_xc_f_s          : std_logic;
  78         signal rd_f_s              : std_logic; -- Filtered RD
  79         signal i_rd_s              : std_logic; -- Internal bus RD (active 1)
  80         -- signal next_i_rd_s         : std_logic;
  81         signal last_i_rd_s         : std_logic; -- Delayed RD bus, used for latching
  82         signal next_last_i_rd_s    : std_logic;
  83         signal i_rd_cycle2_s       : std_logic; -- Some internal subsystems provide
  84         signal next_i_rd_cycle2_s  : std_logic; -- data only after 2 cycles
  85         --
  86         signal address_f_s         : std_logic_vector(15 downto 0); -- Filtered address
  87         --
  88         signal data_f_s            : std_logic_vector(31 downto 0); -- Filterred input data
  89         --
  90         signal data_read_s         : std_logic_vector(31 downto 0); -- Latched read data
  91         signal next_data_read_s    : std_logic_vector(31 downto 0);
  92
  93         -- Writing logic:
  94         signal bls_f_s             : std_logic_vector(3 downto 0); -- Filtered BLS (active 1)
  95         signal i_bls_s             : std_logic_vector(3 downto 0); -- Internal BLS (active 1)
  96         signal next_i_bls_s        : std_logic_vector(3 downto 0);
  97         --
  98         signal data_write_s        : std_logic_vector(31 downto 0); -- Data broadcasted to write
  99         signal next_data_write_s   : std_logic_vector(31 downto 0);
 100
 101         -- signal s0   : std_logic;
 102         -- signal s1   : std_logic;
 103         -- signal s2   : std_logic;
 104
 105         -- XST attributes
 106         attribute REGISTER_DUPLICATION : string;
 107         attribute REGISTER_DUPLICATION of rd : signal is "NO";
 108         attribute REGISTER_DUPLICATION of rd_f_s : signal is "NO";
 109         attribute REGISTER_DUPLICATION of bls : signal is "NO";
 110         attribute REGISTER_DUPLICATION of bls_f_s : signal is "NO";
 111         attribute REGISTER_DUPLICATION of address : signal is "NO";
 112         attribute REGISTER_DUPLICATION of address_f_s : signal is "NO";
 113         attribute REGISTER_DUPLICATION of cs0_xc : signal is "NO";
 114         attribute REGISTER_DUPLICATION of cs0_xc_f_s : signal is "NO";
 115
 116 begin
 117
 118 -- Example connection
 119 memory_bus_example: bus_example
 120         port map
 121         (
 122                 clk_i          => clk_50m,
 123                 reset_i        => reset_s,
 124                 ce_i           => example_ce_s,
 125                 bls_i          => i_bls_s,
 126                 address_i      => address_f_s(11 downto 0),
 127                 data_i         => data_i_s,
 128                 data_o         => example_out_s
 129                 --
 130                 --
 131                 -- additional externally connected signals goes there
 132         );
 133
 134 -- Measurement
 135 memory_bus_measurement: bus_measurement
 136         port map
 137         (
 138                 clk_i     => clk_50m,
 139                 reset_i   => reset_s,
 140                 ce_i      => meas_ce_s,
 141                 address_i => address_f_s(1 downto 0),
 142                 bls_i     => i_bls_s,
 143                 data_i    => data_i_s,
 144                 data_o    => meas_out_s
 145         );
 146
 147 -- Reset
 148 dff_reset: dff2
 149         port map
 150         (
 151                 clk_i   => clk_50m,
 152                 d_i     => init_s,
 153                 q_o     => reset_s
 154         );
 155
 156         -- Reset
 157         init_s          <= not init;
 158
 159         -- Signalling
 160         data_i_s        <= data_write_s;
 161
 162
 163         event_jk_j <= '0';
 164
 165 -- Bus update
 166 memory_bus_logic:
 167         process(cs0_xc_f_s, rd_f_s, last_rd_s, i_rd_cycle2_s, last_i_rd_s,
 168                 bls_f_s, last_bls_s, data_f_s, data_write_s,
 169                 data_o_s, data_read_s, last_address_s, address_f_s)
 170         begin
 171                 -- Defaults
 172                 next_i_rd_cycle2_s <= '0';
 173                 next_address_hold_s <= '0';
 174
 175                 -- Check if we have chip select
 176                 if cs0_xc_f_s = '1' then
 177
 178                         -- Reading
 179                         if rd_f_s = '1' then
 180                                 -- Internal read
 181                                 if last_rd_s = '0' or (last_address_s /= address_f_s) then
 182                                         i_rd_s <= '1';
 183                                         next_i_rd_cycle2_s <= '1';
 184                                         next_last_i_rd_s  <= '1';
 185                                 elsif i_rd_cycle2_s = '1' then    -- FIXME it seems that some internal
 186                                         i_rd_s <= '1';            -- peripherals demands 2 cycles to read
 187                                         next_last_i_rd_s  <= '1';
 188                                 else
 189                                         i_rd_s            <= '0';
 190                                         next_last_i_rd_s  <= '0';
 191                                 end if;
 192
 193                                 if last_i_rd_s = '1' then
 194                                         -- Latch data we just read - they are valid in this cycle
 195                                         next_data_read_s <= data_o_s;
 196                                 else
 197                                         next_data_read_s <= data_read_s;
 198                                 end if;
 199                         else
 200                         --      -- Not reading, anything goes
 201                         --      data_read_s       <= (others => 'X');
 202                                 next_data_read_s  <= data_read_s;
 203                                 i_rd_s            <= '0';
 204                                 next_last_i_rd_s  <= '0';
 205                         end if;
 206
 207                         next_last_rd_s            <= rd_f_s;
 208
 209                         -- Data for write are captured only when BLS signals are stable
 210                         if bls_f_s /= "0000" then
 211                                 next_data_write_s <= data_f_s;
 212                                 next_address_hold_s <= '1';
 213                         else
 214                                 next_data_write_s <= data_write_s;
 215                         end if;
 216
 217                         if (bls_f_s /= "0000") or (rd_f_s = '1') then
 218                                 next_last_address_s <= address_f_s;
 219                         else
 220                                 next_last_address_s <= last_address_s;
 221                         end if;
 222                 else
 223                         next_last_rd_s <= '0';
 224                         i_rd_s <= '0';
 225                         next_last_i_rd_s <= '0';
 226
 227                         next_i_bls_s <= "0000";
 228                         next_data_write_s <= data_write_s;
 229                         next_data_read_s  <= data_read_s;
 230                         next_last_address_s <= last_address_s;
 231                 end if;
 232
 233                 -- Data for write are captured at/before BLS signals are negated
 234                 -- and actual write cycle takes place exacly after BLS negation
 235                 if ((last_bls_s and not bls_f_s) /= "0000") or
 236                     ((last_bls_s /= "0000") and (cs0_xc_f_s = '0')) then
 237                         next_i_bls_s <= last_bls_s;
 238                         next_last_bls_s   <= "0000";
 239                         next_address_hold_s <= '1';
 240                 else
 241                         next_i_bls_s <= "0000";
 242                         if cs0_xc_f_s = '1' then
 243                                 next_last_bls_s <= bls_f_s;
 244                         else
 245                                 next_last_bls_s <= "0000" ;
 246                         end if;
 247                 end if;
 248
 249         end process;
 250
 251 -- Bus update
 252 memory_bus_update:
 253         process
 254         begin
 255
 256                 wait until clk_50m = '1' and clk_50m'event;
 257
 258                 address_hold_s <= next_address_hold_s;
 259
 260                 -- Synchronized external signals with main clock domain
 261                 cs0_xc_f_s     <= not cs0_xc;
 262                 bls_f_s        <= not bls;
 263                 rd_f_s         <= not rd;
 264                 data_f_s       <= data;
 265                 if address_hold_s = '0' then
 266                         address_f_s <= address;
 267                 else
 268                         address_f_s <= next_last_address_s;
 269                 end if;
 270
 271                 -- Synchronoust state andvance to next period
 272                 last_bls_s     <= next_last_bls_s;
 273                 last_rd_s      <= next_last_rd_s;
 274                 i_bls_s        <= next_i_bls_s;
 275                 -- i_rd_s         <= next_i_rd_s;
 276                 i_rd_cycle2_s  <= next_i_rd_cycle2_s;
 277                 last_i_rd_s    <= next_last_i_rd_s;
 278                 data_write_s   <= next_data_write_s;
 279                 last_address_s <= next_last_address_s;
 280                 data_read_s    <= next_data_read_s;
 281
 282         end process;
 283
 284 -- Do the actual wiring here
 285 memory_bus_wiring:
 286         process(cs0_xc_f_s, i_bls_s, address_f_s, example_out_s, meas_out_s)
 287         begin
 288
 289                 -- Inactive by default
 290                 example_ce_s           <= '0';
 291                 meas_ce_s              <= '0';
 292                 data_o_s               <= (others => '0');
 293
 294                 if cs0_xc_f_s = '1' or i_bls_s /= "0000" then
 295
 296                         -- Memory Map (16-bit address @ 32-bit each)
 297
 298                         -- Each address is seen as 32-bit entry now
 299                         -- 0x0000 - 0x0FFF: Example memory
 300                         -- 0x1FFC - 0x1FFF: Measurement
 301                         -- 0x2000 - 0x8FFF: Free space
 302
 303                         if address_f_s < "0001000000000000" then                  -- Tumbl
 304                                 example_ce_s           <= '1';
 305                                 data_o_s               <= example_out_s;
 306                         elsif address_f_s(15 downto 2) = "00011111111111" then    -- Measurement
 307                                 meas_ce_s              <= '1';
 308                                 data_o_s               <= meas_out_s;
 309                         end if;
 310
 311                 end if;
 312
 313         end process;
 314
 315 -- If RD and BLS is not high, we must keep DATA at high impedance
 316 -- or the FPGA collides with SDRAM (damaging each other)
 317 memory_bus_out:
 318         process(cs0_xc, rd, data_read_s)
 319         begin
 320
 321                 -- CS0 / RD / BLS are active LOW
 322                 if cs0_xc = '0' and rd = '0' then
 323                         -- Don't risk flipping (between data_o_s and latched data_read_s, it's better to wait)
 324                         -- Maybe check this later.
 325                         -- if last_i_rd_s = '1' then
 326                         --   data <= data_o_s;
 327                         -- else
 328                         data <= data_read_s;
 329                         -- end if;
 330                 else
 331                         -- IMPORTANT!!!
 332                         data <= (others => 'Z');
 333                 end if;
 334
 335         end process;
 336
 337 end Behavioral;
 338