]> rtime.felk.cvut.cz Git - fpga/lx-cpu1/lx-dad.git/commit
Re-implemented ADC start logic to enable multiple samples per pixel mode.
authorPavel Pisa <pisa@cmp.felk.cvut.cz>
Tue, 3 Nov 2015 19:59:45 +0000 (20:59 +0100)
committerPavel Pisa <pisa@cmp.felk.cvut.cz>
Tue, 3 Nov 2015 19:59:45 +0000 (20:59 +0100)
commit2f235526493db0e0405d16e74c328a84d229e9aa
tree99b615beb9bd4ca7794e40970f60501e743bcaff
parent4de2acbdb1328172d19ae102d98b44820902015f
Re-implemented ADC start logic to enable multiple samples per pixel mode.

Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
hw/clockgen.vhd
hw/lx_adc_if.vhd
hw/lx_dad_top.vhd