]> rtime.felk.cvut.cz Git - fpga/lx-cpu1/lx-dad.git/shortlog
fpga/lx-cpu1/lx-dad.git
2017-09-21 Pavel PisaTestbed updated -g option to work with latest GHDL. master
2015-11-03 Pavel PisaGraph plot added into Python test software.
2015-11-03 Pavel PisaImplemented multiple samples per pixel and times tuning...
2015-11-03 Pavel PisaSetup of viewed signals for GTK Wave updated.
2015-11-03 Pavel PisaTestbed changed to work when samples save is controlled...
2015-11-03 Pavel PisaRe-implemented ADC start logic to enable multiple sampl...
2015-11-03 Pavel PisaUpdate DAD hardware testbed.
2015-10-27 Pavel PisaSimple tool to capture scans written in Python.
2015-10-27 Pavel PisaAdded commands to control echo mode and check commands...
2015-10-27 Pavel PisaClean DAD test code a little to use symbolic names...
2015-10-27 Pavel Pisasysless: update for cmdproc correct return value of...
2015-10-27 Pavel PisaUpdate uLUt and sysless submodules.
2015-07-30 Pavel PisaAdd the second command processor instance for CDC ACM...
2015-07-30 Pavel PisaUSB CDC ACM use maximal packet length - 64 bytes.
2015-07-30 Pavel PisaCompute USB engine event mask by function.
2015-07-30 Pavel PisaUSB CDC ACM send zero length packet if previous one...
2015-07-30 Pavel PisaTest option to use cmdproc IO as POSIX FILE stream.
2015-07-30 Pavel PisaUSB CDC ACM target for command processor implemented.
2015-07-30 Pavel PisauLUt and sysless submodules updated.
2015-05-25 Jan Novotnyall files updated to latest versions
2015-05-20 Jan Novotnyfixed FPGA buggs, added support for single shot measure...
2015-04-30 Jan Novotnyadded custom test to see if memory mapped sensor contro...
2015-04-30 Jan Novotnymodified LED blinking speed to be less distractive
2015-04-30 Jan Novotnymodified project files to support new features
2015-04-30 Jan Novotnyextended memotry for 2 samples of sensor data
2015-04-30 Jan Novotnyadded sensor clock generation files addn ADC readout...
2015-02-15 Pavel PisaInclude simple scripts to build, load and run project...
2015-02-15 Pavel PisaShift some external signals by half of clock cycle...
2015-02-15 Pavel PisaSimplify FPGA design external CPU read logic.
2015-02-15 Pavel PisaGit ignore build outputs.
2015-02-15 Pavel PisaRemove nonstandard ieee.std_logic_arith and ieee.std_lo...
2015-02-15 Pavel PisaInclude testbed for simulation in GHDL.
2015-02-15 Pavel PisaDisable use of unisim library to allow simulation by...
2015-02-15 Pavel PisaInclude example of mapping dualported RAM mapping to...
2015-02-15 Pavel PisaInclude hardware design of FPGA peripherals to external...
2015-02-13 Pavel PisaSwitch LX_DAD default link variant to SDRAM.
2015-02-12 Pavel PisaInclude host tool to send code and FPGA configuration...
2015-02-12 Pavel PisaPrepare build-able skeleton for LX_DAD application.
2015-02-12 Pavel PisaLX_DAD project started.