phi_2 : out std_logic;
phi_st : out std_logic;
ph_rst : out std_logic;
- LED : out std_logic;
+ -- LED : out std_logic;
sck_o : out std_logic;
cnv_o : out std_logic;
-- mem related inputs
- addr_i : in std_logic_vector(1 downto 0);
+ addr_i : in std_logic_vector(3 downto 0);
data_i : in std_logic_vector(31 downto 0);
ce_i : in std_logic;
bls_i : in std_logic_vector(3 downto 0);
--constant CLK_MASTER_FREQ: unsigned := 50000000;
- signal cntra : unsigned(15 downto 0) := (others => '0');
- signal pixel : integer range 0 to 1024;
+ signal cntra : unsigned(31 downto 0) := (others => '0');
+ signal pixel : integer range 0 to 2047;
+
+ signal cntrb : unsigned(31 downto 0) := (others => '0');
signal bank : std_logic;
signal conv_start : std_logic;
signal adc_data_i : std_logic_vector(17 downto 0);
signal adc_drdy_i : std_logic;
+ signal run_single : std_logic;
+ signal run_single_last : std_logic;
+ signal run_single_i : std_logic;
+ signal finished : std_logic:='0';
+ signal finished_i : std_logic:='0';
+ signal stability_m : std_logic;
- type states_i is (i0, i1, i2, i3, i4, i5, i6, i7, i8);
+ type states_i is (i0, i1, i2, i3, i4, i5, i6, i7, i8, iddle);
signal state_i : states_i;
+
+ type meas_states is (normal, multi_per_pixel, leakage);
+ signal state_meas : meas_states;
- signal t1 : unsigned(15 downto 0);
- signal t2 : unsigned(15 downto 0);
- signal t3 : unsigned(15 downto 0);
- signal t4 : unsigned(15 downto 0);
- signal t5 : unsigned(15 downto 0);
- signal t6 : unsigned(15 downto 0);
- signal t7 : unsigned(15 downto 0);
-
- signal t1_i : std_logic_vector(15 downto 0);
- signal t2_i : std_logic_vector(15 downto 0);
- signal t3_i : std_logic_vector(15 downto 0);
- signal t4_i : std_logic_vector(15 downto 0);
- signal t5_i : std_logic_vector(15 downto 0);
- signal t6_i : std_logic_vector(15 downto 0);
- signal t7_i : std_logic_vector(15 downto 0);
+ signal t1 : unsigned(31 downto 0);
+ signal t2 : unsigned(31 downto 0);
+ signal t3 : unsigned(31 downto 0);
+ signal t4 : unsigned(31 downto 0);
+ signal t5 : unsigned(31 downto 0);
+ signal t6 : unsigned(31 downto 0);
+ signal t7 : unsigned(31 downto 0);
+ signal t8 : unsigned(31 downto 0);
+ signal t9 : unsigned(31 downto 0) ;
signal alive_cntr : integer range 0 to 24999999:=0;
SDI => sdi
);
- adc_read : process
- begin
- wait until clk_i'event and clk_i = '1';
- if reset_i = '1' then
- bank <= '0';
- end if;
- ce_o <= '0';
- bls_o <= "0000";
- if adc_drdy_i = '1' then
- mem_o <= std_logic_vector(resize(unsigned(adc_data_i), mem_o'length));
- addr_o <= bank & std_logic_vector(to_unsigned((pixel-1),10));
- bls_o <= "1111";
- ce_o <= '1';
- if pixel = 1024 then
- bank <= not bank;
- end if;
- end if;
- end process;
+ -- adc_read : process(reset_i,clk_i)
+ -- begin
+ -- if reset_i = '1' then
+ -- elsif rising_edge(clk_i) then
+ -- if adc_drdy_i = '1' and pixel < 1025 then
+ --mem_o <= std_logic_vector(resize(unsigned(adc_data_i), mem_o'length));
+ -- mem_o <= std_logic_vector(to_unsigned((pixel),32));
+ -- addr_o <= bank & std_logic_vector(to_unsigned((pixel),10));
+ -- bls_o <= "1111";
+ -- ce_o <= '1';
+ -- end if;
+ -- end if;
+ -- end process;
- interf : process
+ interf : process(reset_i,clk_i)
begin
- wait until clk_i'event and clk_i = '1';
if reset_i = '1' then -- set default timing
- t1 <= "0000000000000010"; --2
- t2 <= "0000000000001001"; --9
- t3 <= "0000010001111101"; --1149
- t4 <= "0000000000001110"; --14
- t5 <= "0000000000000010"; --2
- t6 <= "0000001001010111"; --599
- t7 <= "0000001010010010"; --658
- t1_i <= "0000000000000010"; --2
- t2_i <= "0000000000001001"; --9
- t3_i <= "0000010001111101"; --1149
- t4_i <= "0000000000001110"; --14
- t5_i <= "0000000000000010"; --2
- t6_i <= "0000001001010111"; --599
- t7_i <= "0000001010010010"; --658
+ t1 <= "00000000000000000000000000000110"; --6
+ t2 <= "00000000000000000000001111101000"; --9
+ t3 <= "00000000000000000000010001111101"; --1149
+ t4 <= "00000000000000000000001111101000"; --14
+ t5 <= "00000000000000000000000000000110"; --6
+ t6 <= "00000000000000000000001001010111"; --599
+ t7 <= "00000000000000000000001010010010"; --658
+ t8 <= "00000000000000000001001100010000"; --4880
+ t9 <= "00000000000000000000000111110011";
data_o <= (others => '0');
+ run_single <= '0';
run_readout <= '0';
- elsif ce_i = '1' and bls_i /= "0000" then
- if addr_i = "00" then
- t1_i <= data_i(15 downto 0);
- t2_i <= data_i(31 downto 16);
- elsif addr_i = "01" then
- t3_i <= data_i(15 downto 0);
- t4_i <= data_i(31 downto 16);
- elsif addr_i = "10" then
- t5_i <= data_i(15 downto 0);
- t6_i <= data_i(31 downto 16);
- elsif addr_i = "11" then
- run_readout <= data_i(30); --start/stop the readout
- if data_i(31) = '1' then --update timing constnts
- t1 <= unsigned(t1_i);
- t2 <= unsigned(t2_i);
- t3 <= unsigned(t3_i);
- t4 <= unsigned(t4_i);
- t5 <= unsigned(t5_i);
- t6 <= unsigned(t6_i);
- t7 <= unsigned(t7_i);
- else
- t7_i <= data_i(15 downto 0);
+ elsif rising_edge(clk_i) then
+ run_single <= '0';
+ if finished = '1' then
+ run_readout <= '0';
+ finished_i <= '1';
+ end if;
+ if ce_i = '1' and bls_i /= "0000" then
+ if addr_i = "0000" then
+ run_readout <= data_i(0); --start/stop the readout
+ if data_i(1) = '1' then
+ run_readout <= '1';
+ run_single <= '1';
+ end if;
+ if data_i(3) = '1' then
+ state_meas <= normal;
+ elsif data_i(4) = '1' then
+ state_meas <= leakage;
+ end if;
+ elsif addr_i = "0001" then
+ t1 <= unsigned(data_i);
+ elsif addr_i = "0010" then
+ t2 <= unsigned(data_i);
+ elsif addr_i = "0011" then
+ t3 <= unsigned(data_i);
+ elsif addr_i = "0100" then
+ t4 <= unsigned(data_i);
+ elsif addr_i = "0101" then
+ t5 <= unsigned(data_i);
+ elsif addr_i = "0110" then
+ t6 <= unsigned(data_i);
+ elsif addr_i <= "0111" then
+ t7 <= unsigned(data_i);
+ elsif addr_i <= "1000" then
+ t8 <= unsigned(data_i);
+ elsif addr_i <= "1001" then
+ t9 <= unsigned(data_i);
end if;
end if;
+ if ce_i = '1' then
+ if addr_i = "0000" then
+ data_o <= (others => '0');
+ data_o(2) <= not bank;
+ data_o(6) <= finished_i;
+ data_o(0) <= run_readout;
+ if state_meas = leakage then
+ data_o(4) <= '1';
+ elsif state_meas = normal then
+ data_o(3) <= '1';
+ elsif state_meas = multi_per_pixel then
+ data_o(5) <= '1';
+ end if;
+ finished_i <= '0';
+ elsif addr_i = "0001" then
+ data_o <= std_logic_vector(t1);
+ elsif addr_i = "0010" then
+ data_o <= std_logic_vector(t2);
+ elsif addr_i = "0011" then
+ data_o <= std_logic_vector(t3);
+ elsif addr_i = "0100" then
+ data_o <= std_logic_vector(t4);
+ elsif addr_i = "0101" then
+ data_o <= std_logic_vector(t5);
+ elsif addr_i = "0110" then
+ data_o <= std_logic_vector(t6);
+ elsif addr_i = "0111" then
+ data_o <= std_logic_vector(t7);
+ elsif addr_i = "1000" then
+ data_o <= std_logic_vector(t8);
+ elsif addr_i = "1001" then
+ data_o <= std_logic_vector(t9);
+ end if;
+ end if;
end if;
- if addr_i = "11" then
- data_o <= (others => '0');
- data_o(0) <= not bank;
- end if;
end process;
cntra <= (others => '0');
pixel <= 0;
phi_st <= '0';
+ bank <= '0';
+ ce_o <= '0';
+ bls_o <= "0000";
elsif rising_edge(clk_i) then
+ ce_o <= '0';
+ bls_o <= "0000";
conv_start <= '0';
+ finished <= '0';
+ if run_single = '1' then
+ run_single_i <= '1';
+ end if;
+ if run_readout = '1' then
+ cntrb <= cntrb + 1;
+ else
+ cntrb <= (others => '0');
+ end if;
-- if start_readout = '1' then
-- pixel <= 0;
-- end if;
if cntra = 0 then
- case state_i is
- when i0 =>
- state_i <= i1;
- cntra<=t1;
- phi_2 <= '0';
- when i1 =>
- state_i <= i2;
- phi_1 <= '1';
- cntra<=t2;
- when i2 =>
- state_i <= i3;
- ph_rst <= '1';
- cntra<=t3;
- when i3 =>
- ph_rst <= '0';
- phi_st <= '0';
- state_i <= i4;
- cntra<=t4;
- when i4 =>
- phi_1 <= '0';
- state_i <= i5;
- cntra<=t5;
- when i5 =>
- phi_2 <= '1';
- state_i <= i6;
- cntra <= t6;
- when i6 =>
- state_i <= i0;
- conv_start <= '1';
- -- start the readout from adc
- cntra <= t7;
- if run_readout = '1' and pixel = 0 then
- phi_st <= '1';
- end if;
- if pixel = 1024 then
+ case state_meas is
+ when leakage =>
+ case state_i is
+ when i0 =>
+ if pixel > 0 then
+ mem_o <= "00000000000000"&adc_data_i;
+ --mem_o <= std_logic_vector(to_unsigned((pixel-1),32));
+ addr_o <= bank & std_logic_vector(to_unsigned((pixel-1),10));
+ bls_o <= "1111";
+ ce_o <= '1';
+ end if;
+ if pixel > 1023 then
+ bank <= not bank;
+ state_i <= iddle;
+ if run_single_i = '1' and run_single_last = '0' then
+ run_single_last <= '1';
+ end if;
+ if run_single_i = '1' and run_single_last = '1' then
+ run_single_i <= '0';
+ run_single_last <= '0';
+ finished <= '1';
+ end if;
+ end if;
+ pixel <= pixel +1;
+ conv_start <= '1';
+ cntra <= t9;
+ when others =>
pixel <= 0;
- else
+ cntra <= (others => '0');
+ ph_rst <= '0';
+ if cntrb > t8 then
+ state_i <= i0;
+ cntra <= t9;
+ cntrb <= (others => '0');
+ ph_rst <= '1';
+ end if;
+ end case;
+ when normal =>
+ case state_i is
+ when i0 =>
+ if pixel > 0 and pixel < 1025 then
+ mem_o <= "00000000000000"&adc_data_i;
+ --mem_o <= std_logic_vector(to_unsigned((pixel-1),32));
+ addr_o <= bank & std_logic_vector(to_unsigned((pixel-1),10));
+ bls_o <= "1111";
+ ce_o <= '1';
+ end if;
+ state_i <= i1;
+ cntra<=t1;
+ phi_2 <= '0';
+ when i1 =>
+ state_i <= i2;
+ phi_1 <= '1';
+ cntra<=t2;
+ when i2 =>
+ state_i <= i3;
+ ph_rst <= '0';
+ cntra<=t3;
+ when i3 =>
+ ph_rst <= '1';
+ phi_st <= '0';
+ state_i <= i4;
+ cntra<=t4;
+ when i4 =>
+ phi_1 <= '0';
+ if pixel = 1026 then
+ bank <= not bank;
+ state_i <= iddle;
+ cntra <= (others => '0');
+ if run_single_i = '1' and run_single_last = '0' then
+ run_single_last <= '1';
+ end if;
+ if run_single_i = '1' and run_single_last = '1' then
+ run_single_i <= '0';
+ run_single_last <= '0';
+ finished <= '1';
+ end if;
+ else
+ state_i <= i5;
+ cntra<=t5;
+ end if;
+ when i5 =>
+ phi_2 <= '1';
+ state_i <= i6;
+ cntra <= t6;
+ when i6 =>
+ state_i <= i0;
+ -- start the readout from adc
+ cntra <= t7;
+ if run_readout = '1' then
+ if pixel > 0 then
+ conv_start <= '1';
+ end if;
+ if pixel = 0 then
+ phi_st <= '1';
+ end if;
+ end if;
pixel <= pixel + 1;
- end if;
+ when others =>
+ if cntrb > t8 then
+ cntrb <= (others => '0');
+ state_i <= i1;
+ end if;
+ pixel <= 0;
+ phi_1 <= '0';
+ phi_2 <= '0';
+ ph_rst <= '0';
+ cntra <= (others => '0');
+ end case;
when others =>
- --set 0 to phi1
- phi_1 <= '1';
- phi_2 <= '0';
- state_i <= i0;
- cntra <= (others => '0');
end case;
- --else
- -- cntrb <= cntrb + 1;
- --end if;
else
cntra <= cntra - 1;
end if;
begin
if reset_i = '1' then
alive_cntr <= 0;
- LED <= '1';
+ --LED <= '1';
LED_latch<= '1';
elsif rising_edge(clk_i) then
alive_cntr<=alive_cntr+1;
if alive_cntr = 24999999 then
LED_latch <= not LED_latch;
- LED <= LED_latch;
+ -- LED <= LED_latch;
alive_cntr<=0;
end if;
end if;
cnv_o : out std_logic;\r
data_o : out std_logic_vector((adc_res-1) downto 0);\r
drdy_o : out std_logic;\r
- \r
+ \r
sck_i : in std_logic;\r
SDI : in std_logic\r
);\r
signal ckout : std_logic;\r
--signal active_bit_t integer range 0 to (adc_res-1);\r
signal active_bit_r : integer range 0 to (adc_res-1);\r
- \r
+ \r
signal conv_cnter : integer range 0 to conv_cycles;\r
\r
type states_i is (conv, reading, iddle);\r
\r
signal drdy_i : std_logic;\r
signal drdy_i_last : std_logic;\r
+ signal drdy_i_last_last : std_logic;\r
+ \r
+ attribute REGISTER_DUPLICATION : string;\r
+ attribute REGISTER_DUPLICATION of received : signal is "NO";\r
+ attribute REGISTER_DUPLICATION of drdy_i : signal is "NO";\r
+ attribute REGISTER_DUPLICATION of drdy_i_last : signal is "NO";\r
+ attribute REGISTER_DUPLICATION of drdy_i_last_last : signal is "NO";\r
\r
begin\r
\r
- data_sync: process\r
+ data_sync: process(clk_i,rst_i)\r
begin\r
- wait until clk_i'event and clk_i = '1';\r
- drdy_i_last <= drdy_i;\r
- drdy_o <= '0';\r
- if drdy_i = '1' and drdy_i_last = '0' then\r
- data_o <= received;\r
- drdy_o <= '1';\r
+ if rst_i = '1' then\r
+ drdy_o <= '0';\r
+ drdy_i_last <= '0';\r
+ drdy_i_last_last <= '0';\r
+ data_o <= (others => '0');\r
+ elsif rising_edge(clk_i) then\r
+ drdy_i_last_last <= drdy_i_last;\r
+ drdy_i_last <= drdy_i;\r
+ drdy_o <= '0';\r
+ if drdy_i = '1' and drdy_i_last = '1' and drdy_i_last_last = '0' then\r
+ data_o <= received;\r
+ drdy_o <= '1';\r
+ end if;\r
end if;\r
end process;\r
\r
- adc_readout: process(sck_i, rst_i)\r
+ adc_readout: process(sck_i,rst_i)\r
begin\r
- if rst_i = '1' then\r
- received <= (others => '0');\r
+ if rst_i= '1' then\r
active_bit_r <= 17;\r
drdy_i <= '0';\r
- elsif falling_edge(sck_i) then\r
+ received <= (others => '0');\r
+ elsif rising_edge(sck_i) then\r
if convert = '1' and active_bit_r = 17 then\r
received(active_bit_r) <= SDI;\r
active_bit_r <= 16;\r
if active_bit_r = 0 then\r
drdy_i <= '1';\r
active_bit_r <= 17;\r
+ else\r
+ active_bit_r <= active_bit_r - 1;\r
end if;\r
received(active_bit_r) <= SDI;\r
end if;\r
conv_cnter <= conv_cnter + 1;\r
end if;\r
when reading =>\r
- if conv_cnter < (adc_res-1) then\r
+ if conv_cnter < (adc_res) then\r
if ckout = '1' then\r
conv_cnter <= conv_cnter + 1;\r
end if;\r
int cmd_do_mujtest(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
{
- volatile uint32_t *testaddr = (volatile uint32_t *)0x8000400C;
- int p=(int) strtol(param[1], (char **)NULL, 10);
- printf("jen muj testovaci vypis %X\n", p);
- *testaddr = p;
+ volatile uint32_t *testaddr = (volatile uint32_t *)0x80004000;
+ int p;
+ p=*testaddr++;
+ printf("read %d\n", p);
+ p=*testaddr++;
+ printf("read %d\n", p);
+ p=*testaddr++;
+ printf("read %d\n", p);
+ p=*testaddr++;
+ printf("read %d\n", p);
+ p=*testaddr++;
+ printf("read %d\n", p);
+ p=*testaddr++;
+ printf("read %d\n", p);
+ p=*testaddr++;
+ printf("read %d\n", p);
+ p=*testaddr++;
+ printf("read %d\n", p);
+ p=*testaddr++;
+ printf("read %d\n", p);
+
+}
+
+int cmd_do_zmer(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
+{
+ volatile uint32_t *testaddr = (volatile uint32_t *)0x80004000;
+ int32_t values[2048];
+ uint32_t status, status_old, bank,i;
+ int32_t val;
+ status_old = *testaddr;
+ //while((status_old & (1<<2))==(status & (1<<2))) status=*testaddr;
+ //while (*testaddr &(1<<6));
+ *testaddr = 0xa;
+ while (!(*testaddr & (1<<6))) printf("\ncekam\n");
+ status = *testaddr;
+ testaddr = (volatile uint32_t *)0x80008000;
+ if (status&(1<<2)){
+ // printf("bank1\n");
+ testaddr = (volatile uint32_t *)0x80009000;
+ } else {
+ //printf("bank0\n");
+ }
+ for(i=0;i<1024;i++){
+ // values[i]=*testaddr++;
+ val=*testaddr++;
+ val+=(1<<17);
+ val&=(1<<18)-1;
+ val -= (1<<17);
+ values[i]=val;
+ }
+ if (status&(1<<2)){
+ printf("bank1\n");
+ //testaddr = (volatile uint32_t *)0x80008000;
+ } else {
+ printf("bank0\n");
+ }
+ for (i=0;i<1024;i++){
+ if (i==1024){
+ printf("bank1\n");
+ }
+ printf("%d\n",values[i]);
+
+ }
+ printf("konec\n");
+
+ return 0;
+}
+
+int cmd_do_runnung_meas(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[]){
+ volatile uint32_t *testaddr = (volatile uint32_t *)0x80004000;
+ int32_t values[1024];
+ uint32_t status, status_old, bank,i;
+ int32_t val;
+ status_old = *testaddr;
+ status = *testaddr;
+ while((status_old & (1<<2))==(status & (1<<2))) {status=*testaddr; printf("dely %i %i",status_old & (1<<2),status & (1<<2));}
+ if (status&(1<<2)){
+ testaddr = (volatile uint32_t *)0x80009000;
+ } else {
+ testaddr = (volatile uint32_t *)0x80008000;
+ }
+ for(i=0;i<1024;i++){
+ // values[i]=*testaddr++;
+ val=*testaddr++;
+ val = (val>> 17) == 0 ? val : -1 ^ 0x7FFFF | val;
+ values[i]=-1*val;
+ }
+ if (status&(1<<2)){
+ printf("bank1\n");
+ //testaddr = (volatile uint32_t *)0x80008000;
+ } else {
+ printf("bank0\n");
+ }
+ //printf("zacatek\n");
+ for (i=0;i<1024;i++){
+ printf("%d\n",values[i]);
+ }
+ printf("konec\n");
+ return 0;
+}
+
+
+int cmd_do_init(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
+{
+ printf("init!\n");
+ volatile uint32_t *testaddr = (volatile uint32_t *)0x80004000;
+ *testaddr++ = 0x9;
+// *testaddr++;
+ *testaddr++ = 9;
+ *testaddr++ = 399;
+ *testaddr++ = 409;
+ *testaddr++ = 399;
+ *testaddr++ = 9;
+ *testaddr++ = 599;
+ *testaddr++ = 609;
+ //*testaddr++ = 4879;
+ *testaddr++ = 5023999;
+ *testaddr=499;
+
+ printf("OK!\n");
+ return 0;
+}
+
+int cmd_do_send(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
+{
+ char *end;
+ volatile uint32_t *testaddr = (volatile uint32_t *)0x80004000;
+ int read;
+ int p=(int) strtol(param[1], &end, 10);
+ testaddr+=p;
+ p=(int) strtol(end, &end, 10);
+ *testaddr=p;
+ read=*testaddr;
+ printf("sent %d & read %d\n", p, read);
return 0;
}
cmd_des_t const cmd_des_mujtest={0,0,"mujtest","run my simple test", cmd_do_mujtest,{(void*)0}};
+cmd_des_t const cmd_des_zmer={0,0,"zmer","read values from spectrometer (2 readouts)", cmd_do_zmer,{(void*)0x12}};
+
+cmd_des_t const cmd_des_scan={0,0,"scan","read values from spectrometer (2 readouts)", cmd_do_zmer,{(void*)0x10}};
+
+
+cmd_des_t const cmd_des_init={0,0,"init", "inicializacni vypis pro zacatek komunikace", cmd_do_init,{(void*)0}};
+
+cmd_des_t const cmd_des_sendvalue={0,0,"send", "send value to given address", cmd_do_send,{(void*)0}};
+
+cmd_des_t const cmd_des_runnung_meas = {0,0,"run","read values from spectrometer (running)", cmd_do_runnung_meas,{(void*)0x10}};
+
cmd_des_t const *const cmd_appl_tests[]={
&cmd_des_test_memusage,
&cmd_des_test_adc,
&cmd_des_testmpu,
&cmd_des_goaddr,
&cmd_des_mujtest,
+ &cmd_des_zmer,
+ &cmd_des_scan,
+ &cmd_des_init,
+ &cmd_des_sendvalue,
+ & cmd_des_runnung_meas,
NULL
};
projects / fpga / lx-cpu1 / lx-dad.git / commitdiff