--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include "Std_Types.h"\r
+#include "Mcu.h"\r
+#include "Det.h"\r
+#include <assert.h>\r
+#include "cpu.h"\r
+#include <string.h>\r
+#include "Ramlog.h"\r
+#include "system_stm32f10x.h"
+\r
+//#define USE_TRACE 1\r
+//#define USE_DEBUG 1\r
+#include "Trace.h"\r
+\r
+typedef struct {\r
+ uint32 lossOfLockCnt;\r
+ uint32 lossOfClockCnt;\r
+} Mcu_Stats;\r
+\r
+void Mcu_ConfigureFlash(void);\r
+/**\r
+ * Type that holds all global data for Mcu\r
+ */\r
+typedef struct\r
+{\r
+ // Set if Mcu_Init() have been called\r
+ boolean initRun;\r
+\r
+ // Our config\r
+ const Mcu_ConfigType *config;\r
+\r
+ Mcu_ClockType clockSetting;\r
+\r
+ Mcu_Stats stats;\r
+\r
+} Mcu_GlobalType;\r
+\r
+/* Development error macros. */\r
+#if ( MCU_DEV_ERROR_DETECT == STD_ON )\r
+#define VALIDATE(_exp,_api,_err ) \\r
+ if( !(_exp) ) { \\r
+ Det_ReportError(MODULE_ID_MCU,0,_api,_err); \\r
+ return; \\r
+ }\r
+\r
+#define VALIDATE_W_RV(_exp,_api,_err,_rv ) \\r
+ if( !(_exp) ) { \\r
+ Det_ReportError(MODULE_ID_MCU,0,_api,_err); \\r
+ return (_rv); \\r
+ }\r
+#else\r
+#define VALIDATE(_exp,_api,_err )\r
+#define VALIDATE_W_RV(_exp,_api,_err,_rv )\r
+#endif\r
+\r
+// Global config\r
+Mcu_GlobalType Mcu_Global =\r
+{\r
+ .initRun = 0,\r
+ .config = &McuConfigData[0],\r
+};\r
+\r
+//-------------------------------------------------------------------\r
+\r
+static void Mcu_LossOfLock( void ) {\r
+#if ( MCU_DEV_ERROR_DETECT == STD_ON )\r
+ /* Should report MCU_E_CLOCK_FAILURE with DEM here.... but\r
+ * we do the next best thing. Report with Det with API = 0\r
+ */\r
+ Det_ReportError(MODULE_ID_MCU,0,0,MCU_E_PLL_NOT_LOCKED);\r
+#endif\r
+\r
+ Mcu_Global.stats.lossOfLockCnt++;\r
+ // Clear interrupt\r
+// FMPLL.SYNSR.B.LOLF = 1;\r
+\r
+}\r
+\r
+//-------------------------------------------------------------------\r
+static void Mcu_LossOfCLock( void ) {\r
+\r
+ /* Should report MCU_E_CLOCK_FAILURE with DEM here */\r
+\r
+ Mcu_Global.stats.lossOfClockCnt++;\r
+ // Clear interrupt\r
+// FMPLL.SYNSR.B.LOCF = 1;\r
+}\r
+\r
+\r
+#define SPR_PIR 286\r
+#define SPR_PVR 287\r
+\r
+#define CORE_PVR_E200Z1 0x81440000UL\r
+#define CORE_PVR_E200Z0 0x81710000UL\r
+\r
+\r
+typedef struct {\r
+ char *name;\r
+ uint32 pvr;\r
+} core_info_t;\r
+\r
+typedef struct {\r
+ char *name;\r
+ uint32 pvr;\r
+} cpu_info_t;\r
+\r
+cpu_info_t cpu_info_list[] = {\r
+ {\r
+ .name = "MPC5516",\r
+ .pvr = CORE_PVR_E200Z1,\r
+ },\r
+ {\r
+ .name = "MPC5516",\r
+ .pvr = CORE_PVR_E200Z0,\r
+ },\r
+};\r
+\r
+core_info_t core_info_list[] = {\r
+ {\r
+ .name = "CORE_E200Z1",\r
+ .pvr = CORE_PVR_E200Z1,\r
+ },\r
+ {\r
+ .name = "CORE_E200Z1",\r
+ .pvr = CORE_PVR_E200Z1,\r
+ },\r
+};\r
+\r
+// TODO: move\r
+#define ARRAY_SIZE(_x) (sizeof(_x)/sizeof((_x)[0]))\r
+\r
+static cpu_info_t *Mcu_IdentifyCpu(uint32 pvr)\r
+{\r
+ int i;\r
+ for (i = 0; i < ARRAY_SIZE(cpu_info_list); i++) {\r
+ if (cpu_info_list[i].pvr == pvr) {\r
+ return &cpu_info_list[i];\r
+ }\r
+ }\r
+\r
+ return NULL;\r
+}\r
+\r
+static core_info_t *Mcu_IdentifyCore(uint32 pvr)\r
+{\r
+ int i;\r
+ for (i = 0; i < ARRAY_SIZE(core_info_list); i++) {\r
+ if (core_info_list[i].pvr == pvr) {\r
+ return &core_info_list[i];\r
+ }\r
+ }\r
+\r
+ return NULL;\r
+}\r
+\r
+\r
+static uint32 Mcu_CheckCpu( void ) {\r
+\r
+ uint32 pvr;\r
+ uint32 pir;\r
+ cpu_info_t *cpuType;\r
+ core_info_t *coreType;\r
+\r
+ // We have to registers to read here, PIR and PVR\r
+\r
+#if 0\r
+ pir = get_spr(SPR_PIR);\r
+ pvr = get_spr(SPR_PVR);\r
+#endif\r
+\r
+ cpuType = Mcu_IdentifyCpu(pvr);\r
+ coreType = Mcu_IdentifyCore(pvr);\r
+\r
+ if( (cpuType == NULL) || (coreType == NULL) ) {\r
+ // Just hang\r
+ while(1);\r
+ }\r
+\r
+ //DEBUG(DEBUG_HIGH,"/drivers/mcu: Cpu: %s( 0x%08x )\n",cpuType->name,pvr);\r
+ //DEBUG(DEBUG_HIGH,"/drivers/mcu: Core: %s( 0x%08x )\n",coreType->name,pvr);\r
+\r
+ return 0;\r
+}\r
+\r
+\r
+//-------------------------------------------------------------------\r
+\r
+void Mcu_Init(const Mcu_ConfigType *configPtr)\r
+{\r
+ VALIDATE( ( NULL != configPtr ), MCU_INIT_SERVICE_ID, MCU_E_PARAM_CONFIG );\r
+\r
+ if( !SIMULATOR() ) {\r
+ Mcu_CheckCpu();\r
+ }\r
+\r
+ memset(&Mcu_Global.stats,0,sizeof(Mcu_Global.stats));\r
+
+
+ SystemInit();\r
+
+ Irq_Enable();\r
+\r
+ Mcu_Global.config = configPtr;\r
+ Mcu_Global.initRun = 1;\r
+}\r
+//-------------------------------------------------------------------\r
+\r
+void Mcu_DeInit()\r
+{\r
+ Mcu_Global.initRun = FALSE; // Very simple Deinit. Should we do more?\r
+}\r
+\r
+//-------------------------------------------------------------------\r
+Std_ReturnType Mcu_InitRamSection(const Mcu_RamSectionType RamSection)\r
+{\r
+ VALIDATE_W_RV( ( 1 == Mcu_Global.initRun ), MCU_INITRAMSECTION_SERVICE_ID, MCU_E_UNINIT, E_NOT_OK );\r
+ VALIDATE_W_RV( ( RamSection <= Mcu_Global.config->McuRamSectors ), MCU_INITRAMSECTION_SERVICE_ID, MCU_E_PARAM_RAMSECTION, E_NOT_OK );\r
+\r
+ /* NOT SUPPORTED, reason: no support for external RAM */\r
+\r
+ return E_OK;\r
+}\r
+\r
+\r
+\r
+//-------------------------------------------------------------------\r
+\r
+Std_ReturnType Mcu_InitClock(const Mcu_ClockType ClockSetting)\r
+{\r
+ Mcu_ClockSettingConfigType *clockSettingsPtr;\r
+ VALIDATE_W_RV( ( 1 == Mcu_Global.initRun ), MCU_INITCLOCK_SERVICE_ID, MCU_E_UNINIT, E_NOT_OK );\r
+ VALIDATE_W_RV( ( ClockSetting < Mcu_Global.config->McuClockSettings ), MCU_INITCLOCK_SERVICE_ID, MCU_E_PARAM_CLOCK, E_NOT_OK );\r
+\r
+ Mcu_Global.clockSetting = ClockSetting;\r
+ clockSettingsPtr = &Mcu_Global.config->McuClockSettingConfig[Mcu_Global.clockSetting];\r
+\r
+\r
+\r
+#if 0\r
+ /* 5516clock info:\r
+ * Fsys - System frequency ( CPU + all periperals? )\r
+ *\r
+ * Fsys = EXTAL_FREQ *( (emfd+16) / ( (eprediv+1) * ( erfd+1 )) ) )\r
+ */\r
+ // Check ranges...\r
+ assert((clockSettingsPtr->PllEmfd>=32) && (clockSettingsPtr->PllEmfd<=132));\r
+ assert( (clockSettingsPtr->PllEprediv!=6) &&\r
+ (clockSettingsPtr->PllEprediv!=8) &&\r
+ (clockSettingsPtr->PllEprediv<10) );\r
+ assert( clockSettingsPtr->PllErfd & 1); // Must be odd\r
+#endif\r
+\r
+\r
+\r
+#if defined(USE_DEBUG)\r
+ {\r
+ uint32 extal = Mcu_Global.config->McuClockSettingConfig[Mcu_Global.clockSetting].McuClockReferencePoint;\r
+ uint32 f_sys;\r
+\r
+ f_sys = CALC_SYSTEM_CLOCK( extal,\r
+ clockSettingsPtr->PllEmfd,\r
+ clockSettingsPtr->PllEprediv,\r
+ clockSettingsPtr->PllErfd );\r
+\r
+ //DEBUG(DEBUG_HIGH,"/drivers/mcu: F_sys will be:%08d Hz\n",f_sys);\r
+ }\r
+#endif\r
+\r
+#if defined(CFG_MPC5516)\r
+ // External crystal PLL mode.\r
+ FMPLL.ESYNCR1.B.CLKCFG = 7; //TODO: Hur ställa detta för 5567?\r
+\r
+ // Write pll parameters.\r
+ FMPLL.ESYNCR1.B.EPREDIV = clockSettingsPtr->PllEprediv;\r
+ FMPLL.ESYNCR1.B.EMFD = clockSettingsPtr->PllEmfd;\r
+ FMPLL.ESYNCR2.B.ERFD = clockSettingsPtr->PllErfd;\r
+\r
+ // Connect SYSCLK to FMPLL\r
+ SIU.SYSCLK.B.SYSCLKSEL = SYSCLOCK_SELECT_PLL;\r
+#elif defined(CFG_MPC5554) || defined(CFG_MPC5567)\r
+ FMPLL.SYNCR.B.PREDIV = clockSettingsPtr->PllEprediv;\r
+ FMPLL.SYNCR.B.MFD = clockSettingsPtr->PllEmfd;\r
+ FMPLL.SYNCR.B.RFD = clockSettingsPtr->PllErfd;\r
+#endif\r
+\r
+ return E_OK;\r
+}\r
+\r
+//-------------------------------------------------------------------\r
+\r
+void Mcu_DistributePllClock(void)\r
+{\r
+ VALIDATE( ( 1 == Mcu_Global.initRun ), MCU_DISTRIBUTEPLLCLOCK_SERVICE_ID, MCU_E_UNINIT );\r
+// VALIDATE( ( FMPLL.SYNSR.B.LOCK == 1 ), MCU_DISTRIBUTEPLLCLOCK_SERVICE_ID, MCU_E_PLL_NOT_LOCKED );\r
+\r
+ /* NOT IMPLEMENTED due to pointless function on this hardware */\r
+\r
+}\r
+\r
+//-------------------------------------------------------------------\r
+\r
+Mcu_PllStatusType Mcu_GetPllStatus(void)\r
+{\r
+ VALIDATE_W_RV( ( 1 == Mcu_Global.initRun ), MCU_GETPLLSTATUS_SERVICE_ID, MCU_E_UNINIT, MCU_PLL_STATUS_UNDEFINED );\r
+ Mcu_PllStatusType rv;\r
+\r
+ if( !SIMULATOR() )\r
+ {\r
+#if 0\r
+ if ( !FMPLL.SYNSR.B.LOCK )\r
+ {\r
+ rv = MCU_PLL_UNLOCKED;\r
+ } else\r
+ {\r
+ rv = MCU_PLL_LOCKED;\r
+ }\r
+#endif\r
+ }\r
+ else\r
+ {\r
+ /* We are running on instruction set simulator. PLL is then always in sync... */\r
+ rv = MCU_PLL_LOCKED;\r
+ }\r
+\r
+ return rv;\r
+}\r
+\r
+//-------------------------------------------------------------------\r
+\r
+Mcu_ResetType Mcu_GetResetReason(void)\r
+{\r
+ Mcu_ResetType rv;\r
+\r
+ VALIDATE_W_RV( ( 1 == Mcu_Global.initRun ), MCU_GETRESETREASON_SERVICE_ID, MCU_E_UNINIT, MCU_RESET_UNDEFINED );\r
+\r
+#if 0\r
+ if( SIU.RSR.B.SSRS ) {\r
+ rv = MCU_SW_RESET;\r
+ } else if( SIU.RSR.B.WDRS ) {\r
+ rv = MCU_WATCHDOG_RESET;\r
+ } else if( SIU.RSR.B.PORS || SIU.RSR.B.ERS ) {\r
+ rv = MCU_POWER_ON_RESET;\r
+ } else {\r
+ rv = MCU_RESET_UNDEFINED;\r
+ }\r
+#endif\r
+\r
+ return rv;\r
+}\r
+\r
+//-------------------------------------------------------------------\r
+\r
+Mcu_RawResetType Mcu_GetResetRawValue(void)\r
+{\r
+ VALIDATE_W_RV( ( 1 == Mcu_Global.initRun ), MCU_GETRESETREASON_SERVICE_ID, MCU_E_UNINIT, MCU_GETRESETRAWVALUE_UNINIT_RV );\r
+\r
+ if( !Mcu_Global.initRun ) {\r
+ return MCU_GETRESETRAWVALUE_UNINIT_RV;\r
+ }\r
+\r
+#if 0\r
+ return SIU.RSR.R;\r
+#endif\r
+\r
+ return 0;\r
+}\r
+\r
+//-------------------------------------------------------------------\r
+\r
+#if ( MCU_PERFORM_RESET_API == STD_ON )\r
+void Mcu_PerformReset(void)\r
+{\r
+ VALIDATE( ( 1 == Mcu_Global.initRun ), MCU_PERFORMRESET_SERVICE_ID, MCU_E_UNINIT );\r
+\r
+ NVIC_SystemReset();\r
+}\r
+#endif\r
+\r
+//-------------------------------------------------------------------\r
+\r
+void Mcu_SetMode(const Mcu_ModeType McuMode)\r
+{\r
+ VALIDATE( ( 1 == Mcu_Global.initRun ), MCU_SETMODE_SERVICE_ID, MCU_E_UNINIT );\r
+ VALIDATE( ( McuMode <= Mcu_Global.config->McuNumberOfMcuModes ), MCU_SETMODE_SERVICE_ID, MCU_E_PARAM_MODE );\r
+ (void) McuMode;\r
+\r
+ /* NOT SUPPORTED */\r
+}\r
+\r
+//-------------------------------------------------------------------\r
+\r
+/**\r
+ * Get the system clock in Hz. It calculates the clock from the\r
+ * different register settings in HW.\r
+ */\r
+uint32_t McuE_GetSystemClock(void)\r
+{\r
+ /*\r
+ * System clock calculation\r
+ *\r
+ */\r
+ uint32_t f_sys = 0;\r
+#if 0\r
+ uint32 extal = Mcu_Global.config->McuClockSettingConfig[Mcu_Global.clockSetting].McuClockReferencePoint;\r
+\r
+ f_sys = CALC_SYSTEM_CLOCK(extal,emfd,eprediv,erfd);\r
+#endif\r
+\r
+// f_sys = extal * (emfd+16) / ( (eprediv+1) * ( erfd+1 ));\r
+ return f_sys;\r
+}\r
+\r
+imask_t McuE_EnterCriticalSection()\r
+{\r
+#if 0\r
+ uint32_t msr = get_msr();\r
+ Irq_Disable();\r
+ return msr;\r
+#endif\r
+ return 0;\r
+}\r
+\r
+void McuE_ExitCriticalSection(uint32_t old_state)\r
+{\r
+#if 0\r
+ set_msr(old_state);\r
+#endif\r
+}\r
+\r
+/**\r
+ * Get the peripheral clock in Hz for a specific device\r
+ */\r
+\r
+#if 0\r
+uint32_t McuE_GetPeripheralClock(McuE_PeriperalClock_t type)\r
+{\r
+\r
+ return 0;\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ * Function to setup the internal flash for optimal performance\r
+ */\r
+\r
+void Mcu_ConfigureFlash(void)\r
+{\r
+\r
+}\r
+\r
+void McuE_EnableInterrupts(void)\r
+{\r
+ Irq_Enable();\r
+}\r
+\r
+void McuE_DisableInterrupts(void)\r
+{\r
+ Irq_Disable();\r
+}\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/**\r
+ ******************************************************************************\r
+ * @file misc.c\r
+ * @author MCD Application Team\r
+ * @version V3.1.0\r
+ * @date 06/19/2009\r
+ * @brief This file provides all the miscellaneous firmware functions (add-on\r
+ * to CMSIS functions).\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "misc.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup MISC \r
+ * @brief MISC driver modules\r
+ * @{\r
+ */\r
+\r
+/** @defgroup MISC_Private_TypesDefinitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup MISC_Private_Defines\r
+ * @{\r
+ */\r
+\r
+#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup MISC_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup MISC_Private_Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup MISC_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup MISC_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the priority grouping: pre-emption priority and subpriority.\r
+ * @param NVIC_PriorityGroup: specifies the priority grouping bits length. \r
+ * This parameter can be one of the following values:\r
+ * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority\r
+ * 4 bits for subpriority\r
+ * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority\r
+ * 3 bits for subpriority\r
+ * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority\r
+ * 2 bits for subpriority\r
+ * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority\r
+ * 1 bits for subpriority\r
+ * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority\r
+ * 0 bits for subpriority\r
+ * @retval None\r
+ */\r
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));\r
+ \r
+ /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */\r
+ SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the NVIC peripheral according to the specified\r
+ * parameters in the NVIC_InitStruct.\r
+ * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains\r
+ * the configuration information for the specified NVIC peripheral.\r
+ * @retval None\r
+ */\r
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)\r
+{\r
+ uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));\r
+ assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority)); \r
+ assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));\r
+ \r
+ if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)\r
+ {\r
+ /* Compute the Corresponding IRQ Priority --------------------------------*/ \r
+ tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;\r
+ tmppre = (0x4 - tmppriority);\r
+ tmpsub = tmpsub >> tmppriority;\r
+\r
+ tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;\r
+ tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;\r
+ tmppriority = tmppriority << 0x04;\r
+ \r
+ NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;\r
+ \r
+ /* Enable the Selected IRQ Channels --------------------------------------*/\r
+ NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =\r
+ (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Selected IRQ Channels -------------------------------------*/\r
+ NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =\r
+ (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Sets the vector table location and Offset.\r
+ * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.\r
+ * This parameter can be one of the following values:\r
+ * @arg NVIC_VectTab_RAM\r
+ * @arg NVIC_VectTab_FLASH\r
+ * @param Offset: Vector Table base offset field. This value must be a multiple of 0x100.\r
+ * @retval None\r
+ */\r
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));\r
+ assert_param(IS_NVIC_OFFSET(Offset)); \r
+ \r
+ SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);\r
+}\r
+\r
+/**\r
+ * @brief Selects the condition for the system to enter low power mode.\r
+ * @param LowPowerMode: Specifies the new mode for the system to enter low power mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg NVIC_LP_SEVONPEND\r
+ * @arg NVIC_LP_SLEEPDEEP\r
+ * @arg NVIC_LP_SLEEPONEXIT\r
+ * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_LP(LowPowerMode));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState)); \r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ SCB->SCR |= LowPowerMode;\r
+ }\r
+ else\r
+ {\r
+ SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the SysTick clock source.\r
+ * @param SysTick_CLKSource: specifies the SysTick clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.\r
+ * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.\r
+ * @retval None\r
+ */\r
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));\r
+ if (SysTick_CLKSource == SysTick_CLKSource_HCLK)\r
+ {\r
+ SysTick->CTRL |= SysTick_CLKSource_HCLK;\r
+ }\r
+ else\r
+ {\r
+ SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/**\r
+ ******************************************************************************\r
+ * @file misc.h\r
+ * @author MCD Application Team\r
+ * @version V3.1.0\r
+ * @date 06/19/2009\r
+ * @brief This file contains all the functions prototypes for the miscellaneous\r
+ * firmware library functions (add-on to CMSIS functions).\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __MISC_H\r
+#define __MISC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup MISC\r
+ * @{\r
+ */\r
+\r
+/** @defgroup MISC_Exported_Types\r
+ * @{\r
+ */\r
+\r
+/** \r
+ * @brief NVIC Init Structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.\r
+ This parameter can be a value of @ref IRQn_Type \r
+ (For the complete STM32 Devices IRQ Channels list, please\r
+ refer to stm32f10x.h file) */\r
+\r
+ uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel\r
+ specified in NVIC_IRQChannel. This parameter can be a value\r
+ between 0 and 15 as described in the table @ref NVIC_Priority_Table */\r
+\r
+ uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified\r
+ in NVIC_IRQChannel. This parameter can be a value\r
+ between 0 and 15 as described in the table @ref NVIC_Priority_Table */\r
+\r
+ FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel\r
+ will be enabled or disabled. \r
+ This parameter can be set either to ENABLE or DISABLE */ \r
+} NVIC_InitTypeDef;\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup NVIC_Priority_Table \r
+ * @{\r
+ */\r
+\r
+/**\r
+@code \r
+ The table below gives the allowed values of the pre-emption priority and subpriority according\r
+ to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function\r
+ ============================================================================================================================\r
+ NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description\r
+ ============================================================================================================================\r
+ NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority\r
+ | | | 4 bits for subpriority\r
+ ----------------------------------------------------------------------------------------------------------------------------\r
+ NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority\r
+ | | | 3 bits for subpriority\r
+ ---------------------------------------------------------------------------------------------------------------------------- \r
+ NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority\r
+ | | | 2 bits for subpriority\r
+ ---------------------------------------------------------------------------------------------------------------------------- \r
+ NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority\r
+ | | | 1 bits for subpriority\r
+ ---------------------------------------------------------------------------------------------------------------------------- \r
+ NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority\r
+ | | | 0 bits for subpriority \r
+ ============================================================================================================================\r
+@endcode\r
+*/\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup MISC_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup Vector_Table_Base \r
+ * @{\r
+ */\r
+\r
+#define NVIC_VectTab_RAM ((uint32_t)0x20000000)\r
+#define NVIC_VectTab_FLASH ((uint32_t)0x08000000)\r
+#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \\r
+ ((VECTTAB) == NVIC_VectTab_FLASH))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup System_Low_Power \r
+ * @{\r
+ */\r
+\r
+#define NVIC_LP_SEVONPEND ((uint8_t)0x10)\r
+#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)\r
+#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)\r
+#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \\r
+ ((LP) == NVIC_LP_SLEEPDEEP) || \\r
+ ((LP) == NVIC_LP_SLEEPONEXIT))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Preemption_Priority_Group \r
+ * @{\r
+ */\r
+\r
+#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority\r
+ 4 bits for subpriority */\r
+#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority\r
+ 3 bits for subpriority */\r
+#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority\r
+ 2 bits for subpriority */\r
+#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority\r
+ 1 bits for subpriority */\r
+#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority\r
+ 0 bits for subpriority */\r
+\r
+#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \\r
+ ((GROUP) == NVIC_PriorityGroup_1) || \\r
+ ((GROUP) == NVIC_PriorityGroup_2) || \\r
+ ((GROUP) == NVIC_PriorityGroup_3) || \\r
+ ((GROUP) == NVIC_PriorityGroup_4))\r
+\r
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)\r
+\r
+#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)\r
+\r
+#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x0007FFFF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SysTick_clock_source \r
+ * @{\r
+ */\r
+\r
+#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)\r
+#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)\r
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \\r
+ ((SOURCE) == SysTick_CLKSource_HCLK_Div8))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup MISC_Exported_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup MISC_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);\r
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);\r
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);\r
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);\r
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __MISC_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x.h\r
+ * @author MCD Application Team\r
+ * @version V3.1.0\r
+ * @date 06/19/2009\r
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. \r
+ * This file contains all the peripheral register's definitions, bits \r
+ * definitions and memory mapping for STM32F10x Connectivity line, High\r
+ * density, Medium density and Low density devices.\r
+ ****************************************************************************** \r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/** @addtogroup CMSIS\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup stm32f10x\r
+ * @{\r
+ */\r
+ \r
+#ifndef __STM32F10x_H\r
+#define __STM32F10x_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif \r
+ \r
+/** @addtogroup Library_configuration_section\r
+ * @{\r
+ */\r
+ \r
+/* Uncomment the line below according to the target STM32 device used in your\r
+ application \r
+ */\r
+\r
+#if !defined (STM32F10X_LD) && !defined (STM32F10X_MD) && !defined (STM32F10X_HD) && !defined (STM32F10X_CL)\r
+ /* #define STM32F10X_LD */ /*!< STM32F10X_LD: STM32 Low density devices */\r
+ /* #define STM32F10X_MD */ /*!< STM32F10X_MD: STM32 Medium density devices */\r
+ /* #define STM32F10X_HD */ /*!< STM32F10X_HD: STM32 High density devices */\r
+ #define STM32F10X_CL /*!< STM32F10X_CL: STM32 Connectivity line devices */\r
+#endif\r
+/* Tip: To avoid modifying this file each time you need to switch between these\r
+ devices, you can define the device in your toolchain compiler preprocessor.\r
+\r
+ - Low density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers\r
+ where the Flash memory density ranges between 16 and 32 Kbytes.\r
+ - Medium density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers\r
+ where the Flash memory density ranges between 64 and 128 Kbytes.\r
+ - High density devices are STM32F101xx and STM32F103xx microcontrollers where\r
+ the Flash memory density ranges between 256 and 512 Kbytes.\r
+ - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.\r
+ */\r
+\r
+#if !defined USE_STDPERIPH_DRIVER\r
+/**\r
+ * @brief Comment the line below if you will not use the peripherals drivers.\r
+ In this case, these drivers will not be included and the application code will \r
+ be based on direct access to peripherals registers \r
+ */\r
+ /*#define USE_STDPERIPH_DRIVER*/\r
+#endif\r
+\r
+/**\r
+ * @brief In the following line adjust the value of External High Speed oscillator (HSE)\r
+ used in your application \r
+ \r
+ Tip: To avoid modifying this file each time you need to use different HSE, you\r
+ can define the HSE value in your toolchain compiler preprocessor.\r
+ */ \r
+#if !defined HSE_Value\r
+ #ifdef STM32F10X_CL \r
+ #define HSE_Value ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */\r
+ #else \r
+ #define HSE_Value ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */\r
+ #endif /* STM32F10X_CL */\r
+#endif /* HSE_Value */\r
+\r
+\r
+/**\r
+ * @brief In the following line adjust the External High Speed oscillator (HSE) Startup \r
+ Timeout value \r
+ */\r
+#define HSEStartUp_TimeOut ((uint16_t)0x0500) /*!< Time out for HSE start up */\r
+\r
+#define HSI_Value ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/\r
+\r
+/**\r
+ * @brief STM32F10x Standard Peripheral Library version number\r
+ */\r
+#define __STM32F10X_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:16] STM32F10x Standard Peripheral Library main version */\r
+#define __STM32F10X_STDPERIPH_VERSION_SUB1 (0x01) /*!< [15:8] STM32F10x Standard Peripheral Library sub1 version */\r
+#define __STM32F10X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [7:0] STM32F10x Standard Peripheral Library sub2 version */\r
+#define __STM32F10X_STDPERIPH_VERSION ((__STM32F10X_STDPERIPH_VERSION_MAIN << 16)\\r
+ | (__STM32F10X_STDPERIPH_VERSION_SUB1 << 8)\\r
+ | __STM32F10X_STDPERIPH_VERSION_SUB2)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup Configuration_section_for_CMSIS\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configuration of the Cortex-M3 Processor and Core Peripherals \r
+ */\r
+#define __MPU_PRESENT 0 /*!< STM32 does not provide an MPU */\r
+#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */\r
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */\r
+\r
+/**\r
+ * @brief STM32F10x Interrupt Number Definition, according to the selected device \r
+ * in @ref Library_configuration_section \r
+ */\r
+typedef enum IRQn\r
+{\r
+/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/\r
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */\r
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */\r
+ BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */\r
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */\r
+ SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */\r
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */\r
+ PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */\r
+\r
+/****** STM32 specific Interrupt Numbers *********************************************************/\r
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */\r
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */\r
+ TAMPER_IRQn = 2, /*!< Tamper Interrupt */\r
+ RTC_IRQn = 3, /*!< RTC global Interrupt */\r
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */\r
+ RCC_IRQn = 5, /*!< RCC global Interrupt */\r
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */\r
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */\r
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */\r
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */\r
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */\r
+ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */\r
+ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */\r
+ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */\r
+ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */\r
+ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */\r
+ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */\r
+ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */\r
+ ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */\r
+\r
+#ifdef STM32F10X_LD\r
+ USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */\r
+ USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */\r
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */\r
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */\r
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */\r
+ TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */\r
+ TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */\r
+ TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */\r
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */\r
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */\r
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */\r
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */\r
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */\r
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */\r
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */\r
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */\r
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */\r
+ RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */\r
+ USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ \r
+#endif /* STM32F10X_LD */ \r
+\r
+#ifdef STM32F10X_MD\r
+ USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */\r
+ USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */\r
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */\r
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */\r
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */\r
+ TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */\r
+ TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */\r
+ TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */\r
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */\r
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */\r
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */\r
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */\r
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */\r
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */\r
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */\r
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */\r
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */\r
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */\r
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */\r
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */\r
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */\r
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */\r
+ RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */\r
+ USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ \r
+#endif /* STM32F10X_MD */ \r
+\r
+#ifdef STM32F10X_HD\r
+ USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */\r
+ USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */\r
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */\r
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */\r
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */\r
+ TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */\r
+ TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */\r
+ TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */\r
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */\r
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */\r
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */\r
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */\r
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */\r
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */\r
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */\r
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */\r
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */\r
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */\r
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */\r
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */\r
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */\r
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */\r
+ RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */\r
+ USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */\r
+ TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */\r
+ TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */\r
+ TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */\r
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */\r
+ ADC3_IRQn = 47, /*!< ADC3 global Interrupt */\r
+ FSMC_IRQn = 48, /*!< FSMC global Interrupt */\r
+ SDIO_IRQn = 49, /*!< SDIO global Interrupt */\r
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */\r
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */\r
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */\r
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */\r
+ TIM6_IRQn = 54, /*!< TIM6 global Interrupt */\r
+ TIM7_IRQn = 55, /*!< TIM7 global Interrupt */\r
+ DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */\r
+ DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */\r
+ DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */\r
+ DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */\r
+#endif /* STM32F10X_HD */ \r
+\r
+#ifdef STM32F10X_CL\r
+ CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */\r
+ CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */\r
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */\r
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */\r
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */\r
+ TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */\r
+ TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */\r
+ TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */\r
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */\r
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */\r
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */\r
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */\r
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */\r
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */\r
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */\r
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */\r
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */\r
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */\r
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */\r
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */\r
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */\r
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */\r
+ RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */\r
+ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS WakeUp from suspend through EXTI Line Interrupt */\r
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */\r
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */\r
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */\r
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */\r
+ TIM6_IRQn = 54, /*!< TIM6 global Interrupt */\r
+ TIM7_IRQn = 55, /*!< TIM7 global Interrupt */\r
+ DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */\r
+ DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */\r
+ DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */\r
+ DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */\r
+ DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */\r
+ ETH_IRQn = 61, /*!< Ethernet global Interrupt */\r
+ ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */\r
+ CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */\r
+ CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */\r
+ CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */\r
+ CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */\r
+ OTG_FS_IRQn = 67 /*!< USB OTG FS global Interrupt */\r
+#endif /* STM32F10X_CL */ \r
+} IRQn_Type;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#include "core_cm3.h"\r
+#include "system_stm32f10x.h"\r
+#include <stdint.h>\r
+\r
+/** @addtogroup Exported_types\r
+ * @{\r
+ */ \r
+\r
+/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */\r
+typedef int32_t s32;\r
+typedef int16_t s16;\r
+typedef int8_t s8;\r
+\r
+typedef const int32_t sc32; /*!< Read Only */\r
+typedef const int16_t sc16; /*!< Read Only */\r
+typedef const int8_t sc8; /*!< Read Only */\r
+\r
+typedef __IO int32_t vs32;\r
+typedef __IO int16_t vs16;\r
+typedef __IO int8_t vs8;\r
+\r
+typedef __I int32_t vsc32; /*!< Read Only */\r
+typedef __I int16_t vsc16; /*!< Read Only */\r
+typedef __I int8_t vsc8; /*!< Read Only */\r
+\r
+typedef uint32_t u32;\r
+typedef uint16_t u16;\r
+typedef uint8_t u8;\r
+\r
+typedef const uint32_t uc32; /*!< Read Only */\r
+typedef const uint16_t uc16; /*!< Read Only */\r
+typedef const uint8_t uc8; /*!< Read Only */\r
+\r
+typedef __IO uint32_t vu32;\r
+typedef __IO uint16_t vu16;\r
+typedef __IO uint8_t vu8;\r
+\r
+typedef __I uint32_t vuc32; /*!< Read Only */\r
+typedef __I uint16_t vuc16; /*!< Read Only */\r
+typedef __I uint8_t vuc8; /*!< Read Only */\r
+\r
+#if !defined(FALSE)\r
+#ifndef __cplusplus\r
+typedef enum {FALSE = 0, TRUE = !FALSE} bool;\r
+#endif\r
+#endif\r
+\r
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;\r
+\r
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;\r
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))\r
+\r
+typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup Peripheral_registers_structures\r
+ * @{\r
+ */ \r
+\r
+/** \r
+ * @brief Analog to Digital Converter \r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t SR;\r
+ __IO uint32_t CR1;\r
+ __IO uint32_t CR2;\r
+ __IO uint32_t SMPR1;\r
+ __IO uint32_t SMPR2;\r
+ __IO uint32_t JOFR1;\r
+ __IO uint32_t JOFR2;\r
+ __IO uint32_t JOFR3;\r
+ __IO uint32_t JOFR4;\r
+ __IO uint32_t HTR;\r
+ __IO uint32_t LTR;\r
+ __IO uint32_t SQR1;\r
+ __IO uint32_t SQR2;\r
+ __IO uint32_t SQR3;\r
+ __IO uint32_t JSQR;\r
+ __IO uint32_t JDR1;\r
+ __IO uint32_t JDR2;\r
+ __IO uint32_t JDR3;\r
+ __IO uint32_t JDR4;\r
+ __IO uint32_t DR;\r
+} ADC_TypeDef;\r
+\r
+/** \r
+ * @brief Backup Registers \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0;\r
+ __IO uint16_t DR1;\r
+ uint16_t RESERVED1;\r
+ __IO uint16_t DR2;\r
+ uint16_t RESERVED2;\r
+ __IO uint16_t DR3;\r
+ uint16_t RESERVED3;\r
+ __IO uint16_t DR4;\r
+ uint16_t RESERVED4;\r
+ __IO uint16_t DR5;\r
+ uint16_t RESERVED5;\r
+ __IO uint16_t DR6;\r
+ uint16_t RESERVED6;\r
+ __IO uint16_t DR7;\r
+ uint16_t RESERVED7;\r
+ __IO uint16_t DR8;\r
+ uint16_t RESERVED8;\r
+ __IO uint16_t DR9;\r
+ uint16_t RESERVED9;\r
+ __IO uint16_t DR10;\r
+ uint16_t RESERVED10; \r
+ __IO uint16_t RTCCR;\r
+ uint16_t RESERVED11;\r
+ __IO uint16_t CR;\r
+ uint16_t RESERVED12;\r
+ __IO uint16_t CSR;\r
+ uint16_t RESERVED13[5];\r
+ __IO uint16_t DR11;\r
+ uint16_t RESERVED14;\r
+ __IO uint16_t DR12;\r
+ uint16_t RESERVED15;\r
+ __IO uint16_t DR13;\r
+ uint16_t RESERVED16;\r
+ __IO uint16_t DR14;\r
+ uint16_t RESERVED17;\r
+ __IO uint16_t DR15;\r
+ uint16_t RESERVED18;\r
+ __IO uint16_t DR16;\r
+ uint16_t RESERVED19;\r
+ __IO uint16_t DR17;\r
+ uint16_t RESERVED20;\r
+ __IO uint16_t DR18;\r
+ uint16_t RESERVED21;\r
+ __IO uint16_t DR19;\r
+ uint16_t RESERVED22;\r
+ __IO uint16_t DR20;\r
+ uint16_t RESERVED23;\r
+ __IO uint16_t DR21;\r
+ uint16_t RESERVED24;\r
+ __IO uint16_t DR22;\r
+ uint16_t RESERVED25;\r
+ __IO uint16_t DR23;\r
+ uint16_t RESERVED26;\r
+ __IO uint16_t DR24;\r
+ uint16_t RESERVED27;\r
+ __IO uint16_t DR25;\r
+ uint16_t RESERVED28;\r
+ __IO uint16_t DR26;\r
+ uint16_t RESERVED29;\r
+ __IO uint16_t DR27;\r
+ uint16_t RESERVED30;\r
+ __IO uint16_t DR28;\r
+ uint16_t RESERVED31;\r
+ __IO uint16_t DR29;\r
+ uint16_t RESERVED32;\r
+ __IO uint16_t DR30;\r
+ uint16_t RESERVED33; \r
+ __IO uint16_t DR31;\r
+ uint16_t RESERVED34;\r
+ __IO uint16_t DR32;\r
+ uint16_t RESERVED35;\r
+ __IO uint16_t DR33;\r
+ uint16_t RESERVED36;\r
+ __IO uint16_t DR34;\r
+ uint16_t RESERVED37;\r
+ __IO uint16_t DR35;\r
+ uint16_t RESERVED38;\r
+ __IO uint16_t DR36;\r
+ uint16_t RESERVED39;\r
+ __IO uint16_t DR37;\r
+ uint16_t RESERVED40;\r
+ __IO uint16_t DR38;\r
+ uint16_t RESERVED41;\r
+ __IO uint16_t DR39;\r
+ uint16_t RESERVED42;\r
+ __IO uint16_t DR40;\r
+ uint16_t RESERVED43;\r
+ __IO uint16_t DR41;\r
+ uint16_t RESERVED44;\r
+ __IO uint16_t DR42;\r
+ uint16_t RESERVED45; \r
+} BKP_TypeDef;\r
+\r
+/** \r
+ * @brief Controller Area Network TxMailBox \r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t TIR;\r
+ __IO uint32_t TDTR;\r
+ __IO uint32_t TDLR;\r
+ __IO uint32_t TDHR;\r
+} CAN_TxMailBox_TypeDef;\r
+\r
+/** \r
+ * @brief Controller Area Network FIFOMailBox \r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint32_t RIR;\r
+ __IO uint32_t RDTR;\r
+ __IO uint32_t RDLR;\r
+ __IO uint32_t RDHR;\r
+} CAN_FIFOMailBox_TypeDef;\r
+\r
+/** \r
+ * @brief Controller Area Network FilterRegister \r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint32_t FR1;\r
+ __IO uint32_t FR2;\r
+} CAN_FilterRegister_TypeDef;\r
+\r
+/** \r
+ * @brief Controller Area Network \r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint32_t MCR;\r
+ __IO uint32_t MSR;\r
+ __IO uint32_t TSR;\r
+ __IO uint32_t RF0R;\r
+ __IO uint32_t RF1R;\r
+ __IO uint32_t IER;\r
+ __IO uint32_t ESR;\r
+ __IO uint32_t BTR;\r
+ uint32_t RESERVED0[88];\r
+ CAN_TxMailBox_TypeDef sTxMailBox[3];\r
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];\r
+ uint32_t RESERVED1[12];\r
+ __IO uint32_t FMR;\r
+ __IO uint32_t FM1R;\r
+ uint32_t RESERVED2;\r
+ __IO uint32_t FS1R;\r
+ uint32_t RESERVED3;\r
+ __IO uint32_t FFA1R;\r
+ uint32_t RESERVED4;\r
+ __IO uint32_t FA1R;\r
+ uint32_t RESERVED5[8];\r
+#ifndef STM32F10X_CL\r
+ CAN_FilterRegister_TypeDef sFilterRegister[14];\r
+#else\r
+ CAN_FilterRegister_TypeDef sFilterRegister[28];\r
+#endif /* STM32F10X_CL */ \r
+} CAN_TypeDef;\r
+\r
+/** \r
+ * @brief CRC calculation unit \r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t DR;\r
+ __IO uint8_t IDR;\r
+ uint8_t RESERVED0;\r
+ uint16_t RESERVED1;\r
+ __IO uint32_t CR;\r
+} CRC_TypeDef;\r
+\r
+/** \r
+ * @brief Digital to Analog Converter\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR;\r
+ __IO uint32_t SWTRIGR;\r
+ __IO uint32_t DHR12R1;\r
+ __IO uint32_t DHR12L1;\r
+ __IO uint32_t DHR8R1;\r
+ __IO uint32_t DHR12R2;\r
+ __IO uint32_t DHR12L2;\r
+ __IO uint32_t DHR8R2;\r
+ __IO uint32_t DHR12RD;\r
+ __IO uint32_t DHR12LD;\r
+ __IO uint32_t DHR8RD;\r
+ __IO uint32_t DOR1;\r
+ __IO uint32_t DOR2;\r
+} DAC_TypeDef;\r
+\r
+/** \r
+ * @brief Debug MCU\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t IDCODE;\r
+ __IO uint32_t CR; \r
+}DBGMCU_TypeDef;\r
+\r
+/** \r
+ * @brief DMA Controller\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CCR;\r
+ __IO uint32_t CNDTR;\r
+ __IO uint32_t CPAR;\r
+ __IO uint32_t CMAR;\r
+} DMA_Channel_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t ISR;\r
+ __IO uint32_t IFCR;\r
+} DMA_TypeDef;\r
+\r
+/** \r
+ * @brief Ethernet MAC\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t MACCR;\r
+ __IO uint32_t MACFFR;\r
+ __IO uint32_t MACHTHR;\r
+ __IO uint32_t MACHTLR;\r
+ __IO uint32_t MACMIIAR;\r
+ __IO uint32_t MACMIIDR;\r
+ __IO uint32_t MACFCR;\r
+ __IO uint32_t MACVLANTR; /* 8 */\r
+ uint32_t RESERVED0[2];\r
+ __IO uint32_t MACRWUFFR; /* 11 */\r
+ __IO uint32_t MACPMTCSR;\r
+ uint32_t RESERVED1[2];\r
+ __IO uint32_t MACSR; /* 15 */\r
+ __IO uint32_t MACIMR;\r
+ __IO uint32_t MACA0HR;\r
+ __IO uint32_t MACA0LR;\r
+ __IO uint32_t MACA1HR;\r
+ __IO uint32_t MACA1LR;\r
+ __IO uint32_t MACA2HR;\r
+ __IO uint32_t MACA2LR;\r
+ __IO uint32_t MACA3HR;\r
+ __IO uint32_t MACA3LR; /* 24 */\r
+ uint32_t RESERVED2[40];\r
+ __IO uint32_t MMCCR; /* 65 */\r
+ __IO uint32_t MMCRIR;\r
+ __IO uint32_t MMCTIR;\r
+ __IO uint32_t MMCRIMR;\r
+ __IO uint32_t MMCTIMR; /* 69 */\r
+ uint32_t RESERVED3[14];\r
+ __IO uint32_t MMCTGFSCCR; /* 84 */\r
+ __IO uint32_t MMCTGFMSCCR;\r
+ uint32_t RESERVED4[5];\r
+ __IO uint32_t MMCTGFCR;\r
+ uint32_t RESERVED5[10];\r
+ __IO uint32_t MMCRFCECR;\r
+ __IO uint32_t MMCRFAECR;\r
+ uint32_t RESERVED6[10];\r
+ __IO uint32_t MMCRGUFCR;\r
+ uint32_t RESERVED7[334];\r
+ __IO uint32_t PTPTSCR;\r
+ __IO uint32_t PTPSSIR;\r
+ __IO uint32_t PTPTSHR;\r
+ __IO uint32_t PTPTSLR;\r
+ __IO uint32_t PTPTSHUR;\r
+ __IO uint32_t PTPTSLUR;\r
+ __IO uint32_t PTPTSAR;\r
+ __IO uint32_t PTPTTHR;\r
+ __IO uint32_t PTPTTLR;\r
+ uint32_t RESERVED8[567];\r
+ __IO uint32_t DMABMR;\r
+ __IO uint32_t DMATPDR;\r
+ __IO uint32_t DMARPDR;\r
+ __IO uint32_t DMARDLAR;\r
+ __IO uint32_t DMATDLAR;\r
+ __IO uint32_t DMASR;\r
+ __IO uint32_t DMAOMR;\r
+ __IO uint32_t DMAIER;\r
+ __IO uint32_t DMAMFBOCR;\r
+ uint32_t RESERVED9[9];\r
+ __IO uint32_t DMACHTDR;\r
+ __IO uint32_t DMACHRDR;\r
+ __IO uint32_t DMACHTBAR;\r
+ __IO uint32_t DMACHRBAR;\r
+} ETH_TypeDef;\r
+\r
+/** \r
+ * @brief External Interrupt/Event Controller\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t IMR;\r
+ __IO uint32_t EMR;\r
+ __IO uint32_t RTSR;\r
+ __IO uint32_t FTSR;\r
+ __IO uint32_t SWIER;\r
+ __IO uint32_t PR;\r
+} EXTI_TypeDef;\r
+\r
+/** \r
+ * @brief FLASH Registers\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t ACR;\r
+ __IO uint32_t KEYR;\r
+ __IO uint32_t OPTKEYR;\r
+ __IO uint32_t SR;\r
+ __IO uint32_t CR;\r
+ __IO uint32_t AR;\r
+ __IO uint32_t RESERVED;\r
+ __IO uint32_t OBR;\r
+ __IO uint32_t WRPR;\r
+} FLASH_TypeDef;\r
+\r
+/** \r
+ * @brief Option Bytes Registers\r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint16_t RDP;\r
+ __IO uint16_t USER;\r
+ __IO uint16_t Data0;\r
+ __IO uint16_t Data1;\r
+ __IO uint16_t WRP0;\r
+ __IO uint16_t WRP1;\r
+ __IO uint16_t WRP2;\r
+ __IO uint16_t WRP3;\r
+} OB_TypeDef;\r
+\r
+/** \r
+ * @brief Flexible Static Memory Controller\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t BTCR[8]; \r
+} FSMC_Bank1_TypeDef; \r
+\r
+/** \r
+ * @brief Flexible Static Memory Controller Bank1E\r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint32_t BWTR[7];\r
+} FSMC_Bank1E_TypeDef;\r
+\r
+/** \r
+ * @brief Flexible Static Memory Controller Bank2\r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint32_t PCR2;\r
+ __IO uint32_t SR2;\r
+ __IO uint32_t PMEM2;\r
+ __IO uint32_t PATT2;\r
+ uint32_t RESERVED0; \r
+ __IO uint32_t ECCR2; \r
+} FSMC_Bank2_TypeDef; \r
+\r
+/** \r
+ * @brief Flexible Static Memory Controller Bank3\r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint32_t PCR3;\r
+ __IO uint32_t SR3;\r
+ __IO uint32_t PMEM3;\r
+ __IO uint32_t PATT3;\r
+ uint32_t RESERVED0; \r
+ __IO uint32_t ECCR3; \r
+} FSMC_Bank3_TypeDef; \r
+\r
+/** \r
+ * @brief Flexible Static Memory Controller Bank4\r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint32_t PCR4;\r
+ __IO uint32_t SR4;\r
+ __IO uint32_t PMEM4;\r
+ __IO uint32_t PATT4;\r
+ __IO uint32_t PIO4; \r
+} FSMC_Bank4_TypeDef; \r
+\r
+/** \r
+ * @brief General Purpose I/O\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CRL;\r
+ __IO uint32_t CRH;\r
+ __IO uint32_t IDR;\r
+ __IO uint32_t ODR;\r
+ __IO uint32_t BSRR;\r
+ __IO uint32_t BRR;\r
+ __IO uint32_t LCKR;\r
+} GPIO_TypeDef;\r
+\r
+/** \r
+ * @brief Alternate Function I/O\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t EVCR;\r
+ __IO uint32_t MAPR;\r
+ __IO uint32_t EXTICR[4];\r
+} AFIO_TypeDef;\r
+/** \r
+ * @brief Inter-integrated Circuit Interface\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint16_t CR1;\r
+ uint16_t RESERVED0;\r
+ __IO uint16_t CR2;\r
+ uint16_t RESERVED1;\r
+ __IO uint16_t OAR1;\r
+ uint16_t RESERVED2;\r
+ __IO uint16_t OAR2;\r
+ uint16_t RESERVED3;\r
+ __IO uint16_t DR;\r
+ uint16_t RESERVED4;\r
+ __IO uint16_t SR1;\r
+ uint16_t RESERVED5;\r
+ __IO uint16_t SR2;\r
+ uint16_t RESERVED6;\r
+ __IO uint16_t CCR;\r
+ uint16_t RESERVED7;\r
+ __IO uint16_t TRISE;\r
+ uint16_t RESERVED8;\r
+} I2C_TypeDef;\r
+\r
+/** \r
+ * @brief Independent WATCHDOG\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t KR;\r
+ __IO uint32_t PR;\r
+ __IO uint32_t RLR;\r
+ __IO uint32_t SR;\r
+} IWDG_TypeDef;\r
+\r
+/** \r
+ * @brief Power Control\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR;\r
+ __IO uint32_t CSR;\r
+} PWR_TypeDef;\r
+\r
+/** \r
+ * @brief Reset and Clock Control\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR;\r
+ __IO uint32_t CFGR;\r
+ __IO uint32_t CIR;\r
+ __IO uint32_t APB2RSTR;\r
+ __IO uint32_t APB1RSTR;\r
+ __IO uint32_t AHBENR;\r
+ __IO uint32_t APB2ENR;\r
+ __IO uint32_t APB1ENR;\r
+ __IO uint32_t BDCR;\r
+ __IO uint32_t CSR;\r
+#ifdef STM32F10X_CL \r
+ __IO uint32_t AHBRSTR;\r
+ __IO uint32_t CFGR2;\r
+#endif /* STM32F10X_CL */ \r
+} RCC_TypeDef;\r
+\r
+/** \r
+ * @brief Real-Time Clock\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint16_t CRH;\r
+ uint16_t RESERVED0;\r
+ __IO uint16_t CRL;\r
+ uint16_t RESERVED1;\r
+ __IO uint16_t PRLH;\r
+ uint16_t RESERVED2;\r
+ __IO uint16_t PRLL;\r
+ uint16_t RESERVED3;\r
+ __IO uint16_t DIVH;\r
+ uint16_t RESERVED4;\r
+ __IO uint16_t DIVL;\r
+ uint16_t RESERVED5;\r
+ __IO uint16_t CNTH;\r
+ uint16_t RESERVED6;\r
+ __IO uint16_t CNTL;\r
+ uint16_t RESERVED7;\r
+ __IO uint16_t ALRH;\r
+ uint16_t RESERVED8;\r
+ __IO uint16_t ALRL;\r
+ uint16_t RESERVED9;\r
+} RTC_TypeDef;\r
+\r
+/** \r
+ * @brief SD host Interface\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t POWER;\r
+ __IO uint32_t CLKCR;\r
+ __IO uint32_t ARG;\r
+ __IO uint32_t CMD;\r
+ __I uint32_t RESPCMD;\r
+ __I uint32_t RESP1;\r
+ __I uint32_t RESP2;\r
+ __I uint32_t RESP3;\r
+ __I uint32_t RESP4;\r
+ __IO uint32_t DTIMER;\r
+ __IO uint32_t DLEN;\r
+ __IO uint32_t DCTRL;\r
+ __I uint32_t DCOUNT;\r
+ __I uint32_t STA;\r
+ __IO uint32_t ICR;\r
+ __IO uint32_t MASK;\r
+ uint32_t RESERVED0[2];\r
+ __I uint32_t FIFOCNT;\r
+ uint32_t RESERVED1[13];\r
+ __IO uint32_t FIFO;\r
+} SDIO_TypeDef;\r
+\r
+/** \r
+ * @brief Serial Peripheral Interface\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint16_t CR1;\r
+ uint16_t RESERVED0;\r
+ __IO uint16_t CR2;\r
+ uint16_t RESERVED1;\r
+ __IO uint16_t SR;\r
+ uint16_t RESERVED2;\r
+ __IO uint16_t DR;\r
+ uint16_t RESERVED3;\r
+ __IO uint16_t CRCPR;\r
+ uint16_t RESERVED4;\r
+ __IO uint16_t RXCRCR;\r
+ uint16_t RESERVED5;\r
+ __IO uint16_t TXCRCR;\r
+ uint16_t RESERVED6;\r
+ __IO uint16_t I2SCFGR;\r
+ uint16_t RESERVED7;\r
+ __IO uint16_t I2SPR;\r
+ uint16_t RESERVED8; \r
+} SPI_TypeDef;\r
+\r
+/** \r
+ * @brief TIM\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint16_t CR1;\r
+ uint16_t RESERVED0;\r
+ __IO uint16_t CR2;\r
+ uint16_t RESERVED1;\r
+ __IO uint16_t SMCR;\r
+ uint16_t RESERVED2;\r
+ __IO uint16_t DIER;\r
+ uint16_t RESERVED3;\r
+ __IO uint16_t SR;\r
+ uint16_t RESERVED4;\r
+ __IO uint16_t EGR;\r
+ uint16_t RESERVED5;\r
+ __IO uint16_t CCMR1;\r
+ uint16_t RESERVED6;\r
+ __IO uint16_t CCMR2;\r
+ uint16_t RESERVED7;\r
+ __IO uint16_t CCER;\r
+ uint16_t RESERVED8;\r
+ __IO uint16_t CNT;\r
+ uint16_t RESERVED9;\r
+ __IO uint16_t PSC;\r
+ uint16_t RESERVED10;\r
+ __IO uint16_t ARR;\r
+ uint16_t RESERVED11;\r
+ __IO uint16_t RCR;\r
+ uint16_t RESERVED12;\r
+ __IO uint16_t CCR1;\r
+ uint16_t RESERVED13;\r
+ __IO uint16_t CCR2;\r
+ uint16_t RESERVED14;\r
+ __IO uint16_t CCR3;\r
+ uint16_t RESERVED15;\r
+ __IO uint16_t CCR4;\r
+ uint16_t RESERVED16;\r
+ __IO uint16_t BDTR;\r
+ uint16_t RESERVED17;\r
+ __IO uint16_t DCR;\r
+ uint16_t RESERVED18;\r
+ __IO uint16_t DMAR;\r
+ uint16_t RESERVED19;\r
+} TIM_TypeDef;\r
+\r
+/** \r
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter\r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint16_t SR;\r
+ uint16_t RESERVED0;\r
+ __IO uint16_t DR;\r
+ uint16_t RESERVED1;\r
+ __IO uint16_t BRR;\r
+ uint16_t RESERVED2;\r
+ __IO uint16_t CR1;\r
+ uint16_t RESERVED3;\r
+ __IO uint16_t CR2;\r
+ uint16_t RESERVED4;\r
+ __IO uint16_t CR3;\r
+ uint16_t RESERVED5;\r
+ __IO uint16_t GTPR;\r
+ uint16_t RESERVED6;\r
+} USART_TypeDef;\r
+\r
+/** \r
+ * @brief Window WATCHDOG\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR;\r
+ __IO uint32_t CFR;\r
+ __IO uint32_t SR;\r
+} WWDG_TypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @addtogroup Peripheral_memory_map\r
+ * @{\r
+ */\r
+\r
+#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the alias region */\r
+#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the alias region */\r
+\r
+#define SRAM_BASE ((uint32_t)0x20000000) /*!< Peripheral base address in the bit-band region */\r
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< SRAM base address in the bit-band region */\r
+\r
+#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */\r
+\r
+/*!< Peripheral memory map */\r
+#define APB1PERIPH_BASE PERIPH_BASE\r
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)\r
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)\r
+\r
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)\r
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)\r
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)\r
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)\r
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)\r
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)\r
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800)\r
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)\r
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)\r
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)\r
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)\r
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400)\r
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800)\r
+#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)\r
+#define UART5_BASE (APB1PERIPH_BASE + 0x5000)\r
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)\r
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)\r
+#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)\r
+#define CAN2_BASE (APB1PERIPH_BASE + 0x6800)\r
+#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)\r
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000)\r
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400)\r
+\r
+#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)\r
+#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)\r
+#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)\r
+#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)\r
+#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)\r
+#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)\r
+#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)\r
+#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00)\r
+#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000)\r
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)\r
+#define ADC2_BASE (APB2PERIPH_BASE + 0x2800)\r
+#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)\r
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)\r
+#define TIM8_BASE (APB2PERIPH_BASE + 0x3400)\r
+#define USART1_BASE (APB2PERIPH_BASE + 0x3800)\r
+#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00)\r
+\r
+#define SDIO_BASE (PERIPH_BASE + 0x18000)\r
+\r
+#define DMA1_BASE (AHBPERIPH_BASE + 0x0000)\r
+#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)\r
+#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)\r
+#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)\r
+#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)\r
+#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)\r
+#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)\r
+#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)\r
+#define DMA2_BASE (AHBPERIPH_BASE + 0x0400)\r
+#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408)\r
+#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C)\r
+#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430)\r
+#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444)\r
+#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458)\r
+#define RCC_BASE (AHBPERIPH_BASE + 0x1000)\r
+#define CRC_BASE (AHBPERIPH_BASE + 0x3000)\r
+\r
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */\r
+#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */\r
+\r
+#define ETH_BASE (AHBPERIPH_BASE + 0x8000)\r
+#define ETH_MAC_BASE (ETH_BASE)\r
+#define ETH_MMC_BASE (ETH_BASE + 0x0100)\r
+#define ETH_PTP_BASE (ETH_BASE + 0x0700)\r
+#define ETH_DMA_BASE (ETH_BASE + 0x1000)\r
+\r
+#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */\r
+#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */\r
+#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) /*!< FSMC Bank2 registers base address */\r
+#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) /*!< FSMC Bank3 registers base address */\r
+#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) /*!< FSMC Bank4 registers base address */\r
+\r
+#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @addtogroup Peripheral_declaration\r
+ * @{\r
+ */ \r
+\r
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)\r
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)\r
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)\r
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)\r
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)\r
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)\r
+#define RTC ((RTC_TypeDef *) RTC_BASE)\r
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)\r
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)\r
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)\r
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)\r
+#define USART2 ((USART_TypeDef *) USART2_BASE)\r
+#define USART3 ((USART_TypeDef *) USART3_BASE)\r
+#define UART4 ((USART_TypeDef *) UART4_BASE)\r
+#define UART5 ((USART_TypeDef *) UART5_BASE)\r
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)\r
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)\r
+#define CAN1 ((CAN_TypeDef *) CAN1_BASE)\r
+#define CAN2 ((CAN_TypeDef *) CAN2_BASE)\r
+#define BKP ((BKP_TypeDef *) BKP_BASE)\r
+#define PWR ((PWR_TypeDef *) PWR_BASE)\r
+#define DAC ((DAC_TypeDef *) DAC_BASE)\r
+#define AFIO ((AFIO_TypeDef *) AFIO_BASE)\r
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)\r
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)\r
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)\r
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)\r
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)\r
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)\r
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)\r
+#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)\r
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)\r
+#define ADC2 ((ADC_TypeDef *) ADC2_BASE)\r
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)\r
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)\r
+#define TIM8 ((TIM_TypeDef *) TIM8_BASE)\r
+#define USART1 ((USART_TypeDef *) USART1_BASE)\r
+#define ADC3 ((ADC_TypeDef *) ADC3_BASE)\r
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)\r
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)\r
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)\r
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)\r
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)\r
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)\r
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)\r
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)\r
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)\r
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)\r
+#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)\r
+#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)\r
+#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)\r
+#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)\r
+#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)\r
+#define RCC ((RCC_TypeDef *) RCC_BASE)\r
+#define CRC ((CRC_TypeDef *) CRC_BASE)\r
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)\r
+#define OB ((OB_TypeDef *) OB_BASE) \r
+#define ETH ((ETH_TypeDef *) ETH_BASE)\r
+#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)\r
+#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)\r
+#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)\r
+#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)\r
+#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)\r
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup Exported_constants\r
+ * @{\r
+ */\r
+ \r
+ /** @addtogroup Peripheral_Registers_Bits_Definition\r
+ * @{\r
+ */\r
+ \r
+/******************************************************************************/\r
+/* Peripheral Registers_Bits_Definition */\r
+/******************************************************************************/\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* CRC calculation unit */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for CRC_DR register *********************/\r
+#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */\r
+\r
+\r
+/******************* Bit definition for CRC_IDR register ********************/\r
+#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */\r
+\r
+\r
+/******************** Bit definition for CRC_CR register ********************/\r
+#define CRC_CR_RESET ((uint8_t)0x01) /*!< RESET bit */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Power Control */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************** Bit definition for PWR_CR register ********************/\r
+#define PWR_CR_LPDS ((uint16_t)0x0001) /*!< Low-Power Deepsleep */\r
+#define PWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */\r
+#define PWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */\r
+#define PWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */\r
+#define PWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */\r
+\r
+#define PWR_CR_PLS ((uint16_t)0x00E0) /*!< PLS[2:0] bits (PVD Level Selection) */\r
+#define PWR_CR_PLS_0 ((uint16_t)0x0020) /*!< Bit 0 */\r
+#define PWR_CR_PLS_1 ((uint16_t)0x0040) /*!< Bit 1 */\r
+#define PWR_CR_PLS_2 ((uint16_t)0x0080) /*!< Bit 2 */\r
+\r
+/*!< PVD level configuration */\r
+#define PWR_CR_PLS_2V2 ((uint16_t)0x0000) /*!< PVD level 2.2V */\r
+#define PWR_CR_PLS_2V3 ((uint16_t)0x0020) /*!< PVD level 2.3V */\r
+#define PWR_CR_PLS_2V4 ((uint16_t)0x0040) /*!< PVD level 2.4V */\r
+#define PWR_CR_PLS_2V5 ((uint16_t)0x0060) /*!< PVD level 2.5V */\r
+#define PWR_CR_PLS_2V6 ((uint16_t)0x0080) /*!< PVD level 2.6V */\r
+#define PWR_CR_PLS_2V7 ((uint16_t)0x00A0) /*!< PVD level 2.7V */\r
+#define PWR_CR_PLS_2V8 ((uint16_t)0x00C0) /*!< PVD level 2.8V */\r
+#define PWR_CR_PLS_2V9 ((uint16_t)0x00E0) /*!< PVD level 2.9V */\r
+\r
+#define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */\r
+\r
+\r
+/******************* Bit definition for PWR_CSR register ********************/\r
+#define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */\r
+#define PWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */\r
+#define PWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */\r
+#define PWR_CSR_EWUP ((uint16_t)0x0100) /*!< Enable WKUP pin */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Backup registers */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for BKP_DR1 register ********************/\r
+#define BKP_DR1_D ((uint16_t)0xFFFF) /*!< Backup data */\r
+\r
+/******************* Bit definition for BKP_DR2 register ********************/\r
+#define BKP_DR2_D ((uint16_t)0xFFFF) /*!< Backup data */\r
+\r
+/******************* Bit definition for BKP_DR3 register ********************/\r
+#define BKP_DR3_D ((uint16_t)0xFFFF) /*!< Backup data */\r
+\r
+/******************* Bit definition for BKP_DR4 register ********************/\r
+#define BKP_DR4_D ((uint16_t)0xFFFF) /*!< Backup data */\r
+\r
+/******************* Bit definition for BKP_DR5 register ********************/\r
+#define BKP_DR5_D ((uint16_t)0xFFFF) /*!< Backup data */\r
+\r
+/******************* Bit definition for BKP_DR6 register ********************/\r
+#define BKP_DR6_D ((uint16_t)0xFFFF) /*!< Backup data */\r
+\r
+/******************* Bit definition for BKP_DR7 register ********************/\r
+#define BKP_DR7_D ((uint16_t)0xFFFF) /*!< Backup data */\r
+\r
+/******************* Bit definition for BKP_DR8 register ********************/\r
+#define BKP_DR8_D ((uint16_t)0xFFFF) /*!< Backup data */\r
+\r
+/******************* Bit definition for BKP_DR9 register ********************/\r
+#define BKP_DR9_D ((uint16_t)0xFFFF) /*!< Backup data */\r
+\r
+/******************* Bit definition for BKP_DR10 register *******************/\r
+#define BKP_DR10_D ((uint16_t)0xFFFF) /*!< Backup data */\r
+\r
+/******************* Bit definition for BKP_DR11 register *******************/\r
+#define BKP_DR11_D ((uint16_t)0xFFFF) /*!< Backup data */\r
+\r
+/******************* Bit definition for BKP_DR12 register *******************/\r
+#define BKP_DR12_D ((uint16_t)0xFFFF) /*!< Backup data */\r
+\r
+/******************* Bit definition for BKP_DR13 register *******************/\r
+#define BKP_DR13_D ((uint16_t)0xFFFF) /*!< Backup data */\r
+\r
+/******************* Bit definition for BKP_DR14 register *******************/\r
+#define BKP_DR14_D ((uint16_t)0xFFFF) /*!< Backup data */\r
+\r
+/******************* Bit definition for BKP_DR15 register *******************/\r
+#define BKP_DR15_D ((uint16_t)0xFFFF) /*!< Backup data */\r
+\r
+/******************* Bit definition for BKP_DR16 register *******************/\r
+#define BKP_DR16_D ((uint16_t)0xFFFF) /*!< Backup data */\r
+\r
+/******************* Bit definition for BKP_DR17 register *******************/\r
+#define BKP_DR17_D ((uint16_t)0xFFFF) /*!< Backup data */\r
+\r
+/****************** Bit definition for BKP_DR18 register ********************/\r
+#define BKP_DR18_D ((uint16_t)0xFFFF) /*!< Backup data */\r
+\r
+/******************* Bit definition for BKP_DR19 register *******************/\r
+#define BKP_DR19_D ((uint16_t)0xFFFF) /*!< Backup data */\r
+\r
+/******************* Bit definition for BKP_DR20 register *******************/\r
+#define BKP_DR20_D ((uint16_t)0xFFFF) /*!< Backup data */\r
+\r
+/******************* Bit definition for BKP_DR21 register *******************/\r
+#define BKP_DR21_D ((uint16_t)0xFFFF) /*!< Backup data */\r
+\r
+/******************* Bit definition for BKP_DR22 register *******************/\r
+#define BKP_DR22_D ((uint16_t)0xFFFF) /*!< Backup data */\r
+\r
+/******************* Bit definition for BKP_DR23 register *******************/\r
+#define BKP_DR23_D ((uint16_t)0xFFFF) /*!< Backup data */\r
+\r
+/******************* Bit definition for BKP_DR24 register *******************/\r
+#define BKP_DR24_D ((uint16_t)0xFFFF) /*!< Backup data */\r
+\r
+/******************* Bit definition for BKP_DR25 register *******************/\r
+#define BKP_DR25_D ((uint16_t)0xFFFF) /*!< Backup data */\r
+\r
+/******************* Bit definition for BKP_DR26 register *******************/\r
+#define BKP_DR26_D ((uint16_t)0xFFFF) /*!< Backup data */\r
+\r
+/******************* Bit definition for BKP_DR27 register *******************/\r
+#define BKP_DR27_D ((uint16_t)0xFFFF) /*!< Backup data */\r
+\r
+/******************* Bit definition for BKP_DR28 register *******************/\r
+#define BKP_DR28_D ((uint16_t)0xFFFF) /*!< Backup data */\r
+\r
+/******************* Bit definition for BKP_DR29 register *******************/\r
+#define BKP_DR29_D ((uint16_t)0xFFFF) /*!< Backup data */\r
+\r
+/******************* Bit definition for BKP_DR30 register *******************/\r
+#define BKP_DR30_D ((uint16_t)0xFFFF) /*!< Backup data */\r
+\r
+/******************* Bit definition for BKP_DR31 register *******************/\r
+#define BKP_DR31_D ((uint16_t)0xFFFF) /*!< Backup data */\r
+\r
+/******************* Bit definition for BKP_DR32 register *******************/\r
+#define BKP_DR32_D ((uint16_t)0xFFFF) /*!< Backup data */\r
+\r
+/******************* Bit definition for BKP_DR33 register *******************/\r
+#define BKP_DR33_D ((uint16_t)0xFFFF) /*!< Backup data */\r
+\r
+/******************* Bit definition for BKP_DR34 register *******************/\r
+#define BKP_DR34_D ((uint16_t)0xFFFF) /*!< Backup data */\r
+\r
+/******************* Bit definition for BKP_DR35 register *******************/\r
+#define BKP_DR35_D ((uint16_t)0xFFFF) /*!< Backup data */\r
+\r
+/******************* Bit definition for BKP_DR36 register *******************/\r
+#define BKP_DR36_D ((uint16_t)0xFFFF) /*!< Backup data */\r
+\r
+/******************* Bit definition for BKP_DR37 register *******************/\r
+#define BKP_DR37_D ((uint16_t)0xFFFF) /*!< Backup data */\r
+\r
+/******************* Bit definition for BKP_DR38 register *******************/\r
+#define BKP_DR38_D ((uint16_t)0xFFFF) /*!< Backup data */\r
+\r
+/******************* Bit definition for BKP_DR39 register *******************/\r
+#define BKP_DR39_D ((uint16_t)0xFFFF) /*!< Backup data */\r
+\r
+/******************* Bit definition for BKP_DR40 register *******************/\r
+#define BKP_DR40_D ((uint16_t)0xFFFF) /*!< Backup data */\r
+\r
+/******************* Bit definition for BKP_DR41 register *******************/\r
+#define BKP_DR41_D ((uint16_t)0xFFFF) /*!< Backup data */\r
+\r
+/******************* Bit definition for BKP_DR42 register *******************/\r
+#define BKP_DR42_D ((uint16_t)0xFFFF) /*!< Backup data */\r
+\r
+/****************** Bit definition for BKP_RTCCR register *******************/\r
+#define BKP_RTCCR_CAL ((uint16_t)0x007F) /*!< Calibration value */\r
+#define BKP_RTCCR_CCO ((uint16_t)0x0080) /*!< Calibration Clock Output */\r
+#define BKP_RTCCR_ASOE ((uint16_t)0x0100) /*!< Alarm or Second Output Enable */\r
+#define BKP_RTCCR_ASOS ((uint16_t)0x0200) /*!< Alarm or Second Output Selection */\r
+\r
+/******************** Bit definition for BKP_CR register ********************/\r
+#define BKP_CR_TPE ((uint8_t)0x01) /*!< TAMPER pin enable */\r
+#define BKP_CR_TPAL ((uint8_t)0x02) /*!< TAMPER pin active level */\r
+\r
+/******************* Bit definition for BKP_CSR register ********************/\r
+#define BKP_CSR_CTE ((uint16_t)0x0001) /*!< Clear Tamper event */\r
+#define BKP_CSR_CTI ((uint16_t)0x0002) /*!< Clear Tamper Interrupt */\r
+#define BKP_CSR_TPIE ((uint16_t)0x0004) /*!< TAMPER Pin interrupt enable */\r
+#define BKP_CSR_TEF ((uint16_t)0x0100) /*!< Tamper Event Flag */\r
+#define BKP_CSR_TIF ((uint16_t)0x0200) /*!< Tamper Interrupt Flag */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Reset and Clock Control */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************** Bit definition for RCC_CR register ********************/\r
+#define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */\r
+#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */\r
+#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */\r
+#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */\r
+#define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */\r
+#define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */\r
+#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */\r
+#define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */\r
+#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */\r
+#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */\r
+\r
+#ifdef STM32F10X_CL\r
+ #define RCC_CR_PLL2ON ((uint32_t)0x04000000) /*!< PLL2 enable */\r
+ #define RCC_CR_PLL2RDY ((uint32_t)0x08000000) /*!< PLL2 clock ready flag */\r
+ #define RCC_CR_PLL3ON ((uint32_t)0x10000000) /*!< PLL3 enable */\r
+ #define RCC_CR_PLL3RDY ((uint32_t)0x20000000) /*!< PLL3 clock ready flag */\r
+#endif /* STM32F10X_CL */\r
+\r
+/******************* Bit definition for RCC_CFGR register *******************/\r
+/*!< SW configuration */\r
+#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */\r
+#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+\r
+#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */\r
+#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */\r
+#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */\r
+\r
+/*!< SWS configuration */\r
+#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */\r
+#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */\r
+#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */\r
+\r
+#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */\r
+#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */\r
+#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */\r
+\r
+/*!< HPRE configuration */\r
+#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */\r
+#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */\r
+#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */\r
+#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */\r
+#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */\r
+\r
+#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */\r
+#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */\r
+#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */\r
+#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */\r
+#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */\r
+#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */\r
+#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */\r
+#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */\r
+#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */\r
+\r
+/*!< PPRE1 configuration */\r
+#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */\r
+#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */\r
+#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */\r
+#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */\r
+\r
+#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */\r
+#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */\r
+#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */\r
+#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */\r
+#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */\r
+\r
+/*!< PPRE2 configuration */\r
+#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */\r
+#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */\r
+#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */\r
+#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */\r
+\r
+#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */\r
+#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */\r
+#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */\r
+#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */\r
+#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */\r
+\r
+/*!< ADCPPRE configuration */\r
+#define RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) /*!< ADCPRE[1:0] bits (ADC prescaler) */\r
+#define RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) /*!< Bit 0 */\r
+#define RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) /*!< Bit 1 */\r
+\r
+#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */\r
+#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */\r
+#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */\r
+#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */\r
+\r
+#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */\r
+\r
+#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */\r
+\r
+/*!< PLLMUL configuration */\r
+#define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */\r
+#define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) /*!< Bit 0 */\r
+#define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) /*!< Bit 1 */\r
+#define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) /*!< Bit 2 */\r
+#define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) /*!< Bit 3 */\r
+\r
+#ifdef STM32F10X_CL\r
+ #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */\r
+ #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */\r
+\r
+ #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */\r
+ #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */\r
+\r
+ #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock * 4 */\r
+ #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock * 5 */\r
+ #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock * 6 */\r
+ #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock * 7 */\r
+ #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock * 8 */\r
+ #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock * 9 */\r
+ #define RCC_CFGR_PLLMULL6_5 ((uint32_t)0x00340000) /*!< PLL input clock * 6.5 */\r
+ \r
+ #define RCC_CFGR_OTGFSPRE ((uint32_t)0x00400000) /*!< USB OTG FS prescaler */\r
+ \r
+/*!< MCO configuration */\r
+ #define RCC_CFGR_MCO ((uint32_t)0x0F000000) /*!< MCO[3:0] bits (Microcontroller Clock Output) */\r
+ #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */\r
+ #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */\r
+ #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */\r
+ #define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /*!< Bit 3 */\r
+\r
+ #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */\r
+ #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */\r
+ #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */\r
+ #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */\r
+ #define RCC_CFGR_MCO_PLLCLK_Div2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */\r
+ #define RCC_CFGR_MCO_PLL2CLK ((uint32_t)0x08000000) /*!< PLL2 clock selected as MCO source*/\r
+ #define RCC_CFGR_MCO_PLL3CLK_Div2 ((uint32_t)0x09000000) /*!< PLL3 clock divided by 2 selected as MCO source*/\r
+ #define RCC_CFGR_MCO_Ext_HSE ((uint32_t)0x0A000000) /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */\r
+ #define RCC_CFGR_MCO_PLL3CLK ((uint32_t)0x0B000000) /*!< PLL3 clock selected as MCO source */\r
+#else\r
+ #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */\r
+ #define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE clock selected as PLL entry clock source */\r
+\r
+ #define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */\r
+ #define RCC_CFGR_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */\r
+\r
+ #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */\r
+ #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */\r
+ #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */\r
+ #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */\r
+ #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */\r
+ #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */\r
+ #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */\r
+ #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */\r
+ #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */\r
+ #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */\r
+ #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */\r
+ #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */\r
+ #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */\r
+ #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */\r
+ #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */\r
+ #define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /*!< USB Device prescaler */\r
+\r
+/*!< MCO configuration */\r
+ #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */\r
+ #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */\r
+ #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */\r
+ #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */\r
+\r
+ #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */\r
+ #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */\r
+ #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */\r
+ #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */\r
+ #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */\r
+#endif /* STM32F10X_CL */\r
+\r
+/*!<****************** Bit definition for RCC_CIR register ********************/\r
+#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */\r
+#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */\r
+#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */\r
+#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */\r
+#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */\r
+#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */\r
+#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */\r
+#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */\r
+#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */\r
+#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */\r
+#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */\r
+#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */\r
+#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */\r
+#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */\r
+#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */\r
+#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */\r
+#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */\r
+\r
+#ifdef STM32F10X_CL\r
+ #define RCC_CIR_PLL2RDYF ((uint32_t)0x00000020) /*!< PLL2 Ready Interrupt flag */\r
+ #define RCC_CIR_PLL3RDYF ((uint32_t)0x00000040) /*!< PLL3 Ready Interrupt flag */\r
+ #define RCC_CIR_PLL2RDYIE ((uint32_t)0x00002000) /*!< PLL2 Ready Interrupt Enable */\r
+ #define RCC_CIR_PLL3RDYIE ((uint32_t)0x00004000) /*!< PLL3 Ready Interrupt Enable */\r
+ #define RCC_CIR_PLL2RDYC ((uint32_t)0x00200000) /*!< PLL2 Ready Interrupt Clear */\r
+ #define RCC_CIR_PLL3RDYC ((uint32_t)0x00400000) /*!< PLL3 Ready Interrupt Clear */\r
+#endif /* STM32F10X_CL */\r
+\r
+/***************** Bit definition for RCC_APB2RSTR register *****************/\r
+#define RCC_APB2RSTR_AFIORST ((uint16_t)0x0001) /*!< Alternate Function I/O reset */\r
+#define RCC_APB2RSTR_IOPARST ((uint16_t)0x0004) /*!< I/O port A reset */\r
+#define RCC_APB2RSTR_IOPBRST ((uint16_t)0x0008) /*!< I/O port B reset */\r
+#define RCC_APB2RSTR_IOPCRST ((uint16_t)0x0010) /*!< I/O port C reset */\r
+#define RCC_APB2RSTR_IOPDRST ((uint16_t)0x0020) /*!< I/O port D reset */\r
+#define RCC_APB2RSTR_ADC1RST ((uint16_t)0x0200) /*!< ADC 1 interface reset */\r
+#define RCC_APB2RSTR_ADC2RST ((uint16_t)0x0400) /*!< ADC 2 interface reset */\r
+#define RCC_APB2RSTR_TIM1RST ((uint16_t)0x0800) /*!< TIM1 Timer reset */\r
+#define RCC_APB2RSTR_SPI1RST ((uint16_t)0x1000) /*!< SPI 1 reset */\r
+#define RCC_APB2RSTR_USART1RST ((uint16_t)0x4000) /*!< USART1 reset */\r
+\r
+#ifndef STM32F10X_LD\r
+ #define RCC_APB2RSTR_IOPERST ((uint16_t)0x0040) /*!< I/O port E reset */\r
+#endif /* STM32F10X_HD */\r
+\r
+#ifdef STM32F10X_HD\r
+ #define RCC_APB2RSTR_IOPFRST ((uint16_t)0x0080) /*!< I/O port F reset */\r
+ #define RCC_APB2RSTR_IOPGRST ((uint16_t)0x0100) /*!< I/O port G reset */\r
+ #define RCC_APB2RSTR_TIM8RST ((uint16_t)0x2000) /*!< TIM8 Timer reset */\r
+ #define RCC_APB2RSTR_ADC3RST ((uint16_t)0x8000) /*!< ADC3 interface reset */\r
+#endif /* STM32F10X_HD */\r
+\r
+/***************** Bit definition for RCC_APB1RSTR register *****************/\r
+#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */\r
+#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */\r
+#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */\r
+#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */\r
+#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */\r
+#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) /*!< CAN1 reset */\r
+#define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) /*!< Backup interface reset */\r
+#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */\r
+\r
+#ifndef STM32F10X_LD\r
+ #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */\r
+ #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */\r
+ #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< RUSART 3 reset */\r
+ #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */\r
+#endif /* STM32F10X_HD */\r
+\r
+#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD)\r
+ #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB Device reset */\r
+#endif\r
+\r
+#if defined (STM32F10X_HD) || defined (STM32F10X_CL)\r
+ #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */\r
+ #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */\r
+ #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */\r
+ #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */\r
+ #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */\r
+ #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */\r
+ #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */\r
+#endif\r
+\r
+#ifdef STM32F10X_CL\r
+ #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x08000000) /*!< CAN2 reset */\r
+#endif /* STM32F10X_CL */\r
+\r
+/****************** Bit definition for RCC_AHBENR register ******************/\r
+#define RCC_AHBENR_DMA1EN ((uint16_t)0x0001) /*!< DMA1 clock enable */\r
+#define RCC_AHBENR_SRAMEN ((uint16_t)0x0004) /*!< SRAM interface clock enable */\r
+#define RCC_AHBENR_FLITFEN ((uint16_t)0x0010) /*!< FLITF clock enable */\r
+#define RCC_AHBENR_CRCEN ((uint16_t)0x0040) /*!< CRC clock enable */\r
+\r
+#if defined (STM32F10X_HD) || defined (STM32F10X_CL)\r
+ #define RCC_AHBENR_DMA2EN ((uint16_t)0x0002) /*!< DMA2 clock enable */\r
+#endif\r
+\r
+#ifdef STM32F10X_HD\r
+ #define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */\r
+ #define RCC_AHBENR_SDIOEN ((uint16_t)0x0400) /*!< SDIO clock enable */\r
+#endif /* STM32F10X_HD */\r
+\r
+#ifdef STM32F10X_CL\r
+ #define RCC_AHBENR_OTGFSEN ((uint32_t)0x00001000) /*!< USB OTG FS clock enable */\r
+ #define RCC_AHBENR_ETHMACEN ((uint32_t)0x00004000) /*!< ETHERNET MAC clock enable */\r
+ #define RCC_AHBENR_ETHMACTXEN ((uint32_t)0x00008000) /*!< ETHERNET MAC Tx clock enable */\r
+ #define RCC_AHBENR_ETHMACRXEN ((uint32_t)0x00010000) /*!< ETHERNET MAC Rx clock enable */\r
+#endif /* STM32F10X_CL */\r
+\r
+/****************** Bit definition for RCC_APB2ENR register *****************/\r
+#define RCC_APB2ENR_AFIOEN ((uint16_t)0x0001) /*!< Alternate Function I/O clock enable */\r
+#define RCC_APB2ENR_IOPAEN ((uint16_t)0x0004) /*!< I/O port A clock enable */\r
+#define RCC_APB2ENR_IOPBEN ((uint16_t)0x0008) /*!< I/O port B clock enable */\r
+#define RCC_APB2ENR_IOPCEN ((uint16_t)0x0010) /*!< I/O port C clock enable */\r
+#define RCC_APB2ENR_IOPDEN ((uint16_t)0x0020) /*!< I/O port D clock enable */\r
+#define RCC_APB2ENR_ADC1EN ((uint16_t)0x0200) /*!< ADC 1 interface clock enable */\r
+#define RCC_APB2ENR_ADC2EN ((uint16_t)0x0400) /*!< ADC 2 interface clock enable */\r
+#define RCC_APB2ENR_TIM1EN ((uint16_t)0x0800) /*!< TIM1 Timer clock enable */\r
+#define RCC_APB2ENR_SPI1EN ((uint16_t)0x1000) /*!< SPI 1 clock enable */\r
+#define RCC_APB2ENR_USART1EN ((uint16_t)0x4000) /*!< USART1 clock enable */\r
+\r
+#ifndef STM32F10X_LD\r
+ #define RCC_APB2ENR_IOPEEN ((uint16_t)0x0040) /*!< I/O port E clock enable */\r
+#endif /* STM32F10X_HD */\r
+\r
+#ifdef STM32F10X_HD\r
+ #define RCC_APB2ENR_IOPFEN ((uint16_t)0x0080) /*!< I/O port F clock enable */\r
+ #define RCC_APB2ENR_IOPGEN ((uint16_t)0x0100) /*!< I/O port G clock enable */\r
+ #define RCC_APB2ENR_TIM8EN ((uint16_t)0x2000) /*!< TIM8 Timer clock enable */\r
+ #define RCC_APB2ENR_ADC3EN ((uint16_t)0x8000) /*!< DMA1 clock enable */\r
+#endif /* STM32F10X_HD */\r
+\r
+/***************** Bit definition for RCC_APB1ENR register ******************/\r
+#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/\r
+#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */\r
+#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */\r
+#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */\r
+#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */\r
+#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) /*!< CAN1 clock enable */\r
+#define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) /*!< Backup interface clock enable */\r
+#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */\r
+\r
+#ifndef STM32F10X_LD\r
+ #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */\r
+ #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */\r
+ #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */\r
+ #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */\r
+#endif /* STM32F10X_HD */\r
+\r
+#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD)\r
+ #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB Device clock enable */\r
+#endif\r
+\r
+#if defined (STM32F10X_HD) || defined (STM32F10X_CL)\r
+ #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */\r
+ #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */\r
+ #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */\r
+ #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */\r
+ #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */\r
+ #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */\r
+ #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */\r
+#endif\r
+\r
+#ifdef STM32F10X_CL\r
+ #define RCC_APB1ENR_CAN2EN ((uint32_t)0x08000000) /*!< CAN2 clock enable */\r
+#endif /* STM32F10X_CL */\r
+\r
+/******************* Bit definition for RCC_BDCR register *******************/\r
+#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */\r
+#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */\r
+#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */\r
+\r
+#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */\r
+#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */\r
+#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */\r
+\r
+/*!< RTC congiguration */\r
+#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */\r
+#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */\r
+#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */\r
+#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */\r
+\r
+#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */\r
+#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */\r
+\r
+/******************* Bit definition for RCC_CSR register ********************/ \r
+#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */\r
+#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */\r
+#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */\r
+#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */\r
+#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */\r
+#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */\r
+#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */\r
+#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */\r
+#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */\r
+\r
+#ifdef STM32F10X_CL\r
+/******************* Bit definition for RCC_AHBRSTR register ****************/\r
+ #define RCC_AHBRSTR_OTGFSRST ((uint32_t)0x00001000) /*!< USB OTG FS reset */\r
+ #define RCC_AHBRSTR_ETHMACRST ((uint32_t)0x00004000) /*!< ETHERNET MAC reset */\r
+\r
+/******************* Bit definition for RCC_CFGR2 register ******************/\r
+/*!< PREDIV1 configuration */\r
+ #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */\r
+ #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+ #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+ #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
+ #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */\r
+\r
+ #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */\r
+ #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */\r
+ #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */\r
+ #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */\r
+ #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */\r
+ #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */\r
+ #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */\r
+ #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */\r
+ #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */\r
+ #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */\r
+ #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */\r
+ #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */\r
+ #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */\r
+ #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */\r
+ #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */\r
+ #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */\r
+\r
+/*!< PREDIV2 configuration */\r
+ #define RCC_CFGR2_PREDIV2 ((uint32_t)0x000000F0) /*!< PREDIV2[3:0] bits */\r
+ #define RCC_CFGR2_PREDIV2_0 ((uint32_t)0x00000010) /*!< Bit 0 */\r
+ #define RCC_CFGR2_PREDIV2_1 ((uint32_t)0x00000020) /*!< Bit 1 */\r
+ #define RCC_CFGR2_PREDIV2_2 ((uint32_t)0x00000040) /*!< Bit 2 */\r
+ #define RCC_CFGR2_PREDIV2_3 ((uint32_t)0x00000080) /*!< Bit 3 */\r
+\r
+ #define RCC_CFGR2_PREDIV2_DIV1 ((uint32_t)0x00000000) /*!< PREDIV2 input clock not divided */\r
+ #define RCC_CFGR2_PREDIV2_DIV2 ((uint32_t)0x00000010) /*!< PREDIV2 input clock divided by 2 */\r
+ #define RCC_CFGR2_PREDIV2_DIV3 ((uint32_t)0x00000020) /*!< PREDIV2 input clock divided by 3 */\r
+ #define RCC_CFGR2_PREDIV2_DIV4 ((uint32_t)0x00000030) /*!< PREDIV2 input clock divided by 4 */\r
+ #define RCC_CFGR2_PREDIV2_DIV5 ((uint32_t)0x00000040) /*!< PREDIV2 input clock divided by 5 */\r
+ #define RCC_CFGR2_PREDIV2_DIV6 ((uint32_t)0x00000050) /*!< PREDIV2 input clock divided by 6 */\r
+ #define RCC_CFGR2_PREDIV2_DIV7 ((uint32_t)0x00000060) /*!< PREDIV2 input clock divided by 7 */\r
+ #define RCC_CFGR2_PREDIV2_DIV8 ((uint32_t)0x00000070) /*!< PREDIV2 input clock divided by 8 */\r
+ #define RCC_CFGR2_PREDIV2_DIV9 ((uint32_t)0x00000080) /*!< PREDIV2 input clock divided by 9 */\r
+ #define RCC_CFGR2_PREDIV2_DIV10 ((uint32_t)0x00000090) /*!< PREDIV2 input clock divided by 10 */\r
+ #define RCC_CFGR2_PREDIV2_DIV11 ((uint32_t)0x000000A0) /*!< PREDIV2 input clock divided by 11 */\r
+ #define RCC_CFGR2_PREDIV2_DIV12 ((uint32_t)0x000000B0) /*!< PREDIV2 input clock divided by 12 */\r
+ #define RCC_CFGR2_PREDIV2_DIV13 ((uint32_t)0x000000C0) /*!< PREDIV2 input clock divided by 13 */\r
+ #define RCC_CFGR2_PREDIV2_DIV14 ((uint32_t)0x000000D0) /*!< PREDIV2 input clock divided by 14 */\r
+ #define RCC_CFGR2_PREDIV2_DIV15 ((uint32_t)0x000000E0) /*!< PREDIV2 input clock divided by 15 */\r
+ #define RCC_CFGR2_PREDIV2_DIV16 ((uint32_t)0x000000F0) /*!< PREDIV2 input clock divided by 16 */\r
+\r
+/*!< PLL2MUL configuration */\r
+ #define RCC_CFGR2_PLL2MUL ((uint32_t)0x00000F00) /*!< PLL2MUL[3:0] bits */\r
+ #define RCC_CFGR2_PLL2MUL_0 ((uint32_t)0x00000100) /*!< Bit 0 */\r
+ #define RCC_CFGR2_PLL2MUL_1 ((uint32_t)0x00000200) /*!< Bit 1 */\r
+ #define RCC_CFGR2_PLL2MUL_2 ((uint32_t)0x00000400) /*!< Bit 2 */\r
+ #define RCC_CFGR2_PLL2MUL_3 ((uint32_t)0x00000800) /*!< Bit 3 */\r
+\r
+ #define RCC_CFGR2_PLL2MUL8 ((uint32_t)0x00000600) /*!< PLL2 input clock * 8 */\r
+ #define RCC_CFGR2_PLL2MUL9 ((uint32_t)0x00000700) /*!< PLL2 input clock * 9 */\r
+ #define RCC_CFGR2_PLL2MUL10 ((uint32_t)0x00000800) /*!< PLL2 input clock * 10 */\r
+ #define RCC_CFGR2_PLL2MUL11 ((uint32_t)0x00000900) /*!< PLL2 input clock * 11 */\r
+ #define RCC_CFGR2_PLL2MUL12 ((uint32_t)0x00000A00) /*!< PLL2 input clock * 12 */\r
+ #define RCC_CFGR2_PLL2MUL13 ((uint32_t)0x00000B00) /*!< PLL2 input clock * 13 */\r
+ #define RCC_CFGR2_PLL2MUL14 ((uint32_t)0x00000C00) /*!< PLL2 input clock * 14 */\r
+ #define RCC_CFGR2_PLL2MUL16 ((uint32_t)0x00000E00) /*!< PLL2 input clock * 16 */\r
+ #define RCC_CFGR2_PLL2MUL20 ((uint32_t)0x00000F00) /*!< PLL2 input clock * 20 */\r
+\r
+/*!< PLL3MUL configuration */\r
+ #define RCC_CFGR2_PLL3MUL ((uint32_t)0x0000F000) /*!< PLL3MUL[3:0] bits */\r
+ #define RCC_CFGR2_PLL3MUL_0 ((uint32_t)0x00001000) /*!< Bit 0 */\r
+ #define RCC_CFGR2_PLL3MUL_1 ((uint32_t)0x00002000) /*!< Bit 1 */\r
+ #define RCC_CFGR2_PLL3MUL_2 ((uint32_t)0x00004000) /*!< Bit 2 */\r
+ #define RCC_CFGR2_PLL3MUL_3 ((uint32_t)0x00008000) /*!< Bit 3 */\r
+\r
+ #define RCC_CFGR2_PLL3MUL8 ((uint32_t)0x00006000) /*!< PLL3 input clock * 8 */\r
+ #define RCC_CFGR2_PLL3MUL9 ((uint32_t)0x00007000) /*!< PLL3 input clock * 9 */\r
+ #define RCC_CFGR2_PLL3MUL10 ((uint32_t)0x00008000) /*!< PLL3 input clock * 10 */\r
+ #define RCC_CFGR2_PLL3MUL11 ((uint32_t)0x00009000) /*!< PLL3 input clock * 11 */\r
+ #define RCC_CFGR2_PLL3MUL12 ((uint32_t)0x0000A000) /*!< PLL3 input clock * 12 */\r
+ #define RCC_CFGR2_PLL3MUL13 ((uint32_t)0x0000B000) /*!< PLL3 input clock * 13 */\r
+ #define RCC_CFGR2_PLL3MUL14 ((uint32_t)0x0000C000) /*!< PLL3 input clock * 14 */\r
+ #define RCC_CFGR2_PLL3MUL16 ((uint32_t)0x0000E000) /*!< PLL3 input clock * 16 */\r
+ #define RCC_CFGR2_PLL3MUL20 ((uint32_t)0x0000F000) /*!< PLL3 input clock * 20 */\r
+\r
+ #define RCC_CFGR2_PREDIV1SRC ((uint32_t)0x00010000) /*!< PREDIV1 entry clock source */\r
+ #define RCC_CFGR2_PREDIV1SRC_PLL2 ((uint32_t)0x00010000) /*!< PLL2 selected as PREDIV1 entry clock source */\r
+ #define RCC_CFGR2_PREDIV1SRC_HSE ((uint32_t)0x00000000) /*!< HSE selected as PREDIV1 entry clock source */\r
+ #define RCC_CFGR2_I2S2SRC ((uint32_t)0x00020000) /*!< I2S2 entry clock source */\r
+ #define RCC_CFGR2_I2S3SRC ((uint32_t)0x00040000) /*!< I2S3 clock source */\r
+#endif /* STM32F10X_CL */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* General Purpose and Alternate Function I/O */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for GPIO_CRL register *******************/\r
+#define GPIO_CRL_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */\r
+\r
+#define GPIO_CRL_MODE0 ((uint32_t)0x00000003) /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */\r
+#define GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+\r
+#define GPIO_CRL_MODE1 ((uint32_t)0x00000030) /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */\r
+#define GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) /*!< Bit 0 */\r
+#define GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) /*!< Bit 1 */\r
+\r
+#define GPIO_CRL_MODE2 ((uint32_t)0x00000300) /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */\r
+#define GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) /*!< Bit 0 */\r
+#define GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) /*!< Bit 1 */\r
+\r
+#define GPIO_CRL_MODE3 ((uint32_t)0x00003000) /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */\r
+#define GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) /*!< Bit 0 */\r
+#define GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) /*!< Bit 1 */\r
+\r
+#define GPIO_CRL_MODE4 ((uint32_t)0x00030000) /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */\r
+#define GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) /*!< Bit 0 */\r
+#define GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) /*!< Bit 1 */\r
+\r
+#define GPIO_CRL_MODE5 ((uint32_t)0x00300000) /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */\r
+#define GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) /*!< Bit 0 */\r
+#define GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) /*!< Bit 1 */\r
+\r
+#define GPIO_CRL_MODE6 ((uint32_t)0x03000000) /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */\r
+#define GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) /*!< Bit 0 */\r
+#define GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) /*!< Bit 1 */\r
+\r
+#define GPIO_CRL_MODE7 ((uint32_t)0x30000000) /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */\r
+#define GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) /*!< Bit 0 */\r
+#define GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) /*!< Bit 1 */\r
+\r
+#define GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */\r
+\r
+#define GPIO_CRL_CNF0 ((uint32_t)0x0000000C) /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */\r
+#define GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) /*!< Bit 0 */\r
+#define GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) /*!< Bit 1 */\r
+\r
+#define GPIO_CRL_CNF1 ((uint32_t)0x000000C0) /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */\r
+#define GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) /*!< Bit 0 */\r
+#define GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) /*!< Bit 1 */\r
+\r
+#define GPIO_CRL_CNF2 ((uint32_t)0x00000C00) /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */\r
+#define GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
+#define GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
+\r
+#define GPIO_CRL_CNF3 ((uint32_t)0x0000C000) /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */\r
+#define GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) /*!< Bit 0 */\r
+#define GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) /*!< Bit 1 */\r
+\r
+#define GPIO_CRL_CNF4 ((uint32_t)0x000C0000) /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */\r
+#define GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) /*!< Bit 0 */\r
+#define GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) /*!< Bit 1 */\r
+\r
+#define GPIO_CRL_CNF5 ((uint32_t)0x00C00000) /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */\r
+#define GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) /*!< Bit 0 */\r
+#define GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) /*!< Bit 1 */\r
+\r
+#define GPIO_CRL_CNF6 ((uint32_t)0x0C000000) /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */\r
+#define GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) /*!< Bit 0 */\r
+#define GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) /*!< Bit 1 */\r
+\r
+#define GPIO_CRL_CNF7 ((uint32_t)0xC0000000) /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */\r
+#define GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) /*!< Bit 0 */\r
+#define GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) /*!< Bit 1 */\r
+\r
+/******************* Bit definition for GPIO_CRH register *******************/\r
+#define GPIO_CRH_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */\r
+\r
+#define GPIO_CRH_MODE8 ((uint32_t)0x00000003) /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */\r
+#define GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+\r
+#define GPIO_CRH_MODE9 ((uint32_t)0x00000030) /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */\r
+#define GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) /*!< Bit 0 */\r
+#define GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) /*!< Bit 1 */\r
+\r
+#define GPIO_CRH_MODE10 ((uint32_t)0x00000300) /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */\r
+#define GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) /*!< Bit 0 */\r
+#define GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) /*!< Bit 1 */\r
+\r
+#define GPIO_CRH_MODE11 ((uint32_t)0x00003000) /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */\r
+#define GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) /*!< Bit 0 */\r
+#define GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) /*!< Bit 1 */\r
+\r
+#define GPIO_CRH_MODE12 ((uint32_t)0x00030000) /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */\r
+#define GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) /*!< Bit 0 */\r
+#define GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) /*!< Bit 1 */\r
+\r
+#define GPIO_CRH_MODE13 ((uint32_t)0x00300000) /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */\r
+#define GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) /*!< Bit 0 */\r
+#define GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) /*!< Bit 1 */\r
+\r
+#define GPIO_CRH_MODE14 ((uint32_t)0x03000000) /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */\r
+#define GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) /*!< Bit 0 */\r
+#define GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) /*!< Bit 1 */\r
+\r
+#define GPIO_CRH_MODE15 ((uint32_t)0x30000000) /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */\r
+#define GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) /*!< Bit 0 */\r
+#define GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) /*!< Bit 1 */\r
+\r
+#define GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */\r
+\r
+#define GPIO_CRH_CNF8 ((uint32_t)0x0000000C) /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */\r
+#define GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) /*!< Bit 0 */\r
+#define GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) /*!< Bit 1 */\r
+\r
+#define GPIO_CRH_CNF9 ((uint32_t)0x000000C0) /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */\r
+#define GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) /*!< Bit 0 */\r
+#define GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) /*!< Bit 1 */\r
+\r
+#define GPIO_CRH_CNF10 ((uint32_t)0x00000C00) /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */\r
+#define GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
+#define GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
+\r
+#define GPIO_CRH_CNF11 ((uint32_t)0x0000C000) /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */\r
+#define GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) /*!< Bit 0 */\r
+#define GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) /*!< Bit 1 */\r
+\r
+#define GPIO_CRH_CNF12 ((uint32_t)0x000C0000) /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */\r
+#define GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) /*!< Bit 0 */\r
+#define GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) /*!< Bit 1 */\r
+\r
+#define GPIO_CRH_CNF13 ((uint32_t)0x00C00000) /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */\r
+#define GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) /*!< Bit 0 */\r
+#define GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) /*!< Bit 1 */\r
+\r
+#define GPIO_CRH_CNF14 ((uint32_t)0x0C000000) /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */\r
+#define GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) /*!< Bit 0 */\r
+#define GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) /*!< Bit 1 */\r
+\r
+#define GPIO_CRH_CNF15 ((uint32_t)0xC0000000) /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */\r
+#define GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) /*!< Bit 0 */\r
+#define GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) /*!< Bit 1 */\r
+\r
+/*!<****************** Bit definition for GPIO_IDR register *******************/\r
+#define GPIO_IDR_IDR0 ((uint16_t)0x0001) /*!< Port input data, bit 0 */\r
+#define GPIO_IDR_IDR1 ((uint16_t)0x0002) /*!< Port input data, bit 1 */\r
+#define GPIO_IDR_IDR2 ((uint16_t)0x0004) /*!< Port input data, bit 2 */\r
+#define GPIO_IDR_IDR3 ((uint16_t)0x0008) /*!< Port input data, bit 3 */\r
+#define GPIO_IDR_IDR4 ((uint16_t)0x0010) /*!< Port input data, bit 4 */\r
+#define GPIO_IDR_IDR5 ((uint16_t)0x0020) /*!< Port input data, bit 5 */\r
+#define GPIO_IDR_IDR6 ((uint16_t)0x0040) /*!< Port input data, bit 6 */\r
+#define GPIO_IDR_IDR7 ((uint16_t)0x0080) /*!< Port input data, bit 7 */\r
+#define GPIO_IDR_IDR8 ((uint16_t)0x0100) /*!< Port input data, bit 8 */\r
+#define GPIO_IDR_IDR9 ((uint16_t)0x0200) /*!< Port input data, bit 9 */\r
+#define GPIO_IDR_IDR10 ((uint16_t)0x0400) /*!< Port input data, bit 10 */\r
+#define GPIO_IDR_IDR11 ((uint16_t)0x0800) /*!< Port input data, bit 11 */\r
+#define GPIO_IDR_IDR12 ((uint16_t)0x1000) /*!< Port input data, bit 12 */\r
+#define GPIO_IDR_IDR13 ((uint16_t)0x2000) /*!< Port input data, bit 13 */\r
+#define GPIO_IDR_IDR14 ((uint16_t)0x4000) /*!< Port input data, bit 14 */\r
+#define GPIO_IDR_IDR15 ((uint16_t)0x8000) /*!< Port input data, bit 15 */\r
+\r
+/******************* Bit definition for GPIO_ODR register *******************/\r
+#define GPIO_ODR_ODR0 ((uint16_t)0x0001) /*!< Port output data, bit 0 */\r
+#define GPIO_ODR_ODR1 ((uint16_t)0x0002) /*!< Port output data, bit 1 */\r
+#define GPIO_ODR_ODR2 ((uint16_t)0x0004) /*!< Port output data, bit 2 */\r
+#define GPIO_ODR_ODR3 ((uint16_t)0x0008) /*!< Port output data, bit 3 */\r
+#define GPIO_ODR_ODR4 ((uint16_t)0x0010) /*!< Port output data, bit 4 */\r
+#define GPIO_ODR_ODR5 ((uint16_t)0x0020) /*!< Port output data, bit 5 */\r
+#define GPIO_ODR_ODR6 ((uint16_t)0x0040) /*!< Port output data, bit 6 */\r
+#define GPIO_ODR_ODR7 ((uint16_t)0x0080) /*!< Port output data, bit 7 */\r
+#define GPIO_ODR_ODR8 ((uint16_t)0x0100) /*!< Port output data, bit 8 */\r
+#define GPIO_ODR_ODR9 ((uint16_t)0x0200) /*!< Port output data, bit 9 */\r
+#define GPIO_ODR_ODR10 ((uint16_t)0x0400) /*!< Port output data, bit 10 */\r
+#define GPIO_ODR_ODR11 ((uint16_t)0x0800) /*!< Port output data, bit 11 */\r
+#define GPIO_ODR_ODR12 ((uint16_t)0x1000) /*!< Port output data, bit 12 */\r
+#define GPIO_ODR_ODR13 ((uint16_t)0x2000) /*!< Port output data, bit 13 */\r
+#define GPIO_ODR_ODR14 ((uint16_t)0x4000) /*!< Port output data, bit 14 */\r
+#define GPIO_ODR_ODR15 ((uint16_t)0x8000) /*!< Port output data, bit 15 */\r
+\r
+/****************** Bit definition for GPIO_BSRR register *******************/\r
+#define GPIO_BSRR_BS0 ((uint32_t)0x00000001) /*!< Port x Set bit 0 */\r
+#define GPIO_BSRR_BS1 ((uint32_t)0x00000002) /*!< Port x Set bit 1 */\r
+#define GPIO_BSRR_BS2 ((uint32_t)0x00000004) /*!< Port x Set bit 2 */\r
+#define GPIO_BSRR_BS3 ((uint32_t)0x00000008) /*!< Port x Set bit 3 */\r
+#define GPIO_BSRR_BS4 ((uint32_t)0x00000010) /*!< Port x Set bit 4 */\r
+#define GPIO_BSRR_BS5 ((uint32_t)0x00000020) /*!< Port x Set bit 5 */\r
+#define GPIO_BSRR_BS6 ((uint32_t)0x00000040) /*!< Port x Set bit 6 */\r
+#define GPIO_BSRR_BS7 ((uint32_t)0x00000080) /*!< Port x Set bit 7 */\r
+#define GPIO_BSRR_BS8 ((uint32_t)0x00000100) /*!< Port x Set bit 8 */\r
+#define GPIO_BSRR_BS9 ((uint32_t)0x00000200) /*!< Port x Set bit 9 */\r
+#define GPIO_BSRR_BS10 ((uint32_t)0x00000400) /*!< Port x Set bit 10 */\r
+#define GPIO_BSRR_BS11 ((uint32_t)0x00000800) /*!< Port x Set bit 11 */\r
+#define GPIO_BSRR_BS12 ((uint32_t)0x00001000) /*!< Port x Set bit 12 */\r
+#define GPIO_BSRR_BS13 ((uint32_t)0x00002000) /*!< Port x Set bit 13 */\r
+#define GPIO_BSRR_BS14 ((uint32_t)0x00004000) /*!< Port x Set bit 14 */\r
+#define GPIO_BSRR_BS15 ((uint32_t)0x00008000) /*!< Port x Set bit 15 */\r
+\r
+#define GPIO_BSRR_BR0 ((uint32_t)0x00010000) /*!< Port x Reset bit 0 */\r
+#define GPIO_BSRR_BR1 ((uint32_t)0x00020000) /*!< Port x Reset bit 1 */\r
+#define GPIO_BSRR_BR2 ((uint32_t)0x00040000) /*!< Port x Reset bit 2 */\r
+#define GPIO_BSRR_BR3 ((uint32_t)0x00080000) /*!< Port x Reset bit 3 */\r
+#define GPIO_BSRR_BR4 ((uint32_t)0x00100000) /*!< Port x Reset bit 4 */\r
+#define GPIO_BSRR_BR5 ((uint32_t)0x00200000) /*!< Port x Reset bit 5 */\r
+#define GPIO_BSRR_BR6 ((uint32_t)0x00400000) /*!< Port x Reset bit 6 */\r
+#define GPIO_BSRR_BR7 ((uint32_t)0x00800000) /*!< Port x Reset bit 7 */\r
+#define GPIO_BSRR_BR8 ((uint32_t)0x01000000) /*!< Port x Reset bit 8 */\r
+#define GPIO_BSRR_BR9 ((uint32_t)0x02000000) /*!< Port x Reset bit 9 */\r
+#define GPIO_BSRR_BR10 ((uint32_t)0x04000000) /*!< Port x Reset bit 10 */\r
+#define GPIO_BSRR_BR11 ((uint32_t)0x08000000) /*!< Port x Reset bit 11 */\r
+#define GPIO_BSRR_BR12 ((uint32_t)0x10000000) /*!< Port x Reset bit 12 */\r
+#define GPIO_BSRR_BR13 ((uint32_t)0x20000000) /*!< Port x Reset bit 13 */\r
+#define GPIO_BSRR_BR14 ((uint32_t)0x40000000) /*!< Port x Reset bit 14 */\r
+#define GPIO_BSRR_BR15 ((uint32_t)0x80000000) /*!< Port x Reset bit 15 */\r
+\r
+/******************* Bit definition for GPIO_BRR register *******************/\r
+#define GPIO_BRR_BR0 ((uint16_t)0x0001) /*!< Port x Reset bit 0 */\r
+#define GPIO_BRR_BR1 ((uint16_t)0x0002) /*!< Port x Reset bit 1 */\r
+#define GPIO_BRR_BR2 ((uint16_t)0x0004) /*!< Port x Reset bit 2 */\r
+#define GPIO_BRR_BR3 ((uint16_t)0x0008) /*!< Port x Reset bit 3 */\r
+#define GPIO_BRR_BR4 ((uint16_t)0x0010) /*!< Port x Reset bit 4 */\r
+#define GPIO_BRR_BR5 ((uint16_t)0x0020) /*!< Port x Reset bit 5 */\r
+#define GPIO_BRR_BR6 ((uint16_t)0x0040) /*!< Port x Reset bit 6 */\r
+#define GPIO_BRR_BR7 ((uint16_t)0x0080) /*!< Port x Reset bit 7 */\r
+#define GPIO_BRR_BR8 ((uint16_t)0x0100) /*!< Port x Reset bit 8 */\r
+#define GPIO_BRR_BR9 ((uint16_t)0x0200) /*!< Port x Reset bit 9 */\r
+#define GPIO_BRR_BR10 ((uint16_t)0x0400) /*!< Port x Reset bit 10 */\r
+#define GPIO_BRR_BR11 ((uint16_t)0x0800) /*!< Port x Reset bit 11 */\r
+#define GPIO_BRR_BR12 ((uint16_t)0x1000) /*!< Port x Reset bit 12 */\r
+#define GPIO_BRR_BR13 ((uint16_t)0x2000) /*!< Port x Reset bit 13 */\r
+#define GPIO_BRR_BR14 ((uint16_t)0x4000) /*!< Port x Reset bit 14 */\r
+#define GPIO_BRR_BR15 ((uint16_t)0x8000) /*!< Port x Reset bit 15 */\r
+\r
+/****************** Bit definition for GPIO_LCKR register *******************/\r
+#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) /*!< Port x Lock bit 0 */\r
+#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) /*!< Port x Lock bit 1 */\r
+#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) /*!< Port x Lock bit 2 */\r
+#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) /*!< Port x Lock bit 3 */\r
+#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) /*!< Port x Lock bit 4 */\r
+#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) /*!< Port x Lock bit 5 */\r
+#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) /*!< Port x Lock bit 6 */\r
+#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) /*!< Port x Lock bit 7 */\r
+#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) /*!< Port x Lock bit 8 */\r
+#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) /*!< Port x Lock bit 9 */\r
+#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) /*!< Port x Lock bit 10 */\r
+#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) /*!< Port x Lock bit 11 */\r
+#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) /*!< Port x Lock bit 12 */\r
+#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) /*!< Port x Lock bit 13 */\r
+#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) /*!< Port x Lock bit 14 */\r
+#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) /*!< Port x Lock bit 15 */\r
+#define GPIO_LCKR_LCKK ((uint32_t)0x00010000) /*!< Lock key */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+/****************** Bit definition for AFIO_EVCR register *******************/\r
+#define AFIO_EVCR_PIN ((uint8_t)0x0F) /*!< PIN[3:0] bits (Pin selection) */\r
+#define AFIO_EVCR_PIN_0 ((uint8_t)0x01) /*!< Bit 0 */\r
+#define AFIO_EVCR_PIN_1 ((uint8_t)0x02) /*!< Bit 1 */\r
+#define AFIO_EVCR_PIN_2 ((uint8_t)0x04) /*!< Bit 2 */\r
+#define AFIO_EVCR_PIN_3 ((uint8_t)0x08) /*!< Bit 3 */\r
+\r
+/*!< PIN configuration */\r
+#define AFIO_EVCR_PIN_PX0 ((uint8_t)0x00) /*!< Pin 0 selected */\r
+#define AFIO_EVCR_PIN_PX1 ((uint8_t)0x01) /*!< Pin 1 selected */\r
+#define AFIO_EVCR_PIN_PX2 ((uint8_t)0x02) /*!< Pin 2 selected */\r
+#define AFIO_EVCR_PIN_PX3 ((uint8_t)0x03) /*!< Pin 3 selected */\r
+#define AFIO_EVCR_PIN_PX4 ((uint8_t)0x04) /*!< Pin 4 selected */\r
+#define AFIO_EVCR_PIN_PX5 ((uint8_t)0x05) /*!< Pin 5 selected */\r
+#define AFIO_EVCR_PIN_PX6 ((uint8_t)0x06) /*!< Pin 6 selected */\r
+#define AFIO_EVCR_PIN_PX7 ((uint8_t)0x07) /*!< Pin 7 selected */\r
+#define AFIO_EVCR_PIN_PX8 ((uint8_t)0x08) /*!< Pin 8 selected */\r
+#define AFIO_EVCR_PIN_PX9 ((uint8_t)0x09) /*!< Pin 9 selected */\r
+#define AFIO_EVCR_PIN_PX10 ((uint8_t)0x0A) /*!< Pin 10 selected */\r
+#define AFIO_EVCR_PIN_PX11 ((uint8_t)0x0B) /*!< Pin 11 selected */\r
+#define AFIO_EVCR_PIN_PX12 ((uint8_t)0x0C) /*!< Pin 12 selected */\r
+#define AFIO_EVCR_PIN_PX13 ((uint8_t)0x0D) /*!< Pin 13 selected */\r
+#define AFIO_EVCR_PIN_PX14 ((uint8_t)0x0E) /*!< Pin 14 selected */\r
+#define AFIO_EVCR_PIN_PX15 ((uint8_t)0x0F) /*!< Pin 15 selected */\r
+\r
+#define AFIO_EVCR_PORT ((uint8_t)0x70) /*!< PORT[2:0] bits (Port selection) */\r
+#define AFIO_EVCR_PORT_0 ((uint8_t)0x10) /*!< Bit 0 */\r
+#define AFIO_EVCR_PORT_1 ((uint8_t)0x20) /*!< Bit 1 */\r
+#define AFIO_EVCR_PORT_2 ((uint8_t)0x40) /*!< Bit 2 */\r
+\r
+/*!< PORT configuration */\r
+#define AFIO_EVCR_PORT_PA ((uint8_t)0x00) /*!< Port A selected */\r
+#define AFIO_EVCR_PORT_PB ((uint8_t)0x10) /*!< Port B selected */\r
+#define AFIO_EVCR_PORT_PC ((uint8_t)0x20) /*!< Port C selected */\r
+#define AFIO_EVCR_PORT_PD ((uint8_t)0x30) /*!< Port D selected */\r
+#define AFIO_EVCR_PORT_PE ((uint8_t)0x40) /*!< Port E selected */\r
+\r
+#define AFIO_EVCR_EVOE ((uint8_t)0x80) /*!< Event Output Enable */\r
+\r
+/****************** Bit definition for AFIO_MAPR register *******************/\r
+#define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) /*!< SPI1 remapping */\r
+#define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) /*!< I2C1 remapping */\r
+#define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) /*!< USART1 remapping */\r
+#define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) /*!< USART2 remapping */\r
+\r
+#define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) /*!< USART3_REMAP[1:0] bits (USART3 remapping) */\r
+#define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) /*!< Bit 0 */\r
+#define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) /*!< Bit 1 */\r
+\r
+/* USART3_REMAP configuration */\r
+#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */\r
+#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */\r
+#define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */\r
+\r
+#define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */\r
+#define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) /*!< Bit 0 */\r
+#define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) /*!< Bit 1 */\r
+\r
+/*!< TIM1_REMAP configuration */\r
+#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */\r
+#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */\r
+#define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */\r
+\r
+#define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */\r
+#define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) /*!< Bit 0 */\r
+#define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) /*!< Bit 1 */\r
+\r
+/*!< TIM2_REMAP configuration */\r
+#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */\r
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */\r
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */\r
+#define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */\r
+\r
+#define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */\r
+#define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
+#define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
+\r
+/*!< TIM3_REMAP configuration */\r
+#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */\r
+#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */\r
+#define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */\r
+\r
+#define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) /*!< TIM4_REMAP bit (TIM4 remapping) */\r
+\r
+#define AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000) /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */\r
+#define AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000) /*!< Bit 0 */\r
+#define AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000) /*!< Bit 1 */\r
+\r
+/*!< CAN_REMAP configuration */\r
+#define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /*!< CANRX mapped to PA11, CANTX mapped to PA12 */\r
+#define AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) /*!< CANRX mapped to PB8, CANTX mapped to PB9 */\r
+#define AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) /*!< CANRX mapped to PD0, CANTX mapped to PD1 */\r
+\r
+#define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */\r
+#define AFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000) /*!< TIM5 Channel4 Internal Remap */\r
+#define AFIO_MAPR_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) /*!< ADC 1 External Trigger Injected Conversion remapping */\r
+#define AFIO_MAPR_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) /*!< ADC 1 External Trigger Regular Conversion remapping */\r
+#define AFIO_MAPR_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) /*!< ADC 2 External Trigger Injected Conversion remapping */\r
+#define AFIO_MAPR_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) /*!< ADC 2 External Trigger Regular Conversion remapping */\r
+\r
+/*!< SWJ_CFG configuration */\r
+#define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */\r
+#define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) /*!< Bit 0 */\r
+#define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) /*!< Bit 1 */\r
+#define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) /*!< Bit 2 */\r
+\r
+#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */\r
+#define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */\r
+#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /*!< JTAG-DP Disabled and SW-DP Enabled */\r
+#define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /*!< JTAG-DP Disabled and SW-DP Disabled */\r
+\r
+#ifdef STM32F10X_CL\r
+/*!< ETH_REMAP configuration */\r
+ #define AFIO_MAPR_ETH_REMAP ((uint32_t)0x00200000) /*!< SPI3_REMAP bit (Ethernet MAC I/O remapping) */\r
+\r
+/*!< CAN2_REMAP configuration */\r
+ #define AFIO_MAPR_CAN2_REMAP ((uint32_t)0x00400000) /*!< CAN2_REMAP bit (CAN2 I/O remapping) */\r
+\r
+/*!< MII_RMII_SEL configuration */\r
+ #define AFIO_MAPR_MII_RMII_SEL ((uint32_t)0x00800000) /*!< MII_RMII_SEL bit (Ethernet MII or RMII selection) */\r
+\r
+/*!< SPI3_REMAP configuration */\r
+ #define AFIO_MAPR_SPI3_REMAP ((uint32_t)0x10000000) /*!< SPI3_REMAP bit (SPI3 remapping) */\r
+\r
+/*!< TIM2ITR1_IREMAP configuration */\r
+ #define AFIO_MAPR_TIM2ITR1_IREMAP ((uint32_t)0x20000000) /*!< TIM2ITR1_IREMAP bit (TIM2 internal trigger 1 remapping) */\r
+\r
+/*!< PTP_PPS_REMAP configuration */\r
+ #define AFIO_MAPR_PTP_PPS_REMAP ((uint32_t)0x20000000) /*!< PTP_PPS_REMAP bit (Ethernet PTP PPS remapping) */\r
+#endif\r
+\r
+/***************** Bit definition for AFIO_EXTICR1 register *****************/\r
+#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */\r
+#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */\r
+#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */\r
+#define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */\r
+\r
+/*!< EXTI0 configuration */\r
+#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */\r
+#define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */\r
+#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */\r
+#define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */\r
+#define AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */\r
+#define AFIO_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */\r
+#define AFIO_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /*!< PG[0] pin */\r
+\r
+/*!< EXTI1 configuration */\r
+#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */\r
+#define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */\r
+#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */\r
+#define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */\r
+#define AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */\r
+#define AFIO_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */\r
+#define AFIO_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /*!< PG[1] pin */\r
+\r
+/*!< EXTI2 configuration */ \r
+#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */\r
+#define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */\r
+#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */\r
+#define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */\r
+#define AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */\r
+#define AFIO_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */\r
+#define AFIO_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /*!< PG[2] pin */\r
+\r
+/*!< EXTI3 configuration */\r
+#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */\r
+#define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */\r
+#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */\r
+#define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */\r
+#define AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */\r
+#define AFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */\r
+#define AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /*!< PG[3] pin */\r
+\r
+/***************** Bit definition for AFIO_EXTICR2 register *****************/\r
+#define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */\r
+#define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */\r
+#define AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */\r
+#define AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */\r
+\r
+/*!< EXTI4 configuration */\r
+#define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */\r
+#define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */\r
+#define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */\r
+#define AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */\r
+#define AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */\r
+#define AFIO_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */\r
+#define AFIO_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /*!< PG[4] pin */\r
+\r
+/* EXTI5 configuration */\r
+#define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */\r
+#define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */\r
+#define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */\r
+#define AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */\r
+#define AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */\r
+#define AFIO_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */\r
+#define AFIO_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /*!< PG[5] pin */\r
+\r
+/*!< EXTI6 configuration */ \r
+#define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */\r
+#define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */\r
+#define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */\r
+#define AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */\r
+#define AFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */\r
+#define AFIO_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */\r
+#define AFIO_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /*!< PG[6] pin */\r
+\r
+/*!< EXTI7 configuration */\r
+#define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */\r
+#define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */\r
+#define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */\r
+#define AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */\r
+#define AFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */\r
+#define AFIO_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */\r
+#define AFIO_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /*!< PG[7] pin */\r
+\r
+/***************** Bit definition for AFIO_EXTICR3 register *****************/\r
+#define AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */\r
+#define AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */\r
+#define AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */\r
+#define AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */\r
+\r
+/*!< EXTI8 configuration */\r
+#define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */\r
+#define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */\r
+#define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */\r
+#define AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */\r
+#define AFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */\r
+#define AFIO_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!< PF[8] pin */\r
+#define AFIO_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /*!< PG[8] pin */\r
+\r
+/*!< EXTI9 configuration */\r
+#define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */\r
+#define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */\r
+#define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */\r
+#define AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */\r
+#define AFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */\r
+#define AFIO_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */\r
+#define AFIO_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /*!< PG[9] pin */\r
+\r
+/*!< EXTI10 configuration */ \r
+#define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */\r
+#define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */\r
+#define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */\r
+#define AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */\r
+#define AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PE[10] pin */\r
+#define AFIO_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */\r
+#define AFIO_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /*!< PG[10] pin */\r
+\r
+/*!< EXTI11 configuration */\r
+#define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */\r
+#define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */\r
+#define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */\r
+#define AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */\r
+#define AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */\r
+#define AFIO_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!< PF[11] pin */\r
+#define AFIO_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /*!< PG[11] pin */\r
+\r
+/***************** Bit definition for AFIO_EXTICR4 register *****************/\r
+#define AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */\r
+#define AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */\r
+#define AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */\r
+#define AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */\r
+\r
+/* EXTI12 configuration */\r
+#define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */\r
+#define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */\r
+#define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */\r
+#define AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */\r
+#define AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */\r
+#define AFIO_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!< PF[12] pin */\r
+#define AFIO_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /*!< PG[12] pin */\r
+\r
+/* EXTI13 configuration */\r
+#define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */\r
+#define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */\r
+#define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */\r
+#define AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */\r
+#define AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */\r
+#define AFIO_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!< PF[13] pin */\r
+#define AFIO_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /*!< PG[13] pin */\r
+\r
+/*!< EXTI14 configuration */ \r
+#define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */\r
+#define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */\r
+#define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */\r
+#define AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */\r
+#define AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */\r
+#define AFIO_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!< PF[14] pin */\r
+#define AFIO_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /*!< PG[14] pin */\r
+\r
+/*!< EXTI15 configuration */\r
+#define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */\r
+#define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */\r
+#define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */\r
+#define AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */\r
+#define AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */\r
+#define AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!< PF[15] pin */\r
+#define AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /*!< PG[15] pin */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* SystemTick */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/***************** Bit definition for SysTick_CTRL register *****************/\r
+#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */\r
+#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */\r
+#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */\r
+#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */\r
+\r
+/***************** Bit definition for SysTick_LOAD register *****************/\r
+#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */\r
+\r
+/***************** Bit definition for SysTick_VAL register ******************/\r
+#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */\r
+\r
+/***************** Bit definition for SysTick_CALIB register ****************/\r
+#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */\r
+#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */\r
+#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Nested Vectored Interrupt Controller */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/****************** Bit definition for NVIC_ISER register *******************/\r
+#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */\r
+#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */\r
+#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */\r
+#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */\r
+#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */\r
+#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */\r
+#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */\r
+#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */\r
+#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */\r
+#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */\r
+#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */\r
+#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */\r
+#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */\r
+#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */\r
+#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */\r
+#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */\r
+#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */\r
+#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */\r
+#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */\r
+#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */\r
+#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */\r
+#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */\r
+#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */\r
+#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */\r
+#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */\r
+#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */\r
+#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */\r
+#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */\r
+#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */\r
+#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */\r
+#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */\r
+#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */\r
+#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */\r
+\r
+/****************** Bit definition for NVIC_ICER register *******************/\r
+#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */\r
+#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */\r
+#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */\r
+#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */\r
+#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */\r
+#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */\r
+#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */\r
+#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */\r
+#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */\r
+#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */\r
+#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */\r
+#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */\r
+#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */\r
+#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */\r
+#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */\r
+#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */\r
+#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */\r
+#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */\r
+#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */\r
+#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */\r
+#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */\r
+#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */\r
+#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */\r
+#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */\r
+#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */\r
+#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */\r
+#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */\r
+#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */\r
+#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */\r
+#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */\r
+#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */\r
+#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */\r
+#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */\r
+\r
+/****************** Bit definition for NVIC_ISPR register *******************/\r
+#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */\r
+#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */\r
+#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */\r
+#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */\r
+#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */\r
+#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */\r
+#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */\r
+#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */\r
+#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */\r
+#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */\r
+#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */\r
+#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */\r
+#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */\r
+#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */\r
+#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */\r
+#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */\r
+#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */\r
+#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */\r
+#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */\r
+#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */\r
+#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */\r
+#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */\r
+#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */\r
+#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */\r
+#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */\r
+#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */\r
+#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */\r
+#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */\r
+#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */\r
+#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */\r
+#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */\r
+#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */\r
+#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */\r
+\r
+/****************** Bit definition for NVIC_ICPR register *******************/\r
+#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */\r
+#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */\r
+#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */\r
+#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */\r
+#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */\r
+#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */\r
+#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */\r
+#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */\r
+#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */\r
+#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */\r
+#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */\r
+#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */\r
+#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */\r
+#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */\r
+#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */\r
+#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */\r
+#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */\r
+#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */\r
+#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */\r
+#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */\r
+#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */\r
+#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */\r
+#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */\r
+#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */\r
+#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */\r
+#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */\r
+#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */\r
+#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */\r
+#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */\r
+#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */\r
+#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */\r
+#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */\r
+#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */\r
+\r
+/****************** Bit definition for NVIC_IABR register *******************/\r
+#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */\r
+#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */\r
+#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */\r
+#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */\r
+#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */\r
+#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */\r
+#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */\r
+#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */\r
+#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */\r
+#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */\r
+#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */\r
+#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */\r
+#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */\r
+#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */\r
+#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */\r
+#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */\r
+#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */\r
+#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */\r
+#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */\r
+#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */\r
+#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */\r
+#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */\r
+#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */\r
+#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */\r
+#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */\r
+#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */\r
+#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */\r
+#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */\r
+#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */\r
+#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */\r
+#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */\r
+#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */\r
+#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */\r
+\r
+/****************** Bit definition for NVIC_PRI0 register *******************/\r
+#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */\r
+#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */\r
+#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */\r
+#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */\r
+\r
+/****************** Bit definition for NVIC_PRI1 register *******************/\r
+#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */\r
+#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */\r
+#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */\r
+#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */\r
+\r
+/****************** Bit definition for NVIC_PRI2 register *******************/\r
+#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */\r
+#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */\r
+#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */\r
+#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */\r
+\r
+/****************** Bit definition for NVIC_PRI3 register *******************/\r
+#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */\r
+#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */\r
+#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */\r
+#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */\r
+\r
+/****************** Bit definition for NVIC_PRI4 register *******************/\r
+#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */\r
+#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */\r
+#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */\r
+#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */\r
+\r
+/****************** Bit definition for NVIC_PRI5 register *******************/\r
+#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */\r
+#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */\r
+#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */\r
+#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */\r
+\r
+/****************** Bit definition for NVIC_PRI6 register *******************/\r
+#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */\r
+#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */\r
+#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */\r
+#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */\r
+\r
+/****************** Bit definition for NVIC_PRI7 register *******************/\r
+#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */\r
+#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */\r
+#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */\r
+#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */\r
+\r
+/****************** Bit definition for SCB_CPUID register *******************/\r
+#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */\r
+#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */\r
+#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */\r
+#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */\r
+#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */\r
+\r
+/******************* Bit definition for SCB_ICSR register *******************/\r
+#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */\r
+#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */\r
+#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */\r
+#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */\r
+#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */\r
+#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */\r
+#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */\r
+#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */\r
+#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */\r
+#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */\r
+\r
+/******************* Bit definition for SCB_VTOR register *******************/\r
+#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */\r
+#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */\r
+\r
+/*!<***************** Bit definition for SCB_AIRCR register *******************/\r
+#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */\r
+#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */\r
+#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */\r
+\r
+#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */\r
+#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */\r
+#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */\r
+#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */\r
+\r
+/* prority group configuration */\r
+#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */\r
+#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */\r
+#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */\r
+#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */\r
+#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */\r
+#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */\r
+#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */\r
+#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */\r
+\r
+#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */\r
+#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */\r
+\r
+/******************* Bit definition for SCB_SCR register ********************/\r
+#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< Sleep on exit bit */\r
+#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< Sleep deep bit */\r
+#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< Wake up from WFE */\r
+\r
+/******************** Bit definition for SCB_CCR register *******************/\r
+#define SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */\r
+#define SCB_CCR_USERSETMPEND ((uint16_t)0x0002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */\r
+#define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) /*!< Trap for unaligned access */\r
+#define SCB_CCR_DIV_0_TRP ((uint16_t)0x0010) /*!< Trap on Divide by 0 */\r
+#define SCB_CCR_BFHFNMIGN ((uint16_t)0x0100) /*!< Handlers running at priority -1 and -2 */\r
+#define SCB_CCR_STKALIGN ((uint16_t)0x0200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */\r
+\r
+/******************* Bit definition for SCB_SHPR register ********************/\r
+#define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */\r
+#define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */\r
+#define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */\r
+#define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */\r
+\r
+/****************** Bit definition for SCB_SHCSR register *******************/\r
+#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */\r
+#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */\r
+#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */\r
+#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */\r
+#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */\r
+#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */\r
+#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */\r
+#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */\r
+#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */\r
+#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */\r
+#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */\r
+#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */\r
+#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */\r
+#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */\r
+\r
+/******************* Bit definition for SCB_CFSR register *******************/\r
+/*!< MFSR */\r
+#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */\r
+#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */\r
+#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */\r
+#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */\r
+#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */\r
+/*!< BFSR */\r
+#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */\r
+#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */\r
+#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */\r
+#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */\r
+#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */\r
+#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */\r
+/*!< UFSR */\r
+#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to excecute an undefined instruction */\r
+#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */\r
+#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */\r
+#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */\r
+#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */\r
+#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */\r
+\r
+/******************* Bit definition for SCB_HFSR register *******************/\r
+#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occures because of vector table read on exception processing */\r
+#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */\r
+#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */\r
+\r
+/******************* Bit definition for SCB_DFSR register *******************/\r
+#define SCB_DFSR_HALTED ((uint8_t)0x01) /*!< Halt request flag */\r
+#define SCB_DFSR_BKPT ((uint8_t)0x02) /*!< BKPT flag */\r
+#define SCB_DFSR_DWTTRAP ((uint8_t)0x04) /*!< Data Watchpoint and Trace (DWT) flag */\r
+#define SCB_DFSR_VCATCH ((uint8_t)0x08) /*!< Vector catch flag */\r
+#define SCB_DFSR_EXTERNAL ((uint8_t)0x10) /*!< External debug request flag */\r
+\r
+/******************* Bit definition for SCB_MMFAR register ******************/\r
+#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */\r
+\r
+/******************* Bit definition for SCB_BFAR register *******************/\r
+#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */\r
+\r
+/******************* Bit definition for SCB_afsr register *******************/\r
+#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* External Interrupt/Event Controller */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for EXTI_IMR register *******************/\r
+#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */\r
+#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */\r
+#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */\r
+#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */\r
+#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */\r
+#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */\r
+#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */\r
+#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */\r
+#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */\r
+#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */\r
+#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */\r
+#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */\r
+#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */\r
+#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */\r
+#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */\r
+#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */\r
+#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */\r
+#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */\r
+#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */\r
+#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */\r
+\r
+/******************* Bit definition for EXTI_EMR register *******************/\r
+#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */\r
+#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */\r
+#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */\r
+#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */\r
+#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */\r
+#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */\r
+#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */\r
+#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */\r
+#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */\r
+#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */\r
+#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */\r
+#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */\r
+#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */\r
+#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */\r
+#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */\r
+#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */\r
+#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */\r
+#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */\r
+#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */\r
+#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */\r
+\r
+/****************** Bit definition for EXTI_RTSR register *******************/\r
+#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */\r
+#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */\r
+#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */\r
+#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */\r
+#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */\r
+#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */\r
+#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */\r
+#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */\r
+#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */\r
+#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */\r
+#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */\r
+#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */\r
+#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */\r
+#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */\r
+#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */\r
+#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */\r
+#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */\r
+#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */\r
+#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */\r
+#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */\r
+\r
+/****************** Bit definition for EXTI_FTSR register *******************/\r
+#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */\r
+#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */\r
+#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */\r
+#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */\r
+#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */\r
+#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */\r
+#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */\r
+#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */\r
+#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */\r
+#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */\r
+#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */\r
+#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */\r
+#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */\r
+#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */\r
+#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */\r
+#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */\r
+#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */\r
+#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */\r
+#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */\r
+#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */\r
+\r
+/****************** Bit definition for EXTI_SWIER register ******************/\r
+#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */\r
+#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */\r
+#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */\r
+#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */\r
+#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */\r
+#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */\r
+#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */\r
+#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */\r
+#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */\r
+#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */\r
+#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */\r
+#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */\r
+#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */\r
+#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */\r
+#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */\r
+#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */\r
+#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */\r
+#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */\r
+#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */\r
+#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */\r
+\r
+/******************* Bit definition for EXTI_PR register ********************/\r
+#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */\r
+#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */\r
+#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */\r
+#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */\r
+#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */\r
+#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */\r
+#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */\r
+#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */\r
+#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */\r
+#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */\r
+#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */\r
+#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */\r
+#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */\r
+#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */\r
+#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */\r
+#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */\r
+#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */\r
+#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */\r
+#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */\r
+#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* DMA Controller */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for DMA_ISR register ********************/\r
+#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */\r
+#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */\r
+#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */\r
+#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */\r
+#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */\r
+#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */\r
+#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */\r
+#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */\r
+#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */\r
+#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */\r
+#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */\r
+#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */\r
+#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */\r
+#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */\r
+#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */\r
+#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */\r
+#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */\r
+#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */\r
+#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */\r
+#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */\r
+#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */\r
+#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */\r
+#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */\r
+#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */\r
+#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */\r
+#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */\r
+#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */\r
+#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */\r
+\r
+/******************* Bit definition for DMA_IFCR register *******************/\r
+#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clearr */\r
+#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */\r
+#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */\r
+#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */\r
+#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */\r
+#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */\r
+#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */\r
+#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */\r
+#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */\r
+#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */\r
+#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */\r
+#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */\r
+#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */\r
+#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */\r
+#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */\r
+#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */\r
+#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */\r
+#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */\r
+#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */\r
+#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */\r
+#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */\r
+#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */\r
+#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */\r
+#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */\r
+#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */\r
+#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */\r
+#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */\r
+#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */\r
+\r
+/******************* Bit definition for DMA_CCR1 register *******************/\r
+#define DMA_CCR1_EN ((uint16_t)0x0001) /*!< Channel enable*/\r
+#define DMA_CCR1_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */\r
+#define DMA_CCR1_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */\r
+#define DMA_CCR1_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */\r
+#define DMA_CCR1_DIR ((uint16_t)0x0010) /*!< Data transfer direction */\r
+#define DMA_CCR1_CIRC ((uint16_t)0x0020) /*!< Circular mode */\r
+#define DMA_CCR1_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */\r
+#define DMA_CCR1_MINC ((uint16_t)0x0080) /*!< Memory increment mode */\r
+\r
+#define DMA_CCR1_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */\r
+#define DMA_CCR1_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */\r
+#define DMA_CCR1_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */\r
+\r
+#define DMA_CCR1_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */\r
+#define DMA_CCR1_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */\r
+#define DMA_CCR1_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */\r
+\r
+#define DMA_CCR1_PL ((uint16_t)0x3000) /*!< PL[1:0] bits(Channel Priority level) */\r
+#define DMA_CCR1_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */\r
+#define DMA_CCR1_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */\r
+\r
+#define DMA_CCR1_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */\r
+\r
+/******************* Bit definition for DMA_CCR2 register *******************/\r
+#define DMA_CCR2_EN ((uint16_t)0x0001) /*!< Channel enable */\r
+#define DMA_CCR2_TCIE ((uint16_t)0x0002) /*!< ransfer complete interrupt enable */\r
+#define DMA_CCR2_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */\r
+#define DMA_CCR2_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */\r
+#define DMA_CCR2_DIR ((uint16_t)0x0010) /*!< Data transfer direction */\r
+#define DMA_CCR2_CIRC ((uint16_t)0x0020) /*!< Circular mode */\r
+#define DMA_CCR2_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */\r
+#define DMA_CCR2_MINC ((uint16_t)0x0080) /*!< Memory increment mode */\r
+\r
+#define DMA_CCR2_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */\r
+#define DMA_CCR2_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */\r
+#define DMA_CCR2_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */\r
+\r
+#define DMA_CCR2_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */\r
+#define DMA_CCR2_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */\r
+#define DMA_CCR2_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */\r
+\r
+#define DMA_CCR2_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */\r
+#define DMA_CCR2_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */\r
+#define DMA_CCR2_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */\r
+\r
+#define DMA_CCR2_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */\r
+\r
+/******************* Bit definition for DMA_CCR3 register *******************/\r
+#define DMA_CCR3_EN ((uint16_t)0x0001) /*!< Channel enable */\r
+#define DMA_CCR3_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */\r
+#define DMA_CCR3_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */\r
+#define DMA_CCR3_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */\r
+#define DMA_CCR3_DIR ((uint16_t)0x0010) /*!< Data transfer direction */\r
+#define DMA_CCR3_CIRC ((uint16_t)0x0020) /*!< Circular mode */\r
+#define DMA_CCR3_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */\r
+#define DMA_CCR3_MINC ((uint16_t)0x0080) /*!< Memory increment mode */\r
+\r
+#define DMA_CCR3_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */\r
+#define DMA_CCR3_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */\r
+#define DMA_CCR3_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */\r
+\r
+#define DMA_CCR3_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */\r
+#define DMA_CCR3_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */\r
+#define DMA_CCR3_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */\r
+\r
+#define DMA_CCR3_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */\r
+#define DMA_CCR3_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */\r
+#define DMA_CCR3_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */\r
+\r
+#define DMA_CCR3_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */\r
+\r
+/*!<****************** Bit definition for DMA_CCR4 register *******************/\r
+#define DMA_CCR4_EN ((uint16_t)0x0001) /*!<Channel enable */\r
+#define DMA_CCR4_TCIE ((uint16_t)0x0002) /*!<Transfer complete interrupt enable */\r
+#define DMA_CCR4_HTIE ((uint16_t)0x0004) /*!<Half Transfer interrupt enable */\r
+#define DMA_CCR4_TEIE ((uint16_t)0x0008) /*!<Transfer error interrupt enable */\r
+#define DMA_CCR4_DIR ((uint16_t)0x0010) /*!<Data transfer direction */\r
+#define DMA_CCR4_CIRC ((uint16_t)0x0020) /*!<Circular mode */\r
+#define DMA_CCR4_PINC ((uint16_t)0x0040) /*!<Peripheral increment mode */\r
+#define DMA_CCR4_MINC ((uint16_t)0x0080) /*!<Memory increment mode */\r
+\r
+#define DMA_CCR4_PSIZE ((uint16_t)0x0300) /*!<PSIZE[1:0] bits (Peripheral size) */\r
+#define DMA_CCR4_PSIZE_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
+#define DMA_CCR4_PSIZE_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
+\r
+#define DMA_CCR4_MSIZE ((uint16_t)0x0C00) /*!<MSIZE[1:0] bits (Memory size) */\r
+#define DMA_CCR4_MSIZE_0 ((uint16_t)0x0400) /*!<Bit 0 */\r
+#define DMA_CCR4_MSIZE_1 ((uint16_t)0x0800) /*!<Bit 1 */\r
+\r
+#define DMA_CCR4_PL ((uint16_t)0x3000) /*!<PL[1:0] bits (Channel Priority level) */\r
+#define DMA_CCR4_PL_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define DMA_CCR4_PL_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+\r
+#define DMA_CCR4_MEM2MEM ((uint16_t)0x4000) /*!<Memory to memory mode */\r
+\r
+/****************** Bit definition for DMA_CCR5 register *******************/\r
+#define DMA_CCR5_EN ((uint16_t)0x0001) /*!<Channel enable */\r
+#define DMA_CCR5_TCIE ((uint16_t)0x0002) /*!<Transfer complete interrupt enable */\r
+#define DMA_CCR5_HTIE ((uint16_t)0x0004) /*!<Half Transfer interrupt enable */\r
+#define DMA_CCR5_TEIE ((uint16_t)0x0008) /*!<Transfer error interrupt enable */\r
+#define DMA_CCR5_DIR ((uint16_t)0x0010) /*!<Data transfer direction */\r
+#define DMA_CCR5_CIRC ((uint16_t)0x0020) /*!<Circular mode */\r
+#define DMA_CCR5_PINC ((uint16_t)0x0040) /*!<Peripheral increment mode */\r
+#define DMA_CCR5_MINC ((uint16_t)0x0080) /*!<Memory increment mode */\r
+\r
+#define DMA_CCR5_PSIZE ((uint16_t)0x0300) /*!<PSIZE[1:0] bits (Peripheral size) */\r
+#define DMA_CCR5_PSIZE_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
+#define DMA_CCR5_PSIZE_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
+\r
+#define DMA_CCR5_MSIZE ((uint16_t)0x0C00) /*!<MSIZE[1:0] bits (Memory size) */\r
+#define DMA_CCR5_MSIZE_0 ((uint16_t)0x0400) /*!<Bit 0 */\r
+#define DMA_CCR5_MSIZE_1 ((uint16_t)0x0800) /*!<Bit 1 */\r
+\r
+#define DMA_CCR5_PL ((uint16_t)0x3000) /*!<PL[1:0] bits (Channel Priority level) */\r
+#define DMA_CCR5_PL_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define DMA_CCR5_PL_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+\r
+#define DMA_CCR5_MEM2MEM ((uint16_t)0x4000) /*!<Memory to memory mode enable */\r
+\r
+/******************* Bit definition for DMA_CCR6 register *******************/\r
+#define DMA_CCR6_EN ((uint16_t)0x0001) /*!<Channel enable */\r
+#define DMA_CCR6_TCIE ((uint16_t)0x0002) /*!<Transfer complete interrupt enable */\r
+#define DMA_CCR6_HTIE ((uint16_t)0x0004) /*!<Half Transfer interrupt enable */\r
+#define DMA_CCR6_TEIE ((uint16_t)0x0008) /*!<Transfer error interrupt enable */\r
+#define DMA_CCR6_DIR ((uint16_t)0x0010) /*!<Data transfer direction */\r
+#define DMA_CCR6_CIRC ((uint16_t)0x0020) /*!<Circular mode */\r
+#define DMA_CCR6_PINC ((uint16_t)0x0040) /*!<Peripheral increment mode */\r
+#define DMA_CCR6_MINC ((uint16_t)0x0080) /*!<Memory increment mode */\r
+\r
+#define DMA_CCR6_PSIZE ((uint16_t)0x0300) /*!<PSIZE[1:0] bits (Peripheral size) */\r
+#define DMA_CCR6_PSIZE_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
+#define DMA_CCR6_PSIZE_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
+\r
+#define DMA_CCR6_MSIZE ((uint16_t)0x0C00) /*!<MSIZE[1:0] bits (Memory size) */\r
+#define DMA_CCR6_MSIZE_0 ((uint16_t)0x0400) /*!<Bit 0 */\r
+#define DMA_CCR6_MSIZE_1 ((uint16_t)0x0800) /*!<Bit 1 */\r
+\r
+#define DMA_CCR6_PL ((uint16_t)0x3000) /*!<PL[1:0] bits (Channel Priority level) */\r
+#define DMA_CCR6_PL_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define DMA_CCR6_PL_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+\r
+#define DMA_CCR6_MEM2MEM ((uint16_t)0x4000) /*!<Memory to memory mode */\r
+\r
+/******************* Bit definition for DMA_CCR7 register *******************/\r
+#define DMA_CCR7_EN ((uint16_t)0x0001) /*!<Channel enable */\r
+#define DMA_CCR7_TCIE ((uint16_t)0x0002) /*!<Transfer complete interrupt enable */\r
+#define DMA_CCR7_HTIE ((uint16_t)0x0004) /*!<Half Transfer interrupt enable */\r
+#define DMA_CCR7_TEIE ((uint16_t)0x0008) /*!<Transfer error interrupt enable */\r
+#define DMA_CCR7_DIR ((uint16_t)0x0010) /*!<Data transfer direction */\r
+#define DMA_CCR7_CIRC ((uint16_t)0x0020) /*!<Circular mode */\r
+#define DMA_CCR7_PINC ((uint16_t)0x0040) /*!<Peripheral increment mode */\r
+#define DMA_CCR7_MINC ((uint16_t)0x0080) /*!<Memory increment mode */\r
+\r
+#define DMA_CCR7_PSIZE , ((uint16_t)0x0300) /*!<PSIZE[1:0] bits (Peripheral size) */\r
+#define DMA_CCR7_PSIZE_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
+#define DMA_CCR7_PSIZE_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
+\r
+#define DMA_CCR7_MSIZE ((uint16_t)0x0C00) /*!<MSIZE[1:0] bits (Memory size) */\r
+#define DMA_CCR7_MSIZE_0 ((uint16_t)0x0400) /*!<Bit 0 */\r
+#define DMA_CCR7_MSIZE_1 ((uint16_t)0x0800) /*!<Bit 1 */\r
+\r
+#define DMA_CCR7_PL ((uint16_t)0x3000) /*!<PL[1:0] bits (Channel Priority level) */\r
+#define DMA_CCR7_PL_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define DMA_CCR7_PL_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+\r
+#define DMA_CCR7_MEM2MEM ((uint16_t)0x4000) /*!<Memory to memory mode enable */\r
+\r
+/****************** Bit definition for DMA_CNDTR1 register ******************/\r
+#define DMA_CNDTR1_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */\r
+\r
+/****************** Bit definition for DMA_CNDTR2 register ******************/\r
+#define DMA_CNDTR2_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */\r
+\r
+/****************** Bit definition for DMA_CNDTR3 register ******************/\r
+#define DMA_CNDTR3_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */\r
+\r
+/****************** Bit definition for DMA_CNDTR4 register ******************/\r
+#define DMA_CNDTR4_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */\r
+\r
+/****************** Bit definition for DMA_CNDTR5 register ******************/\r
+#define DMA_CNDTR5_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */\r
+\r
+/****************** Bit definition for DMA_CNDTR6 register ******************/\r
+#define DMA_CNDTR6_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */\r
+\r
+/****************** Bit definition for DMA_CNDTR7 register ******************/\r
+#define DMA_CNDTR7_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */\r
+\r
+/****************** Bit definition for DMA_CPAR1 register *******************/\r
+#define DMA_CPAR1_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */\r
+\r
+/****************** Bit definition for DMA_CPAR2 register *******************/\r
+#define DMA_CPAR2_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */\r
+\r
+/****************** Bit definition for DMA_CPAR3 register *******************/\r
+#define DMA_CPAR3_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */\r
+\r
+\r
+/****************** Bit definition for DMA_CPAR4 register *******************/\r
+#define DMA_CPAR4_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */\r
+\r
+/****************** Bit definition for DMA_CPAR5 register *******************/\r
+#define DMA_CPAR5_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */\r
+\r
+/****************** Bit definition for DMA_CPAR6 register *******************/\r
+#define DMA_CPAR6_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */\r
+\r
+\r
+/****************** Bit definition for DMA_CPAR7 register *******************/\r
+#define DMA_CPAR7_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */\r
+\r
+/****************** Bit definition for DMA_CMAR1 register *******************/\r
+#define DMA_CMAR1_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */\r
+\r
+/****************** Bit definition for DMA_CMAR2 register *******************/\r
+#define DMA_CMAR2_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */\r
+\r
+/****************** Bit definition for DMA_CMAR3 register *******************/\r
+#define DMA_CMAR3_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */\r
+\r
+\r
+/****************** Bit definition for DMA_CMAR4 register *******************/\r
+#define DMA_CMAR4_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */\r
+\r
+/****************** Bit definition for DMA_CMAR5 register *******************/\r
+#define DMA_CMAR5_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */\r
+\r
+/****************** Bit definition for DMA_CMAR6 register *******************/\r
+#define DMA_CMAR6_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */\r
+\r
+/****************** Bit definition for DMA_CMAR7 register *******************/\r
+#define DMA_CMAR7_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Analog to Digital Converter */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************** Bit definition for ADC_SR register ********************/\r
+#define ADC_SR_AWD ((uint8_t)0x01) /*!<Analog watchdog flag */\r
+#define ADC_SR_EOC ((uint8_t)0x02) /*!<End of conversion */\r
+#define ADC_SR_JEOC ((uint8_t)0x04) /*!<Injected channel end of conversion */\r
+#define ADC_SR_JSTRT ((uint8_t)0x08) /*!<Injected channel Start flag */\r
+#define ADC_SR_STRT ((uint8_t)0x10) /*!<Regular channel Start flag */\r
+\r
+/******************* Bit definition for ADC_CR1 register ********************/\r
+#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */\r
+#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+\r
+#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */\r
+#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */\r
+#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */\r
+#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!<Scan mode */\r
+#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */\r
+#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!<Automatic injected group conversion */\r
+#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */\r
+#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */\r
+\r
+#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */\r
+#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!<Bit 0 */\r
+#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!<Bit 1 */\r
+#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!<Bit 2 */\r
+\r
+#define ADC_CR1_DUALMOD ((uint32_t)0x000F0000) /*!<DUALMOD[3:0] bits (Dual mode selection) */\r
+#define ADC_CR1_DUALMOD_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define ADC_CR1_DUALMOD_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define ADC_CR1_DUALMOD_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define ADC_CR1_DUALMOD_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+\r
+#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */\r
+#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */\r
+\r
+ \r
+/******************* Bit definition for ADC_CR2 register ********************/\r
+#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */\r
+#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!<Continuous Conversion */\r
+#define ADC_CR2_CAL ((uint32_t)0x00000004) /*!<A/D Calibration */\r
+#define ADC_CR2_RSTCAL ((uint32_t)0x00000008) /*!<Reset Calibration */\r
+#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!<Direct Memory access mode */\r
+#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!<Data Alignment */\r
+\r
+#define ADC_CR2_JEXTSEL ((uint32_t)0x00007000) /*!<JEXTSEL[2:0] bits (External event select for injected group) */\r
+#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) /*!<Bit 0 */\r
+#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) /*!<Bit 1 */\r
+#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) /*!<Bit 2 */\r
+\r
+#define ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) /*!<External Trigger Conversion mode for injected channels */\r
+\r
+#define ADC_CR2_EXTSEL ((uint32_t)0x000E0000) /*!<EXTSEL[2:0] bits (External Event Select for regular group) */\r
+#define ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) /*!<Bit 0 */\r
+#define ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) /*!<Bit 1 */\r
+#define ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) /*!<Bit 2 */\r
+\r
+#define ADC_CR2_EXTTRIG ((uint32_t)0x00100000) /*!<External Trigger Conversion mode for regular channels */\r
+#define ADC_CR2_JSWSTART ((uint32_t)0x00200000) /*!<Start Conversion of injected channels */\r
+#define ADC_CR2_SWSTART ((uint32_t)0x00400000) /*!<Start Conversion of regular channels */\r
+#define ADC_CR2_TSVREFE ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */\r
+\r
+/****************** Bit definition for ADC_SMPR1 register *******************/\r
+#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */\r
+#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+\r
+#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */\r
+#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!<Bit 0 */\r
+#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!<Bit 1 */\r
+#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!<Bit 2 */\r
+\r
+#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */\r
+#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!<Bit 0 */\r
+#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!<Bit 1 */\r
+#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!<Bit 2 */\r
+\r
+#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */\r
+#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!<Bit 0 */\r
+#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!<Bit 1 */\r
+#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!<Bit 2 */\r
+\r
+#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */\r
+#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!<Bit 0 */\r
+#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!<Bit 1 */\r
+#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!<Bit 2 */\r
+\r
+#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */\r
+#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!<Bit 0 */\r
+#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!<Bit 1 */\r
+#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!<Bit 2 */\r
+\r
+#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */\r
+#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!<Bit 0 */\r
+#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!<Bit 1 */\r
+#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!<Bit 2 */\r
+\r
+#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */\r
+#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!<Bit 0 */\r
+#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!<Bit 1 */\r
+#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!<Bit 2 */\r
+\r
+/****************** Bit definition for ADC_SMPR2 register *******************/\r
+#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */\r
+#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+\r
+#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */\r
+#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!<Bit 0 */\r
+#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!<Bit 1 */\r
+#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!<Bit 2 */\r
+\r
+#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */\r
+#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!<Bit 0 */\r
+#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!<Bit 1 */\r
+#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!<Bit 2 */\r
+\r
+#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */\r
+#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!<Bit 0 */\r
+#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!<Bit 1 */\r
+#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!<Bit 2 */\r
+\r
+#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */\r
+#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!<Bit 0 */\r
+#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!<Bit 1 */\r
+#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!<Bit 2 */\r
+\r
+#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */\r
+#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!<Bit 0 */\r
+#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!<Bit 1 */\r
+#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!<Bit 2 */\r
+\r
+#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */\r
+#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!<Bit 0 */\r
+#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!<Bit 1 */\r
+#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!<Bit 2 */\r
+\r
+#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */\r
+#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!<Bit 0 */\r
+#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!<Bit 1 */\r
+#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!<Bit 2 */\r
+\r
+#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */\r
+#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+\r
+#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */\r
+#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!<Bit 0 */\r
+#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!<Bit 1 */\r
+#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!<Bit 2 */\r
+\r
+/****************** Bit definition for ADC_JOFR1 register *******************/\r
+#define ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 1 */\r
+\r
+/****************** Bit definition for ADC_JOFR2 register *******************/\r
+#define ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 2 */\r
+\r
+/****************** Bit definition for ADC_JOFR3 register *******************/\r
+#define ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 3 */\r
+\r
+/****************** Bit definition for ADC_JOFR4 register *******************/\r
+#define ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 4 */\r
+\r
+/******************* Bit definition for ADC_HTR register ********************/\r
+#define ADC_HTR_HT ((uint16_t)0x0FFF) /*!<Analog watchdog high threshold */\r
+\r
+/******************* Bit definition for ADC_LTR register ********************/\r
+#define ADC_LTR_LT ((uint16_t)0x0FFF) /*!<Analog watchdog low threshold */\r
+\r
+/******************* Bit definition for ADC_SQR1 register *******************/\r
+#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */\r
+#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+\r
+#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */\r
+#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!<Bit 0 */\r
+#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!<Bit 1 */\r
+#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!<Bit 2 */\r
+#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!<Bit 3 */\r
+#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!<Bit 4 */\r
+\r
+#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */\r
+#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!<Bit 0 */\r
+#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!<Bit 1 */\r
+#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!<Bit 2 */\r
+#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!<Bit 3 */\r
+#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!<Bit 4 */\r
+\r
+#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */\r
+#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!<Bit 0 */\r
+#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!<Bit 1 */\r
+#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!<Bit 2 */\r
+#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!<Bit 3 */\r
+#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!<Bit 4 */\r
+\r
+#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */\r
+#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
+#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
+\r
+/******************* Bit definition for ADC_SQR2 register *******************/\r
+#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */\r
+#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+\r
+#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */\r
+#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!<Bit 0 */\r
+#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!<Bit 1 */\r
+#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!<Bit 2 */\r
+#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!<Bit 3 */\r
+#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!<Bit 4 */\r
+\r
+#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */\r
+#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!<Bit 0 */\r
+#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!<Bit 1 */\r
+#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!<Bit 2 */\r
+#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!<Bit 3 */\r
+#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!<Bit 4 */\r
+\r
+#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */\r
+#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!<Bit 0 */\r
+#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!<Bit 1 */\r
+#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!<Bit 2 */\r
+#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!<Bit 3 */\r
+#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!<Bit 4 */\r
+\r
+#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */\r
+#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
+#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
+#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!<Bit 4 */\r
+\r
+#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */\r
+#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!<Bit 0 */\r
+#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!<Bit 1 */\r
+#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!<Bit 2 */\r
+#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!<Bit 3 */\r
+#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!<Bit 4 */\r
+\r
+/******************* Bit definition for ADC_SQR3 register *******************/\r
+#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */\r
+#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+\r
+#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */\r
+#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */\r
+#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */\r
+#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */\r
+#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */\r
+#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */\r
+\r
+#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */\r
+#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */\r
+#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */\r
+#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */\r
+#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */\r
+#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */\r
+\r
+#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */\r
+#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */\r
+#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */\r
+#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */\r
+#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */\r
+#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */\r
+\r
+#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */\r
+#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
+#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
+#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!<Bit 4 */\r
+\r
+#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */\r
+#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!<Bit 0 */\r
+#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!<Bit 1 */\r
+#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!<Bit 2 */\r
+#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!<Bit 3 */\r
+#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!<Bit 4 */\r
+\r
+/******************* Bit definition for ADC_JSQR register *******************/\r
+#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */ \r
+#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+\r
+#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */\r
+#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */\r
+#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */\r
+#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */\r
+#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */\r
+#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */\r
+\r
+#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */\r
+#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */\r
+#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */\r
+#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */\r
+#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */\r
+#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */\r
+\r
+#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */\r
+#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */\r
+#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */\r
+#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */\r
+#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */\r
+#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */\r
+\r
+#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */\r
+#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+\r
+/******************* Bit definition for ADC_JDR1 register *******************/\r
+#define ADC_JDR1_JDATA ((uint16_t)0xFFFF) /*!<Injected data */\r
+\r
+/******************* Bit definition for ADC_JDR2 register *******************/\r
+#define ADC_JDR2_JDATA ((uint16_t)0xFFFF) /*!<Injected data */\r
+\r
+/******************* Bit definition for ADC_JDR3 register *******************/\r
+#define ADC_JDR3_JDATA ((uint16_t)0xFFFF) /*!<Injected data */\r
+\r
+/******************* Bit definition for ADC_JDR4 register *******************/\r
+#define ADC_JDR4_JDATA ((uint16_t)0xFFFF) /*!<Injected data */\r
+\r
+/******************** Bit definition for ADC_DR register ********************/\r
+#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!<Regular data */\r
+#define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!<ADC2 data */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Digital to Analog Converter */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************** Bit definition for DAC_CR register ********************/\r
+#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */\r
+#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */\r
+#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */\r
+\r
+#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */\r
+#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */\r
+#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */\r
+#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */\r
+\r
+#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */\r
+#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */\r
+#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */\r
+\r
+#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */\r
+#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+\r
+#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */\r
+#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */\r
+#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */\r
+#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */\r
+\r
+#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */\r
+#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */\r
+#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */\r
+#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */\r
+\r
+#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */\r
+#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */\r
+#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */\r
+\r
+#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */\r
+#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+\r
+#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */\r
+\r
+/***************** Bit definition for DAC_SWTRIGR register ******************/\r
+#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!<DAC channel1 software trigger */\r
+#define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /*!<DAC channel2 software trigger */\r
+\r
+/***************** Bit definition for DAC_DHR12R1 register ******************/\r
+#define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */\r
+\r
+/***************** Bit definition for DAC_DHR12L1 register ******************/\r
+#define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */\r
+\r
+/****************** Bit definition for DAC_DHR8R1 register ******************/\r
+#define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */\r
+\r
+/***************** Bit definition for DAC_DHR12R2 register ******************/\r
+#define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */\r
+\r
+/***************** Bit definition for DAC_DHR12L2 register ******************/\r
+#define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */\r
+\r
+/****************** Bit definition for DAC_DHR8R2 register ******************/\r
+#define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */\r
+\r
+/***************** Bit definition for DAC_DHR12RD register ******************/\r
+#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */\r
+#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */\r
+\r
+/***************** Bit definition for DAC_DHR12LD register ******************/\r
+#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */\r
+#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */\r
+\r
+/****************** Bit definition for DAC_DHR8RD register ******************/\r
+#define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) /*!<DAC channel1 8-bit Right aligned data */\r
+#define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) /*!<DAC channel2 8-bit Right aligned data */\r
+\r
+/******************* Bit definition for DAC_DOR1 register *******************/\r
+#define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /*!<DAC channel1 data output */\r
+\r
+/******************* Bit definition for DAC_DOR2 register *******************/\r
+#define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*!<DAC channel2 data output */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* TIM */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for TIM_CR1 register ********************/\r
+#define TIM_CR1_CEN ((uint16_t)0x0001) /*!<Counter enable */\r
+#define TIM_CR1_UDIS ((uint16_t)0x0002) /*!<Update disable */\r
+#define TIM_CR1_URS ((uint16_t)0x0004) /*!<Update request source */\r
+#define TIM_CR1_OPM ((uint16_t)0x0008) /*!<One pulse mode */\r
+#define TIM_CR1_DIR ((uint16_t)0x0010) /*!<Direction */\r
+\r
+#define TIM_CR1_CMS ((uint16_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */\r
+#define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*!<Bit 0 */\r
+#define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*!<Bit 1 */\r
+\r
+#define TIM_CR1_ARPE ((uint16_t)0x0080) /*!<Auto-reload preload enable */\r
+\r
+#define TIM_CR1_CKD ((uint16_t)0x0300) /*!<CKD[1:0] bits (clock division) */\r
+#define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
+#define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
+\r
+/******************* Bit definition for TIM_CR2 register ********************/\r
+#define TIM_CR2_CCPC ((uint16_t)0x0001) /*!<Capture/Compare Preloaded Control */\r
+#define TIM_CR2_CCUS ((uint16_t)0x0004) /*!<Capture/Compare Control Update Selection */\r
+#define TIM_CR2_CCDS ((uint16_t)0x0008) /*!<Capture/Compare DMA Selection */\r
+\r
+#define TIM_CR2_MMS ((uint16_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */\r
+#define TIM_CR2_MMS_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define TIM_CR2_MMS_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+#define TIM_CR2_MMS_2 ((uint16_t)0x0040) /*!<Bit 2 */\r
+\r
+#define TIM_CR2_TI1S ((uint16_t)0x0080) /*!<TI1 Selection */\r
+#define TIM_CR2_OIS1 ((uint16_t)0x0100) /*!<Output Idle state 1 (OC1 output) */\r
+#define TIM_CR2_OIS1N ((uint16_t)0x0200) /*!<Output Idle state 1 (OC1N output) */\r
+#define TIM_CR2_OIS2 ((uint16_t)0x0400) /*!<Output Idle state 2 (OC2 output) */\r
+#define TIM_CR2_OIS2N ((uint16_t)0x0800) /*!<Output Idle state 2 (OC2N output) */\r
+#define TIM_CR2_OIS3 ((uint16_t)0x1000) /*!<Output Idle state 3 (OC3 output) */\r
+#define TIM_CR2_OIS3N ((uint16_t)0x2000) /*!<Output Idle state 3 (OC3N output) */\r
+#define TIM_CR2_OIS4 ((uint16_t)0x4000) /*!<Output Idle state 4 (OC4 output) */\r
+\r
+/******************* Bit definition for TIM_SMCR register *******************/\r
+#define TIM_SMCR_SMS ((uint16_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */\r
+#define TIM_SMCR_SMS_0 ((uint16_t)0x0001) /*!<Bit 0 */\r
+#define TIM_SMCR_SMS_1 ((uint16_t)0x0002) /*!<Bit 1 */\r
+#define TIM_SMCR_SMS_2 ((uint16_t)0x0004) /*!<Bit 2 */\r
+\r
+#define TIM_SMCR_TS ((uint16_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */\r
+#define TIM_SMCR_TS_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define TIM_SMCR_TS_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+#define TIM_SMCR_TS_2 ((uint16_t)0x0040) /*!<Bit 2 */\r
+\r
+#define TIM_SMCR_MSM ((uint16_t)0x0080) /*!<Master/slave mode */\r
+\r
+#define TIM_SMCR_ETF ((uint16_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */\r
+#define TIM_SMCR_ETF_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
+#define TIM_SMCR_ETF_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
+#define TIM_SMCR_ETF_2 ((uint16_t)0x0400) /*!<Bit 2 */\r
+#define TIM_SMCR_ETF_3 ((uint16_t)0x0800) /*!<Bit 3 */\r
+\r
+#define TIM_SMCR_ETPS ((uint16_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */\r
+#define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+\r
+#define TIM_SMCR_ECE ((uint16_t)0x4000) /*!<External clock enable */\r
+#define TIM_SMCR_ETP ((uint16_t)0x8000) /*!<External trigger polarity */\r
+\r
+/******************* Bit definition for TIM_DIER register *******************/\r
+#define TIM_DIER_UIE ((uint16_t)0x0001) /*!<Update interrupt enable */\r
+#define TIM_DIER_CC1IE ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt enable */\r
+#define TIM_DIER_CC2IE ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt enable */\r
+#define TIM_DIER_CC3IE ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt enable */\r
+#define TIM_DIER_CC4IE ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt enable */\r
+#define TIM_DIER_COMIE ((uint16_t)0x0020) /*!<COM interrupt enable */\r
+#define TIM_DIER_TIE ((uint16_t)0x0040) /*!<Trigger interrupt enable */\r
+#define TIM_DIER_BIE ((uint16_t)0x0080) /*!<Break interrupt enable */\r
+#define TIM_DIER_UDE ((uint16_t)0x0100) /*!<Update DMA request enable */\r
+#define TIM_DIER_CC1DE ((uint16_t)0x0200) /*!<Capture/Compare 1 DMA request enable */\r
+#define TIM_DIER_CC2DE ((uint16_t)0x0400) /*!<Capture/Compare 2 DMA request enable */\r
+#define TIM_DIER_CC3DE ((uint16_t)0x0800) /*!<Capture/Compare 3 DMA request enable */\r
+#define TIM_DIER_CC4DE ((uint16_t)0x1000) /*!<Capture/Compare 4 DMA request enable */\r
+#define TIM_DIER_COMDE ((uint16_t)0x2000) /*!<COM DMA request enable */\r
+#define TIM_DIER_TDE ((uint16_t)0x4000) /*!<Trigger DMA request enable */\r
+\r
+/******************** Bit definition for TIM_SR register ********************/\r
+#define TIM_SR_UIF ((uint16_t)0x0001) /*!<Update interrupt Flag */\r
+#define TIM_SR_CC1IF ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */\r
+#define TIM_SR_CC2IF ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */\r
+#define TIM_SR_CC3IF ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */\r
+#define TIM_SR_CC4IF ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */\r
+#define TIM_SR_COMIF ((uint16_t)0x0020) /*!<COM interrupt Flag */\r
+#define TIM_SR_TIF ((uint16_t)0x0040) /*!<Trigger interrupt Flag */\r
+#define TIM_SR_BIF ((uint16_t)0x0080) /*!<Break interrupt Flag */\r
+#define TIM_SR_CC1OF ((uint16_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */\r
+#define TIM_SR_CC2OF ((uint16_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */\r
+#define TIM_SR_CC3OF ((uint16_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */\r
+#define TIM_SR_CC4OF ((uint16_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */\r
+\r
+/******************* Bit definition for TIM_EGR register ********************/\r
+#define TIM_EGR_UG ((uint8_t)0x01) /*!<Update Generation */\r
+#define TIM_EGR_CC1G ((uint8_t)0x02) /*!<Capture/Compare 1 Generation */\r
+#define TIM_EGR_CC2G ((uint8_t)0x04) /*!<Capture/Compare 2 Generation */\r
+#define TIM_EGR_CC3G ((uint8_t)0x08) /*!<Capture/Compare 3 Generation */\r
+#define TIM_EGR_CC4G ((uint8_t)0x10) /*!<Capture/Compare 4 Generation */\r
+#define TIM_EGR_COMG ((uint8_t)0x20) /*!<Capture/Compare Control Update Generation */\r
+#define TIM_EGR_TG ((uint8_t)0x40) /*!<Trigger Generation */\r
+#define TIM_EGR_BG ((uint8_t)0x80) /*!<Break Generation */\r
+\r
+/****************** Bit definition for TIM_CCMR1 register *******************/\r
+#define TIM_CCMR1_CC1S ((uint16_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */\r
+#define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) /*!<Bit 0 */\r
+#define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR1_OC1FE ((uint16_t)0x0004) /*!<Output Compare 1 Fast enable */\r
+#define TIM_CCMR1_OC1PE ((uint16_t)0x0008) /*!<Output Compare 1 Preload enable */\r
+\r
+#define TIM_CCMR1_OC1M ((uint16_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */\r
+#define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+#define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) /*!<Bit 2 */\r
+\r
+#define TIM_CCMR1_OC1CE ((uint16_t)0x0080) /*!<Output Compare 1Clear Enable */\r
+\r
+#define TIM_CCMR1_CC2S ((uint16_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */\r
+#define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
+#define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR1_OC2FE ((uint16_t)0x0400) /*!<Output Compare 2 Fast enable */\r
+#define TIM_CCMR1_OC2PE ((uint16_t)0x0800) /*!<Output Compare 2 Preload enable */\r
+\r
+#define TIM_CCMR1_OC2M ((uint16_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */\r
+#define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+#define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) /*!<Bit 2 */\r
+\r
+#define TIM_CCMR1_OC2CE ((uint16_t)0x8000) /*!<Output Compare 2 Clear Enable */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+#define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */\r
+#define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */\r
+#define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR1_IC1F ((uint16_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */\r
+#define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+#define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) /*!<Bit 2 */\r
+#define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) /*!<Bit 3 */\r
+\r
+#define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */\r
+#define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */\r
+#define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR1_IC2F ((uint16_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */\r
+#define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+#define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) /*!<Bit 2 */\r
+#define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) /*!<Bit 3 */\r
+\r
+/****************** Bit definition for TIM_CCMR2 register *******************/\r
+#define TIM_CCMR2_CC3S ((uint16_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */\r
+#define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) /*!<Bit 0 */\r
+#define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR2_OC3FE ((uint16_t)0x0004) /*!<Output Compare 3 Fast enable */\r
+#define TIM_CCMR2_OC3PE ((uint16_t)0x0008) /*!<Output Compare 3 Preload enable */\r
+\r
+#define TIM_CCMR2_OC3M ((uint16_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */\r
+#define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+#define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) /*!<Bit 2 */\r
+\r
+#define TIM_CCMR2_OC3CE ((uint16_t)0x0080) /*!<Output Compare 3 Clear Enable */\r
+\r
+#define TIM_CCMR2_CC4S ((uint16_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */\r
+#define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
+#define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR2_OC4FE ((uint16_t)0x0400) /*!<Output Compare 4 Fast enable */\r
+#define TIM_CCMR2_OC4PE ((uint16_t)0x0800) /*!<Output Compare 4 Preload enable */\r
+\r
+#define TIM_CCMR2_OC4M ((uint16_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */\r
+#define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+#define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) /*!<Bit 2 */\r
+\r
+#define TIM_CCMR2_OC4CE ((uint16_t)0x8000) /*!<Output Compare 4 Clear Enable */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+#define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */\r
+#define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */\r
+#define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR2_IC3F ((uint16_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */\r
+#define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+#define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) /*!<Bit 2 */\r
+#define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) /*!<Bit 3 */\r
+\r
+#define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */\r
+#define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */\r
+#define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR2_IC4F ((uint16_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */\r
+#define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+#define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) /*!<Bit 2 */\r
+#define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) /*!<Bit 3 */\r
+\r
+/******************* Bit definition for TIM_CCER register *******************/\r
+#define TIM_CCER_CC1E ((uint16_t)0x0001) /*!<Capture/Compare 1 output enable */\r
+#define TIM_CCER_CC1P ((uint16_t)0x0002) /*!<Capture/Compare 1 output Polarity */\r
+#define TIM_CCER_CC1NE ((uint16_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */\r
+#define TIM_CCER_CC1NP ((uint16_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */\r
+#define TIM_CCER_CC2E ((uint16_t)0x0010) /*!<Capture/Compare 2 output enable */\r
+#define TIM_CCER_CC2P ((uint16_t)0x0020) /*!<Capture/Compare 2 output Polarity */\r
+#define TIM_CCER_CC2NE ((uint16_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */\r
+#define TIM_CCER_CC2NP ((uint16_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */\r
+#define TIM_CCER_CC3E ((uint16_t)0x0100) /*!<Capture/Compare 3 output enable */\r
+#define TIM_CCER_CC3P ((uint16_t)0x0200) /*!<Capture/Compare 3 output Polarity */\r
+#define TIM_CCER_CC3NE ((uint16_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */\r
+#define TIM_CCER_CC3NP ((uint16_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */\r
+#define TIM_CCER_CC4E ((uint16_t)0x1000) /*!<Capture/Compare 4 output enable */\r
+#define TIM_CCER_CC4P ((uint16_t)0x2000) /*!<Capture/Compare 4 output Polarity */\r
+\r
+/******************* Bit definition for TIM_CNT register ********************/\r
+#define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!<Counter Value */\r
+\r
+/******************* Bit definition for TIM_PSC register ********************/\r
+#define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!<Prescaler Value */\r
+\r
+/******************* Bit definition for TIM_ARR register ********************/\r
+#define TIM_ARR_ARR ((uint16_t)0xFFFF) /*!<actual auto-reload Value */\r
+\r
+/******************* Bit definition for TIM_RCR register ********************/\r
+#define TIM_RCR_REP ((uint8_t)0xFF) /*!<Repetition Counter Value */\r
+\r
+/******************* Bit definition for TIM_CCR1 register *******************/\r
+#define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*!<Capture/Compare 1 Value */\r
+\r
+/******************* Bit definition for TIM_CCR2 register *******************/\r
+#define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*!<Capture/Compare 2 Value */\r
+\r
+/******************* Bit definition for TIM_CCR3 register *******************/\r
+#define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*!<Capture/Compare 3 Value */\r
+\r
+/******************* Bit definition for TIM_CCR4 register *******************/\r
+#define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*!<Capture/Compare 4 Value */\r
+\r
+/******************* Bit definition for TIM_BDTR register *******************/\r
+#define TIM_BDTR_DTG ((uint16_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */\r
+#define TIM_BDTR_DTG_0 ((uint16_t)0x0001) /*!<Bit 0 */\r
+#define TIM_BDTR_DTG_1 ((uint16_t)0x0002) /*!<Bit 1 */\r
+#define TIM_BDTR_DTG_2 ((uint16_t)0x0004) /*!<Bit 2 */\r
+#define TIM_BDTR_DTG_3 ((uint16_t)0x0008) /*!<Bit 3 */\r
+#define TIM_BDTR_DTG_4 ((uint16_t)0x0010) /*!<Bit 4 */\r
+#define TIM_BDTR_DTG_5 ((uint16_t)0x0020) /*!<Bit 5 */\r
+#define TIM_BDTR_DTG_6 ((uint16_t)0x0040) /*!<Bit 6 */\r
+#define TIM_BDTR_DTG_7 ((uint16_t)0x0080) /*!<Bit 7 */\r
+\r
+#define TIM_BDTR_LOCK ((uint16_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */\r
+#define TIM_BDTR_LOCK_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
+#define TIM_BDTR_LOCK_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
+\r
+#define TIM_BDTR_OSSI ((uint16_t)0x0400) /*!<Off-State Selection for Idle mode */\r
+#define TIM_BDTR_OSSR ((uint16_t)0x0800) /*!<Off-State Selection for Run mode */\r
+#define TIM_BDTR_BKE ((uint16_t)0x1000) /*!<Break enable */\r
+#define TIM_BDTR_BKP ((uint16_t)0x2000) /*!<Break Polarity */\r
+#define TIM_BDTR_AOE ((uint16_t)0x4000) /*!<Automatic Output enable */\r
+#define TIM_BDTR_MOE ((uint16_t)0x8000) /*!<Main Output enable */\r
+\r
+/******************* Bit definition for TIM_DCR register ********************/\r
+#define TIM_DCR_DBA ((uint16_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */\r
+#define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*!<Bit 0 */\r
+#define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*!<Bit 1 */\r
+#define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*!<Bit 2 */\r
+#define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*!<Bit 3 */\r
+#define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*!<Bit 4 */\r
+\r
+#define TIM_DCR_DBL ((uint16_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */\r
+#define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
+#define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
+#define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*!<Bit 2 */\r
+#define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*!<Bit 3 */\r
+#define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*!<Bit 4 */\r
+\r
+/******************* Bit definition for TIM_DMAR register *******************/\r
+#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*!<DMA register for burst accesses */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Real-Time Clock */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for RTC_CRH register ********************/\r
+#define RTC_CRH_SECIE ((uint8_t)0x01) /*!<Second Interrupt Enable */\r
+#define RTC_CRH_ALRIE ((uint8_t)0x02) /*!<Alarm Interrupt Enable */\r
+#define RTC_CRH_OWIE ((uint8_t)0x04) /*!<OverfloW Interrupt Enable */\r
+\r
+/******************* Bit definition for RTC_CRL register ********************/\r
+#define RTC_CRL_SECF ((uint8_t)0x01) /*!<Second Flag */\r
+#define RTC_CRL_ALRF ((uint8_t)0x02) /*!<Alarm Flag */\r
+#define RTC_CRL_OWF ((uint8_t)0x04) /*!<OverfloW Flag */\r
+#define RTC_CRL_RSF ((uint8_t)0x08) /*!<Registers Synchronized Flag */\r
+#define RTC_CRL_CNF ((uint8_t)0x10) /*!<Configuration Flag */\r
+#define RTC_CRL_RTOFF ((uint8_t)0x20) /*!<RTC operation OFF */\r
+\r
+/******************* Bit definition for RTC_PRLH register *******************/\r
+#define RTC_PRLH_PRL ((uint16_t)0x000F) /*!<RTC Prescaler Reload Value High */\r
+\r
+/******************* Bit definition for RTC_PRLL register *******************/\r
+#define RTC_PRLL_PRL ((uint16_t)0xFFFF) /*!<RTC Prescaler Reload Value Low */\r
+\r
+/******************* Bit definition for RTC_DIVH register *******************/\r
+#define RTC_DIVH_RTC_DIV ((uint16_t)0x000F) /*!<RTC Clock Divider High */\r
+\r
+/******************* Bit definition for RTC_DIVL register *******************/\r
+#define RTC_DIVL_RTC_DIV ((uint16_t)0xFFFF) /*!<RTC Clock Divider Low */\r
+\r
+/******************* Bit definition for RTC_CNTH register *******************/\r
+#define RTC_CNTH_RTC_CNT ((uint16_t)0xFFFF) /*!<RTC Counter High */\r
+\r
+/******************* Bit definition for RTC_CNTL register *******************/\r
+#define RTC_CNTL_RTC_CNT ((uint16_t)0xFFFF) /*!<RTC Counter Low */\r
+\r
+/******************* Bit definition for RTC_ALRH register *******************/\r
+#define RTC_ALRH_RTC_ALR ((uint16_t)0xFFFF) /*!<RTC Alarm High */\r
+\r
+/******************* Bit definition for RTC_ALRL register *******************/\r
+#define RTC_ALRL_RTC_ALR ((uint16_t)0xFFFF) /*!<RTC Alarm Low */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Independent WATCHDOG */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for IWDG_KR register ********************/\r
+#define IWDG_KR_KEY ((uint16_t)0xFFFF) /*!<Key value (write only, read 0000h) */\r
+\r
+/******************* Bit definition for IWDG_PR register ********************/\r
+#define IWDG_PR_PR ((uint8_t)0x07) /*!<PR[2:0] (Prescaler divider) */\r
+#define IWDG_PR_PR_0 ((uint8_t)0x01) /*!<Bit 0 */\r
+#define IWDG_PR_PR_1 ((uint8_t)0x02) /*!<Bit 1 */\r
+#define IWDG_PR_PR_2 ((uint8_t)0x04) /*!<Bit 2 */\r
+\r
+/******************* Bit definition for IWDG_RLR register *******************/\r
+#define IWDG_RLR_RL ((uint16_t)0x0FFF) /*!<Watchdog counter reload value */\r
+\r
+/******************* Bit definition for IWDG_SR register ********************/\r
+#define IWDG_SR_PVU ((uint8_t)0x01) /*!<Watchdog prescaler value update */\r
+#define IWDG_SR_RVU ((uint8_t)0x02) /*!<Watchdog counter reload value update */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Window WATCHDOG */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for WWDG_CR register ********************/\r
+#define WWDG_CR_T ((uint8_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */\r
+#define WWDG_CR_T0 ((uint8_t)0x01) /*!<Bit 0 */\r
+#define WWDG_CR_T1 ((uint8_t)0x02) /*!<Bit 1 */\r
+#define WWDG_CR_T2 ((uint8_t)0x04) /*!<Bit 2 */\r
+#define WWDG_CR_T3 ((uint8_t)0x08) /*!<Bit 3 */\r
+#define WWDG_CR_T4 ((uint8_t)0x10) /*!<Bit 4 */\r
+#define WWDG_CR_T5 ((uint8_t)0x20) /*!<Bit 5 */\r
+#define WWDG_CR_T6 ((uint8_t)0x40) /*!<Bit 6 */\r
+\r
+#define WWDG_CR_WDGA ((uint8_t)0x80) /*!<Activation bit */\r
+\r
+/******************* Bit definition for WWDG_CFR register *******************/\r
+#define WWDG_CFR_W ((uint16_t)0x007F) /*!<W[6:0] bits (7-bit window value) */\r
+#define WWDG_CFR_W0 ((uint16_t)0x0001) /*!<Bit 0 */\r
+#define WWDG_CFR_W1 ((uint16_t)0x0002) /*!<Bit 1 */\r
+#define WWDG_CFR_W2 ((uint16_t)0x0004) /*!<Bit 2 */\r
+#define WWDG_CFR_W3 ((uint16_t)0x0008) /*!<Bit 3 */\r
+#define WWDG_CFR_W4 ((uint16_t)0x0010) /*!<Bit 4 */\r
+#define WWDG_CFR_W5 ((uint16_t)0x0020) /*!<Bit 5 */\r
+#define WWDG_CFR_W6 ((uint16_t)0x0040) /*!<Bit 6 */\r
+\r
+#define WWDG_CFR_WDGTB ((uint16_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */\r
+#define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /*!<Bit 0 */\r
+#define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /*!<Bit 1 */\r
+\r
+#define WWDG_CFR_EWI ((uint16_t)0x0200) /*!<Early Wakeup Interrupt */\r
+\r
+/******************* Bit definition for WWDG_SR register ********************/\r
+#define WWDG_SR_EWIF ((uint8_t)0x01) /*!<Early Wakeup Interrupt Flag */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Flexible Static Memory Controller */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/****************** Bit definition for FSMC_BCR1 register *******************/\r
+#define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */\r
+#define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */\r
+\r
+#define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */\r
+#define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */\r
+#define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */\r
+\r
+#define FSMC_BCR1_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */\r
+#define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+\r
+#define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */\r
+#define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */\r
+#define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */\r
+#define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */\r
+#define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */\r
+#define FSMC_BCR1_WREN ((uint32_t)0x00001000) /*!<Write enable bit */\r
+#define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */\r
+#define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */\r
+#define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */\r
+\r
+/****************** Bit definition for FSMC_BCR2 register *******************/\r
+#define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */\r
+#define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */\r
+\r
+#define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */\r
+#define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */\r
+#define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */\r
+\r
+#define FSMC_BCR2_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */\r
+#define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+\r
+#define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */\r
+#define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */\r
+#define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */\r
+#define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */\r
+#define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */\r
+#define FSMC_BCR2_WREN ((uint32_t)0x00001000) /*!<Write enable bit */\r
+#define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */\r
+#define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */\r
+#define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */\r
+\r
+/****************** Bit definition for FSMC_BCR3 register *******************/\r
+#define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */\r
+#define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */\r
+\r
+#define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */\r
+#define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */\r
+#define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */\r
+\r
+#define FSMC_BCR3_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */\r
+#define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+\r
+#define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */\r
+#define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */\r
+#define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit. */\r
+#define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */\r
+#define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */\r
+#define FSMC_BCR3_WREN ((uint32_t)0x00001000) /*!<Write enable bit */\r
+#define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */\r
+#define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */\r
+#define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */\r
+\r
+/****************** Bit definition for FSMC_BCR4 register *******************/\r
+#define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */\r
+#define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */\r
+\r
+#define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */\r
+#define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */\r
+#define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */\r
+\r
+#define FSMC_BCR4_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */\r
+#define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+\r
+#define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */\r
+#define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */\r
+#define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */\r
+#define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */\r
+#define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */\r
+#define FSMC_BCR4_WREN ((uint32_t)0x00001000) /*!<Write enable bit */\r
+#define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */\r
+#define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */\r
+#define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */\r
+\r
+/****************** Bit definition for FSMC_BTR1 register ******************/\r
+#define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+#define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+#define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
+#define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */\r
+#define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
+#define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
+\r
+/****************** Bit definition for FSMC_BTR2 register *******************/\r
+#define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+#define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+#define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
+#define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */\r
+#define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
+#define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
+\r
+/******************* Bit definition for FSMC_BTR3 register *******************/\r
+#define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+#define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+#define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
+#define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */\r
+#define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
+#define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
+\r
+/****************** Bit definition for FSMC_BTR4 register *******************/\r
+#define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+#define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+#define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
+#define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */\r
+#define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
+#define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
+\r
+/****************** Bit definition for FSMC_BWTR1 register ******************/\r
+#define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+\r
+#define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+#define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
+\r
+#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+\r
+#define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+#define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
+#define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
+\r
+#define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */\r
+#define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+\r
+#define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
+#define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
+\r
+/****************** Bit definition for FSMC_BWTR2 register ******************/\r
+#define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+\r
+#define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+#define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
+\r
+#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+\r
+#define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1*/\r
+#define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
+#define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
+\r
+#define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */\r
+#define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+\r
+#define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
+#define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
+\r
+/****************** Bit definition for FSMC_BWTR3 register ******************/\r
+#define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+\r
+#define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+#define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
+\r
+#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+\r
+#define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+#define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
+#define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
+\r
+#define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */\r
+#define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+\r
+#define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
+#define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
+\r
+/****************** Bit definition for FSMC_BWTR4 register ******************/\r
+#define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+\r
+#define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+#define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
+\r
+#define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+\r
+#define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+#define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
+#define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
+\r
+#define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */\r
+#define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+\r
+#define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
+#define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
+\r
+/****************** Bit definition for FSMC_PCR2 register *******************/\r
+#define FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */\r
+#define FSMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */\r
+#define FSMC_PCR2_PTYP ((uint32_t)0x00000008) /*!<Memory type */\r
+\r
+#define FSMC_PCR2_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */\r
+#define FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+\r
+#define FSMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */\r
+\r
+#define FSMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */\r
+#define FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */\r
+#define FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */\r
+#define FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */\r
+#define FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */\r
+\r
+#define FSMC_PCR2_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */\r
+#define FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */\r
+#define FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */\r
+#define FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */\r
+#define FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */\r
+\r
+#define FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[1:0] bits (ECC page size) */\r
+#define FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */\r
+#define FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */\r
+#define FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */\r
+\r
+/****************** Bit definition for FSMC_PCR3 register *******************/\r
+#define FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */\r
+#define FSMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */\r
+#define FSMC_PCR3_PTYP ((uint32_t)0x00000008) /*!<Memory type */\r
+\r
+#define FSMC_PCR3_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */\r
+#define FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+\r
+#define FSMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */\r
+\r
+#define FSMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */\r
+#define FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */\r
+#define FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */\r
+#define FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */\r
+#define FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */\r
+\r
+#define FSMC_PCR3_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */\r
+#define FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */\r
+#define FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */\r
+#define FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */\r
+#define FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */\r
+\r
+#define FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */\r
+#define FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */\r
+#define FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */\r
+#define FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */\r
+\r
+/****************** Bit definition for FSMC_PCR4 register *******************/\r
+#define FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */\r
+#define FSMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */\r
+#define FSMC_PCR4_PTYP ((uint32_t)0x00000008) /*!<Memory type */\r
+\r
+#define FSMC_PCR4_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */\r
+#define FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+\r
+#define FSMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */\r
+\r
+#define FSMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */\r
+#define FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */\r
+#define FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */\r
+#define FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */\r
+#define FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */\r
+\r
+#define FSMC_PCR4_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */\r
+#define FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */\r
+#define FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */\r
+#define FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */\r
+#define FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */\r
+\r
+#define FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */\r
+#define FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */\r
+#define FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */\r
+#define FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */\r
+\r
+/******************* Bit definition for FSMC_SR2 register *******************/\r
+#define FSMC_SR2_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */\r
+#define FSMC_SR2_ILS ((uint8_t)0x02) /*!<Interrupt Level status */\r
+#define FSMC_SR2_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */\r
+#define FSMC_SR2_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */\r
+#define FSMC_SR2_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */\r
+#define FSMC_SR2_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */\r
+#define FSMC_SR2_FEMPT ((uint8_t)0x40) /*!<FIFO empty */\r
+\r
+/******************* Bit definition for FSMC_SR3 register *******************/\r
+#define FSMC_SR3_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */\r
+#define FSMC_SR3_ILS ((uint8_t)0x02) /*!<Interrupt Level status */\r
+#define FSMC_SR3_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */\r
+#define FSMC_SR3_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */\r
+#define FSMC_SR3_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */\r
+#define FSMC_SR3_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */\r
+#define FSMC_SR3_FEMPT ((uint8_t)0x40) /*!<FIFO empty */\r
+\r
+/******************* Bit definition for FSMC_SR4 register *******************/\r
+#define FSMC_SR4_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */\r
+#define FSMC_SR4_ILS ((uint8_t)0x02) /*!<Interrupt Level status */\r
+#define FSMC_SR4_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */\r
+#define FSMC_SR4_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */\r
+#define FSMC_SR4_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */\r
+#define FSMC_SR4_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */\r
+#define FSMC_SR4_FEMPT ((uint8_t)0x40) /*!<FIFO empty */\r
+\r
+/****************** Bit definition for FSMC_PMEM2 register ******************/\r
+#define FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */\r
+#define FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+#define FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */\r
+#define FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */\r
+#define FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */\r
+\r
+#define FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */\r
+#define FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+#define FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
+#define FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
+#define FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
+#define FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
+\r
+#define FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */\r
+#define FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+#define FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */\r
+#define FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */\r
+#define FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */\r
+#define FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */\r
+\r
+#define FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */\r
+#define FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+#define FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */\r
+#define FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */\r
+#define FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */\r
+#define FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */\r
+\r
+/****************** Bit definition for FSMC_PMEM3 register ******************/\r
+#define FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */\r
+#define FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+#define FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */\r
+#define FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */\r
+#define FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */\r
+\r
+#define FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */\r
+#define FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+#define FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
+#define FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
+#define FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
+#define FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
+\r
+#define FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */\r
+#define FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+#define FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */\r
+#define FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */\r
+#define FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */\r
+#define FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */\r
+\r
+#define FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */\r
+#define FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+#define FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */\r
+#define FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */\r
+#define FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */\r
+#define FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */\r
+\r
+/****************** Bit definition for FSMC_PMEM4 register ******************/\r
+#define FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */\r
+#define FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+#define FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */\r
+#define FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */\r
+#define FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */\r
+\r
+#define FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */\r
+#define FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+#define FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
+#define FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
+#define FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
+#define FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
+\r
+#define FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */\r
+#define FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+#define FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */\r
+#define FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */\r
+#define FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */\r
+#define FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */\r
+\r
+#define FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */\r
+#define FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+#define FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */\r
+#define FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */\r
+#define FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */\r
+#define FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */\r
+\r
+/****************** Bit definition for FSMC_PATT2 register ******************/\r
+#define FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */\r
+#define FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+#define FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */\r
+#define FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */\r
+#define FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */\r
+\r
+#define FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */\r
+#define FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+#define FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
+#define FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
+#define FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
+#define FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
+\r
+#define FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */\r
+#define FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+#define FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */\r
+#define FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */\r
+#define FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */\r
+#define FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */\r
+\r
+#define FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */\r
+#define FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+#define FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */\r
+#define FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */\r
+#define FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */\r
+#define FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */\r
+\r
+/****************** Bit definition for FSMC_PATT3 register ******************/\r
+#define FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */\r
+#define FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+#define FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */\r
+#define FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */\r
+#define FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */\r
+\r
+#define FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */\r
+#define FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+#define FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
+#define FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
+#define FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
+#define FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
+\r
+#define FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */\r
+#define FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+#define FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */\r
+#define FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */\r
+#define FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */\r
+#define FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */\r
+\r
+#define FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */\r
+#define FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+#define FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */\r
+#define FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */\r
+#define FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */\r
+#define FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */\r
+\r
+/****************** Bit definition for FSMC_PATT4 register ******************/\r
+#define FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */\r
+#define FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+#define FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */\r
+#define FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */\r
+#define FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */\r
+\r
+#define FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */\r
+#define FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+#define FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
+#define FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
+#define FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
+#define FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
+\r
+#define FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */\r
+#define FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+#define FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */\r
+#define FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */\r
+#define FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */\r
+#define FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */\r
+\r
+#define FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */\r
+#define FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+#define FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */\r
+#define FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */\r
+#define FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */\r
+#define FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */\r
+\r
+/****************** Bit definition for FSMC_PIO4 register *******************/\r
+#define FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!<IOSET4[7:0] bits (I/O 4 setup time) */\r
+#define FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+#define FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */\r
+#define FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */\r
+#define FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */\r
+\r
+#define FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */\r
+#define FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+#define FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
+#define FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
+#define FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
+#define FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
+\r
+#define FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */\r
+#define FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+#define FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */\r
+#define FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */\r
+#define FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */\r
+#define FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */\r
+\r
+#define FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */\r
+#define FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+#define FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */\r
+#define FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */\r
+#define FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */\r
+#define FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */\r
+\r
+/****************** Bit definition for FSMC_ECCR2 register ******************/\r
+#define FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!<ECC result */\r
+\r
+/****************** Bit definition for FSMC_ECCR3 register ******************/\r
+#define FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!<ECC result */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* SD host Interface */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/****************** Bit definition for SDIO_POWER register ******************/\r
+#define SDIO_POWER_PWRCTRL ((uint8_t)0x03) /*!<PWRCTRL[1:0] bits (Power supply control bits) */\r
+#define SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) /*!<Bit 0 */\r
+#define SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) /*!<Bit 1 */\r
+\r
+/****************** Bit definition for SDIO_CLKCR register ******************/\r
+#define SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) /*!<Clock divide factor */\r
+#define SDIO_CLKCR_CLKEN ((uint16_t)0x0100) /*!<Clock enable bit */\r
+#define SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) /*!<Power saving configuration bit */\r
+#define SDIO_CLKCR_BYPASS ((uint16_t)0x0400) /*!<Clock divider bypass enable bit */\r
+\r
+#define SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */\r
+#define SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) /*!<Bit 0 */\r
+#define SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) /*!<Bit 1 */\r
+\r
+#define SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) /*!<SDIO_CK dephasing selection bit */\r
+#define SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) /*!<HW Flow Control enable */\r
+\r
+/******************* Bit definition for SDIO_ARG register *******************/\r
+#define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!<Command argument */\r
+\r
+/******************* Bit definition for SDIO_CMD register *******************/\r
+#define SDIO_CMD_CMDINDEX ((uint16_t)0x003F) /*!<Command Index */\r
+\r
+#define SDIO_CMD_WAITRESP ((uint16_t)0x00C0) /*!<WAITRESP[1:0] bits (Wait for response bits) */\r
+#define SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) /*!< Bit 0 */\r
+#define SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) /*!< Bit 1 */\r
+\r
+#define SDIO_CMD_WAITINT ((uint16_t)0x0100) /*!<CPSM Waits for Interrupt Request */\r
+#define SDIO_CMD_WAITPEND ((uint16_t)0x0200) /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */\r
+#define SDIO_CMD_CPSMEN ((uint16_t)0x0400) /*!<Command path state machine (CPSM) Enable bit */\r
+#define SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) /*!<SD I/O suspend command */\r
+#define SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) /*!<Enable CMD completion */\r
+#define SDIO_CMD_NIEN ((uint16_t)0x2000) /*!<Not Interrupt Enable */\r
+#define SDIO_CMD_CEATACMD ((uint16_t)0x4000) /*!<CE-ATA command */\r
+\r
+/***************** Bit definition for SDIO_RESPCMD register *****************/\r
+#define SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) /*!<Response command index */\r
+\r
+/****************** Bit definition for SDIO_RESP0 register ******************/\r
+#define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!<Card Status */\r
+\r
+/****************** Bit definition for SDIO_RESP1 register ******************/\r
+#define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!<Card Status */\r
+\r
+/****************** Bit definition for SDIO_RESP2 register ******************/\r
+#define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!<Card Status */\r
+\r
+/****************** Bit definition for SDIO_RESP3 register ******************/\r
+#define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!<Card Status */\r
+\r
+/****************** Bit definition for SDIO_RESP4 register ******************/\r
+#define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!<Card Status */\r
+\r
+/****************** Bit definition for SDIO_DTIMER register *****************/\r
+#define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!<Data timeout period. */\r
+\r
+/****************** Bit definition for SDIO_DLEN register *******************/\r
+#define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!<Data length value */\r
+\r
+/****************** Bit definition for SDIO_DCTRL register ******************/\r
+#define SDIO_DCTRL_DTEN ((uint16_t)0x0001) /*!<Data transfer enabled bit */\r
+#define SDIO_DCTRL_DTDIR ((uint16_t)0x0002) /*!<Data transfer direction selection */\r
+#define SDIO_DCTRL_DTMODE ((uint16_t)0x0004) /*!<Data transfer mode selection */\r
+#define SDIO_DCTRL_DMAEN ((uint16_t)0x0008) /*!<DMA enabled bit */\r
+\r
+#define SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) /*!<DBLOCKSIZE[3:0] bits (Data block size) */\r
+#define SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+#define SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) /*!<Bit 2 */\r
+#define SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) /*!<Bit 3 */\r
+\r
+#define SDIO_DCTRL_RWSTART ((uint16_t)0x0100) /*!<Read wait start */\r
+#define SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) /*!<Read wait stop */\r
+#define SDIO_DCTRL_RWMOD ((uint16_t)0x0400) /*!<Read wait mode */\r
+#define SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) /*!<SD I/O enable functions */\r
+\r
+/****************** Bit definition for SDIO_DCOUNT register *****************/\r
+#define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!<Data count value */\r
+\r
+/****************** Bit definition for SDIO_STA register ********************/\r
+#define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!<Command response received (CRC check failed) */\r
+#define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!<Data block sent/received (CRC check failed) */\r
+#define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!<Command response timeout */\r
+#define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!<Data timeout */\r
+#define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!<Transmit FIFO underrun error */\r
+#define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!<Received FIFO overrun error */\r
+#define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!<Command response received (CRC check passed) */\r
+#define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!<Command sent (no response required) */\r
+#define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!<Data end (data counter, SDIDCOUNT, is zero) */\r
+#define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!<Start bit not detected on all data signals in wide bus mode */\r
+#define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!<Data block sent/received (CRC check passed) */\r
+#define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!<Command transfer in progress */\r
+#define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!<Data transmit in progress */\r
+#define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!<Data receive in progress */\r
+#define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */\r
+#define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */\r
+#define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!<Transmit FIFO full */\r
+#define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!<Receive FIFO full */\r
+#define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!<Transmit FIFO empty */\r
+#define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!<Receive FIFO empty */\r
+#define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!<Data available in transmit FIFO */\r
+#define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!<Data available in receive FIFO */\r
+#define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!<SDIO interrupt received */\r
+#define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received for CMD61 */\r
+\r
+/******************* Bit definition for SDIO_ICR register *******************/\r
+#define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!<CCRCFAIL flag clear bit */\r
+#define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!<DCRCFAIL flag clear bit */\r
+#define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!<CTIMEOUT flag clear bit */\r
+#define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!<DTIMEOUT flag clear bit */\r
+#define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!<TXUNDERR flag clear bit */\r
+#define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!<RXOVERR flag clear bit */\r
+#define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!<CMDREND flag clear bit */\r
+#define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!<CMDSENT flag clear bit */\r
+#define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!<DATAEND flag clear bit */\r
+#define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!<STBITERR flag clear bit */\r
+#define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!<DBCKEND flag clear bit */\r
+#define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!<SDIOIT flag clear bit */\r
+#define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!<CEATAEND flag clear bit */\r
+\r
+/****************** Bit definition for SDIO_MASK register *******************/\r
+#define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!<Command CRC Fail Interrupt Enable */\r
+#define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!<Data CRC Fail Interrupt Enable */\r
+#define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!<Command TimeOut Interrupt Enable */\r
+#define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!<Data TimeOut Interrupt Enable */\r
+#define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!<Tx FIFO UnderRun Error Interrupt Enable */\r
+#define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!<Rx FIFO OverRun Error Interrupt Enable */\r
+#define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!<Command Response Received Interrupt Enable */\r
+#define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!<Command Sent Interrupt Enable */\r
+#define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!<Data End Interrupt Enable */\r
+#define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!<Start Bit Error Interrupt Enable */\r
+#define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!<Data Block End Interrupt Enable */\r
+#define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!<CCommand Acting Interrupt Enable */\r
+#define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!<Data Transmit Acting Interrupt Enable */\r
+#define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!<Data receive acting interrupt enabled */\r
+#define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!<Tx FIFO Half Empty interrupt Enable */\r
+#define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!<Rx FIFO Half Full interrupt Enable */\r
+#define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!<Tx FIFO Full interrupt Enable */\r
+#define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!<Rx FIFO Full interrupt Enable */\r
+#define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!<Tx FIFO Empty interrupt Enable */\r
+#define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!<Rx FIFO Empty interrupt Enable */\r
+#define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!<Data available in Tx FIFO interrupt Enable */\r
+#define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!<Data available in Rx FIFO interrupt Enable */\r
+#define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!<SDIO Mode Interrupt Received interrupt Enable */\r
+#define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received Interrupt Enable */\r
+\r
+/***************** Bit definition for SDIO_FIFOCNT register *****************/\r
+#define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!<Remaining number of words to be written to or read from the FIFO */\r
+\r
+/****************** Bit definition for SDIO_FIFO register *******************/\r
+#define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!<Receive and transmit FIFO data */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* USB Device FS */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/*!<Endpoint-specific registers */\r
+/******************* Bit definition for USB_EP0R register *******************/\r
+#define USB_EP0R_EA ((uint16_t)0x000F) /*!<Endpoint Address */\r
+\r
+#define USB_EP0R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
+#define USB_EP0R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define USB_EP0R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+\r
+#define USB_EP0R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */\r
+#define USB_EP0R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */\r
+#define USB_EP0R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */\r
+\r
+#define USB_EP0R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */\r
+#define USB_EP0R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */\r
+#define USB_EP0R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */\r
+\r
+#define USB_EP0R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */\r
+\r
+#define USB_EP0R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
+#define USB_EP0R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define USB_EP0R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+\r
+#define USB_EP0R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */\r
+#define USB_EP0R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */\r
+\r
+/******************* Bit definition for USB_EP1R register *******************/\r
+#define USB_EP1R_EA ((uint16_t)0x000F) /*!<Endpoint Address */\r
+\r
+#define USB_EP1R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
+#define USB_EP1R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define USB_EP1R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+\r
+#define USB_EP1R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */\r
+#define USB_EP1R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */\r
+#define USB_EP1R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */\r
+\r
+#define USB_EP1R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */\r
+#define USB_EP1R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */\r
+#define USB_EP1R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */\r
+\r
+#define USB_EP1R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */\r
+\r
+#define USB_EP1R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
+#define USB_EP1R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define USB_EP1R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+\r
+#define USB_EP1R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */\r
+#define USB_EP1R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */\r
+\r
+/******************* Bit definition for USB_EP2R register *******************/\r
+#define USB_EP2R_EA ((uint16_t)0x000F) /*!<Endpoint Address */\r
+\r
+#define USB_EP2R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
+#define USB_EP2R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define USB_EP2R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+\r
+#define USB_EP2R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */\r
+#define USB_EP2R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */\r
+#define USB_EP2R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */\r
+\r
+#define USB_EP2R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */\r
+#define USB_EP2R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */\r
+#define USB_EP2R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */\r
+\r
+#define USB_EP2R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */\r
+\r
+#define USB_EP2R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
+#define USB_EP2R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define USB_EP2R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+\r
+#define USB_EP2R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */\r
+#define USB_EP2R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */\r
+\r
+/******************* Bit definition for USB_EP3R register *******************/\r
+#define USB_EP3R_EA ((uint16_t)0x000F) /*!<Endpoint Address */\r
+\r
+#define USB_EP3R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
+#define USB_EP3R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define USB_EP3R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+\r
+#define USB_EP3R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */\r
+#define USB_EP3R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */\r
+#define USB_EP3R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */\r
+\r
+#define USB_EP3R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */\r
+#define USB_EP3R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */\r
+#define USB_EP3R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */\r
+\r
+#define USB_EP3R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */\r
+\r
+#define USB_EP3R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
+#define USB_EP3R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define USB_EP3R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+\r
+#define USB_EP3R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */\r
+#define USB_EP3R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */\r
+\r
+/******************* Bit definition for USB_EP4R register *******************/\r
+#define USB_EP4R_EA ((uint16_t)0x000F) /*!<Endpoint Address */\r
+\r
+#define USB_EP4R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
+#define USB_EP4R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define USB_EP4R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+\r
+#define USB_EP4R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */\r
+#define USB_EP4R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */\r
+#define USB_EP4R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */\r
+\r
+#define USB_EP4R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */\r
+#define USB_EP4R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */\r
+#define USB_EP4R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */\r
+\r
+#define USB_EP4R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */\r
+\r
+#define USB_EP4R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
+#define USB_EP4R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define USB_EP4R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+\r
+#define USB_EP4R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */\r
+#define USB_EP4R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */\r
+\r
+/******************* Bit definition for USB_EP5R register *******************/\r
+#define USB_EP5R_EA ((uint16_t)0x000F) /*!<Endpoint Address */\r
+\r
+#define USB_EP5R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
+#define USB_EP5R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define USB_EP5R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+\r
+#define USB_EP5R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */\r
+#define USB_EP5R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */\r
+#define USB_EP5R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */\r
+\r
+#define USB_EP5R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */\r
+#define USB_EP5R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */\r
+#define USB_EP5R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */\r
+\r
+#define USB_EP5R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */\r
+\r
+#define USB_EP5R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
+#define USB_EP5R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define USB_EP5R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+\r
+#define USB_EP5R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */\r
+#define USB_EP5R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */\r
+\r
+/******************* Bit definition for USB_EP6R register *******************/\r
+#define USB_EP6R_EA ((uint16_t)0x000F) /*!<Endpoint Address */\r
+\r
+#define USB_EP6R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
+#define USB_EP6R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define USB_EP6R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+\r
+#define USB_EP6R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */\r
+#define USB_EP6R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */\r
+#define USB_EP6R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */\r
+\r
+#define USB_EP6R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */\r
+#define USB_EP6R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */\r
+#define USB_EP6R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */\r
+\r
+#define USB_EP6R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */\r
+\r
+#define USB_EP6R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
+#define USB_EP6R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define USB_EP6R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+\r
+#define USB_EP6R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */\r
+#define USB_EP6R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */\r
+\r
+/******************* Bit definition for USB_EP7R register *******************/\r
+#define USB_EP7R_EA ((uint16_t)0x000F) /*!<Endpoint Address */\r
+\r
+#define USB_EP7R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */\r
+#define USB_EP7R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define USB_EP7R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+\r
+#define USB_EP7R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */\r
+#define USB_EP7R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */\r
+#define USB_EP7R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */\r
+\r
+#define USB_EP7R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */\r
+#define USB_EP7R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */\r
+#define USB_EP7R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */\r
+\r
+#define USB_EP7R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */\r
+\r
+#define USB_EP7R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */\r
+#define USB_EP7R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define USB_EP7R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+\r
+#define USB_EP7R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */\r
+#define USB_EP7R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */\r
+\r
+/*!<Common registers */\r
+/******************* Bit definition for USB_CNTR register *******************/\r
+#define USB_CNTR_FRES ((uint16_t)0x0001) /*!<Force USB Reset */\r
+#define USB_CNTR_PDWN ((uint16_t)0x0002) /*!<Power down */\r
+#define USB_CNTR_LP_MODE ((uint16_t)0x0004) /*!<Low-power mode */\r
+#define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!<Force suspend */\r
+#define USB_CNTR_RESUME ((uint16_t)0x0010) /*!<Resume request */\r
+#define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!<Expected Start Of Frame Interrupt Mask */\r
+#define USB_CNTR_SOFM ((uint16_t)0x0200) /*!<Start Of Frame Interrupt Mask */\r
+#define USB_CNTR_RESETM ((uint16_t)0x0400) /*!<RESET Interrupt Mask */\r
+#define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!<Suspend mode Interrupt Mask */\r
+#define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!<Wakeup Interrupt Mask */\r
+#define USB_CNTR_ERRM ((uint16_t)0x2000) /*!<Error Interrupt Mask */\r
+#define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!<Packet Memory Area Over / Underrun Interrupt Mask */\r
+#define USB_CNTR_CTRM ((uint16_t)0x8000) /*!<Correct Transfer Interrupt Mask */\r
+\r
+/******************* Bit definition for USB_ISTR register *******************/\r
+#define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!<Endpoint Identifier */\r
+#define USB_ISTR_DIR ((uint16_t)0x0010) /*!<Direction of transaction */\r
+#define USB_ISTR_ESOF ((uint16_t)0x0100) /*!<Expected Start Of Frame */\r
+#define USB_ISTR_SOF ((uint16_t)0x0200) /*!<Start Of Frame */\r
+#define USB_ISTR_RESET ((uint16_t)0x0400) /*!<USB RESET request */\r
+#define USB_ISTR_SUSP ((uint16_t)0x0800) /*!<Suspend mode request */\r
+#define USB_ISTR_WKUP ((uint16_t)0x1000) /*!<Wake up */\r
+#define USB_ISTR_ERR ((uint16_t)0x2000) /*!<Error */\r
+#define USB_ISTR_PMAOVR ((uint16_t)0x4000) /*!<Packet Memory Area Over / Underrun */\r
+#define USB_ISTR_CTR ((uint16_t)0x8000) /*!<Correct Transfer */\r
+\r
+/******************* Bit definition for USB_FNR register ********************/\r
+#define USB_FNR_FN ((uint16_t)0x07FF) /*!<Frame Number */\r
+#define USB_FNR_LSOF ((uint16_t)0x1800) /*!<Lost SOF */\r
+#define USB_FNR_LCK ((uint16_t)0x2000) /*!<Locked */\r
+#define USB_FNR_RXDM ((uint16_t)0x4000) /*!<Receive Data - Line Status */\r
+#define USB_FNR_RXDP ((uint16_t)0x8000) /*!<Receive Data + Line Status */\r
+\r
+/****************** Bit definition for USB_DADDR register *******************/\r
+#define USB_DADDR_ADD ((uint8_t)0x7F) /*!<ADD[6:0] bits (Device Address) */\r
+#define USB_DADDR_ADD0 ((uint8_t)0x01) /*!<Bit 0 */\r
+#define USB_DADDR_ADD1 ((uint8_t)0x02) /*!<Bit 1 */\r
+#define USB_DADDR_ADD2 ((uint8_t)0x04) /*!<Bit 2 */\r
+#define USB_DADDR_ADD3 ((uint8_t)0x08) /*!<Bit 3 */\r
+#define USB_DADDR_ADD4 ((uint8_t)0x10) /*!<Bit 4 */\r
+#define USB_DADDR_ADD5 ((uint8_t)0x20) /*!<Bit 5 */\r
+#define USB_DADDR_ADD6 ((uint8_t)0x40) /*!<Bit 6 */\r
+\r
+#define USB_DADDR_EF ((uint8_t)0x80) /*!<Enable Function */\r
+\r
+/****************** Bit definition for USB_BTABLE register ******************/ \r
+#define USB_BTABLE_BTABLE ((uint16_t)0xFFF8) /*!<Buffer Table */\r
+\r
+/*!<Buffer descriptor table */\r
+/***************** Bit definition for USB_ADDR0_TX register *****************/\r
+#define USB_ADDR0_TX_ADDR0_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 0 */\r
+\r
+/***************** Bit definition for USB_ADDR1_TX register *****************/\r
+#define USB_ADDR1_TX_ADDR1_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 1 */\r
+\r
+/***************** Bit definition for USB_ADDR2_TX register *****************/\r
+#define USB_ADDR2_TX_ADDR2_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 2 */\r
+\r
+/***************** Bit definition for USB_ADDR3_TX register *****************/\r
+#define USB_ADDR3_TX_ADDR3_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 3 */\r
+\r
+/***************** Bit definition for USB_ADDR4_TX register *****************/\r
+#define USB_ADDR4_TX_ADDR4_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 4 */\r
+\r
+/***************** Bit definition for USB_ADDR5_TX register *****************/\r
+#define USB_ADDR5_TX_ADDR5_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 5 */\r
+\r
+/***************** Bit definition for USB_ADDR6_TX register *****************/\r
+#define USB_ADDR6_TX_ADDR6_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 6 */\r
+\r
+/***************** Bit definition for USB_ADDR7_TX register *****************/\r
+#define USB_ADDR7_TX_ADDR7_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 7 */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+/***************** Bit definition for USB_COUNT0_TX register ****************/\r
+#define USB_COUNT0_TX_COUNT0_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 0 */\r
+\r
+/***************** Bit definition for USB_COUNT1_TX register ****************/\r
+#define USB_COUNT1_TX_COUNT1_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 1 */\r
+\r
+/***************** Bit definition for USB_COUNT2_TX register ****************/\r
+#define USB_COUNT2_TX_COUNT2_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 2 */\r
+\r
+/***************** Bit definition for USB_COUNT3_TX register ****************/\r
+#define USB_COUNT3_TX_COUNT3_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 3 */\r
+\r
+/***************** Bit definition for USB_COUNT4_TX register ****************/\r
+#define USB_COUNT4_TX_COUNT4_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 4 */\r
+\r
+/***************** Bit definition for USB_COUNT5_TX register ****************/\r
+#define USB_COUNT5_TX_COUNT5_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 5 */\r
+\r
+/***************** Bit definition for USB_COUNT6_TX register ****************/\r
+#define USB_COUNT6_TX_COUNT6_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 6 */\r
+\r
+/***************** Bit definition for USB_COUNT7_TX register ****************/\r
+#define USB_COUNT7_TX_COUNT7_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 7 */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+/**************** Bit definition for USB_COUNT0_TX_0 register ***************/\r
+#define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 0 (low) */\r
+\r
+/**************** Bit definition for USB_COUNT0_TX_1 register ***************/\r
+#define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 0 (high) */\r
+\r
+/**************** Bit definition for USB_COUNT1_TX_0 register ***************/\r
+#define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 1 (low) */\r
+\r
+/**************** Bit definition for USB_COUNT1_TX_1 register ***************/\r
+#define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 1 (high) */\r
+\r
+/**************** Bit definition for USB_COUNT2_TX_0 register ***************/\r
+#define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 2 (low) */\r
+\r
+/**************** Bit definition for USB_COUNT2_TX_1 register ***************/\r
+#define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 2 (high) */\r
+\r
+/**************** Bit definition for USB_COUNT3_TX_0 register ***************/\r
+#define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint16_t)0x000003FF) /*!<Transmission Byte Count 3 (low) */\r
+\r
+/**************** Bit definition for USB_COUNT3_TX_1 register ***************/\r
+#define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint16_t)0x03FF0000) /*!<Transmission Byte Count 3 (high) */\r
+\r
+/**************** Bit definition for USB_COUNT4_TX_0 register ***************/\r
+#define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 4 (low) */\r
+\r
+/**************** Bit definition for USB_COUNT4_TX_1 register ***************/\r
+#define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 4 (high) */\r
+\r
+/**************** Bit definition for USB_COUNT5_TX_0 register ***************/\r
+#define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 5 (low) */\r
+\r
+/**************** Bit definition for USB_COUNT5_TX_1 register ***************/\r
+#define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 5 (high) */\r
+\r
+/**************** Bit definition for USB_COUNT6_TX_0 register ***************/\r
+#define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 6 (low) */\r
+\r
+/**************** Bit definition for USB_COUNT6_TX_1 register ***************/\r
+#define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 6 (high) */\r
+\r
+/**************** Bit definition for USB_COUNT7_TX_0 register ***************/\r
+#define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 7 (low) */\r
+\r
+/**************** Bit definition for USB_COUNT7_TX_1 register ***************/\r
+#define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 7 (high) */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+/***************** Bit definition for USB_ADDR0_RX register *****************/\r
+#define USB_ADDR0_RX_ADDR0_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 0 */\r
+\r
+/***************** Bit definition for USB_ADDR1_RX register *****************/\r
+#define USB_ADDR1_RX_ADDR1_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 1 */\r
+\r
+/***************** Bit definition for USB_ADDR2_RX register *****************/\r
+#define USB_ADDR2_RX_ADDR2_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 2 */\r
+\r
+/***************** Bit definition for USB_ADDR3_RX register *****************/\r
+#define USB_ADDR3_RX_ADDR3_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 3 */\r
+\r
+/***************** Bit definition for USB_ADDR4_RX register *****************/\r
+#define USB_ADDR4_RX_ADDR4_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 4 */\r
+\r
+/***************** Bit definition for USB_ADDR5_RX register *****************/\r
+#define USB_ADDR5_RX_ADDR5_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 5 */\r
+\r
+/***************** Bit definition for USB_ADDR6_RX register *****************/\r
+#define USB_ADDR6_RX_ADDR6_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 6 */\r
+\r
+/***************** Bit definition for USB_ADDR7_RX register *****************/\r
+#define USB_ADDR7_RX_ADDR7_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 7 */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+/***************** Bit definition for USB_COUNT0_RX register ****************/\r
+#define USB_COUNT0_RX_COUNT0_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */\r
+\r
+#define USB_COUNT0_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */\r
+#define USB_COUNT0_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */\r
+#define USB_COUNT0_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */\r
+#define USB_COUNT0_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */\r
+#define USB_COUNT0_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */\r
+#define USB_COUNT0_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */\r
+\r
+#define USB_COUNT0_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */\r
+\r
+/***************** Bit definition for USB_COUNT1_RX register ****************/\r
+#define USB_COUNT1_RX_COUNT1_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */\r
+\r
+#define USB_COUNT1_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */\r
+#define USB_COUNT1_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */\r
+#define USB_COUNT1_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */\r
+#define USB_COUNT1_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */\r
+#define USB_COUNT1_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */\r
+#define USB_COUNT1_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */\r
+\r
+#define USB_COUNT1_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */\r
+\r
+/***************** Bit definition for USB_COUNT2_RX register ****************/\r
+#define USB_COUNT2_RX_COUNT2_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */\r
+\r
+#define USB_COUNT2_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */\r
+#define USB_COUNT2_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */\r
+#define USB_COUNT2_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */\r
+#define USB_COUNT2_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */\r
+#define USB_COUNT2_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */\r
+#define USB_COUNT2_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */\r
+\r
+#define USB_COUNT2_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */\r
+\r
+/***************** Bit definition for USB_COUNT3_RX register ****************/\r
+#define USB_COUNT3_RX_COUNT3_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */\r
+\r
+#define USB_COUNT3_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */\r
+#define USB_COUNT3_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */\r
+#define USB_COUNT3_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */\r
+#define USB_COUNT3_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */\r
+#define USB_COUNT3_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */\r
+#define USB_COUNT3_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */\r
+\r
+#define USB_COUNT3_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */\r
+\r
+/***************** Bit definition for USB_COUNT4_RX register ****************/\r
+#define USB_COUNT4_RX_COUNT4_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */\r
+\r
+#define USB_COUNT4_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */\r
+#define USB_COUNT4_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */\r
+#define USB_COUNT4_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */\r
+#define USB_COUNT4_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */\r
+#define USB_COUNT4_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */\r
+#define USB_COUNT4_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */\r
+\r
+#define USB_COUNT4_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */\r
+\r
+/***************** Bit definition for USB_COUNT5_RX register ****************/\r
+#define USB_COUNT5_RX_COUNT5_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */\r
+\r
+#define USB_COUNT5_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */\r
+#define USB_COUNT5_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */\r
+#define USB_COUNT5_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */\r
+#define USB_COUNT5_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */\r
+#define USB_COUNT5_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */\r
+#define USB_COUNT5_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */\r
+\r
+#define USB_COUNT5_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */\r
+\r
+/***************** Bit definition for USB_COUNT6_RX register ****************/\r
+#define USB_COUNT6_RX_COUNT6_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */\r
+\r
+#define USB_COUNT6_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */\r
+#define USB_COUNT6_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */\r
+#define USB_COUNT6_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */\r
+#define USB_COUNT6_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */\r
+#define USB_COUNT6_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */\r
+#define USB_COUNT6_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */\r
+\r
+#define USB_COUNT6_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */\r
+\r
+/***************** Bit definition for USB_COUNT7_RX register ****************/\r
+#define USB_COUNT7_RX_COUNT7_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */\r
+\r
+#define USB_COUNT7_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */\r
+#define USB_COUNT7_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */\r
+#define USB_COUNT7_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */\r
+#define USB_COUNT7_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */\r
+#define USB_COUNT7_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */\r
+#define USB_COUNT7_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */\r
+\r
+#define USB_COUNT7_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+/**************** Bit definition for USB_COUNT0_RX_0 register ***************/\r
+#define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */\r
+\r
+#define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */\r
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */\r
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */\r
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */\r
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */\r
+\r
+#define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */\r
+\r
+/**************** Bit definition for USB_COUNT0_RX_1 register ***************/\r
+#define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */\r
+\r
+#define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 1 */\r
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */\r
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */\r
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */\r
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */\r
+\r
+#define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */\r
+\r
+/**************** Bit definition for USB_COUNT1_RX_0 register ***************/\r
+#define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */\r
+\r
+#define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */\r
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */\r
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */\r
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */\r
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */\r
+\r
+#define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */\r
+\r
+/**************** Bit definition for USB_COUNT1_RX_1 register ***************/\r
+#define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */\r
+\r
+#define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */\r
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */\r
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */\r
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */\r
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */\r
+\r
+#define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */\r
+\r
+/**************** Bit definition for USB_COUNT2_RX_0 register ***************/\r
+#define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */\r
+\r
+#define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */\r
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */\r
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */\r
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */\r
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */\r
+\r
+#define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */\r
+\r
+/**************** Bit definition for USB_COUNT2_RX_1 register ***************/\r
+#define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */\r
+\r
+#define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */\r
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */\r
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */\r
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */\r
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */\r
+\r
+#define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */\r
+\r
+/**************** Bit definition for USB_COUNT3_RX_0 register ***************/\r
+#define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */\r
+\r
+#define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */\r
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */\r
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */\r
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */\r
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */\r
+\r
+#define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */\r
+\r
+/**************** Bit definition for USB_COUNT3_RX_1 register ***************/\r
+#define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */\r
+\r
+#define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */\r
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */\r
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */\r
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */\r
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */\r
+\r
+#define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */\r
+\r
+/**************** Bit definition for USB_COUNT4_RX_0 register ***************/\r
+#define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */\r
+\r
+#define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */\r
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */\r
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */\r
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */\r
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */\r
+\r
+#define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */\r
+\r
+/**************** Bit definition for USB_COUNT4_RX_1 register ***************/\r
+#define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */\r
+\r
+#define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */\r
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */\r
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */\r
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */\r
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */\r
+\r
+#define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */\r
+\r
+/**************** Bit definition for USB_COUNT5_RX_0 register ***************/\r
+#define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */\r
+\r
+#define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */\r
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */\r
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */\r
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */\r
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */\r
+\r
+#define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */\r
+\r
+/**************** Bit definition for USB_COUNT5_RX_1 register ***************/\r
+#define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */\r
+\r
+#define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */\r
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */\r
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */\r
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */\r
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */\r
+\r
+#define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */\r
+\r
+/*************** Bit definition for USB_COUNT6_RX_0 register ***************/\r
+#define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */\r
+\r
+#define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */\r
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */\r
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */\r
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */\r
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */\r
+\r
+#define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */\r
+\r
+/**************** Bit definition for USB_COUNT6_RX_1 register ***************/\r
+#define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */\r
+\r
+#define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */\r
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */\r
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */\r
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */\r
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */\r
+\r
+#define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */\r
+\r
+/*************** Bit definition for USB_COUNT7_RX_0 register ****************/\r
+#define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */\r
+\r
+#define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\r
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */\r
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */\r
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */\r
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */\r
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */\r
+\r
+#define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */\r
+\r
+/*************** Bit definition for USB_COUNT7_RX_1 register ****************/\r
+#define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */\r
+\r
+#define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\r
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */\r
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */\r
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */\r
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */\r
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */\r
+\r
+#define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Controller Area Network */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/*!<CAN control and status registers */\r
+/******************* Bit definition for CAN_MCR register ********************/\r
+#define CAN_MCR_INRQ ((uint16_t)0x0001) /*!<Initialization Request */\r
+#define CAN_MCR_SLEEP ((uint16_t)0x0002) /*!<Sleep Mode Request */\r
+#define CAN_MCR_TXFP ((uint16_t)0x0004) /*!<Transmit FIFO Priority */\r
+#define CAN_MCR_RFLM ((uint16_t)0x0008) /*!<Receive FIFO Locked Mode */\r
+#define CAN_MCR_NART ((uint16_t)0x0010) /*!<No Automatic Retransmission */\r
+#define CAN_MCR_AWUM ((uint16_t)0x0020) /*!<Automatic Wakeup Mode */\r
+#define CAN_MCR_ABOM ((uint16_t)0x0040) /*!<Automatic Bus-Off Management */\r
+#define CAN_MCR_TTCM ((uint16_t)0x0080) /*!<Time Triggered Communication Mode */\r
+#define CAN_MCR_RESET ((uint16_t)0x8000) /*!<bxCAN software master reset */\r
+\r
+/******************* Bit definition for CAN_MSR register ********************/\r
+#define CAN_MSR_INAK ((uint16_t)0x0001) /*!<Initialization Acknowledge */\r
+#define CAN_MSR_SLAK ((uint16_t)0x0002) /*!<Sleep Acknowledge */\r
+#define CAN_MSR_ERRI ((uint16_t)0x0004) /*!<Error Interrupt */\r
+#define CAN_MSR_WKUI ((uint16_t)0x0008) /*!<Wakeup Interrupt */\r
+#define CAN_MSR_SLAKI ((uint16_t)0x0010) /*!<Sleep Acknowledge Interrupt */\r
+#define CAN_MSR_TXM ((uint16_t)0x0100) /*!<Transmit Mode */\r
+#define CAN_MSR_RXM ((uint16_t)0x0200) /*!<Receive Mode */\r
+#define CAN_MSR_SAMP ((uint16_t)0x0400) /*!<Last Sample Point */\r
+#define CAN_MSR_RX ((uint16_t)0x0800) /*!<CAN Rx Signal */\r
+\r
+/******************* Bit definition for CAN_TSR register ********************/\r
+#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */\r
+#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */\r
+#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */\r
+#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */\r
+#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */\r
+#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */\r
+#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */\r
+#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */\r
+#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */\r
+#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */\r
+#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */\r
+#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */\r
+#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */\r
+#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */\r
+#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */\r
+#define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */\r
+\r
+#define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */\r
+#define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */\r
+#define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */\r
+#define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */\r
+\r
+#define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */\r
+#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */\r
+#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */\r
+#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */\r
+\r
+/******************* Bit definition for CAN_RF0R register *******************/\r
+#define CAN_RF0R_FMP0 ((uint8_t)0x03) /*!<FIFO 0 Message Pending */\r
+#define CAN_RF0R_FULL0 ((uint8_t)0x08) /*!<FIFO 0 Full */\r
+#define CAN_RF0R_FOVR0 ((uint8_t)0x10) /*!<FIFO 0 Overrun */\r
+#define CAN_RF0R_RFOM0 ((uint8_t)0x20) /*!<Release FIFO 0 Output Mailbox */\r
+\r
+/******************* Bit definition for CAN_RF1R register *******************/\r
+#define CAN_RF1R_FMP1 ((uint8_t)0x03) /*!<FIFO 1 Message Pending */\r
+#define CAN_RF1R_FULL1 ((uint8_t)0x08) /*!<FIFO 1 Full */\r
+#define CAN_RF1R_FOVR1 ((uint8_t)0x10) /*!<FIFO 1 Overrun */\r
+#define CAN_RF1R_RFOM1 ((uint8_t)0x20) /*!<Release FIFO 1 Output Mailbox */\r
+\r
+/******************** Bit definition for CAN_IER register *******************/\r
+#define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */\r
+#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */\r
+#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */\r
+#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */\r
+#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */\r
+#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */\r
+#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */\r
+#define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */\r
+#define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */\r
+#define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */\r
+#define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */\r
+#define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */\r
+#define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */\r
+#define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */\r
+\r
+/******************** Bit definition for CAN_ESR register *******************/\r
+#define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */\r
+#define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */\r
+#define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */\r
+\r
+#define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */\r
+#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+\r
+#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */\r
+#define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */\r
+\r
+/******************* Bit definition for CAN_BTR register ********************/\r
+#define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */\r
+#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */\r
+#define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */\r
+#define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */\r
+#define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */\r
+#define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */\r
+\r
+/*!<Mailbox registers */\r
+/****************** Bit definition for CAN_TI0R register ********************/\r
+#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */\r
+#define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */\r
+#define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */\r
+#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */\r
+#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */\r
+\r
+/****************** Bit definition for CAN_TDT0R register *******************/\r
+#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */\r
+#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */\r
+#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */\r
+\r
+/****************** Bit definition for CAN_TDL0R register *******************/\r
+#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */\r
+#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */\r
+#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */\r
+#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */\r
+\r
+/****************** Bit definition for CAN_TDH0R register *******************/\r
+#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */\r
+#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */\r
+#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */\r
+#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */\r
+\r
+/******************* Bit definition for CAN_TI1R register *******************/\r
+#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */\r
+#define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */\r
+#define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */\r
+#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */\r
+#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */\r
+\r
+/******************* Bit definition for CAN_TDT1R register ******************/\r
+#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */\r
+#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */\r
+#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */\r
+\r
+/******************* Bit definition for CAN_TDL1R register ******************/\r
+#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */\r
+#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */\r
+#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */\r
+#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */\r
+\r
+/******************* Bit definition for CAN_TDH1R register ******************/\r
+#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */\r
+#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */\r
+#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */\r
+#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */\r
+\r
+/******************* Bit definition for CAN_TI2R register *******************/\r
+#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */\r
+#define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */\r
+#define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */\r
+#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */\r
+#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */\r
+\r
+/******************* Bit definition for CAN_TDT2R register ******************/ \r
+#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */\r
+#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */\r
+#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */\r
+\r
+/******************* Bit definition for CAN_TDL2R register ******************/\r
+#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */\r
+#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */\r
+#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */\r
+#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */\r
+\r
+/******************* Bit definition for CAN_TDH2R register ******************/\r
+#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */\r
+#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */\r
+#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */\r
+#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */\r
+\r
+/******************* Bit definition for CAN_RI0R register *******************/\r
+#define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */\r
+#define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */\r
+#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */\r
+#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */\r
+\r
+/******************* Bit definition for CAN_RDT0R register ******************/\r
+#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */\r
+#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */\r
+#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */\r
+\r
+/******************* Bit definition for CAN_RDL0R register ******************/\r
+#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */\r
+#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */\r
+#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */\r
+#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */\r
+\r
+/******************* Bit definition for CAN_RDH0R register ******************/\r
+#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */\r
+#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */\r
+#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */\r
+#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */\r
+\r
+/******************* Bit definition for CAN_RI1R register *******************/\r
+#define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */\r
+#define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */\r
+#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */\r
+#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */\r
+\r
+/******************* Bit definition for CAN_RDT1R register ******************/\r
+#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */\r
+#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */\r
+#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */\r
+\r
+/******************* Bit definition for CAN_RDL1R register ******************/\r
+#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */\r
+#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */\r
+#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */\r
+#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */\r
+\r
+/******************* Bit definition for CAN_RDH1R register ******************/\r
+#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */\r
+#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */\r
+#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */\r
+#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */\r
+\r
+/*!<CAN filter registers */\r
+/******************* Bit definition for CAN_FMR register ********************/\r
+#define CAN_FMR_FINIT ((uint8_t)0x01) /*!<Filter Init Mode */\r
+\r
+/******************* Bit definition for CAN_FM1R register *******************/\r
+#define CAN_FM1R_FBM ((uint16_t)0x3FFF) /*!<Filter Mode */\r
+#define CAN_FM1R_FBM0 ((uint16_t)0x0001) /*!<Filter Init Mode bit 0 */\r
+#define CAN_FM1R_FBM1 ((uint16_t)0x0002) /*!<Filter Init Mode bit 1 */\r
+#define CAN_FM1R_FBM2 ((uint16_t)0x0004) /*!<Filter Init Mode bit 2 */\r
+#define CAN_FM1R_FBM3 ((uint16_t)0x0008) /*!<Filter Init Mode bit 3 */\r
+#define CAN_FM1R_FBM4 ((uint16_t)0x0010) /*!<Filter Init Mode bit 4 */\r
+#define CAN_FM1R_FBM5 ((uint16_t)0x0020) /*!<Filter Init Mode bit 5 */\r
+#define CAN_FM1R_FBM6 ((uint16_t)0x0040) /*!<Filter Init Mode bit 6 */\r
+#define CAN_FM1R_FBM7 ((uint16_t)0x0080) /*!<Filter Init Mode bit 7 */\r
+#define CAN_FM1R_FBM8 ((uint16_t)0x0100) /*!<Filter Init Mode bit 8 */\r
+#define CAN_FM1R_FBM9 ((uint16_t)0x0200) /*!<Filter Init Mode bit 9 */\r
+#define CAN_FM1R_FBM10 ((uint16_t)0x0400) /*!<Filter Init Mode bit 10 */\r
+#define CAN_FM1R_FBM11 ((uint16_t)0x0800) /*!<Filter Init Mode bit 11 */\r
+#define CAN_FM1R_FBM12 ((uint16_t)0x1000) /*!<Filter Init Mode bit 12 */\r
+#define CAN_FM1R_FBM13 ((uint16_t)0x2000) /*!<Filter Init Mode bit 13 */\r
+\r
+/******************* Bit definition for CAN_FS1R register *******************/\r
+#define CAN_FS1R_FSC ((uint16_t)0x3FFF) /*!<Filter Scale Configuration */\r
+#define CAN_FS1R_FSC0 ((uint16_t)0x0001) /*!<Filter Scale Configuration bit 0 */\r
+#define CAN_FS1R_FSC1 ((uint16_t)0x0002) /*!<Filter Scale Configuration bit 1 */\r
+#define CAN_FS1R_FSC2 ((uint16_t)0x0004) /*!<Filter Scale Configuration bit 2 */\r
+#define CAN_FS1R_FSC3 ((uint16_t)0x0008) /*!<Filter Scale Configuration bit 3 */\r
+#define CAN_FS1R_FSC4 ((uint16_t)0x0010) /*!<Filter Scale Configuration bit 4 */\r
+#define CAN_FS1R_FSC5 ((uint16_t)0x0020) /*!<Filter Scale Configuration bit 5 */\r
+#define CAN_FS1R_FSC6 ((uint16_t)0x0040) /*!<Filter Scale Configuration bit 6 */\r
+#define CAN_FS1R_FSC7 ((uint16_t)0x0080) /*!<Filter Scale Configuration bit 7 */\r
+#define CAN_FS1R_FSC8 ((uint16_t)0x0100) /*!<Filter Scale Configuration bit 8 */\r
+#define CAN_FS1R_FSC9 ((uint16_t)0x0200) /*!<Filter Scale Configuration bit 9 */\r
+#define CAN_FS1R_FSC10 ((uint16_t)0x0400) /*!<Filter Scale Configuration bit 10 */\r
+#define CAN_FS1R_FSC11 ((uint16_t)0x0800) /*!<Filter Scale Configuration bit 11 */\r
+#define CAN_FS1R_FSC12 ((uint16_t)0x1000) /*!<Filter Scale Configuration bit 12 */\r
+#define CAN_FS1R_FSC13 ((uint16_t)0x2000) /*!<Filter Scale Configuration bit 13 */\r
+\r
+/****************** Bit definition for CAN_FFA1R register *******************/\r
+#define CAN_FFA1R_FFA ((uint16_t)0x3FFF) /*!<Filter FIFO Assignment */\r
+#define CAN_FFA1R_FFA0 ((uint16_t)0x0001) /*!<Filter FIFO Assignment for Filter 0 */\r
+#define CAN_FFA1R_FFA1 ((uint16_t)0x0002) /*!<Filter FIFO Assignment for Filter 1 */\r
+#define CAN_FFA1R_FFA2 ((uint16_t)0x0004) /*!<Filter FIFO Assignment for Filter 2 */\r
+#define CAN_FFA1R_FFA3 ((uint16_t)0x0008) /*!<Filter FIFO Assignment for Filter 3 */\r
+#define CAN_FFA1R_FFA4 ((uint16_t)0x0010) /*!<Filter FIFO Assignment for Filter 4 */\r
+#define CAN_FFA1R_FFA5 ((uint16_t)0x0020) /*!<Filter FIFO Assignment for Filter 5 */\r
+#define CAN_FFA1R_FFA6 ((uint16_t)0x0040) /*!<Filter FIFO Assignment for Filter 6 */\r
+#define CAN_FFA1R_FFA7 ((uint16_t)0x0080) /*!<Filter FIFO Assignment for Filter 7 */\r
+#define CAN_FFA1R_FFA8 ((uint16_t)0x0100) /*!<Filter FIFO Assignment for Filter 8 */\r
+#define CAN_FFA1R_FFA9 ((uint16_t)0x0200) /*!<Filter FIFO Assignment for Filter 9 */\r
+#define CAN_FFA1R_FFA10 ((uint16_t)0x0400) /*!<Filter FIFO Assignment for Filter 10 */\r
+#define CAN_FFA1R_FFA11 ((uint16_t)0x0800) /*!<Filter FIFO Assignment for Filter 11 */\r
+#define CAN_FFA1R_FFA12 ((uint16_t)0x1000) /*!<Filter FIFO Assignment for Filter 12 */\r
+#define CAN_FFA1R_FFA13 ((uint16_t)0x2000) /*!<Filter FIFO Assignment for Filter 13 */\r
+\r
+/******************* Bit definition for CAN_FA1R register *******************/\r
+#define CAN_FA1R_FACT ((uint16_t)0x3FFF) /*!<Filter Active */\r
+#define CAN_FA1R_FACT0 ((uint16_t)0x0001) /*!<Filter 0 Active */\r
+#define CAN_FA1R_FACT1 ((uint16_t)0x0002) /*!<Filter 1 Active */\r
+#define CAN_FA1R_FACT2 ((uint16_t)0x0004) /*!<Filter 2 Active */\r
+#define CAN_FA1R_FACT3 ((uint16_t)0x0008) /*!<Filter 3 Active */\r
+#define CAN_FA1R_FACT4 ((uint16_t)0x0010) /*!<Filter 4 Active */\r
+#define CAN_FA1R_FACT5 ((uint16_t)0x0020) /*!<Filter 5 Active */\r
+#define CAN_FA1R_FACT6 ((uint16_t)0x0040) /*!<Filter 6 Active */\r
+#define CAN_FA1R_FACT7 ((uint16_t)0x0080) /*!<Filter 7 Active */\r
+#define CAN_FA1R_FACT8 ((uint16_t)0x0100) /*!<Filter 8 Active */\r
+#define CAN_FA1R_FACT9 ((uint16_t)0x0200) /*!<Filter 9 Active */\r
+#define CAN_FA1R_FACT10 ((uint16_t)0x0400) /*!<Filter 10 Active */\r
+#define CAN_FA1R_FACT11 ((uint16_t)0x0800) /*!<Filter 11 Active */\r
+#define CAN_FA1R_FACT12 ((uint16_t)0x1000) /*!<Filter 12 Active */\r
+#define CAN_FA1R_FACT13 ((uint16_t)0x2000) /*!<Filter 13 Active */\r
+\r
+/******************* Bit definition for CAN_F0R1 register *******************/\r
+#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F1R1 register *******************/\r
+#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F2R1 register *******************/\r
+#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F3R1 register *******************/\r
+#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F4R1 register *******************/\r
+#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F5R1 register *******************/\r
+#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F6R1 register *******************/\r
+#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F7R1 register *******************/\r
+#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F8R1 register *******************/\r
+#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F9R1 register *******************/\r
+#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F10R1 register ******************/\r
+#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F11R1 register ******************/\r
+#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F12R1 register ******************/\r
+#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F13R1 register ******************/\r
+#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F0R2 register *******************/\r
+#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F1R2 register *******************/\r
+#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F2R2 register *******************/\r
+#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F3R2 register *******************/\r
+#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F4R2 register *******************/\r
+#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F5R2 register *******************/\r
+#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F6R2 register *******************/\r
+#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F7R2 register *******************/\r
+#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F8R2 register *******************/\r
+#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F9R2 register *******************/\r
+#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F10R2 register ******************/\r
+#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F11R2 register ******************/\r
+#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F12R2 register ******************/\r
+#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F13R2 register ******************/\r
+#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Serial Peripheral Interface */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for SPI_CR1 register ********************/\r
+#define SPI_CR1_CPHA ((uint16_t)0x0001) /*!<Clock Phase */\r
+#define SPI_CR1_CPOL ((uint16_t)0x0002) /*!<Clock Polarity */\r
+#define SPI_CR1_MSTR ((uint16_t)0x0004) /*!<Master Selection */\r
+\r
+#define SPI_CR1_BR ((uint16_t)0x0038) /*!<BR[2:0] bits (Baud Rate Control) */\r
+#define SPI_CR1_BR_0 ((uint16_t)0x0008) /*!<Bit 0 */\r
+#define SPI_CR1_BR_1 ((uint16_t)0x0010) /*!<Bit 1 */\r
+#define SPI_CR1_BR_2 ((uint16_t)0x0020) /*!<Bit 2 */\r
+\r
+#define SPI_CR1_SPE ((uint16_t)0x0040) /*!<SPI Enable */\r
+#define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /*!<Frame Format */\r
+#define SPI_CR1_SSI ((uint16_t)0x0100) /*!<Internal slave select */\r
+#define SPI_CR1_SSM ((uint16_t)0x0200) /*!<Software slave management */\r
+#define SPI_CR1_RXONLY ((uint16_t)0x0400) /*!<Receive only */\r
+#define SPI_CR1_DFF ((uint16_t)0x0800) /*!<Data Frame Format */\r
+#define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /*!<Transmit CRC next */\r
+#define SPI_CR1_CRCEN ((uint16_t)0x2000) /*!<Hardware CRC calculation enable */\r
+#define SPI_CR1_BIDIOE ((uint16_t)0x4000) /*!<Output enable in bidirectional mode */\r
+#define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /*!<Bidirectional data mode enable */\r
+\r
+/******************* Bit definition for SPI_CR2 register ********************/\r
+#define SPI_CR2_RXDMAEN ((uint8_t)0x01) /*!<Rx Buffer DMA Enable */\r
+#define SPI_CR2_TXDMAEN ((uint8_t)0x02) /*!<Tx Buffer DMA Enable */\r
+#define SPI_CR2_SSOE ((uint8_t)0x04) /*!<SS Output Enable */\r
+#define SPI_CR2_ERRIE ((uint8_t)0x20) /*!<Error Interrupt Enable */\r
+#define SPI_CR2_RXNEIE ((uint8_t)0x40) /*!<RX buffer Not Empty Interrupt Enable */\r
+#define SPI_CR2_TXEIE ((uint8_t)0x80) /*!<Tx buffer Empty Interrupt Enable */\r
+\r
+/******************** Bit definition for SPI_SR register ********************/\r
+#define SPI_SR_RXNE ((uint8_t)0x01) /*!<Receive buffer Not Empty */\r
+#define SPI_SR_TXE ((uint8_t)0x02) /*!<Transmit buffer Empty */\r
+#define SPI_SR_CHSIDE ((uint8_t)0x04) /*!<Channel side */\r
+#define SPI_SR_UDR ((uint8_t)0x08) /*!<Underrun flag */\r
+#define SPI_SR_CRCERR ((uint8_t)0x10) /*!<CRC Error flag */\r
+#define SPI_SR_MODF ((uint8_t)0x20) /*!<Mode fault */\r
+#define SPI_SR_OVR ((uint8_t)0x40) /*!<Overrun flag */\r
+#define SPI_SR_BSY ((uint8_t)0x80) /*!<Busy flag */\r
+\r
+/******************** Bit definition for SPI_DR register ********************/\r
+#define SPI_DR_DR ((uint16_t)0xFFFF) /*!<Data Register */\r
+\r
+/******************* Bit definition for SPI_CRCPR register ******************/\r
+#define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /*!<CRC polynomial register */\r
+\r
+/****************** Bit definition for SPI_RXCRCR register ******************/\r
+#define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /*!<Rx CRC Register */\r
+\r
+/****************** Bit definition for SPI_TXCRCR register ******************/\r
+#define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /*!<Tx CRC Register */\r
+\r
+/****************** Bit definition for SPI_I2SCFGR register *****************/\r
+#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /*!<Channel length (number of bits per audio channel) */\r
+\r
+#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /*!<DATLEN[1:0] bits (Data length to be transferred) */\r
+#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /*!<Bit 0 */\r
+#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /*!<Bit 1 */\r
+\r
+#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /*!<steady state clock polarity */\r
+\r
+#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /*!<I2SSTD[1:0] bits (I2S standard selection) */\r
+#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+\r
+#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /*!<PCM frame synchronization */\r
+\r
+#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */\r
+#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
+#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
+\r
+#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /*!<I2S Enable */\r
+#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /*!<I2S mode selection */\r
+\r
+/****************** Bit definition for SPI_I2SPR register *******************/\r
+#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /*!<I2S Linear prescaler */\r
+#define SPI_I2SPR_ODD ((uint16_t)0x0100) /*!<Odd factor for the prescaler */\r
+#define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /*!<Master Clock Output Enable */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Inter-integrated Circuit Interface */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for I2C_CR1 register ********************/\r
+#define I2C_CR1_PE ((uint16_t)0x0001) /*!<Peripheral Enable */\r
+#define I2C_CR1_SMBUS ((uint16_t)0x0002) /*!<SMBus Mode */\r
+#define I2C_CR1_SMBTYPE ((uint16_t)0x0008) /*!<SMBus Type */\r
+#define I2C_CR1_ENARP ((uint16_t)0x0010) /*!<ARP Enable */\r
+#define I2C_CR1_ENPEC ((uint16_t)0x0020) /*!<PEC Enable */\r
+#define I2C_CR1_ENGC ((uint16_t)0x0040) /*!<General Call Enable */\r
+#define I2C_CR1_NOSTRETCH ((uint16_t)0x0080) /*!<Clock Stretching Disable (Slave mode) */\r
+#define I2C_CR1_START ((uint16_t)0x0100) /*!<Start Generation */\r
+#define I2C_CR1_STOP ((uint16_t)0x0200) /*!<Stop Generation */\r
+#define I2C_CR1_ACK ((uint16_t)0x0400) /*!<Acknowledge Enable */\r
+#define I2C_CR1_POS ((uint16_t)0x0800) /*!<Acknowledge/PEC Position (for data reception) */\r
+#define I2C_CR1_PEC ((uint16_t)0x1000) /*!<Packet Error Checking */\r
+#define I2C_CR1_ALERT ((uint16_t)0x2000) /*!<SMBus Alert */\r
+#define I2C_CR1_SWRST ((uint16_t)0x8000) /*!<Software Reset */\r
+\r
+/******************* Bit definition for I2C_CR2 register ********************/\r
+#define I2C_CR2_FREQ ((uint16_t)0x003F) /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */\r
+#define I2C_CR2_FREQ_0 ((uint16_t)0x0001) /*!<Bit 0 */\r
+#define I2C_CR2_FREQ_1 ((uint16_t)0x0002) /*!<Bit 1 */\r
+#define I2C_CR2_FREQ_2 ((uint16_t)0x0004) /*!<Bit 2 */\r
+#define I2C_CR2_FREQ_3 ((uint16_t)0x0008) /*!<Bit 3 */\r
+#define I2C_CR2_FREQ_4 ((uint16_t)0x0010) /*!<Bit 4 */\r
+#define I2C_CR2_FREQ_5 ((uint16_t)0x0020) /*!<Bit 5 */\r
+\r
+#define I2C_CR2_ITERREN ((uint16_t)0x0100) /*!<Error Interrupt Enable */\r
+#define I2C_CR2_ITEVTEN ((uint16_t)0x0200) /*!<Event Interrupt Enable */\r
+#define I2C_CR2_ITBUFEN ((uint16_t)0x0400) /*!<Buffer Interrupt Enable */\r
+#define I2C_CR2_DMAEN ((uint16_t)0x0800) /*!<DMA Requests Enable */\r
+#define I2C_CR2_LAST ((uint16_t)0x1000) /*!<DMA Last Transfer */\r
+\r
+/******************* Bit definition for I2C_OAR1 register *******************/\r
+#define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) /*!<Interface Address */\r
+#define I2C_OAR1_ADD8_9 ((uint16_t)0x0300) /*!<Interface Address */\r
+\r
+#define I2C_OAR1_ADD0 ((uint16_t)0x0001) /*!<Bit 0 */\r
+#define I2C_OAR1_ADD1 ((uint16_t)0x0002) /*!<Bit 1 */\r
+#define I2C_OAR1_ADD2 ((uint16_t)0x0004) /*!<Bit 2 */\r
+#define I2C_OAR1_ADD3 ((uint16_t)0x0008) /*!<Bit 3 */\r
+#define I2C_OAR1_ADD4 ((uint16_t)0x0010) /*!<Bit 4 */\r
+#define I2C_OAR1_ADD5 ((uint16_t)0x0020) /*!<Bit 5 */\r
+#define I2C_OAR1_ADD6 ((uint16_t)0x0040) /*!<Bit 6 */\r
+#define I2C_OAR1_ADD7 ((uint16_t)0x0080) /*!<Bit 7 */\r
+#define I2C_OAR1_ADD8 ((uint16_t)0x0100) /*!<Bit 8 */\r
+#define I2C_OAR1_ADD9 ((uint16_t)0x0200) /*!<Bit 9 */\r
+\r
+#define I2C_OAR1_ADDMODE ((uint16_t)0x8000) /*!<Addressing Mode (Slave mode) */\r
+\r
+/******************* Bit definition for I2C_OAR2 register *******************/\r
+#define I2C_OAR2_ENDUAL ((uint8_t)0x01) /*!<Dual addressing mode enable */\r
+#define I2C_OAR2_ADD2 ((uint8_t)0xFE) /*!<Interface address */\r
+\r
+/******************** Bit definition for I2C_DR register ********************/\r
+#define I2C_DR_DR ((uint8_t)0xFF) /*!<8-bit Data Register */\r
+\r
+/******************* Bit definition for I2C_SR1 register ********************/\r
+#define I2C_SR1_SB ((uint16_t)0x0001) /*!<Start Bit (Master mode) */\r
+#define I2C_SR1_ADDR ((uint16_t)0x0002) /*!<Address sent (master mode)/matched (slave mode) */\r
+#define I2C_SR1_BTF ((uint16_t)0x0004) /*!<Byte Transfer Finished */\r
+#define I2C_SR1_ADD10 ((uint16_t)0x0008) /*!<10-bit header sent (Master mode) */\r
+#define I2C_SR1_STOPF ((uint16_t)0x0010) /*!<Stop detection (Slave mode) */\r
+#define I2C_SR1_RXNE ((uint16_t)0x0040) /*!<Data Register not Empty (receivers) */\r
+#define I2C_SR1_TXE ((uint16_t)0x0080) /*!<Data Register Empty (transmitters) */\r
+#define I2C_SR1_BERR ((uint16_t)0x0100) /*!<Bus Error */\r
+#define I2C_SR1_ARLO ((uint16_t)0x0200) /*!<Arbitration Lost (master mode) */\r
+#define I2C_SR1_AF ((uint16_t)0x0400) /*!<Acknowledge Failure */\r
+#define I2C_SR1_OVR ((uint16_t)0x0800) /*!<Overrun/Underrun */\r
+#define I2C_SR1_PECERR ((uint16_t)0x1000) /*!<PEC Error in reception */\r
+#define I2C_SR1_TIMEOUT ((uint16_t)0x4000) /*!<Timeout or Tlow Error */\r
+#define I2C_SR1_SMBALERT ((uint16_t)0x8000) /*!<SMBus Alert */\r
+\r
+/******************* Bit definition for I2C_SR2 register ********************/\r
+#define I2C_SR2_MSL ((uint16_t)0x0001) /*!<Master/Slave */\r
+#define I2C_SR2_BUSY ((uint16_t)0x0002) /*!<Bus Busy */\r
+#define I2C_SR2_TRA ((uint16_t)0x0004) /*!<Transmitter/Receiver */\r
+#define I2C_SR2_GENCALL ((uint16_t)0x0010) /*!<General Call Address (Slave mode) */\r
+#define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) /*!<SMBus Device Default Address (Slave mode) */\r
+#define I2C_SR2_SMBHOST ((uint16_t)0x0040) /*!<SMBus Host Header (Slave mode) */\r
+#define I2C_SR2_DUALF ((uint16_t)0x0080) /*!<Dual Flag (Slave mode) */\r
+#define I2C_SR2_PEC ((uint16_t)0xFF00) /*!<Packet Error Checking Register */\r
+\r
+/******************* Bit definition for I2C_CCR register ********************/\r
+#define I2C_CCR_CCR ((uint16_t)0x0FFF) /*!<Clock Control Register in Fast/Standard mode (Master mode) */\r
+#define I2C_CCR_DUTY ((uint16_t)0x4000) /*!<Fast Mode Duty Cycle */\r
+#define I2C_CCR_FS ((uint16_t)0x8000) /*!<I2C Master Mode Selection */\r
+\r
+/****************** Bit definition for I2C_TRISE register *******************/\r
+#define I2C_TRISE_TRISE ((uint8_t)0x3F) /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Universal Synchronous Asynchronous Receiver Transmitter */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for USART_SR register *******************/\r
+#define USART_SR_PE ((uint16_t)0x0001) /*!<Parity Error */\r
+#define USART_SR_FE ((uint16_t)0x0002) /*!<Framing Error */\r
+#define USART_SR_NE ((uint16_t)0x0004) /*!<Noise Error Flag */\r
+#define USART_SR_ORE ((uint16_t)0x0008) /*!<OverRun Error */\r
+#define USART_SR_IDLE ((uint16_t)0x0010) /*!<IDLE line detected */\r
+#define USART_SR_RXNE ((uint16_t)0x0020) /*!<Read Data Register Not Empty */\r
+#define USART_SR_TC ((uint16_t)0x0040) /*!<Transmission Complete */\r
+#define USART_SR_TXE ((uint16_t)0x0080) /*!<Transmit Data Register Empty */\r
+#define USART_SR_LBD ((uint16_t)0x0100) /*!<LIN Break Detection Flag */\r
+#define USART_SR_CTS ((uint16_t)0x0200) /*!<CTS Flag */\r
+\r
+/******************* Bit definition for USART_DR register *******************/\r
+#define USART_DR_DR ((uint16_t)0x01FF) /*!<Data value */\r
+\r
+/****************** Bit definition for USART_BRR register *******************/\r
+#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /*!<Fraction of USARTDIV */\r
+#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /*!<Mantissa of USARTDIV */\r
+\r
+/****************** Bit definition for USART_CR1 register *******************/\r
+#define USART_CR1_SBK ((uint16_t)0x0001) /*!<Send Break */\r
+#define USART_CR1_RWU ((uint16_t)0x0002) /*!<Receiver wakeup */\r
+#define USART_CR1_RE ((uint16_t)0x0004) /*!<Receiver Enable */\r
+#define USART_CR1_TE ((uint16_t)0x0008) /*!<Transmitter Enable */\r
+#define USART_CR1_IDLEIE ((uint16_t)0x0010) /*!<IDLE Interrupt Enable */\r
+#define USART_CR1_RXNEIE ((uint16_t)0x0020) /*!<RXNE Interrupt Enable */\r
+#define USART_CR1_TCIE ((uint16_t)0x0040) /*!<Transmission Complete Interrupt Enable */\r
+#define USART_CR1_TXEIE ((uint16_t)0x0080) /*!<PE Interrupt Enable */\r
+#define USART_CR1_PEIE ((uint16_t)0x0100) /*!<PE Interrupt Enable */\r
+#define USART_CR1_PS ((uint16_t)0x0200) /*!<Parity Selection */\r
+#define USART_CR1_PCE ((uint16_t)0x0400) /*!<Parity Control Enable */\r
+#define USART_CR1_WAKE ((uint16_t)0x0800) /*!<Wakeup method */\r
+#define USART_CR1_M ((uint16_t)0x1000) /*!<Word length */\r
+#define USART_CR1_UE ((uint16_t)0x2000) /*!<USART Enable */\r
+\r
+/****************** Bit definition for USART_CR2 register *******************/\r
+#define USART_CR2_ADD ((uint16_t)0x000F) /*!<Address of the USART node */\r
+#define USART_CR2_LBDL ((uint16_t)0x0020) /*!<LIN Break Detection Length */\r
+#define USART_CR2_LBDIE ((uint16_t)0x0040) /*!<LIN Break Detection Interrupt Enable */\r
+#define USART_CR2_LBCL ((uint16_t)0x0100) /*!<Last Bit Clock pulse */\r
+#define USART_CR2_CPHA ((uint16_t)0x0200) /*!<Clock Phase */\r
+#define USART_CR2_CPOL ((uint16_t)0x0400) /*!<Clock Polarity */\r
+#define USART_CR2_CLKEN ((uint16_t)0x0800) /*!<Clock Enable */\r
+\r
+#define USART_CR2_STOP ((uint16_t)0x3000) /*!<STOP[1:0] bits (STOP bits) */\r
+#define USART_CR2_STOP_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define USART_CR2_STOP_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+\r
+#define USART_CR2_LINEN ((uint16_t)0x4000) /*!<LIN mode enable */\r
+\r
+/****************** Bit definition for USART_CR3 register *******************/\r
+#define USART_CR3_EIE ((uint16_t)0x0001) /*!<Error Interrupt Enable */\r
+#define USART_CR3_IREN ((uint16_t)0x0002) /*!<IrDA mode Enable */\r
+#define USART_CR3_IRLP ((uint16_t)0x0004) /*!<IrDA Low-Power */\r
+#define USART_CR3_HDSEL ((uint16_t)0x0008) /*!<Half-Duplex Selection */\r
+#define USART_CR3_NACK ((uint16_t)0x0010) /*!<Smartcard NACK enable */\r
+#define USART_CR3_SCEN ((uint16_t)0x0020) /*!<Smartcard mode enable */\r
+#define USART_CR3_DMAR ((uint16_t)0x0040) /*!<DMA Enable Receiver */\r
+#define USART_CR3_DMAT ((uint16_t)0x0080) /*!<DMA Enable Transmitter */\r
+#define USART_CR3_RTSE ((uint16_t)0x0100) /*!<RTS Enable */\r
+#define USART_CR3_CTSE ((uint16_t)0x0200) /*!<CTS Enable */\r
+#define USART_CR3_CTSIE ((uint16_t)0x0400) /*!<CTS Interrupt Enable */\r
+\r
+/****************** Bit definition for USART_GTPR register ******************/\r
+#define USART_GTPR_PSC ((uint16_t)0x00FF) /*!<PSC[7:0] bits (Prescaler value) */\r
+#define USART_GTPR_PSC_0 ((uint16_t)0x0001) /*!<Bit 0 */\r
+#define USART_GTPR_PSC_1 ((uint16_t)0x0002) /*!<Bit 1 */\r
+#define USART_GTPR_PSC_2 ((uint16_t)0x0004) /*!<Bit 2 */\r
+#define USART_GTPR_PSC_3 ((uint16_t)0x0008) /*!<Bit 3 */\r
+#define USART_GTPR_PSC_4 ((uint16_t)0x0010) /*!<Bit 4 */\r
+#define USART_GTPR_PSC_5 ((uint16_t)0x0020) /*!<Bit 5 */\r
+#define USART_GTPR_PSC_6 ((uint16_t)0x0040) /*!<Bit 6 */\r
+#define USART_GTPR_PSC_7 ((uint16_t)0x0080) /*!<Bit 7 */\r
+\r
+#define USART_GTPR_GT ((uint16_t)0xFF00) /*!<Guard time value */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Debug MCU */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/**************** Bit definition for DBGMCU_IDCODE register *****************/\r
+#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!<Device Identifier */\r
+\r
+#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!<REV_ID[15:0] bits (Revision Identifier) */\r
+#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!<Bit 4 */\r
+#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!<Bit 5 */\r
+#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!<Bit 6 */\r
+#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!<Bit 7 */\r
+#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!<Bit 8 */\r
+#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!<Bit 9 */\r
+#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!<Bit 10 */\r
+#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!<Bit 11 */\r
+#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!<Bit 12 */\r
+#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!<Bit 13 */\r
+#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!<Bit 14 */\r
+#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!<Bit 15 */\r
+\r
+/****************** Bit definition for DBGMCU_CR register *******************/\r
+#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /*!<Debug Sleep Mode */\r
+#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!<Debug Stop Mode */\r
+#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!<Debug Standby mode */\r
+#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) /*!<Trace Pin Assignment Control */\r
+\r
+#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) /*!<TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */\r
+#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /*!<Bit 0 */\r
+#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /*!<Bit 1 */\r
+\r
+#define DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100) /*!<Debug Independent Watchdog stopped when Core is halted */\r
+#define DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200) /*!<Debug Window Watchdog stopped when Core is halted */\r
+#define DBGMCU_CR_DBG_TIM1_STOP ((uint32_t)0x00000400) /*!<TIM1 counter stopped when core is halted */\r
+#define DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800) /*!<TIM2 counter stopped when core is halted */\r
+#define DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000) /*!<TIM3 counter stopped when core is halted */\r
+#define DBGMCU_CR_DBG_TIM4_STOP ((uint32_t)0x00002000) /*!<TIM4 counter stopped when core is halted */\r
+#define DBGMCU_CR_DBG_CAN1_STOP ((uint32_t)0x00004000) /*!<Debug CAN1 stopped when Core is halted */\r
+#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) /*!<SMBUS timeout mode stopped when Core is halted */\r
+#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) /*!<SMBUS timeout mode stopped when Core is halted */\r
+#define DBGMCU_CR_DBG_TIM8_STOP ((uint32_t)0x00020000) /*!<TIM8 counter stopped when core is halted */\r
+#define DBGMCU_CR_DBG_TIM5_STOP ((uint32_t)0x00040000) /*!<TIM5 counter stopped when core is halted */\r
+#define DBGMCU_CR_DBG_TIM6_STOP ((uint32_t)0x00080000) /*!<TIM6 counter stopped when core is halted */\r
+#define DBGMCU_CR_DBG_TIM7_STOP ((uint32_t)0x00100000) /*!<TIM7 counter stopped when core is halted */\r
+#define DBGMCU_CR_DBG_CAN2_STOP ((uint32_t)0x00200000) /*!<Debug CAN2 stopped when Core is halted */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* FLASH and Option Bytes Registers */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************* Bit definition for FLASH_ACR register ******************/\r
+#define FLASH_ACR_LATENCY ((uint8_t)0x03) /*!<LATENCY[2:0] bits (Latency) */\r
+#define FLASH_ACR_LATENCY_0 ((uint8_t)0x00) /*!<Bit 0 */\r
+#define FLASH_ACR_LATENCY_1 ((uint8_t)0x01) /*!<Bit 0 */\r
+#define FLASH_ACR_LATENCY_2 ((uint8_t)0x02) /*!<Bit 1 */\r
+\r
+#define FLASH_ACR_HLFCYA ((uint8_t)0x08) /*!<Flash Half Cycle Access Enable */\r
+#define FLASH_ACR_PRFTBE ((uint8_t)0x10) /*!<Prefetch Buffer Enable */\r
+#define FLASH_ACR_PRFTBS ((uint8_t)0x20) /*!<Prefetch Buffer Status */\r
+\r
+/****************** Bit definition for FLASH_KEYR register ******************/\r
+#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!<FPEC Key */\r
+\r
+/***************** Bit definition for FLASH_OPTKEYR register ****************/\r
+#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!<Option Byte Key */\r
+\r
+/****************** Bit definition for FLASH_SR register *******************/\r
+#define FLASH_SR_BSY ((uint8_t)0x01) /*!<Busy */\r
+#define FLASH_SR_PGERR ((uint8_t)0x04) /*!<Programming Error */\r
+#define FLASH_SR_WRPRTERR ((uint8_t)0x10) /*!<Write Protection Error */\r
+#define FLASH_SR_EOP ((uint8_t)0x20) /*!<End of operation */\r
+\r
+/******************* Bit definition for FLASH_CR register *******************/\r
+#define FLASH_CR_PG ((uint16_t)0x0001) /*!<Programming */\r
+#define FLASH_CR_PER ((uint16_t)0x0002) /*!<Page Erase */\r
+#define FLASH_CR_MER ((uint16_t)0x0004) /*!<Mass Erase */\r
+#define FLASH_CR_OPTPG ((uint16_t)0x0010) /*!<Option Byte Programming */\r
+#define FLASH_CR_OPTER ((uint16_t)0x0020) /*!<Option Byte Erase */\r
+#define FLASH_CR_STRT ((uint16_t)0x0040) /*!<Start */\r
+#define FLASH_CR_LOCK ((uint16_t)0x0080) /*!<Lock */\r
+#define FLASH_CR_OPTWRE ((uint16_t)0x0200) /*!<Option Bytes Write Enable */\r
+#define FLASH_CR_ERRIE ((uint16_t)0x0400) /*!<Error Interrupt Enable */\r
+#define FLASH_CR_EOPIE ((uint16_t)0x1000) /*!<End of operation interrupt enable */\r
+\r
+/******************* Bit definition for FLASH_AR register *******************/\r
+#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!<Flash Address */\r
+\r
+/****************** Bit definition for FLASH_OBR register *******************/\r
+#define FLASH_OBR_OPTERR ((uint16_t)0x0001) /*!<Option Byte Error */\r
+#define FLASH_OBR_RDPRT ((uint16_t)0x0002) /*!<Read protection */\r
+\r
+#define FLASH_OBR_USER ((uint16_t)0x03FC) /*!<User Option Bytes */\r
+#define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /*!<WDG_SW */\r
+#define FLASH_OBR_nRST_STOP ((uint16_t)0x0008) /*!<nRST_STOP */\r
+#define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) /*!<nRST_STDBY */\r
+#define FLASH_OBR_Notused ((uint16_t)0x03E0) /*!<Not used */\r
+\r
+/****************** Bit definition for FLASH_WRPR register ******************/\r
+#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!<Write Protect */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+/****************** Bit definition for FLASH_RDP register *******************/\r
+#define FLASH_RDP_RDP ((uint32_t)0x000000FF) /*!<Read protection option byte */\r
+#define FLASH_RDP_nRDP ((uint32_t)0x0000FF00) /*!<Read protection complemented option byte */\r
+\r
+/****************** Bit definition for FLASH_USER register ******************/\r
+#define FLASH_USER_USER ((uint32_t)0x00FF0000) /*!<User option byte */\r
+#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /*!<User complemented option byte */\r
+\r
+/****************** Bit definition for FLASH_Data0 register *****************/\r
+#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /*!<User data storage option byte */\r
+#define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /*!<User data storage complemented option byte */\r
+\r
+/****************** Bit definition for FLASH_Data1 register *****************/\r
+#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /*!<User data storage option byte */\r
+#define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /*!<User data storage complemented option byte */\r
+\r
+/****************** Bit definition for FLASH_WRP0 register ******************/\r
+#define FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) /*!<Flash memory write protection option bytes */\r
+#define FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!<Flash memory write protection complemented option bytes */\r
+\r
+/****************** Bit definition for FLASH_WRP1 register ******************/\r
+#define FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!<Flash memory write protection option bytes */\r
+#define FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!<Flash memory write protection complemented option bytes */\r
+\r
+/****************** Bit definition for FLASH_WRP2 register ******************/\r
+#define FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) /*!<Flash memory write protection option bytes */\r
+#define FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!<Flash memory write protection complemented option bytes */\r
+\r
+/****************** Bit definition for FLASH_WRP3 register ******************/\r
+#define FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!<Flash memory write protection option bytes */\r
+#define FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!<Flash memory write protection complemented option bytes */\r
+\r
+#ifdef STM32F10X_CL\r
+/******************************************************************************/\r
+/* Ethernet MAC Registers bits definitions */\r
+/******************************************************************************/\r
+/* Bit definition for Ethernet MAC Control Register register */\r
+#define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */\r
+#define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */\r
+#define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */\r
+ #define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */\r
+ #define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */\r
+ #define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */\r
+ #define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */\r
+ #define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */ \r
+ #define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */\r
+ #define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */\r
+ #define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */ \r
+#define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */\r
+#define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */\r
+#define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */\r
+#define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */\r
+#define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */\r
+#define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */\r
+#define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */\r
+#define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */\r
+#define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling\r
+ a transmission attempt during retries after a collision: 0 =< r <2^k */\r
+ #define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */\r
+ #define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */\r
+ #define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */\r
+ #define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */ \r
+#define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */\r
+#define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */\r
+#define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */\r
+\r
+/* Bit definition for Ethernet MAC Frame Filter Register */\r
+#define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */ \r
+#define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */ \r
+#define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */ \r
+#define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */ \r
+#define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */\r
+ #define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */\r
+ #define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */\r
+ #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */ \r
+#define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */ \r
+#define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */ \r
+#define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */ \r
+#define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */ \r
+#define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */\r
+#define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */\r
+\r
+/* Bit definition for Ethernet MAC Hash Table High Register */\r
+#define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */\r
+\r
+/* Bit definition for Ethernet MAC Hash Table Low Register */\r
+#define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */\r
+\r
+/* Bit definition for Ethernet MAC MII Address Register */\r
+#define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */ \r
+#define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */ \r
+#define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */ \r
+ #define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-72 MHz; MDC clock= HCLK/42 */\r
+ #define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */\r
+ #define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */\r
+#define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */ \r
+#define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */ \r
+ \r
+/* Bit definition for Ethernet MAC MII Data Register */\r
+#define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */\r
+\r
+/* Bit definition for Ethernet MAC Flow Control Register */\r
+#define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */\r
+#define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */\r
+#define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */\r
+ #define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */\r
+ #define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */\r
+ #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */\r
+ #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */ \r
+#define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */\r
+#define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */\r
+#define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */\r
+#define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */\r
+\r
+/* Bit definition for Ethernet MAC VLAN Tag Register */\r
+#define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */\r
+#define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */\r
+\r
+/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ \r
+#define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */\r
+/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.\r
+ Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */\r
+/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask\r
+ Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask\r
+ Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask\r
+ Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask\r
+ Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - \r
+ RSVD - Filter1 Command - RSVD - Filter0 Command\r
+ Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset\r
+ Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16\r
+ Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */\r
+\r
+/* Bit definition for Ethernet MAC PMT Control and Status Register */ \r
+#define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */\r
+#define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */\r
+#define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */\r
+#define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */\r
+#define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */\r
+#define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */\r
+#define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */\r
+\r
+/* Bit definition for Ethernet MAC Status Register */\r
+#define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */\r
+#define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */\r
+#define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */\r
+#define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */\r
+#define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */\r
+\r
+/* Bit definition for Ethernet MAC Interrupt Mask Register */\r
+#define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */\r
+#define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */\r
+\r
+/* Bit definition for Ethernet MAC Address0 High Register */\r
+#define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */\r
+\r
+/* Bit definition for Ethernet MAC Address0 Low Register */\r
+#define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */\r
+\r
+/* Bit definition for Ethernet MAC Address1 High Register */\r
+#define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */\r
+#define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */\r
+#define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */\r
+ #define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */\r
+ #define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */\r
+ #define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */\r
+ #define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */\r
+ #define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */\r
+ #define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */ \r
+#define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */\r
+\r
+/* Bit definition for Ethernet MAC Address1 Low Register */\r
+#define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */\r
+\r
+/* Bit definition for Ethernet MAC Address2 High Register */\r
+#define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */\r
+#define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */\r
+#define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */\r
+ #define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */\r
+ #define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */\r
+ #define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */\r
+ #define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */\r
+ #define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */\r
+ #define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */\r
+#define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */\r
+\r
+/* Bit definition for Ethernet MAC Address2 Low Register */\r
+#define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */\r
+\r
+/* Bit definition for Ethernet MAC Address3 High Register */\r
+#define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */\r
+#define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */\r
+#define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */\r
+ #define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */\r
+ #define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */\r
+ #define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */\r
+ #define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */\r
+ #define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */\r
+ #define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */\r
+#define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */\r
+\r
+/* Bit definition for Ethernet MAC Address3 Low Register */\r
+#define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */\r
+\r
+/******************************************************************************/\r
+/* Ethernet MMC Registers bits definition */\r
+/******************************************************************************/\r
+\r
+/* Bit definition for Ethernet MMC Contol Register */\r
+#define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */\r
+#define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */\r
+#define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */\r
+#define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */\r
+\r
+/* Bit definition for Ethernet MMC Receive Interrupt Register */\r
+#define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */\r
+#define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */\r
+#define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */\r
+\r
+/* Bit definition for Ethernet MMC Transmit Interrupt Register */\r
+#define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */\r
+#define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */\r
+#define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */\r
+\r
+/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */\r
+#define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */\r
+#define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */\r
+#define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */\r
+\r
+/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */\r
+#define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */\r
+#define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */\r
+#define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */\r
+\r
+/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */\r
+#define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */\r
+\r
+/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */\r
+#define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */\r
+\r
+/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */\r
+#define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */\r
+\r
+/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */\r
+#define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */\r
+\r
+/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */\r
+#define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */\r
+\r
+/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */\r
+#define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */\r
+\r
+/******************************************************************************/\r
+/* Ethernet PTP Registers bits definition */\r
+/******************************************************************************/\r
+\r
+/* Bit definition for Ethernet PTP Time Stamp Contol Register */\r
+#define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */\r
+#define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */\r
+#define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */\r
+#define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */\r
+#define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */\r
+#define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */\r
+\r
+/* Bit definition for Ethernet PTP Sub-Second Increment Register */\r
+#define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */\r
+\r
+/* Bit definition for Ethernet PTP Time Stamp High Register */\r
+#define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */\r
+\r
+/* Bit definition for Ethernet PTP Time Stamp Low Register */\r
+#define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */\r
+#define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */\r
+\r
+/* Bit definition for Ethernet PTP Time Stamp High Update Register */\r
+#define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */\r
+\r
+/* Bit definition for Ethernet PTP Time Stamp Low Update Register */\r
+#define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */\r
+#define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */\r
+\r
+/* Bit definition for Ethernet PTP Time Stamp Addend Register */\r
+#define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */\r
+\r
+/* Bit definition for Ethernet PTP Target Time High Register */\r
+#define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */\r
+\r
+/* Bit definition for Ethernet PTP Target Time Low Register */\r
+#define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */\r
+\r
+/******************************************************************************/\r
+/* Ethernet DMA Registers bits definition */\r
+/******************************************************************************/\r
+\r
+/* Bit definition for Ethernet DMA Bus Mode Register */\r
+#define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */\r
+#define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */\r
+#define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */\r
+#define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */\r
+ #define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */\r
+ #define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */\r
+ #define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */\r
+ #define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */\r
+ #define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */\r
+ #define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ \r
+ #define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */\r
+ #define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */\r
+ #define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */\r
+ #define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */\r
+ #define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */\r
+ #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ \r
+#define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */\r
+#define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */\r
+ #define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */\r
+ #define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */\r
+ #define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */\r
+ #define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */ \r
+#define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */\r
+ #define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */\r
+ #define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */\r
+ #define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */\r
+ #define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */\r
+ #define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */\r
+ #define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ \r
+ #define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */\r
+ #define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */\r
+ #define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */\r
+ #define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */\r
+ #define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */\r
+ #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */\r
+#define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */\r
+#define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */\r
+#define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */\r
+\r
+/* Bit definition for Ethernet DMA Transmit Poll Demand Register */\r
+#define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */\r
+\r
+/* Bit definition for Ethernet DMA Receive Poll Demand Register */\r
+#define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */\r
+\r
+/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */\r
+#define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */\r
+\r
+/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */\r
+#define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */\r
+\r
+/* Bit definition for Ethernet DMA Status Register */\r
+#define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */\r
+#define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */\r
+#define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */\r
+#define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */\r
+ /* combination with EBS[2:0] for GetFlagStatus function */\r
+ #define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */\r
+ #define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */\r
+ #define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */\r
+#define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */\r
+ #define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */\r
+ #define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */\r
+ #define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */\r
+ #define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */\r
+ #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */\r
+ #define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */\r
+#define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */\r
+ #define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */\r
+ #define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */\r
+ #define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */\r
+ #define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */\r
+ #define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */\r
+ #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */\r
+#define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */\r
+#define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */\r
+#define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */\r
+#define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */\r
+#define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */\r
+#define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */\r
+#define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */\r
+#define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */\r
+#define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */\r
+#define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */\r
+#define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */\r
+#define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */\r
+#define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */\r
+#define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */\r
+#define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */\r
+\r
+/* Bit definition for Ethernet DMA Operation Mode Register */\r
+#define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */\r
+#define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */\r
+#define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */\r
+#define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */\r
+#define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */\r
+#define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */\r
+ #define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */\r
+ #define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */\r
+ #define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */\r
+ #define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */\r
+ #define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */\r
+ #define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */\r
+ #define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */\r
+ #define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */\r
+#define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */\r
+#define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */\r
+#define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */\r
+#define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */\r
+ #define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */\r
+ #define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */\r
+ #define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */\r
+ #define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */\r
+#define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */\r
+#define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */\r
+\r
+/* Bit definition for Ethernet DMA Interrupt Enable Register */\r
+#define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */\r
+#define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */\r
+#define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */\r
+#define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */\r
+#define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */\r
+#define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */\r
+#define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */\r
+#define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */\r
+#define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */\r
+#define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */\r
+#define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */\r
+#define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */\r
+#define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */\r
+#define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */\r
+#define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */\r
+\r
+/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */\r
+#define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */\r
+#define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */\r
+#define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */\r
+#define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */\r
+\r
+/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */\r
+#define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */\r
+\r
+/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */\r
+#define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */\r
+\r
+/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */\r
+#define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */\r
+\r
+/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */\r
+#define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */\r
+#endif /* STM32F10X_CL */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+ /**\r
+ * @}\r
+ */ \r
+\r
+#ifdef USE_STDPERIPH_DRIVER\r
+ #include "stm32f10x_conf.h"\r
+#endif\r
+\r
+/** @addtogroup Exported_macro\r
+ * @{\r
+ */\r
+\r
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))\r
+\r
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))\r
+\r
+#define READ_BIT(REG, BIT) ((REG) & (BIT))\r
+\r
+#define CLEAR_REG(REG) ((REG) = (0x0))\r
+\r
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))\r
+\r
+#define READ_REG(REG) ((REG))\r
+\r
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F10x_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+ /**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/**\r
+ ******************************************************************************\r
+ * @file system_stm32f10x.c\r
+ * @author MCD Application Team\r
+ * @version V3.1.0\r
+ * @date 06/19/2009\r
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.\r
+ ****************************************************************************** \r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/** @addtogroup CMSIS\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup stm32f10x_system\r
+ * @{\r
+ */ \r
+ \r
+/** @addtogroup STM32F10x_System_Private_Includes\r
+ * @{\r
+ */\r
+\r
+#include "stm32f10x.h"\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F10x_System_Private_TypesDefinitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F10x_System_Private_Defines\r
+ * @{\r
+ */\r
+\r
+/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)\r
+ frequency (after reset the HSI is used as SYSCLK source)\r
+ \r
+ IMPORTANT NOTE:\r
+ ============== \r
+ 1. After each device reset the HSI is used as System clock source.\r
+\r
+ 2. Please make sure that the selected System clock doesn't exceed your device's\r
+ maximum frequency.\r
+ \r
+ 3. If none of the define below is enabled, the HSI is used as System clock\r
+ source.\r
+\r
+ 4. The System clock configuration functions provided within this file assume that:\r
+ - For Low, Medium and High density devices an external 8MHz crystal is\r
+ used to drive the System clock.\r
+ - For Connectivity line devices an external 25MHz crystal is used to drive\r
+ the System clock.\r
+ If you are using different crystal you have to adapt those functions accordingly.\r
+ */\r
+ \r
+/* #define SYSCLK_FREQ_HSE HSE_Value */\r
+/* #define SYSCLK_FREQ_24MHz 24000000 */\r
+/* #define SYSCLK_FREQ_36MHz 36000000 */\r
+/* #define SYSCLK_FREQ_48MHz 48000000 */\r
+/* #define SYSCLK_FREQ_56MHz 56000000 */\r
+#define SYSCLK_FREQ_72MHz 72000000\r
+\r
+/*!< Uncomment the following line if you need to use external SRAM mounted\r
+ on STM3210E-EVAL board (STM32 High density devices) as data memory */ \r
+#ifdef STM32F10X_HD\r
+/* #define DATA_IN_ExtSRAM */\r
+#endif /* STM32F10X_HD */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F10x_System_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F10x_System_Private_Variables\r
+ * @{\r
+ */\r
+\r
+/*******************************************************************************\r
+* Clock Definitions\r
+*******************************************************************************/\r
+#ifdef SYSCLK_FREQ_HSE\r
+ const uint32_t SystemFrequency = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */\r
+ const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_HSE; /*!< System clock */\r
+ const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_HSE; /*!< AHB System bus speed */\r
+ const uint32_t SystemFrequency_APB1Clk = SYSCLK_FREQ_HSE; /*!< APB Peripheral bus 1 (low) speed */\r
+ const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_HSE; /*!< APB Peripheral bus 2 (high) speed */\r
+#elif defined SYSCLK_FREQ_24MHz\r
+ const uint32_t SystemFrequency = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */\r
+ const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_24MHz; /*!< System clock */\r
+ const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_24MHz; /*!< AHB System bus speed */\r
+ const uint32_t SystemFrequency_APB1Clk = SYSCLK_FREQ_24MHz; /*!< APB Peripheral bus 1 (low) speed */\r
+ const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_24MHz; /*!< APB Peripheral bus 2 (high) speed */\r
+#elif defined SYSCLK_FREQ_36MHz\r
+ const uint32_t SystemFrequency = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */\r
+ const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_36MHz; /*!< System clock */\r
+ const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_36MHz; /*!< AHB System bus speed */\r
+ const uint32_t SystemFrequency_APB1Clk = SYSCLK_FREQ_36MHz; /*!< APB Peripheral bus 1 (low) speed */\r
+ const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_36MHz; /*!< APB Peripheral bus 2 (high) speed */\r
+#elif defined SYSCLK_FREQ_48MHz\r
+ const uint32_t SystemFrequency = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */\r
+ const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_48MHz; /*!< System clock */\r
+ const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_48MHz; /*!< AHB System bus speed */\r
+ const uint32_t SystemFrequency_APB1Clk = (SYSCLK_FREQ_48MHz/2); /*!< APB Peripheral bus 1 (low) speed */\r
+ const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_48MHz; /*!< APB Peripheral bus 2 (high) speed */\r
+#elif defined SYSCLK_FREQ_56MHz\r
+ const uint32_t SystemFrequency = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */\r
+ const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_56MHz; /*!< System clock */\r
+ const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_56MHz; /*!< AHB System bus speed */\r
+ const uint32_t SystemFrequency_APB1Clk = (SYSCLK_FREQ_56MHz/2); /*!< APB Peripheral bus 1 (low) speed */\r
+ const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_56MHz; /*!< APB Peripheral bus 2 (high) speed */ \r
+#elif defined SYSCLK_FREQ_72MHz\r
+ const uint32_t SystemFrequency = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */\r
+ const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_72MHz; /*!< System clock */\r
+ const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_72MHz; /*!< AHB System bus speed */\r
+ const uint32_t SystemFrequency_APB1Clk = (SYSCLK_FREQ_72MHz/2); /*!< APB Peripheral bus 1 (low) speed */\r
+ const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_72MHz; /*!< APB Peripheral bus 2 (high) speed */\r
+#else /*!< HSI Selected as System Clock source */\r
+ const uint32_t SystemFrequency = HSI_Value; /*!< System Clock Frequency (Core Clock) */\r
+ const uint32_t SystemFrequency_SysClk = HSI_Value; /*!< System clock */\r
+ const uint32_t SystemFrequency_AHBClk = HSI_Value; /*!< AHB System bus speed */\r
+ const uint32_t SystemFrequency_APB1Clk = HSI_Value; /*!< APB Peripheral bus 1 (low) speed */\r
+ const uint32_t SystemFrequency_APB2Clk = HSI_Value; /*!< APB Peripheral bus 2 (high) speed */\r
+#endif\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F10x_System_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+static void SetSysClock(void);\r
+\r
+#ifdef SYSCLK_FREQ_HSE\r
+ static void SetSysClockToHSE(void);\r
+#elif defined SYSCLK_FREQ_24MHz\r
+ static void SetSysClockTo24(void);\r
+#elif defined SYSCLK_FREQ_36MHz\r
+ static void SetSysClockTo36(void);\r
+#elif defined SYSCLK_FREQ_48MHz\r
+ static void SetSysClockTo48(void);\r
+#elif defined SYSCLK_FREQ_56MHz\r
+ static void SetSysClockTo56(void); \r
+#elif defined SYSCLK_FREQ_72MHz\r
+ static void SetSysClockTo72(void);\r
+#endif\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F10x_System_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Setup the microcontroller system\r
+ * Initialize the Embedded Flash Interface, the PLL and update the SystemFrequency variable.\r
+ * @note This function should be used only after reset.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemInit (void)\r
+{\r
+ /* Reset the RCC clock configuration to the default reset state(for debug purpose) */\r
+ /* Set HSION bit */\r
+ RCC->CR |= (uint32_t)0x00000001;\r
+\r
+ /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */\r
+#ifndef STM32F10X_CL\r
+ RCC->CFGR &= (uint32_t)0xF8FF0000;\r
+#else\r
+ RCC->CFGR &= (uint32_t)0xF0FF0000;\r
+#endif /* STM32F10X_CL */ \r
+ \r
+ /* Reset HSEON, CSSON and PLLON bits */\r
+ RCC->CR &= (uint32_t)0xFEF6FFFF;\r
+\r
+ /* Reset HSEBYP bit */\r
+ RCC->CR &= (uint32_t)0xFFFBFFFF;\r
+\r
+ /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */\r
+ RCC->CFGR &= (uint32_t)0xFF80FFFF;\r
+\r
+#ifndef STM32F10X_CL\r
+ /* Disable all interrupts and clear pending bits */\r
+ RCC->CIR = 0x009F0000;\r
+#else\r
+ /* Reset PLL2ON and PLL3ON bits */\r
+ RCC->CR &= (uint32_t)0xEBFFFFFF;\r
+\r
+ /* Disable all interrupts and clear pending bits */\r
+ RCC->CIR = 0x00FF0000;\r
+\r
+ /* Reset CFGR2 register */\r
+ RCC->CFGR2 = 0x00000000;\r
+#endif /* STM32F10X_CL */\r
+ \r
+ /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */\r
+ /* Configure the Flash Latency cycles and enable prefetch buffer */\r
+ SetSysClock();\r
+\r
+}\r
+\r
+/**\r
+ * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+static void SetSysClock(void)\r
+{\r
+#ifdef SYSCLK_FREQ_HSE\r
+ SetSysClockToHSE();\r
+#elif defined SYSCLK_FREQ_24MHz\r
+ SetSysClockTo24();\r
+#elif defined SYSCLK_FREQ_36MHz\r
+ SetSysClockTo36();\r
+#elif defined SYSCLK_FREQ_48MHz\r
+ SetSysClockTo48();\r
+#elif defined SYSCLK_FREQ_56MHz\r
+ SetSysClockTo56(); \r
+#elif defined SYSCLK_FREQ_72MHz\r
+ SetSysClockTo72();\r
+#endif\r
+ \r
+ /* If none of the define above is enabled, the HSI is used as System clock\r
+ source (default after reset) */ \r
+}\r
+\r
+/**\r
+ * @brief Setup the external memory controller. Called in startup_stm32f10x.s \r
+ * before jump to __main\r
+ * @param None\r
+ * @retval None\r
+ */ \r
+#ifdef DATA_IN_ExtSRAM\r
+/**\r
+ * @brief Setup the external memory controller. \r
+ * Called in startup_stm32f10x_xx.s/.c before jump to main.\r
+ * This function configures the external SRAM mounted on STM3210E-EVAL\r
+ * board (STM32 High density devices). This SRAM will be used as program\r
+ * data memory (including heap and stack).\r
+ * @param None\r
+ * @retval None\r
+ */ \r
+void SystemInit_ExtMemCtl(void) \r
+{\r
+/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is \r
+ required, then adjust the Register Addresses */\r
+\r
+ /* Enable FSMC clock */\r
+ RCC->AHBENR = 0x00000114;\r
+ \r
+ /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */ \r
+ RCC->APB2ENR = 0x000001E0;\r
+ \r
+/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/\r
+/*---------------- SRAM Address lines configuration -------------------------*/\r
+/*---------------- NOE and NWE configuration --------------------------------*/ \r
+/*---------------- NE3 configuration ----------------------------------------*/\r
+/*---------------- NBL0, NBL1 configuration ---------------------------------*/\r
+ \r
+ GPIOD->CRL = 0x44BB44BB; \r
+ GPIOD->CRH = 0xBBBBBBBB;\r
+\r
+ GPIOE->CRL = 0xB44444BB; \r
+ GPIOE->CRH = 0xBBBBBBBB;\r
+\r
+ GPIOF->CRL = 0x44BBBBBB; \r
+ GPIOF->CRH = 0xBBBB4444;\r
+\r
+ GPIOG->CRL = 0x44BBBBBB; \r
+ GPIOG->CRH = 0x44444B44;\r
+ \r
+/*---------------- FSMC Configuration ---------------------------------------*/ \r
+/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/\r
+ \r
+ FSMC_Bank1->BTCR[4] = 0x00001011;\r
+ FSMC_Bank1->BTCR[5] = 0x00000200;\r
+}\r
+#endif /* DATA_IN_ExtSRAM */\r
+\r
+#ifdef SYSCLK_FREQ_HSE\r
+/**\r
+ * @brief Selects HSE as System clock source and configure HCLK, PCLK2\r
+ * and PCLK1 prescalers.\r
+ * @note This function should be used only after reset.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+static void SetSysClockToHSE(void)\r
+{\r
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;\r
+ \r
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ \r
+ /* Enable HSE */ \r
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);\r
+ \r
+ /* Wait till HSE is ready and if Time out is reached exit */\r
+ do\r
+ {\r
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;\r
+ StartUpCounter++; \r
+ } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));\r
+\r
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)\r
+ {\r
+ HSEStatus = (uint32_t)0x01;\r
+ }\r
+ else\r
+ {\r
+ HSEStatus = (uint32_t)0x00;\r
+ } \r
+\r
+ if (HSEStatus == (uint32_t)0x01)\r
+ {\r
+ /* Enable Prefetch Buffer */\r
+ FLASH->ACR |= FLASH_ACR_PRFTBE;\r
+\r
+ /* Flash 0 wait state */\r
+ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);\r
+\r
+#ifndef STM32F10X_CL\r
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;\r
+#else\r
+ if (HSE_Value <= 24000000)\r
+ {\r
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;\r
+ }\r
+ else\r
+ {\r
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;\r
+ }\r
+#endif /* STM32F10X_CL */\r
+ \r
+ /* HCLK = SYSCLK */\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;\r
+ \r
+ /* PCLK2 = HCLK */\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;\r
+ \r
+ /* PCLK1 = HCLK */\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;\r
+ \r
+ /* Select HSE as system clock source */\r
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE; \r
+\r
+ /* Wait till HSE is used as system clock source */\r
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)\r
+ {\r
+ }\r
+ }\r
+ else\r
+ { /* If HSE fails to start-up, the application will have wrong clock \r
+ configuration. User can add here some code to deal with this error */ \r
+\r
+ /* Go to infinite loop */\r
+ while (1)\r
+ {\r
+ }\r
+ } \r
+}\r
+#elif defined SYSCLK_FREQ_24MHz\r
+/**\r
+ * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 \r
+ * and PCLK1 prescalers.\r
+ * @note This function should be used only after reset.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+static void SetSysClockTo24(void)\r
+{\r
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;\r
+ \r
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ \r
+ /* Enable HSE */ \r
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);\r
+ \r
+ /* Wait till HSE is ready and if Time out is reached exit */\r
+ do\r
+ {\r
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;\r
+ StartUpCounter++; \r
+ } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));\r
+\r
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)\r
+ {\r
+ HSEStatus = (uint32_t)0x01;\r
+ }\r
+ else\r
+ {\r
+ HSEStatus = (uint32_t)0x00;\r
+ } \r
+\r
+ if (HSEStatus == (uint32_t)0x01)\r
+ {\r
+ /* Enable Prefetch Buffer */\r
+ FLASH->ACR |= FLASH_ACR_PRFTBE;\r
+\r
+ /* Flash 0 wait state */\r
+ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);\r
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; \r
+ \r
+ /* HCLK = SYSCLK */\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;\r
+ \r
+ /* PCLK2 = HCLK */\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;\r
+ \r
+ /* PCLK1 = HCLK */\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;\r
+ \r
+#ifdef STM32F10X_CL\r
+ /* Configure PLLs ------------------------------------------------------*/\r
+ /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ \r
+ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);\r
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | \r
+ RCC_CFGR_PLLMULL6); \r
+\r
+ /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */\r
+ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ \r
+ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |\r
+ RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);\r
+ RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |\r
+ RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);\r
+ \r
+ /* Enable PLL2 */\r
+ RCC->CR |= RCC_CR_PLL2ON;\r
+ /* Wait till PLL2 is ready */\r
+ while((RCC->CR & RCC_CR_PLL2RDY) == 0)\r
+ {\r
+ } \r
+#else \r
+ /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */\r
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));\r
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);\r
+#endif /* STM32F10X_CL */\r
+\r
+ /* Enable PLL */\r
+ RCC->CR |= RCC_CR_PLLON;\r
+\r
+ /* Wait till PLL is ready */\r
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)\r
+ {\r
+ }\r
+\r
+ /* Select PLL as system clock source */\r
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; \r
+\r
+ /* Wait till PLL is used as system clock source */\r
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)\r
+ {\r
+ }\r
+ }\r
+ else\r
+ { /* If HSE fails to start-up, the application will have wrong clock \r
+ configuration. User can add here some code to deal with this error */ \r
+\r
+ /* Go to infinite loop */\r
+ while (1)\r
+ {\r
+ }\r
+ } \r
+}\r
+#elif defined SYSCLK_FREQ_36MHz\r
+/**\r
+ * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2 \r
+ * and PCLK1 prescalers. \r
+ * @note This function should be used only after reset.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+static void SetSysClockTo36(void)\r
+{\r
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;\r
+ \r
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ \r
+ /* Enable HSE */ \r
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);\r
+ \r
+ /* Wait till HSE is ready and if Time out is reached exit */\r
+ do\r
+ {\r
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;\r
+ StartUpCounter++; \r
+ } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));\r
+\r
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)\r
+ {\r
+ HSEStatus = (uint32_t)0x01;\r
+ }\r
+ else\r
+ {\r
+ HSEStatus = (uint32_t)0x00;\r
+ } \r
+\r
+ if (HSEStatus == (uint32_t)0x01)\r
+ {\r
+ /* Enable Prefetch Buffer */\r
+ FLASH->ACR |= FLASH_ACR_PRFTBE;\r
+\r
+ /* Flash 1 wait state */\r
+ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);\r
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; \r
+ \r
+ /* HCLK = SYSCLK */\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;\r
+ \r
+ /* PCLK2 = HCLK */\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;\r
+ \r
+ /* PCLK1 = HCLK */\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;\r
+ \r
+#ifdef STM32F10X_CL\r
+ /* Configure PLLs ------------------------------------------------------*/\r
+ \r
+ /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ \r
+ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);\r
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | \r
+ RCC_CFGR_PLLMULL9); \r
+\r
+ /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */\r
+ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */\r
+ \r
+ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |\r
+ RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);\r
+ RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |\r
+ RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);\r
+ \r
+ /* Enable PLL2 */\r
+ RCC->CR |= RCC_CR_PLL2ON;\r
+ /* Wait till PLL2 is ready */\r
+ while((RCC->CR & RCC_CR_PLL2RDY) == 0)\r
+ {\r
+ }\r
+ \r
+#else \r
+ /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */\r
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));\r
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);\r
+#endif /* STM32F10X_CL */\r
+\r
+ /* Enable PLL */\r
+ RCC->CR |= RCC_CR_PLLON;\r
+\r
+ /* Wait till PLL is ready */\r
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)\r
+ {\r
+ }\r
+\r
+ /* Select PLL as system clock source */\r
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; \r
+\r
+ /* Wait till PLL is used as system clock source */\r
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)\r
+ {\r
+ }\r
+ }\r
+ else\r
+ { /* If HSE fails to start-up, the application will have wrong clock \r
+ configuration. User can add here some code to deal with this error */ \r
+\r
+ /* Go to infinite loop */\r
+ while (1)\r
+ {\r
+ }\r
+ } \r
+}\r
+#elif defined SYSCLK_FREQ_48MHz\r
+/**\r
+ * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 \r
+ * and PCLK1 prescalers. \r
+ * @note This function should be used only after reset.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+static void SetSysClockTo48(void)\r
+{\r
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;\r
+ \r
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ \r
+ /* Enable HSE */ \r
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);\r
+ \r
+ /* Wait till HSE is ready and if Time out is reached exit */\r
+ do\r
+ {\r
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;\r
+ StartUpCounter++; \r
+ } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));\r
+\r
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)\r
+ {\r
+ HSEStatus = (uint32_t)0x01;\r
+ }\r
+ else\r
+ {\r
+ HSEStatus = (uint32_t)0x00;\r
+ } \r
+\r
+ if (HSEStatus == (uint32_t)0x01)\r
+ {\r
+ /* Enable Prefetch Buffer */\r
+ FLASH->ACR |= FLASH_ACR_PRFTBE;\r
+\r
+ /* Flash 1 wait state */\r
+ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);\r
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; \r
+ \r
+ /* HCLK = SYSCLK */\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;\r
+ \r
+ /* PCLK2 = HCLK */\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;\r
+ \r
+ /* PCLK1 = HCLK */\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;\r
+ \r
+#ifdef STM32F10X_CL\r
+ /* Configure PLLs ------------------------------------------------------*/\r
+ /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */\r
+ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */\r
+ \r
+ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |\r
+ RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);\r
+ RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |\r
+ RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);\r
+ \r
+ /* Enable PLL2 */\r
+ RCC->CR |= RCC_CR_PLL2ON;\r
+ /* Wait till PLL2 is ready */\r
+ while((RCC->CR & RCC_CR_PLL2RDY) == 0)\r
+ {\r
+ }\r
+ \r
+ \r
+ /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ \r
+ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);\r
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | \r
+ RCC_CFGR_PLLMULL6); \r
+#else \r
+ /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */\r
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));\r
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);\r
+#endif /* STM32F10X_CL */\r
+\r
+ /* Enable PLL */\r
+ RCC->CR |= RCC_CR_PLLON;\r
+\r
+ /* Wait till PLL is ready */\r
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)\r
+ {\r
+ }\r
+\r
+ /* Select PLL as system clock source */\r
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; \r
+\r
+ /* Wait till PLL is used as system clock source */\r
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)\r
+ {\r
+ }\r
+ }\r
+ else\r
+ { /* If HSE fails to start-up, the application will have wrong clock \r
+ configuration. User can add here some code to deal with this error */ \r
+\r
+ /* Go to infinite loop */\r
+ while (1)\r
+ {\r
+ }\r
+ } \r
+}\r
+\r
+#elif defined SYSCLK_FREQ_56MHz\r
+/**\r
+ * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 \r
+ * and PCLK1 prescalers. \r
+ * @note This function should be used only after reset.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+static void SetSysClockTo56(void)\r
+{\r
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;\r
+ \r
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ \r
+ /* Enable HSE */ \r
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);\r
+ \r
+ /* Wait till HSE is ready and if Time out is reached exit */\r
+ do\r
+ {\r
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;\r
+ StartUpCounter++; \r
+ } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));\r
+\r
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)\r
+ {\r
+ HSEStatus = (uint32_t)0x01;\r
+ }\r
+ else\r
+ {\r
+ HSEStatus = (uint32_t)0x00;\r
+ } \r
+\r
+ if (HSEStatus == (uint32_t)0x01)\r
+ {\r
+ /* Enable Prefetch Buffer */\r
+ FLASH->ACR |= FLASH_ACR_PRFTBE;\r
+\r
+ /* Flash 1 wait state */\r
+ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);\r
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; \r
+ \r
+ /* HCLK = SYSCLK */\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;\r
+ \r
+ /* PCLK2 = HCLK */\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;\r
+ \r
+ /* PCLK1 = HCLK */\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;\r
+\r
+#ifdef STM32F10X_CL\r
+ /* Configure PLLs ------------------------------------------------------*/\r
+ /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */\r
+ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */\r
+ \r
+ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |\r
+ RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);\r
+ RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |\r
+ RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);\r
+ \r
+ /* Enable PLL2 */\r
+ RCC->CR |= RCC_CR_PLL2ON;\r
+ /* Wait till PLL2 is ready */\r
+ while((RCC->CR & RCC_CR_PLL2RDY) == 0)\r
+ {\r
+ }\r
+ \r
+ \r
+ /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ \r
+ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);\r
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | \r
+ RCC_CFGR_PLLMULL7); \r
+#else \r
+ /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */\r
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));\r
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);\r
+\r
+#endif /* STM32F10X_CL */\r
+\r
+ /* Enable PLL */\r
+ RCC->CR |= RCC_CR_PLLON;\r
+\r
+ /* Wait till PLL is ready */\r
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)\r
+ {\r
+ }\r
+\r
+ /* Select PLL as system clock source */\r
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; \r
+\r
+ /* Wait till PLL is used as system clock source */\r
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)\r
+ {\r
+ }\r
+ }\r
+ else\r
+ { /* If HSE fails to start-up, the application will have wrong clock \r
+ configuration. User can add here some code to deal with this error */ \r
+\r
+ /* Go to infinite loop */\r
+ while (1)\r
+ {\r
+ }\r
+ } \r
+}\r
+\r
+#elif defined SYSCLK_FREQ_72MHz\r
+/**\r
+ * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 \r
+ * and PCLK1 prescalers. \r
+ * @note This function should be used only after reset.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+static void SetSysClockTo72(void)\r
+{\r
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;\r
+ \r
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ \r
+ /* Enable HSE */ \r
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);\r
+ \r
+ /* Wait till HSE is ready and if Time out is reached exit */\r
+ do\r
+ {\r
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;\r
+ StartUpCounter++; \r
+ } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));\r
+\r
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)\r
+ {\r
+ HSEStatus = (uint32_t)0x01;\r
+ }\r
+ else\r
+ {\r
+ HSEStatus = (uint32_t)0x00;\r
+ } \r
+\r
+ if (HSEStatus == (uint32_t)0x01)\r
+ {\r
+ /* Enable Prefetch Buffer */\r
+ FLASH->ACR |= FLASH_ACR_PRFTBE;\r
+\r
+ /* Flash 2 wait state */\r
+ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);\r
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; \r
+\r
+ \r
+ /* HCLK = SYSCLK */\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;\r
+ \r
+ /* PCLK2 = HCLK */\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;\r
+ \r
+ /* PCLK1 = HCLK */\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;\r
+\r
+#ifdef STM32F10X_CL\r
+ /* Configure PLLs ------------------------------------------------------*/\r
+ /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */\r
+ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */\r
+ \r
+ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |\r
+ RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);\r
+ RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |\r
+ RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);\r
+ \r
+ /* Enable PLL2 */\r
+ RCC->CR |= RCC_CR_PLL2ON;\r
+ /* Wait till PLL2 is ready */\r
+ while((RCC->CR & RCC_CR_PLL2RDY) == 0)\r
+ {\r
+ }\r
+ \r
+ \r
+ /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ \r
+ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);\r
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | \r
+ RCC_CFGR_PLLMULL9); \r
+#else \r
+ /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */\r
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |\r
+ RCC_CFGR_PLLMULL));\r
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);\r
+#endif /* STM32F10X_CL */\r
+\r
+ /* Enable PLL */\r
+ RCC->CR |= RCC_CR_PLLON;\r
+\r
+ /* Wait till PLL is ready */\r
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)\r
+ {\r
+ }\r
+ \r
+ /* Select PLL as system clock source */\r
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; \r
+\r
+ /* Wait till PLL is used as system clock source */\r
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)\r
+ {\r
+ }\r
+ }\r
+ else\r
+ { /* If HSE fails to start-up, the application will have wrong clock \r
+ configuration. User can add here some code to deal with this error */ \r
+\r
+ /* Go to infinite loop */\r
+ while (1)\r
+ {\r
+ }\r
+ }\r
+}\r
+#endif\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/**\r
+ ******************************************************************************\r
+ * @file system_stm32f10x.h\r
+ * @author MCD Application Team\r
+ * @version V3.1.0\r
+ * @date 06/19/2009\r
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.\r
+ ****************************************************************************** \r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/** @addtogroup CMSIS\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup stm32f10x_system\r
+ * @{\r
+ */ \r
+ \r
+/**\r
+ * @brief Define to prevent recursive inclusion\r
+ */\r
+#ifndef __SYSTEM_STM32F10X_H\r
+#define __SYSTEM_STM32F10X_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif \r
+\r
+/** @addtogroup STM32F10x_System_Includes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @addtogroup STM32F10x_System_Exported_types\r
+ * @{\r
+ */\r
+\r
+extern const uint32_t SystemFrequency; /*!< System Clock Frequency (Core Clock) */\r
+extern const uint32_t SystemFrequency_SysClk; /*!< System clock */\r
+extern const uint32_t SystemFrequency_AHBClk; /*!< AHB System bus speed */\r
+extern const uint32_t SystemFrequency_APB1Clk; /*!< APB Peripheral Bus 1 (low) speed */\r
+extern const uint32_t SystemFrequency_APB2Clk; /*!< APB Peripheral Bus 2 (high) speed */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F10x_System_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F10x_System_Exported_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F10x_System_Exported_Functions\r
+ * @{\r
+ */\r
+ \r
+extern void SystemInit(void);\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__SYSTEM_STM32F10X_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*\r
+ * timer.c\r
+ *\r
+ * Created on: 2009-jan-17\r
+ * Author: mahi\r
+ */\r
+\r
+#include "Os.h"\r
+#include "sys.h"\r
+#include "pcb.h"\r
+#include "internal.h"\r
+#include "stm32f10x.h"\r
+#include "core_cm3.h"\r
+\r
+/**\r
+ * Init of free running timer.\r
+ */\r
+void Frt_Init( void ) {\r
+ TaskType tid;\r
+ tid = Os_CreateIsr(OsTick,6/*prio*/,"OsTick");\r
+ IntCtrl_AttachIsr2(tid,NULL,7);\r
+}\r
+\r
+/**\r
+ *
+ * @param period_ticks How long the period in timer ticks should be. The timer\r
+ * on PowerPC often driver by the CPU clock or some platform clock.\r
+ *
+ */\r
+
+void Frt_Start(uint32_t period_ticks) {
+
+ SysTick_Config(period_ticks);
+
+#if 0
+ // SysTick interrupt each 250ms with counter clock equal to 9MHz
+ if (SysTick_Config((SystemFrequency / 8) / 4)) {
+ // Capture error
+ while (1)
+ ;
+ }
+
+ // Select HCLK/8 as SysTick clock source
+ SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK_Div8);
+#endif
+
+}\r
+\r
+/**\r
+ * @return
+ */\r
+\r
+uint32_t Frt_GetTimeElapsed( void )\r
+{\r
+ return (SysTick->VAL);\r
+}\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+//#include "arch_offset.h"\r
+#include "pcb.h"\r
+#include "sys.h"\r
+#include <stdlib.h>\r
+#include "task_i.h"\r
+#include "stack.h"\r
+#include "arch_offset.h"\r
+#include "stm32f10x.h"\r
+#include "core_cm3.h"\r
+\r
+/**\r
+ * Function make sure that we switch to supervisor mode(rfi) before\r
+ * we call a task for the first time.\r
+ */\r
+\r
+void os_arch_first_call( void )\r
+{\r
+ // TODO: make swicth here... for now just call func.\r
+ os_sys.curr_pcb->entry();\r
+}\r
+\r
+void *os_arch_get_stackptr( void ) {\r
+\r
+ return __get_MSP();\r
+}\r
+\r
+unsigned int os_arch_get_sc_size( void ) {\r
+ return SC_SIZE;\r
+}\r
+
+\r
+void os_arch_setup_context( pcb_t *pcb ) {\r
+ // TODO: Add lots of things here, see ppc55xx\r
+ uint32_t *context = (uint32_t *)pcb->stack.curr;\r
+ context[C_CONTEXT_OFFS/4] = SC_PATTERN;\r
+\r
+ /* Set LR to start function */\r
+ if( pcb->proc_type == PROC_EXTENDED ) {\r
+ context[C_LR_OFF/4] = (uint32_t)os_proc_start_extended;\r
+ } else if( pcb->proc_type == PROC_BASIC ) {\r
+ context[C_LR_OFF/4] = (uint32_t)os_proc_start_basic;\r
+ }\r
+// os_arch_setup_context_asm(pcb->stack.curr,NULL);\r
+}\r
+\r
+void os_arch_init( void ) {\r
+ // nothing to do here, yet :)\r
+}\r
--- /dev/null
+\r
+\r
+#define _ASSEMBLER_\r
+#include "kernel_offset.h"\r
+#include "arch_offset.h"\r
+#include "stack.h"\r
+\r
+.extern os_sys\r
+\r
+ .syntax unified\r
+ .cpu cortex-m3\r
+ .fpu softvfp\r
+ .thumb\r
+\r
+ .global os_arch_swap_context_to\r
+ .global os_arch_swap_context\r
+ .section .text\r
+/* r0 - pcb for old task\r
+ * r1 pcb for new task\r
+ *\r
+ * -------------- higher addr\r
+ * r4-r8,etc\r
+ * -------\r
+ * 4 - Large or Small context indicator\r
+ * 0 - ?\r
+ * ---------- <- JABBA\r
+ *\r
+ */\r
+os_arch_swap_context:\r
+ mov r0, sp\r
+ push {r0,r4-r8,r10,r11,lr}\r
+\r
+\r
+ // Store c-frame\r
+ sub.w sp,sp,#C_SIZE\r
+ mov.w r4,#SC_PATTERN\r
+\r
+ str r4,[sp,#4]\r
+ // store old stack for old task\r
+ str sp,[r0,#PCB_STACK_CURR_P]\r
+os_arch_swap_context_to:\r
+ // Get stack for new task\r
+ ldr sp,[r1,#PCB_STACK_CURR_P]\r
+\r
+// TODO: Fix this for all arch's..call pre,post hooks. Done here or after?\r
+// Set new current pcb\r
+ ldr r5,= os_sys\r
+ str r1,[r5,#SYS_CURR_PCB_P]\r
+\r
+// Restore C context\r
+ ldr r6,[sp,#4]\r
+ cmp r6,#SC_PATTERN\r
+ beq os_sc_restore\r
+ cmp r6,#LC_PATTERN\r
+ beq os_lc_restore\r
+os_stack_problem:\r
+// TODO: Jump to error handler\r
+ b os_stack_problem\r
+\r
+os_sc_restore:\r
+ add.w sp,sp,#C_SIZE\r
+ pop {r4-r8,r10,r11,lr}\r
+ // ehh, we are in handler mode so a bx instruction works here\r
+ bx lr\r
+\r
+os_lc_restore:\r
+ add.w sp,sp,#C_SIZE\r
+ pop {r4-r8,r10,r11,lr}\r
+ // ehh, we are in handler mode so a bx instruction works here\r
+ bx lr\r
+\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+\r
+#include <stddef.h>\r
+#include <stdint.h>\r
+\r
+#define DECLARE(_sym,_val) \\r
+ __asm("#define " #_sym " %0 ": : "i" (_val))\r
+\r
+\r
+#include "stack.h"\r
+\r
+void arch_foo(void) {\r
+ /* StackNvgprType */\r
+ DECLARE(STACK_NVGPR_R4, offsetof(StackNvgprType, r4));\r
+ DECLARE(STACK_NVGPR_R5, offsetof(StackNvgprType, r5));\r
+ DECLARE(STACK_NVGPR_R6, offsetof(StackNvgprType, r6));\r
+ DECLARE(STACK_NVGPR_R7, offsetof(StackNvgprType, r7));\r
+ DECLARE(STACK_NVGPR_R8, offsetof(StackNvgprType, r8));\r
+ DECLARE(STACK_NVGPR_R10, offsetof(StackNvgprType, r10));\r
+ DECLARE(STACK_NVGPR_R11, offsetof(StackNvgprType, r11));\r
+ DECLARE(STACK_NVGPR_VA, offsetof(StackNvgprType, va));\r
+\r
+ /* StackCallAndContextType */\r
+}\r
+\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/******************************************************************************\r
+ * @file: core_cm3.c\r
+ * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Source File\r
+ * @version: V1.20\r
+ * @date: 22. May 2009\r
+ *----------------------------------------------------------------------------\r
+ *\r
+ * Copyright (C) 2009 ARM Limited. All rights reserved.\r
+ *\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-Mx \r
+ * processor based microcontrollers. This file can be freely distributed \r
+ * within development tools that are supporting such ARM based processors. \r
+ *\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+\r
+\r
+#include <stdint.h>\r
+\r
+\r
+/* define compiler specific symbols */\r
+#if defined ( __CC_ARM )\r
+ #define __ASM __asm /*!< asm keyword for armcc */\r
+ #define __INLINE __inline /*!< inline keyword for armcc */\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #define __ASM __asm /*!< asm keyword for iarcc */\r
+ #define __INLINE inline /*!< inline keyword for iarcc. Only avaiable in High optimization mode! */\r
+\r
+#elif defined ( __GNUC__ )\r
+ #define __ASM __asm /*!< asm keyword for gcc */\r
+ #define __INLINE inline /*!< inline keyword for gcc */\r
+\r
+#elif defined ( __TASKING__ )\r
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
+\r
+#endif\r
+\r
+\r
+\r
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
+\r
+/**\r
+ * @brief Return the Process Stack Pointer\r
+ *\r
+ * @param none\r
+ * @return uint32_t ProcessStackPointer\r
+ *\r
+ * Return the actual process stack pointer\r
+ */\r
+__ASM uint32_t __get_PSP(void)\r
+{\r
+ mrs r0, psp\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Set the Process Stack Pointer\r
+ *\r
+ * @param uint32_t Process Stack Pointer\r
+ * @return none\r
+ *\r
+ * Assign the value ProcessStackPointer to the MSP \r
+ * (process stack pointer) Cortex processor register\r
+ */\r
+__ASM void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ msr psp, r0\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Return the Main Stack Pointer\r
+ *\r
+ * @param none\r
+ * @return uint32_t Main Stack Pointer\r
+ *\r
+ * Return the current value of the MSP (main stack pointer)\r
+ * Cortex processor register\r
+ */\r
+__ASM uint32_t __get_MSP(void)\r
+{\r
+ mrs r0, msp\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Set the Main Stack Pointer\r
+ *\r
+ * @param uint32_t Main Stack Pointer\r
+ * @return none\r
+ *\r
+ * Assign the value mainStackPointer to the MSP \r
+ * (main stack pointer) Cortex processor register\r
+ */\r
+__ASM void __set_MSP(uint32_t mainStackPointer)\r
+{\r
+ msr msp, r0\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Reverse byte order in unsigned short value\r
+ *\r
+ * @param uint16_t value to reverse\r
+ * @return uint32_t reversed value\r
+ *\r
+ * Reverse byte order in unsigned short value\r
+ */\r
+__ASM uint32_t __REV16(uint16_t value)\r
+{\r
+ rev16 r0, r0\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Reverse byte order in signed short value with sign extension to integer\r
+ *\r
+ * @param int16_t value to reverse\r
+ * @return int32_t reversed value\r
+ *\r
+ * Reverse byte order in signed short value with sign extension to integer\r
+ */\r
+__ASM int32_t __REVSH(int16_t value)\r
+{\r
+ revsh r0, r0\r
+ bx lr\r
+}\r
+\r
+\r
+#if (__ARMCC_VERSION < 400000)\r
+\r
+/**\r
+ * @brief Remove the exclusive lock created by ldrex\r
+ *\r
+ * @param none\r
+ * @return none\r
+ *\r
+ * Removes the exclusive lock which is created by ldrex.\r
+ */\r
+__ASM void __CLREX(void)\r
+{\r
+ clrex\r
+}\r
+\r
+/**\r
+ * @brief Return the Base Priority value\r
+ *\r
+ * @param none\r
+ * @return uint32_t BasePriority\r
+ *\r
+ * Return the content of the base priority register\r
+ */\r
+__ASM uint32_t __get_BASEPRI(void)\r
+{\r
+ mrs r0, basepri\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Set the Base Priority value\r
+ *\r
+ * @param uint32_t BasePriority\r
+ * @return none\r
+ *\r
+ * Set the base priority register\r
+ */\r
+__ASM void __set_BASEPRI(uint32_t basePri)\r
+{\r
+ msr basepri, r0\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Return the Priority Mask value\r
+ *\r
+ * @param none\r
+ * @return uint32_t PriMask\r
+ *\r
+ * Return the state of the priority mask bit from the priority mask\r
+ * register\r
+ */\r
+__ASM uint32_t __get_PRIMASK(void)\r
+{\r
+ mrs r0, primask\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Set the Priority Mask value\r
+ *\r
+ * @param uint32_t PriMask\r
+ * @return none\r
+ *\r
+ * Set the priority mask bit in the priority mask register\r
+ */\r
+__ASM void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ msr primask, r0\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Return the Fault Mask value\r
+ *\r
+ * @param none\r
+ * @return uint32_t FaultMask\r
+ *\r
+ * Return the content of the fault mask register\r
+ */\r
+__ASM uint32_t __get_FAULTMASK(void)\r
+{\r
+ mrs r0, faultmask\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Set the Fault Mask value\r
+ *\r
+ * @param uint32_t faultMask value\r
+ * @return none\r
+ *\r
+ * Set the fault mask register\r
+ */\r
+__ASM void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ msr faultmask, r0\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Return the Control Register value\r
+ * \r
+ * @param none\r
+ * @return uint32_t Control value\r
+ *\r
+ * Return the content of the control register\r
+ */\r
+__ASM uint32_t __get_CONTROL(void)\r
+{\r
+ mrs r0, control\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Set the Control Register value\r
+ *\r
+ * @param uint32_t Control value\r
+ * @return none\r
+ *\r
+ * Set the control register\r
+ */\r
+__ASM void __set_CONTROL(uint32_t control)\r
+{\r
+ msr control, r0\r
+ bx lr\r
+}\r
+\r
+#endif /* __ARMCC_VERSION */ \r
+\r
+\r
+#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/\r
+#pragma diag_suppress=Pe940\r
+\r
+/**\r
+ * @brief Return the Process Stack Pointer\r
+ *\r
+ * @param none\r
+ * @return uint32_t ProcessStackPointer\r
+ *\r
+ * Return the actual process stack pointer\r
+ */\r
+uint32_t __get_PSP(void)\r
+{\r
+ __ASM("mrs r0, psp");\r
+ __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief Set the Process Stack Pointer\r
+ *\r
+ * @param uint32_t Process Stack Pointer\r
+ * @return none\r
+ *\r
+ * Assign the value ProcessStackPointer to the MSP \r
+ * (process stack pointer) Cortex processor register\r
+ */\r
+void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ __ASM("msr psp, r0");\r
+ __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief Return the Main Stack Pointer\r
+ *\r
+ * @param none\r
+ * @return uint32_t Main Stack Pointer\r
+ *\r
+ * Return the current value of the MSP (main stack pointer)\r
+ * Cortex processor register\r
+ */\r
+uint32_t __get_MSP(void)\r
+{\r
+ __ASM("mrs r0, msp");\r
+ __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief Set the Main Stack Pointer\r
+ *\r
+ * @param uint32_t Main Stack Pointer\r
+ * @return none\r
+ *\r
+ * Assign the value mainStackPointer to the MSP \r
+ * (main stack pointer) Cortex processor register\r
+ */\r
+void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+ __ASM("msr msp, r0");\r
+ __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief Reverse byte order in unsigned short value\r
+ *\r
+ * @param uint16_t value to reverse\r
+ * @return uint32_t reversed value\r
+ *\r
+ * Reverse byte order in unsigned short value\r
+ */\r
+uint32_t __REV16(uint16_t value)\r
+{\r
+ __ASM("rev16 r0, r0");\r
+ __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief Reverse bit order of value\r
+ *\r
+ * @param uint32_t value to reverse\r
+ * @return uint32_t reversed value\r
+ *\r
+ * Reverse bit order of value\r
+ */\r
+uint32_t __RBIT(uint32_t value)\r
+{\r
+ __ASM("rbit r0, r0");\r
+ __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief LDR Exclusive\r
+ *\r
+ * @param uint8_t* address\r
+ * @return uint8_t value of (*address)\r
+ *\r
+ * Exclusive LDR command\r
+ */\r
+uint8_t __LDREXB(uint8_t *addr)\r
+{\r
+ __ASM("ldrexb r0, [r0]");\r
+ __ASM("bx lr"); \r
+}\r
+\r
+/**\r
+ * @brief LDR Exclusive\r
+ *\r
+ * @param uint16_t* address\r
+ * @return uint16_t value of (*address)\r
+ *\r
+ * Exclusive LDR command\r
+ */\r
+uint16_t __LDREXH(uint16_t *addr)\r
+{\r
+ __ASM("ldrexh r0, [r0]");\r
+ __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief LDR Exclusive\r
+ *\r
+ * @param uint32_t* address\r
+ * @return uint32_t value of (*address)\r
+ *\r
+ * Exclusive LDR command\r
+ */\r
+uint32_t __LDREXW(uint32_t *addr)\r
+{\r
+ __ASM("ldrex r0, [r0]");\r
+ __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief STR Exclusive\r
+ *\r
+ * @param uint8_t *address\r
+ * @param uint8_t value to store\r
+ * @return uint32_t successful / failed\r
+ *\r
+ * Exclusive STR command\r
+ */\r
+uint32_t __STREXB(uint8_t value, uint8_t *addr)\r
+{\r
+ __ASM("strexb r0, r0, [r1]");\r
+ __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief STR Exclusive\r
+ *\r
+ * @param uint16_t *address\r
+ * @param uint16_t value to store\r
+ * @return uint32_t successful / failed\r
+ *\r
+ * Exclusive STR command\r
+ */\r
+uint32_t __STREXH(uint16_t value, uint16_t *addr)\r
+{\r
+ __ASM("strexh r0, r0, [r1]");\r
+ __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief STR Exclusive\r
+ *\r
+ * @param uint32_t *address\r
+ * @param uint32_t value to store\r
+ * @return uint32_t successful / failed\r
+ *\r
+ * Exclusive STR command\r
+ */\r
+uint32_t __STREXW(uint32_t value, uint32_t *addr)\r
+{\r
+ __ASM("strex r0, r0, [r1]");\r
+ __ASM("bx lr");\r
+}\r
+\r
+#pragma diag_default=Pe940\r
+\r
+\r
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/\r
+\r
+/**\r
+ * @brief Return the Process Stack Pointer\r
+ *\r
+ * @param none\r
+ * @return uint32_t ProcessStackPointer\r
+ *\r
+ * Return the actual process stack pointer\r
+ */\r
+uint32_t __get_PSP(void) __attribute__( ( naked ) );\r
+uint32_t __get_PSP(void)\r
+{\r
+ uint32_t result=0;\r
+\r
+ __ASM volatile ("MRS %0, psp\n\t" \r
+ "MOV r0, %0 \n\t"\r
+ "BX lr \n\t" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Set the Process Stack Pointer\r
+ *\r
+ * @param uint32_t Process Stack Pointer\r
+ * @return none\r
+ *\r
+ * Assign the value ProcessStackPointer to the MSP \r
+ * (process stack pointer) Cortex processor register\r
+ */\r
+void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) );\r
+void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ __ASM volatile ("MSR psp, %0\n\t"\r
+ "BX lr \n\t" : : "r" (topOfProcStack) );\r
+}\r
+\r
+/**\r
+ * @brief Return the Main Stack Pointer\r
+ *\r
+ * @param none\r
+ * @return uint32_t Main Stack Pointer\r
+ *\r
+ * Return the current value of the MSP (main stack pointer)\r
+ * Cortex processor register\r
+ */\r
+uint32_t __get_MSP(void) __attribute__( ( naked ) );\r
+uint32_t __get_MSP(void)\r
+{\r
+ uint32_t result=0;\r
+\r
+ __ASM volatile ("MRS %0, msp\n\t" \r
+ "MOV r0, %0 \n\t"\r
+ "BX lr \n\t" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief Set the Main Stack Pointer\r
+ *\r
+ * @param uint32_t Main Stack Pointer\r
+ * @return none\r
+ *\r
+ * Assign the value mainStackPointer to the MSP \r
+ * (main stack pointer) Cortex processor register\r
+ */\r
+void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) );\r
+void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+ __ASM volatile ("MSR msp, %0\n\t"\r
+ "BX lr \n\t" : : "r" (topOfMainStack) );\r
+}\r
+\r
+/**\r
+ * @brief Return the Base Priority value\r
+ *\r
+ * @param none\r
+ * @return uint32_t BasePriority\r
+ *\r
+ * Return the content of the base priority register\r
+ */\r
+uint32_t __get_BASEPRI(void)\r
+{\r
+ uint32_t result=0;\r
+ \r
+ __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief Set the Base Priority value\r
+ *\r
+ * @param uint32_t BasePriority\r
+ * @return none\r
+ *\r
+ * Set the base priority register\r
+ */\r
+void __set_BASEPRI(uint32_t value)\r
+{\r
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) );\r
+}\r
+\r
+/**\r
+ * @brief Return the Priority Mask value\r
+ *\r
+ * @param none\r
+ * @return uint32_t PriMask\r
+ *\r
+ * Return the state of the priority mask bit from the priority mask\r
+ * register\r
+ */\r
+uint32_t __get_PRIMASK(void)\r
+{\r
+ uint32_t result=0;\r
+\r
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief Set the Priority Mask value\r
+ *\r
+ * @param uint32_t PriMask\r
+ * @return none\r
+ *\r
+ * Set the priority mask bit in the priority mask register\r
+ */\r
+void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) );\r
+}\r
+\r
+/**\r
+ * @brief Return the Fault Mask value\r
+ *\r
+ * @param none\r
+ * @return uint32_t FaultMask\r
+ *\r
+ * Return the content of the fault mask register\r
+ */\r
+uint32_t __get_FAULTMASK(void)\r
+{\r
+ uint32_t result=0;\r
+ \r
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief Set the Fault Mask value\r
+ *\r
+ * @param uint32_t faultMask value\r
+ * @return none\r
+ *\r
+ * Set the fault mask register\r
+ */\r
+void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );\r
+}\r
+\r
+/**\r
+ * @brief Reverse byte order in integer value\r
+ *\r
+ * @param uint32_t value to reverse\r
+ * @return uint32_t reversed value\r
+ *\r
+ * Reverse byte order in integer value\r
+ */\r
+uint32_t __REV(uint32_t value)\r
+{\r
+ uint32_t result=0;\r
+ \r
+ __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief Reverse byte order in unsigned short value\r
+ *\r
+ * @param uint16_t value to reverse\r
+ * @return uint32_t reversed value\r
+ *\r
+ * Reverse byte order in unsigned short value\r
+ */\r
+uint32_t __REV16(uint16_t value)\r
+{\r
+ uint32_t result=0;\r
+ \r
+ __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief Reverse byte order in signed short value with sign extension to integer\r
+ *\r
+ * @param int32_t value to reverse\r
+ * @return int32_t reversed value\r
+ *\r
+ * Reverse byte order in signed short value with sign extension to integer\r
+ */\r
+int32_t __REVSH(int16_t value)\r
+{\r
+ uint32_t result=0;\r
+ \r
+ __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief Reverse bit order of value\r
+ *\r
+ * @param uint32_t value to reverse\r
+ * @return uint32_t reversed value\r
+ *\r
+ * Reverse bit order of value\r
+ */\r
+uint32_t __RBIT(uint32_t value)\r
+{\r
+ uint32_t result=0;\r
+ \r
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief LDR Exclusive\r
+ *\r
+ * @param uint8_t* address\r
+ * @return uint8_t value of (*address)\r
+ *\r
+ * Exclusive LDR command\r
+ */\r
+uint8_t __LDREXB(uint8_t *addr)\r
+{\r
+ uint8_t result=0;\r
+ \r
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief LDR Exclusive\r
+ *\r
+ * @param uint16_t* address\r
+ * @return uint16_t value of (*address)\r
+ *\r
+ * Exclusive LDR command\r
+ */\r
+uint16_t __LDREXH(uint16_t *addr)\r
+{\r
+ uint16_t result=0;\r
+ \r
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief LDR Exclusive\r
+ *\r
+ * @param uint32_t* address\r
+ * @return uint32_t value of (*address)\r
+ *\r
+ * Exclusive LDR command\r
+ */\r
+uint32_t __LDREXW(uint32_t *addr)\r
+{\r
+ uint32_t result=0;\r
+ \r
+ __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief STR Exclusive\r
+ *\r
+ * @param uint8_t *address\r
+ * @param uint8_t value to store\r
+ * @return uint32_t successful / failed\r
+ *\r
+ * Exclusive STR command\r
+ */\r
+uint32_t __STREXB(uint8_t value, uint8_t *addr)\r
+{\r
+ uint32_t result=0;\r
+ \r
+ __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief STR Exclusive\r
+ *\r
+ * @param uint16_t *address\r
+ * @param uint16_t value to store\r
+ * @return uint32_t successful / failed\r
+ *\r
+ * Exclusive STR command\r
+ */\r
+uint32_t __STREXH(uint16_t value, uint16_t *addr)\r
+{\r
+ uint32_t result=0;\r
+ \r
+ __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief STR Exclusive\r
+ *\r
+ * @param uint32_t *address\r
+ * @param uint32_t value to store\r
+ * @return uint32_t successful / failed\r
+ *\r
+ * Exclusive STR command\r
+ */\r
+uint32_t __STREXW(uint32_t value, uint32_t *addr)\r
+{\r
+ uint32_t result=0;\r
+ \r
+ __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief Return the Control Register value\r
+ * \r
+ * @param none\r
+ * @return uint32_t Control value\r
+ *\r
+ * Return the content of the control register\r
+ */\r
+uint32_t __get_CONTROL(void)\r
+{\r
+ uint32_t result=0;\r
+\r
+ __ASM volatile ("MRS %0, control" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief Set the Control Register value\r
+ *\r
+ * @param uint32_t Control value\r
+ * @return none\r
+ *\r
+ * Set the control register\r
+ */\r
+void __set_CONTROL(uint32_t control)\r
+{\r
+ __ASM volatile ("MSR control, %0" : : "r" (control) );\r
+}\r
+\r
+#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/\r
+/* TASKING carm specific functions */\r
+\r
+/*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all instrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+#endif\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/******************************************************************************\r
+ * @file: core_cm3.h\r
+ * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Header File\r
+ * @version: V1.20\r
+ * @date: 22. May 2009\r
+ *----------------------------------------------------------------------------\r
+ *\r
+ * Copyright (C) 2009 ARM Limited. All rights reserved.\r
+ *\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-Mx \r
+ * processor based microcontrollers. This file can be freely distributed \r
+ * within development tools that are supporting such ARM based processors. \r
+ *\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#ifndef __CM3_CORE_H__\r
+#define __CM3_CORE_H__\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif \r
+\r
+#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */\r
+#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */\r
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (0x03) /*!< Cortex core */\r
+\r
+/**\r
+ * Lint configuration \n\r
+ * ----------------------- \n\r
+ *\r
+ * The following Lint messages will be suppressed and not shown: \n\r
+ * \n\r
+ * --- Error 10: --- \n\r
+ * register uint32_t __regBasePri __asm("basepri"); \n\r
+ * Error 10: Expecting ';' \n\r
+ * \n\r
+ * --- Error 530: --- \n\r
+ * return(__regBasePri); \n\r
+ * Warning 530: Symbol '__regBasePri' (line 264) not initialized \n\r
+ * \n\r
+ * --- Error 550: --- \n\r
+ * __regBasePri = (basePri & 0x1ff); \n\r
+ * } \n\r
+ * Warning 550: Symbol '__regBasePri' (line 271) not accessed \n\r
+ * \n\r
+ * --- Error 754: --- \n\r
+ * uint32_t RESERVED0[24]; \n\r
+ * Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced \n\r
+ * \n\r
+ * --- Error 750: --- \n\r
+ * #define __CM3_CORE_H__ \n\r
+ * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced \n\r
+ * \n\r
+ * --- Error 528: --- \n\r
+ * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n\r
+ * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced \n\r
+ * \n\r
+ * --- Error 751: --- \n\r
+ * } InterruptType_Type; \n\r
+ * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced \n\r
+ * \n\r
+ * \n\r
+ * Note: To re-enable a Message, insert a space before 'lint' * \n\r
+ *\r
+ */\r
+\r
+/*lint -save */\r
+/*lint -e10 */\r
+/*lint -e530 */\r
+/*lint -e550 */\r
+/*lint -e754 */\r
+/*lint -e750 */\r
+/*lint -e528 */\r
+/*lint -e751 */\r
+\r
+\r
+#include <stdint.h> /* Include standard types */\r
+\r
+#if defined (__ICCARM__)\r
+ #include <intrinsics.h> /* IAR Intrinsics */\r
+#endif\r
+\r
+\r
+#ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */\r
+#endif\r
+\r
+\r
+\r
+\r
+/**\r
+ * IO definitions\r
+ *\r
+ * define access restrictions to peripheral registers\r
+ */\r
+\r
+#ifdef __cplusplus\r
+#define __I volatile /*!< defines 'read only' permissions */\r
+#else\r
+#define __I volatile const /*!< defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< defines 'write only' permissions */\r
+#define __IO volatile /*!< defines 'read / write' permissions */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ ******************************************************************************/\r
+\r
+\r
+/* System Reset */\r
+#define NVIC_VECTRESET 0 /*!< Vector Reset Bit */\r
+#define NVIC_SYSRESETREQ 2 /*!< System Reset Request */\r
+#define NVIC_AIRCR_VECTKEY (0x5FA << 16) /*!< AIRCR Key for write access */\r
+#define NVIC_AIRCR_ENDIANESS 15 /*!< Endianess */\r
+\r
+/* Core Debug */\r
+#define CoreDebug_DEMCR_TRCENA (1 << 24) /*!< DEMCR TRCENA enable */\r
+#define ITM_TCR_ITMENA 1 /*!< ITM enable */\r
+\r
+\r
+\r
+\r
+/* memory mapping struct for Nested Vectored Interrupt Controller (NVIC) */\r
+typedef struct\r
+{\r
+ __IO uint32_t ISER[8]; /*!< Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[24];\r
+ __IO uint32_t ICER[8]; /*!< Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[24];\r
+ __IO uint32_t ISPR[8]; /*!< Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[24];\r
+ __IO uint32_t ICPR[8]; /*!< Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[24];\r
+ __IO uint32_t IABR[8]; /*!< Interrupt Active bit Register */\r
+ uint32_t RESERVED4[56];\r
+ __IO uint8_t IP[240]; /*!< Interrupt Priority Register, 8Bit wide */\r
+ uint32_t RESERVED5[644];\r
+ __O uint32_t STIR; /*!< Software Trigger Interrupt Register */\r
+} NVIC_Type;\r
+\r
+\r
+/* memory mapping struct for System Control Block */\r
+typedef struct\r
+{\r
+ __I uint32_t CPUID; /*!< CPU ID Base Register */\r
+ __IO uint32_t ICSR; /*!< Interrupt Control State Register */\r
+ __IO uint32_t VTOR; /*!< Vector Table Offset Register */\r
+ __IO uint32_t AIRCR; /*!< Application Interrupt / Reset Control Register */\r
+ __IO uint32_t SCR; /*!< System Control Register */\r
+ __IO uint32_t CCR; /*!< Configuration Control Register */\r
+ __IO uint8_t SHP[12]; /*!< System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
+ __IO uint32_t SHCSR; /*!< System Handler Control and State Register */\r
+ __IO uint32_t CFSR; /*!< Configurable Fault Status Register */\r
+ __IO uint32_t HFSR; /*!< Hard Fault Status Register */\r
+ __IO uint32_t DFSR; /*!< Debug Fault Status Register */\r
+ __IO uint32_t MMFAR; /*!< Mem Manage Address Register */\r
+ __IO uint32_t BFAR; /*!< Bus Fault Address Register */\r
+ __IO uint32_t AFSR; /*!< Auxiliary Fault Status Register */\r
+ __I uint32_t PFR[2]; /*!< Processor Feature Register */\r
+ __I uint32_t DFR; /*!< Debug Feature Register */\r
+ __I uint32_t ADR; /*!< Auxiliary Feature Register */\r
+ __I uint32_t MMFR[4]; /*!< Memory Model Feature Register */\r
+ __I uint32_t ISAR[5]; /*!< ISA Feature Register */\r
+} SCB_Type;\r
+\r
+\r
+/* memory mapping struct for SysTick */\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /*!< SysTick Control and Status Register */\r
+ __IO uint32_t LOAD; /*!< SysTick Reload Value Register */\r
+ __IO uint32_t VAL; /*!< SysTick Current Value Register */\r
+ __I uint32_t CALIB; /*!< SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+\r
+/* memory mapping structur for ITM */\r
+typedef struct\r
+{\r
+ __O union \r
+ {\r
+ __O uint8_t u8; /*!< ITM Stimulus Port 8-bit */\r
+ __O uint16_t u16; /*!< ITM Stimulus Port 16-bit */\r
+ __O uint32_t u32; /*!< ITM Stimulus Port 32-bit */\r
+ } PORT [32]; /*!< ITM Stimulus Port Registers */\r
+ uint32_t RESERVED0[864];\r
+ __IO uint32_t TER; /*!< ITM Trace Enable Register */\r
+ uint32_t RESERVED1[15];\r
+ __IO uint32_t TPR; /*!< ITM Trace Privilege Register */\r
+ uint32_t RESERVED2[15];\r
+ __IO uint32_t TCR; /*!< ITM Trace Control Register */\r
+ uint32_t RESERVED3[29];\r
+ __IO uint32_t IWR; /*!< ITM Integration Write Register */\r
+ __IO uint32_t IRR; /*!< ITM Integration Read Register */\r
+ __IO uint32_t IMCR; /*!< ITM Integration Mode Control Register */\r
+ uint32_t RESERVED4[43];\r
+ __IO uint32_t LAR; /*!< ITM Lock Access Register */\r
+ __IO uint32_t LSR; /*!< ITM Lock Status Register */\r
+ uint32_t RESERVED5[6];\r
+ __I uint32_t PID4; /*!< ITM Product ID Registers */\r
+ __I uint32_t PID5;\r
+ __I uint32_t PID6;\r
+ __I uint32_t PID7;\r
+ __I uint32_t PID0;\r
+ __I uint32_t PID1;\r
+ __I uint32_t PID2;\r
+ __I uint32_t PID3;\r
+ __I uint32_t CID0;\r
+ __I uint32_t CID1;\r
+ __I uint32_t CID2;\r
+ __I uint32_t CID3;\r
+} ITM_Type;\r
+\r
+\r
+/* memory mapped struct for Interrupt Type */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0;\r
+ __I uint32_t ICTR; /*!< Interrupt Control Type Register */\r
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))\r
+ __IO uint32_t ACTLR; /*!< Auxiliary Control Register */\r
+#else\r
+ uint32_t RESERVED1;\r
+#endif\r
+} InterruptType_Type;\r
+\r
+\r
+/* Memory Protection Unit */\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)\r
+typedef struct\r
+{\r
+ __I uint32_t TYPE; /*!< MPU Type Register */\r
+ __IO uint32_t CTRL; /*!< MPU Control Register */\r
+ __IO uint32_t RNR; /*!< MPU Region RNRber Register */\r
+ __IO uint32_t RBAR; /*!< MPU Region Base Address Register */\r
+ __IO uint32_t RASR; /*!< MPU Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A1; /*!< MPU Alias 1 Region Base Address Register */\r
+ __IO uint32_t RASR_A1; /*!< MPU Alias 1 Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A2; /*!< MPU Alias 2 Region Base Address Register */\r
+ __IO uint32_t RASR_A2; /*!< MPU Alias 2 Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A3; /*!< MPU Alias 3 Region Base Address Register */\r
+ __IO uint32_t RASR_A3; /*!< MPU Alias 3 Region Attribute and Size Register */\r
+} MPU_Type;\r
+#endif\r
+\r
+\r
+/* Core Debug Register */\r
+typedef struct\r
+{\r
+ __IO uint32_t DHCSR; /*!< Debug Halting Control and Status Register */\r
+ __O uint32_t DCRSR; /*!< Debug Core Register Selector Register */\r
+ __IO uint32_t DCRDR; /*!< Debug Core Register Data Register */\r
+ __IO uint32_t DEMCR; /*!< Debug Exception and Monitor Control Register */\r
+} CoreDebug_Type;\r
+\r
+\r
+/* Memory mapping of Cortex-M3 Hardware */\r
+#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */\r
+#define ITM_BASE (0xE0000000) /*!< ITM Base Address */\r
+#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */\r
+\r
+#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */\r
+#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */\r
+#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */\r
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */\r
+#endif\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ ******************************************************************************/\r
+\r
+\r
+#if defined ( __CC_ARM )\r
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */\r
+\r
+#elif defined ( __GNUC__ )\r
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
+\r
+#elif defined ( __TASKING__ )\r
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
+\r
+#endif\r
+\r
+\r
+/* ################### Compiler specific Intrinsics ########################### */\r
+\r
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
+/* ARM armcc specific functions */\r
+\r
+#define __enable_fault_irq __enable_fiq\r
+#define __disable_fault_irq __disable_fiq\r
+\r
+#define __NOP __nop\r
+#define __WFI __wfi\r
+#define __WFE __wfe\r
+#define __SEV __sev\r
+#define __ISB() __isb(0)\r
+#define __DSB() __dsb(0)\r
+#define __DMB() __dmb(0)\r
+#define __REV __rev\r
+#define __RBIT __rbit\r
+#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr))\r
+#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr))\r
+#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr))\r
+#define __STREXB(value, ptr) __strex(value, ptr)\r
+#define __STREXH(value, ptr) __strex(value, ptr)\r
+#define __STREXW(value, ptr) __strex(value, ptr)\r
+\r
+\r
+/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */\r
+/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */\r
+/* intrinsic void __enable_irq(); */\r
+/* intrinsic void __disable_irq(); */\r
+\r
+\r
+/**\r
+ * @brief Return the Process Stack Pointer\r
+ *\r
+ * @param none\r
+ * @return uint32_t ProcessStackPointer\r
+ *\r
+ * Return the actual process stack pointer\r
+ */\r
+extern uint32_t __get_PSP(void);\r
+\r
+/**\r
+ * @brief Set the Process Stack Pointer\r
+ *\r
+ * @param uint32_t Process Stack Pointer\r
+ * @return none\r
+ *\r
+ * Assign the value ProcessStackPointer to the MSP \r
+ * (process stack pointer) Cortex processor register\r
+ */\r
+extern void __set_PSP(uint32_t topOfProcStack);\r
+\r
+/**\r
+ * @brief Return the Main Stack Pointer\r
+ *\r
+ * @param none\r
+ * @return uint32_t Main Stack Pointer\r
+ *\r
+ * Return the current value of the MSP (main stack pointer)\r
+ * Cortex processor register\r
+ */\r
+extern uint32_t __get_MSP(void);\r
+\r
+/**\r
+ * @brief Set the Main Stack Pointer\r
+ *\r
+ * @param uint32_t Main Stack Pointer\r
+ * @return none\r
+ *\r
+ * Assign the value mainStackPointer to the MSP \r
+ * (main stack pointer) Cortex processor register\r
+ */\r
+extern void __set_MSP(uint32_t topOfMainStack);\r
+\r
+/**\r
+ * @brief Reverse byte order in unsigned short value\r
+ *\r
+ * @param uint16_t value to reverse\r
+ * @return uint32_t reversed value\r
+ *\r
+ * Reverse byte order in unsigned short value\r
+ */\r
+extern uint32_t __REV16(uint16_t value);\r
+\r
+/*\r
+ * @brief Reverse byte order in signed short value with sign extension to integer\r
+ *\r
+ * @param int16_t value to reverse\r
+ * @return int32_t reversed value\r
+ *\r
+ * Reverse byte order in signed short value with sign extension to integer\r
+ */\r
+extern int32_t __REVSH(int16_t value);\r
+\r
+\r
+#if (__ARMCC_VERSION < 400000)\r
+\r
+/**\r
+ * @brief Remove the exclusive lock created by ldrex\r
+ *\r
+ * @param none\r
+ * @return none\r
+ *\r
+ * Removes the exclusive lock which is created by ldrex.\r
+ */\r
+extern void __CLREX(void);\r
+\r
+/**\r
+ * @brief Return the Base Priority value\r
+ *\r
+ * @param none\r
+ * @return uint32_t BasePriority\r
+ *\r
+ * Return the content of the base priority register\r
+ */\r
+extern uint32_t __get_BASEPRI(void);\r
+\r
+/**\r
+ * @brief Set the Base Priority value\r
+ *\r
+ * @param uint32_t BasePriority\r
+ * @return none\r
+ *\r
+ * Set the base priority register\r
+ */\r
+extern void __set_BASEPRI(uint32_t basePri);\r
+\r
+/**\r
+ * @brief Return the Priority Mask value\r
+ *\r
+ * @param none\r
+ * @return uint32_t PriMask\r
+ *\r
+ * Return the state of the priority mask bit from the priority mask\r
+ * register\r
+ */\r
+extern uint32_t __get_PRIMASK(void);\r
+\r
+/**\r
+ * @brief Set the Priority Mask value\r
+ *\r
+ * @param uint32_t PriMask\r
+ * @return none\r
+ *\r
+ * Set the priority mask bit in the priority mask register\r
+ */\r
+extern void __set_PRIMASK(uint32_t priMask);\r
+\r
+/**\r
+ * @brief Return the Fault Mask value\r
+ *\r
+ * @param none\r
+ * @return uint32_t FaultMask\r
+ *\r
+ * Return the content of the fault mask register\r
+ */\r
+extern uint32_t __get_FAULTMASK(void);\r
+\r
+/**\r
+ * @brief Set the Fault Mask value\r
+ *\r
+ * @param uint32_t faultMask value\r
+ * @return none\r
+ *\r
+ * Set the fault mask register\r
+ */\r
+extern void __set_FAULTMASK(uint32_t faultMask);\r
+\r
+/**\r
+ * @brief Return the Control Register value\r
+ * \r
+ * @param none\r
+ * @return uint32_t Control value\r
+ *\r
+ * Return the content of the control register\r
+ */\r
+extern uint32_t __get_CONTROL(void);\r
+\r
+/**\r
+ * @brief Set the Control Register value\r
+ *\r
+ * @param uint32_t Control value\r
+ * @return none\r
+ *\r
+ * Set the control register\r
+ */\r
+extern void __set_CONTROL(uint32_t control);\r
+\r
+#else /* (__ARMCC_VERSION >= 400000) */\r
+\r
+\r
+/**\r
+ * @brief Remove the exclusive lock created by ldrex\r
+ *\r
+ * @param none\r
+ * @return none\r
+ *\r
+ * Removes the exclusive lock which is created by ldrex.\r
+ */\r
+#define __CLREX __clrex\r
+\r
+/**\r
+ * @brief Return the Base Priority value\r
+ *\r
+ * @param none\r
+ * @return uint32_t BasePriority\r
+ *\r
+ * Return the content of the base priority register\r
+ */\r
+static __INLINE uint32_t __get_BASEPRI(void)\r
+{\r
+ register uint32_t __regBasePri __ASM("basepri");\r
+ return(__regBasePri);\r
+}\r
+\r
+/**\r
+ * @brief Set the Base Priority value\r
+ *\r
+ * @param uint32_t BasePriority\r
+ * @return none\r
+ *\r
+ * Set the base priority register\r
+ */\r
+static __INLINE void __set_BASEPRI(uint32_t basePri)\r
+{\r
+ register uint32_t __regBasePri __ASM("basepri");\r
+ __regBasePri = (basePri & 0x1ff);\r
+}\r
+\r
+/**\r
+ * @brief Return the Priority Mask value\r
+ *\r
+ * @param none\r
+ * @return uint32_t PriMask\r
+ *\r
+ * Return the state of the priority mask bit from the priority mask\r
+ * register\r
+ */\r
+static __INLINE uint32_t __get_PRIMASK(void)\r
+{\r
+ register uint32_t __regPriMask __ASM("primask");\r
+ return(__regPriMask);\r
+}\r
+\r
+/**\r
+ * @brief Set the Priority Mask value\r
+ *\r
+ * @param uint32_t PriMask\r
+ * @return none\r
+ *\r
+ * Set the priority mask bit in the priority mask register\r
+ */\r
+static __INLINE void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ register uint32_t __regPriMask __ASM("primask");\r
+ __regPriMask = (priMask);\r
+}\r
+\r
+/**\r
+ * @brief Return the Fault Mask value\r
+ *\r
+ * @param none\r
+ * @return uint32_t FaultMask\r
+ *\r
+ * Return the content of the fault mask register\r
+ */\r
+static __INLINE uint32_t __get_FAULTMASK(void)\r
+{\r
+ register uint32_t __regFaultMask __ASM("faultmask");\r
+ return(__regFaultMask);\r
+}\r
+\r
+/**\r
+ * @brief Set the Fault Mask value\r
+ *\r
+ * @param uint32_t faultMask value\r
+ * @return none\r
+ *\r
+ * Set the fault mask register\r
+ */\r
+static __INLINE void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ register uint32_t __regFaultMask __ASM("faultmask");\r
+ __regFaultMask = (faultMask & 1);\r
+}\r
+\r
+/**\r
+ * @brief Return the Control Register value\r
+ * \r
+ * @param none\r
+ * @return uint32_t Control value\r
+ *\r
+ * Return the content of the control register\r
+ */\r
+static __INLINE uint32_t __get_CONTROL(void)\r
+{\r
+ register uint32_t __regControl __ASM("control");\r
+ return(__regControl);\r
+}\r
+\r
+/**\r
+ * @brief Set the Control Register value\r
+ *\r
+ * @param uint32_t Control value\r
+ * @return none\r
+ *\r
+ * Set the control register\r
+ */\r
+static __INLINE void __set_CONTROL(uint32_t control)\r
+{\r
+ register uint32_t __regControl __ASM("control");\r
+ __regControl = control;\r
+}\r
+\r
+#endif /* __ARMCC_VERSION */ \r
+\r
+\r
+\r
+#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/\r
+/* IAR iccarm specific functions */\r
+\r
+#define __enable_irq __enable_interrupt /*!< global Interrupt enable */\r
+#define __disable_irq __disable_interrupt /*!< global Interrupt disable */\r
+\r
+static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); }\r
+static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); }\r
+\r
+#define __NOP __no_operation() /*!< no operation intrinsic in IAR Compiler */ \r
+static __INLINE void __WFI() { __ASM ("wfi"); }\r
+static __INLINE void __WFE() { __ASM ("wfe"); }\r
+static __INLINE void __SEV() { __ASM ("sev"); }\r
+static __INLINE void __CLREX() { __ASM ("clrex"); }\r
+\r
+/* intrinsic void __ISB(void) */\r
+/* intrinsic void __DSB(void) */\r
+/* intrinsic void __DMB(void) */\r
+/* intrinsic void __set_PRIMASK(); */\r
+/* intrinsic void __get_PRIMASK(); */\r
+/* intrinsic void __set_FAULTMASK(); */\r
+/* intrinsic void __get_FAULTMASK(); */\r
+/* intrinsic uint32_t __REV(uint32_t value); */\r
+/* intrinsic uint32_t __REVSH(uint32_t value); */\r
+/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */\r
+/* intrinsic unsigned long __LDREX(unsigned long *); */\r
+\r
+\r
+/**\r
+ * @brief Return the Process Stack Pointer\r
+ *\r
+ * @param none\r
+ * @return uint32_t ProcessStackPointer\r
+ *\r
+ * Return the actual process stack pointer\r
+ */\r
+extern uint32_t __get_PSP(void);\r
+\r
+/**\r
+ * @brief Set the Process Stack Pointer\r
+ *\r
+ * @param uint32_t Process Stack Pointer\r
+ * @return none\r
+ *\r
+ * Assign the value ProcessStackPointer to the MSP \r
+ * (process stack pointer) Cortex processor register\r
+ */\r
+extern void __set_PSP(uint32_t topOfProcStack);\r
+\r
+/**\r
+ * @brief Return the Main Stack Pointer\r
+ *\r
+ * @param none\r
+ * @return uint32_t Main Stack Pointer\r
+ *\r
+ * Return the current value of the MSP (main stack pointer)\r
+ * Cortex processor register\r
+ */\r
+extern uint32_t __get_MSP(void);\r
+\r
+/**\r
+ * @brief Set the Main Stack Pointer\r
+ *\r
+ * @param uint32_t Main Stack Pointer\r
+ * @return none\r
+ *\r
+ * Assign the value mainStackPointer to the MSP \r
+ * (main stack pointer) Cortex processor register\r
+ */\r
+extern void __set_MSP(uint32_t topOfMainStack);\r
+\r
+/**\r
+ * @brief Reverse byte order in unsigned short value\r
+ *\r
+ * @param uint16_t value to reverse\r
+ * @return uint32_t reversed value\r
+ *\r
+ * Reverse byte order in unsigned short value\r
+ */\r
+extern uint32_t __REV16(uint16_t value);\r
+\r
+/**\r
+ * @brief Reverse bit order of value\r
+ *\r
+ * @param uint32_t value to reverse\r
+ * @return uint32_t reversed value\r
+ *\r
+ * Reverse bit order of value\r
+ */\r
+extern uint32_t __RBIT(uint32_t value);\r
+\r
+/**\r
+ * @brief LDR Exclusive\r
+ *\r
+ * @param uint8_t* address\r
+ * @return uint8_t value of (*address)\r
+ *\r
+ * Exclusive LDR command\r
+ */\r
+extern uint8_t __LDREXB(uint8_t *addr);\r
+\r
+/**\r
+ * @brief LDR Exclusive\r
+ *\r
+ * @param uint16_t* address\r
+ * @return uint16_t value of (*address)\r
+ *\r
+ * Exclusive LDR command\r
+ */\r
+extern uint16_t __LDREXH(uint16_t *addr);\r
+\r
+/**\r
+ * @brief LDR Exclusive\r
+ *\r
+ * @param uint32_t* address\r
+ * @return uint32_t value of (*address)\r
+ *\r
+ * Exclusive LDR command\r
+ */\r
+extern uint32_t __LDREXW(uint32_t *addr);\r
+\r
+/**\r
+ * @brief STR Exclusive\r
+ *\r
+ * @param uint8_t *address\r
+ * @param uint8_t value to store\r
+ * @return uint32_t successful / failed\r
+ *\r
+ * Exclusive STR command\r
+ */\r
+extern uint32_t __STREXB(uint8_t value, uint8_t *addr);\r
+\r
+/**\r
+ * @brief STR Exclusive\r
+ *\r
+ * @param uint16_t *address\r
+ * @param uint16_t value to store\r
+ * @return uint32_t successful / failed\r
+ *\r
+ * Exclusive STR command\r
+ */\r
+extern uint32_t __STREXH(uint16_t value, uint16_t *addr);\r
+\r
+/**\r
+ * @brief STR Exclusive\r
+ *\r
+ * @param uint32_t *address\r
+ * @param uint32_t value to store\r
+ * @return uint32_t successful / failed\r
+ *\r
+ * Exclusive STR command\r
+ */\r
+extern uint32_t __STREXW(uint32_t value, uint32_t *addr);\r
+\r
+\r
+\r
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/\r
+/* GNU gcc specific functions */\r
+\r
+static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); }\r
+static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); }\r
+\r
+static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); }\r
+static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); }\r
+\r
+static __INLINE void __NOP() { __ASM volatile ("nop"); }\r
+static __INLINE void __WFI() { __ASM volatile ("wfi"); }\r
+static __INLINE void __WFE() { __ASM volatile ("wfe"); }\r
+static __INLINE void __SEV() { __ASM volatile ("sev"); }\r
+static __INLINE void __ISB() { __ASM volatile ("isb"); }\r
+static __INLINE void __DSB() { __ASM volatile ("dsb"); }\r
+static __INLINE void __DMB() { __ASM volatile ("dmb"); }\r
+static __INLINE void __CLREX() { __ASM volatile ("clrex"); }\r
+\r
+\r
+/**\r
+ * @brief Return the Process Stack Pointer\r
+ *\r
+ * @param none\r
+ * @return uint32_t ProcessStackPointer\r
+ *\r
+ * Return the actual process stack pointer\r
+ */\r
+extern uint32_t __get_PSP(void);\r
+\r
+/**\r
+ * @brief Set the Process Stack Pointer\r
+ *\r
+ * @param uint32_t Process Stack Pointer\r
+ * @return none\r
+ *\r
+ * Assign the value ProcessStackPointer to the MSP \r
+ * (process stack pointer) Cortex processor register\r
+ */\r
+extern void __set_PSP(uint32_t topOfProcStack);\r
+\r
+/**\r
+ * @brief Return the Main Stack Pointer\r
+ *\r
+ * @param none\r
+ * @return uint32_t Main Stack Pointer\r
+ *\r
+ * Return the current value of the MSP (main stack pointer)\r
+ * Cortex processor register\r
+ */\r
+extern uint32_t __get_MSP(void);\r
+\r
+/**\r
+ * @brief Set the Main Stack Pointer\r
+ *\r
+ * @param uint32_t Main Stack Pointer\r
+ * @return none\r
+ *\r
+ * Assign the value mainStackPointer to the MSP \r
+ * (main stack pointer) Cortex processor register\r
+ */\r
+extern void __set_MSP(uint32_t topOfMainStack);\r
+\r
+/**\r
+ * @brief Return the Base Priority value\r
+ *\r
+ * @param none\r
+ * @return uint32_t BasePriority\r
+ *\r
+ * Return the content of the base priority register\r
+ */\r
+extern uint32_t __get_BASEPRI(void);\r
+\r
+/**\r
+ * @brief Set the Base Priority value\r
+ *\r
+ * @param uint32_t BasePriority\r
+ * @return none\r
+ *\r
+ * Set the base priority register\r
+ */\r
+extern void __set_BASEPRI(uint32_t basePri);\r
+\r
+/**\r
+ * @brief Return the Priority Mask value\r
+ *\r
+ * @param none\r
+ * @return uint32_t PriMask\r
+ *\r
+ * Return the state of the priority mask bit from the priority mask\r
+ * register\r
+ */\r
+extern uint32_t __get_PRIMASK(void);\r
+\r
+/**\r
+ * @brief Set the Priority Mask value\r
+ *\r
+ * @param uint32_t PriMask\r
+ * @return none\r
+ *\r
+ * Set the priority mask bit in the priority mask register\r
+ */\r
+extern void __set_PRIMASK(uint32_t priMask);\r
+\r
+/**\r
+ * @brief Return the Fault Mask value\r
+ *\r
+ * @param none\r
+ * @return uint32_t FaultMask\r
+ *\r
+ * Return the content of the fault mask register\r
+ */\r
+extern uint32_t __get_FAULTMASK(void);\r
+\r
+/**\r
+ * @brief Set the Fault Mask value\r
+ *\r
+ * @param uint32_t faultMask value\r
+ * @return none\r
+ *\r
+ * Set the fault mask register\r
+ */\r
+extern void __set_FAULTMASK(uint32_t faultMask);\r
+\r
+/**\r
+ * @brief Return the Control Register value\r
+* \r
+* @param none\r
+* @return uint32_t Control value\r
+ *\r
+ * Return the content of the control register\r
+ */\r
+extern uint32_t __get_CONTROL(void);\r
+\r
+/**\r
+ * @brief Set the Control Register value\r
+ *\r
+ * @param uint32_t Control value\r
+ * @return none\r
+ *\r
+ * Set the control register\r
+ */\r
+extern void __set_CONTROL(uint32_t control);\r
+\r
+/**\r
+ * @brief Reverse byte order in integer value\r
+ *\r
+ * @param uint32_t value to reverse\r
+ * @return uint32_t reversed value\r
+ *\r
+ * Reverse byte order in integer value\r
+ */\r
+extern uint32_t __REV(uint32_t value);\r
+\r
+/**\r
+ * @brief Reverse byte order in unsigned short value\r
+ *\r
+ * @param uint16_t value to reverse\r
+ * @return uint32_t reversed value\r
+ *\r
+ * Reverse byte order in unsigned short value\r
+ */\r
+extern uint32_t __REV16(uint16_t value);\r
+\r
+/*\r
+ * Reverse byte order in signed short value with sign extension to integer\r
+ *\r
+ * @param int16_t value to reverse\r
+ * @return int32_t reversed value\r
+ *\r
+ * @brief Reverse byte order in signed short value with sign extension to integer\r
+ */\r
+extern int32_t __REVSH(int16_t value);\r
+\r
+/**\r
+ * @brief Reverse bit order of value\r
+ *\r
+ * @param uint32_t value to reverse\r
+ * @return uint32_t reversed value\r
+ *\r
+ * Reverse bit order of value\r
+ */\r
+extern uint32_t __RBIT(uint32_t value);\r
+\r
+/**\r
+ * @brief LDR Exclusive\r
+ *\r
+ * @param uint8_t* address\r
+ * @return uint8_t value of (*address)\r
+ *\r
+ * Exclusive LDR command\r
+ */\r
+extern uint8_t __LDREXB(uint8_t *addr);\r
+\r
+/**\r
+ * @brief LDR Exclusive\r
+ *\r
+ * @param uint16_t* address\r
+ * @return uint16_t value of (*address)\r
+ *\r
+ * Exclusive LDR command\r
+ */\r
+extern uint16_t __LDREXH(uint16_t *addr);\r
+\r
+/**\r
+ * @brief LDR Exclusive\r
+ *\r
+ * @param uint32_t* address\r
+ * @return uint32_t value of (*address)\r
+ *\r
+ * Exclusive LDR command\r
+ */\r
+extern uint32_t __LDREXW(uint32_t *addr);\r
+\r
+/**\r
+ * @brief STR Exclusive\r
+ *\r
+ * @param uint8_t *address\r
+ * @param uint8_t value to store\r
+ * @return uint32_t successful / failed\r
+ *\r
+ * Exclusive STR command\r
+ */\r
+extern uint32_t __STREXB(uint8_t value, uint8_t *addr);\r
+\r
+/**\r
+ * @brief STR Exclusive\r
+ *\r
+ * @param uint16_t *address\r
+ * @param uint16_t value to store\r
+ * @return uint32_t successful / failed\r
+ *\r
+ * Exclusive STR command\r
+ */\r
+extern uint32_t __STREXH(uint16_t value, uint16_t *addr);\r
+\r
+/**\r
+ * @brief STR Exclusive\r
+ *\r
+ * @param uint32_t *address\r
+ * @param uint32_t value to store\r
+ * @return uint32_t successful / failed\r
+ *\r
+ * Exclusive STR command\r
+ */\r
+extern uint32_t __STREXW(uint32_t value, uint32_t *addr);\r
+\r
+\r
+#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/\r
+/* TASKING carm specific functions */\r
+\r
+/*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all instrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+#endif\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+\r
+\r
+/**\r
+ * @brief Set the Priority Grouping in NVIC Interrupt Controller\r
+ *\r
+ * @param uint32_t priority_grouping is priority grouping field\r
+ * @return none \r
+ *\r
+ * Set the priority grouping field using the required unlock sequence.\r
+ * The parameter priority_grouping is assigned to the field \r
+ * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used.\r
+ * In case of a conflict between priority grouping and available\r
+ * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+ */\r
+static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+ uint32_t reg_value;\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ \r
+ reg_value = SCB->AIRCR; /* read old register configuration */\r
+ reg_value &= ~((0xFFFFU << 16) | (0x0F << 8)); /* clear bits to change */\r
+ reg_value = ((reg_value | NVIC_AIRCR_VECTKEY | (PriorityGroupTmp << 8))); /* Insert write key and priorty group */\r
+ SCB->AIRCR = reg_value;\r
+}\r
+\r
+/**\r
+ * @brief Get the Priority Grouping from NVIC Interrupt Controller\r
+ *\r
+ * @param none\r
+ * @return uint32_t priority grouping field \r
+ *\r
+ * Get the priority grouping from NVIC Interrupt Controller.\r
+ * priority grouping is SCB->AIRCR [10:8] PRIGROUP field.\r
+ */\r
+static __INLINE uint32_t NVIC_GetPriorityGrouping(void)\r
+{\r
+ return ((SCB->AIRCR >> 8) & 0x07); /* read priority grouping field */\r
+}\r
+\r
+/**\r
+ * @brief Enable Interrupt in NVIC Interrupt Controller\r
+ *\r
+ * @param IRQn_Type IRQn specifies the interrupt number\r
+ * @return none \r
+ *\r
+ * Enable a device specific interupt in the NVIC interrupt controller.\r
+ * The interrupt number cannot be a negative value.\r
+ */\r
+static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */\r
+}\r
+\r
+/**\r
+ * @brief Disable the interrupt line for external interrupt specified\r
+ * \r
+ * @param IRQn_Type IRQn is the positive number of the external interrupt\r
+ * @return none\r
+ * \r
+ * Disable a device specific interupt in the NVIC interrupt controller.\r
+ * The interrupt number cannot be a negative value.\r
+ */\r
+static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */\r
+}\r
+\r
+/**\r
+ * @brief Read the interrupt pending bit for a device specific interrupt source\r
+ * \r
+ * @param IRQn_Type IRQn is the number of the device specifc interrupt\r
+ * @return uint32_t 1 if pending interrupt else 0\r
+ *\r
+ * Read the pending register in NVIC and return 1 if its status is pending, \r
+ * otherwise it returns 0\r
+ */\r
+static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */\r
+}\r
+\r
+/**\r
+ * @brief Set the pending bit for an external interrupt\r
+ * \r
+ * @param IRQn_Type IRQn is the Number of the interrupt\r
+ * @return none\r
+ *\r
+ * Set the pending bit for the specified interrupt.\r
+ * The interrupt number cannot be a negative value.\r
+ */\r
+static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */\r
+}\r
+\r
+/**\r
+ * @brief Clear the pending bit for an external interrupt\r
+ *\r
+ * @param IRQn_Type IRQn is the Number of the interrupt\r
+ * @return none\r
+ *\r
+ * Clear the pending bit for the specified interrupt. \r
+ * The interrupt number cannot be a negative value.\r
+ */\r
+static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r
+}\r
+\r
+/**\r
+ * @brief Read the active bit for an external interrupt\r
+ *\r
+ * @param IRQn_Type IRQn is the Number of the interrupt\r
+ * @return uint32_t 1 if active else 0\r
+ *\r
+ * Read the active register in NVIC and returns 1 if its status is active, \r
+ * otherwise it returns 0.\r
+ */\r
+static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */\r
+}\r
+\r
+/**\r
+ * @brief Set the priority for an interrupt\r
+ *\r
+ * @param IRQn_Type IRQn is the Number of the interrupt\r
+ * @param priority is the priority for the interrupt\r
+ * @return none\r
+ *\r
+ * Set the priority for the specified interrupt. The interrupt \r
+ * number can be positive to specify an external (device specific) \r
+ * interrupt, or negative to specify an internal (core) interrupt. \n\r
+ *\r
+ * Note: The priority cannot be set for every core interrupt.\r
+ */\r
+static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if(IRQn < 0) {\r
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */\r
+ else {\r
+ NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */\r
+}\r
+\r
+/**\r
+ * @brief Read the priority for an interrupt\r
+ *\r
+ * @param IRQn_Type IRQn is the Number of the interrupt\r
+ * @return uint32_t priority is the priority for the interrupt\r
+ *\r
+ * Read the priority for the specified interrupt. The interrupt \r
+ * number can be positive to specify an external (device specific) \r
+ * interrupt, or negative to specify an internal (core) interrupt.\r
+ *\r
+ * The returned priority value is automatically aligned to the implemented\r
+ * priority bits of the microcontroller.\r
+ *\r
+ * Note: The priority cannot be set for every core interrupt.\r
+ */\r
+static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if(IRQn < 0) {\r
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */\r
+ else {\r
+ return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */\r
+}\r
+\r
+\r
+/**\r
+ * @brief Encode the priority for an interrupt\r
+ *\r
+ * @param uint32_t PriorityGroup is the used priority group\r
+ * @param uint32_t PreemptPriority is the preemptive priority value (starting from 0)\r
+ * @param uint32_t SubPriority is the sub priority value (starting from 0)\r
+ * @return uint32_t the priority for the interrupt\r
+ *\r
+ * Encode the priority for an interrupt with the given priority group,\r
+ * preemptive priority value and sub priority value.\r
+ * In case of a conflict between priority grouping and available\r
+ * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.\r
+ *\r
+ * The returned priority value can be used for NVIC_SetPriority(...) function\r
+ */\r
+static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+ \r
+ return (\r
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |\r
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ * @brief Decode the priority of an interrupt\r
+ *\r
+ * @param uint32_t Priority the priority for the interrupt\r
+ * @param uint32_t PrioGroup is the used priority group\r
+ * @param uint32_t* pPreemptPrio is the preemptive priority value (starting from 0)\r
+ * @param uint32_t* pSubPrio is the sub priority value (starting from 0)\r
+ * @return none\r
+ *\r
+ * Decode an interrupt priority value with the given priority group to \r
+ * preemptive priority value and sub priority value.\r
+ * In case of a conflict between priority grouping and available\r
+ * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.\r
+ *\r
+ * The priority value can be retrieved with NVIC_GetPriority(...) function\r
+ */\r
+static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+ \r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);\r
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);\r
+}\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+\r
+#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)\r
+\r
+/* SysTick constants */\r
+#define SYSTICK_ENABLE 0 /* Config-Bit to start or stop the SysTick Timer */\r
+#define SYSTICK_TICKINT 1 /* Config-Bit to enable or disable the SysTick interrupt */\r
+#define SYSTICK_CLKSOURCE 2 /* Clocksource has the offset 2 in SysTick Control and Status Register */\r
+#define SYSTICK_MAXCOUNT ((1<<24) -1) /* SysTick MaxCount */\r
+\r
+/**\r
+ * @brief Initialize and start the SysTick counter and its interrupt.\r
+ *\r
+ * @param uint32_t ticks is the number of ticks between two interrupts\r
+ * @return none\r
+ *\r
+ * Initialise the system tick timer and its interrupt and start the\r
+ * system tick timer / counter in free running mode to generate \r
+ * periodical interrupts.\r
+ */\r
+static __INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{ \r
+ if (ticks > SYSTICK_MAXCOUNT) return (1); /* Reload value impossible */\r
+\r
+ SysTick->LOAD = (ticks & SYSTICK_MAXCOUNT) - 1; /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */\r
+ SysTick->VAL = (0x00); /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = (1 << SYSTICK_CLKSOURCE) | (1<<SYSTICK_ENABLE) | (1<<SYSTICK_TICKINT); /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+\r
+\r
+\r
+\r
+/* ################################## Reset function ############################################ */\r
+\r
+/**\r
+ * @brief Initiate a system reset request.\r
+ *\r
+ * @param none\r
+ * @return none\r
+ *\r
+ * Initialize a system reset request to reset the MCU\r
+ */\r
+static __INLINE void NVIC_SystemReset(void)\r
+{\r
+ SCB->AIRCR = (NVIC_AIRCR_VECTKEY | (SCB->AIRCR & (0x700)) | (1<<NVIC_SYSRESETREQ)); /* Keep priority group unchanged */\r
+ __DSB(); /* Ensure completion of memory access */ \r
+ while(1); /* wait until reset */\r
+}\r
+\r
+\r
+/* ################################## Debug Output function ############################################ */\r
+\r
+\r
+/**\r
+ * @brief Outputs a character via the ITM channel 0\r
+ *\r
+ * @param uint32_t character to output\r
+ * @return uint32_t input character\r
+ *\r
+ * The function outputs a character via the ITM channel 0. \r
+ * The function returns when no debugger is connected that has booked the output. \r
+ * It is blocking when a debugger is connected, but the previous character send is not transmitted. \r
+ */\r
+static __INLINE uint32_t ITM_SendChar (uint32_t ch)\r
+{\r
+ if (ch == '\n') ITM_SendChar('\r');\r
+ \r
+ if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA) &&\r
+ (ITM->TCR & ITM_TCR_ITMENA) &&\r
+ (ITM->TER & (1UL << 0)) ) \r
+ {\r
+ while (ITM->PORT[0].u32 == 0);\r
+ ITM->PORT[0].u8 = (uint8_t) ch;\r
+ } \r
+ return (ch);\r
+}\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CM3_CORE_H__ */\r
+\r
+/*lint -restore */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*
+ * int_ctrl.c
+ *
+ * Created on: Jul 13, 2009
+ * Author: mahi
+ */
+
+#include "pcb.h"
+#include "sys.h"
+#include "internal.h"
+#include "task_i.h"
+#include "hooks.h"
+#include "swap.h"
+#include "stm32f10x.h"
+#include "int_ctrl.h"
+
+extern void * intc_vector_tbl[NUMBER_OF_INTERRUPTS_AND_EXCEPTIONS];
+extern uint8 intc_type_tbl[NUMBER_OF_INTERRUPTS_AND_EXCEPTIONS];
+
+
+void IntCtrl_Init( void ) {
+
+
+}
+
+void IntCtrl_EOI( void ) {
+
+}
+
+/**
+ *
+ * @param stack_p Ptr to the current stack.
+ *
+ * The stack holds C, NVGPR, VGPR and the EXC frame.
+ *
+ */
+void *IntCtrl_Entry( void *stack_p )
+{
+ uint32_t vector = 0;
+ uint32_t *stack = (uint32_t *)stack_p;
+// uint32_t exc_vector = (EXC_OFF_FROM_BOTTOM+EXC_VECTOR_OFF) / sizeof(uint32_t);
+
+ if( intc_type_tbl[vector] == PROC_ISR1 ) {
+ // It's a function, just call it.
+ ((func_t)intc_vector_tbl[vector])();
+ return stack;
+ } else {
+ // It's a PCB
+ // Let the kernel handle the rest,
+ return Os_Isr(stack, (void *)intc_vector_tbl[vector]);
+ }
+}
+
+/**
+ * Attach an ISR type 1 to the interrupt controller.
+ *
+ * @param entry
+ * @param int_ctrl
+ * @param vector
+ * @param prio
+ */
+void IntCtrl_AttachIsr1( void (*entry)(void), void *int_ctrl, uint32_t vector, uint8_t prio) {
+
+ // TODO: Use NVIC_Init here
+ /*
+ NVIC_InitTypeDef NVIC_InitStructure;
+
+ // Enable and configure RCC global IRQ channel
+ NVIC_InitStructure.NVIC_IRQChannel = RCC_IRQn;
+ NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
+ NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
+ NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+ NVIC_Init(&NVIC_InitStructure);
+ */
+}
+
+/**
+ * Attach a ISR type 2 to the interrupt controller.
+ *
+ * @param tid
+ * @param int_ctrl
+ * @param vector
+ */
+void IntCtrl_AttachIsr2(TaskType tid,void *int_ctrl,uint32_t vector ) {
+ pcb_t *pcb;
+
+ pcb = os_find_task(tid);
+
+ // TODO: Same as for AttachIsr1
+
+}
+
+
+/**
+ * Generates a soft interrupt
+ * @param vector
+ */
+void IntCtrl_GenerateSoftInt( IrqType vector ) {
+
+ // NVIC_STIR
+}
+
+/**
+ * Get the current priority from the interrupt controller.
+ * @param cpu
+ * @return
+ */
+uint8_t IntCtrl_GetCurrentPriority( Cpu_t cpu) {
+
+ uint8_t prio = 0;
+
+ // SCB_ICSR contains the active vector
+ return prio;
+}
+
+typedef struct {
+ uint32_t dummy;
+} exc_stack_t;
+
+
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*\r
+ * irq.h\r
+ *\r
+ * Created on: 4 aug 2009\r
+ * Author: mahi\r
+ */\r
+\r
+#ifndef IRQ_H_\r
+#define IRQ_H_\r
+\r
+#include "stm32f10x.h"\r
+\r
+typedef IRQn_Type IrqType;\r
+\r
+#define NUMBER_OF_INTERRUPTS_AND_EXCEPTIONS (OTG_FS_IRQn+15)\r
+\r
+typedef enum {\r
+ CPU_0=0,\r
+} Cpu_t;\r
+\r
+#endif /* IRQ_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*\r
+ * context.h\r
+ *\r
+ * Created on: 7 jul 2009\r
+ * Author: mahi\r
+ *\r
+ * DESCRIPTION\r
+ * ARM Cortex-M3 (architecture ARMv7-M).\r
+ *\r
+ * REFERENCES\r
+ * - Procedure Call Standard for the ARM Architecture, release 2.07\r
+ *\r
+ * REGISTER USE\r
+ * Args\r
+ * r0-r3\r
+ *\r
+ * Non-volatile regs (saved by function call)\r
+ * r4-r8,r10,r11 and SP\r
+ *\r
+ * Misc\r
+ * r9 - Platform specific ???\r
+ * r12 - IP\r
+ * r13 - SP\r
+ * r14 - LR\r
+ * r15 - PC\r
+ *\r
+ * EXCEPTION FRAME\r
+ *\r
+ * The following registers are auto-magically pushed by the CPU\r
+ * Pushes:\r
+ * <previous>\r
+ * xPSR\r
+ * PC (r15)\r
+ * LR (r14)\r
+ * r12,r3,r2,r1,r0\r
+ *\r
+ * EXCEPTION/IRQ TABLE\r
+ * The table is a combined exception and irq table. The first 16 (0 to 15) entries\r
+ * are exceptions and the rest are irq's.\r
+ * The table just lists the addresses of the handlers (offset of 4 bytes)\r
+ *\r
+ * EXCEPTIONS\r
+ * There are fixed negative priority values for Reset, Hard fault and NMI.\r
+ * For the rest of the exceptions prio's can be set to 0-15. Priority 0 have higher\r
+ * priority than 1. Access through SHPRx.\r
+ *\r
+ * IRQ\r
+ * The IRQ's also have 4-bits of priority. All IRQ prio's are squeezed into\r
+ * 17 registers (4 in each) -> 68 IRQ's. Of the 8 bits accesssible to the\r
+ * priority only 4 bits are used, the least significant nibble is 0.\r
+ * Access through NVIC_IPR0 to IVPR_IPR16.\r
+ *\r
+ * EXCEPTION/IRQ FLOW\r
+ * - The exception hits\r
+ * - The handler is called\r
+ *\r
+ */\r
+\r
+#ifndef CONTEXT_H_\r
+#define CONTEXT_H_\r
+\r
+\r
+#define SC_PATTERN 0xde\r
+#define LC_PATTERN 0xad\r
+\r
+/* Minimum alignment req */\r
+#define ARCH_ALIGN 4\r
+\r
+/* Small context (task swap==function call) */\r
+#define SAVE_NVGPR(_x,_y)\r
+#define RESTORE_NVGPR(_x,_y)\r
+\r
+/* Save volatile regs, NOT preserved by function calls */\r
+#define SAVE_VGPR(_x,_y)\r
+#define RESTORE_VGPR(_x,_y)\r
+\r
+/* Large context (interrupt) */\r
+#define SAVE_ALL_GPR(_x,_y)\r
+#define RESTORE_ALL_GPR(_x,_y)\r
+\r
+#define C_SIZE 16\r
+#define C_SP_OFF 0\r
+#define C_CONTEXT_OFF 4\r
+#define C_LR_OFF 8\r
+#define C_CR_OFF 12\r
+\r
+#define C_CONTEXT_OFFS 10\r
+\r
+#define SC_SIZE 32\r
+\r
+#if !defined(_ASSEMBLER_)\r
+\r
+/* These are auto-magically pushed by the hardware */\r
+typedef struct StackException {\r
+ uint32_t backChain;\r
+ uint32_t psr;\r
+ uint32_t pc;\r
+ uint32_t lr;\r
+ uint32_t r12;\r
+ uint32_t r3;\r
+ uint32_t r2;\r
+ uint32_t r1;\r
+} StackExceptionType;\r
+\r
+typedef struct StackNvgpr {\r
+ uint32_t r4;\r
+ uint32_t r5;\r
+ uint32_t r6;\r
+ uint32_t r7;\r
+ uint32_t r8;\r
+ uint32_t r10;\r
+ uint32_t r11;\r
+ uint32_t va;\r
+} StackNvgprType;\r
+\r
+struct StackVGpr {\r
+ uint32_t i_have_no_idea;\r
+};\r
+\r
+\r
+typedef struct StackCallAndContext {\r
+ uint32_t context;\r
+ // possibly some backchains and other stuff here..\r
+} StackCallAndContextType;\r
+\r
+#endif /* _ASSEMBLER_ */\r
+\r
+\r
+#endif /* CONTEXT_H_ */\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file startup_stm32f10x_cl.s\r
+ * @author MCD Application Team\r
+ * @version V3.1.0\r
+ * @date 06/19/2009\r
+ * @brief STM32F10x Connectivity line Devices vector table for RIDE7 toolchain.\r
+ * This module performs:\r
+ * - Set the initial SP\r
+ * - Set the initial PC == Reset_Handler,\r
+ * - Set the vector table entries with the exceptions ISR \r
+ * address.\r
+ * - Branches to main in the C library (which eventually\r
+ * calls main()).\r
+ * After Reset the Cortex-M3 processor is in Thread mode,\r
+ * priority is Privileged, and the Stack is set to Main.\r
+ *******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>\r
+ */ \r
+ \r
+ .syntax unified\r
+ .cpu cortex-m3\r
+ .fpu softvfp\r
+ .thumb\r
+\r
+.global g_pfnVectors\r
+.global SystemInit_ExtMemCtl_Dummy\r
+.global Default_Handler\r
+\r
+/* start address for the initialization values of the .data section. \r
+defined in linker script */\r
+.word _sidata\r
+/* start address for the .data section. defined in linker script */ \r
+.word _sdata\r
+/* end address for the .data section. defined in linker script */\r
+.word _edata\r
+/* start address for the .bss section. defined in linker script */\r
+.word _sbss\r
+/* end address for the .bss section. defined in linker script */\r
+.word _ebss\r
+\r
+.equ BootRAM, 0xF1E0F85F\r
+/**\r
+ * @brief This is the code that gets called when the processor first\r
+ * starts execution following a reset event. Only the absolutely\r
+ * necessary set is performed, after which the application\r
+ * supplied main() routine is called. \r
+ * @param None\r
+ * @retval : None\r
+*/\r
+\r
+ .section .text.Reset_Handler\r
+ .weak Reset_Handler\r
+ .type Reset_Handler, %function\r
+Reset_Handler: \r
+\r
+/* Copy the data segment initializers from flash to SRAM */ \r
+ movs r1, #0\r
+ b LoopCopyDataInit\r
+\r
+CopyDataInit:\r
+ ldr r3, =_sidata\r
+ ldr r3, [r3, r1]\r
+ str r3, [r0, r1]\r
+ adds r1, r1, #4\r
+ \r
+LoopCopyDataInit:\r
+ ldr r0, =_sdata\r
+ ldr r3, =_edata\r
+ adds r2, r0, r1\r
+ cmp r2, r3\r
+ bcc CopyDataInit\r
+ ldr r2, =_sbss\r
+ b LoopFillZerobss\r
+\r
+/* Zero fill the bss segment. */ \r
+FillZerobss:\r
+ movs r3, #0\r
+ str r3, [r2], #4\r
+ \r
+LoopFillZerobss:\r
+ ldr r3, = _ebss\r
+ cmp r2, r3\r
+ bcc FillZerobss\r
+/* Call the application's entry point.*/\r
+ bl main\r
+ bx lr \r
+.size Reset_Handler, .-Reset_Handler\r
+\r
+/**\r
+ * @brief This is the code that gets called when the processor receives an \r
+ * unexpected interrupt. This simply enters an infinite loop, preserving\r
+ * the system state for examination by a debugger.\r
+ *\r
+ * @param None \r
+ * @retval : None \r
+*/\r
+ .section .text.Default_Handler,"ax",%progbits\r
+Default_Handler:\r
+Infinite_Loop:\r
+ b Infinite_Loop\r
+ .size Default_Handler, .-Default_Handler\r
+\r
+/******************************************************************************\r
+*\r
+* The minimal vector table for a Cortex M3. Note that the proper constructs\r
+* must be placed on this to ensure that it ends up at physical address\r
+* 0x0000.0000.\r
+*\r
+******************************************************************************/ \r
+ .section .isr_vector,"a",%progbits\r
+ .type g_pfnVectors, %object\r
+ .size g_pfnVectors, .-g_pfnVectors\r
+ \r
+ \r
+g_pfnVectors:\r
+ .word _estack\r
+ .word Reset_Handler\r
+ .word NMI_Handler\r
+ .word HardFault_Handler\r
+ .word MemManage_Handler\r
+ .word BusFault_Handler\r
+ .word UsageFault_Handler\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word SVC_Handler\r
+ .word DebugMon_Handler\r
+ .word 0\r
+ .word PendSV_Handler\r
+ .word SysTick_Handler\r
+ .word WWDG_IRQHandler\r
+ .word PVD_IRQHandler\r
+ .word TAMPER_IRQHandler\r
+ .word RTC_IRQHandler\r
+ .word FLASH_IRQHandler\r
+ .word RCC_IRQHandler\r
+ .word EXTI0_IRQHandler\r
+ .word EXTI1_IRQHandler\r
+ .word EXTI2_IRQHandler\r
+ .word EXTI3_IRQHandler\r
+ .word EXTI4_IRQHandler\r
+ .word DMA1_Channel1_IRQHandler\r
+ .word DMA1_Channel2_IRQHandler\r
+ .word DMA1_Channel3_IRQHandler\r
+ .word DMA1_Channel4_IRQHandler\r
+ .word DMA1_Channel5_IRQHandler\r
+ .word DMA1_Channel6_IRQHandler\r
+ .word DMA1_Channel7_IRQHandler\r
+ .word ADC1_2_IRQHandler\r
+ .word CAN1_TX_IRQHandler\r
+ .word CAN1_RX0_IRQHandler\r
+ .word CAN1_RX1_IRQHandler\r
+ .word CAN1_SCE_IRQHandler\r
+ .word EXTI9_5_IRQHandler\r
+ .word TIM1_BRK_IRQHandler\r
+ .word TIM1_UP_IRQHandler\r
+ .word TIM1_TRG_COM_IRQHandler\r
+ .word TIM1_CC_IRQHandler\r
+ .word TIM2_IRQHandler\r
+ .word TIM3_IRQHandler\r
+ .word TIM4_IRQHandler\r
+ .word I2C1_EV_IRQHandler\r
+ .word I2C1_ER_IRQHandler\r
+ .word I2C2_EV_IRQHandler\r
+ .word I2C2_ER_IRQHandler\r
+ .word SPI1_IRQHandler\r
+ .word SPI2_IRQHandler\r
+ .word USART1_IRQHandler\r
+ .word USART2_IRQHandler\r
+ .word USART3_IRQHandler\r
+ .word EXTI15_10_IRQHandler\r
+ .word RTCAlarm_IRQHandler\r
+ .word OTG_FS_WKUP_IRQHandler \r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word TIM5_IRQHandler \r
+ .word SPI3_IRQHandler \r
+ .word UART4_IRQHandler \r
+ .word UART5_IRQHandler \r
+ .word TIM6_IRQHandler \r
+ .word TIM7_IRQHandler \r
+ .word DMA2_Channel1_IRQHandler \r
+ .word DMA2_Channel2_IRQHandler \r
+ .word DMA2_Channel3_IRQHandler \r
+ .word DMA2_Channel4_IRQHandler \r
+ .word DMA2_Channel5_IRQHandler \r
+ .word ETH_IRQHandler \r
+ .word ETH_WKUP_IRQHandler \r
+ .word CAN2_TX_IRQHandler \r
+ .word CAN2_RX0_IRQHandler \r
+ .word CAN2_RX1_IRQHandler \r
+ .word CAN2_SCE_IRQHandler \r
+ .word OTG_FS_IRQHandler \r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0 \r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0 \r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0 \r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0 \r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0 \r
+ .word BootRAM /* @0x1E0. This is for boot in RAM mode for \r
+ STM32F10x Connectivity line Devices. */\r
+ \r
+/*******************************************************************************\r
+*\r
+* Provide weak aliases for each Exception handler to the Default_Handler. \r
+* As they are weak aliases, any function with the same name will override \r
+* this definition.\r
+*\r
+*******************************************************************************/\r
+ .weak NMI_Handler\r
+ .thumb_set NMI_Handler,Default_Handler\r
+ \r
+ .weak HardFault_Handler\r
+ .thumb_set HardFault_Handler,Default_Handler\r
+ \r
+ .weak MemManage_Handler\r
+ .thumb_set MemManage_Handler,Default_Handler\r
+ \r
+ .weak BusFault_Handler\r
+ .thumb_set BusFault_Handler,Default_Handler\r
+\r
+ .weak UsageFault_Handler\r
+ .thumb_set UsageFault_Handler,Default_Handler\r
+\r
+ .weak SVC_Handler\r
+ .thumb_set SVC_Handler,Default_Handler\r
+\r
+ .weak DebugMon_Handler\r
+ .thumb_set DebugMon_Handler,Default_Handler\r
+\r
+ .weak PendSV_Handler\r
+ .thumb_set PendSV_Handler,Default_Handler\r
+\r
+ .weak SysTick_Handler\r
+ .thumb_set SysTick_Handler,Default_Handler\r
+\r
+ .weak WWDG_IRQHandler\r
+ .thumb_set WWDG_IRQHandler,Default_Handler\r
+\r
+ .weak PVD_IRQHandler\r
+ .thumb_set PVD_IRQHandler,Default_Handler\r
+\r
+ .weak TAMPER_IRQHandler\r
+ .thumb_set TAMPER_IRQHandler,Default_Handler\r
+\r
+ .weak RTC_IRQHandler\r
+ .thumb_set RTC_IRQHandler,Default_Handler\r
+\r
+ .weak FLASH_IRQHandler\r
+ .thumb_set FLASH_IRQHandler,Default_Handler\r
+\r
+ .weak RCC_IRQHandler\r
+ .thumb_set RCC_IRQHandler,Default_Handler\r
+\r
+ .weak EXTI0_IRQHandler\r
+ .thumb_set EXTI0_IRQHandler,Default_Handler\r
+\r
+ .weak EXTI1_IRQHandler\r
+ .thumb_set EXTI1_IRQHandler,Default_Handler\r
+\r
+ .weak EXTI2_IRQHandler\r
+ .thumb_set EXTI2_IRQHandler,Default_Handler\r
+\r
+ .weak EXTI3_IRQHandler\r
+ .thumb_set EXTI3_IRQHandler,Default_Handler\r
+\r
+ .weak EXTI4_IRQHandler\r
+ .thumb_set EXTI4_IRQHandler,Default_Handler\r
+\r
+ .weak DMA1_Channel1_IRQHandler\r
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler\r
+\r
+ .weak DMA1_Channel2_IRQHandler\r
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler\r
+\r
+ .weak DMA1_Channel3_IRQHandler\r
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler\r
+\r
+ .weak DMA1_Channel4_IRQHandler\r
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler\r
+\r
+ .weak DMA1_Channel5_IRQHandler\r
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler\r
+\r
+ .weak DMA1_Channel6_IRQHandler\r
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler\r
+\r
+ .weak DMA1_Channel7_IRQHandler\r
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler\r
+\r
+ .weak ADC1_2_IRQHandler\r
+ .thumb_set ADC1_2_IRQHandler,Default_Handler\r
+\r
+ .weak CAN1_TX_IRQHandler\r
+ .thumb_set CAN1_TX_IRQHandler,Default_Handler\r
+\r
+ .weak CAN1_RX0_IRQHandler\r
+ .thumb_set CAN1_RX0_IRQHandler,Default_Handler\r
+\r
+ .weak CAN1_RX1_IRQHandler\r
+ .thumb_set CAN1_RX1_IRQHandler,Default_Handler\r
+\r
+ .weak CAN1_SCE_IRQHandler\r
+ .thumb_set CAN1_SCE_IRQHandler,Default_Handler\r
+\r
+ .weak EXTI9_5_IRQHandler\r
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler\r
+\r
+ .weak TIM1_BRK_IRQHandler\r
+ .thumb_set TIM1_BRK_IRQHandler,Default_Handler\r
+\r
+ .weak TIM1_UP_IRQHandler\r
+ .thumb_set TIM1_UP_IRQHandler,Default_Handler\r
+\r
+ .weak TIM1_TRG_COM_IRQHandler\r
+ .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler\r
+\r
+ .weak TIM1_CC_IRQHandler\r
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler\r
+\r
+ .weak TIM2_IRQHandler\r
+ .thumb_set TIM2_IRQHandler,Default_Handler\r
+\r
+ .weak TIM3_IRQHandler\r
+ .thumb_set TIM3_IRQHandler,Default_Handler\r
+\r
+ .weak TIM4_IRQHandler\r
+ .thumb_set TIM4_IRQHandler,Default_Handler\r
+\r
+ .weak I2C1_EV_IRQHandler\r
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler\r
+\r
+ .weak I2C1_ER_IRQHandler\r
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler\r
+\r
+ .weak I2C2_EV_IRQHandler\r
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler\r
+\r
+ .weak I2C2_ER_IRQHandler\r
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler\r
+\r
+ .weak SPI1_IRQHandler\r
+ .thumb_set SPI1_IRQHandler,Default_Handler\r
+\r
+ .weak SPI2_IRQHandler\r
+ .thumb_set SPI2_IRQHandler,Default_Handler\r
+\r
+ .weak USART1_IRQHandler\r
+ .thumb_set USART1_IRQHandler,Default_Handler\r
+\r
+ .weak USART2_IRQHandler\r
+ .thumb_set USART2_IRQHandler,Default_Handler\r
+\r
+ .weak USART3_IRQHandler\r
+ .thumb_set USART3_IRQHandler,Default_Handler\r
+\r
+ .weak EXTI15_10_IRQHandler\r
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler\r
+\r
+ .weak RTCAlarm_IRQHandler\r
+ .thumb_set RTCAlarm_IRQHandler,Default_Handler\r
+\r
+ .weak OTG_FS_WKUP_IRQHandler\r
+ .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler\r
+\r
+ .weak TIM5_IRQHandler\r
+ .thumb_set TIM5_IRQHandler,Default_Handler\r
+\r
+ .weak SPI3_IRQHandler \r
+ .thumb_set SPI3_IRQHandler,Default_Handler\r
+\r
+ .weak UART4_IRQHandler \r
+ .thumb_set UART4_IRQHandler,Default_Handler\r
+\r
+ .weak UART5_IRQHandler \r
+ .thumb_set UART5_IRQHandler,Default_Handler\r
+\r
+ .weak TIM6_IRQHandler \r
+ .thumb_set TIM6_IRQHandler,Default_Handler\r
+\r
+ .weak TIM7_IRQHandler \r
+ .thumb_set TIM7_IRQHandler,Default_Handler\r
+\r
+ .weak DMA2_Channel1_IRQHandler \r
+ .thumb_set DMA2_Channel1_IRQHandler,Default_Handler\r
+\r
+ .weak DMA2_Channel2_IRQHandler \r
+ .thumb_set DMA2_Channel2_IRQHandler,Default_Handler\r
+\r
+ .weak DMA2_Channel3_IRQHandler \r
+ .thumb_set DMA2_Channel3_IRQHandler,Default_Handler\r
+\r
+ .weak DMA2_Channel4_IRQHandler \r
+ .thumb_set DMA2_Channel4_IRQHandler,Default_Handler\r
+\r
+ .weak DMA2_Channel5_IRQHandler \r
+ .thumb_set DMA2_Channel5_IRQHandler,Default_Handler\r
+\r
+ .weak ETH_IRQHandler \r
+ .thumb_set ETH_IRQHandler,Default_Handler\r
+\r
+ .weak ETH_WKUP_IRQHandler \r
+ .thumb_set ETH_WKUP_IRQHandler,Default_Handler\r
+\r
+ .weak CAN2_TX_IRQHandler \r
+ .thumb_set CAN2_TX_IRQHandler,Default_Handler\r
+\r
+ .weak CAN2_RX0_IRQHandler \r
+ .thumb_set CAN2_RX0_IRQHandler,Default_Handler\r
+\r
+ .weak CAN2_RX1_IRQHandler \r
+ .thumb_set CAN2_RX1_IRQHandler,Default_Handler\r
+\r
+ .weak CAN2_SCE_IRQHandler \r
+ .thumb_set CAN2_SCE_IRQHandler,Default_Handler\r
+\r
+ .weak OTG_FS_IRQHandler \r
+ .thumb_set OTG_FS_IRQHandler ,Default_Handler\r
+ \r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file startup_stm32f10x_hd.s\r
+ * @author MCD Application Team\r
+ * @version V3.1.0\r
+ * @date 06/19/2009\r
+ * @brief STM32F10x High Density Devices vector table for RIDE7 toolchain. \r
+ * This module performs:\r
+ * - Set the initial SP\r
+ * - Set the initial PC == Reset_Handler,\r
+ * - Set the vector table entries with the exceptions ISR address,\r
+ * - Configure external SRAM mounted on STM3210E-EVAL board\r
+ * to be used as data memory (optional, to be enabled by user)\r
+ * - Branches to main in the C library (which eventually\r
+ * calls main()).\r
+ * After Reset the Cortex-M3 processor is in Thread mode,\r
+ * priority is Privileged, and the Stack is set to Main.\r
+ *******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>\r
+ */ \r
+ \r
+ .syntax unified\r
+ .cpu cortex-m3\r
+ .fpu softvfp\r
+ .thumb\r
+\r
+.global g_pfnVectors\r
+.global SystemInit_ExtMemCtl_Dummy\r
+.global Default_Handler\r
+\r
+/* start address for the initialization values of the .data section. \r
+defined in linker script */\r
+.word _sidata\r
+/* start address for the .data section. defined in linker script */ \r
+.word _sdata\r
+/* end address for the .data section. defined in linker script */\r
+.word _edata\r
+/* start address for the .bss section. defined in linker script */\r
+.word _sbss\r
+/* end address for the .bss section. defined in linker script */\r
+.word _ebss\r
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */\r
+\r
+.equ Initial_spTop, 0x20000400 \r
+.equ BootRAM, 0xF1E0F85F\r
+/**\r
+ * @brief This is the code that gets called when the processor first\r
+ * starts execution following a reset event. Only the absolutely\r
+ * necessary set is performed, after which the application\r
+ * supplied main() routine is called. \r
+ * @param None\r
+ * @retval : None\r
+*/\r
+\r
+ .section .text.Reset_Handler\r
+ .weak Reset_Handler\r
+ .type Reset_Handler, %function\r
+Reset_Handler: \r
+\r
+/* FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is \r
+ required, then adjust the Register Addresses */\r
+ bl SystemInit_ExtMemCtl\r
+/* restore original stack pointer */ \r
+ LDR r0, =_estack\r
+ MSR msp, r0\r
+/* Copy the data segment initializers from flash to SRAM */ \r
+ movs r1, #0\r
+ b LoopCopyDataInit\r
+\r
+CopyDataInit:\r
+ ldr r3, =_sidata\r
+ ldr r3, [r3, r1]\r
+ str r3, [r0, r1]\r
+ adds r1, r1, #4\r
+ \r
+LoopCopyDataInit:\r
+ ldr r0, =_sdata\r
+ ldr r3, =_edata\r
+ adds r2, r0, r1\r
+ cmp r2, r3\r
+ bcc CopyDataInit\r
+ ldr r2, =_sbss\r
+ b LoopFillZerobss\r
+/* Zero fill the bss segment. */ \r
+FillZerobss:\r
+ movs r3, #0\r
+ str r3, [r2], #4\r
+ \r
+LoopFillZerobss:\r
+ ldr r3, = _ebss\r
+ cmp r2, r3\r
+ bcc FillZerobss\r
+/* Call the application's entry point.*/\r
+ bl main\r
+ bx lr \r
+.size Reset_Handler, .-Reset_Handler\r
+\r
+/**\r
+ * @brief Dummy SystemInit_ExtMemCtl function \r
+ * @param None \r
+ * @retval : None \r
+*/\r
+ .section .text.SystemInit_ExtMemCtl_Dummy,"ax",%progbits\r
+SystemInit_ExtMemCtl_Dummy:\r
+ bx lr\r
+ .size SystemInit_ExtMemCtl_Dummy, .-SystemInit_ExtMemCtl_Dummy\r
+\r
+/**\r
+ * @brief This is the code that gets called when the processor receives an \r
+ * unexpected interrupt. This simply enters an infinite loop, preserving\r
+ * the system state for examination by a debugger.\r
+ *\r
+ * @param None \r
+ * @retval : None \r
+*/\r
+ .section .text.Default_Handler,"ax",%progbits\r
+Default_Handler:\r
+Infinite_Loop:\r
+ b Infinite_Loop\r
+ .size Default_Handler, .-Default_Handler\r
+/******************************************************************************\r
+*\r
+* The minimal vector table for a Cortex M3. Note that the proper constructs\r
+* must be placed on this to ensure that it ends up at physical address\r
+* 0x0000.0000.\r
+*\r
+******************************************************************************/ \r
+ .section .isr_vector,"a",%progbits\r
+ .type g_pfnVectors, %object\r
+ .size g_pfnVectors, .-g_pfnVectors\r
+ \r
+ \r
+g_pfnVectors:\r
+ .word Initial_spTop\r
+ .word Reset_Handler\r
+ .word NMI_Handler\r
+ .word HardFault_Handler\r
+ .word MemManage_Handler\r
+ .word BusFault_Handler\r
+ .word UsageFault_Handler\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word SVC_Handler\r
+ .word DebugMon_Handler\r
+ .word 0\r
+ .word PendSV_Handler\r
+ .word SysTick_Handler\r
+ .word WWDG_IRQHandler\r
+ .word PVD_IRQHandler\r
+ .word TAMPER_IRQHandler\r
+ .word RTC_IRQHandler\r
+ .word FLASH_IRQHandler\r
+ .word RCC_IRQHandler\r
+ .word EXTI0_IRQHandler\r
+ .word EXTI1_IRQHandler\r
+ .word EXTI2_IRQHandler\r
+ .word EXTI3_IRQHandler\r
+ .word EXTI4_IRQHandler\r
+ .word DMA1_Channel1_IRQHandler\r
+ .word DMA1_Channel2_IRQHandler\r
+ .word DMA1_Channel3_IRQHandler\r
+ .word DMA1_Channel4_IRQHandler\r
+ .word DMA1_Channel5_IRQHandler\r
+ .word DMA1_Channel6_IRQHandler\r
+ .word DMA1_Channel7_IRQHandler\r
+ .word ADC1_2_IRQHandler\r
+ .word USB_HP_CAN1_TX_IRQHandler\r
+ .word USB_LP_CAN1_RX0_IRQHandler\r
+ .word CAN1_RX1_IRQHandler\r
+ .word CAN1_SCE_IRQHandler\r
+ .word EXTI9_5_IRQHandler\r
+ .word TIM1_BRK_IRQHandler\r
+ .word TIM1_UP_IRQHandler\r
+ .word TIM1_TRG_COM_IRQHandler\r
+ .word TIM1_CC_IRQHandler\r
+ .word TIM2_IRQHandler\r
+ .word TIM3_IRQHandler\r
+ .word TIM4_IRQHandler\r
+ .word I2C1_EV_IRQHandler\r
+ .word I2C1_ER_IRQHandler\r
+ .word I2C2_EV_IRQHandler\r
+ .word I2C2_ER_IRQHandler\r
+ .word SPI1_IRQHandler\r
+ .word SPI2_IRQHandler\r
+ .word USART1_IRQHandler\r
+ .word USART2_IRQHandler\r
+ .word USART3_IRQHandler\r
+ .word EXTI15_10_IRQHandler\r
+ .word RTCAlarm_IRQHandler\r
+ .word USBWakeUp_IRQHandler\r
+ .word TIM8_BRK_IRQHandler\r
+ .word TIM8_UP_IRQHandler\r
+ .word TIM8_TRG_COM_IRQHandler\r
+ .word TIM8_CC_IRQHandler\r
+ .word ADC3_IRQHandler\r
+ .word FSMC_IRQHandler\r
+ .word SDIO_IRQHandler\r
+ .word TIM5_IRQHandler\r
+ .word SPI3_IRQHandler\r
+ .word UART4_IRQHandler\r
+ .word UART5_IRQHandler\r
+ .word TIM6_IRQHandler\r
+ .word TIM7_IRQHandler\r
+ .word DMA2_Channel1_IRQHandler\r
+ .word DMA2_Channel2_IRQHandler\r
+ .word DMA2_Channel3_IRQHandler\r
+ .word DMA2_Channel4_5_IRQHandler\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word BootRAM /* @0x1E0. This is for boot in RAM mode for \r
+ STM32F10x High Density devices. */\r
+ \r
+/*******************************************************************************\r
+*\r
+* Provide weak aliases for each Exception handler to the Default_Handler. \r
+* As they are weak aliases, any function with the same name will override \r
+* this definition.\r
+*\r
+*******************************************************************************/\r
+ \r
+ .weak NMI_Handler\r
+ .thumb_set NMI_Handler,Default_Handler\r
+ \r
+ .weak HardFault_Handler\r
+ .thumb_set HardFault_Handler,Default_Handler\r
+ \r
+ .weak MemManage_Handler\r
+ .thumb_set MemManage_Handler,Default_Handler\r
+ \r
+ .weak BusFault_Handler\r
+ .thumb_set BusFault_Handler,Default_Handler\r
+\r
+ .weak UsageFault_Handler\r
+ .thumb_set UsageFault_Handler,Default_Handler\r
+\r
+ .weak SVC_Handler\r
+ .thumb_set SVC_Handler,Default_Handler\r
+\r
+ .weak DebugMon_Handler\r
+ .thumb_set DebugMon_Handler,Default_Handler\r
+\r
+ .weak PendSV_Handler\r
+ .thumb_set PendSV_Handler,Default_Handler\r
+\r
+ .weak SysTick_Handler\r
+ .thumb_set SysTick_Handler,Default_Handler\r
+\r
+ .weak WWDG_IRQHandler\r
+ .thumb_set WWDG_IRQHandler,Default_Handler\r
+\r
+ .weak PVD_IRQHandler\r
+ .thumb_set PVD_IRQHandler,Default_Handler\r
+\r
+ .weak TAMPER_IRQHandler\r
+ .thumb_set TAMPER_IRQHandler,Default_Handler\r
+\r
+ .weak RTC_IRQHandler\r
+ .thumb_set RTC_IRQHandler,Default_Handler\r
+\r
+ .weak FLASH_IRQHandler\r
+ .thumb_set FLASH_IRQHandler,Default_Handler\r
+\r
+ .weak RCC_IRQHandler\r
+ .thumb_set RCC_IRQHandler,Default_Handler\r
+\r
+ .weak EXTI0_IRQHandler\r
+ .thumb_set EXTI0_IRQHandler,Default_Handler\r
+\r
+ .weak EXTI1_IRQHandler\r
+ .thumb_set EXTI1_IRQHandler,Default_Handler\r
+\r
+ .weak EXTI2_IRQHandler\r
+ .thumb_set EXTI2_IRQHandler,Default_Handler\r
+\r
+ .weak EXTI3_IRQHandler\r
+ .thumb_set EXTI3_IRQHandler,Default_Handler\r
+\r
+ .weak EXTI4_IRQHandler\r
+ .thumb_set EXTI4_IRQHandler,Default_Handler\r
+\r
+ .weak DMA1_Channel1_IRQHandler\r
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler\r
+\r
+ .weak DMA1_Channel2_IRQHandler\r
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler\r
+\r
+ .weak DMA1_Channel3_IRQHandler\r
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler\r
+\r
+ .weak DMA1_Channel4_IRQHandler\r
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler\r
+\r
+ .weak DMA1_Channel5_IRQHandler\r
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler\r
+\r
+ .weak DMA1_Channel6_IRQHandler\r
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler\r
+\r
+ .weak DMA1_Channel7_IRQHandler\r
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler\r
+\r
+ .weak ADC1_2_IRQHandler\r
+ .thumb_set ADC1_2_IRQHandler,Default_Handler\r
+\r
+ .weak USB_HP_CAN1_TX_IRQHandler\r
+ .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler\r
+\r
+ .weak USB_LP_CAN1_RX0_IRQHandler\r
+ .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler\r
+\r
+ .weak CAN1_RX1_IRQHandler\r
+ .thumb_set CAN1_RX1_IRQHandler,Default_Handler\r
+\r
+ .weak CAN1_SCE_IRQHandler\r
+ .thumb_set CAN1_SCE_IRQHandler,Default_Handler\r
+\r
+ .weak EXTI9_5_IRQHandler\r
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler\r
+\r
+ .weak TIM1_BRK_IRQHandler\r
+ .thumb_set TIM1_BRK_IRQHandler,Default_Handler\r
+\r
+ .weak TIM1_UP_IRQHandler\r
+ .thumb_set TIM1_UP_IRQHandler,Default_Handler\r
+\r
+ .weak TIM1_TRG_COM_IRQHandler\r
+ .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler\r
+\r
+ .weak TIM1_CC_IRQHandler\r
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler\r
+\r
+ .weak TIM2_IRQHandler\r
+ .thumb_set TIM2_IRQHandler,Default_Handler\r
+\r
+ .weak TIM3_IRQHandler\r
+ .thumb_set TIM3_IRQHandler,Default_Handler\r
+\r
+ .weak TIM4_IRQHandler\r
+ .thumb_set TIM4_IRQHandler,Default_Handler\r
+\r
+ .weak I2C1_EV_IRQHandler\r
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler\r
+\r
+ .weak I2C1_ER_IRQHandler\r
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler\r
+\r
+ .weak I2C2_EV_IRQHandler\r
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler\r
+\r
+ .weak I2C2_ER_IRQHandler\r
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler\r
+\r
+ .weak SPI1_IRQHandler\r
+ .thumb_set SPI1_IRQHandler,Default_Handler\r
+\r
+ .weak SPI2_IRQHandler\r
+ .thumb_set SPI2_IRQHandler,Default_Handler\r
+\r
+ .weak USART1_IRQHandler\r
+ .thumb_set USART1_IRQHandler,Default_Handler\r
+\r
+ .weak USART2_IRQHandler\r
+ .thumb_set USART2_IRQHandler,Default_Handler\r
+\r
+ .weak USART3_IRQHandler\r
+ .thumb_set USART3_IRQHandler,Default_Handler\r
+\r
+ .weak EXTI15_10_IRQHandler\r
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler\r
+\r
+ .weak RTCAlarm_IRQHandler\r
+ .thumb_set RTCAlarm_IRQHandler,Default_Handler\r
+\r
+ .weak USBWakeUp_IRQHandler\r
+ .thumb_set USBWakeUp_IRQHandler,Default_Handler\r
+\r
+ .weak TIM8_BRK_IRQHandler\r
+ .thumb_set TIM8_BRK_IRQHandler,Default_Handler\r
+\r
+ .weak TIM8_UP_IRQHandler\r
+ .thumb_set TIM8_UP_IRQHandler,Default_Handler\r
+\r
+ .weak TIM8_TRG_COM_IRQHandler\r
+ .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler\r
+\r
+ .weak TIM8_CC_IRQHandler\r
+ .thumb_set TIM8_CC_IRQHandler,Default_Handler\r
+\r
+ .weak ADC3_IRQHandler\r
+ .thumb_set ADC3_IRQHandler,Default_Handler\r
+\r
+ .weak FSMC_IRQHandler\r
+ .thumb_set FSMC_IRQHandler,Default_Handler\r
+\r
+ .weak SDIO_IRQHandler\r
+ .thumb_set SDIO_IRQHandler,Default_Handler\r
+\r
+ .weak TIM5_IRQHandler\r
+ .thumb_set TIM5_IRQHandler,Default_Handler\r
+\r
+ .weak SPI3_IRQHandler\r
+ .thumb_set SPI3_IRQHandler,Default_Handler\r
+\r
+ .weak UART4_IRQHandler\r
+ .thumb_set UART4_IRQHandler,Default_Handler\r
+\r
+ .weak UART5_IRQHandler\r
+ .thumb_set UART5_IRQHandler,Default_Handler\r
+\r
+ .weak TIM6_IRQHandler\r
+ .thumb_set TIM6_IRQHandler,Default_Handler\r
+\r
+ .weak TIM7_IRQHandler\r
+ .thumb_set TIM7_IRQHandler,Default_Handler\r
+\r
+ .weak DMA2_Channel1_IRQHandler\r
+ .thumb_set DMA2_Channel1_IRQHandler,Default_Handler\r
+\r
+ .weak DMA2_Channel2_IRQHandler\r
+ .thumb_set DMA2_Channel2_IRQHandler,Default_Handler\r
+\r
+ .weak DMA2_Channel3_IRQHandler\r
+ .thumb_set DMA2_Channel3_IRQHandler,Default_Handler\r
+\r
+ .weak DMA2_Channel4_5_IRQHandler\r
+ .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler\r
+\r
+ .weak SystemInit_ExtMemCtl\r
+ .thumb_set SystemInit_ExtMemCtl,SystemInit_ExtMemCtl_Dummy\r
+\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file startup_stm32f10x_ld.s\r
+ * @author MCD Application Team\r
+ * @version V3.1.0\r
+ * @date 06/19/2009\r
+ * @brief STM32F10x Low Density Devices vector table for RIDE7 toolchain.\r
+ * This module performs:\r
+ * - Set the initial SP\r
+ * - Set the initial PC == Reset_Handler,\r
+ * - Set the vector table entries with the exceptions ISR address.\r
+ * - Branches to main in the C library (which eventually\r
+ * calls main()).\r
+ * After Reset the Cortex-M3 processor is in Thread mode,\r
+ * priority is Privileged, and the Stack is set to Main.\r
+ *******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>\r
+ */ \r
+ \r
+ .syntax unified\r
+ .cpu cortex-m3\r
+ .fpu softvfp\r
+ .thumb\r
+\r
+.global g_pfnVectors\r
+.global SystemInit_ExtMemCtl_Dummy\r
+.global Default_Handler\r
+\r
+/* start address for the initialization values of the .data section. \r
+defined in linker script */\r
+.word _sidata\r
+/* start address for the .data section. defined in linker script */ \r
+.word _sdata\r
+/* end address for the .data section. defined in linker script */\r
+.word _edata\r
+/* start address for the .bss section. defined in linker script */\r
+.word _sbss\r
+/* end address for the .bss section. defined in linker script */\r
+.word _ebss\r
+\r
+.equ BootRAM, 0xF108F85F\r
+/**\r
+ * @brief This is the code that gets called when the processor first\r
+ * starts execution following a reset event. Only the absolutely\r
+ * necessary set is performed, after which the application\r
+ * supplied main() routine is called. \r
+ * @param None\r
+ * @retval : None\r
+*/\r
+\r
+ .section .text.Reset_Handler\r
+ .weak Reset_Handler\r
+ .type Reset_Handler, %function\r
+Reset_Handler: \r
+\r
+/* Copy the data segment initializers from flash to SRAM */ \r
+ movs r1, #0\r
+ b LoopCopyDataInit\r
+\r
+CopyDataInit:\r
+ ldr r3, =_sidata\r
+ ldr r3, [r3, r1]\r
+ str r3, [r0, r1]\r
+ adds r1, r1, #4\r
+ \r
+LoopCopyDataInit:\r
+ ldr r0, =_sdata\r
+ ldr r3, =_edata\r
+ adds r2, r0, r1\r
+ cmp r2, r3\r
+ bcc CopyDataInit\r
+ ldr r2, =_sbss\r
+ b LoopFillZerobss\r
+/* Zero fill the bss segment. */ \r
+FillZerobss:\r
+ movs r3, #0\r
+ str r3, [r2], #4\r
+ \r
+LoopFillZerobss:\r
+ ldr r3, = _ebss\r
+ cmp r2, r3\r
+ bcc FillZerobss\r
+/* Call the application's entry point.*/\r
+ bl main\r
+ bx lr \r
+.size Reset_Handler, .-Reset_Handler\r
+\r
+/**\r
+ * @brief This is the code that gets called when the processor receives an \r
+ * unexpected interrupt. This simply enters an infinite loop, preserving\r
+ * the system state for examination by a debugger.\r
+ *\r
+ * @param None \r
+ * @retval : None \r
+*/\r
+ .section .text.Default_Handler,"ax",%progbits\r
+Default_Handler:\r
+Infinite_Loop:\r
+ b Infinite_Loop\r
+ .size Default_Handler, .-Default_Handler\r
+/******************************************************************************\r
+*\r
+* The minimal vector table for a Cortex M3. Note that the proper constructs\r
+* must be placed on this to ensure that it ends up at physical address\r
+* 0x0000.0000.\r
+*\r
+******************************************************************************/ \r
+ .section .isr_vector,"a",%progbits\r
+ .type g_pfnVectors, %object\r
+ .size g_pfnVectors, .-g_pfnVectors\r
+ \r
+ \r
+g_pfnVectors:\r
+ .word _estack\r
+ .word Reset_Handler\r
+ .word NMI_Handler\r
+ .word HardFault_Handler\r
+ .word MemManage_Handler\r
+ .word BusFault_Handler\r
+ .word UsageFault_Handler\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word SVC_Handler\r
+ .word DebugMon_Handler\r
+ .word 0\r
+ .word PendSV_Handler\r
+ .word SysTick_Handler\r
+ .word WWDG_IRQHandler\r
+ .word PVD_IRQHandler\r
+ .word TAMPER_IRQHandler\r
+ .word RTC_IRQHandler\r
+ .word FLASH_IRQHandler\r
+ .word RCC_IRQHandler\r
+ .word EXTI0_IRQHandler\r
+ .word EXTI1_IRQHandler\r
+ .word EXTI2_IRQHandler\r
+ .word EXTI3_IRQHandler\r
+ .word EXTI4_IRQHandler\r
+ .word DMA1_Channel1_IRQHandler\r
+ .word DMA1_Channel2_IRQHandler\r
+ .word DMA1_Channel3_IRQHandler\r
+ .word DMA1_Channel4_IRQHandler\r
+ .word DMA1_Channel5_IRQHandler\r
+ .word DMA1_Channel6_IRQHandler\r
+ .word DMA1_Channel7_IRQHandler\r
+ .word ADC1_2_IRQHandler\r
+ .word USB_HP_CAN1_TX_IRQHandler\r
+ .word USB_LP_CAN1_RX0_IRQHandler\r
+ .word CAN1_RX1_IRQHandler\r
+ .word CAN1_SCE_IRQHandler\r
+ .word EXTI9_5_IRQHandler\r
+ .word TIM1_BRK_IRQHandler\r
+ .word TIM1_UP_IRQHandler\r
+ .word TIM1_TRG_COM_IRQHandler\r
+ .word TIM1_CC_IRQHandler\r
+ .word TIM2_IRQHandler\r
+ .word TIM3_IRQHandler\r
+ 0\r
+ .word I2C1_EV_IRQHandler\r
+ .word I2C1_ER_IRQHandler\r
+ 0\r
+ 0\r
+ .word SPI1_IRQHandler\r
+ 0\r
+ .word USART1_IRQHandler\r
+ .word USART2_IRQHandler\r
+ 0\r
+ .word EXTI15_10_IRQHandler\r
+ .word RTCAlarm_IRQHandler\r
+ .word USBWakeUp_IRQHandler \r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word BootRAM /* @0x108. This is for boot in RAM mode for \r
+ STM32F10x Low Density devices.*/\r
+ \r
+/*******************************************************************************\r
+*\r
+* Provide weak aliases for each Exception handler to the Default_Handler. \r
+* As they are weak aliases, any function with the same name will override \r
+* this definition.\r
+*\r
+*******************************************************************************/\r
+ \r
+ .weak NMI_Handler\r
+ .thumb_set NMI_Handler,Default_Handler\r
+ \r
+ .weak HardFault_Handler\r
+ .thumb_set HardFault_Handler,Default_Handler\r
+ \r
+ .weak MemManage_Handler\r
+ .thumb_set MemManage_Handler,Default_Handler\r
+ \r
+ .weak BusFault_Handler\r
+ .thumb_set BusFault_Handler,Default_Handler\r
+\r
+ .weak UsageFault_Handler\r
+ .thumb_set UsageFault_Handler,Default_Handler\r
+\r
+ .weak SVC_Handler\r
+ .thumb_set SVC_Handler,Default_Handler\r
+\r
+ .weak DebugMon_Handler\r
+ .thumb_set DebugMon_Handler,Default_Handler\r
+\r
+ .weak PendSV_Handler\r
+ .thumb_set PendSV_Handler,Default_Handler\r
+\r
+ .weak SysTick_Handler\r
+ .thumb_set SysTick_Handler,Default_Handler\r
+\r
+ .weak WWDG_IRQHandler\r
+ .thumb_set WWDG_IRQHandler,Default_Handler\r
+\r
+ .weak PVD_IRQHandler\r
+ .thumb_set PVD_IRQHandler,Default_Handler\r
+\r
+ .weak TAMPER_IRQHandler\r
+ .thumb_set TAMPER_IRQHandler,Default_Handler\r
+\r
+ .weak RTC_IRQHandler\r
+ .thumb_set RTC_IRQHandler,Default_Handler\r
+\r
+ .weak FLASH_IRQHandler\r
+ .thumb_set FLASH_IRQHandler,Default_Handler\r
+\r
+ .weak RCC_IRQHandler\r
+ .thumb_set RCC_IRQHandler,Default_Handler\r
+\r
+ .weak EXTI0_IRQHandler\r
+ .thumb_set EXTI0_IRQHandler,Default_Handler\r
+\r
+ .weak EXTI1_IRQHandler\r
+ .thumb_set EXTI1_IRQHandler,Default_Handler\r
+\r
+ .weak EXTI2_IRQHandler\r
+ .thumb_set EXTI2_IRQHandler,Default_Handler\r
+\r
+ .weak EXTI3_IRQHandler\r
+ .thumb_set EXTI3_IRQHandler,Default_Handler\r
+\r
+ .weak EXTI4_IRQHandler\r
+ .thumb_set EXTI4_IRQHandler,Default_Handler\r
+\r
+ .weak DMA1_Channel1_IRQHandler\r
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler\r
+\r
+ .weak DMA1_Channel2_IRQHandler\r
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler\r
+\r
+ .weak DMA1_Channel3_IRQHandler\r
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler\r
+\r
+ .weak DMA1_Channel4_IRQHandler\r
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler\r
+\r
+ .weak DMA1_Channel5_IRQHandler\r
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler\r
+\r
+ .weak DMA1_Channel6_IRQHandler\r
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler\r
+\r
+ .weak DMA1_Channel7_IRQHandler\r
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler\r
+\r
+ .weak ADC1_2_IRQHandler\r
+ .thumb_set ADC1_2_IRQHandler,Default_Handler\r
+\r
+ .weak USB_HP_CAN1_TX_IRQHandler\r
+ .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler\r
+\r
+ .weak USB_LP_CAN1_RX0_IRQHandler\r
+ .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler\r
+\r
+ .weak CAN1_RX1_IRQHandler\r
+ .thumb_set CAN1_RX1_IRQHandler,Default_Handler\r
+\r
+ .weak CAN1_SCE_IRQHandler\r
+ .thumb_set CAN1_SCE_IRQHandler,Default_Handler\r
+\r
+ .weak EXTI9_5_IRQHandler\r
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler\r
+\r
+ .weak TIM1_BRK_IRQHandler\r
+ .thumb_set TIM1_BRK_IRQHandler,Default_Handler\r
+\r
+ .weak TIM1_UP_IRQHandler\r
+ .thumb_set TIM1_UP_IRQHandler,Default_Handler\r
+\r
+ .weak TIM1_TRG_COM_IRQHandler\r
+ .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler\r
+\r
+ .weak TIM1_CC_IRQHandler\r
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler\r
+\r
+ .weak TIM2_IRQHandler\r
+ .thumb_set TIM2_IRQHandler,Default_Handler\r
+\r
+ .weak TIM3_IRQHandler\r
+ .thumb_set TIM3_IRQHandler,Default_Handler\r
+\r
+ .weak I2C1_EV_IRQHandler\r
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler\r
+\r
+ .weak I2C1_ER_IRQHandler\r
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler\r
+\r
+ .weak SPI1_IRQHandler\r
+ .thumb_set SPI1_IRQHandler,Default_Handler\r
+\r
+ .weak USART1_IRQHandler\r
+ .thumb_set USART1_IRQHandler,Default_Handler\r
+\r
+ .weak USART2_IRQHandler\r
+ .thumb_set USART2_IRQHandler,Default_Handler\r
+\r
+ .weak EXTI15_10_IRQHandler\r
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler\r
+\r
+ .weak RTCAlarm_IRQHandler\r
+ .thumb_set RTCAlarm_IRQHandler,Default_Handler\r
+\r
+ .weak USBWakeUp_IRQHandler\r
+ .thumb_set USBWakeUp_IRQHandler,Default_Handler \r
+\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file startup_stm32f10x_md.s\r
+ * @author MCD Application Team\r
+ * @version V3.1.0\r
+ * @date 06/19/2009\r
+ * @brief STM32F10x Medium Density Devices vector table for RIDE7 toolchain.\r
+ * This module performs:\r
+ * - Set the initial SP\r
+ * - Set the initial PC == Reset_Handler,\r
+ * - Set the vector table entries with the exceptions ISR address\r
+ * - Branches to main in the C library (which eventually\r
+ * calls main()).\r
+ * After Reset the Cortex-M3 processor is in Thread mode,\r
+ * priority is Privileged, and the Stack is set to Main.\r
+ *******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>\r
+ */ \r
+ \r
+ .syntax unified\r
+ .cpu cortex-m3\r
+ .fpu softvfp\r
+ .thumb\r
+\r
+.global g_pfnVectors\r
+.global SystemInit_ExtMemCtl_Dummy\r
+.global Default_Handler\r
+\r
+/* start address for the initialization values of the .data section. \r
+defined in linker script */\r
+.word _sidata\r
+/* start address for the .data section. defined in linker script */ \r
+.word _sdata\r
+/* end address for the .data section. defined in linker script */\r
+.word _edata\r
+/* start address for the .bss section. defined in linker script */\r
+.word _sbss\r
+/* end address for the .bss section. defined in linker script */\r
+.word _ebss\r
+\r
+.equ BootRAM, 0xF108F85F\r
+/**\r
+ * @brief This is the code that gets called when the processor first\r
+ * starts execution following a reset event. Only the absolutely\r
+ * necessary set is performed, after which the application\r
+ * supplied main() routine is called. \r
+ * @param None\r
+ * @retval : None\r
+*/\r
+\r
+ .section .text.Reset_Handler\r
+ .weak Reset_Handler\r
+ .type Reset_Handler, %function\r
+Reset_Handler: \r
+\r
+/* Copy the data segment initializers from flash to SRAM */ \r
+ movs r1, #0\r
+ b LoopCopyDataInit\r
+\r
+CopyDataInit:\r
+ ldr r3, =_sidata\r
+ ldr r3, [r3, r1]\r
+ str r3, [r0, r1]\r
+ adds r1, r1, #4\r
+ \r
+LoopCopyDataInit:\r
+ ldr r0, =_sdata\r
+ ldr r3, =_edata\r
+ adds r2, r0, r1\r
+ cmp r2, r3\r
+ bcc CopyDataInit\r
+ ldr r2, =_sbss\r
+ b LoopFillZerobss\r
+/* Zero fill the bss segment. */ \r
+FillZerobss:\r
+ movs r3, #0\r
+ str r3, [r2], #4\r
+ \r
+LoopFillZerobss:\r
+ ldr r3, = _ebss\r
+ cmp r2, r3\r
+ bcc FillZerobss\r
+/* Call the application's entry point.*/\r
+ bl main\r
+ bx lr \r
+.size Reset_Handler, .-Reset_Handler\r
+\r
+/**\r
+ * @brief This is the code that gets called when the processor receives an \r
+ * unexpected interrupt. This simply enters an infinite loop, preserving\r
+ * the system state for examination by a debugger.\r
+ *\r
+ * @param None \r
+ * @retval : None \r
+*/\r
+ .section .text.Default_Handler,"ax",%progbits\r
+Default_Handler:\r
+Infinite_Loop:\r
+ b Infinite_Loop\r
+ .size Default_Handler, .-Default_Handler\r
+/******************************************************************************\r
+*\r
+* The minimal vector table for a Cortex M3. Note that the proper constructs\r
+* must be placed on this to ensure that it ends up at physical address\r
+* 0x0000.0000.\r
+*\r
+******************************************************************************/ \r
+ .section .isr_vector,"a",%progbits\r
+ .type g_pfnVectors, %object\r
+ .size g_pfnVectors, .-g_pfnVectors\r
+ \r
+ \r
+g_pfnVectors:\r
+ .word _estack\r
+ .word Reset_Handler\r
+ .word NMI_Handler\r
+ .word HardFault_Handler\r
+ .word MemManage_Handler\r
+ .word BusFault_Handler\r
+ .word UsageFault_Handler\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word SVC_Handler\r
+ .word DebugMon_Handler\r
+ .word 0\r
+ .word PendSV_Handler\r
+ .word SysTick_Handler\r
+ .word WWDG_IRQHandler\r
+ .word PVD_IRQHandler\r
+ .word TAMPER_IRQHandler\r
+ .word RTC_IRQHandler\r
+ .word FLASH_IRQHandler\r
+ .word RCC_IRQHandler\r
+ .word EXTI0_IRQHandler\r
+ .word EXTI1_IRQHandler\r
+ .word EXTI2_IRQHandler\r
+ .word EXTI3_IRQHandler\r
+ .word EXTI4_IRQHandler\r
+ .word DMA1_Channel1_IRQHandler\r
+ .word DMA1_Channel2_IRQHandler\r
+ .word DMA1_Channel3_IRQHandler\r
+ .word DMA1_Channel4_IRQHandler\r
+ .word DMA1_Channel5_IRQHandler\r
+ .word DMA1_Channel6_IRQHandler\r
+ .word DMA1_Channel7_IRQHandler\r
+ .word ADC1_2_IRQHandler\r
+ .word USB_HP_CAN1_TX_IRQHandler\r
+ .word USB_LP_CAN1_RX0_IRQHandler\r
+ .word CAN1_RX1_IRQHandler\r
+ .word CAN1_SCE_IRQHandler\r
+ .word EXTI9_5_IRQHandler\r
+ .word TIM1_BRK_IRQHandler\r
+ .word TIM1_UP_IRQHandler\r
+ .word TIM1_TRG_COM_IRQHandler\r
+ .word TIM1_CC_IRQHandler\r
+ .word TIM2_IRQHandler\r
+ .word TIM3_IRQHandler\r
+ .word TIM4_IRQHandler\r
+ .word I2C1_EV_IRQHandler\r
+ .word I2C1_ER_IRQHandler\r
+ .word I2C2_EV_IRQHandler\r
+ .word I2C2_ER_IRQHandler\r
+ .word SPI1_IRQHandler\r
+ .word SPI2_IRQHandler\r
+ .word USART1_IRQHandler\r
+ .word USART2_IRQHandler\r
+ .word USART3_IRQHandler\r
+ .word EXTI15_10_IRQHandler\r
+ .word RTCAlarm_IRQHandler\r
+ .word USBWakeUp_IRQHandler \r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word BootRAM /* @0x108. This is for boot in RAM mode for \r
+ STM32F10x Medium Density devices. */\r
+ \r
+/*******************************************************************************\r
+*\r
+* Provide weak aliases for each Exception handler to the Default_Handler. \r
+* As they are weak aliases, any function with the same name will override \r
+* this definition.\r
+*\r
+*******************************************************************************/\r
+ \r
+ .weak NMI_Handler\r
+ .thumb_set NMI_Handler,Default_Handler\r
+ \r
+ .weak HardFault_Handler\r
+ .thumb_set HardFault_Handler,Default_Handler\r
+ \r
+ .weak MemManage_Handler\r
+ .thumb_set MemManage_Handler,Default_Handler\r
+ \r
+ .weak BusFault_Handler\r
+ .thumb_set BusFault_Handler,Default_Handler\r
+\r
+ .weak UsageFault_Handler\r
+ .thumb_set UsageFault_Handler,Default_Handler\r
+\r
+ .weak SVC_Handler\r
+ .thumb_set SVC_Handler,Default_Handler\r
+\r
+ .weak DebugMon_Handler\r
+ .thumb_set DebugMon_Handler,Default_Handler\r
+\r
+ .weak PendSV_Handler\r
+ .thumb_set PendSV_Handler,Default_Handler\r
+\r
+ .weak SysTick_Handler\r
+ .thumb_set SysTick_Handler,Default_Handler\r
+\r
+ .weak WWDG_IRQHandler\r
+ .thumb_set WWDG_IRQHandler,Default_Handler\r
+\r
+ .weak PVD_IRQHandler\r
+ .thumb_set PVD_IRQHandler,Default_Handler\r
+\r
+ .weak TAMPER_IRQHandler\r
+ .thumb_set TAMPER_IRQHandler,Default_Handler\r
+\r
+ .weak RTC_IRQHandler\r
+ .thumb_set RTC_IRQHandler,Default_Handler\r
+\r
+ .weak FLASH_IRQHandler\r
+ .thumb_set FLASH_IRQHandler,Default_Handler\r
+\r
+ .weak RCC_IRQHandler\r
+ .thumb_set RCC_IRQHandler,Default_Handler\r
+\r
+ .weak EXTI0_IRQHandler\r
+ .thumb_set EXTI0_IRQHandler,Default_Handler\r
+\r
+ .weak EXTI1_IRQHandler\r
+ .thumb_set EXTI1_IRQHandler,Default_Handler\r
+\r
+ .weak EXTI2_IRQHandler\r
+ .thumb_set EXTI2_IRQHandler,Default_Handler\r
+\r
+ .weak EXTI3_IRQHandler\r
+ .thumb_set EXTI3_IRQHandler,Default_Handler\r
+\r
+ .weak EXTI4_IRQHandler\r
+ .thumb_set EXTI4_IRQHandler,Default_Handler\r
+\r
+ .weak DMA1_Channel1_IRQHandler\r
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler\r
+\r
+ .weak DMA1_Channel2_IRQHandler\r
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler\r
+\r
+ .weak DMA1_Channel3_IRQHandler\r
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler\r
+\r
+ .weak DMA1_Channel4_IRQHandler\r
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler\r
+\r
+ .weak DMA1_Channel5_IRQHandler\r
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler\r
+\r
+ .weak DMA1_Channel6_IRQHandler\r
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler\r
+\r
+ .weak DMA1_Channel7_IRQHandler\r
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler\r
+\r
+ .weak ADC1_2_IRQHandler\r
+ .thumb_set ADC1_2_IRQHandler,Default_Handler\r
+\r
+ .weak USB_HP_CAN1_TX_IRQHandler\r
+ .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler\r
+\r
+ .weak USB_LP_CAN1_RX0_IRQHandler\r
+ .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler\r
+\r
+ .weak CAN1_RX1_IRQHandler\r
+ .thumb_set CAN1_RX1_IRQHandler,Default_Handler\r
+\r
+ .weak CAN1_SCE_IRQHandler\r
+ .thumb_set CAN1_SCE_IRQHandler,Default_Handler\r
+\r
+ .weak EXTI9_5_IRQHandler\r
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler\r
+\r
+ .weak TIM1_BRK_IRQHandler\r
+ .thumb_set TIM1_BRK_IRQHandler,Default_Handler\r
+\r
+ .weak TIM1_UP_IRQHandler\r
+ .thumb_set TIM1_UP_IRQHandler,Default_Handler\r
+\r
+ .weak TIM1_TRG_COM_IRQHandler\r
+ .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler\r
+\r
+ .weak TIM1_CC_IRQHandler\r
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler\r
+\r
+ .weak TIM2_IRQHandler\r
+ .thumb_set TIM2_IRQHandler,Default_Handler\r
+\r
+ .weak TIM3_IRQHandler\r
+ .thumb_set TIM3_IRQHandler,Default_Handler\r
+\r
+ .weak TIM4_IRQHandler\r
+ .thumb_set TIM4_IRQHandler,Default_Handler\r
+\r
+ .weak I2C1_EV_IRQHandler\r
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler\r
+\r
+ .weak I2C1_ER_IRQHandler\r
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler\r
+\r
+ .weak I2C2_EV_IRQHandler\r
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler\r
+\r
+ .weak I2C2_ER_IRQHandler\r
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler\r
+\r
+ .weak SPI1_IRQHandler\r
+ .thumb_set SPI1_IRQHandler,Default_Handler\r
+\r
+ .weak SPI2_IRQHandler\r
+ .thumb_set SPI2_IRQHandler,Default_Handler\r
+\r
+ .weak USART1_IRQHandler\r
+ .thumb_set USART1_IRQHandler,Default_Handler\r
+\r
+ .weak USART2_IRQHandler\r
+ .thumb_set USART2_IRQHandler,Default_Handler\r
+\r
+ .weak USART3_IRQHandler\r
+ .thumb_set USART3_IRQHandler,Default_Handler\r
+\r
+ .weak EXTI15_10_IRQHandler\r
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler\r
+\r
+ .weak RTCAlarm_IRQHandler\r
+ .thumb_set RTCAlarm_IRQHandler,Default_Handler\r
+\r
+ .weak USBWakeUp_IRQHandler\r
+ .thumb_set USBWakeUp_IRQHandler,Default_Handler\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/**\r
+ ******************************************************************************\r
+ * @file system_stm32f10x.c\r
+ * @author MCD Application Team\r
+ * @version V3.1.0\r
+ * @date 06/19/2009\r
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.\r
+ ****************************************************************************** \r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/** @addtogroup CMSIS\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup stm32f10x_system\r
+ * @{\r
+ */ \r
+ \r
+/** @addtogroup STM32F10x_System_Private_Includes\r
+ * @{\r
+ */\r
+\r
+#include "stm32f10x.h"\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F10x_System_Private_TypesDefinitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F10x_System_Private_Defines\r
+ * @{\r
+ */\r
+\r
+/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)\r
+ frequency (after reset the HSI is used as SYSCLK source)\r
+ \r
+ IMPORTANT NOTE:\r
+ ============== \r
+ 1. After each device reset the HSI is used as System clock source.\r
+\r
+ 2. Please make sure that the selected System clock doesn't exceed your device's\r
+ maximum frequency.\r
+ \r
+ 3. If none of the define below is enabled, the HSI is used as System clock\r
+ source.\r
+\r
+ 4. The System clock configuration functions provided within this file assume that:\r
+ - For Low, Medium and High density devices an external 8MHz crystal is\r
+ used to drive the System clock.\r
+ - For Connectivity line devices an external 25MHz crystal is used to drive\r
+ the System clock.\r
+ If you are using different crystal you have to adapt those functions accordingly.\r
+ */\r
+ \r
+/* #define SYSCLK_FREQ_HSE HSE_Value */\r
+/* #define SYSCLK_FREQ_24MHz 24000000 */\r
+/* #define SYSCLK_FREQ_36MHz 36000000 */\r
+/* #define SYSCLK_FREQ_48MHz 48000000 */\r
+/* #define SYSCLK_FREQ_56MHz 56000000 */\r
+#define SYSCLK_FREQ_72MHz 72000000\r
+\r
+/*!< Uncomment the following line if you need to use external SRAM mounted\r
+ on STM3210E-EVAL board (STM32 High density devices) as data memory */ \r
+#ifdef STM32F10X_HD\r
+/* #define DATA_IN_ExtSRAM */\r
+#endif /* STM32F10X_HD */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F10x_System_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F10x_System_Private_Variables\r
+ * @{\r
+ */\r
+\r
+/*******************************************************************************\r
+* Clock Definitions\r
+*******************************************************************************/\r
+#ifdef SYSCLK_FREQ_HSE\r
+ const uint32_t SystemFrequency = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */\r
+ const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_HSE; /*!< System clock */\r
+ const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_HSE; /*!< AHB System bus speed */\r
+ const uint32_t SystemFrequency_APB1Clk = SYSCLK_FREQ_HSE; /*!< APB Peripheral bus 1 (low) speed */\r
+ const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_HSE; /*!< APB Peripheral bus 2 (high) speed */\r
+#elif defined SYSCLK_FREQ_24MHz\r
+ const uint32_t SystemFrequency = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */\r
+ const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_24MHz; /*!< System clock */\r
+ const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_24MHz; /*!< AHB System bus speed */\r
+ const uint32_t SystemFrequency_APB1Clk = SYSCLK_FREQ_24MHz; /*!< APB Peripheral bus 1 (low) speed */\r
+ const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_24MHz; /*!< APB Peripheral bus 2 (high) speed */\r
+#elif defined SYSCLK_FREQ_36MHz\r
+ const uint32_t SystemFrequency = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */\r
+ const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_36MHz; /*!< System clock */\r
+ const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_36MHz; /*!< AHB System bus speed */\r
+ const uint32_t SystemFrequency_APB1Clk = SYSCLK_FREQ_36MHz; /*!< APB Peripheral bus 1 (low) speed */\r
+ const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_36MHz; /*!< APB Peripheral bus 2 (high) speed */\r
+#elif defined SYSCLK_FREQ_48MHz\r
+ const uint32_t SystemFrequency = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */\r
+ const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_48MHz; /*!< System clock */\r
+ const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_48MHz; /*!< AHB System bus speed */\r
+ const uint32_t SystemFrequency_APB1Clk = (SYSCLK_FREQ_48MHz/2); /*!< APB Peripheral bus 1 (low) speed */\r
+ const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_48MHz; /*!< APB Peripheral bus 2 (high) speed */\r
+#elif defined SYSCLK_FREQ_56MHz\r
+ const uint32_t SystemFrequency = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */\r
+ const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_56MHz; /*!< System clock */\r
+ const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_56MHz; /*!< AHB System bus speed */\r
+ const uint32_t SystemFrequency_APB1Clk = (SYSCLK_FREQ_56MHz/2); /*!< APB Peripheral bus 1 (low) speed */\r
+ const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_56MHz; /*!< APB Peripheral bus 2 (high) speed */ \r
+#elif defined SYSCLK_FREQ_72MHz\r
+ const uint32_t SystemFrequency = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */\r
+ const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_72MHz; /*!< System clock */\r
+ const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_72MHz; /*!< AHB System bus speed */\r
+ const uint32_t SystemFrequency_APB1Clk = (SYSCLK_FREQ_72MHz/2); /*!< APB Peripheral bus 1 (low) speed */\r
+ const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_72MHz; /*!< APB Peripheral bus 2 (high) speed */\r
+#else /*!< HSI Selected as System Clock source */\r
+ const uint32_t SystemFrequency = HSI_Value; /*!< System Clock Frequency (Core Clock) */\r
+ const uint32_t SystemFrequency_SysClk = HSI_Value; /*!< System clock */\r
+ const uint32_t SystemFrequency_AHBClk = HSI_Value; /*!< AHB System bus speed */\r
+ const uint32_t SystemFrequency_APB1Clk = HSI_Value; /*!< APB Peripheral bus 1 (low) speed */\r
+ const uint32_t SystemFrequency_APB2Clk = HSI_Value; /*!< APB Peripheral bus 2 (high) speed */\r
+#endif\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F10x_System_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+static void SetSysClock(void);\r
+\r
+#ifdef SYSCLK_FREQ_HSE\r
+ static void SetSysClockToHSE(void);\r
+#elif defined SYSCLK_FREQ_24MHz\r
+ static void SetSysClockTo24(void);\r
+#elif defined SYSCLK_FREQ_36MHz\r
+ static void SetSysClockTo36(void);\r
+#elif defined SYSCLK_FREQ_48MHz\r
+ static void SetSysClockTo48(void);\r
+#elif defined SYSCLK_FREQ_56MHz\r
+ static void SetSysClockTo56(void); \r
+#elif defined SYSCLK_FREQ_72MHz\r
+ static void SetSysClockTo72(void);\r
+#endif\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F10x_System_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Setup the microcontroller system\r
+ * Initialize the Embedded Flash Interface, the PLL and update the SystemFrequency variable.\r
+ * @note This function should be used only after reset.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemInit (void)\r
+{\r
+ /* Reset the RCC clock configuration to the default reset state(for debug purpose) */\r
+ /* Set HSION bit */\r
+ RCC->CR |= (uint32_t)0x00000001;\r
+\r
+ /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */\r
+#ifndef STM32F10X_CL\r
+ RCC->CFGR &= (uint32_t)0xF8FF0000;\r
+#else\r
+ RCC->CFGR &= (uint32_t)0xF0FF0000;\r
+#endif /* STM32F10X_CL */ \r
+ \r
+ /* Reset HSEON, CSSON and PLLON bits */\r
+ RCC->CR &= (uint32_t)0xFEF6FFFF;\r
+\r
+ /* Reset HSEBYP bit */\r
+ RCC->CR &= (uint32_t)0xFFFBFFFF;\r
+\r
+ /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */\r
+ RCC->CFGR &= (uint32_t)0xFF80FFFF;\r
+\r
+#ifndef STM32F10X_CL\r
+ /* Disable all interrupts and clear pending bits */\r
+ RCC->CIR = 0x009F0000;\r
+#else\r
+ /* Reset PLL2ON and PLL3ON bits */\r
+ RCC->CR &= (uint32_t)0xEBFFFFFF;\r
+\r
+ /* Disable all interrupts and clear pending bits */\r
+ RCC->CIR = 0x00FF0000;\r
+\r
+ /* Reset CFGR2 register */\r
+ RCC->CFGR2 = 0x00000000;\r
+#endif /* STM32F10X_CL */\r
+ \r
+ /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */\r
+ /* Configure the Flash Latency cycles and enable prefetch buffer */\r
+ SetSysClock();\r
+\r
+}\r
+\r
+/**\r
+ * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+static void SetSysClock(void)\r
+{\r
+#ifdef SYSCLK_FREQ_HSE\r
+ SetSysClockToHSE();\r
+#elif defined SYSCLK_FREQ_24MHz\r
+ SetSysClockTo24();\r
+#elif defined SYSCLK_FREQ_36MHz\r
+ SetSysClockTo36();\r
+#elif defined SYSCLK_FREQ_48MHz\r
+ SetSysClockTo48();\r
+#elif defined SYSCLK_FREQ_56MHz\r
+ SetSysClockTo56(); \r
+#elif defined SYSCLK_FREQ_72MHz\r
+ SetSysClockTo72();\r
+#endif\r
+ \r
+ /* If none of the define above is enabled, the HSI is used as System clock\r
+ source (default after reset) */ \r
+}\r
+\r
+/**\r
+ * @brief Setup the external memory controller. Called in startup_stm32f10x.s \r
+ * before jump to __main\r
+ * @param None\r
+ * @retval None\r
+ */ \r
+#ifdef DATA_IN_ExtSRAM\r
+/**\r
+ * @brief Setup the external memory controller. \r
+ * Called in startup_stm32f10x_xx.s/.c before jump to main.\r
+ * This function configures the external SRAM mounted on STM3210E-EVAL\r
+ * board (STM32 High density devices). This SRAM will be used as program\r
+ * data memory (including heap and stack).\r
+ * @param None\r
+ * @retval None\r
+ */ \r
+void SystemInit_ExtMemCtl(void) \r
+{\r
+/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is \r
+ required, then adjust the Register Addresses */\r
+\r
+ /* Enable FSMC clock */\r
+ RCC->AHBENR = 0x00000114;\r
+ \r
+ /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */ \r
+ RCC->APB2ENR = 0x000001E0;\r
+ \r
+/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/\r
+/*---------------- SRAM Address lines configuration -------------------------*/\r
+/*---------------- NOE and NWE configuration --------------------------------*/ \r
+/*---------------- NE3 configuration ----------------------------------------*/\r
+/*---------------- NBL0, NBL1 configuration ---------------------------------*/\r
+ \r
+ GPIOD->CRL = 0x44BB44BB; \r
+ GPIOD->CRH = 0xBBBBBBBB;\r
+\r
+ GPIOE->CRL = 0xB44444BB; \r
+ GPIOE->CRH = 0xBBBBBBBB;\r
+\r
+ GPIOF->CRL = 0x44BBBBBB; \r
+ GPIOF->CRH = 0xBBBB4444;\r
+\r
+ GPIOG->CRL = 0x44BBBBBB; \r
+ GPIOG->CRH = 0x44444B44;\r
+ \r
+/*---------------- FSMC Configuration ---------------------------------------*/ \r
+/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/\r
+ \r
+ FSMC_Bank1->BTCR[4] = 0x00001011;\r
+ FSMC_Bank1->BTCR[5] = 0x00000200;\r
+}\r
+#endif /* DATA_IN_ExtSRAM */\r
+\r
+#ifdef SYSCLK_FREQ_HSE\r
+/**\r
+ * @brief Selects HSE as System clock source and configure HCLK, PCLK2\r
+ * and PCLK1 prescalers.\r
+ * @note This function should be used only after reset.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+static void SetSysClockToHSE(void)\r
+{\r
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;\r
+ \r
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ \r
+ /* Enable HSE */ \r
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);\r
+ \r
+ /* Wait till HSE is ready and if Time out is reached exit */\r
+ do\r
+ {\r
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;\r
+ StartUpCounter++; \r
+ } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));\r
+\r
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)\r
+ {\r
+ HSEStatus = (uint32_t)0x01;\r
+ }\r
+ else\r
+ {\r
+ HSEStatus = (uint32_t)0x00;\r
+ } \r
+\r
+ if (HSEStatus == (uint32_t)0x01)\r
+ {\r
+ /* Enable Prefetch Buffer */\r
+ FLASH->ACR |= FLASH_ACR_PRFTBE;\r
+\r
+ /* Flash 0 wait state */\r
+ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);\r
+\r
+#ifndef STM32F10X_CL\r
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;\r
+#else\r
+ if (HSE_Value <= 24000000)\r
+ {\r
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;\r
+ }\r
+ else\r
+ {\r
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;\r
+ }\r
+#endif /* STM32F10X_CL */\r
+ \r
+ /* HCLK = SYSCLK */\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;\r
+ \r
+ /* PCLK2 = HCLK */\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;\r
+ \r
+ /* PCLK1 = HCLK */\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;\r
+ \r
+ /* Select HSE as system clock source */\r
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE; \r
+\r
+ /* Wait till HSE is used as system clock source */\r
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)\r
+ {\r
+ }\r
+ }\r
+ else\r
+ { /* If HSE fails to start-up, the application will have wrong clock \r
+ configuration. User can add here some code to deal with this error */ \r
+\r
+ /* Go to infinite loop */\r
+ while (1)\r
+ {\r
+ }\r
+ } \r
+}\r
+#elif defined SYSCLK_FREQ_24MHz\r
+/**\r
+ * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 \r
+ * and PCLK1 prescalers.\r
+ * @note This function should be used only after reset.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+static void SetSysClockTo24(void)\r
+{\r
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;\r
+ \r
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ \r
+ /* Enable HSE */ \r
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);\r
+ \r
+ /* Wait till HSE is ready and if Time out is reached exit */\r
+ do\r
+ {\r
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;\r
+ StartUpCounter++; \r
+ } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));\r
+\r
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)\r
+ {\r
+ HSEStatus = (uint32_t)0x01;\r
+ }\r
+ else\r
+ {\r
+ HSEStatus = (uint32_t)0x00;\r
+ } \r
+\r
+ if (HSEStatus == (uint32_t)0x01)\r
+ {\r
+ /* Enable Prefetch Buffer */\r
+ FLASH->ACR |= FLASH_ACR_PRFTBE;\r
+\r
+ /* Flash 0 wait state */\r
+ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);\r
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; \r
+ \r
+ /* HCLK = SYSCLK */\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;\r
+ \r
+ /* PCLK2 = HCLK */\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;\r
+ \r
+ /* PCLK1 = HCLK */\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;\r
+ \r
+#ifdef STM32F10X_CL\r
+ /* Configure PLLs ------------------------------------------------------*/\r
+ /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ \r
+ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);\r
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | \r
+ RCC_CFGR_PLLMULL6); \r
+\r
+ /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */\r
+ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ \r
+ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |\r
+ RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);\r
+ RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |\r
+ RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);\r
+ \r
+ /* Enable PLL2 */\r
+ RCC->CR |= RCC_CR_PLL2ON;\r
+ /* Wait till PLL2 is ready */\r
+ while((RCC->CR & RCC_CR_PLL2RDY) == 0)\r
+ {\r
+ } \r
+#else \r
+ /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */\r
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));\r
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);\r
+#endif /* STM32F10X_CL */\r
+\r
+ /* Enable PLL */\r
+ RCC->CR |= RCC_CR_PLLON;\r
+\r
+ /* Wait till PLL is ready */\r
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)\r
+ {\r
+ }\r
+\r
+ /* Select PLL as system clock source */\r
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; \r
+\r
+ /* Wait till PLL is used as system clock source */\r
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)\r
+ {\r
+ }\r
+ }\r
+ else\r
+ { /* If HSE fails to start-up, the application will have wrong clock \r
+ configuration. User can add here some code to deal with this error */ \r
+\r
+ /* Go to infinite loop */\r
+ while (1)\r
+ {\r
+ }\r
+ } \r
+}\r
+#elif defined SYSCLK_FREQ_36MHz\r
+/**\r
+ * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2 \r
+ * and PCLK1 prescalers. \r
+ * @note This function should be used only after reset.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+static void SetSysClockTo36(void)\r
+{\r
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;\r
+ \r
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ \r
+ /* Enable HSE */ \r
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);\r
+ \r
+ /* Wait till HSE is ready and if Time out is reached exit */\r
+ do\r
+ {\r
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;\r
+ StartUpCounter++; \r
+ } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));\r
+\r
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)\r
+ {\r
+ HSEStatus = (uint32_t)0x01;\r
+ }\r
+ else\r
+ {\r
+ HSEStatus = (uint32_t)0x00;\r
+ } \r
+\r
+ if (HSEStatus == (uint32_t)0x01)\r
+ {\r
+ /* Enable Prefetch Buffer */\r
+ FLASH->ACR |= FLASH_ACR_PRFTBE;\r
+\r
+ /* Flash 1 wait state */\r
+ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);\r
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; \r
+ \r
+ /* HCLK = SYSCLK */\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;\r
+ \r
+ /* PCLK2 = HCLK */\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;\r
+ \r
+ /* PCLK1 = HCLK */\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;\r
+ \r
+#ifdef STM32F10X_CL\r
+ /* Configure PLLs ------------------------------------------------------*/\r
+ \r
+ /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ \r
+ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);\r
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | \r
+ RCC_CFGR_PLLMULL9); \r
+\r
+ /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */\r
+ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */\r
+ \r
+ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |\r
+ RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);\r
+ RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |\r
+ RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);\r
+ \r
+ /* Enable PLL2 */\r
+ RCC->CR |= RCC_CR_PLL2ON;\r
+ /* Wait till PLL2 is ready */\r
+ while((RCC->CR & RCC_CR_PLL2RDY) == 0)\r
+ {\r
+ }\r
+ \r
+#else \r
+ /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */\r
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));\r
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);\r
+#endif /* STM32F10X_CL */\r
+\r
+ /* Enable PLL */\r
+ RCC->CR |= RCC_CR_PLLON;\r
+\r
+ /* Wait till PLL is ready */\r
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)\r
+ {\r
+ }\r
+\r
+ /* Select PLL as system clock source */\r
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; \r
+\r
+ /* Wait till PLL is used as system clock source */\r
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)\r
+ {\r
+ }\r
+ }\r
+ else\r
+ { /* If HSE fails to start-up, the application will have wrong clock \r
+ configuration. User can add here some code to deal with this error */ \r
+\r
+ /* Go to infinite loop */\r
+ while (1)\r
+ {\r
+ }\r
+ } \r
+}\r
+#elif defined SYSCLK_FREQ_48MHz\r
+/**\r
+ * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 \r
+ * and PCLK1 prescalers. \r
+ * @note This function should be used only after reset.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+static void SetSysClockTo48(void)\r
+{\r
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;\r
+ \r
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ \r
+ /* Enable HSE */ \r
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);\r
+ \r
+ /* Wait till HSE is ready and if Time out is reached exit */\r
+ do\r
+ {\r
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;\r
+ StartUpCounter++; \r
+ } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));\r
+\r
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)\r
+ {\r
+ HSEStatus = (uint32_t)0x01;\r
+ }\r
+ else\r
+ {\r
+ HSEStatus = (uint32_t)0x00;\r
+ } \r
+\r
+ if (HSEStatus == (uint32_t)0x01)\r
+ {\r
+ /* Enable Prefetch Buffer */\r
+ FLASH->ACR |= FLASH_ACR_PRFTBE;\r
+\r
+ /* Flash 1 wait state */\r
+ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);\r
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; \r
+ \r
+ /* HCLK = SYSCLK */\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;\r
+ \r
+ /* PCLK2 = HCLK */\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;\r
+ \r
+ /* PCLK1 = HCLK */\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;\r
+ \r
+#ifdef STM32F10X_CL\r
+ /* Configure PLLs ------------------------------------------------------*/\r
+ /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */\r
+ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */\r
+ \r
+ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |\r
+ RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);\r
+ RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |\r
+ RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);\r
+ \r
+ /* Enable PLL2 */\r
+ RCC->CR |= RCC_CR_PLL2ON;\r
+ /* Wait till PLL2 is ready */\r
+ while((RCC->CR & RCC_CR_PLL2RDY) == 0)\r
+ {\r
+ }\r
+ \r
+ \r
+ /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ \r
+ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);\r
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | \r
+ RCC_CFGR_PLLMULL6); \r
+#else \r
+ /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */\r
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));\r
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);\r
+#endif /* STM32F10X_CL */\r
+\r
+ /* Enable PLL */\r
+ RCC->CR |= RCC_CR_PLLON;\r
+\r
+ /* Wait till PLL is ready */\r
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)\r
+ {\r
+ }\r
+\r
+ /* Select PLL as system clock source */\r
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; \r
+\r
+ /* Wait till PLL is used as system clock source */\r
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)\r
+ {\r
+ }\r
+ }\r
+ else\r
+ { /* If HSE fails to start-up, the application will have wrong clock \r
+ configuration. User can add here some code to deal with this error */ \r
+\r
+ /* Go to infinite loop */\r
+ while (1)\r
+ {\r
+ }\r
+ } \r
+}\r
+\r
+#elif defined SYSCLK_FREQ_56MHz\r
+/**\r
+ * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 \r
+ * and PCLK1 prescalers. \r
+ * @note This function should be used only after reset.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+static void SetSysClockTo56(void)\r
+{\r
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;\r
+ \r
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ \r
+ /* Enable HSE */ \r
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);\r
+ \r
+ /* Wait till HSE is ready and if Time out is reached exit */\r
+ do\r
+ {\r
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;\r
+ StartUpCounter++; \r
+ } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));\r
+\r
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)\r
+ {\r
+ HSEStatus = (uint32_t)0x01;\r
+ }\r
+ else\r
+ {\r
+ HSEStatus = (uint32_t)0x00;\r
+ } \r
+\r
+ if (HSEStatus == (uint32_t)0x01)\r
+ {\r
+ /* Enable Prefetch Buffer */\r
+ FLASH->ACR |= FLASH_ACR_PRFTBE;\r
+\r
+ /* Flash 1 wait state */\r
+ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);\r
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; \r
+ \r
+ /* HCLK = SYSCLK */\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;\r
+ \r
+ /* PCLK2 = HCLK */\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;\r
+ \r
+ /* PCLK1 = HCLK */\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;\r
+\r
+#ifdef STM32F10X_CL\r
+ /* Configure PLLs ------------------------------------------------------*/\r
+ /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */\r
+ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */\r
+ \r
+ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |\r
+ RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);\r
+ RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |\r
+ RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);\r
+ \r
+ /* Enable PLL2 */\r
+ RCC->CR |= RCC_CR_PLL2ON;\r
+ /* Wait till PLL2 is ready */\r
+ while((RCC->CR & RCC_CR_PLL2RDY) == 0)\r
+ {\r
+ }\r
+ \r
+ \r
+ /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ \r
+ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);\r
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | \r
+ RCC_CFGR_PLLMULL7); \r
+#else \r
+ /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */\r
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));\r
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);\r
+\r
+#endif /* STM32F10X_CL */\r
+\r
+ /* Enable PLL */\r
+ RCC->CR |= RCC_CR_PLLON;\r
+\r
+ /* Wait till PLL is ready */\r
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)\r
+ {\r
+ }\r
+\r
+ /* Select PLL as system clock source */\r
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; \r
+\r
+ /* Wait till PLL is used as system clock source */\r
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)\r
+ {\r
+ }\r
+ }\r
+ else\r
+ { /* If HSE fails to start-up, the application will have wrong clock \r
+ configuration. User can add here some code to deal with this error */ \r
+\r
+ /* Go to infinite loop */\r
+ while (1)\r
+ {\r
+ }\r
+ } \r
+}\r
+\r
+#elif defined SYSCLK_FREQ_72MHz\r
+/**\r
+ * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 \r
+ * and PCLK1 prescalers. \r
+ * @note This function should be used only after reset.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+static void SetSysClockTo72(void)\r
+{\r
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;\r
+ \r
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ \r
+ /* Enable HSE */ \r
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);\r
+ \r
+ /* Wait till HSE is ready and if Time out is reached exit */\r
+ do\r
+ {\r
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;\r
+ StartUpCounter++; \r
+ } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));\r
+\r
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)\r
+ {\r
+ HSEStatus = (uint32_t)0x01;\r
+ }\r
+ else\r
+ {\r
+ HSEStatus = (uint32_t)0x00;\r
+ } \r
+\r
+ if (HSEStatus == (uint32_t)0x01)\r
+ {\r
+ /* Enable Prefetch Buffer */\r
+ FLASH->ACR |= FLASH_ACR_PRFTBE;\r
+\r
+ /* Flash 2 wait state */\r
+ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);\r
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; \r
+\r
+ \r
+ /* HCLK = SYSCLK */\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;\r
+ \r
+ /* PCLK2 = HCLK */\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;\r
+ \r
+ /* PCLK1 = HCLK */\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;\r
+\r
+#ifdef STM32F10X_CL\r
+ /* Configure PLLs ------------------------------------------------------*/\r
+ /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */\r
+ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */\r
+ \r
+ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |\r
+ RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);\r
+ RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |\r
+ RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);\r
+ \r
+ /* Enable PLL2 */\r
+ RCC->CR |= RCC_CR_PLL2ON;\r
+ /* Wait till PLL2 is ready */\r
+ while((RCC->CR & RCC_CR_PLL2RDY) == 0)\r
+ {\r
+ }\r
+ \r
+ \r
+ /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ \r
+ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);\r
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | \r
+ RCC_CFGR_PLLMULL9); \r
+#else \r
+ /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */\r
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |\r
+ RCC_CFGR_PLLMULL));\r
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);\r
+#endif /* STM32F10X_CL */\r
+\r
+ /* Enable PLL */\r
+ RCC->CR |= RCC_CR_PLLON;\r
+\r
+ /* Wait till PLL is ready */\r
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)\r
+ {\r
+ }\r
+ \r
+ /* Select PLL as system clock source */\r
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; \r
+\r
+ /* Wait till PLL is used as system clock source */\r
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)\r
+ {\r
+ }\r
+ }\r
+ else\r
+ { /* If HSE fails to start-up, the application will have wrong clock \r
+ configuration. User can add here some code to deal with this error */ \r
+\r
+ /* Go to infinite loop */\r
+ while (1)\r
+ {\r
+ }\r
+ }\r
+}\r
+#endif\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/**\r
+ ******************************************************************************\r
+ * @file system_stm32f10x.h\r
+ * @author MCD Application Team\r
+ * @version V3.1.0\r
+ * @date 06/19/2009\r
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.\r
+ ****************************************************************************** \r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>\r
+ ******************************************************************************\r
+ */\r
+\r
+/** @addtogroup CMSIS\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup stm32f10x_system\r
+ * @{\r
+ */ \r
+ \r
+/**\r
+ * @brief Define to prevent recursive inclusion\r
+ */\r
+#ifndef __SYSTEM_STM32F10X_H\r
+#define __SYSTEM_STM32F10X_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif \r
+\r
+/** @addtogroup STM32F10x_System_Includes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @addtogroup STM32F10x_System_Exported_types\r
+ * @{\r
+ */\r
+\r
+extern const uint32_t SystemFrequency; /*!< System Clock Frequency (Core Clock) */\r
+extern const uint32_t SystemFrequency_SysClk; /*!< System clock */\r
+extern const uint32_t SystemFrequency_AHBClk; /*!< AHB System bus speed */\r
+extern const uint32_t SystemFrequency_APB1Clk; /*!< APB Peripheral Bus 1 (low) speed */\r
+extern const uint32_t SystemFrequency_APB2Clk; /*!< APB Peripheral Bus 2 (high) speed */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F10x_System_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F10x_System_Exported_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F10x_System_Exported_Functions\r
+ * @{\r
+ */\r
+ \r
+extern void SystemInit(void);\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__SYSTEM_STM32F10X_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+\r
+\r
+\r
+# prefered version\r
+CC_VERSION=4.1.2\r
+# ARMv7, Thumb-2, little endian, soft-float. \r
+cflags-y += -mthumb -mcpu=cortex-m3 -mfix-cortex-m3-ldrd\r
+cflags-y += -g\r
+# experimental\r
+#cflags-y += -mno-common\r
+\r
+#cflags-y += -mno-common\r
+\r
+lib-y += -lgcc -lc\r
+ASFLAGS += -mcpu=cortex-m3 -mthumb\r
+\r
+\r
--- /dev/null
+/*\r
+Default linker script for STM32F10x_512K_64K\r
+Copyright RAISONANCE S.A.S. 2008\r
+*/\r
+\r
+/* include the common STM32F10x sub-script */\r
+\r
+/* Common part of the linker scripts for STM32 devices*/\r
+\r
+\r
+/* default stack sizes. \r
+\r
+These are used by the startup in order to allocate stacks for the different modes.\r
+*/\r
+\r
+__Stack_Size = 1024 ;\r
+\r
+PROVIDE ( _Stack_Size = __Stack_Size ) ;\r
+\r
+__Stack_Init = _estack - __Stack_Size ;\r
+\r
+/*"PROVIDE" allows to easily override these values from an object file or the commmand line.*/\r
+PROVIDE ( _Stack_Init = __Stack_Init ) ;\r
+\r
+/*\r
+There will be a link error if there is not this amount of RAM free at the end.\r
+*/\r
+_Minimum_Stack_Size = 0x100 ;\r
+\r
+\r
+/* include the memory spaces definitions sub-script */\r
+/*\r
+Linker subscript for STM32F10x definitions with 512K Flash and 1024K RAM */\r
+\r
+/* Memory Spaces Definitions */\r
+\r
+MEMORY\r
+{\r
+ RAM (xrw) : ORIGIN = 0x68000000, LENGTH = 64K\r
+ FLASH (rx) : ORIGIN = 0x0000000, LENGTH = 512K\r
+ FLASHB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0\r
+ EXTMEMB0 (rx) : ORIGIN = 0x00000000, LENGTH = 0\r
+ EXTMEMB1 (rx) : ORIGIN = 0x00000000, LENGTH = 0\r
+ EXTMEMB2 (rx) : ORIGIN = 0x00000000, LENGTH = 0\r
+ EXTMEMB3 (rx) : ORIGIN = 0x00000000, LENGTH = 0\r
+}\r
+\r
+/* higher address of the user mode stack */\r
+_estack = 0x68100000;\r
+\r
+\r
+\r
+/* include the sections management sub-script for FLASH mode */\r
+\r
+/* Sections Definitions */\r
+\r
+SECTIONS\r
+{\r
+ /* for Cortex devices, the beginning of the startup code is stored in the .isr_vector section, which goes to FLASH */\r
+ .isr_vector :\r
+ {\r
+ . = ALIGN(4);\r
+ KEEP(*(.isr_vector)) /* Startup code */\r
+ . = ALIGN(4);\r
+ } >FLASH\r
+ \r
+ /* for some STRx devices, the beginning of the startup code is stored in the .flashtext section, which goes to FLASH */\r
+ .flashtext :\r
+ {\r
+ . = ALIGN(4);\r
+ *(.flashtext) /* Startup code */\r
+ . = ALIGN(4);\r
+ } >FLASH\r
+ \r
+ \r
+ /* the program code is stored in the .text section, which goes to Flash */\r
+ .text :\r
+ {\r
+ . = ALIGN(4);\r
+ \r
+ *(.text) /* remaining code */\r
+ *(.text.*) /* remaining code */ \r
+ *(.rodata) /* read-only data (constants) */\r
+ *(.rodata*)\r
+ *(.glue_7)\r
+ *(.glue_7t)\r
+ \r
+ . = ALIGN(4);\r
+ _etext = .;\r
+ /* This is used by the startup in order to initialize the .data secion */\r
+/*\r
+ _sidata = _etext;\r
+*/ \r
+ } >FLASH\r
+\r
+ /* Special sucky exception section */\r
+ .ARM.exidx : { \r
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r
+ _sidata = .; \r
+ } >FLASH\r
+ __exidx_start = .;\r
+\r
+ /* This is the initialized data section\r
+ The program executes knowing that the data is in the RAM\r
+ but the loader puts the initial values in the FLASH (inidata).\r
+ It is one task of the startup to copy the initial values from FLASH to RAM. */\r
+ .data : AT ( _sidata )\r
+ {\r
+ . = ALIGN(4);\r
+ /* This is used by the startup in order to initialize the .data secion */\r
+ _sdata = . ;\r
+ \r
+ *(.data)\r
+ *(.data.*)\r
+ *(.ARM.extab* .gnu.linkonce.armextab.*) \r
+ . = ALIGN(4);\r
+ /* This is used by the startup in order to initialize the .data secion */\r
+ _edata = . ;\r
+ } >RAM\r
+ \r
+ \r
+\r
+ /* This is the uninitialized data section */\r
+ .bss :\r
+ {\r
+ . = ALIGN(4);\r
+ /* This is used by the startup in order to initialize the .bss secion */\r
+ _sbss = .;\r
+ \r
+ *(.bss)\r
+ *(.t32_outport)\r
+ *(COMMON)\r
+ \r
+ . = ALIGN(4);\r
+ /* This is used by the startup in order to initialize the .bss secion */\r
+ _ebss = . ;\r
+ } >RAM\r
+ \r
+ PROVIDE ( end = _ebss );\r
+ PROVIDE ( _end = _ebss );\r
+ \r
+ /* This is the user stack section \r
+ This is just to check that there is enough RAM left for the User mode stack\r
+ It should generate an error if it's full.\r
+ */\r
+ ._usrstack :\r
+ {\r
+ . = ALIGN(4);\r
+ _susrstack = . ;\r
+ \r
+ . = . + _Minimum_Stack_Size ;\r
+ \r
+ . = ALIGN(4);\r
+ _eusrstack = . ;\r
+ } >RAM\r
+ \r
+\r
+ \r
+ /* this is the FLASH Bank1 */\r
+ /* the C or assembly source must explicitly place the code or data there\r
+ using the "section" attribute */\r
+ .b1text :\r
+ {\r
+ *(.b1text) /* remaining code */\r
+ *(.b1rodata) /* read-only data (constants) */\r
+ *(.b1rodata*)\r
+ } >FLASHB1\r
+ \r
+ /* this is the EXTMEM */\r
+ /* the C or assembly source must explicitly place the code or data there\r
+ using the "section" attribute */\r
+ \r
+ /* EXTMEM Bank0 */\r
+ .eb0text :\r
+ {\r
+ *(.eb0text) /* remaining code */\r
+ *(.eb0rodata) /* read-only data (constants) */\r
+ *(.eb0rodata*)\r
+ } >EXTMEMB0\r
+ \r
+ /* EXTMEM Bank1 */\r
+ .eb1text :\r
+ {\r
+ *(.eb1text) /* remaining code */\r
+ *(.eb1rodata) /* read-only data (constants) */\r
+ *(.eb1rodata*)\r
+ } >EXTMEMB1\r
+ \r
+ /* EXTMEM Bank2 */\r
+ .eb2text :\r
+ {\r
+ *(.eb2text) /* remaining code */\r
+ *(.eb2rodata) /* read-only data (constants) */\r
+ *(.eb2rodata*)\r
+ } >EXTMEMB2\r
+ \r
+ /* EXTMEM Bank0 */\r
+ .eb3text :\r
+ {\r
+ *(.eb3text) /* remaining code */\r
+ *(.eb3rodata) /* read-only data (constants) */\r
+ *(.eb3rodata*)\r
+ } >EXTMEMB3\r
+ \r
+ \r
+ \r
+ /* after that it's only debugging information. */\r
+ \r
+ /* remove the debugging information from the standard libraries */\r
+\r
+ /DISCARD/ :\r
+ {\r
+ libc.a ( * )\r
+ libm.a ( * )\r
+ libgcc.a ( * )\r
+ }\r
+ \r
+ /* Stabs debugging sections. */\r
+ .stab 0 : { *(.stab) }\r
+ .stabstr 0 : { *(.stabstr) }\r
+ .stab.excl 0 : { *(.stab.excl) }\r
+ .stab.exclstr 0 : { *(.stab.exclstr) }\r
+ .stab.index 0 : { *(.stab.index) }\r
+ .stab.indexstr 0 : { *(.stab.indexstr) }\r
+ .comment 0 : { *(.comment) }\r
+ /* DWARF debug sections.\r
+ Symbols in the DWARF debugging sections are relative to the beginning\r
+ of the section so we begin them at 0. */\r
+ /* DWARF 1 */\r
+ .debug 0 : { *(.debug) }\r
+ .line 0 : { *(.line) }\r
+ /* GNU DWARF 1 extensions */\r
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }\r
+ .debug_sfnames 0 : { *(.debug_sfnames) }\r
+ /* DWARF 1.1 and DWARF 2 */\r
+ .debug_aranges 0 : { *(.debug_aranges) }\r
+ .debug_pubnames 0 : { *(.debug_pubnames) }\r
+ /* DWARF 2 */\r
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }\r
+ .debug_abbrev 0 : { *(.debug_abbrev) }\r
+ .debug_line 0 : { *(.debug_line) }\r
+ .debug_frame 0 : { *(.debug_frame) }\r
+ .debug_str 0 : { *(.debug_str) }\r
+ .debug_loc 0 : { *(.debug_loc) }\r
+ .debug_macinfo 0 : { *(.debug_macinfo) }\r
+ /* SGI/MIPS DWARF 2 extensions */\r
+ .debug_weaknames 0 : { *(.debug_weaknames) }\r
+ .debug_funcnames 0 : { *(.debug_funcnames) }\r
+ .debug_typenames 0 : { *(.debug_typenames) }\r
+ .debug_varnames 0 : { *(.debug_varnames) }\r
+}\r
--- /dev/null
+#include "asm_ppc.h"\r
+\r
+.section ".rcw","ax"\r
+.global _resetconfiguration\r
+_resetconfiguration:\r
+ .byte 0x00 #no watchdog\r
+ .byte 0x5A #Boot identifier\r
+ .byte 0x00\r
+ .byte 0x00\r
+ .long _start\r
+\r
+\r
+ .text\r
+ .align 4\r
+\r
+ .globl _start\r
+ .type _start,@function\r
+\r
+ // Good information about the E500 is freescale doc: E500ABIUG.pdf\r
+_start:\r
+ // Set up the reserved registers in EABI: r1,r2 and r13\r
+\r
+ // r1, stack pointer\r
+ lis r1,__SP_INIT@h\r
+ ori r1,r1,__SP_INIT@l\r
+\r
+ // r13, base of .sdata\r
+ lis r13,_SDA_BASE_@h\r
+ ori r13,r13,_SDA_BASE_@l\r
+\r
+ // r2, base of .sdata2 and .sbss2\r
+ lis r2,_SDA2_BASE_@h\r
+ ori r2,r2,_SDA2_BASE_@l\r
+\r
+ // make space for initial backchain..\r
+ subi r1,r1,16\r
+\r
+ // Copy initialized data from ROM to RAM\r
+ lis r3,__DATA_ROM@h\r
+ ori r3,r3,__DATA_ROM@l\r
+ lis r4,__DATA_RAM@h\r
+ ori r4,r4,__DATA_RAM@l\r
+ lis r5,__DATA_END@h\r
+ ori r5,r5,__DATA_END@l\r
+\r
+ cmplw r3,r4\r
+ beq skip_data\r
+ cmplw r4,r5\r
+ beq skip_data\r
+ subi r3,r3,1\r
+ subi r4,r4,1\r
+1:\r
+ lbzu r6,1(r3)\r
+ stbu r6,1(r4)\r
+ cmplw r4,r5\r
+ bne+ 1b\r
+skip_data:\r
+\r
+ # Clear uninitialized data( holds both bss and sbss )\r
+ lis r3,__BSS_START@h\r
+ ori r3,r3,__BSS_START@l\r
+ lis r4,__BSS_END@h\r
+ ori r4,r4,__BSS_END@l\r
+ cmplw r3,r4\r
+ beq 3f\r
+ li r0,0\r
+ subi r3,r3,1\r
+2:\r
+ stbu r0,1(r3)\r
+ cmplw r3,r4\r
+ bne+ 2b\r
+3:\r
+\r
+ # Call main() with argc set to 1 and argv ignored\r
+ li r3,1\r
+ bl main\r
+\r
+ # Call exit() with the return value from main() as argument\r
+ b exit\r
+\r
+ .globl _exit\r
+_exit:\r
+ b _exit\r
+\r
+\r
+ .end\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*************************************************************************\r
+ * (c) Copyright Motorola 2005, All Rights Reserved *\r
+ *************************************************************************\r
+ * *\r
+ * Motorola reserves the right to make changes without further notice *\r
+ * to any product herein to improve reliability, function or design. *\r
+ * Motorola does not assume any liability arising out of the *\r
+ * application or use of any product, circuit, or software described *\r
+ * herein; neither does it convey any license under its patent rights *\r
+ * nor the rights of others. *\r
+ * *\r
+ * Motorola products are not designed, intended, or authorized for *\r
+ * use as components in systems intended for surgical implant into *\r
+ * the body, or other applications intended to support life, or for *\r
+ * any other application in which the failure of the Motorola product *\r
+ * could create a situation where personal injury or death may occur. *\r
+ * *\r
+ * Should Buyer purchase or use Motorola products for any such *\r
+ * unintended or unauthorized application, Buyer shall indemnify and *\r
+ * hold Motorola and its officers, employees, subsidiaries, *\r
+ * affiliates, and distributors harmless against all claims costs, *\r
+ * damages, and expenses, and reasonable attorney fees arising out *\r
+ * of, directly or indirectly, any claim of personal injury or death *\r
+ * associated with such unintended or unauthorized use, even if such *\r
+ * claim alleges that Motorola was negligent regarding the design *\r
+ * or manufacture of the part. *\r
+ * *\r
+ * Motorola and the Motorola logo* are registered trademarks of *\r
+ * Motorola Ltd. *\r
+ * *\r
+ *************************************************************************\r
+\r
+ *************************************************************************\r
+ * *\r
+ * Standard Software H7F Driver for MPC55xx *\r
+ * *\r
+ * FILE NAME : ssd_h7f.h *\r
+ * DATE : June 23, 2005 *\r
+ * *\r
+ * AUTHOR : Flash Team, *\r
+ * Global Software Group, China, Motorola Inc. *\r
+ * E-mail : flash@sc.mcel.mot.com *\r
+ * *\r
+ *************************************************************************/\r
+\r
+/******************************* CHANGES *********************************\r
+ 3.20 2005.06.23 Cloud Li Initial Version\r
+ *************************************************************************/\r
+\r
+#ifndef _SSD_H7F_H_\r
+#define _SSD_H7F_H_\r
+\r
+/*************************************************************************/\r
+/* Offsets of H7F Control Registers and PFBIU Control Registers */\r
+/*************************************************************************/\r
+#define H7F_MCR 0x0000 /* Module Configuration Register */\r
+#define H7F_LML 0x0004 /* Low/Mid Address Space Block Locking Register */\r
+#define H7F_HBL 0x0008 /* High Address Space Block Locking Register */\r
+#define H7F_SLL 0x000C /* Secondary Low/Mid Address Space Block Locking Register */\r
+#define H7F_LMS 0x0010 /* Low/Mid Address Space Block Select Register */\r
+#define H7F_HBS 0x0014 /* High Address Space Block Select Register */\r
+#define H7F_ADR 0x0018 /* Address Register */\r
+#define PFB_CR 0x001C /* PFBIU Configuration Register */\r
+\r
+/*************************************************************************/\r
+/* H7F Module Control Registers Field Definition */\r
+/*************************************************************************/\r
+/* Module Configuration Register */\r
+#define H7F_MCR_SFS 0x10000000 /* Special Flash Selector */\r
+#define H7F_MCR_SIZE 0x0F000000 /* Array Space Size */\r
+#define H7F_MCR_LAS 0x00700000 /* Low Address Space Size */\r
+#define H7F_MCR_MAS 0x00010000 /* Mid Address Space Size */\r
+#define H7F_MCR_EER 0x00008000 /* ECC Event Error */\r
+#define H7F_MCR_RWE 0x00004000 /* Read While Write Event Error */\r
+#define H7F_MCR_BBEPE 0x00002000 /* Boot Block External Program Erase Status */\r
+#define H7F_MCR_EPE 0x00001000 /* External Program Erase Status */\r
+#define H7F_MCR_PEAS 0x00000800 /* Program/Erase Access Space */\r
+#define H7F_MCR_DONE 0x00000400 /* State Machine Status */\r
+#define H7F_MCR_PEG 0x00000200 /* Program/Erase Good */\r
+#define H7F_MCR_PRD 0x00000080 /* Pipelined Reads Disabled */\r
+#define H7F_MCR_STOP 0x00000040 /* Stop Mode Enabled */\r
+#define H7F_MCR_PGM 0x00000010 /* Program */\r
+#define H7F_MCR_PSUS 0x00000008 /* Program Suspend */\r
+#define H7F_MCR_ERS 0x00000004 /* Erase */\r
+#define H7F_MCR_ESUS 0x00000002 /* Erase Suspend */\r
+#define H7F_MCR_EHV 0x00000001 /* Enable High Voltage */\r
+\r
+\r
+/* Low/Mid Address Space Block Locking Register */\r
+#define H7F_LML_LME 0x80000000 /* Low and Mid Address Lock Enable */\r
+#define H7F_LML_SLOCK 0x00100000 /* Shadow Lock */\r
+#define H7F_LML_MLOCK 0x000F0000 /* Mid Address Block Lock */\r
+#define H7F_LML_LLOCK 0x0000FFFF /* Low Address Block Lock */\r
+\r
+/* EEPROM High Address Space Block Locking Register */\r
+#define H7F_HBL_HBE 0x80000000 /* High Address Lock Enable */\r
+#define H7F_HBL_HBLOCK 0x0FFFFFFF /* High Address Space Block Lock */\r
+\r
+/* Secondary Low/Mid Address Space Block Locking Register */\r
+#define H7F_SLL_SLE 0x80000000 /* Secondary Low and Mid Address Lock Enable */\r
+#define H7F_SLL_SSLOCK 0x00100000 /* Secondary Shadow Lock */\r
+#define H7F_SLL_SMLOCK 0x000F0000 /* Secondary Mid Address Block Lock */\r
+#define H7F_SLL_SLLOCK 0x0000FFFF /* Secondary Low Address Block Lock */\r
+\r
+/* Low/Mid Address Space Block Select Register */\r
+#define H7F_LMS_MSEL 0x000F0000 /* Mid Address Space Block Select */\r
+#define H7F_LMS_LSEL 0x0000FFFF /* Low Address Space Block Select */\r
+\r
+/* High Address Space Block Select Register */\r
+#define H7F_HBS_HBSEL 0x0FFFFFFF /* High Address Space Block Select */\r
+\r
+/* Platform Flash BIU Configuration Register */\r
+#define PFB_CR_APC 0x0000E000 /* Address Pipelining Control */\r
+#define PFB_CR_WWSC 0x00001800 /* Write Wait State Control */\r
+#define PFB_CR_RWSC 0x00000700 /* Read Wait State Control */\r
+#define PFB_CR_BFEN 0x00000001 /* PFBIU Line Read Buffers Enable */\r
+\r
+/* MCU ID Register */\r
+#define SIU_MIDR 0xC3F90004\r
+\r
+/* Macros for Accessing the Registers */\r
+#define H7F_REG_BIT_SET(address, mask) (*(VUINT32*)(address) |= (mask))\r
+#define H7F_REG_BIT_CLEAR(address, mask) (*(VUINT32*)(address) &= ~(mask))\r
+#define H7F_REG_BIT_TEST(address, mask) (*(VUINT32*)(address) & (mask))\r
+#define H7F_REG_WRITE(address, value) (*(VUINT32*)(address) = (value))\r
+#define H7F_REG_READ(address) ((UINT32)(*(VUINT32*)(address)))\r
+\r
+/* Set/Clear H7FMCR bits without affecting MCR-EER and MCR-RWE */\r
+#define H7FMCR_BIT_SET(MCRAddress, mask) \\r
+ H7F_REG_WRITE(MCRAddress, ((mask | H7F_REG_READ(MCRAddress)) & (~(H7F_MCR_EER | H7F_MCR_RWE))))\r
+\r
+#define H7FMCR_BIT_CLEAR(MCRAddress, mask) \\r
+ H7F_REG_WRITE(MCRAddress, (((~mask) & H7F_REG_READ(MCRAddress)) & (~(H7F_MCR_EER | H7F_MCR_RWE))))\r
+\r
+/*************************************************************************/\r
+/* Return Codes for SSD functions */\r
+/*************************************************************************/\r
+\r
+#define H7F_OK 0x00000000\r
+#define H7F_INFO_RWE 0x00000001 /* There is read-while-write error for previous reads */\r
+#define H7F_INFO_EER 0x00000002 /* There is ECC error for previous reads */\r
+#define H7F_INFO_EPE 0x00000004 /* The program/erase for all blocks including shadow row and excluding the boot block is disabled */\r
+#define H7F_INFO_BBEPE 0x00000008 /* The program/erase for boot block is disabled */\r
+#define H7F_ERROR_PARTID 0x00000010 /* The SSD cannot operate on this part */\r
+#define H7F_ERROR_STOP 0x00000020 /* The flash is in STOP mode and no operation is allowed */\r
+#define H7F_ERROR_ALIGNMENT 0x00000100 /* Alignment error */\r
+#define H7F_ERROR_RANGE 0x00000200 /* Address range error */\r
+#define H7F_ERROR_BUSY 0x00000300 /* New program/erase cannot be preformed while previous high voltage operation in progress */\r
+#define H7F_ERROR_PGOOD 0x00000400 /* The program operation is unsuccessful */\r
+#define H7F_ERROR_EGOOD 0x00000500 /* The erase operation is unsuccessful */\r
+#define H7F_ERROR_NOT_BLANK 0x00000600 /* There is non-blank location in the checked flash memory */\r
+#define H7F_ERROR_VERIFY 0x00000700 /* There is a mismatch between the source data and content in the checked flash memory */\r
+#define H7F_ERROR_LOCK_INDICATOR 0x00000800 /* Invalid block lock indicator */\r
+#define H7F_ERROR_RWE 0x00000900 /* Read while write error on the previous reads */\r
+#define H7F_ERROR_PASSWORD 0x00000B00 /* The password provided cannot unlock the block lock register for register writes */\r
+\r
+\r
+/*************************************************************************/\r
+/* Other Macros for SSD functions */\r
+/*************************************************************************/\r
+\r
+#define H7F_WORD_SIZE 4 /* size of a word in byte */\r
+#define H7F_DWORD_SIZE 8 /* size of a double word in byte */\r
+\r
+/* Indication for setting/getting block lock state */\r
+#define LOCK_SHADOW_PRIMARY 0 /* Primary Block lock protection of shadow address space */\r
+#define LOCK_SHADOW_SECONDARY 1 /* Secondary Block lock protection of shadow address space */\r
+#define LOCK_LOW_PRIMARY 2 /* Primary block lock protection of low address space */\r
+#define LOCK_LOW_SECONDARY 3 /* Secondary block lock protection of low address space */\r
+#define LOCK_MID_PRIMARY 4 /* Primary block lock protection of mid address space */\r
+#define LOCK_MID_SECONDARY 5 /* Secondary block lock protection of mid address space */\r
+#define LOCK_HIGH 6 /* Block lock protection of high address space */\r
+\r
+/* Macros for flash suspend operation */\r
+#define NO_OPERATION 0 /* no program/erase operation */\r
+#define PGM_WRITE 1 /* A program sequence in interlock write stage. */\r
+#define ERS_WRITE 2 /* An erase sequence in interlock write stage. */\r
+#define ERS_SUS_PGM_WRITE 3 /* A erase-suspend program sequence in interlock write stage. */\r
+#define PGM_SUS 4 /* The program operation is in suspend state */\r
+#define ERS_SUS 5 /* The erase operation on main array is in suspend state */\r
+#define SHADOW_ERS_SUS 6 /* The erase operation on shadow row is in suspend state. */\r
+#define ERS_SUS_PGM_SUS 7 /* The erase-suspended program operation is in suspend state */\r
+\r
+/* Macros for flash resume operation */\r
+#define RES_NOTHING 0 /* No suspended program/erase operation */\r
+#define RES_PGM 1 /* The program operation is resumed */\r
+#define RES_ERS 2 /* The erase operation is resumed */\r
+#define RES_ERS_PGM 3 /* The erase-suspended program operation is resumed */\r
+\r
+\r
+/*************************************************************************/\r
+/* SSD Configuration Structure */\r
+/*************************************************************************/\r
+typedef enum _h7f_page_size\r
+{\r
+ H7FA_PAGE_SIZE,\r
+ H7FB_PAGE_SIZE\r
+} H7F_PAGE_SIZE;\r
+\r
+typedef struct _ssd_config\r
+{\r
+ UINT32 h7fRegBase; /* H7F control register base */\r
+ UINT32 mainArrayBase; /* base of main array */\r
+ UINT32 mainArraySize; /* size of main array */\r
+ UINT32 shadowRowBase; /* base of shadow row */\r
+ UINT32 shadowRowSize; /* size of shadow row */\r
+ UINT32 lowBlockNum; /* block number in low address space */\r
+ UINT32 midBlockNum; /* block number in middle address space */\r
+ UINT32 highBlockNum; /* block number in high address space */\r
+ H7F_PAGE_SIZE pageSize; /* page size */\r
+ UINT32 BDMEnable; /* debug mode selection */\r
+} SSD_CONFIG, *PSSD_CONFIG;\r
+\r
+/*************************************************************************/\r
+/* NULL CallBack Function Pointer */\r
+/*************************************************************************/\r
+#define NULL_CALLBACK ((void *)0xFFFFFFFF)\r
+\r
+/*************************************************************************/\r
+/* Prototypes of SSD Functions */\r
+/*************************************************************************/\r
+\r
+UINT32 FlashInit ( PSSD_CONFIG pSSDConfig );\r
+\r
+UINT32 FlashErase ( PSSD_CONFIG pSSDConfig,\r
+ BOOL shadowFlag,\r
+ UINT32 lowEnabledBlocks,\r
+ UINT32 midEnabledBlocks,\r
+ UINT32 highEnabledBlocks,\r
+ void (*CallBack)(void)\r
+ );\r
+\r
+UINT32 BlankCheck ( PSSD_CONFIG pSSDConfig,\r
+ UINT32 dest,\r
+ UINT32 size,\r
+ UINT32 *pFailAddress,\r
+ UINT64 *pFailData,\r
+ void (*CallBack)(void)\r
+ );\r
+\r
+UINT32 FlashProgram ( PSSD_CONFIG pSSDConfig,\r
+ UINT32 dest,\r
+ UINT32 size,\r
+ UINT32 source,\r
+ void (*CallBack)(void)\r
+ );\r
+\r
+UINT32 ProgramVerify ( PSSD_CONFIG pSSDConfig,\r
+ UINT32 dest,\r
+ UINT32 size,\r
+ UINT32 source,\r
+ UINT32 *pFailAddress,\r
+ UINT64 *pFailData,\r
+ UINT64 *pFailSource,\r
+ void (*CallBack)(void)\r
+ );\r
+\r
+UINT32 CheckSum ( PSSD_CONFIG pSSDConfig,\r
+ UINT32 dest,\r
+ UINT32 size,\r
+ UINT32 *pSum,\r
+ void (*CallBack)(void)\r
+ );\r
+\r
+UINT32 FlashSuspend ( PSSD_CONFIG pSSDConfig,\r
+ UINT8 *suspendState,\r
+ BOOL *suspendFlag\r
+ );\r
+\r
+UINT32 FlashResume ( PSSD_CONFIG pSSDConfig,\r
+ UINT8 *resumeState\r
+ );\r
+\r
+UINT32 GetLock ( PSSD_CONFIG pSSDConfig,\r
+ UINT8 blkLockIndicator,\r
+ BOOL *blkLockEnabled,\r
+ UINT32 *blkLockState\r
+ );\r
+\r
+UINT32 SetLock ( PSSD_CONFIG pSSDConfig,\r
+ UINT8 blkLockIndicator,\r
+ UINT32 blkLockState,\r
+ UINT32 password\r
+ );\r
+\r
+UINT32 RWECheck ( PSSD_CONFIG pSSDConfig );\r
+\r
+UINT32 GetWaitState ( PSSD_CONFIG pSSDConfig,\r
+ UINT32 *pAPCValue,\r
+ UINT32 *pWWSCValue,\r
+ UINT32 *pRWSCValue\r
+ );\r
+\r
+UINT32 SetWaitState ( PSSD_CONFIG pSSDConfig,\r
+ UINT32 APCValue,\r
+ UINT32 WWSCValue,\r
+ UINT32 RWSCValue\r
+ );\r
+\r
+/*************************************************************************/\r
+/* SSD Function Pointer Types */\r
+/*************************************************************************/\r
+\r
+typedef UINT32 (*pFLASHINIT) ( PSSD_CONFIG pSSDConfig );\r
+\r
+typedef UINT32 (*pFLASHERASE) (\r
+ PSSD_CONFIG pSSDConfig,\r
+ BOOL shadowFlag,\r
+ UINT32 lowEnabledBlocks,\r
+ UINT32 midEnabledBlocks,\r
+ UINT32 highEnabledBlocks,\r
+ void (*CallBack)(void)\r
+ );\r
+\r
+typedef UINT32 (*pBLANKCHECK) (\r
+ PSSD_CONFIG pSSDConfig,\r
+ UINT32 dest,\r
+ UINT32 size,\r
+ UINT32 *pFailAddress,\r
+ UINT64 *pFailData,\r
+ void (*CallBack)(void)\r
+ );\r
+\r
+typedef UINT32 (*pFLASHPROGRAM) (\r
+ PSSD_CONFIG pSSDConfig,\r
+ UINT32 dest,\r
+ UINT32 size,\r
+ UINT32 source,\r
+ void (*CallBack)(void)\r
+ );\r
+\r
+typedef UINT32 (*pPROGRAMVERIFY) (\r
+ PSSD_CONFIG pSSDConfig,\r
+ UINT32 dest,\r
+ UINT32 size,\r
+ UINT32 source,\r
+ UINT32 *pFailAddress,\r
+ UINT64 *pFailData,\r
+ UINT64 *pFailSource,\r
+ void (*CallBack)(void)\r
+ );\r
+\r
+typedef UINT32 (*pCHECKSUM) (\r
+ PSSD_CONFIG pSSDConfig,\r
+ UINT32 dest,\r
+ UINT32 size,\r
+ UINT32 *pSum,\r
+ void (*CallBack)(void)\r
+ );\r
+\r
+typedef UINT32 (*pFLASHSUSPEND) (\r
+ PSSD_CONFIG pSSDConfig,\r
+ UINT8 *suspendState,\r
+ BOOL *suspendFlag\r
+ );\r
+\r
+typedef UINT32 (*pFLASHRESUME) (\r
+ PSSD_CONFIG pSSDConfig,\r
+ UINT8 *resumeState\r
+ );\r
+\r
+typedef UINT32 (*pGETLOCK) (\r
+ PSSD_CONFIG pSSDConfig,\r
+ UINT8 blkLockIndicator,\r
+ BOOL *blkLockEnabled,\r
+ UINT32 *blkLockState\r
+ );\r
+\r
+typedef UINT32 (*pSETLOCK) (\r
+ PSSD_CONFIG pSSDConfig,\r
+ UINT8 blkLockIndicator,\r
+ UINT32 blkLockState,\r
+ UINT32 password\r
+ );\r
+\r
+typedef UINT32 (*pRWECHECK) ( PSSD_CONFIG pSSDConfig );\r
+\r
+typedef UINT32 (*pGETWAITSTATE) (\r
+ PSSD_CONFIG pSSDConfig,\r
+ UINT32 *pAPCValue,\r
+ UINT32 *pWWSCValue,\r
+ UINT32 *pRWSCValue\r
+ );\r
+\r
+typedef UINT32 (*pSETWAITSTATE) (\r
+ PSSD_CONFIG pSSDConfig,\r
+ UINT32 APCValue,\r
+ UINT32 WWSCValue,\r
+ UINT32 RWSCValue\r
+ );\r
+\r
+#endif\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*************************************************************************\r
+ * (c) Copyright Motorola 2005, All Rights Reserved *\r
+ *************************************************************************\r
+ * *\r
+ * Motorola reserves the right to make changes without further notice *\r
+ * to any product herein to improve reliability, function or design. *\r
+ * Motorola does not assume any liability arising out of the *\r
+ * application or use of any product, circuit, or software described *\r
+ * herein; neither does it convey any license under its patent rights *\r
+ * nor the rights of others. *\r
+ * *\r
+ * Motorola products are not designed, intended, or authorized for *\r
+ * use as components in systems intended for surgical implant into *\r
+ * the body, or other applications intended to support life, or for *\r
+ * any other application in which the failure of the Motorola product *\r
+ * could create a situation where personal injury or death may occur. *\r
+ * *\r
+ * Should Buyer purchase or use Motorola products for any such *\r
+ * unintended or unauthorized application, Buyer shall indemnify and *\r
+ * hold Motorola and its officers, employees, subsidiaries, *\r
+ * affiliates, and distributors harmless against all claims costs, *\r
+ * damages, and expenses, and reasonable attorney fees arising out *\r
+ * of, directly or indirectly, any claim of personal injury or death *\r
+ * associated with such unintended or unauthorized use, even if such *\r
+ * claim alleges that Motorola was negligent regarding the design *\r
+ * or manufacture of the part. *\r
+ * *\r
+ * Motorola and the Motorola logo* are registered trademarks of *\r
+ * Motorola Ltd. *\r
+ * *\r
+ *************************************************************************\r
+\r
+ *************************************************************************\r
+ * *\r
+ * Standard Software H7F Driver for MPC55xx *\r
+ * *\r
+ * FILE NAME : ssd_h7f_internal.h *\r
+ * DATE : June 23, 2005 *\r
+ * *\r
+ * AUTHOR : Flash Team, *\r
+ * Global Software Group, China, Motorola Inc. *\r
+ * E-mail : flash@sc.mcel.mot.com *\r
+ * *\r
+ *************************************************************************/\r
+\r
+/******************************* CHANGES *********************************\r
+ 3.20 2005.06.23 Cloud Li Initial Version\r
+ *************************************************************************/\r
+\r
+#ifndef _SSD_H7F_INTERNAL_H_\r
+#define _SSD_H7F_INTERNAL_H_\r
+\r
+/* cycles counter used in FlashResume */\r
+/* about 500ns at 400MHz system clock */\r
+#define FLASH_RESUME_WAIT 15\r
+\r
+/*************************************************************************/\r
+/* CallBack function period */\r
+/*************************************************************************/\r
+#define CALLBACK_BC 90\r
+#define CALLBACK_PV 80\r
+#define CALLBACK_CS 120\r
+\r
+#endif /* _SSD_H7F_INTERNAL_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*************************************************************************\r
+ * (c) Copyright Motorola 2005, All Rights Reserved *\r
+ *************************************************************************\r
+ * *\r
+ * Motorola reserves the right to make changes without further notice *\r
+ * to any product herein to improve reliability, function or design. *\r
+ * Motorola does not assume any liability arising out of the *\r
+ * application or use of any product, circuit, or software described *\r
+ * herein; neither does it convey any license under its patent rights *\r
+ * nor the rights of others. *\r
+ * *\r
+ * Motorola products are not designed, intended, or authorized for *\r
+ * use as components in systems intended for surgical implant into *\r
+ * the body, or other applications intended to support life, or for *\r
+ * any other application in which the failure of the Motorola product *\r
+ * could create a situation where personal injury or death may occur. *\r
+ * *\r
+ * Should Buyer purchase or use Motorola products for any such *\r
+ * unintended or unauthorized application, Buyer shall indemnify and *\r
+ * hold Motorola and its officers, employees, subsidiaries, *\r
+ * affiliates, and distributors harmless against all claims costs, *\r
+ * damages, and expenses, and reasonable attorney fees arising out *\r
+ * of, directly or indirectly, any claim of personal injury or death *\r
+ * associated with such unintended or unauthorized use, even if such *\r
+ * claim alleges that Motorola was negligent regarding the design *\r
+ * or manufacture of the part. *\r
+ * *\r
+ * Motorola and the Motorola logo* are registered trademarks of *\r
+ * Motorola Ltd. *\r
+ * *\r
+ *************************************************************************\r
+\r
+ *************************************************************************\r
+ * *\r
+ * Standard Software H7F Driver for MPC55xx *\r
+ * *\r
+ * FILE NAME : ssd_types.h *\r
+ * DATE : June 23, 2005 *\r
+ * *\r
+ * AUTHOR : Flash Team, *\r
+ * Global Software Group, China, Motorola Inc. *\r
+ * E-mail : flash@sc.mcel.mot.com *\r
+ * *\r
+ *************************************************************************/\r
+\r
+/******************************* CHANGES *********************************\r
+ 3.20 2005.06.23 Cloud Li Initial Version\r
+ *************************************************************************/\r
+\r
+#ifndef _SSD_TYPES_H_\r
+#define _SSD_TYPES_H_\r
+\r
+/*************************************************************************/\r
+/* SSD general data types */\r
+/*************************************************************************/\r
+\r
+#ifndef FALSE\r
+#define FALSE 0\r
+#endif\r
+\r
+#ifndef TRUE\r
+#define TRUE (!FALSE)\r
+#endif\r
+\r
+typedef unsigned char BOOL;\r
+\r
+typedef signed char INT8;\r
+typedef unsigned char UINT8;\r
+typedef volatile signed char VINT8;\r
+typedef volatile unsigned char VUINT8;\r
+\r
+typedef signed short INT16;\r
+typedef unsigned short UINT16;\r
+typedef volatile signed short VINT16;\r
+typedef volatile unsigned short VUINT16;\r
+\r
+typedef signed long INT32;\r
+typedef unsigned long UINT32;\r
+typedef volatile signed long VINT32;\r
+typedef volatile unsigned long VUINT32;\r
+\r
+typedef signed long long INT64;\r
+typedef unsigned long long UINT64;\r
+typedef volatile signed long long VINT64;\r
+typedef volatile unsigned long long VUINT64;\r
+\r
+#endif /* _SSD_TYPES_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include <assert.h>\r
+#include <stdlib.h>\r
+//#include "System.h"\r
+#include "mpc55xx.h"\r
+#include "Modules.h"\r
+#include "Mcu.h"\r
+#include "Adc.h"\r
+#include "Dma.h"\r
+#include "Det.h"\r
+#if defined(USE_KERNEL)\r
+#include "Os.h"\r
+#endif\r
+\r
+\r
+typedef union\r
+{\r
+ vuint32_t R;\r
+ struct\r
+ {\r
+ vuint32_t EOQ:1;\r
+ vuint32_t PAUSE:1;\r
+ vuint32_t :4;\r
+ vuint32_t BN:1;\r
+ vuint32_t RW:1;\r
+ vuint32_t ADC_REG:16;\r
+ vuint32_t ADC_REG_ADDR:8;\r
+ } B;\r
+}Adc_RegisterWriteType;\r
+\r
+typedef union\r
+{\r
+ vuint32_t R;\r
+ struct\r
+ {\r
+ vuint32_t EOQ:1;\r
+ vuint32_t PAUSE:1;\r
+ vuint32_t :4;\r
+ vuint32_t BN:1;\r
+ vuint32_t RW:1;\r
+ vuint32_t MESSAGE_TAG:4;\r
+ vuint32_t :12;\r
+ vuint32_t ADC_REG_ADDR:8;\r
+ } B;\r
+}Adc_RegisterReadType;\r
+\r
+typedef enum\r
+{\r
+ ADC_UNINIT,\r
+ ADC_INIT,\r
+}Adc_StateType;\r
+\r
+typedef enum\r
+{\r
+ ADC_EQADC_QUEUE_0,\r
+ ADC_EQADC_QUEUE_1,\r
+ ADC_EQADC_QUEUE_2,\r
+ ADC_EQADC_QUEUE_3,\r
+ ADC_EQADC_QUEUE_4,\r
+ ADC_EQADC_QUEUE_5,\r
+ ADC_EQADC_NBR_OF_QUEUES\r
+}Adc_eQADCQueueType;\r
+\r
+typedef enum\r
+{\r
+ EQADC_CFIFO_STATUS_IDLE = 0,\r
+ EQADC_CFIFO_STATUS_WAITINGFOR_TRIGGER = 0x2,\r
+ EQADC_CFIFO_STATUS_TRIGGERED = 0x3\r
+}Adc_EQADCQueueStatusType;\r
+\r
+\r
+typedef int16_t Adc_EQADCRegister;\r
+\r
+typedef enum\r
+{\r
+ ADC0_CR = 1,\r
+ ADC0_TSCR,\r
+ ADC0_TBCR,\r
+ ADC0_GCCR,\r
+ ADC0_OCCR\r
+}Adc_EQADCRegisterType;\r
+\r
+/* Function prototypes. */\r
+static void Adc_ConfigureEQADC (const Adc_ConfigType *ConfigPtr);\r
+static void Adc_ConfigureEQADCInterrupts (void);\r
+static void Adc_EQADCCalibrationSequence (void);\r
+static void Adc_WriteEQADCRegister (Adc_EQADCRegisterType reg, Adc_EQADCRegister value);\r
+static Adc_EQADCRegister Adc_ReadEQADCRegister (Adc_EQADCRegisterType reg);\r
+\r
+/* Development error checking. */\r
+static Std_ReturnType Adc_CheckReadGroup (Adc_GroupType group);\r
+static Std_ReturnType Adc_CheckStartGroupConversion (Adc_GroupType group);\r
+static Std_ReturnType Adc_CheckInit (const Adc_ConfigType *ConfigPtr);\r
+static Std_ReturnType Adc_CheckSetupResultBuffer (Adc_GroupType group);\r
+\r
+\r
+static Adc_StateType adcState = ADC_UNINIT;\r
+\r
+/* Pointer to configuration structure. */\r
+static const Adc_ConfigType *AdcConfigPtr;\r
+\r
+/* Command queue for calibration sequence. See 31.5.6 in reference manual. */\r
+const Adc_CommandType AdcCalibrationCommandQueue [] =\r
+{\r
+ /* Four samples of 25 % of (VRh - VRl). */\r
+ {\r
+ .B.EOQ = 0, .B.PAUSE = 0, .B.BN = 0, .B.CAL = 0, .B.MESSAGE_TAG = 0, .B.LST = ADC_CONVERSION_TIME_128_CLOCKS, .B.TSR = 0, .B.FMT = 0,\r
+ .B.CHANNEL_NUMBER = 44\r
+ },\r
+ {\r
+ .B.EOQ = 0, .B.PAUSE = 0, .B.BN = 0, .B.CAL = 0, .B.MESSAGE_TAG = 0, .B.LST = ADC_CONVERSION_TIME_128_CLOCKS, .B.TSR = 0, .B.FMT = 0,\r
+ .B.CHANNEL_NUMBER = 44\r
+ },\r
+ {\r
+ .B.EOQ = 0, .B.PAUSE = 0, .B.BN = 0, .B.CAL = 0, .B.MESSAGE_TAG = 0, .B.LST = ADC_CONVERSION_TIME_128_CLOCKS, .B.TSR = 0, .B.FMT = 0,\r
+ .B.CHANNEL_NUMBER = 44\r
+ },\r
+ {\r
+ .B.EOQ = 0, .B.PAUSE = 0, .B.BN = 0, .B.CAL = 0, .B.MESSAGE_TAG = 0, .B.LST = ADC_CONVERSION_TIME_128_CLOCKS, .B.TSR = 0, .B.FMT = 0,\r
+ .B.CHANNEL_NUMBER = 44\r
+ },\r
+ /* Four samples of 75 % of (VRh - VRl). */\r
+ {\r
+ .B.EOQ = 0, .B.PAUSE = 0, .B.BN = 0, .B.CAL = 0, .B.MESSAGE_TAG = 0, .B.LST = ADC_CONVERSION_TIME_128_CLOCKS, .B.TSR = 0, .B.FMT = 0,\r
+ .B.CHANNEL_NUMBER = 43\r
+ },\r
+ {\r
+ .B.EOQ = 0, .B.PAUSE = 0, .B.BN = 0, .B.CAL = 0, .B.MESSAGE_TAG = 0, .B.LST = ADC_CONVERSION_TIME_128_CLOCKS, .B.TSR = 0, .B.FMT = 0,\r
+ .B.CHANNEL_NUMBER = 43\r
+ },\r
+ {\r
+ .B.EOQ = 0, .B.PAUSE = 0, .B.BN = 0, .B.CAL = 0, .B.MESSAGE_TAG = 0, .B.LST = ADC_CONVERSION_TIME_128_CLOCKS, .B.TSR = 0, .B.FMT = 0,\r
+ .B.CHANNEL_NUMBER = 43\r
+ },\r
+ {\r
+ .B.EOQ = 1, .B.PAUSE = 0, .B.BN = 0, .B.CAL = 0, .B.MESSAGE_TAG = 0, .B.LST = ADC_CONVERSION_TIME_128_CLOCKS, .B.TSR = 0, .B.FMT = 0,\r
+ .B.CHANNEL_NUMBER = 43\r
+ }\r
+};\r
+\r
+/* DMA configuration for calibration sequence. */\r
+const struct tcd_t AdcCalibrationDMACommandConfig =\r
+{\r
+ .SADDR = (uint32_t)AdcCalibrationCommandQueue,\r
+ .SMOD = 0,\r
+ .SSIZE = DMA_TRANSFER_SIZE_32BITS,\r
+ .DMOD = 0,\r
+ .DSIZE = DMA_TRANSFER_SIZE_32BITS,\r
+ .SOFF = sizeof(Adc_CommandType),\r
+ .NBYTES = sizeof(Adc_CommandType),\r
+ .SLAST = 0,\r
+ .DADDR = (vint32_t)&EQADC.CFPR[0].R,\r
+ .CITERE_LINK = 0,\r
+ .CITER = 0,\r
+ .DOFF = 0,\r
+ .DLAST_SGA = 0,\r
+ .BITERE_LINK = 0,\r
+ .BITER = 0,\r
+ .BWC = 0,\r
+ .MAJORLINKCH = 0,\r
+ .DONE = 0,\r
+ .ACTIVE = 0,\r
+ .MAJORE_LINK = 0,\r
+ .E_SG = 0,\r
+ .D_REQ = 0,\r
+ .INT_HALF = 0,\r
+ .INT_MAJ = 0,\r
+ .START = 0,\r
+};\r
+\r
+const struct tcd_t AdcCalibrationDMAResultConfig =\r
+{\r
+ .SADDR = (vint32_t)&EQADC.RFPR[0].R + 2,\r
+ .SMOD = 0,\r
+ .SSIZE = DMA_TRANSFER_SIZE_16BITS,\r
+ .DMOD = 0,\r
+ .DSIZE = DMA_TRANSFER_SIZE_16BITS,\r
+ .SOFF = 0,\r
+ .NBYTES = sizeof(Adc_ValueGroupType),\r
+ .SLAST = 0,\r
+ .DADDR = 0, /* Dynamic address, written later. */\r
+ .CITERE_LINK = 0,\r
+ .CITER = 0,\r
+ .DOFF = sizeof(Adc_ValueGroupType),\r
+ .DLAST_SGA = 0,\r
+ .BITERE_LINK = 0,\r
+ .BITER = 0,\r
+ .BWC = 0,\r
+ .MAJORLINKCH = 0,\r
+ .DONE = 0,\r
+ .ACTIVE = 0,\r
+ .MAJORE_LINK = 0,\r
+ .E_SG = 0,\r
+ .D_REQ = 0,\r
+ .INT_HALF = 0,\r
+ .INT_MAJ = 0,\r
+ .START = 0\r
+};\r
+\r
+#if (ADC_DEINIT_API == STD_ON)\r
+Std_ReturnType Adc_DeInit (const Adc_ConfigType *ConfigPtr)\r
+{\r
+ Adc_eQADCQueueType queue;\r
+ Adc_GroupType group;\r
+ boolean queueStopped;\r
+\r
+ if (ADC_UNINIT != adcState)\r
+ {\r
+ /* Stop all queues. */\r
+ for (queue = ADC_EQADC_QUEUE_0; queue < ADC_EQADC_NBR_OF_QUEUES; queue++)\r
+ {\r
+ /* Disable queue. */\r
+ EQADC.CFCR[queue].B.MODE = 0;\r
+\r
+ /* Wait for queue to enter idle state. */\r
+ queueStopped = FALSE;\r
+ /* TODO replace switch with bit pattern. */\r
+ while (!queueStopped)\r
+ {\r
+ switch (queue)\r
+ {\r
+ case ADC_EQADC_QUEUE_0:\r
+ queueStopped = (EQADC.CFSR.B.CFS0 == EQADC_CFIFO_STATUS_IDLE);\r
+ break;\r
+ case ADC_EQADC_QUEUE_1:\r
+ queueStopped = (EQADC.CFSR.B.CFS1 == EQADC_CFIFO_STATUS_IDLE);\r
+ break;\r
+ case ADC_EQADC_QUEUE_2:\r
+ queueStopped = (EQADC.CFSR.B.CFS2 == EQADC_CFIFO_STATUS_IDLE);\r
+ break;\r
+ case ADC_EQADC_QUEUE_3:\r
+ queueStopped = (EQADC.CFSR.B.CFS3 == EQADC_CFIFO_STATUS_IDLE);\r
+ break;\r
+ case ADC_EQADC_QUEUE_4:\r
+ queueStopped = (EQADC.CFSR.B.CFS4 == EQADC_CFIFO_STATUS_IDLE);\r
+ break;\r
+ case ADC_EQADC_QUEUE_5:\r
+ queueStopped = (EQADC.CFSR.B.CFS5 == EQADC_CFIFO_STATUS_IDLE);\r
+ break;\r
+ default :\r
+ /* We should never get here... Terminate loop. */\r
+ queueStopped = TRUE;\r
+ break;\r
+ }\r
+ }\r
+\r
+ /* Disable eDMA requests for commands and results. */\r
+ EQADC.IDCR[queue].B.CFFS = 0;\r
+ EQADC.IDCR[queue].B.RFDS = 0;\r
+\r
+ /* Disable FIFO fill requests. */\r
+ EQADC.IDCR[queue].B.CFFE = 0;\r
+ EQADC.IDCR[queue].B.RFDE = 0;\r
+\r
+ /* Disable interrupts. */\r
+ EQADC.IDCR[queue].B.RFOIE = 0;\r
+ EQADC.IDCR[queue].B.CFUIE = 0;\r
+ EQADC.IDCR[queue].B.TORIE = 0;\r
+ EQADC.IDCR[queue].B.EOQIE = 0;\r
+ }\r
+\r
+ /* Stop all DMA channels connected to EQADC. */\r
+ for (group = ADC_GROUP0; group < AdcConfigPtr->nbrOfGroups; group++)\r
+ {\r
+ Dma_StopChannel (AdcConfigPtr->groupConfigPtr [group].dmaCommandChannel);\r
+ Dma_StopChannel (AdcConfigPtr->groupConfigPtr [group].dmaResultChannel);\r
+\r
+ /* Set group status to idle. */\r
+ AdcConfigPtr->groupConfigPtr[group].status->groupStatus = ADC_IDLE;\r
+ }\r
+\r
+ /* Disable EQADC. */\r
+ Adc_WriteEQADCRegister (ADC0_CR, 0);\r
+\r
+ /* Clean internal status. */\r
+ AdcConfigPtr = (Adc_ConfigType *)NULL;\r
+ adcState = ADC_UNINIT;\r
+ }\r
+ return (E_OK);\r
+}\r
+#endif\r
+\r
+Std_ReturnType Adc_Init (const Adc_ConfigType *ConfigPtr)\r
+{\r
+ Std_ReturnType returnValue;\r
+ Adc_ChannelType channel;\r
+ Adc_ChannelType channelId;\r
+ Adc_GroupType group;\r
+ Adc_CommandType *commandQueue;\r
+ Adc_CommandType command;\r
+\r
+ if (E_OK == Adc_CheckInit(ConfigPtr))\r
+ {\r
+ /* First of all, store the location of the configuration data. */\r
+ AdcConfigPtr = ConfigPtr;\r
+\r
+ /* Start configuring the eQADC queues. */\r
+ for (group = ADC_GROUP0; group < ConfigPtr->nbrOfGroups; group++)\r
+ {\r
+ /* Loop through all channels and make the command queue. */\r
+ for (channel = 0; channel < ConfigPtr->groupConfigPtr[group].numberOfChannels; channel++)\r
+ {\r
+ /* Get physical channel. */\r
+ channelId = ConfigPtr->groupConfigPtr[group].channelList[channel];\r
+\r
+ commandQueue = ConfigPtr->groupConfigPtr[group].commandBuffer;\r
+\r
+ /* Begin with empty command. */\r
+ command.R = 0;\r
+\r
+ /* Physical channel number. */\r
+ command.B.CHANNEL_NUMBER = channelId;\r
+ /* Sample time. */\r
+ command.B.LST = ConfigPtr->channelConfigPtr [channel].adcChannelConvTime;\r
+ /* Calibration feature. */\r
+ command.B.CAL = ConfigPtr->channelConfigPtr [channel].adcChannelCalibrationEnable;\r
+ /* Result buffer FIFO. The number of groups must not be greater than the number of queues. */\r
+ command.B.MESSAGE_TAG = group;\r
+\r
+ /* Write command to command queue. */\r
+ commandQueue [channel].R = command.R;\r
+\r
+ /* Last channel in group. Write EOQ and configure eQADC FIFO. */\r
+ if (channel == (ConfigPtr->groupConfigPtr[group].numberOfChannels - 1))\r
+ {\r
+ commandQueue [channel].B.EOQ = 1;\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Enable ADC. */\r
+ Adc_ConfigureEQADC (ConfigPtr);\r
+\r
+ /* Perform calibration of the ADC. */\r
+ Adc_EQADCCalibrationSequence ();\r
+\r
+ /* Configure DMA channels. */\r
+ for (group = ADC_GROUP0; group < ConfigPtr->nbrOfGroups; group++)\r
+ {\r
+ /* ADC307. */\r
+ ConfigPtr->groupConfigPtr[group].status->groupStatus = ADC_IDLE;\r
+\r
+ Dma_ConfigureChannel ((struct tcd_t *)ConfigPtr->groupConfigPtr [group].groupDMAResults, ConfigPtr->groupConfigPtr [group].dmaResultChannel);\r
+ Dma_ConfigureChannel ((struct tcd_t *)ConfigPtr->groupConfigPtr [group].groupDMACommands, ConfigPtr->groupConfigPtr [group].dmaCommandChannel);\r
+ }\r
+\r
+ /* Start DMA channels. */\r
+ for (group = ADC_GROUP0; group < ConfigPtr->nbrOfGroups; group++)\r
+ {\r
+ /* Invalidate queues. */\r
+ EQADC.CFCR[group].B.CFINV = 1;\r
+\r
+ Dma_StartChannel (ConfigPtr->groupConfigPtr [group].dmaResultChannel);\r
+ Dma_StartChannel (ConfigPtr->groupConfigPtr [group].dmaCommandChannel);\r
+ }\r
+\r
+ Adc_ConfigureEQADCInterrupts ();\r
+\r
+ /* Move on to INIT state. */\r
+ adcState = ADC_INIT;\r
+ returnValue = E_OK;\r
+ }\r
+ else\r
+ {\r
+ returnValue = E_NOT_OK;\r
+ }\r
+\r
+ return (returnValue);\r
+}\r
+\r
+Std_ReturnType Adc_SetupResultBuffer (Adc_GroupType group, Adc_ValueGroupType *bufferPtr)\r
+{\r
+ Std_ReturnType returnValue;\r
+\r
+ /* Check for development errors. */\r
+ if (E_OK == Adc_CheckSetupResultBuffer (group))\r
+ {\r
+ AdcConfigPtr->groupConfigPtr[group].status->resultBufferPtr = bufferPtr;\r
+ returnValue = E_OK;\r
+ }\r
+ else\r
+ {\r
+ /* An error have been raised from Adc_CheckSetupResultBuffer(). */\r
+ returnValue = E_NOT_OK;\r
+ }\r
+\r
+ return (returnValue);\r
+}\r
+\r
+#if (ADC_READ_GROUP_API == STD_ON)\r
+Std_ReturnType Adc_ReadGroup (Adc_GroupType group, Adc_ValueGroupType *dataBufferPtr)\r
+{\r
+ Std_ReturnType returnValue;\r
+ Adc_ChannelType channel;\r
+\r
+ if (E_OK == Adc_CheckReadGroup (group))\r
+ {\r
+ if ((ADC_CONV_MODE_CONTINOUS == AdcConfigPtr->groupConfigPtr[group].conversionMode) &&\r
+ ((ADC_STREAM_COMPLETED == AdcConfigPtr->groupConfigPtr[group].status->groupStatus) ||\r
+ (ADC_COMPLETED == AdcConfigPtr->groupConfigPtr[group].status->groupStatus)))\r
+ {\r
+ /* ADC329, ADC331. */\r
+ AdcConfigPtr->groupConfigPtr[group].status->groupStatus = ADC_BUSY;\r
+ returnValue = E_OK;\r
+ }\r
+ else if ((ADC_CONV_MODE_ONESHOT == AdcConfigPtr->groupConfigPtr[group].conversionMode) &&\r
+ (ADC_STREAM_COMPLETED == AdcConfigPtr->groupConfigPtr[group].status->groupStatus))\r
+ {\r
+ /* ADC330. */\r
+ AdcConfigPtr->groupConfigPtr[group].status->groupStatus = ADC_IDLE;\r
+\r
+ returnValue = E_OK;\r
+ }\r
+ else\r
+ {\r
+ /* Keep status. */\r
+ returnValue = E_OK;\r
+ }\r
+\r
+ if (E_OK == returnValue)\r
+ {\r
+ /* Copy the result to application buffer. */\r
+ for (channel = 0; channel < AdcConfigPtr->groupConfigPtr[group].numberOfChannels; channel++)\r
+ {\r
+ dataBufferPtr[channel] = AdcConfigPtr->groupConfigPtr[group].resultBuffer[channel];\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* An error have been raised from Adc_CheckReadGroup(). */\r
+ returnValue = E_NOT_OK;\r
+ }\r
+\r
+ return (returnValue);\r
+}\r
+#endif\r
+\r
+Adc_StatusType Adc_GetGroupStatus (Adc_GroupType group)\r
+{\r
+ Adc_StatusType returnValue;\r
+ if ((ADC_INIT == adcState) && (AdcConfigPtr != NULL))\r
+ {\r
+ /* Adc initilised, OK to move on... */\r
+ returnValue = AdcConfigPtr->groupConfigPtr[group].status->groupStatus;\r
+ }\r
+ else\r
+ {\r
+ returnValue = ADC_IDLE;\r
+#if ( ADC_DEV_ERROR_DETECT == STD_ON )\r
+ Det_ReportError(MODULE_ID_ADC,0,ADC_GETGROUPSTATUS_ID, ADC_E_UNINIT );\r
+#endif\r
+ }\r
+\r
+ return (returnValue);\r
+}\r
+\r
+\r
+void Adc_Group0ConversionComplete (void)\r
+{\r
+ /* ISR for FIFO 0 end of queue. Clear interrupt flag. */\r
+ EQADC.FISR[ADC_EQADC_QUEUE_0].B.EOQF = 1;\r
+\r
+ /* Sample completed. */\r
+ AdcConfigPtr->groupConfigPtr[ADC_GROUP0].status->groupStatus = ADC_STREAM_COMPLETED;\r
+\r
+ /* Call notification if enabled. */\r
+#if (ADC_GRP_NOTIF_CAPABILITY == STD_ON)\r
+ if (AdcConfigPtr->groupConfigPtr[ADC_GROUP0].status->notifictionEnable && AdcConfigPtr->groupConfigPtr[ADC_GROUP0].groupCallback != NULL)\r
+ {\r
+ AdcConfigPtr->groupConfigPtr[ADC_GROUP0].groupCallback();\r
+ }\r
+#endif\r
+}\r
+void Adc_Group1ConversionComplete (void)\r
+{\r
+ /* ISR for FIFO 0 end of queue. Clear interrupt flag. */\r
+ EQADC.FISR[ADC_EQADC_QUEUE_1].B.EOQF = 1;\r
+\r
+ /* Sample completed. */\r
+ AdcConfigPtr->groupConfigPtr[ADC_GROUP1].status->groupStatus = ADC_STREAM_COMPLETED;\r
+\r
+ /* Call notification if enabled. */\r
+#if (ADC_GRP_NOTIF_CAPABILITY == STD_ON)\r
+ if (AdcConfigPtr->groupConfigPtr[ADC_GROUP1].status->notifictionEnable && AdcConfigPtr->groupConfigPtr[ADC_GROUP1].groupCallback != NULL)\r
+ {\r
+ AdcConfigPtr->groupConfigPtr[ADC_GROUP1].groupCallback();\r
+ }\r
+#endif\r
+}\r
+\r
+void Adc_EQADCError (void)\r
+{\r
+ /* Something is wrong!! Check the cause of the error and try to correct it. */\r
+ if (EQADC.FISR[ADC_EQADC_QUEUE_0].B.TORF)\r
+ {\r
+ /* Trigger overrun on queue 0!! */\r
+ assert (0);\r
+ }\r
+ else if (EQADC.FISR[ADC_EQADC_QUEUE_1].B.TORF)\r
+ {\r
+ /* Trigger overrun on queue 1!! */\r
+ assert (0);\r
+ }\r
+ else if (EQADC.FISR[ADC_EQADC_QUEUE_0].B.CFUF)\r
+ {\r
+ /* Command underflow on queue 0!! */\r
+ assert (0);\r
+ }\r
+ else if (EQADC.FISR[ADC_EQADC_QUEUE_1].B.CFUF)\r
+ {\r
+ /* Command underflow on queue 1!! */\r
+ assert (0);\r
+ }\r
+ else if (EQADC.FISR[ADC_EQADC_QUEUE_0].B.RFOF)\r
+ {\r
+ /* Result overflow on queue 0!! */\r
+ assert (0);\r
+ }\r
+ else if (EQADC.FISR[ADC_EQADC_QUEUE_1].B.RFOF)\r
+ {\r
+ /* Result overflow on queue 1!! */\r
+ assert (0);\r
+ }\r
+ else\r
+ {\r
+ /* Something else... TODO What have we missed above */\r
+ assert(0);\r
+ }\r
+}\r
+\r
+/* Helper macro to make sure that the qommand queue have\r
+ * executed the commands in the fifo.\r
+ * First check that the H/W negate the\r
+ * single scan bit and then wait for EOQ. */\r
+#define WAIT_FOR_QUEUE_TO_FINISH(q) \\r
+ while (EQADC.FISR[q].B.SSS) \\r
+ { \\r
+ ; \\r
+ } \\r
+ \\r
+ while (!EQADC.FISR[q].B.EOQF) \\r
+ { \\r
+ ; \\r
+ }\r
+\r
+static void Adc_WriteEQADCRegister (Adc_EQADCRegisterType reg, Adc_EQADCRegister value)\r
+{\r
+ Adc_RegisterWriteType writeReg;\r
+ uint32_t temp, oldMode;\r
+\r
+ writeReg.R = 0;\r
+\r
+ /* Write command. */\r
+ writeReg.B.RW = 0;\r
+ writeReg.B.EOQ = 1;\r
+ writeReg.B.ADC_REG = value;\r
+ writeReg.B.ADC_REG_ADDR = reg;\r
+\r
+ /* Invalidate queue. */\r
+ EQADC.CFCR[ADC_EQADC_QUEUE_0].B.CFINV = 1;\r
+\r
+\r
+ /* Write command through FIFO. */\r
+ EQADC.CFPR[ADC_EQADC_QUEUE_0].R = writeReg.R;\r
+\r
+ /* Enable FIFO. */\r
+ oldMode = EQADC.CFCR[ADC_EQADC_QUEUE_0].B.MODE;\r
+ EQADC.CFCR[ADC_EQADC_QUEUE_0].B.MODE = ADC_CONV_MODE_ONESHOT;\r
+ EQADC.CFCR[ADC_EQADC_QUEUE_0].B.SSE = 1;\r
+\r
+ /* Wait for command to be executed. */\r
+ WAIT_FOR_QUEUE_TO_FINISH(ADC_EQADC_QUEUE_0);\r
+\r
+ /* Flush result buffer. */\r
+ temp = EQADC.RFPR[ADC_EQADC_QUEUE_0].R;\r
+ EQADC.FISR[ADC_EQADC_QUEUE_0].B.EOQF = 1;\r
+\r
+ EQADC.CFCR[ADC_EQADC_QUEUE_0].B.MODE = oldMode;\r
+\r
+}\r
+\r
+static Adc_EQADCRegister Adc_ReadEQADCRegister (Adc_EQADCRegisterType reg)\r
+{\r
+ Adc_RegisterReadType readReg;\r
+ Adc_EQADCRegister result;\r
+ uint32_t oldMode, dmaRequestEnable;\r
+\r
+ readReg.R = 0;\r
+\r
+ /* Read command. */\r
+ readReg.B.RW = 1;\r
+ readReg.B.EOQ = 1;\r
+ readReg.B.ADC_REG_ADDR = reg;\r
+ readReg.B.MESSAGE_TAG = ADC_EQADC_QUEUE_0;\r
+\r
+ /* Make sure that DMA requests for command fill and result drain is disabled. */\r
+ if (EQADC.IDCR[ADC_EQADC_QUEUE_0].B.RFDE || EQADC.IDCR[ADC_EQADC_QUEUE_0].B.CFFE)\r
+ {\r
+ EQADC.IDCR[ADC_EQADC_QUEUE_0].B.CFFE = 0;\r
+ EQADC.IDCR[ADC_EQADC_QUEUE_0].B.RFDE = 0;\r
+\r
+ /* Remember to enable requests again... */\r
+ dmaRequestEnable = TRUE;\r
+ }\r
+ else\r
+ {\r
+ dmaRequestEnable = FALSE;\r
+ }\r
+\r
+ /* Invalidate queue. */\r
+ EQADC.CFCR[ADC_EQADC_QUEUE_0].B.CFINV = 1;\r
+\r
+ /* Write command through FIFO. */\r
+ EQADC.CFPR[ADC_EQADC_QUEUE_0].R = readReg.R;\r
+\r
+ /* Enable FIFO. */\r
+ oldMode = EQADC.CFCR[ADC_EQADC_QUEUE_0].B.MODE;\r
+ EQADC.CFCR[ADC_EQADC_QUEUE_0].B.MODE = ADC_CONV_MODE_ONESHOT;\r
+ EQADC.CFCR[ADC_EQADC_QUEUE_0].B.SSE = 1;\r
+\r
+ /* Wait for command to be executed. */\r
+ WAIT_FOR_QUEUE_TO_FINISH(ADC_EQADC_QUEUE_0);\r
+\r
+ /* Read result buffer. */\r
+ result = EQADC.RFPR[ADC_EQADC_QUEUE_0].R;\r
+ EQADC.FISR[ADC_EQADC_QUEUE_0].B.EOQF = 1;\r
+\r
+ EQADC.CFCR[ADC_EQADC_QUEUE_0].B.MODE = oldMode;\r
+\r
+ if (dmaRequestEnable)\r
+ {\r
+ EQADC.IDCR[ADC_EQADC_QUEUE_0].B.CFFE = 1;\r
+ EQADC.IDCR[ADC_EQADC_QUEUE_0].B.RFDE = 1;\r
+ }\r
+ else\r
+ {\r
+ /* Do nothing. */\r
+ }\r
+ return (result);\r
+}\r
+\r
+#define SYSTEM_CLOCK_DIVIDE(f) ((f / 2) - 1)\r
+static void Adc_ConfigureEQADC (const Adc_ConfigType *ConfigPtr)\r
+{\r
+ Adc_GroupType group;\r
+\r
+ enum\r
+ {\r
+ ADC_ENABLE = 0x8000,\r
+ };\r
+ /* Enable ADC0. */\r
+ Adc_WriteEQADCRegister (ADC0_CR, (ADC_ENABLE | ConfigPtr->hwConfigPtr->adcPrescale));\r
+\r
+ /* Disable time stamp timer. */\r
+ Adc_WriteEQADCRegister (ADC0_TSCR, 0);\r
+\r
+ for (group = ADC_GROUP0; group < ConfigPtr->nbrOfGroups; group++)\r
+ {\r
+ /* Enable eDMA requests for commands and results. */\r
+ EQADC.IDCR[group].B.CFFS = 1;\r
+ EQADC.IDCR[group].B.RFDS = 1;\r
+\r
+ /* Invalidate FIFO. */\r
+ EQADC.CFCR[group].B.CFINV = 1;\r
+\r
+ /* Enable FIFO fill requests. */\r
+ EQADC.IDCR[group].B.CFFE = 1;\r
+ EQADC.IDCR[group].B.RFDE = 1;\r
+ }\r
+}\r
+\r
+/* TODO How do we handle interrupt priorities? */\r
+#define EQADC_FIFO0_END_OF_QUEUE_PRIORITY (1)\r
+#define EQADC_FIFO1_END_OF_QUEUE_PRIORITY (1)\r
+#define EQADC_FISR_OVER_PRIORITY (1)\r
+\r
+void Adc_ConfigureEQADCInterrupts (void)\r
+{\r
+ Adc_GroupType group;\r
+\r
+#if defined(USE_KERNEL)\r
+ TaskType tid;\r
+ tid = Os_CreateIsr(Adc_EQADCError,EQADC_FISR_OVER_PRIORITY,"Adc_Err");\r
+ IntCtrl_AttachIsr2(tid,NULL,EQADC_FISR_OVER);\r
+\r
+ tid = Os_CreateIsr(Adc_Group0ConversionComplete,EQADC_FIFO0_END_OF_QUEUE_PRIORITY,"Adc_Grp0");\r
+ IntCtrl_AttachIsr2(tid,NULL,EQADC_FISR0_EOQF0);\r
+\r
+ tid = Os_CreateIsr(Adc_Group1ConversionComplete,EQADC_FIFO1_END_OF_QUEUE_PRIORITY,"Adc_Grp1");\r
+ IntCtrl_AttachIsr2(tid,NULL,EQADC_FISR1_EOQF1);\r
+\r
+#else\r
+ IntCtrl_InstallVector (Adc_EQADCError,\r
+ EQADC_FISR_OVER,\r
+ EQADC_FISR_OVER_PRIORITY, CPU_Z1);\r
+\r
+ IntCtrl_InstallVector (Adc_Group0ConversionComplete,\r
+ EQADC_FISR0_EOQF0,\r
+ EQADC_FIFO0_END_OF_QUEUE_PRIORITY, CPU_Z1);\r
+\r
+ IntCtrl_InstallVector (Adc_Group1ConversionComplete,\r
+ EQADC_FISR1_EOQF1,\r
+ EQADC_FIFO1_END_OF_QUEUE_PRIORITY, CPU_Z1);\r
+\r
+#endif\r
+ for (group = ADC_GROUP0; group < AdcConfigPtr->nbrOfGroups; group++)\r
+ {\r
+ /* Enable end of queue, queue overflow/underflow interrupts. Clear corresponding flags. */\r
+ EQADC.FISR[group].B.RFOF = 1;\r
+ EQADC.IDCR[group].B.RFOIE = 1;\r
+\r
+ EQADC.FISR[group].B.CFUF = 1;\r
+ EQADC.IDCR[group].B.CFUIE = 1;\r
+\r
+ EQADC.FISR[group].B.TORF = 1;\r
+ EQADC.IDCR[group].B.TORIE = 1;\r
+\r
+ EQADC.FISR[group].B.EOQF = 1;\r
+ EQADC.IDCR[group].B.EOQIE = 1;\r
+ }\r
+}\r
+\r
+#if (ADC_ENABLE_START_STOP_GROUP_API == STD_ON)\r
+void Adc_StartGroupConversion (Adc_GroupType group)\r
+{\r
+ /* Run development error check. */\r
+ if (E_OK == Adc_CheckStartGroupConversion (group))\r
+ {\r
+ /* Set conversion mode. */\r
+ EQADC.CFCR[group].B.MODE = AdcConfigPtr->groupConfigPtr[group].conversionMode;\r
+\r
+ /* Set single scan enable bit if this group is one shot. */\r
+ if (AdcConfigPtr->groupConfigPtr[group].conversionMode == ADC_CONV_MODE_ONESHOT)\r
+ {\r
+ EQADC.CFCR[group].B.SSE = 1;\r
+\r
+ /* Set group state to BUSY. */\r
+ AdcConfigPtr->groupConfigPtr[group].status->groupStatus = ADC_BUSY;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Error have been set within Adc_CheckStartGroupConversion(). */\r
+ }\r
+}\r
+\r
+\r
+#endif\r
+\r
+#if (ADC_GRP_NOTIF_CAPABILITY == STD_ON)\r
+void Adc_EnableGroupNotification (Adc_GroupType group)\r
+{\r
+ AdcConfigPtr->groupConfigPtr[group].status->notifictionEnable = 1;\r
+}\r
+\r
+void Adc_DisableGroupNotification (Adc_GroupType group)\r
+{\r
+ AdcConfigPtr->groupConfigPtr[group].status->notifictionEnable = 0;\r
+}\r
+#endif\r
+\r
+static void Adc_EQADCCalibrationSequence (void)\r
+{\r
+ Adc_ValueGroupType calibrationResult[sizeof(AdcCalibrationCommandQueue)/sizeof(AdcCalibrationCommandQueue[0])];\r
+ int32_t point25Average, point75Average, i;\r
+ Adc_EQADCRegister tempGCC, tempOCC;\r
+ enum\r
+ {\r
+ IDEAL_RES25 = 0x1000,\r
+ IDEAL_RES75 = 0x3000,\r
+ };\r
+\r
+ /* Use group 0 DMA channel for calibration. */\r
+ Dma_ConfigureChannel ((struct tcd_t *)&AdcCalibrationDMACommandConfig,DMA_ADC_GROUP0_COMMAND_CHANNEL);\r
+ Dma_ConfigureChannelTranferSize (sizeof(AdcCalibrationCommandQueue)/sizeof(AdcCalibrationCommandQueue[0]),\r
+ DMA_ADC_GROUP0_COMMAND_CHANNEL);\r
+ Dma_ConfigureChannelSourceCorr (-sizeof(AdcCalibrationCommandQueue), DMA_ADC_GROUP0_COMMAND_CHANNEL);\r
+\r
+ Dma_ConfigureChannel ((struct tcd_t *)&AdcCalibrationDMAResultConfig, DMA_ADC_GROUP0_RESULT_CHANNEL);\r
+ Dma_ConfigureChannelTranferSize (sizeof(calibrationResult)/sizeof(calibrationResult[0]),\r
+ DMA_ADC_GROUP0_RESULT_CHANNEL);\r
+ Dma_ConfigureChannelDestinationCorr (-sizeof(calibrationResult), DMA_ADC_GROUP0_RESULT_CHANNEL);\r
+ Dma_ConfigureDestinationAddress ((uint32_t)calibrationResult, DMA_ADC_GROUP0_RESULT_CHANNEL);\r
+\r
+ /* Invalidate queues. */\r
+ EQADC.CFCR[ADC_EQADC_QUEUE_0].B.CFINV = 1;\r
+\r
+ Dma_StartChannel (DMA_ADC_GROUP0_COMMAND_CHANNEL);\r
+ Dma_StartChannel (DMA_ADC_GROUP0_RESULT_CHANNEL);\r
+\r
+ /* Start conversion. */\r
+ EQADC.CFCR[ADC_EQADC_QUEUE_0].B.MODE = ADC_CONV_MODE_ONESHOT;\r
+ EQADC.CFCR[ADC_EQADC_QUEUE_0].B.SSE = 1;\r
+\r
+ /* Wait for conversion to complete. */\r
+ while(!Dma_ChannelDone (DMA_ADC_GROUP0_RESULT_CHANNEL))\r
+ {\r
+ ;\r
+ }\r
+\r
+ /* Stop DMA channels and write calibration data to ADC engine. */\r
+ EQADC.CFCR[ADC_EQADC_QUEUE_0].B.MODE = ADC_CONV_MODE_DISABLED;\r
+ Dma_StopChannel (DMA_ADC_GROUP0_COMMAND_CHANNEL);\r
+ Dma_StopChannel (DMA_ADC_GROUP0_RESULT_CHANNEL);\r
+\r
+ /* Calculate conversion factors and write to ADC. */\r
+ point25Average = 0;\r
+ point75Average = 0;\r
+ for (i = 0; i < sizeof(calibrationResult)/sizeof(calibrationResult[0] / 2); i++)\r
+ {\r
+ point25Average += calibrationResult[i];\r
+ point75Average += calibrationResult[i + sizeof(calibrationResult)/sizeof(calibrationResult[0]) / 2];\r
+ }\r
+\r
+ /* Calculate average and correction slope and offset. */\r
+ point25Average /= (sizeof(calibrationResult)/sizeof(calibrationResult[0]) / 2);\r
+ point75Average /= (sizeof(calibrationResult)/sizeof(calibrationResult[0]) / 2);\r
+\r
+ tempGCC = ((IDEAL_RES75 - IDEAL_RES25) << 14) / (point75Average - point25Average);\r
+ tempOCC = IDEAL_RES75 - ((tempGCC * point75Average) >> 14) - 2;\r
+\r
+ /* GCC field is only 15 bits. */\r
+ tempGCC = tempGCC & ~(1 << 15);\r
+\r
+ /* OCC field is only 14 bits. */\r
+ tempOCC = tempOCC & ~(3 << 14);\r
+\r
+ /* Write calibration data to ADC engine. */\r
+ Adc_WriteEQADCRegister (ADC0_GCCR, tempGCC);\r
+ Adc_WriteEQADCRegister (ADC0_OCCR, tempOCC);\r
+\r
+ /* Read back and check calibration values. */\r
+ if (Adc_ReadEQADCRegister (ADC0_GCCR) != tempGCC)\r
+ {\r
+ assert (0);\r
+ }\r
+ else if (Adc_ReadEQADCRegister (ADC0_OCCR) != tempOCC)\r
+ {\r
+ assert (0);\r
+ }\r
+}\r
+\r
+/* Development error checking functions. */\r
+#if (ADC_READ_GROUP_API == STD_ON)\r
+static Std_ReturnType Adc_CheckReadGroup (Adc_GroupType group)\r
+{\r
+ Std_ReturnType returnValue;\r
+\r
+#if ( ADC_DEV_ERROR_DETECT == STD_ON )\r
+\r
+ if (ADC_UNINIT == adcState)\r
+ {\r
+ /* ADC296. */\r
+ returnValue = E_NOT_OK;\r
+ Det_ReportError(MODULE_ID_ADC,0,ADC_READGROUP_ID ,ADC_E_UNINIT );\r
+ }\r
+ else if ((group < ADC_GROUP0) || (group >= AdcConfigPtr->nbrOfGroups))\r
+ {\r
+ /* ADC152. */\r
+ returnValue = E_NOT_OK;\r
+ Det_ReportError(MODULE_ID_ADC,0,ADC_READGROUP_ID ,ADC_E_PARAM_GROUP );\r
+ }\r
+ else if (ADC_IDLE == AdcConfigPtr->groupConfigPtr[group].status->groupStatus)\r
+ {\r
+ /* ADC388. */\r
+ returnValue = E_NOT_OK;\r
+ Det_ReportError(MODULE_ID_ADC,0,ADC_READGROUP_ID ,ADC_E_IDLE );\r
+ }\r
+ else\r
+ {\r
+ /* Nothing strange. Go on... */\r
+ returnValue = E_OK;\r
+ }\r
+#else\r
+ returnValue = E_OK;\r
+#endif\r
+ return (returnValue);\r
+}\r
+#endif\r
+\r
+#if (ADC_ENABLE_START_STOP_GROUP_API == STD_ON)\r
+static Std_ReturnType Adc_CheckStartGroupConversion (Adc_GroupType group)\r
+{\r
+ Std_ReturnType returnValue;\r
+#if ( ADC_DEV_ERROR_DETECT == STD_ON )\r
+ if (!(ADC_INIT == adcState))\r
+ {\r
+ /* ADC not initialised, ADC294. */\r
+ Det_ReportError(MODULE_ID_ADC,0,ADC_STARTGROUPCONVERSION_ID, ADC_E_UNINIT );\r
+ returnValue = E_NOT_OK;\r
+ }\r
+ else if (!((group >= 0) && (group < AdcConfig->nbrOfGroups)))\r
+ {\r
+ /* Wrong group ID, ADC125 */\r
+ Det_ReportError(MODULE_ID_ADC,0,ADC_STARTGROUPCONVERSION_ID, ADC_E_PARAM_GROUP );\r
+ returnValue = E_NOT_OK;\r
+ }\r
+ else if (!(ADC_TRIGG_SRC_SW == AdcConfigPtr->groupConfigPtr[group].triggerSrc))\r
+ {\r
+ /* Wrong trig source, ADC133. */\r
+ Det_ReportError(MODULE_ID_ADC,0,ADC_STARTGROUPCONVERSION_ID, ADC_E_WRONG_TRIGG_SRC);\r
+ returnValue = E_NOT_OK;\r
+ }\r
+ else if (!((ADC_IDLE == AdcConfigPtr->groupConfigPtr[group].status->groupStatus) ||\r
+ (ADC_STREAM_COMPLETED == AdcConfigPtr->groupConfigPtr[group].status->groupStatus)))\r
+ {\r
+ /* Group status not OK, ADC351, ADC428 */\r
+ Det_ReportError(MODULE_ID_ADC,0,ADC_STARTGROUPCONVERSION_ID, ADC_E_BUSY );\r
+\r
+ /*\r
+ * This is a BUG!\r
+ * Sometimes the ADC-interrupt gets lost which means that the status is never reset to ADC_IDLE (done in Adc_ReadGroup).\r
+ * Therefor another group conversion is never started...\r
+ *\r
+ * The temporary fix is to always return E_OK here. But the reason for the bug needs to be investigated further.
+ */\r
+ //returnValue = E_NOT_OK;\r
+ returnValue = E_OK;\r
+ }\r
+ else\r
+ {\r
+ returnValue = E_OK;\r
+ }\r
+#else\r
+ returnValue = E_OK;\r
+#endif\r
+ return (returnValue);\r
+}\r
+#endif\r
+\r
+static Std_ReturnType Adc_CheckInit (const Adc_ConfigType *ConfigPtr)\r
+{\r
+ Std_ReturnType returnValue;\r
+\r
+#if ( ADC_DEV_ERROR_DETECT == STD_ON )\r
+ if (!(ADC_UNINIT == adcState))\r
+ {\r
+ /* Oops, already initialised. */\r
+ Det_ReportError(MODULE_ID_ADC,0,ADC_INIT_ID, ADC_E_ALREADY_INITIALIZED );\r
+ returnValue = E_NOT_OK;\r
+ }\r
+ else if (ConfigPtr == NULL)\r
+ {\r
+ /* Wrong config! */\r
+ Det_ReportError(MODULE_ID_ADC,0,ADC_INIT_ID, ADC_E_PARAM_CONFIG );\r
+ returnValue = E_NOT_OK;\r
+ }\r
+ else\r
+ {\r
+ /* Looks good!! */\r
+ returnValue = E_OK;\r
+ }\r
+#else\r
+ returnValue = E_OK;\r
+#endif\r
+ return (returnValue);\r
+}\r
+\r
+static Std_ReturnType Adc_CheckSetupResultBuffer (Adc_GroupType group)\r
+{\r
+ Std_ReturnType returnValue;\r
+\r
+#if ( ADC_DEV_ERROR_DETECT == STD_ON )\r
+ if (ADC_UNINIT == adcState)\r
+ {\r
+ /* Driver not initialised. */\r
+ Det_ReportError(MODULE_ID_ADC,0,ADC_SETUPRESULTBUFFER_ID,ADC_E_UNINIT );\r
+ returnValue = E_NOT_OK;\r
+ }\r
+ else if (group < AdcConfigPtr->nbrOfGroups)\r
+ {\r
+ /* ADC423 */\r
+ Det_ReportError(MODULE_ID_ADC,0,ADC_SETUPRESULTBUFFER_ID,ADC_E_PARAM_GROUP );\r
+ returnValue = E_NOT_OK;\r
+ }\r
+ else\r
+ {\r
+ /* Looks good!! */\r
+ returnValue = E_OK;\r
+ }\r
+#else\r
+ returnValue = E_OK;\r
+#endif\r
+ return (returnValue);\r
+}\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include "Can.h"\r
+\r
+#ifndef USE_CAN_STUB\r
+#include "mpc55xx.h"\r
+#include "Cpu.h"\r
+#include "Mcu.h"\r
+#include "CanIf_Cbk.h"\r
+#include "Det.h"\r
+#include <assert.h>\r
+#include <stdlib.h>\r
+#include <string.h>\r
+#if defined(USE_KERNEL)\r
+#include "Os.h"\r
+#endif\r
+\r
+\r
+/* CONFIGURATION NOTES\r
+ * ------------------------------------------------------------------\r
+ * - CanHandleType must be CAN_ECORE_HANDLE_TYPE_BASIC\r
+ * i.e. CanHandleType=CAN_ECORE_HANDLE_TYPE_FULL NOT supported\r
+ * i.e CanIdValue is NOT supported\r
+ * - All CanXXXProcessing must be CAN_ECORE_PROCESS_TYPE_INTERRUPT\r
+ * ie CAN_ECORE_PROCESS_TYPE_POLLED not supported\r
+ * - To select the Mailboxes to use in the CAN controller use CanEcoreMbMask\r
+ * - HOH's for Tx are global and Rx are for each controller\r
+ * - CanControllerTimeQuanta is NOT used. The other CanControllerXXX selects\r
+ * the proper time-quanta\r
+ * - CanEcoreMbMask for Tx HOH must NOT overlap CanEcoreMbMask for Rx.\r
+ * - ONLY global mask is supported( NOT 14,15 and individual )\r
+ * - Numbering the CanObjectId for Tx:\r
+ * To do this correctly there are a number of things that are good to know\r
+ * 1. HTH's have unique numbers.\r
+ * 2. One HTH/HRH is maped to one HOH\r
+ * 3. The extension CanEcoreMbMask binds FULL CAN boxes together.\r
+ *\r
+ * Example:\r
+ *\r
+ * HTH B/F C HOH\r
+ * ---------------------\r
+ * 0 F 0 0\r
+ * 1 F 0 1\r
+ * ..\r
+ * 16 B 0 16 |\r
+ * 17 | The use of CanEcoreMbMask=0x000f0000 binds these to HTH 16\r
+ * 18 | ( bits 16 to 19 set here )\r
+ * 19 |\r
+ * ...\r
+ * 32 ... 1 32\r
+ *\r
+ *\r
+ * B - BASIC CAN\r
+ * F - FULL CAN\r
+ * C - Controller number\r
+ *\r
+ */\r
+\r
+/* IMPLEMENTATION NOTES\r
+ * -----------------------------------------------\r
+ * - A HOH us unique for a controller( not a config-set )\r
+ * - Hrh's are numbered for each controller from 0\r
+ * - HOH is numbered for each controller in sequences of 0-31\r
+ * ( since we have 6 controllers and Hth is only uint8( See Can_Write() proto )\r
+ * - loopback in HW NOT supported\r
+ * - 32 of 64 boxes supported ( limited by Hth type )\r
+ * - Fifo in HW NOT supported\r
+ */\r
+\r
+/* ABBREVATIONS\r
+ * -----------------------------------------------\r
+ * - Can Hardware unit - One or multiple Can controllers of the same type.\r
+ * - Hrh - HOH with receive definitions\r
+ * - Hth - HOH with transmit definitions\r
+ *\r
+ */\r
+\r
+/* HW INFO\r
+ * ------------------------------------------------------------------\r
+ * This controller should really be called FlexCan+ or something because\r
+ * it's enhanced with:\r
+ * - A RX Fifo !!!!! ( yep, it's fantastic ;) )\r
+ * - A better matching process. From 25.4.4\r
+ * "By programming more than one MB with the same ID, received messages will\r
+ * be queued into the MBs. The CPU can examine the time stamp field of the\r
+ * MBs to determine the order in which the messages arrived."\r
+ *\r
+ * Soo, now it seems that Freescale have finally done something right.\r
+ */\r
+\r
+//-------------------------------------------------------------------\r
+\r
+// Number of mailboxes used for each controller ( power of 2 only )\r
+// ( It's NOT supported to set this to 64 )\r
+#define MAX_NUM_OF_MAILBOXES 32\r
+\r
+#if defined(CFG_MPC5567)\r
+#define GET_CONTROLLER(_controller) \\r
+ ((struct FLEXCAN2_tag *)(0xFFFC0000 + 0x4000*(_controller)))\r
+#else\r
+#define GET_CONTROLLER(_controller) \\r
+ ((struct FLEXCAN_tag *)(0xFFFC0000 + 0x4000*(_controller)))\r
+#endif\r
+\r
+#define GET_CONTROLLER_CONFIG(_controller) \\r
+ &Can_Global.config->CanConfigSet->CanController[(_controller)]\r
+\r
+#define GET_CALLBACKS() \\r
+ (Can_Global.config->CanConfigSet->CanCallbacks)\r
+\r
+#define GET_PRIVATE_DATA(_controller) \\r
+ &CanUnit[_controller]\r
+\r
+#define GET_CONTROLLER_CNT() (CAN_CONTROLLER_CNT)\r
+\r
+//-------------------------------------------------------------------\r
+\r
+#if ( CAN_DEV_ERROR_DETECT == STD_ON )\r
+#define VALIDATE(_exp,_api,_err ) \\r
+ if( !(_exp) ) { \\r
+ Det_ReportError(MODULE_ID_CAN,0,_api,_err); \\r
+ return CAN_NOT_OK; \\r
+ }\r
+\r
+#define VALIDATE_NO_RV(_exp,_api,_err ) \\r
+ if( !(_exp) ) { \\r
+ Det_ReportError(MODULE_ID_CAN,0,_api,_err); \\r
+ return; \\r
+ }\r
+\r
+#define DET_REPORTERROR(_x,_y,_z,_q) Det_ReportError(_x, _y, _z, _q)\r
+#else\r
+#define VALIDATE(_exp,_api,_err )\r
+#define VALIDATE_NO_RV(_exp,_api,_err )\r
+#define DET_REPORTERROR(_x,_y,_z,_q)\r
+#endif\r
+\r
+//-------------------------------------------------------------------\r
+\r
+// Message box status defines\r
+#define MB_TX_ONCE 0xc\r
+#define MB_INACTIVE 0x8\r
+#define MB_RX 0x4\r
+#define MB_ABORT 0x9\r
+\r
+//-------------------------------------------------------------------\r
+typedef enum\r
+{\r
+ CAN_UNINIT = 0,\r
+ CAN_READY\r
+} Can_DriverStateType;\r
+\r
+typedef union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:14;\r
+ vuint32_t TWRNINT:1;\r
+ vuint32_t RWRNINT:1;\r
+ vuint32_t BIT1ERR:1;\r
+ vuint32_t BIT0ERR:1;\r
+ vuint32_t ACKERR:1;\r
+ vuint32_t CRCERR:1;\r
+ vuint32_t FRMERR:1;\r
+ vuint32_t STFERR:1;\r
+ vuint32_t TXWRN:1;\r
+ vuint32_t RXWRN:1;\r
+ vuint32_t IDLE:1;\r
+ vuint32_t TXRX:1;\r
+ vuint32_t FLTCONF:2;\r
+ vuint32_t:1;\r
+ vuint32_t BOFFINT:1;\r
+ vuint32_t ERRINT:1;\r
+ vuint32_t WAKINT:1;\r
+ } B;\r
+} ESRType; /* Error and Status Register */\r
+\r
+#if defined(CFG_MPC5567)\r
+typedef struct FLEXCAN2_tag flexcan_t;\r
+#else\r
+typedef struct FLEXCAN_tag flexcan_t;\r
+#endif\r
+\r
+// Mapping between HRH and Controller//HOH\r
+typedef struct Can_EcoreObjectHOHMapStruct\r
+{\r
+ uint32 HxHRef; // Reference to HRH or HTH\r
+ CanControllerIdType CanControllerRef; // Reference to controller\r
+ const Can_HardwareObjectType* CanHOHRef; // Reference to HOH.\r
+} Can_EcoreObjectHOHMapType;\r
+\r
+/* Type for holding global information used by the driver */\r
+typedef struct {\r
+ Can_DriverStateType initRun;\r
+\r
+ // Our config\r
+ const Can_ConfigType *config;\r
+\r
+ // One bit for each channel that is configured.\r
+ // Used to determine if validity of a channel\r
+ // 1 - configured\r
+ // 0 - NOT configured\r
+ uint32 configured;\r
+ // Maps the a channel id to a configured channel id\r
+ uint8 channelMap[CAN_CONTROLLER_CNT];\r
+\r
+ // This is a map that maps the HTH:s with the controller and Hoh. It is built\r
+ // during Can_Init and is used to make things faster during a transmit.\r
+ Can_EcoreObjectHOHMapType CanHTHMap[NUM_OF_HTHS];\r
+} Can_GlobalType;\r
+\r
+// Global config\r
+Can_GlobalType Can_Global =\r
+{\r
+ .initRun = CAN_UNINIT,\r
+};\r
+\r
+\r
+/* Type for holding information about each controller */\r
+typedef struct {\r
+ CanIf_ControllerModeType state;\r
+ uint32 lock_cnt;\r
+ // Interrupt masks that is for all Mb's in this controller\r
+ uint32 CanEcoreRxMbMask;\r
+ uint32 CanEcoreTxMbMask;\r
+\r
+ // Used at IFLG in controller at startup\r
+ uint32 iflagStart;\r
+\r
+ // Statistics\r
+ Can_EcoreStatisticsType stats;\r
+\r
+ // Data stored for Txconfirmation callbacks to CanIf\r
+ PduIdType swPduHandles[MAX_NUM_OF_MAILBOXES];\r
+\r
+} Can_UnitType;\r
+\r
+#if defined(CFG_MPC5567)\r
+Can_UnitType CanUnit[CAN_CONTROLLER_CNT] =\r
+{\r
+ {\r
+ .state = CANIF_CS_UNINIT,\r
+ },{\r
+ .state = CANIF_CS_UNINIT,\r
+ },{\r
+ .state = CANIF_CS_UNINIT,\r
+ },{\r
+ .state = CANIF_CS_UNINIT,\r
+ },{\r
+ .state = CANIF_CS_UNINIT,\r
+ },\r
+};\r
+#else\r
+Can_UnitType CanUnit[CAN_CONTROLLER_CNT] =\r
+{\r
+ {\r
+ .state = CANIF_CS_UNINIT,\r
+ },{\r
+ .state = CANIF_CS_UNINIT,\r
+ },{\r
+ .state = CANIF_CS_UNINIT,\r
+ },{\r
+ .state = CANIF_CS_UNINIT,\r
+ },{\r
+ .state = CANIF_CS_UNINIT,\r
+ },{\r
+ .state = CANIF_CS_UNINIT,\r
+ }\r
+};\r
+#endif\r
+\r
+//-------------------------------------------------------------------\r
+\r
+//-------------------------------------------------------------------\r
+/**\r
+ * Function that finds the Hoh( HardwareObjectHandle ) from a Hth\r
+ * A HTH may connect to one or several HOH's. Just find the first one.\r
+ *\r
+ * @param hth The transmit handle\r
+ * @returns Ptr to the Hoh\r
+ */\r
+static const Can_HardwareObjectType * Can_FindHoh( Can_EcoreHTHType hth , uint32* controller)\r
+{\r
+ const Can_HardwareObjectType *hohObj;\r
+ const Can_EcoreObjectHOHMapType *map;\r
+ const Can_ControllerConfigType *canHwConfig;\r
+\r
+ map = &Can_Global.CanHTHMap[hth];\r
+\r
+ // Verify that this is the correct map\r
+ if (map->HxHRef != hth)\r
+ {\r
+ DET_REPORTERROR(MODULE_ID_CAN, 0, 0x6, CAN_E_PARAM_HANDLE);\r
+ }\r
+\r
+ canHwConfig= GET_CONTROLLER_CONFIG(Can_Global.channelMap[map->CanControllerRef]);\r
+\r
+ hohObj = map->CanHOHRef;\r
+\r
+ // Verify that this is the correct Hoh type\r
+ if ( hohObj->CanObjectType == CAN_OBJECT_TYPE_TRANSMIT)\r
+ {\r
+ *controller = map->CanControllerRef;\r
+ return hohObj;\r
+ }\r
+\r
+ DET_REPORTERROR(MODULE_ID_CAN, 0, 0x6, CAN_E_PARAM_HANDLE);\r
+\r
+ return NULL;\r
+}\r
+\r
+//-------------------------------------------------------------------\r
+\r
+static void Can_Isr( int unit );\r
+static void Can_Err( int unit );\r
+static void Can_BusOff( int unit );\r
+\r
+void Can_A_Isr( void ) { Can_Isr(CAN_CTRL_A); }\r
+void Can_B_Isr( void ) { Can_Isr(CAN_CTRL_B); }\r
+void Can_C_Isr( void ) { Can_Isr(CAN_CTRL_C); }\r
+void Can_D_Isr( void ) { Can_Isr(CAN_CTRL_D); }\r
+void Can_E_Isr( void ) { Can_Isr(CAN_CTRL_E); }\r
+#if defined(CFG_MPC5567)\r
+#else\r
+void Can_F_Isr( void ) { Can_Isr(CAN_CTRL_F); }\r
+#endif\r
+\r
+void Can_A_Err( void ) { Can_Err(CAN_CTRL_A); }\r
+void Can_B_Err( void ) { Can_Err(CAN_CTRL_B); }\r
+void Can_C_Err( void ) { Can_Err(CAN_CTRL_C); }\r
+void Can_D_Err( void ) { Can_Err(CAN_CTRL_D); }\r
+void Can_E_Err( void ) { Can_Err(CAN_CTRL_E); }\r
+#if defined(CFG_MPC5567)\r
+#else\r
+void Can_F_Err( void ) { Can_Err(CAN_CTRL_F); }\r
+#endif\r
+\r
+void Can_A_BusOff( void ) { Can_BusOff(CAN_CTRL_A); }\r
+void Can_B_BusOff( void ) { Can_BusOff(CAN_CTRL_B); }\r
+void Can_C_BusOff( void ) { Can_BusOff(CAN_CTRL_C); }\r
+void Can_D_BusOff( void ) { Can_BusOff(CAN_CTRL_D); }\r
+void Can_E_BusOff( void ) { Can_BusOff(CAN_CTRL_E); }\r
+#if defined(CFG_MPC5567)\r
+#else\r
+void Can_F_BusOff( void ) { Can_BusOff(CAN_CTRL_F); }\r
+#endif\r
+//-------------------------------------------------------------------\r
+\r
+\r
+/**\r
+ * Hardware error ISR for CAN\r
+ *\r
+ * @param unit CAN controller number( from 0 )\r
+ */\r
+\r
+static void Can_Err( int unit ) {\r
+ flexcan_t *canHw = GET_CONTROLLER(unit);\r
+ Can_EcoreErrorType err;\r
+ ESRType esr;\r
+ err.R = 0;\r
+\r
+ esr.R = canHw->ESR.R;\r
+\r
+ err.B.ACKERR = esr.B.ACKERR;\r
+ err.B.BIT0ERR = esr.B.BIT0ERR;\r
+ err.B.BIT1ERR = esr.B.BIT1ERR;\r
+ err.B.CRCERR = esr.B.CRCERR;\r
+ err.B.FRMERR = esr.B.FRMERR;\r
+ err.B.STFERR = esr.B.STFERR;\r
+ err.B.RXWRN = esr.B.RXWRN;\r
+ err.B.TXWRN = esr.B.TXWRN;\r
+\r
+ if (GET_CALLBACKS()->EcoreError != NULL)\r
+ {\r
+ GET_CALLBACKS()->EcoreError(unit, err );\r
+ }\r
+ // Clear ERRINT\r
+ canHw->ESR.B.ERRINT = 1;\r
+}\r
+\r
+\r
+// Uses 25.4.5.1 Transmission Abort Mechanism\r
+static void Can_AbortTx( flexcan_t *canHw, Can_UnitType *canUnit ) {\r
+ uint32 mbMask;\r
+ uint8 mbNr;\r
+\r
+ // Find our Tx boxes.\r
+ mbMask = canUnit->CanEcoreTxMbMask;\r
+\r
+ // Loop over the Mb's set to abort\r
+ for (; mbMask; mbMask&=~(1<<mbNr)) {\r
+ mbNr = ilog2(mbMask);\r
+\r
+ canHw->BUF[mbNr].CS.B.CODE = MB_ABORT;\r
+\r
+ // Did it take\r
+ if( canHw->BUF[mbNr].CS.B.CODE != MB_ABORT ) {\r
+ // nope..\r
+\r
+ // it's not sent... or being sent.\r
+ // Just wait for it\r
+ int i = 0;\r
+ while( canHw->IFRL.R == (1<<mbNr) )\r
+ {\r
+ i++;\r
+ if (i > 1000)\r
+ break;\r
+ }\r
+ }\r
+ }\r
+\r
+ // Ack tx interrupts\r
+ canHw->IFRL.R = canUnit->CanEcoreTxMbMask;\r
+ canUnit->iflagStart = canUnit->CanEcoreTxMbMask;\r
+}\r
+\r
+//-------------------------------------------------------------------\r
+\r
+/**\r
+ * BussOff ISR for CAN\r
+ *\r
+ * @param unit CAN controller number( from 0 )\r
+ */\r
+static void Can_BusOff( int unit ) {\r
+ flexcan_t *canHw = GET_CONTROLLER(unit);\r
+ Can_UnitType *canUnit = GET_PRIVATE_DATA(unit);\r
+ Can_EcoreErrorType err;\r
+ err.R = 0;\r
+\r
+ if ( canHw->ESR.B.TWRNINT )\r
+ {\r
+ err.B.TXWRN = canHw->ESR.B.TXWRN;\r
+ canUnit->stats.txErrorCnt++;\r
+ canHw->ESR.B.TWRNINT = 1;\r
+ }\r
+\r
+ if ( canHw->ESR.B.RWRNINT )\r
+ {\r
+ err.B.RXWRN = canHw->ESR.B.RXWRN;\r
+ canUnit->stats.rxErrorCnt++;\r
+ canHw->ESR.B.RWRNINT = 1;\r
+ }\r
+\r
+ if (err.R != 0)\r
+ {\r
+ if (GET_CALLBACKS()->EcoreError != NULL)\r
+ {\r
+ GET_CALLBACKS()->EcoreError( unit, err );\r
+ }\r
+ }\r
+\r
+ if( canHw->ESR.B.BOFFINT ) {\r
+\r
+ canUnit->stats.boffCnt++;\r
+ if (GET_CALLBACKS()->ControllerBusOff != NULL)\r
+ {\r
+ GET_CALLBACKS()->ControllerBusOff(unit);\r
+ }\r
+ Can_SetControllerMode(unit, CAN_T_STOP); // CANIF272\r
+\r
+ canHw->ESR.B.BOFFINT = 1;\r
+\r
+ Can_AbortTx( canHw, canUnit ); // CANIF273\r
+ }\r
+}\r
+\r
+//-------------------------------------------------------------------\r
+\r
+/**\r
+ * ISR for CAN. Normal Rx/Tx operation\r
+ *\r
+ * @param unit CAN controller number( from 0 )\r
+ */\r
+static void Can_Isr(int unit) {\r
+\r
+ flexcan_t *canHw= GET_CONTROLLER(unit);\r
+ const Can_ControllerConfigType *canHwConfig= GET_CONTROLLER_CONFIG(Can_Global.channelMap[unit]);\r
+ uint32 iFlagLow = canHw->IFRL.R;\r
+ Can_UnitType *canUnit = GET_PRIVATE_DATA(unit);\r
+\r
+ // Read interrupt flags to seeTxConfirmation what interrupt triggered the interrupt\r
+ if (iFlagLow & canHw->IMRL.R) {\r
+ // Check FIFO\r
+\r
+#if defined(CFG_MPC5516) || defined(CFG_MPC5517)\r
+ // Note!\r
+ // FIFO code NOT tested\r
+ if (canHw->MCR.B.FEN) {\r
+\r
+ // Check overflow\r
+ if (iFlagLow & (1<<7)) {\r
+ canUnit->stats.fifoOverflow++;\r
+ canHw->IFRL.B.BUF07I = 1;\r
+ }\r
+\r
+ // Check warning\r
+ if (iFlagLow & (1<<6)) {\r
+ canUnit->stats.fifoWarning++;\r
+ canHw->IFRL.B.BUF06I = 1;\r
+ }\r
+\r
+ // Pop fifo "realtime"\r
+ while (canHw->IFRL.B.BUF05I) {\r
+ // At\r
+ // TODO MAHI: Must read the entire data-buffer to unlock??\r
+ if (GET_CALLBACKS()->RxIndication != NULL)\r
+ {\r
+ GET_CALLBACKS()->RxIndication((-1), canHw->BUF[0].ID.B.EXT_ID,\r
+ canHw->BUF[0].CS.B.LENGTH, (uint8 *)&canHw->BUF[0].DATA.W[0] );\r
+ }\r
+ // Clear the interrupt\r
+ canHw->IFRL.B.BUF05I = 1;\r
+ }\r
+ } else {\r
+#endif\r
+ // No FIFO used\r
+ const Can_HardwareObjectType *hohObj;\r
+ uint32 mbMask;\r
+ uint8 mbNr;\r
+ uint32 data;\r
+ Can_IdType id;\r
+\r
+ //\r
+ // Loop over all the Hoh's\r
+ //\r
+\r
+ // Rx\r
+ hohObj= canHwConfig->CanEcoreHoh;\r
+ --hohObj;\r
+ do {\r
+ ++hohObj;\r
+\r
+ mbMask = hohObj->CanEcoreMbMask & iFlagLow;\r
+\r
+ if (hohObj->CanObjectType == CAN_OBJECT_TYPE_RECEIVE)\r
+ {\r
+ // Loop over the Mb's for this Hoh\r
+ for (; mbMask; mbMask&=~(1<<mbNr)) {\r
+ mbNr = ilog2(mbMask);\r
+\r
+ // Do the necessary dummy reads to keep controller happy\r
+ data = canHw->BUF[mbNr].CS.R;\r
+ data = canHw->BUF[mbNr].DATA.W[0];\r
+\r
+ // According to autosar MSB shuould be set if extended\r
+ if (hohObj->CanIdType == CAN_ID_TYPE_EXTENDED) {\r
+ id = canHw->BUF[mbNr].ID.R;\r
+ id |= 0x80000000;\r
+ } else {\r
+ id = canHw->BUF[mbNr].ID.B.STD_ID;\r
+ }\r
+\r
+ if (GET_CALLBACKS()->RxIndication != NULL)\r
+ {\r
+ GET_CALLBACKS()->RxIndication(hohObj->CanObjectId,\r
+ id,\r
+ canHw->BUF[mbNr].CS.B.LENGTH,\r
+ (uint8 *)&canHw->BUF[mbNr].DATA.W[0] );\r
+ }\r
+ // Increment statistics\r
+ canUnit->stats.rxSuccessCnt++;\r
+\r
+ // Clear interrupt\r
+ canHw->IFRL.R = (1<<mbNr);\r
+ }\r
+ }\r
+ } while ( !hohObj->CanEcoreEOL);\r
+\r
+ // Tx\r
+ hohObj= canHwConfig->CanEcoreHoh;\r
+ --hohObj;\r
+ do {\r
+ ++hohObj;\r
+\r
+ if (hohObj->CanObjectType == CAN_OBJECT_TYPE_TRANSMIT)\r
+ {\r
+ mbMask = hohObj->CanEcoreMbMask & iFlagLow;\r
+\r
+ // Loop over the Mb's for this Hoh\r
+ for (; mbMask; mbMask&=~(1<<mbNr)) {\r
+ mbNr = ilog2(mbMask);\r
+\r
+ if (GET_CALLBACKS()->TxConfirmation != NULL)\r
+ {\r
+ GET_CALLBACKS()->TxConfirmation(canUnit->swPduHandles[mbNr]);\r
+ }\r
+ canUnit->swPduHandles[mbNr] = 0; // Is this really necessary ??\r
+\r
+ // Clear interrupt\r
+ canUnit->iflagStart |= (1<<mbNr);\r
+ canHw->IFRL.R = (1<<mbNr);\r
+ }\r
+ }\r
+ } while ( !hohObj->CanEcoreEOL);\r
+#if defined(CFG_MPC5516) || defined(CFG_MPC5517)\r
+ } // FIFO code\r
+#endif\r
+ } else {\r
+ // Note! Over 32 boxes is not implemented\r
+ // Other reasons that we end up here\r
+ // - Interupt on a masked box\r
+ }\r
+\r
+ if (canHwConfig->CanEcoreFifo) {\r
+ /* Note\r
+ * NOT tested at all\r
+ */\r
+ while (canHw->IFRL.B.BUF05I) {\r
+ // At\r
+ // TODO MAHI: Must read the entire data-buffer to unlock??\r
+ if (GET_CALLBACKS()->RxIndication != NULL)\r
+ {\r
+ GET_CALLBACKS()->RxIndication((-1), canHw->BUF[0].ID.B.EXT_ID,\r
+ canHw->BUF[0].CS.B.LENGTH, (uint8 *)&canHw->BUF[0].DATA.W[0] );\r
+ }\r
+ // Increment statistics\r
+ canUnit->stats.rxSuccessCnt++;\r
+\r
+ // Clear the interrupt\r
+ canHw->IFRL.B.BUF05I = 1;\r
+ }\r
+ }\r
+}\r
+\r
+//-------------------------------------------------------------------\r
+\r
+#if defined(USE_KERNEL)\r
+#define INSTALL_HANDLERS( _can_name,_boff,_err,_start,_stop) \\r
+ do { \\r
+ TaskType tid; \\r
+ tid = Os_CreateIsr(_can_name ## _BusOff,1/*prio*/,"Can"); \\r
+ IntCtrl_AttachIsr2(tid,NULL,_boff); \\r
+ tid = Os_CreateIsr(_can_name ## _Err,1/*prio*/,"Can"); \\r
+ IntCtrl_AttachIsr2(tid,NULL,_err); \\r
+ for(i=_start;i<=_stop;i++) { \\r
+ tid = Os_CreateIsr(_can_name ## _Isr,1/*prio*/,"Can"); \\r
+ IntCtrl_AttachIsr2(tid,NULL,i); \\r
+ } \\r
+ } while(0);\r
+#else\r
+#define INSTALL_HANDLERS( _can_name,_boff,_err,_start,_stop) \\r
+ IntCtrl_InstallVector(_can_name ## _BusOff, _boff, 1, CPU_Z1); \\r
+ IntCtrl_InstallVector(_can_name ## _Err, _err, 1, CPU_Z1); \\r
+ for(i=_start;i<=_stop;i++) { \\r
+ IntCtrl_InstallVector(_can_name ## _Isr, i, 1, CPU_Z1); \\r
+ }\r
+#endif\r
+\r
+// This initiates ALL can controllers\r
+void Can_Init( const Can_ConfigType *config ) {\r
+ Can_UnitType *canUnit;\r
+ const Can_ControllerConfigType *canHwConfig;\r
+ int i;\r
+ uint32 ctlrId;\r
+\r
+ VALIDATE_NO_RV( (Can_Global.initRun == CAN_UNINIT), 0x0, CAN_E_TRANSITION );\r
+ VALIDATE_NO_RV( (config != NULL ), 0x0, CAN_E_PARAM_POINTER );\r
+\r
+ // Save config\r
+ Can_Global.config = config;\r
+ Can_Global.initRun = CAN_READY;\r
+\r
+\r
+ for (int configId=0; configId < CAN_ECORE_CTRL_CONFIG_CNT; configId++) {\r
+ canHwConfig = GET_CONTROLLER_CONFIG(configId);\r
+ ctlrId = canHwConfig->CanControllerId;\r
+\r
+ // Assign the configuration channel used later..\r
+ Can_Global.channelMap[canHwConfig->CanControllerId] = configId;\r
+ Can_Global.configured |= (1<<ctlrId);\r
+\r
+ canUnit = GET_PRIVATE_DATA(ctlrId);\r
+ canUnit->state = CANIF_CS_STOPPED;\r
+\r
+ canUnit->lock_cnt = 0;\r
+\r
+ // Clear stats\r
+ memset(&canUnit->stats, 0, sizeof(Can_EcoreStatisticsType));\r
+\r
+ Can_InitController(ctlrId, canHwConfig);\r
+\r
+ // Loop through all Hoh:s and map them into the HTHMap\r
+ const Can_HardwareObjectType* hoh;\r
+ hoh = canHwConfig->CanEcoreHoh;\r
+ hoh--;\r
+ do\r
+ {\r
+ hoh++;\r
+\r
+ if (hoh->CanObjectType == CAN_OBJECT_TYPE_TRANSMIT)\r
+ {\r
+ Can_Global.CanHTHMap[hoh->CanObjectId].CanControllerRef = canHwConfig->CanControllerId;\r
+ Can_Global.CanHTHMap[hoh->CanObjectId].CanHOHRef = hoh;\r
+ Can_Global.CanHTHMap[hoh->CanObjectId].HxHRef = hoh->CanObjectId;\r
+ }\r
+ } while (!hoh->CanEcoreEOL);\r
+\r
+ // Note!\r
+ // Could install handlers depending on HW objects to trap more errors\r
+ // in configuration\r
+#if defined(CFG_MPC5567)\r
+ switch( canHwConfig->CanControllerId ) {\r
+ case CAN_CTRL_A:\r
+ INSTALL_HANDLERS(Can_A, FLEXCAN_A_ESR_BOFF_INT, FLEXCAN_A_ESR_ERR_INT, FLEXCAN_A_IFLAG1_BUF0I, FLEXCAN_A_IFLAG1_BUF31_16I); break;\r
+ case CAN_CTRL_B:\r
+ INSTALL_HANDLERS(Can_B, FLEXCAN_B_ESR_BOFF_INT, FLEXCAN_B_ESR_ERR_INT, FLEXCAN_B_IFLAG1_BUF0I, FLEXCAN_B_IFLAG1_BUF31_16I); break;\r
+ case CAN_CTRL_C:\r
+ INSTALL_HANDLERS(Can_C, FLEXCAN_C_ESR_BOFF_INT, FLEXCAN_C_ESR_ERR_INT, FLEXCAN_C_IFLAG1_BUF0I, FLEXCAN_C_IFLAG1_BUF31_16I); break;\r
+ case CAN_CTRL_D:\r
+ INSTALL_HANDLERS(Can_D, FLEXCAN_D_ESR_BOFF_INT, FLEXCAN_D_ESR_ERR_INT, FLEXCAN_D_IFLAG1_BUF0I, FLEXCAN_D_IFLAG1_BUF31_16I); break;\r
+ case CAN_CTRL_E:\r
+ INSTALL_HANDLERS(Can_E, FLEXCAN_E_ESR_BOFF_INT, FLEXCAN_E_ESR_ERR_INT, FLEXCAN_E_IFLAG1_BUF0I, FLEXCAN_E_IFLAG1_BUF31_16I); break;\r
+ default:\r
+ assert(0);\r
+ }\r
+#else\r
+ switch( canHwConfig->CanControllerId ) {\r
+ case CAN_CTRL_A:\r
+ INSTALL_HANDLERS(Can_A, FLEXCAN_A_ESR_BOFF_INT, FLEXCAN_A_ESR_ERR_INT, FLEXCAN_A_IFLAG1_BUF0I, FLEXCAN_A_IFLAG1_BUF31_16I); break;\r
+ case CAN_CTRL_B:\r
+ INSTALL_HANDLERS(Can_B, FLEXCAN_B_ESR_BOFF_INT, FLEXCAN_B_ESR_ERR_INT, FLEXCAN_B_IFLAG1_BUF0I, FLEXCAN_B_IFLAG1_BUF31_16I); break;\r
+ case CAN_CTRL_C:\r
+ INSTALL_HANDLERS(Can_C, FLEXCAN_C_ESR_BOFF_INT, FLEXCAN_C_ESR_ERR_INT, FLEXCAN_C_IFLAG1_BUF0I, FLEXCAN_C_IFLAG1_BUF31_16I); break;\r
+ case CAN_CTRL_D:\r
+ INSTALL_HANDLERS(Can_D, FLEXCAN_D_ESR_BOFF_INT, FLEXCAN_D_ESR_ERR_INT, FLEXCAN_D_IFLAG1_BUF0I, FLEXCAN_D_IFLAG1_BUF31_16I); break;\r
+ case CAN_CTRL_E:\r
+ INSTALL_HANDLERS(Can_E, FLEXCAN_E_ESR_BOFF_INT, FLEXCAN_E_ESR_ERR_INT, FLEXCAN_E_IFLAG1_BUF0I, FLEXCAN_E_IFLAG1_BUF31_16I); break;\r
+ case CAN_CTRL_F:\r
+ INSTALL_HANDLERS(Can_F, FLEXCAN_F_ESR_BOFF_INT, FLEXCAN_F_ESR_ERR_INT, FLEXCAN_F_IFLAG1_BUF0I, FLEXCAN_F_IFLAG1_BUF31_16I); break;\r
+ default:\r
+ assert(0);\r
+ }\r
+#endif\r
+ }\r
+ return;\r
+}\r
+\r
+// Unitialize the module\r
+void Can_DeInit()\r
+{\r
+ Can_UnitType *canUnit;\r
+ const Can_ControllerConfigType *canHwConfig;\r
+ uint32 ctlrId;\r
+\r
+ for (int configId=0; configId < CAN_ECORE_CTRL_CONFIG_CNT; configId++) {\r
+ canHwConfig = GET_CONTROLLER_CONFIG(configId);\r
+ ctlrId = canHwConfig->CanControllerId;\r
+\r
+ canUnit = GET_PRIVATE_DATA(ctlrId);\r
+ canUnit->state = CANIF_CS_UNINIT;\r
+\r
+ Can_DisableControllerInterrupts(ctlrId);\r
+\r
+ canUnit->lock_cnt = 0;\r
+\r
+ // Clear stats\r
+ memset(&canUnit->stats, 0, sizeof(Can_EcoreStatisticsType));\r
+ }\r
+\r
+ Can_Global.config = NULL;\r
+ Can_Global.initRun = CAN_UNINIT;\r
+\r
+ return;\r
+}\r
+\r
+void Can_InitController( uint8 controller, const Can_ControllerConfigType *config) {\r
+\r
+ flexcan_t *canHw;\r
+ uint8_t tq;\r
+ uint8_t tq1;\r
+ uint8_t tq2;\r
+ uint32_t clock;\r
+ int i;\r
+ Can_UnitType *canUnit;\r
+ uint8 cId = controller;\r
+ const Can_ControllerConfigType *canHwConfig;\r
+ const Can_HardwareObjectType *hohObj;\r
+\r
+ VALIDATE_NO_RV( (Can_Global.initRun == CAN_READY), 0x2, CAN_E_UNINIT );\r
+ VALIDATE_NO_RV( (config != NULL ), 0x2,CAN_E_PARAM_POINTER);\r
+ VALIDATE_NO_RV( (controller < GET_CONTROLLER_CNT()), 0x2, CAN_E_PARAM_CONTROLLER );\r
+\r
+ canUnit = GET_PRIVATE_DATA(controller);\r
+\r
+ VALIDATE_NO_RV( (canUnit->state==CANIF_CS_STOPPED), 0x2, CAN_E_TRANSITION );\r
+\r
+ canHw = GET_CONTROLLER(cId);\r
+ canHwConfig = GET_CONTROLLER_CONFIG(Can_Global.channelMap[cId]);\r
+\r
+ // Start this baby up\r
+ canHw->MCR.B.MDIS = 0;\r
+\r
+ // Wait for it to reset\r
+ if( !SIMULATOR() ) {\r
+ // Make a reset so we have a known state\r
+ canHw->MCR.B.SOFTRST = 1;\r
+ while( canHw->MCR.B.SOFTRST == 1);\r
+ // Freeze to write all mem mapped registers ( see 25.4.8.1 )\r
+ canHw->MCR.B.FRZ = 1;\r
+ while( canHw->MCR.B.FRZACK == 0);\r
+ }\r
+\r
+#if defined(CFG_MPC5516) || defined(CFG_MPC5517)\r
+ // Note!\r
+ // FIFO implemenation not tested\r
+ if( config->CanEcoreFifo ) {\r
+ canHw->MCR.B.FEN = 1; // Enable FIFO\r
+ canHw->MCR.B.IDAM = 0; // We want extended id's to match with\r
+ }\r
+ canHw->MCR.B.BCC = 1; // Enable all nice features\r
+#endif\r
+ /* Use Fsys derivate */\r
+ canHw->CR.B.CLKSRC = 1;\r
+ canHw->MCR.B.MAXMB = MAX_NUM_OF_MAILBOXES - 1;\r
+\r
+ /* Disable selfreception */\r
+ canHw->MCR.B.SRXDIS = !config->CanEcoreLoopback;\r
+\r
+ // Clock calucation\r
+ // -------------------------------------------------------------------\r
+ //\r
+ // * 1 TQ = Sclk period( also called SCK )\r
+ // * Ftq = Fcanclk / ( PRESDIV + 1 ) = Sclk\r
+ // ( Fcanclk can come from crystal or from the peripheral dividers )\r
+ //\r
+ // -->\r
+ // TQ = 1/Ftq = (PRESDIV+1)/Fcanclk --> PRESDIV = (TQ * Fcanclk - 1 )\r
+ // TQ is between 8 and 25\r
+\r
+ // Calculate the number of timequanta's\r
+ // From "Protocol Timing"( chap. 25.4.7.4 )\r
+ tq1 = ( config->CanControllerPropSeg + config->CanControllerSeg1 + 2);\r
+ tq2 = (config->CanControllerSeg2 + 1);\r
+ tq = 1 + tq1 + tq2;\r
+\r
+ // Check TQ limitations..\r
+ VALIDATE_NO_RV(( (tq1>=4) && (tq1<=16)), 0x2, CAN_E_TIMEOUT ); // Actually should be sent to DEM\r
+ VALIDATE_NO_RV(( (tq2>=2) && (tq2<=8)), 0x2, CAN_E_TIMEOUT ); // but this is the next best thing\r
+ VALIDATE_NO_RV(( (tq>8) && (tq<25 )), 0x2, CAN_E_TIMEOUT );\r
+\r
+ // Assume we're using the peripheral clock instead of the crystal.\r
+ clock = McuE_GetPeripheralClock(config->CanCpuClockRef);\r
+\r
+ canHw->CR.B.PRESDIV = clock/(config->CanControllerBaudRate*1000*tq) - 1;\r
+ canHw->CR.B.PROPSEG = config->CanControllerPropSeg;\r
+ canHw->CR.B.PSEG1 = config->CanControllerSeg1;\r
+ canHw->CR.B.PSEG2 = config->CanControllerSeg2;\r
+ canHw->CR.B.SMP = 1; // 3 samples better than 1 ??\r
+ canHw->CR.B.LPB = config->CanEcoreLoopback;\r
+ canHw->CR.B.BOFFREC = 1; // Disable bus off recovery\r
+\r
+#if defined(CFG_MPC5516) || defined(CFG_MPC5517)\r
+ // Check if we use individual masks. If so accept anything(=0) for now\r
+ if( canHw->MCR.B.BCC ) {\r
+ i = (config->CanEcoreFifo ? 8 : 0 );\r
+ for(;i<63;i++) {\r
+ canHw->RXIMR[i].R = 0;\r
+ }\r
+ }\r
+#else\r
+#endif\r
+ // Set the id's\r
+ if( config->CanEcoreFifo ) {\r
+ // Clear ID's in FIFO also, MUST set extended bit here\r
+ uint32_t *fifoId = (uint32_t*)(((uint8_t *)canHw)+0xe0);\r
+ for(int k=0;k<8;k++) {\r
+ fifoId[k] = 0x40000000; // accept extended frames\r
+ }\r
+ }\r
+\r
+ // Mark all slots as inactive( depending on fifo )\r
+ i = (config->CanEcoreFifo ? 8 : 0 );\r
+ for(; i < 63; i++) {\r
+ //canHw->BUF[i].CS.B.CODE = 0;\r
+ canHw->BUF[i].CS.R = 0;\r
+ canHw->BUF[i].ID.R = 0;\r
+ }\r
+\r
+ {\r
+ /* Build a global interrupt/mb mask for all Hoh's */\r
+ uint32 mbMask;\r
+ uint32 mbNr = 0;\r
+ Can_FilterMaskType mask = 0xffffffff;\r
+\r
+ // Rx\r
+ hohObj = canHwConfig->CanEcoreHoh;\r
+ --hohObj;\r
+ do {\r
+ ++hohObj;\r
+\r
+ mbMask = hohObj->CanEcoreMbMask;\r
+ mbNr = 0;\r
+\r
+ if (hohObj->CanObjectType == CAN_OBJECT_TYPE_RECEIVE)\r
+ {\r
+ for(;mbMask;mbMask&=~(1<<mbNr)) {\r
+ mbNr = ilog2(mbMask);\r
+ canHw->BUF[mbNr].CS.B.CODE = MB_RX;\r
+ if ( hohObj->CanIdType == CAN_ID_TYPE_EXTENDED )\r
+ {\r
+ canHw->BUF[mbNr].CS.B.IDE = 1;\r
+ canHw->BUF[mbNr].ID.R = *hohObj->CanFilterMaskRef; // Write 29-bit MB IDs\r
+ }\r
+ else\r
+ {\r
+ canHw->BUF[mbNr].CS.B.IDE = 0;\r
+ canHw->BUF[mbNr].ID.B.STD_ID = *hohObj->CanFilterMaskRef;\r
+ }\r
+ }\r
+\r
+ // Add to global mask\r
+ canUnit->CanEcoreRxMbMask |= hohObj->CanEcoreMbMask;\r
+ if( hohObj->CanFilterMaskRef != NULL ) {\r
+ mask &= *hohObj->CanFilterMaskRef;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ canUnit->CanEcoreTxMbMask |= hohObj->CanEcoreMbMask;\r
+ }\r
+ } while( !hohObj->CanEcoreEOL );\r
+\r
+\r
+ // Set global mask\r
+ canHw->RXGMASK.R = mask;\r
+ // Don't use them\r
+ canHw->RX14MASK.R = 0;\r
+ canHw->RX15MASK.R = 0;\r
+ }\r
+\r
+ canUnit->iflagStart = canUnit->CanEcoreTxMbMask;\r
+\r
+ canUnit->state = CANIF_CS_STOPPED;\r
+ Can_EnableControllerInterrupts(cId);\r
+\r
+ return;\r
+}\r
+\r
+\r
+Can_ReturnType Can_SetControllerMode( uint8 controller, Can_StateTransitionType transition ) {\r
+ flexcan_t *canHw;\r
+ Can_ReturnType rv = CAN_OK;\r
+ VALIDATE( (controller < GET_CONTROLLER_CNT()), 0x3, CAN_E_PARAM_CONTROLLER );\r
+\r
+ Can_UnitType *canUnit = GET_PRIVATE_DATA(controller);\r
+\r
+ VALIDATE( (canUnit->state!=CANIF_CS_UNINIT), 0x3, CAN_E_UNINIT );\r
+ canHw = GET_CONTROLLER(controller);\r
+\r
+ switch(transition )\r
+ {\r
+ case CAN_T_START:\r
+ canHw->MCR.B.FRZ = 0;\r
+ canHw->MCR.B.HALT = 0;\r
+ canUnit->state = CANIF_CS_STARTED;\r
+ imask_t state = McuE_EnterCriticalSection();\r
+ if (canUnit->lock_cnt == 0) // REQ CAN196\r
+ Can_EnableControllerInterrupts(controller);\r
+ McuE_ExitCriticalSection(state);\r
+ break;\r
+ case CAN_T_WAKEUP: //CAN267\r
+ case CAN_T_SLEEP: //CAN258, CAN290\r
+ // Should be reported to DEM but DET is the next best\r
+ VALIDATE(canUnit->state == CANIF_CS_STOPPED, 0x3, CAN_E_TRANSITION);\r
+ case CAN_T_STOP:\r
+ // Stop\r
+ canHw->MCR.B.FRZ = 1;\r
+ canHw->MCR.B.HALT = 1;\r
+ canUnit->state = CANIF_CS_STOPPED;\r
+ Can_AbortTx( canHw, canUnit ); // CANIF282\r
+ break;\r
+ default:\r
+ // Should be reported to DEM but DET is the next best\r
+ VALIDATE(canUnit->state == CANIF_CS_STOPPED, 0x3, CAN_E_TRANSITION);\r
+ break;\r
+ }\r
+\r
+ return rv;\r
+}\r
+\r
+void Can_DisableControllerInterrupts( uint8 controller )\r
+{\r
+ Can_UnitType *canUnit;\r
+ flexcan_t *canHw;\r
+\r
+ VALIDATE_NO_RV( (controller < GET_CONTROLLER_CNT()), 0x4, CAN_E_PARAM_CONTROLLER );\r
+\r
+ canUnit = GET_PRIVATE_DATA(controller);\r
+\r
+ VALIDATE_NO_RV( (canUnit->state!=CANIF_CS_UNINIT), 0x4, CAN_E_UNINIT );\r
+\r
+ imask_t state = McuE_EnterCriticalSection();\r
+ if(canUnit->lock_cnt > 0 )\r
+ {\r
+ // Interrupts already disabled\r
+ canUnit->lock_cnt++;\r
+ McuE_ExitCriticalSection(state);\r
+ return;\r
+ }\r
+ canUnit->lock_cnt++;\r
+ McuE_ExitCriticalSection(state);\r
+\r
+ /* Don't try to be intelligent, turn everything off */\r
+ canHw = GET_CONTROLLER(controller);\r
+\r
+ /* Turn off the interrupt mailboxes */\r
+ canHw->IMRH.R = 0;\r
+ canHw->IMRL.R = 0;\r
+\r
+ /* Turn off the bus off/tx warning/rx warning and error */\r
+ canHw->MCR.B.WRNEN = 0; /* Disable warning int */\r
+ canHw->CR.B.ERRMSK = 0; /* Disable error interrupt */\r
+ canHw->CR.B.BOFFMSK = 0; /* Disable bus-off interrupt */\r
+ canHw->CR.B.TWRNMSK = 0; /* Disable Tx warning */\r
+ canHw->CR.B.RWRNMSK = 0; /* Disable Rx warning */\r
+}\r
+\r
+void Can_EnableControllerInterrupts( uint8 controller ) {\r
+ Can_UnitType *canUnit;\r
+ flexcan_t *canHw;\r
+ const Can_ControllerConfigType *canHwConfig;\r
+ VALIDATE_NO_RV( (controller < GET_CONTROLLER_CNT()), 0x5, CAN_E_PARAM_CONTROLLER );\r
+\r
+ canUnit = GET_PRIVATE_DATA(controller);\r
+\r
+ VALIDATE_NO_RV( (canUnit->state!=CANIF_CS_UNINIT), 0x5, CAN_E_UNINIT );\r
+\r
+ imask_t state = McuE_EnterCriticalSection();\r
+ if( canUnit->lock_cnt > 1 )\r
+ {\r
+ // IRQ should still be disabled so just decrement counter\r
+ canUnit->lock_cnt--;\r
+ McuE_ExitCriticalSection(state);\r
+ return;\r
+ } else if (canUnit->lock_cnt == 1)\r
+ {\r
+ canUnit->lock_cnt = 0;\r
+ }\r
+ McuE_ExitCriticalSection(state);\r
+\r
+ canHw = GET_CONTROLLER(controller);\r
+\r
+ canHwConfig = GET_CONTROLLER_CONFIG(Can_Global.channelMap[controller]);\r
+\r
+ canHw->IMRH.R = 0;\r
+ canHw->IMRL.R = 0;\r
+\r
+ if( canHwConfig->CanRxProcessing == CAN_ECORE_PROCESS_TYPE_INTERRUPT ) {\r
+ /* Turn on the interrupt mailboxes */\r
+ canHw->IMRL.R = canUnit->CanEcoreRxMbMask;\r
+ }\r
+\r
+ if( canHwConfig->CanTxProcessing == CAN_ECORE_PROCESS_TYPE_INTERRUPT ) {\r
+ /* Turn on the interrupt mailboxes */\r
+ canHw->IMRL.R |= canUnit->CanEcoreTxMbMask;\r
+ }\r
+\r
+ // BusOff here represents all errors and warnings\r
+ if( canHwConfig->CanBusOffProcessing == CAN_ECORE_PROCESS_TYPE_INTERRUPT ) {\r
+ canHw->MCR.B.WRNEN = 1; /* Turn On warning int */\r
+\r
+ canHw->CR.B.ERRMSK = 1; /* Enable error interrupt */\r
+ canHw->CR.B.BOFFMSK = 1; /* Enable bus-off interrupt */\r
+ canHw->CR.B.TWRNMSK = 1; /* Enable Tx warning */\r
+ canHw->CR.B.RWRNMSK = 1; /* Enable Rx warning */\r
+ }\r
+\r
+ return;\r
+}\r
+\r
+Can_ReturnType Can_Write( Can_EcoreHTHType hth, Can_PduType *pduInfo ) {\r
+ uint16_t timer;\r
+ uint32_t iflag;\r
+ Can_ReturnType rv = CAN_OK;\r
+ uint32_t mbNr;\r
+ flexcan_t *canHw;\r
+ const Can_HardwareObjectType *hohObj;\r
+ uint32 controller;\r
+ uint32 oldMsr;\r
+\r
+ VALIDATE( (Can_Global.initRun == CAN_READY), 0x6, CAN_E_UNINIT );\r
+ VALIDATE( (pduInfo != NULL), 0x6, CAN_E_PARAM_POINTER );\r
+ VALIDATE( (pduInfo->length <= 8), 0x6, CAN_E_PARAM_DLC );\r
+ VALIDATE( (hth < NUM_OF_HTHS ), 0x6, CAN_E_PARAM_HANDLE );\r
+\r
+ hohObj = Can_FindHoh(hth, &controller);\r
+ if (hohObj == NULL)\r
+ return CAN_NOT_OK;\r
+\r
+ Can_UnitType *canUnit = GET_PRIVATE_DATA(controller);\r
+\r
+ canHw = GET_CONTROLLER(controller);\r
+ oldMsr = McuE_EnterCriticalSection();\r
+ iflag = canHw->IFRL.R & canUnit->CanEcoreTxMbMask;\r
+\r
+ // check for any free box\r
+ // Normally we would just use the iflag to get the free box\r
+ // but that does not work the first time( iflag == 0 ) so we\r
+ // create one( iflagStart )\r
+ if( iflag | canUnit->iflagStart ) {\r
+ mbNr = ilog2((iflag | canUnit->iflagStart)); // find mb number\r
+ // clear flag\r
+ canHw->IFRL.R = (1<<mbNr);\r
+ canUnit->iflagStart &= ~(1<<mbNr);\r
+\r
+ // Setup message box type\r
+ if( hohObj->CanIdType == CAN_ID_TYPE_EXTENDED ) {\r
+ canHw->BUF[mbNr].CS.B.IDE = 1;\r
+ } else if ( hohObj->CanIdType == CAN_ID_TYPE_STANDARD ) {\r
+ canHw->BUF[mbNr].CS.B.IDE = 0;\r
+ } else {\r
+ // No support for mixed in this processor\r
+ assert(0);\r
+ }\r
+\r
+ // Send on buf\r
+ canHw->BUF[mbNr].CS.B.CODE = MB_INACTIVE; // Hold the transmit buffer inactive\r
+ if( hohObj->CanIdType == CAN_ID_TYPE_EXTENDED ) {\r
+ canHw->BUF[mbNr].ID.R = pduInfo->id; // Write 29-bit MB IDs\r
+ } else {\r
+ assert( !(pduInfo->id & 0xfffff800) );\r
+ canHw->BUF[mbNr].ID.B.STD_ID = pduInfo->id;\r
+ }\r
+\r
+#if defined(CFG_MPC5516) || defined(CFG_MPC5517)\r
+ canHw->BUF[mbNr].ID.B.PRIO = 1; // Set Local Priority\r
+#endif\r
+\r
+ memset(&canHw->BUF[mbNr].DATA, 0, 8);\r
+ memcpy(&canHw->BUF[mbNr].DATA, pduInfo->sdu, pduInfo->length);\r
+\r
+ canHw->BUF[mbNr].CS.B.SRR = 1;\r
+ canHw->BUF[mbNr].CS.B.RTR = 0;\r
+\r
+ canHw->BUF[mbNr].CS.B.LENGTH = pduInfo->length;\r
+ canHw->BUF[mbNr].CS.B.CODE = MB_TX_ONCE; // Write tx once code\r
+ timer = canHw->TIMER.R; // Unlock Message buffers\r
+\r
+ canUnit->stats.txSuccessCnt++;\r
+\r
+ // Store pdu handle in unit to be used by TxConfirmation\r
+ canUnit->swPduHandles[mbNr] = pduInfo->swPduHandle;\r
+\r
+ } else {\r
+ rv = CAN_BUSY;\r
+ }\r
+ McuE_ExitCriticalSection(oldMsr);\r
+\r
+ return rv;\r
+}\r
+\r
+void Can_MainFunction_Read( void ) {\r
+\r
+ /* NOT SUPPORTED */\r
+}\r
+\r
+void Can_MainFunction_BusOff( void ) {\r
+ /* Bus-off polling events */\r
+\r
+ /* NOT SUPPORTED */\r
+}\r
+\r
+void Can_MainFunction_Wakeup( void ) {\r
+ /* Wakeup polling events */\r
+\r
+ /* NOT SUPPORTED */\r
+}\r
+\r
+\r
+/**\r
+ * Get send/receive/error statistics for a controller\r
+ *\r
+ * @param controller The controller\r
+ * @param stats Pointer to data to copy statistics to\r
+ */\r
+\r
+void Can_EcoreGetStatistics( uint8 controller, Can_EcoreStatisticsType *stats)\r
+{\r
+ Can_UnitType *canUnit = GET_PRIVATE_DATA(controller);\r
+ *stats = canUnit->stats;\r
+}\r
+\r
+\r
+\r
+#else // Stub all functions for use in simulator environment\r
+\r
+#include "Trace.h"\r
+\r
+void Can_Init( const Can_ConfigType *Config )\r
+{\r
+ // Do initial configuration of layer here\r
+}\r
+\r
+void Can_InitController( uint8 controller, const Can_ControllerConfigType *config)\r
+{\r
+ // Do initialisation of controller here.\r
+}\r
+\r
+Can_ReturnType Can_SetControllerMode( uint8 Controller, Can_StateTransitionType transition )\r
+{\r
+ // Turn on off controller here depending on transition\r
+ return E_OK;\r
+}\r
+\r
+Can_ReturnType Can_Write( Can_EcoreHTHType hth, Can_PduType *pduInfo )\r
+{\r
+ // Write to mailbox on controller here.\r
+ DEBUG(DEBUG_MEDIUM, "Can_Write(stub): Received data ");\r
+ for (int i = 0; i < pduInfo->length; i++) {\r
+ DEBUG(DEBUG_MEDIUM, "%d ", pduInfo->sdu[i]);\r
+ }\r
+ DEBUG(DEBUG_MEDIUM, "\n");\r
+\r
+ return E_OK;\r
+}\r
+\r
+extern void CanIf_RxIndication(uint8 Hrh, Can_IdType CanId, uint8 CanDlc, const uint8 *CanSduPtr);\r
+Can_ReturnType Can_ReceiveAFrame()\r
+{\r
+ // This function is not part of autosar but needed to feed the stack with data\r
+ // from the mailboxes. Normally this is an interrup but probably not in the PCAN case.\r
+ uint8 CanSduData[] = {1,2,1,0,0,0,0,0};\r
+ CanIf_RxIndication(CAN_HRH_A_1, 3, 8, CanSduData);\r
+\r
+ return E_OK;\r
+}\r
+\r
+void Can_DisableControllerInterrupts( uint8 controller )\r
+{\r
+}\r
+\r
+void Can_EnableControllerInterrupts( uint8 controller )\r
+{\r
+}\r
+\r
+\r
+// Hth - for Flexcan, the hardware message box number... .We don't care\r
+void Can_Cbk_CheckWakeup( uint8 controller ){}\r
+\r
+void Can_MainFunction_Write( void ){}\r
+void Can_MainFunction_Read( void ){}\r
+void Can_MainFunction_BusOff( void ){}\r
+void Can_MainFunction_Wakeup( void ){}\r
+\r
+void Can_EcoreGetStatistics( uint8 controller, Can_EcoreStatisticsType * stat){}\r
+\r
+#endif\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include "Det.h"
+#include "CanIf.h"
+
+#include "Can.h"
+#include "CanIf_Cbk.h"
+#include "string.h"
+
+// Added by Mattias 2008-11-18
+#include "Trace.h"
+#include "PduR.h"
+
+#if 0
+// TODO: Include upper layer functions, See CANIF208 and CANIF233
+#include "PduR_CanIf.h"
+#include "CanNm.h"
+#include "CanTp.h"
+
+#include "PduR_Cbk.h"
+#include "CanNm_Cbk.h"
+#include "CanTp_Cbk.h"
+#endif
+
+#if ( CANIF_DEV_ERROR_DETECT == STD_ON )
+#define VALIDATE(_exp,_api,_err ) \
+ if( !(_exp) ) { \
+ Det_ReportError(MODULE_ID_CANIF, 0, _api, _err); \
+ return E_NOT_OK; \
+ }
+
+#define VALIDATE_NO_RV(_exp,_api,_err ) \
+ if( !(_exp) ) { \
+ Det_ReportError(MODULE_ID_CANIF, 0, _api, _err); \
+ return; \
+ }
+#undef DET_REPORTERROR
+#define DET_REPORTERROR(_x,_y,_z,_q) Det_ReportError(_x, _y, _z, _q)
+
+#else
+#define VALIDATE(_exp,_api,_err )
+#define VALIDATE_NO_RV(_exp,_api,_err )
+#define DET_REPORTERROR(_x,_y,_z,_q)
+#endif
+
+#define GET_CONTROLLER_CNT() CAN_ECORE_CTRL_CONFIG_CNT
+
+/* Global configure */
+static const CanIf_ConfigType *CanIf_ConfigPtr;
+
+// Struct of controller private data.
+typedef struct CanIf_ControllerPrivateStruct
+{
+ CanIf_ControllerModeType ControllerMode;
+ CanIf_ChannelGetModeType ChannelMode;
+} CanIf_ControllerPrivateType;
+
+typedef struct
+{
+ boolean initRun;
+ CanIf_ControllerPrivateType controllerData[GET_CONTROLLER_CNT()];
+} CanIf_GlobalType;
+
+static sint8 CanIf_FindHrhCtrl( Can_EcoreHRHType hrh )
+{
+ const CanIf_HrhConfigType *hrhConfig;
+
+ hrhConfig = CanIf_ConfigPtr->InitConfig->CanIfHohConfigPtr->CanIfHrhConfig;
+
+ hrhConfig--;
+ do
+ {
+ hrhConfig++;
+ if (hrhConfig->CanIfHrhIdSymRef == hrh)
+ return hrhConfig->CanIfCanControllerHrhIdRef;
+ } while(!hrhConfig->CanIfEcoreEOL);
+
+ DET_REPORTERROR(MODULE_ID_CANIF, 0, CANIF_RXINDICATION_ID, CANIF_E_PARAM_HRH);
+
+ return -1;
+}
+
+// Global config
+CanIf_GlobalType CanIf_Global;
+
+void CanIf_Init(const CanIf_ConfigType *ConfigPtr)
+{
+ VALIDATE_NO_RV(ConfigPtr != 0, CANIF_INIT_ID, CANIF_E_PARAM_POINTER); // Only PostBuild case supported
+
+ CanIf_ConfigPtr = ConfigPtr;
+
+ for (uint16 i = 0; i < GET_CONTROLLER_CNT(); i++)
+ {
+ CanIf_Global.controllerData[i].ControllerMode = CANIF_CS_STOPPED;
+ CanIf_Global.controllerData[i].ChannelMode = CANIF_GET_OFFLINE;
+ }
+
+ // NOTE!
+ // Do NOT initialise the Can Drivers and Tranceivers, see CANIF085
+ //
+
+ CanIf_Global.initRun = TRUE;
+}
+
+//-------------------------------------------------------------------
+
+void CanIf_InitController(uint8 Controller, uint8 ConfigurationIndex)
+{
+ VALIDATE_NO_RV(CanIf_Global.initRun, CANIF_INIT_CONTROLLER_ID, CANIF_E_UNINIT );
+ VALIDATE_NO_RV(Controller < GET_CONTROLLER_CNT(), CANIF_INIT_CONTROLLER_ID, CANIF_E_PARAM_CONTROLLER);
+ VALIDATE_NO_RV(ConfigurationIndex < CAN_ECORE_CTRL_CONFIG_CNT, CANIF_INIT_CONTROLLER_ID, CANIF_E_PARAM_POINTER);
+
+#if (CANIF_DEV_ERROR_DETECT == STD_ON)
+ CanIf_ControllerModeType mode;
+
+ if (CanIf_GetControllerMode(Controller, &mode) == E_OK)
+ {
+ VALIDATE_NO_RV((mode != CANIF_CS_UNINIT), CANIF_INIT_CONTROLLER_ID, CANIF_E_PARAM_CONTROLLER_MODE );
+ }
+ else
+ {
+ VALIDATE_NO_RV(FALSE, CANIF_INIT_CONTROLLER_ID, CANIF_E_PARAM_CONTROLLER_MODE);
+ }
+#endif
+
+ if (CanIf_GetControllerMode(Controller, &mode) == E_OK)
+ {
+ if (mode == CANIF_CS_STARTED)
+ {
+ CanIf_SetControllerMode(Controller, CANIF_CS_STOPPED); // CANIF092
+ }
+ else if (mode != CANIF_CS_STOPPED)
+ {
+ VALIDATE_NO_RV(FALSE, CANIF_INIT_CONTROLLER_ID, CANIF_E_PARAM_CONTROLLER_MODE); // CANIF092
+ }
+ }
+
+ // CANIF293: ..Subsequently the CAN Interface calls the corresponding
+ // CAN Driver initialization services.
+
+ // CANIF066: The CAN Interface has access to the CAN Driver configuration data. All
+ // public CAN Driver configuration data are described in [8] Specification of CAN Driver.
+
+ // Grab the configuration from the Can Controller
+ const Can_ControllerConfigType *canConfig;
+
+ // Validate that the configuration index match the right controller
+ VALIDATE_NO_RV(CanIf_ConfigPtr->ControllerConfig[ConfigurationIndex].CanIfControllerIdRef == Controller, CANIF_INIT_CONTROLLER_ID, CANIF_E_PARAM_CONTROLLER);
+
+ canConfig = CanIf_ConfigPtr->ControllerConfig[ConfigurationIndex].CanIfInitControllerRef;
+
+ Can_InitController(Controller, canConfig);
+
+ // Set mode to stopped
+ CanIf_SetControllerMode(Controller, CANIF_CS_STOPPED);
+}
+
+//-------------------------------------------------------------------
+
+Std_ReturnType CanIf_SetControllerMode(uint8 Controller,
+ CanIf_ControllerModeType ControllerMode)
+{
+ CanIf_ControllerModeType oldMode;
+
+ VALIDATE( CanIf_Global.initRun, CANIF_SET_CONTROLLER_MODE_ID, CANIF_E_UNINIT );
+ VALIDATE( Controller < GET_CONTROLLER_CNT(), CANIF_SET_CONTROLLER_MODE_ID, CANIF_E_PARAM_CONTROLLER );
+
+ oldMode = CanIf_Global.controllerData[Controller].ControllerMode;
+
+ if (oldMode == CANIF_CS_UNINIT)
+ {
+ VALIDATE(FALSE, CANIF_SET_CONTROLLER_MODE_ID, CANIF_E_UNINIT); // See figure 32, 33
+ return E_NOT_OK;
+ }
+
+ switch (ControllerMode)
+ {
+ case CANIF_CS_STARTED: // Figure 32
+ {
+ switch (oldMode)
+ {
+ case CANIF_CS_SLEEP:
+ if (Can_SetControllerMode(Controller, CAN_T_STOP) == CAN_NOT_OK)
+ return E_NOT_OK;
+ CanIf_Global.controllerData[Controller].ControllerMode = CANIF_CS_STOPPED;
+ break;
+ default:
+ // Just fall through
+ break;
+ }
+
+ CanIf_SetPduMode(Controller, CANIF_SET_ONLINE);
+ if (Can_SetControllerMode(Controller, CAN_T_START) == CAN_NOT_OK)
+ return E_NOT_OK;
+ CanIf_Global.controllerData[Controller].ControllerMode = CANIF_CS_STARTED;
+ }
+ break;
+
+ case CANIF_CS_SLEEP: // Figure 33
+ {
+ switch (oldMode) {
+ case CANIF_CS_STARTED:
+ if (Can_SetControllerMode(Controller, CAN_T_STOP) == CAN_NOT_OK)
+ return E_NOT_OK;
+ CanIf_Global.controllerData[Controller].ControllerMode = CANIF_CS_STOPPED;
+ break;
+ default:
+ // Just fall through for other cases
+ break;
+ }
+
+ if (Can_SetControllerMode(Controller, CAN_T_SLEEP) == CAN_NOT_OK)
+ return E_NOT_OK;
+ CanIf_Global.controllerData[Controller].ControllerMode = CANIF_CS_SLEEP;
+ }
+
+ case CANIF_CS_STOPPED:
+ {
+ switch (oldMode)
+ {
+ case CANIF_CS_SLEEP:
+ if (Can_SetControllerMode(Controller, CAN_T_WAKEUP) == CAN_NOT_OK)
+ return E_NOT_OK;
+ break;
+ default:
+ // Just fall through for other cases
+ break;
+ }
+
+ CanIf_SetPduMode(Controller, CANIF_SET_OFFLINE);
+ if (Can_SetControllerMode(Controller, CAN_T_STOP) == CAN_NOT_OK)
+ return E_NOT_OK;
+ CanIf_Global.controllerData[Controller].ControllerMode = CANIF_CS_STOPPED;
+ }
+
+ case CANIF_CS_UNINIT:
+ // Jusr fall through
+ break;
+ }
+ return E_OK;
+}
+
+//-------------------------------------------------------------------
+
+Std_ReturnType CanIf_GetControllerMode(uint8 Controller,
+ CanIf_ControllerModeType *ControllerModePtr)
+{
+ VALIDATE(CanIf_Global.initRun, CANIF_GET_CONTROLLER_MODE_ID, CANIF_E_UNINIT );
+ VALIDATE(Controller < GET_CONTROLLER_CNT(), CANIF_GET_CONTROLLER_MODE_ID, CANIF_E_PARAM_CONTROLLER );
+ VALIDATE(ControllerModePtr != NULL, CANIF_GET_CONTROLLER_MODE_ID, CANIF_E_PARAM_POINTER );
+
+ *ControllerModePtr = CanIf_Global.controllerData[Controller].ControllerMode;
+
+ return E_OK;
+}
+
+//-------------------------------------------------------------------
+/**
+ * Matches a Tx PDU id agaist the ones that are in the database.
+ *
+ * @returns Ptr a TxPdu
+ */
+static const CanIf_TxPduConfigType * CanIf_FindTxPduEntry(PduIdType id)
+{
+ const CanIf_TxPduConfigType *entry =
+ CanIf_ConfigPtr->InitConfig->CanIfTxPduConfigPtr;
+
+ for (uint16 i = 0; i < CanIf_ConfigPtr->InitConfig->CanIfNumberOfCanTXPduIds; i++)
+ {
+ if (entry->CanIfTxPduId == id)
+ {
+ return entry;
+ }
+ entry++;
+ }
+
+ return 0;
+}
+
+//-------------------------------------------------------------------
+
+Std_ReturnType CanIf_Transmit(PduIdType CanTxPduId,
+ const PduInfoType *PduInfoPtr)
+{
+ Can_PduType canPdu;
+ const CanIf_TxPduConfigType *txEntry;
+ CanIf_ControllerModeType csMode;
+ CanIf_ChannelGetModeType pduMode;
+
+ VALIDATE(CanIf_Global.initRun, CANIF_TRANSMIT_ID, CANIF_E_UNINIT );
+ VALIDATE((PduInfoPtr != 0), CANIF_TRANSMIT_ID, CANIF_E_PARAM_POINTER );
+
+ // Get the controller from L-PDU handle
+ txEntry = CanIf_FindTxPduEntry(CanTxPduId);
+
+ if (txEntry == 0)
+ {
+ VALIDATE(FALSE, CANIF_TRANSMIT_ID, CANIF_E_INVALID_TXPDUID);
+ return E_NOT_OK;
+ }
+
+ uint8 controller = txEntry->CanIfCanTxPduHthRef->CanIfCanControllerIdRef;
+
+ // Get and verify the controller mode
+ if (CanIf_GetControllerMode(controller, &csMode) == E_NOT_OK)
+ return E_NOT_OK;
+
+ if (csMode != CANIF_CS_STARTED) // CANIF_161
+ return E_NOT_OK;
+
+ // Get and verify the PDU channel mode control
+ if (CanIf_GetPduMode(controller, &pduMode) == E_NOT_OK)
+ return E_NOT_OK;
+
+ if ((pduMode != CANIF_GET_TX_ONLINE) && (pduMode != CANIF_GET_ONLINE))
+ return E_NOT_OK;
+
+ canPdu.id = txEntry->CanIfCanTxPduIdCanId;
+
+ canPdu.length = PduInfoPtr->SduLength;
+ canPdu.sdu = PduInfoPtr->SduDataPtr;
+ canPdu.swPduHandle = CanTxPduId;
+
+ Can_ReturnType rVal = Can_Write(txEntry->CanIfCanTxPduHthRef->CanIfHthIdSymRef, &canPdu);
+
+ if (rVal == CAN_NOT_OK)
+ return E_NOT_OK;
+
+ if (rVal == CAN_BUSY) // CANIF 082, CANIF 161
+ {
+ // Tx buffering not supported so just return.
+ return E_NOT_OK;
+ }
+
+ return E_OK;
+}
+
+//-------------------------------------------------------------------
+
+#if ( CANIF_READRXPDU_DATA_API == STD_ON )
+Std_ReturnType CanIf_ReadRxPduData(PduIdType CanRxPduId,
+ PduInfoType *PduInfoPtr)
+{
+ VALIDATE(FALSE, CANIF_READTXPDUDATA_ID, CANIF_E_NOK_NOSUPPORT);
+ VALIDATE(CanIf_Global.initRun == STD_ON, CANIF_READTXPDUDATA_ID, CANIF_E_UNINIT );
+ VALIDATE(PduInfoPtr != 0, CANIF_READTXPDUDATA_ID, CANIF_E_PARAM_POINTER );
+
+ // This function is not supported
+
+ return E_NOT_OK;
+}
+#endif
+
+//-------------------------------------------------------------------
+
+#if ( CANIF_READTXPDU_NOTIFY_STATUS_API == STD_ON )
+CanIf_NotifStatusType CanIf_ReadTxNotifStatus(PduIdType CanTxPduId)
+{
+ const CanIf_TxPduConfigType *txEntry;
+ VALIDATE(FALSE, CANIF_READTXNOTIFSTATUS_ID, CANIF_E_NOK_NOSUPPORT);
+ VALIDATE(CanIf_Global.initRun, CANIF_READTXNOTIFSTATUS_ID, CANIF_E_UNINIT );
+
+ // Get the controller from L-PDU handle
+ txEntry = CanIf_FindTxPduEntry(CanTxPduId);
+
+ if (txEntry == 0)
+ {
+ VALIDATE(FALSE, CANIF_READTXNOTIFSTATUS_ID, CANIF_E_INVALID_TXPDUID);
+ return CANIF_NO_NOTIFICATION;
+ }
+
+ if (txEntry->CanIfReadTxPduNotifyStatus == FALSE)
+ {
+ VALIDATE(FALSE, CANIF_READTXNOTIFSTATUS_ID, CANIF_E_INVALID_TXPDUID);
+ return CANIF_NO_NOTIFICATION;
+ }
+
+ // This function is not supported
+
+ return CANIF_NO_NOTIFICATION;
+}
+#endif
+
+//-------------------------------------------------------------------
+
+#if ( CANIF_READRXPDU_NOTIFY_STATUS_API == STD_ON )
+CanIf_NotifStatusType CanIf_ReadRxNotifStatus(PduIdType CanRxPduId)
+{
+ VALIDATE(FALSE, CANIF_READRXNOTIFSTATUS_ID, CANIF_E_NOK_NOSUPPORT);
+ VALIDATE(CanIf_Global.initRun, CANIF_READRXNOTIFSTATUS_ID, CANIF_E_UNINIT );
+
+ return CANIF_NO_NOTIFICATION;
+}
+#endif
+
+//-------------------------------------------------------------------
+
+Std_ReturnType CanIf_SetPduMode(uint8 Controller,
+ CanIf_ChannelSetModeType PduModeRequest)
+{
+ VALIDATE( CanIf_Global.initRun, CANIF_SETPDUMODE_ID, CANIF_E_UNINIT );
+ VALIDATE( Controller < GET_CONTROLLER_CNT(), CANIF_SETPDUMODE_ID, CANIF_E_PARAM_CONTROLLER );
+
+ CanIf_ChannelGetModeType oldMode = CanIf_Global.controllerData[Controller].ChannelMode;
+
+ switch(PduModeRequest)
+ {
+ case CANIF_SET_OFFLINE:
+ CanIf_Global.controllerData[Controller].ChannelMode = CANIF_GET_OFFLINE;
+ break;
+ case CANIF_SET_RX_OFFLINE:
+ if (oldMode == CANIF_GET_RX_ONLINE)
+ CanIf_Global.controllerData[Controller].ChannelMode = CANIF_GET_OFFLINE;
+ else if (oldMode == CANIF_GET_ONLINE)
+ CanIf_Global.controllerData[Controller].ChannelMode = CANIF_GET_TX_ONLINE;
+ else if (oldMode == CANIF_GET_OFFLINE_ACTIVE_RX_ONLINE)
+ CanIf_Global.controllerData[Controller].ChannelMode = CANIF_GET_OFFLINE_ACTIVE;
+
+ // Other oldmodes don't care
+ break;
+ case CANIF_SET_RX_ONLINE:
+ if (oldMode == CANIF_GET_OFFLINE)
+ CanIf_Global.controllerData[Controller].ChannelMode = CANIF_GET_RX_ONLINE;
+ else if (oldMode == CANIF_GET_TX_ONLINE)
+ CanIf_Global.controllerData[Controller].ChannelMode = CANIF_GET_ONLINE;
+ else if (oldMode == CANIF_GET_OFFLINE_ACTIVE)
+ CanIf_Global.controllerData[Controller].ChannelMode = CANIF_GET_OFFLINE_ACTIVE_RX_ONLINE;
+
+ // Other oldmodes don't care
+ break;
+ case CANIF_SET_TX_OFFLINE:
+ if (oldMode == CANIF_GET_TX_ONLINE)
+ CanIf_Global.controllerData[Controller].ChannelMode = CANIF_GET_OFFLINE;
+ else if (oldMode == CANIF_GET_ONLINE)
+ CanIf_Global.controllerData[Controller].ChannelMode = CANIF_GET_RX_ONLINE;
+ else if (oldMode == CANIF_GET_OFFLINE_ACTIVE)
+ CanIf_Global.controllerData[Controller].ChannelMode = CANIF_GET_OFFLINE;
+ else if (oldMode == CANIF_GET_OFFLINE_ACTIVE_RX_ONLINE)
+ CanIf_Global.controllerData[Controller].ChannelMode = CANIF_GET_RX_ONLINE;
+
+ // Other oldmodes don't care
+ break;
+ case CANIF_SET_TX_ONLINE:
+ if (oldMode == CANIF_GET_OFFLINE)
+ CanIf_Global.controllerData[Controller].ChannelMode = CANIF_GET_TX_ONLINE;
+ else if (oldMode == CANIF_GET_RX_ONLINE)
+ CanIf_Global.controllerData[Controller].ChannelMode = CANIF_GET_ONLINE;
+ else if (oldMode == CANIF_GET_OFFLINE_ACTIVE)
+ CanIf_Global.controllerData[Controller].ChannelMode = CANIF_GET_TX_ONLINE;
+ else if (oldMode == CANIF_GET_OFFLINE_ACTIVE_RX_ONLINE)
+ CanIf_Global.controllerData[Controller].ChannelMode = CANIF_GET_ONLINE;
+
+ // Other oldmodes don't care
+ break;
+ case CANIF_SET_ONLINE:
+ CanIf_Global.controllerData[Controller].ChannelMode = CANIF_GET_ONLINE;
+ break;
+
+ case CANIF_SET_TX_OFFLINE_ACTIVE:
+ if (oldMode == CANIF_GET_OFFLINE)
+ CanIf_Global.controllerData[Controller].ChannelMode = CANIF_GET_OFFLINE_ACTIVE;
+ else if (oldMode == CANIF_GET_RX_ONLINE)
+ CanIf_Global.controllerData[Controller].ChannelMode = CANIF_GET_OFFLINE_ACTIVE_RX_ONLINE;
+ else if (oldMode == CANIF_GET_TX_ONLINE)
+ CanIf_Global.controllerData[Controller].ChannelMode = CANIF_GET_OFFLINE_ACTIVE;
+ else if (oldMode == CANIF_GET_ONLINE)
+ CanIf_Global.controllerData[Controller].ChannelMode = CANIF_GET_OFFLINE_ACTIVE_RX_ONLINE;
+
+ // Other oldmodes don't care
+ break;
+ }
+
+ return E_OK;
+}
+
+//-------------------------------------------------------------------
+
+Std_ReturnType CanIf_GetPduMode(uint8 Controller,
+ CanIf_ChannelGetModeType *PduModePtr)
+{
+ VALIDATE( CanIf_Global.initRun, CANIF_GETPDUMODE_ID, CANIF_E_UNINIT );
+ VALIDATE( Controller < GET_CONTROLLER_CNT(), CANIF_GETPDUMODE_ID, CANIF_E_PARAM_CONTROLLER );
+
+ *PduModePtr = CanIf_Global.controllerData[Controller].ChannelMode;
+
+ return E_OK;
+}
+
+#if ( CANIF_SETDYNAMICTXID_API == STD_ON )
+void CanIf_SetDynamicTxId(PduIdType CanTxPduId, Can_IdType CanId)
+{
+ const CanIf_TxPduConfigType *txEntry;
+ VALIDATE(FALSE, CANIF_SETDYNAMICTX_ID, CANIF_E_NOK_NOSUPPORT);
+ VALIDATE_NO_RV(CanIf_Global.initRun, CANIF_SETDYNAMICTX_ID, CANIF_E_UNINIT );
+
+ // Get the controller from L-PDU handle
+ txEntry = CanIf_FindTxPduEntry(CanTxPduId);
+
+ if (txEntry == 0)
+ {
+ VALIDATE_NO_RV(FALSE, CANIF_SETDYNAMICTX_ID, CANIF_E_INVALID_TXPDUID);
+ return;
+ }
+
+ // Check that this is a dymanic PDU
+ if (txEntry->CanIfCanTxPduType != ECORE_PDU_TYPE_DYNAMIC)
+ {
+ VALIDATE_NO_RV(FALSE, CANIF_SETDYNAMICTX_ID, CANIF_E_INVALID_TXPDUID);
+ return;
+ }
+
+ // Check that this is an extended or standard id
+ if (((CanId & 0x80000000) && (txEntry->CanIfTxPduIdCanIdType == ECORE_CAN_ID_TYPE_29)) ||
+ (((CanId & 0x80000000) == 0) && (txEntry->CanIfTxPduIdCanIdType == ECORE_CAN_ID_TYPE_11)))
+ {
+ // Update the CanID
+ //txEntry->CanIfCanTxPduIdCanId = CanId; // TODO How do we fix this from a const pointer
+
+ // NOT SUPPORTED
+ }
+ else
+ {
+ // Inavlid Canid to configuration
+ VALIDATE_NO_RV(FALSE, CANIF_SETDYNAMICTX_ID, CANIF_E_PARAM_CANID);
+ }
+}
+#endif
+
+#if ( CANIF_TRANSCEIVER_API == STD_ON )
+Std_ReturnType CanIf_SetTransceiverMode(uint8 Transceiver,
+ CanIf_TransceiverModeType TransceiverMode)
+{
+ VALIDATE(FALSE, CANIF_SET_TRANSCEIVERMODE_ID, CANIF_E_NOK_NOSUPPORT);
+// Not supported
+
+ return E_NOT_OK;
+}
+
+Std_ReturnType CanIf_GetTransceiverMode(uint8 Transceiver,
+ CanIf_TransceiverModeType *TransceiverModePtr)
+{
+ VALIDATE(FALSE, CANIF_GET_TRANSCEIVERMODE_ID, CANIF_E_NOK_NOSUPPORT);
+ // Not supported
+
+ return E_NOT_OK;
+}
+
+Std_ReturnType CanIf_GetTrcvWakeupReason(uint8 Transceiver,
+ CanIf_TrcvWakeupReasonType *TrcvWuReasonPtr)
+{
+ VALIDATE(FALSE, CANIF_GET_TRCVMODEREASON_ID, CANIF_E_NOK_NOSUPPORT);
+ // Not supported
+
+ return E_NOT_OK;
+}
+
+Std_ReturnType CanIf_SetTransceiverWakeupMode(uint8 Transceiver,
+ CanIf_TrcvWakeupModeType *TrcvWakeupMode)
+{
+ VALIDATE(FALSE, CANIF_SET_TRANSCEIVERWAKEMODE_ID, CANIF_E_NOK_NOSUPPORT);
+ // Not supported
+
+ return E_NOT_OK;
+}
+#endif
+
+#if ( CANIF_WAKEUP_EVENT_API == STD_ON )
+Std_ReturnType CanIf_CheckWakeup(EcuM_WakeupSourceType WakeupSource)
+{
+ VALIDATE(FALSE, CANIF_CHECKWAKEUP_ID, CANIF_E_NOK_NOSUPPORT);
+ // Not supported
+
+ return E_NOT_OK;
+}
+
+Std_ReturnType CanIf_CheckValidation(EcuM_WakeupSourceType WakeupSource)
+{
+ VALIDATE(FALSE, CANIF_CHECKVALIDATION_ID, CANIF_E_NOK_NOSUPPORT);
+ // Not supported
+
+ return E_NOT_OK;
+}
+#endif
+
+/*
+ * Callback interface from driver
+ */
+void CanIf_TxConfirmation(PduIdType canTxPduId)
+{
+ VALIDATE_NO_RV(CanIf_Global.initRun, CANIF_TXCONFIRMATION_ID, CANIF_E_UNINIT)
+
+ const CanIf_TxPduConfigType *entry =
+ CanIf_ConfigPtr->InitConfig->CanIfTxPduConfigPtr;
+
+ /* Find the CAN id in the TxPduList */
+ for (uint16 i = 0; i < CanIf_ConfigPtr->InitConfig->CanIfNumberOfCanTXPduIds; i++)
+ {
+ if (entry->CanIfTxPduId == canTxPduId)
+ {
+ if (entry->CanIfUserTxConfirmation != NULL)
+ {
+ CanIf_ChannelGetModeType mode;
+ CanIf_GetPduMode(entry->CanIfCanTxPduHthRef->CanIfCanControllerIdRef, &mode);
+ if ((mode == CANIF_GET_TX_ONLINE) || (mode == CANIF_GET_ONLINE)
+ || (mode == CANIF_GET_OFFLINE_ACTIVE) || (mode == CANIF_GET_OFFLINE_ACTIVE_RX_ONLINE) )
+ {
+ entry->CanIfUserTxConfirmation(canTxPduId); /* CANIF053 */
+ }
+ }
+ return;
+ }
+
+ entry++;
+ }
+
+ // Did not find the PDU, something is wrong
+ VALIDATE_NO_RV(FALSE, CANIF_TXCONFIRMATION_ID, CANIF_E_PARAM_LPDU);
+}
+
+void CanIf_RxIndication(uint8 Hrh, Can_IdType CanId, uint8 CanDlc,
+ const uint8 *CanSduPtr)
+{
+ VALIDATE_NO_RV(CanIf_Global.initRun, CANIF_RXINDICATION_ID, CANIF_E_UNINIT);
+ VALIDATE_NO_RV(CanSduPtr != NULL, CANIF_RXINDICATION_ID, CANIF_E_PARAM_POINTER);
+
+ /* Check PDU mode before continue processing */
+ CanIf_ChannelGetModeType mode;
+ sint8 controller = CanIf_FindHrhCtrl(Hrh);
+ if (controller == -1) // Invalid HRH
+ {
+ return;
+ }
+
+ if (CanIf_GetPduMode(controller, &mode) == E_OK)
+ {
+ if (mode == CANIF_GET_OFFLINE || mode == CANIF_GET_TX_ONLINE ||
+ mode == CANIF_GET_OFFLINE_ACTIVE)
+ {
+ // Receiver path is disabled so just drop it
+ return;
+ }
+ }
+ else
+ {
+ return; // No mode so just return
+ }
+
+ const CanIf_RxPduConfigType *entry = CanIf_ConfigPtr->InitConfig->CanIfRxPduConfigPtr;
+
+ /* Find the CAN id in the RxPduList */
+ for (uint16 i = 0; i < CanIf_ConfigPtr->InitConfig->CanIfNumberOfCanRxPduIds; i++)
+ {
+ if (entry->CanIfCanRxPduHrhRef->CanIfHrhIdSymRef == Hrh)
+ {
+ // Software filtering
+ if (entry->CanIfCanRxPduHrhRef->CanIfHrhType == CAN_ECORE_HANDLE_TYPE_BASIC)
+ {
+ if (entry->CanIfCanRxPduHrhRef->CanIfSoftwareFilterHrh)
+ {
+ if (entry->CanIfSoftwareFilterType == CANIF_SOFTFILTER_TYPE_MASK)
+ {
+ if ((CanId & entry->CanIfCanRxPduCanIdMask ) ==
+ ( entry->CanIfCanRxPduCanId & entry->CanIfCanRxPduCanIdMask))
+ {
+ // We found a pdu so call higher layers
+ }
+ else
+ {
+ entry++;
+ continue; // Not a supported filter type, so just drop the frame
+ }
+ }
+ else
+ {
+ DET_REPORTERROR(MODULE_ID_CAN, 0, CANIF_RXINDICATION_ID, CANIF_E_PARAM_HRH);
+ continue; // Not a supported filter type, so just drop the frame
+ }
+ }
+ }
+
+#if (CANIF_DLC_CHECK == STD_ON)
+ if (CanDlc < entry->CanIfCanRxPduDlc)
+ {
+ VALIDATE_NO_RV(FALSE, CANIF_RXINDICATION_ID, CANIF_E_PARAM_DLC);
+ return;
+ }
+#endif
+
+ switch (entry->CanIfRxUserType)
+ {
+ case CANIF_USER_TYPE_CAN_SPECIAL:
+ {
+ ((CanIf_FuncTypeCanSpecial) (entry->CanIfUserRxIndication))(entry->CanIfCanRxPduId,
+ CanSduPtr, CanDlc, CanId);
+ return;
+ }
+ break;
+ case CANIF_USER_TYPE_CAN_NM:
+ case CANIF_USER_TYPE_CAN_PDUR:
+ // Send Can frame to PDU router
+ PduR_CanIfRxIndication(entry->CanIfCanRxPduId,CanSduPtr);
+ return;
+ break;
+
+ case CANIF_USER_TYPE_CAN_TP:
+ continue; // Not supported yet
+ return;
+ break;
+ }
+ }
+
+ entry++;
+ }
+
+ // Did not find the PDU, something is wrong
+ VALIDATE_NO_RV(FALSE, CANIF_RXINDICATION_ID, CANIF_E_PARAM_LPDU);
+}
+
+#if ( CANIF_TRANSMIT_CANCELLATION == STD_ON )
+void CanIf_CancelTxConfirmation(const Can_PduType *PduInfoPtr)
+{
+ VALIDATE(FALSE, CANIF_CANCELTXCONFIRMATION_ID, CANIF_E_NOK_NOSUPPORT);
+ VALIDATE_NO_RV(CanIf_Global.initRun, CANIF_CANCELTXCONFIRMATION_ID, CANIF_E_UNINIT);
+ VALIDATE_NO_RV(PduInfoPtr != NULL, CANIF_RXINDICATION_ID, CANIF_E_PARAM_POINTER);
+
+ const CanIf_TxPduConfigType *entry =
+ CanIf_ConfigPtr->InitConfig->CanIfTxPduConfigPtr;
+
+ /* Find the CAN id in the TxPduList */
+ for (uint16 i = 0; i < CanIf_ConfigPtr->InitConfig->CanIfNumberOfCanTXPduIds; i++)
+ {
+ if (entry->CanIfTxPduId == canTxPduId)
+ {
+ // Not supported
+ return;
+ }
+
+ entry++;
+ }
+
+ // Did not find the PDU, something is wrong
+ VALIDATE_NO_RV(FALSE, CANIF_TXCONFIRMATION_ID, CANIF_E_PARAM_LPDU);
+}
+#endif
+
+void CanIf_ControllerBusOff(uint8 Controller)
+{
+ VALIDATE_NO_RV( CanIf_Global.initRun, CANIF_CONTROLLER_BUSOFF_ID, CANIF_E_UNINIT );
+ VALIDATE_NO_RV( Controller < GET_CONTROLLER_CNT(), CANIF_CONTROLLER_BUSOFF_ID, CANIF_E_PARAM_CONTROLLER );
+
+ // According to figure 35 in canif spec this should be done in
+ // Can driver but it is better to do it here
+ CanIf_SetControllerMode(Controller, CANIF_CS_STOPPED);
+
+ if (CanIf_ConfigPtr->DispatchConfig->CanIfBusOffNotification != NULL)
+ {
+ CanIf_ConfigPtr->DispatchConfig->CanIfBusOffNotification(Controller);
+ }
+}
+
+void CanIf_SetWakeupEvent(uint8 Controller)
+{
+ VALIDATE_NO_RV(FALSE, CANIF_SETWAKEUPEVENT_ID, CANIF_E_NOK_NOSUPPORT);
+ VALIDATE_NO_RV( CanIf_Global.initRun, CANIF_SETWAKEUPEVENT_ID, CANIF_E_UNINIT );
+ VALIDATE_NO_RV( Controller < GET_CONTROLLER_CNT(), CANIF_SETWAKEUPEVENT_ID, CANIF_E_PARAM_CONTROLLER );
+
+ // Not supported
+}
+
+void CanIf_EcoreError(uint8 Controller, Can_EcoreErrorType Error)
+{
+ VALIDATE_NO_RV( CanIf_Global.initRun, CANIF_ECOREERROR_ID, CANIF_E_UNINIT );
+ VALIDATE_NO_RV( Controller < GET_CONTROLLER_CNT(), CANIF_ECOREERROR_ID, CANIF_E_PARAM_CONTROLLER );
+
+ if (CanIf_ConfigPtr->DispatchConfig->CanIfErrorNotificaton != NULL)
+ {
+ CanIf_ConfigPtr->DispatchConfig->CanIfErrorNotificaton(Controller, Error);
+ }
+}
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef CAN_TEST_H_\r
+#define CAN_TEST_H_\r
+\r
+void CT_CanIf_TxConfirmation_Called( PduIdType canTxPduId );\r
+void CT_CanIf_RxIndication_Called( uint8 Hrh,Can_IdType CanId,uint8 CanDlc, const uint8 *CanSduPtr );\r
+void CT_CanIf_CancelTxConfirmation_Called( const Can_PduType *PduInfoPtr );\r
+void CT_CanIf_ControllerBusOff_Called( uint8 Controller );\r
+void CT_CanIf_ControllerWakeup_Called( uint8 Controller );\r
+\r
+#endif /*CAN_TEST_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*\r
+ * ports: PBxx to PJxx with xx ranging from 0 to 15\r
+ *\r
+ */\r
+\r
+#include "Std_Types.h"\r
+#include "Dio.h"\r
+#include "Det.h"\r
+#include <string.h>\r
+#include "mpc55xx.h"\r
+\r
+#if ( DIO_VERSION_INFO_API == STD_ON )\r
+static Std_VersionInfoType _Dio_VersionInfo =\r
+{\r
+ .vendorID = (uint16)1,\r
+ .moduleID = (uint16)1,\r
+ .instanceID = (uint8)1,\r
+ .sw_major_version = (uint8)DIO_SW_MAJOR_VERSION,\r
+ .sw_minor_version = (uint8)DIO_SW_MINOR_VERSION,\r
+ .sw_patch_version = (uint8)DIO_SW_PATCH_VERSION,\r
+ .ar_major_version = (uint8)DIO_AR_MAJOR_VERSION,\r
+ .ar_minor_version = (uint8)DIO_AR_MINOR_VERSION,\r
+ .ar_patch_version = (uint8)DIO_AR_PATCH_VERSION,\r
+};\r
+#endif\r
+\r
+#if ( DIO_DEV_ERROR_DETECT == STD_ON )\r
+static int Channel_Config_Contains(Dio_ChannelType channelId)\r
+{\r
+ Dio_ChannelType* ch_ptr=(Dio_ChannelType*)CHANNEL_PTR;\r
+ int rv=0;\r
+ while (DIO_END_OF_LIST!=*ch_ptr)\r
+ {\r
+ if (*ch_ptr==channelId)\r
+ { rv=1; break;}\r
+ ch_ptr++;\r
+ }\r
+ return rv;\r
+}\r
+\r
+static int Port_Config_Contains(Dio_PortType portId)\r
+{\r
+ Dio_PortType* port_ptr=(Dio_PortType*)PORT_PTR;\r
+ int rv=0;\r
+ while (DIO_END_OF_LIST!=*port_ptr)\r
+ {\r
+ if (*port_ptr==portId)\r
+ { rv=1; break;}\r
+ port_ptr++;\r
+ }\r
+ return rv;\r
+}\r
+\r
+static int Channel_Group_Config_Contains(const Dio_ChannelGroupType* _channelGroupIdPtr)\r
+{\r
+ Dio_ChannelGroupType* chGrp_ptr=(Dio_ChannelGroupType*)CHANNEL_GRP_PTR;\r
+ int rv=0;\r
+\r
+ while (DIO_END_OF_LIST!=chGrp_ptr->port)\r
+ {\r
+ if (chGrp_ptr->port==_channelGroupIdPtr->port&&\r
+ chGrp_ptr->offset==_channelGroupIdPtr->offset&&\r
+ chGrp_ptr->mask==_channelGroupIdPtr->mask)\r
+ { rv=1; break;}\r
+ chGrp_ptr++;\r
+ }\r
+ return rv;\r
+}\r
+\r
+#define VALIDATE_CHANNEL(_channelId, _api) \\r
+ if(0==Channel_Config_Contains(channelId)) { \\r
+ Det_ReportError(MODULE_ID_DIO,0,_api,DIO_E_PARAM_INVALID_CHANNEL_ID ); \\r
+ level = 0; \\r
+ goto cleanup; \\r
+ }\r
+#define VALIDATE_PORT(_portId, _api)\\r
+ if(0==Port_Config_Contains(_portId)) {\\r
+ Det_ReportError(MODULE_ID_DIO,0,_api,DIO_E_PARAM_INVALID_PORT_ID ); \\r
+ level = STD_LOW;\\r
+ goto cleanup;\\r
+ }\r
+#define VALIDATE_CHANNELGROUP(_channelGroupIdPtr, _api)\\r
+ if(0==Channel_Group_Config_Contains(_channelGroupIdPtr)) {\\r
+ Det_ReportError(MODULE_ID_DIO,0,_api,DIO_E_PARAM_INVALID_GROUP_ID ); \\r
+ level = STD_LOW;\\r
+ goto cleanup;\\r
+ }\r
+#else\r
+#define VALIDATE_CHANNEL(_channelId, _api)\r
+#define VALIDATE_PORT(_portId, _api)\r
+#define VALIDATE_CHANNELGROUP(_channelGroupIdPtr, _api)\r
+#endif\r
+\r
+Dio_LevelType Dio_ReadChannel(Dio_ChannelType channelId)\r
+{\r
+ Dio_LevelType level;\r
+ VALIDATE_CHANNEL(channelId, DIO_READCHANNEL_ID);\r
+ // Read level from SIU.\r
+ if (SIU.GPDI [channelId].R)\r
+ {\r
+ level = STD_HIGH;\r
+ } else\r
+ {\r
+ level = STD_LOW;\r
+ }\r
+ cleanup: return (level);\r
+}\r
+\r
+void Dio_WriteChannel(Dio_ChannelType channelId, Dio_LevelType level)\r
+{\r
+ VALIDATE_CHANNEL(channelId, DIO_WRITECHANNEL_ID);\r
+ // Write level to SIU.\r
+ SIU.GPDO [channelId].R = level;\r
+ cleanup: return;\r
+}\r
+\r
+Dio_PortLevelType Dio_ReadPort(Dio_PortType portId)\r
+{\r
+ Dio_LevelType level;\r
+ VALIDATE_PORT(portId, DIO_READPORT_ID);\r
+\r
+#if defined(CFG_MPC5554)||defined(CFG_MPC5567)\r
+ vuint16_t *ptr = (vuint16_t *)&SIU.GPDI;\r
+#else\r
+ vuint16_t *ptr = (vuint16_t *)&SIU.PGPDI0; // The GPDI 0-3 is organized in 32bit chunks but we want to step them in 16bit port-widths\r
+#endif\r
+ level = ptr[portId]; // Read the bit pattern (16bits) to the port\r
+ cleanup: return level;\r
+}\r
+\r
+void Dio_WritePort(Dio_PortType portId, Dio_PortLevelType level)\r
+{\r
+ VALIDATE_PORT(portId, DIO_WRITEPORT_ID);\r
+\r
+ // find address of first port\r
+#if defined(CFG_MPC5554)||defined(CFG_MPC5567)\r
+ vuint16_t *ptr = (vuint16_t *)&SIU.GPDO;\r
+#else\r
+ vuint16_t *ptr = (vuint16_t *)&SIU.PGPDO0; // The GPDO 0-3 is organized in 32bit chunks but we want to step them in 16bit port-widths\r
+#endif\r
+ ptr[portId] = level; // Write the bit pattern (16bits) to the port\r
+ cleanup: return;\r
+}\r
+\r
+Dio_PortLevelType Dio_ReadChannelGroup(\r
+ const Dio_ChannelGroupType *channelGroupIdPtr)\r
+{\r
+ Dio_LevelType level;\r
+ VALIDATE_CHANNELGROUP(channelGroupIdPtr,DIO_READCHANNELGROUP_ID);\r
+\r
+ // find address of first port\r
+#if defined(CFG_MPC5554)||defined(CFG_MPC5567)\r
+ vuint16_t *ptr = (vuint16_t *)&SIU.GPDI;\r
+#else\r
+ uint16 *ptr = (uint16 *)&SIU.PGPDI0; // The GPDI 0-3 is organized in 32bit chunks but we want to step them in 16bit port-widths\r
+#endif\r
+\r
+ // Get masked values\r
+ level = ptr[channelGroupIdPtr->port] & channelGroupIdPtr->mask;\r
+\r
+ // Shift down\r
+ level<<=channelGroupIdPtr->offset;\r
+ cleanup: return level;\r
+}\r
+\r
+void Dio_WriteChannelGroup(const Dio_ChannelGroupType *channelGroupIdPtr,\r
+ Dio_PortLevelType level)\r
+{\r
+#if defined(CFG_MPC5516)\r
+ VALIDATE_CHANNELGROUP(channelGroupIdPtr,DIO_WRITECHANNELGROUP_ID);\r
+ // find address of first port of the masked register\r
+ uint32 *ptr = (uint32 *)&SIU.MPGPDO0; // The GPDI 0-3 is organized in 32bit chunks but we want to step them in 16bit port-widths\r
+\r
+ // Build the 32 bits Mask_Valule, and write to masked output register\r
+ ptr[channelGroupIdPtr->port] = (channelGroupIdPtr->mask << 16)&((level\r
+ <<channelGroupIdPtr->offset)|0xFFFF);\r
+ cleanup: return;\r
+#else\r
+ return;\r
+#endif\r
+}\r
+\r
+#if (DIO_VERSION_INFO_API == STD_ON)\r
+void Dio_GetVersionInfo(Std_VersionInfoType *versionInfo)\r
+{\r
+ memcpy(versionInfo, &_Dio_VersionInfo, sizeof(Std_VersionInfoType));\r
+}\r
+#endif\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include <assert.h>\r
+\r
+#include "Std_Types.h"\r
+#include "mpc55xx.h"\r
+#include "Mcu.h"\r
+#include "Dma.h"\r
+\r
+void Dma_Init (const Dma_ConfigType *ConfigPtr)\r
+{\r
+ Dma_ChannelType channel;\r
+ for (channel = 0; channel < DMA_NUMBER_OF_CHANNELS; channel++)\r
+ {\r
+#if defined(CFG_MPC5516) || defined(CFG_MPC5517)\r
+ /* DMA mux configuration. */\r
+ DMAMUX.CHCONFIG[channel].B.ENBL = ConfigPtr->dmaMuxConfigPtr[channel].DMA_CHANNEL_ENABLE;\r
+ DMAMUX.CHCONFIG[channel].B.TRIG = ConfigPtr->dmaMuxConfigPtr[channel].DMA_CHANNEL_TRIG_ENABLE;\r
+ DMAMUX.CHCONFIG[channel].B.SOURCE = ConfigPtr->dmaMuxConfigPtr[channel].DMA_CHANNEL_SOURCE;\r
+#endif\r
+\r
+ /* DMA channel configration. */\r
+ EDMA.CPR[channel].B.ECP = ConfigPtr->dmaChannelConfigPtr[channel].DMA_CHANNEL_PREEMTION_ENABLE;\r
+ EDMA.CPR[channel].B.CHPRI = ConfigPtr->dmaChannelConfigPtr[channel].DMA_CHANNEL_PRIORITY;\r
+ }\r
+\r
+ /* Write channel arbitration mode. */\r
+ EDMA.CR.B.ERCA = ConfigPtr->dmaChannelArbitration;\r
+}\r
+\r
+void Dma_ConfigureChannel (struct tcd_t *tcd, Dma_ChannelType channel)\r
+{\r
+ /* Copy transfer configuration to correct channel. */\r
+ EDMA.TCD[channel] = *tcd;\r
+\r
+ /* Disable channel. */\r
+ EDMA.CERQR.R = channel;\r
+\r
+ /* Check configuration. */\r
+ if (EDMA.ESR.B.VLD)\r
+ {\r
+ assert(0);\r
+ }\r
+ else\r
+ {\r
+ /* Configuration seems to be OK. Do nothing. */\r
+ }\r
+}\r
+\r
+struct tcd_t * Dma_GetTcd( Dma_ChannelType channel ) {\r
+ return &EDMA.TCD[channel];\r
+}\r
+\r
+boolean Dma_CheckConfig( void ) {\r
+ /* Check configuration. */\r
+ if (EDMA.ESR.B.VLD)\r
+ {\r
+ assert(0);\r
+ }\r
+ else\r
+ {\r
+ /* Configuration seems to be OK. Do nothing. */\r
+ }\r
+ return TRUE;\r
+}\r
+\r
+void Dma_ConfigureChannelTranferSize (uint32_t nbrOfIterations, Dma_ChannelType channel)\r
+{\r
+ EDMA.TCD[channel].BITER = nbrOfIterations;\r
+ EDMA.TCD[channel].CITER = nbrOfIterations;\r
+}\r
+\r
+void Dma_ConfigureChannelSourceCorr (uint32_t sourceCorrection, Dma_ChannelType channel)\r
+{\r
+ EDMA.TCD[channel].SLAST = sourceCorrection;\r
+}\r
+\r
+void Dma_ConfigureChannelDestinationCorr (uint32_t destinationCorrection, Dma_ChannelType channel)\r
+{\r
+ EDMA.TCD[channel].DLAST_SGA = destinationCorrection;\r
+}\r
+\r
+void Dma_ConfigureDestinationAddress (uint32_t destAddr, Dma_ChannelType channel)\r
+{\r
+ EDMA.TCD[channel].DADDR = destAddr;\r
+}\r
+\r
+void Dma_ConfigureSourceAddress (uint32_t sourceAddr, Dma_ChannelType channel)\r
+{\r
+ EDMA.TCD[channel].SADDR = sourceAddr;\r
+}\r
+\r
+int Dma_Active(Dma_ChannelType channel) {\r
+ return EDMA.TCD[channel].ACTIVE;\r
+}\r
+\r
+void Dma_StartChannel (Dma_ChannelType channel)\r
+{\r
+ /* Start the channel... */\r
+ EDMA.SERQR.R = channel;\r
+}\r
+\r
+#if 0\r
+void Dma_EnableInterrupt (Dma_ChannelType channel)\r
+{\r
+ /* Start the channel... */\r
+ EDMA.IRQRL.R = (1<<channel);\r
+}\r
+#endif\r
+\r
+void Dma_ClearInterrupt (Dma_ChannelType channel)\r
+{\r
+ /* Start the channel... */\r
+ EDMA.CIRQR.R = channel;\r
+}\r
+\r
+\r
+\r
+void Dma_StopChannel (Dma_ChannelType channel)\r
+{\r
+ /* Stop the channel... */\r
+ EDMA.CERQR.R = channel;\r
+}\r
+\r
+Std_ReturnType Dma_ChannelDone (Dma_ChannelType channel)\r
+{\r
+ Std_ReturnType returnValue;\r
+\r
+ returnValue = EDMA.TCD[channel].DONE;\r
+\r
+ return (returnValue);\r
+}\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef DMA_H_\r
+#define DMA_H_\r
+\r
+\r
+#include "Std_Types.h"\r
+#include "Dma_Cfg.h"\r
+#include "mpc55xx.h"\r
+\r
+typedef enum\r
+{\r
+ DMA_CHANNEL_DISABLED,\r
+ DMA_SCI_A_COMBTX,\r
+ DMA_SCI_A_COMBRX,\r
+ DMA_SCI_B_COMBTX,\r
+ DMA_SCI_B_COMBRX,\r
+ DMA_SCI_C_COMBTX,\r
+ DMA_SCI_C_COMBRX,\r
+ DMA_SCI_D_COMBTX,\r
+ DMA_SCI_D_COMBRX,\r
+ DMA_SCI_E_COMBTX,\r
+ DMA_SCI_E_COMBRX,\r
+ DMA_SCI_F_COMBTX,\r
+ DMA_SCI_F_COMBRX,\r
+ DMA_SCI_G_COMBTX,\r
+ DMA_SCI_G_COMBRX,\r
+ DMA_SCI_H_COMBTX,\r
+ DMA_SCI_H_COMBRX,\r
+\r
+ DMA_DSPI_A_SR_TFFF,\r
+ DMA_DSPI_A_SR_RFRD,\r
+ DMA_DSPI_B_SR_TFFF,\r
+ DMA_DSPI_B_SR_RFRD,\r
+ DMA_DSPI_C_SR_TFFF,\r
+ DMA_DSPI_C_SR_RFRD,\r
+ DMA_DSPI_D_SR_TFFF,\r
+ DMA_DSPI_D_SR_RFRD,\r
+\r
+ DMA_EMIOS200_FLAG_F0,\r
+ DMA_EMIOS200_FLAG_F1,\r
+ DMA_EMIOS200_FLAG_F2,\r
+ DMA_EMIOS200_FLAG_F3,\r
+ DMA_EMIOS200_FLAG_F4,\r
+ DMA_EMIOS200_FLAG_F5,\r
+ DMA_EMIOS200_FLAG_F6,\r
+ DMA_EMIOS200_FLAG_F7,\r
+ DMA_EMIOS200_FLAG_F8,\r
+ DMA_EMIOS200_FLAG_F9,\r
+ DMA_EMIOS200_FLAG_F10,\r
+ DMA_EMIOS200_FLAG_F11,\r
+ DMA_EMIOS200_FLAG_F12,\r
+ DMA_EMIOS200_FLAG_F13,\r
+ DMA_EMIOS200_FLAG_F14,\r
+ DMA_EMIOS200_FLAG_F15,\r
+\r
+ DMA_IIC_A_TX,\r
+ DMA_IIC_A_RX,\r
+\r
+ DMA_RESERVED1,\r
+ DMA_RESERVED2,\r
+\r
+ DMA_SIU_EISR_EIF1,\r
+ DMA_SIU_EISR_EIF2,\r
+ DMA_SIU_EISR_EIF3,\r
+ DMA_SIU_EISR_EIF4,\r
+\r
+ DMA_EQADC_FISR0_RFDF0,\r
+ DMA_EQADC_FISR0_CFFF0,\r
+ DMA_EQADC_FISR1_RFDF0,\r
+ DMA_EQADC_FISR1_CFFF0,\r
+\r
+ DMA_MLB_DMA_REQ,\r
+\r
+ DMA_RESERVED3,\r
+ DMA_RESERVED4,\r
+\r
+ DMA_ALWAYS_ENABLED1,\r
+ DMA_ALWAYS_ENABLED2,\r
+ DMA_ALWAYS_ENABLED3,\r
+ DMA_ALWAYS_ENABLED4,\r
+ DMA_ALWAYS_ENABLED5,\r
+ DMA_ALWAYS_ENABLED6,\r
+ DMA_ALWAYS_ENABLED7,\r
+ DMA_ALWAYS_ENABLED8\r
+}Dma_MuxChannels;\r
+\r
+typedef struct\r
+{\r
+ vuint8_t DMA_CHANNEL_ENABLE;\r
+ vuint8_t DMA_CHANNEL_TRIG_ENABLE;\r
+ Dma_MuxChannels DMA_CHANNEL_SOURCE;\r
+} Dma_MuxConfigType;\r
+\r
+typedef struct\r
+{\r
+ vuint8_t DMA_CHANNEL_PRIORITY;\r
+ vuint8_t DMA_CHANNEL_PREEMTION_ENABLE;\r
+}Dma_ChannelConfigType;\r
+\r
+typedef enum\r
+{\r
+ DMA_TRANSFER_SIZE_8BITS,\r
+ DMA_TRANSFER_SIZE_16BITS,\r
+ DMA_TRANSFER_SIZE_32BITS,\r
+ DMA_TRANSFER_SIZE_64BITS,\r
+ DMA_TRANSFER_SIZE_16BYTES_BURST,\r
+ DMA_TRANSFER_SIZE_32BYTES_BURST\r
+}Dma_DataTranferSizeType;\r
+\r
+typedef enum\r
+{\r
+ DMA_FIXED_PRIORITY_ARBITRATION,\r
+ DMA_ROUND_ROBIN_ARBITRATION\r
+}Dma_ChannelArbitrationType;\r
+\r
+typedef struct\r
+{
+ // 5567 has no Dma Mux, but maybe this should be left in anyway?\r
+#if defined(CFG_MPC5516) || defined(CFG_MPC5517)\r
+ const Dma_MuxConfigType *dmaMuxConfigPtr;\r
+#endif\r
+ const Dma_ChannelConfigType *dmaChannelConfigPtr;\r
+ const Dma_ChannelArbitrationType dmaChannelArbitration;\r
+}Dma_ConfigType;\r
+\r
+extern const Dma_ConfigType DmaConfig [];\r
+\r
+\r
+void Dma_Init (const Dma_ConfigType *ConfigPtr);\r
+void Dma_ConfigureChannel (struct tcd_t *tcd, Dma_ChannelType channel);\r
+void Dma_ConfigureChannelTranferSize (uint32_t nbrOfIterations, Dma_ChannelType channel);\r
+void Dma_ConfigureChannelSourceCorr (uint32_t sourceCorrection, Dma_ChannelType channel);\r
+void Dma_ConfigureChannelDestinationCorr (uint32_t destinationCorrection, Dma_ChannelType channel);\r
+void Dma_ConfigureDestinationAddress (uint32_t destAddr, Dma_ChannelType channel);\r
+void Dma_ConfigureSourceAddress (uint32_t sourceAddr, Dma_ChannelType channel);\r
+void Dma_StartChannel (Dma_ChannelType channel);\r
+void Dma_StopChannel (Dma_ChannelType channel);\r
+Std_ReturnType Dma_ChannelDone (Dma_ChannelType channel);\r
+struct tcd_t * Dma_GetTcd( Dma_ChannelType channel );\r
+boolean Dma_CheckConfig( void );\r
+\r
+#endif /* DMA_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+
+/*
+ * IMPLEMENTATION NOTES
+ * - The SPI implementation only supports 64 bytes in one go so this is
+ * a limitation for the EEP driver also.
+ * - The specification if SPI functions should be blocking or not. For now
+ * the driver uses blocking SPI communication.
+ */
+
+/* DEVICE SUPPORT
+ * STMicroelectronics:
+ * M95256
+ */
+
+/* REQUIREMENTS
+ * - EEP060
+ * Only EEP_WRITE_CYCLE_REDUCTION = STD_OFF is supported
+ *
+ * - EEP075
+ * MEMIF_COMPARE_UNEQUAL does not exist in the MemIf specification 1.2.1(rel 3.0 )
+ * So, it's not supported. It returns MEMIF_JOB_FAILED instead.
+ *
+ * - EEP084
+ * EepJobCallCycle not used
+ * We are not using interrupts so EEP_USE_INTERRUPTS must be STD_OFF
+ */
+
+
+#include "Eep.h"
+#include "Spi.h"
+//#include "Dem.h"
+#include "Det.h"
+#include <stdlib.h>
+#include <assert.h>
+#include <string.h>
+
+//#define USE_DEBUG 1
+#include "Trace.h"
+#define MODULE_NAME "/driver/Eep"
+
+// Define if you to check if the E2 seems sane at init..
+#define CHECK_SANE 1
+//#undef CHECK_SANE
+
+/* The width in bytes used by this eeprom */
+#define ADDR_LENGTH 2
+
+/* Helper macro for the process function */
+#define SET_STATE(_done,_state) done=(_done);job->state=(_state)
+
+#if ( EEP_DEV_ERROR_DETECT == STD_ON ) // Report DEV errors
+#define VALIDATE(_exp,_api,_err ) \
+ if( !(_exp) ) { \
+ Det_ReportError(MODULE_ID_GPT,0,_api,_err); \
+ return; \
+ }
+
+#define VALIDATE_W_RV(_exp,_api,_err,_rv ) \
+ if( !(_exp) ) { \
+ Det_ReportError(MODULE_ID_GPT,0,_api,_err); \
+ return (_rv); \
+ }
+
+#define VALID_CHANNEL(_ch) ( Gpt_Global.configured & (1<<(_ch)) )
+
+#else // Validate but do not report
+#define VALIDATE(_exp,_api,_err )\
+ if( !(_exp) ) { \
+ return; \
+ }
+#define VALIDATE_W_RV(_exp,_api,_err,_rv )\
+ if( !(_exp) ) { \
+ return (_rv); \
+ }
+#endif
+
+#if ( EEP_DEV_ERROR_DETECT == STD_ON )
+#define VALIDATE_CONFIG(_x) assert(_x)
+#define DET_REPORTERROR(_x,_y,_z,_q) Det_ReportError(MODULE_ID_EEP, _y, _z, _q)
+#else
+#define VALIDATE_CONFIG(_x)
+#define DET_REPORTERROR(_x,_y,_z,_q)
+#endif
+
+#define EEP_JOB_END_NOTIFICATION() \
+ if (Eep_Global.config->Eep_JobEndNotification!=NULL) { \
+ Eep_Global.config->Eep_JobEndNotification(); \
+ }
+
+#define EEP_JOB_ERROR_NOTIFICATION() \
+ if (Eep_Global.config->Eep_JobErrorNotification!=NULL) { \
+ Eep_Global.config->Eep_JobErrorNotification(); \
+ }
+
+/* Job state */
+typedef enum {
+ EEP_NONE,
+ EEP_COMPARE,
+ EEP_ERASE,
+ EEP_READ,
+ EEP_WRITE,
+} Eep_EcoreJobType;
+
+/* Spi job state */
+typedef enum {
+ JOB_MAIN,
+ JOB_READ_STATUS,
+ JOB_READ_STATUS_RESULT,
+} Job_StateType;
+
+/* Information about a job */
+typedef struct {
+ uint8 *targetAddr;
+ Eep_AddressType eepAddr;
+ uint32 left;
+ Job_StateType state;
+ Eep_EcoreJobType mainState;
+ Spi_SequenceType currSeq;
+ uint32 chunkSize;
+} Eep_JobInfoType;
+
+#define JOB_SET_STATE(_x,_y) job->state=(_x);job->mainState=(_y)
+
+
+/*
+ * Holds all global information that is needed by the driver
+ *
+ */
+typedef struct {
+ // The configuration
+ const Eep_ConfigType *config;
+
+ // Status of driver
+ MemIf_StatusType status;
+ MemIf_JobResultType jobResultType;
+ Eep_EcoreJobType jobType;
+
+ // Saved information from API calls.
+ MemIf_AddressType e2Addr;
+ uint8 *targetAddr;
+ MemIf_LengthType length;
+
+ // Data containers for EB buffers
+ Spi_DataType ebCmd;
+ Spi_DataType ebReadStatus;
+ Spi_DataType ebE2Addr[ADDR_LENGTH];
+ // What mode we are in ( normal/fast )
+ MemIf_ModeType mode;
+
+ // Hold job information
+ Eep_JobInfoType job;
+
+} Eep_GlobalType;
+
+#if 0
+#define SPI_TRANSMIT_FUNC(_x) Spi_SyncTransmit(_x)
+#else
+#define SPI_TRANSMIT_FUNC(_x,_y) Eep_AsyncTransmit(_x,_y)
+
+Std_ReturnType Eep_AsyncTransmit(Spi_SequenceType Sequence,Eep_JobInfoType *job) {
+ Std_ReturnType rv;
+ job->currSeq = Sequence;
+ rv = Spi_AsyncTransmit(Sequence);
+ return rv;
+}
+#endif
+
+#define CFG_P() Eep_Global.config
+
+Eep_GlobalType Eep_Global;
+
+/**
+ * Converts Eep_AddressType to one that can be read by SPI( Spi_DataType )
+ *
+ * @param spiAddr Pointer to an address were the result is written.
+ * @param eepAddr The Eep address to convert
+ */
+static void Spi_ConvertToSpiAddr(Spi_DataType *spiAddr, Eep_AddressType eepAddr ) {
+ spiAddr[1] = (eepAddr)&0xff;
+ spiAddr[0] = (eepAddr>>8)&0xff;
+}
+
+
+#if defined(CHECK_SANE)
+static void Eep_WREN( void ) {
+ Eep_Global.ebCmd = E2_WREN;
+ Spi_SetupEB( CFG_P()->EepDataChannel, NULL ,NULL ,1);
+ Spi_SyncTransmit(CFG_P()->EepCmdSequence);
+}
+
+static void Eep_WRDI( void ) {
+ Eep_Global.ebCmd = E2_WRDI;
+ Spi_SetupEB( CFG_P()->EepDataChannel, NULL ,NULL ,1);
+ Spi_SyncTransmit(CFG_P()->EepCmdSequence);
+
+}
+
+static uint8 Eep_ReadStatusReg( void ) {
+ Spi_SetupEB( CFG_P()->EepDataChannel, NULL, &Eep_Global.ebReadStatus, 1);
+ Eep_Global.ebCmd = E2_RDSR;
+ Spi_SyncTransmit(CFG_P()->EepCmd2Sequence);
+ return Eep_Global.ebReadStatus;
+}
+#endif
+
+void Eep_Init( const Eep_ConfigType* ConfigPtr ){
+ VALIDATE( (ConfigPtr != NULL) , EEP_INIT_ID, EEP_E_PARAM_CONFIG );
+ Eep_Global.config = ConfigPtr;
+
+ Spi_SetupEB( CFG_P()->EepCmdChannel, &Eep_Global.ebCmd,NULL,sizeof(Eep_Global.ebCmd)/sizeof(Eep_Global.ebCmd));
+ Spi_SetupEB( CFG_P()->EepAddrChannel, Eep_Global.ebE2Addr,NULL,sizeof(Eep_Global.ebE2Addr)/sizeof(Eep_Global.ebE2Addr[0]));
+ Spi_SetupEB( CFG_P()->EepWrenChannel, NULL,NULL,1);
+
+#if defined( CHECK_SANE )
+
+ // Simple check,
+ // - write WREN,
+ // - check if 1 by reading with RDSR,
+ // - write WRDE
+ // - check if 0 by reading with RDSR,
+ Eep_WREN();
+
+ if( (Eep_ReadStatusReg() & 0x2) == 0 ) {
+ while(1);
+ }
+ Eep_WRDI();
+ if( (Eep_ReadStatusReg() & 0x2) ) {
+ while(1);
+ }
+
+#endif
+
+ Eep_Global.status = MEMIF_IDLE;
+ Eep_Global.jobResultType = MEMIF_JOB_OK;
+
+}
+
+
+void Eep_SetMode( MemIf_ModeType Mode ){
+ VALIDATE( ( Eep_Global.status != MEMIF_UNINIT ), EEP_SETMODE_ID, EEP_E_UNINIT );
+ VALIDATE( ( Eep_Global.status != MEMIF_BUSY ), EEP_SETMODE_ID, EEP_E_BUSY );
+
+ Eep_Global.mode = Mode;
+}
+
+Std_ReturnType Eep_Read ( Eep_AddressType EepromAddress,
+ uint8 *TargetAddressPtr,
+ Eep_LengthType Length )
+{
+ Eep_JobInfoType *job = &Eep_Global.job;
+
+ VALIDATE_W_RV( ( Eep_Global.status != MEMIF_UNINIT ), EEP_READ_ID, EEP_E_UNINIT, E_NOT_OK );
+ VALIDATE_W_RV( ( Eep_Global.status != MEMIF_BUSY ), EEP_READ_ID, EEP_E_BUSY, E_NOT_OK );
+ VALIDATE_W_RV( ( TargetAddressPtr != NULL ) , EEP_READ_ID, EEP_E_PARAM_DATA, E_NOT_OK );
+ VALIDATE_W_RV( ( (EepromAddress) < (Eep_Global.config->EepSize) ) , EEP_READ_ID, EEP_E_PARAM_ADDRESS, E_NOT_OK );
+ VALIDATE_W_RV( ( (Eep_Global.config->EepSize - EepromAddress) >= Length ) , EEP_READ_ID, EEP_E_PARAM_LENGTH, E_NOT_OK );
+
+ Eep_Global.status = MEMIF_BUSY;
+ Eep_Global.jobResultType = MEMIF_JOB_PENDING;
+ Eep_Global.jobType = EEP_READ;
+
+ if( Eep_Global.mode == MEMIF_MODE_FAST ) {
+ job->chunkSize = Eep_Global.config->EepFastReadBlockSize;
+ } else {
+ job->chunkSize = Eep_Global.config->EepNormalReadBlockSize;
+ }
+
+ job->eepAddr = EepromAddress;
+ job->targetAddr = TargetAddressPtr;
+ job->left = Length;
+
+ JOB_SET_STATE(JOB_MAIN,EEP_READ);
+
+ return E_OK;
+}
+
+Std_ReturnType Eep_Erase( Eep_AddressType TargetAddress, Eep_LengthType Length ){
+ VALIDATE_W_RV( ( Eep_Global.status != MEMIF_UNINIT ), EEP_ERASE_ID, EEP_E_UNINIT, E_NOT_OK );
+ VALIDATE_W_RV( ( Eep_Global.status != MEMIF_BUSY ), EEP_ERASE_ID, EEP_E_BUSY, E_NOT_OK );
+ VALIDATE_W_RV( ( (TargetAddress) < (Eep_Global.config->EepSize) ) , EEP_ERASE_ID, EEP_E_PARAM_ADDRESS, E_NOT_OK );
+ VALIDATE_W_RV( ( (Eep_Global.config->EepSize - TargetAddress) >= Length ) , EEP_ERASE_ID, EEP_E_PARAM_LENGTH, E_NOT_OK );
+
+ /* TODO : NOT IMPLEMENTED
+ * ( Since this E2 do not have erase )
+ * */
+ Std_ReturnType rv = E_NOT_OK;
+ Eep_Global.status = MEMIF_BUSY;
+ Eep_Global.status = MEMIF_IDLE;
+ return rv;
+}
+
+Std_ReturnType Eep_Write( Eep_AddressType EepromAddress, const uint8* DataBufferPtr, Eep_LengthType Length ){
+ Eep_JobInfoType *job = &Eep_Global.job;
+
+ VALIDATE_W_RV( ( Eep_Global.status != MEMIF_UNINIT ), EEP_WRITE_ID, EEP_E_UNINIT, E_NOT_OK );
+ VALIDATE_W_RV( ( Eep_Global.status != MEMIF_BUSY ), EEP_WRITE_ID, EEP_E_BUSY, E_NOT_OK );
+ VALIDATE_W_RV( ( DataBufferPtr != NULL ) , EEP_WRITE_ID, EEP_E_PARAM_DATA, E_NOT_OK );
+ VALIDATE_W_RV( ( (EepromAddress) < (Eep_Global.config->EepSize) ) , EEP_WRITE_ID, EEP_E_PARAM_ADDRESS, E_NOT_OK );
+ VALIDATE_W_RV( ( Length <= (Eep_Global.config->EepSize - EepromAddress) ) , EEP_WRITE_ID, EEP_E_PARAM_LENGTH, E_NOT_OK );
+
+ Eep_Global.jobResultType = MEMIF_JOB_PENDING;
+ Eep_Global.status = MEMIF_BUSY;
+ Eep_Global.jobType = EEP_WRITE;
+
+ if( Eep_Global.mode == MEMIF_MODE_FAST ) {
+ job->chunkSize = Eep_Global.config->EepFastWriteBlockSize;
+ } else {
+ job->chunkSize = Eep_Global.config->EepNormalWriteBlockSize;
+ }
+
+ job->eepAddr = EepromAddress;
+ job->targetAddr = (uint8 *)DataBufferPtr;
+ job->left = Length;
+
+ JOB_SET_STATE(JOB_MAIN,EEP_WRITE);
+
+ return E_OK;
+}
+
+
+Std_ReturnType Eep_Compare( Eep_AddressType EepromAddress, uint8 *TargetAddressPtr, Eep_LengthType Length )
+{
+ Eep_JobInfoType *job = &Eep_Global.job;
+
+ VALIDATE_W_RV( ( Eep_Global.status != MEMIF_UNINIT ), EEP_COMPARE_ID, EEP_E_UNINIT, E_NOT_OK );
+ VALIDATE_W_RV( ( Eep_Global.status != MEMIF_BUSY ), EEP_COMPARE_ID, EEP_E_BUSY, E_NOT_OK );
+ VALIDATE_W_RV( ( TargetAddressPtr != NULL ) , EEP_COMPARE_ID, EEP_E_PARAM_DATA, E_NOT_OK );
+ VALIDATE_W_RV( ( (EepromAddress) < (Eep_Global.config->EepSize) ) , EEP_COMPARE_ID, EEP_E_PARAM_ADDRESS, E_NOT_OK );
+ VALIDATE_W_RV( ( (Eep_Global.config->EepSize - EepromAddress) >= Length ) , EEP_COMPARE_ID, EEP_E_PARAM_LENGTH, E_NOT_OK );
+
+ Eep_Global.status = MEMIF_BUSY;
+ Eep_Global.jobResultType = MEMIF_JOB_PENDING;
+ Eep_Global.jobType = EEP_COMPARE;
+
+ /* This is a compare job but the compare jobs really issues read in portions
+ * big enough to fit it's static buffers
+ */
+ if( Eep_Global.mode == MEMIF_MODE_FAST ) {
+ job->chunkSize = Eep_Global.config->EepFastReadBlockSize;
+ } else {
+ job->chunkSize = Eep_Global.config->EepNormalReadBlockSize;
+ }
+
+ job->eepAddr = EepromAddress;
+ job->targetAddr = TargetAddressPtr;
+ job->left = Length;
+
+ JOB_SET_STATE(JOB_MAIN,EEP_COMPARE);
+
+ return E_OK;
+}
+
+
+void Eep_Cancel( void ){
+ EEP_JOB_END_NOTIFICATION();
+
+ if (MEMIF_JOB_PENDING==Eep_Global.jobResultType) {
+ Eep_Global.jobResultType=MEMIF_JOB_CANCELLED;
+ }
+
+ Eep_Global.status = MEMIF_IDLE;
+}
+
+MemIf_StatusType Eep_GetStatus( void ){
+ return Eep_Global.status;
+}
+
+MemIf_JobResultType Eep_GetJobResult( void ){
+ return Eep_Global.jobResultType;
+}
+
+
+/**
+ * Function that process read/write/erase requests to the SPI
+ *
+ * @param job The present job
+ */
+
+static Spi_SeqResultType Eep_ProcessJob( Eep_JobInfoType *job ) {
+ Spi_SeqResultType rv;
+ _Bool done = 0;
+
+ /* Check if previous sequence is OK */
+ rv = Spi_GetSequenceResult(job->currSeq);
+ if( rv != SPI_SEQ_OK ) {
+ return rv;
+ }
+
+ rv = SPI_SEQ_PENDING;
+
+ do {
+ switch(job->state ) {
+ case JOB_READ_STATUS:
+ DEBUG(DEBUG_LOW,"%s: READ_STATUS\n",MODULE_NAME);
+ /* Check status from erase cmd, read status from flash */
+ Spi_SetupEB( CFG_P()->EepDataChannel, NULL, &Eep_Global.ebReadStatus, 1);
+ Eep_Global.ebCmd = E2_RDSR;
+ if( SPI_TRANSMIT_FUNC(CFG_P()->EepCmd2Sequence,job ) != E_OK ) {
+ assert(0);
+ }
+ SET_STATE(1,JOB_READ_STATUS_RESULT);
+ break;
+
+ case JOB_READ_STATUS_RESULT:
+ DEBUG(DEBUG_LOW,"%s: READ_STATUS_RESULT\n",MODULE_NAME);
+ if( Eep_Global.ebReadStatus&1 ) {
+ SET_STATE(0,JOB_READ_STATUS);
+ } else {
+ SET_STATE(0,JOB_MAIN);
+ }
+ break;
+
+ case JOB_MAIN:
+ if( job->left != 0 ) {
+ if( job->left <= job->chunkSize ) {
+ job->chunkSize = job->left;
+ }
+
+ Spi_ConvertToSpiAddr(Eep_Global.ebE2Addr,job->eepAddr);
+
+ switch(job->mainState) {
+
+ case EEP_ERASE:
+ /* NOT USED */
+ break;
+ case EEP_READ:
+ case EEP_COMPARE:
+ DEBUG(DEBUG_LOW,"%s: READ s:%04x d:%04x l:%04x\n",MODULE_NAME,job->eepAddr, job->targetAddr, job->left);
+ Eep_Global.ebCmd = E2_READ;
+ Spi_SetupEB( CFG_P()->EepDataChannel, NULL ,job->targetAddr,job->chunkSize);
+ SPI_TRANSMIT_FUNC(CFG_P()->EepReadSequence,job );
+ break;
+
+ case EEP_WRITE:
+ DEBUG(DEBUG_LOW,"%s: WRITE d:%04x s:%04x first data:%02x\n",MODULE_NAME,job->eepAddr,job->targetAddr,*job->targetAddr);
+ Eep_Global.ebCmd = E2_WRITE;
+ Spi_ConvertToSpiAddr(Eep_Global.ebE2Addr,job->eepAddr);
+ Spi_SetupEB( CFG_P()->EepDataChannel, job->targetAddr, NULL, job->chunkSize);
+ SPI_TRANSMIT_FUNC(CFG_P()->EepWriteSequence,job );
+ break;
+
+ default:
+ assert(0);
+ break;
+ }
+
+ job->eepAddr += job->chunkSize;
+ job->targetAddr += job->chunkSize;
+ job->left -= job->chunkSize;
+ SET_STATE(1,JOB_READ_STATUS);
+
+ } else {
+ /* We are done :) */
+ SET_STATE(1,JOB_MAIN);
+ job->mainState = EEP_NONE;
+ rv = SPI_SEQ_OK;
+ }
+ break;
+
+ default:
+ assert(0);
+ break;
+
+ }
+ } while(!done);
+ return rv;
+}
+
+#define CMP_BUFF_SIZE SPI_EB_MAX_LENGTH
+
+void Eep_MainFunction( void )
+{
+ Spi_SeqResultType jobResult;
+
+ if( Eep_Global.jobResultType == MEMIF_JOB_PENDING ) {
+ switch (Eep_Global.jobType) {
+ case EEP_COMPARE: {
+ static Eep_JobInfoType readJob;
+ static uint8 Eep_CompareBuffer[SPI_EB_MAX_LENGTH];
+ Eep_JobInfoType *gJob = &Eep_Global.job;
+ static _Bool firstTime = 1;
+ static uint32 readSize;
+
+ /* Compare jobs must use a local buffer to hold one portion
+ * of the job. Since Eep_ProcessJob() also manipulates the
+ * job structure we need to create a new local job each time.
+ * The global job updates is updated for each process job.
+ */
+
+ if (firstTime == 1) {
+ readJob = *gJob;
+
+ if ( gJob->left <= CMP_BUFF_SIZE ) {
+ readSize = gJob->left;
+ } else {
+ readSize = CMP_BUFF_SIZE;
+ }
+ readJob.left = readSize;
+ readJob.targetAddr = Eep_CompareBuffer;
+ firstTime = 0;
+ }
+
+ jobResult = Eep_ProcessJob(&readJob);
+
+ if( jobResult == SPI_SEQ_PENDING ) {
+ /* Do nothing */
+ } else if( jobResult == SPI_SEQ_OK ) {
+
+ if( memcmp(Eep_CompareBuffer,gJob->targetAddr, readSize) != 0 ) {
+ DET_REPORTERROR(MODULE_ID_EEP,0, 0x9, MEMIF_JOB_FAILED );
+ EEP_JOB_ERROR_NOTIFICATION();
+ return;
+ }
+ // Update the global comare job
+ gJob->targetAddr += readSize;
+ gJob->eepAddr += readSize;
+ gJob->left -= readSize;
+
+ // Check if we are done
+ if( gJob->left == 0 ) {
+ Eep_Global.jobResultType = MEMIF_JOB_OK;
+ Eep_Global.jobType = EEP_NONE;
+ Eep_Global.status = MEMIF_IDLE;
+ EEP_JOB_END_NOTIFICATION();
+ firstTime = 1;
+ return;
+ }
+ // Calculate new readSize
+ if ( gJob->left <= CMP_BUFF_SIZE ) {
+ readSize = gJob->left;
+ } else {
+ readSize = CMP_BUFF_SIZE;
+ }
+
+ // Update the readjob for next session
+ readJob = *gJob;
+ readJob.left = readSize;
+ readJob.targetAddr = Eep_CompareBuffer;
+ } else {
+ // all other cases are bad
+ firstTime = 1;
+ Eep_Global.jobResultType = MEMIF_JOB_FAILED;
+ Eep_Global.jobType = EEP_NONE;
+ Eep_Global.status = MEMIF_IDLE;
+
+ DET_REPORTERROR(MODULE_ID_EEP,0, 0x9, MEMIF_JOB_FAILED );
+ EEP_JOB_ERROR_NOTIFICATION();
+ }
+ }
+ break;
+
+ case EEP_ERASE:
+ case EEP_READ:
+ case EEP_WRITE:
+
+ jobResult = Eep_ProcessJob(&Eep_Global.job);
+
+ if( jobResult == SPI_SEQ_OK ) {
+
+ Eep_Global.jobResultType = MEMIF_JOB_OK;
+ Eep_Global.jobType = EEP_NONE;
+ Eep_Global.status = MEMIF_IDLE;
+ EEP_JOB_END_NOTIFICATION();
+ } else if( jobResult == SPI_SEQ_PENDING ) {
+ /* Busy, Do nothing */
+ } else {
+ // Error
+ Eep_Global.jobResultType = MEMIF_JOB_FAILED;
+ Eep_Global.jobType = EEP_NONE;
+ Eep_Global.status = MEMIF_IDLE;
+
+ switch(Eep_Global.jobType) {
+ case EEP_ERASE:
+ DET_REPORTERROR(MODULE_ID_EEP,0, 0x9, MEMIF_JOB_FAILED );
+ break;
+ case EEP_READ:
+ DET_REPORTERROR(MODULE_ID_EEP,0, 0x9, MEMIF_JOB_FAILED );
+ break;
+ case EEP_WRITE:
+ DET_REPORTERROR(MODULE_ID_EEP,0, 0x9, MEMIF_JOB_FAILED );
+ break;
+ default:
+ assert(0);
+ }
+
+ EEP_JOB_ERROR_NOTIFICATION();
+ }
+ break;
+ case EEP_NONE:
+ assert(0);
+ break;
+ }
+ }
+}
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef ESCI_H_\r
+#define ESCI_H_\r
+\r
+#endif /* ESCI_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/**
+ * @file Fls.c
+ * @breif Autosar Flash driver for Freescale MPC55xx.
+ */
+
+
+/*
+ * IMPLEMENTATION NOTES
+ * - It seems that the Autosar specification is not consistent. For
+ * FLS_AC_LOAD_ON_JOB_START == STD_ON it seems that the driver suddenly
+ * becomes blocking.
+ *
+ */
+
+/*
+ * Use cases:
+ * 1. Bootloader, self replace
+ * 2. Bootloader, application loading
+ *
+ * In case 2 it's very straight forward and you can just use all the functions
+ * as intended. In case 1. there are some problems understanding how Autosar
+ * want to implement it. What is given from spec is.
+ * - If FLS_AC_LOAD_ON_JOB_START == STD_ON we copy the flash access routines
+ * to RAM( to FlsAcErase and FlsAcWrite ).
+ *
+ * Strange things:
+ * - What happens to all the other functions that is needed to get the status
+ * for the flash driver. Did the driver just get blocking ??
+ *
+ */
+
+#include "Fls.h"
+/* Freescale driver */
+#include "ssd_types.h"
+#include "ssd_h7f.h"
+#include <stdlib.h>
+#include <assert.h>
+#include <string.h>
+#include "Det.h"
+#include "h7f_types.h"
+#include "Cpu.h"
+#include "mpc55xx.h"
+#include "Fls_H7F.h"
+
+
+/* Flash layout for MPC5516 */
+/*
+ * Low: 8x16K + 2x64k
+ * Mid: 2x128K
+ * High: 8x128K
+ */
+
+#define H7F_REG_BASE 0xFFFF8000
+#define MAIN_ARRAY_BASE 0x00000000
+#define SHADOW_ROW_BASE 0x00FF8000
+#define SHADOW_ROW_SIZE 0x00008000
+#define FLASH_PAGE_SIZE H7FB_PAGE_SIZE
+
+#if 0
+#define VFLAGS_ADDR_SECT (1<<0)
+#define VFLAGS_ADDR_PAGE (1<<1)
+#define VFLAGS_LEN_SECT (1<<2)
+#define VFLAGS_LEN_PAGE (1<<3)
+
+static inline int Fls_Validate( uint32 addr,uint32 length, uint32 api,uint32 rv ) {
+ int i;
+ int addrOk=0;
+ uint32 flags_ok;
+ const Fls_SectorType* sector;
+ Fls_ConfigType *cfg = Fls_Global.config;
+
+ // Pre checks.
+ if( flags & VFLAGS_LEN_SECT ) {
+ if( (addr + length) > FLS_TOTAL_SIZE ) {
+ return (-1);
+ }
+ }
+
+ for(i=0;i<cfg->FlsSectorListSize;i++) {
+ sector = &cfg->FlsSectorList[sectorIndex];
+ if( addr > (sector->FlsSectorStartaddress + sector->FlsNumberOfSectors * sector->FlsNumberOfSectors) ) {
+ continue;
+ }
+ if( flags & VFLAGS_ADDR_SECT ) {
+ if( (addr % sector->FlsSectorSize) == 0) {
+ flags &= ~VFLAGS_ADDR_SECT;
+ }
+ }
+ if( flags & VFLAGS_ADDR_PAGE ) {
+ if( (addr % sector->FlsPageSize) == 0) {
+ flags &= ~VFLAGS_ADDR_PAGE;
+ }
+ }
+ if( flags & VFLAGS_LEN_SECT ) {
+ // Check
+ if( (0!= length) && (length < sectorPtr->FlsSectorSize) ) {
+ flags &= ~VFLAGS_ADDR_SECT;
+ }
+ }
+ if( flags & VFLAGS_LEN_PAGE ) {
+ if( (0!= length) && (length < sectorPtr->FlsPageSize)) {
+ flags &= ~VFLAGS_ADDR_PAGE;
+ }
+ }
+ }
+}
+#endif
+
+#if ( FLS_DEV_ERROR_DETECT == STD_ON )
+#define FLS_VALIDATE_PARAM_ADDRESS_SECTOR_W_RV(_addr, _api, _rv)\
+ int sectorIndex;\
+ int addrOk=0;\
+ const Fls_SectorType* sector;\
+ for (sectorIndex=0; sectorIndex<Fls_Global.config->FlsSectorListSize;sectorIndex++) {\
+ sector = &Fls_Global.config->FlsSectorList[sectorIndex];\
+ if((((uint32)_addr-sector->FlsSectorStartaddress) / sector->FlsSectorSize)<sector->FlsNumberOfSectors){\
+ /* Within the right adress space */\
+ if (!(((uint32)_addr-sector->FlsSectorStartaddress) % sector->FlsSectorSize)){\
+ /* Address is correctly aligned */\
+ addrOk=1;\
+ break;\
+ }\
+ }\
+ }\
+ if (1!=addrOk){\
+ Det_ReportError(MODULE_ID_FLS,0,_api,FLS_E_PARAM_ADDRESS ); \
+ return _rv; \
+ }
+
+#define FLS_VALIDATE_PARAM_ADDRESS_PAGE_W_RV(_addr, _api, _rv)\
+ int sectorIndex;\
+ int addrOk=0;\
+ const Fls_SectorType* sector;\
+ for (sectorIndex=0; sectorIndex<Fls_Global.config->FlsSectorListSize;sectorIndex++) {\
+ sector = &Fls_Global.config->FlsSectorList[sectorIndex];\
+ if((((uint32)_addr-sector->FlsSectorStartaddress) / sector->FlsSectorSize)<sector->FlsNumberOfSectors){\
+ /* Within the right adress space */\
+ if (!(((uint32)_addr-sector->FlsSectorStartaddress) % sector->FlsPageSize)){\
+ /* Address is correctly aligned */\
+ addrOk=1;\
+ break;\
+ }\
+ }\
+ }\
+ if (1!=addrOk){\
+ Det_ReportError(MODULE_ID_FLS,0,_api,FLS_E_PARAM_ADDRESS ); \
+ return _rv; \
+ }
+
+#define FLS_VALIDATE_PARAM_LENGTH_PAGE_W_RV(_addr, _length, _api, _rv)\
+ int i;\
+ int lengthOk=0;\
+ const Fls_SectorType* sectorPtr= &Fls_Global.config->FlsSectorList[0];\
+ for (i=0; i<Fls_Global.config->FlsSectorListSize;i++) {\
+ if ((sectorPtr->FlsSectorStartaddress + (sectorPtr->FlsNumberOfSectors * sectorPtr->FlsSectorSize))>=(uint32_t)(_addr+(_length))){\
+ if ((0!=_length)&&!(_length % sectorPtr->FlsPageSize)){\
+ lengthOk=1;\
+ break;\
+ }\
+ }\
+ sectorPtr++;\
+ }\
+ if (!lengthOk){\
+ Det_ReportError(MODULE_ID_FLS,0,_api,FLS_E_PARAM_LENGTH ); \
+ return _rv; \
+ }
+
+#define FLS_VALIDATE_PARAM_LENGTH_SECTOR_W_RV(_addr, _length, _api, _rv)\
+ int i;\
+ int lengthOk=0;\
+ const Fls_SectorType* sectorPtr= &Fls_Global.config->FlsSectorList[0];\
+ for (i=0; i<Fls_Global.config->FlsSectorListSize;i++) {\
+ if ((sectorPtr->FlsSectorStartaddress + (sectorPtr->FlsNumberOfSectors * sectorPtr->FlsSectorSize))>=(uint32_t)(_addr+(_length))){\
+ if ((0!=_length)&& !(_length % sectorPtr->FlsSectorSize)){\
+ lengthOk=1;\
+ break;\
+ }\
+ }\
+ sectorPtr++;\
+ }\
+ if (!lengthOk){\
+ Det_ReportError(MODULE_ID_FLS,0,_api,FLS_E_PARAM_LENGTH ); \
+ return _rv; \
+ }
+
+#define FLS_VALIDATE_STATUS_UNINIT_W_RV(_status, _api, _rv)\
+ if (MEMIF_UNINIT == _status){\
+ Det_ReportError(MODULE_ID_FLS,0,_api,FLS_E_UNINIT); \
+ return _rv; \
+ }
+
+#define FLS_VALIDATE_STATUS_BUSY(_status, _api)\
+ if (MEMIF_BUSY == _status){\
+ Det_ReportError(MODULE_ID_FLS,0,_api,FLS_E_BUSY); \
+ return; \
+ }
+
+#define FLS_VALIDATE_STATUS_BUSY_W_RV(_status, _api, _rv)\
+ if (MEMIF_BUSY == _status){\
+ Det_ReportError(MODULE_ID_FLS,0,_api,FLS_E_BUSY); \
+ return _rv; \
+ }
+
+#define FLS_VALIDATE_PARAM_DATA_W_RV(_ptr,_api, _rv) \
+ if( (_ptr)==((void *)0)) { \
+ Det_ReportError(MODULE_ID_FLS,0,_api,FLS_E_PARAM_DATA); \
+ return _rv; \
+ }
+#else
+ #define FLS_VALIDATE_PARAM_ADDRESS_SECTOR_W_RV(_addr, _api, _rv)
+ #define FLS_VALIDATE_PARAM_ADDRESS_PAGE_W_RV(_addr, _api, _rv)
+ #define FLS_VALIDATE_PARAM_LENGTH_SECTOR_W_RV(_addr, _length, _api, _rv)
+ #define FLS_VALIDATE_PARAM_LENGTH_PAGE_W_RV(_addr, _length, _api, _rv)
+ #define FLS_VALIDATE_STATUS_UNINIT_W_RV(_status, _api, _rv)
+ #define FLS_VALIDATE_STATUS_BUSY(_status, _api)
+ #define FLS_VALIDATE_STATUS_BUSY_W_RV(_status, _api, _rv)
+ #define FLS_VALIDATE_PARAM_DATA_W_RV(_ptr,_api,_rv)
+#endif
+
+#if ( FLS_DEV_ERROR_DETECT == STD_ON )
+#define DET_REPORTERROR(_x,_y,_z,_q) Det_ReportError(MODULE_ID_FLS, _y, _z, _q)
+#else
+#define DET_REPORTERROR(_x,_y,_z,_q)
+#endif
+
+#if ( FLS_GET_JOB_RESULT_API == STD_ON)
+#define FEE_JOB_END_NOTIFICATION() \
+ if( Fls_Global.config->FlsJobEndNotification != NULL ) { \
+ Fls_Global.config->FlsJobEndNotification(); \
+ }
+#define FEE_JOB_ERROR_NOTIFICATION() \
+ if( Fls_Global.config->FlsJobErrorNotification != NULL ) { \
+ Fls_Global.config->FlsJobErrorNotification(); \
+ }
+#else
+#define FEE_JOB_END_NOTIFICATION()
+#define FEE_JOB_ERROR_NOTIFICATION()
+#endif
+
+
+
+/**
+ * Get PC.
+ * Since you can't read the PC on PPC, do the next best thing.
+ * Ensure that the function is not inlined
+ */
+static uint32 Fls_GetPc( void ) __attribute__ ((noinline));
+
+static uint32 Fls_GetPc( void )
+{
+ return get_spr(SPR_LR);
+}
+
+
+typedef struct {
+ uint32 addr;
+ uint32 size;
+} Fls_InternalSectorType;
+
+
+SSD_CONFIG ssdConfig = {
+ H7F_REG_BASE, /* H7F control register base */
+ MAIN_ARRAY_BASE, /* base of main array */
+ 0, /* size of main array */
+ SHADOW_ROW_BASE, /* base of shadow row */
+ SHADOW_ROW_SIZE, /* size of shadow row */
+ 0, /* block number in low address space */
+ 0, /* block number in middle address space */
+ 0, /* block number in high address space */
+ 8, /* page size */
+ FALSE, /* debug mode selection */
+};
+
+static Std_VersionInfoType _Fls_VersionInfo = {
+ .vendorID = (uint16)1,
+ .moduleID = (uint16) MODULE_ID_FLS,
+ .instanceID = (uint8)1,
+ /* Vendor numbers */
+ .sw_major_version = (uint8)FLS_SW_MAJOR_VERSION,
+ .sw_minor_version = (uint8)FLS_SW_MINOR_VERSION,
+ .sw_patch_version = (uint8)FLS_SW_PATCH_VERSION,
+ .ar_major_version = (uint8)FLS_AR_MAJOR_VERSION,
+ .ar_minor_version = (uint8)FLS_AR_MINOR_VERSION,
+ .ar_patch_version = (uint8)FLS_AR_PATCH_VERSION,
+};
+
+//
+typedef enum {
+ FLS_JOB_NONE,
+ FLS_JOB_COMPARE,
+ FLS_JOB_ERASE,
+ FLS_JOB_READ,
+ FLS_JOB_WRITE,
+} Fls_EcoreJobType;
+
+#if 0
+typedef struct {
+ MemIf_StatusType status;
+ MemIf_JobResultType jobResultType;
+ Fls_EcoreJobType jobType;
+ MemIf_AddressType sourceAddr;
+ uint8 *targetAddr;
+ MemIf_LengthType length;
+
+ Fls_ProgInfoType flashWriteInfo;
+
+} FlsUnit_t;
+#endif
+
+
+#if 0
+static FlsUnit_t privData = {
+ .status = MEMIF_UNINIT,
+ .jobResultType = MEMIF_JOB_OK,
+ .jobType = FLS_JOB_NONE,
+
+};
+#endif
+
+// Default Config
+#if 0
+const Fls_ConfigType * configDataPtr = &FlsConfigSet[0];
+#endif
+
+// TODO: Comment and cleanup
+typedef struct {
+ const Fls_ConfigType * config;
+ Fls_EraseBlockType lockBits;
+
+ MemIf_StatusType status;
+ MemIf_JobResultType jobResultType;
+ Fls_EcoreJobType jobType;
+ MemIf_AddressType sourceAddr;
+ uint8 *targetAddr;
+ MemIf_LengthType length;
+
+ Fls_ProgInfoType flashWriteInfo;
+} Fls_GlobalType;
+
+Fls_GlobalType Fls_Global = {
+ .status = MEMIF_UNINIT,
+ .jobResultType = MEMIF_JOB_OK,
+ .jobType = FLS_JOB_NONE,
+};
+
+
+#if 0
+static inline uint32 rlwimi(uint32 val, uint16 sh, uint16 mb,uint16 me)
+{
+ uint32 result;
+ asm volatile("rlwimi %0,%1,8,16,23"
+ : "=r" (result)
+ : "r" (val),"g" (sh), "g" (mb), "g" (me) );
+ return result;
+}
+
+#define CREATE_MASK(_start,_stop) rlwimi(0xffffffff,0x0,0x0,0x10)
+#endif
+
+/**
+ * Converts an address to a freescale erase block.
+ * Assumes addr is located from FLS_BASE_ADDRESS
+ *
+ * @param addr address to convert
+ * @param rem pointer to reminder that gets filled in by the function
+ * @return A block number
+ */
+
+// TODO: This have hardcoded limits. Get from config instead
+static uint32 address_to_block( uint32 addr, uint32 *rem ) {
+ uint32 block;
+
+ if( addr < 0x20000) {
+ // Low range, 8x16K
+ block = addr / 0x4000;
+ *rem = addr % 0x4000;
+ } else if ( addr < 0x40000) {
+ // Low range, 2x64k range
+ block = 8 + ( addr - 0x20000 ) / 0x10000;
+ *rem = addr % 0x10000;
+ } else if( addr < 0x80000 ) {
+ // mid range
+ block = 10 + ( addr - 0x40000 ) / 0x20000;
+ *rem = addr % 0x20000;
+ } else if( addr < 0x180000 ) {
+ // high range
+ block = 12 + ( addr - 0x80000 ) / 0x20000;
+ *rem = addr % 0x20000;
+ } else {
+ block = (-1);
+ *rem = (-1);
+ }
+ return block;
+}
+
+
+/**
+ * Converts an address range( addr to addr + size) to freescale bit erase
+ * blocks. The function adds the erase block information to eraseBlocks ptr.
+ *
+ * @param eraseBlocks Ptr to an erase structure
+ * @param addr The start-address to convert
+ * @param size The size of the block
+ * @return The test results
+ */
+static void address_to_erase_blocks( Fls_EraseBlockType *eraseBlocks, uint32 addr, uint32 size ) {
+// EraseBlock_t eraseBlocks;
+ uint32 startBlock;
+ uint32 endBlock;
+ uint32 mask1;
+ uint32 mask2;
+ uint32 mask;
+ uint32 rem;
+
+ /* Create a mask with continuous set of 1's */
+ startBlock = address_to_block( addr,&rem );
+ endBlock = address_to_block( addr + size - 1,&rem );
+
+ // Check so our implementation holds..
+ assert( endBlock<=32 );
+
+#define BLOCK_MASK 0x0003ffffUL
+
+ // create the mask
+ mask1 = ((-1UL)<<(31-endBlock))>>(31-endBlock);
+ mask2 = ((-1UL)>>startBlock)<<startBlock;
+ mask = mask1 & mask2;
+
+
+ // shift things in to make freescale driver happy
+ eraseBlocks->lowEnabledBlocks = mask&0x3f; // ????
+ eraseBlocks->midEnabledBlocks = (mask>>10)&3; // ????
+ eraseBlocks->highEnabledBlocks = mask>>12;
+
+
+ return ;
+}
+
+
+void Fls_Init( const Fls_ConfigType *ConfigPtr )
+{
+ FLS_VALIDATE_STATUS_BUSY(Fls_Global.status, FLS_INIT_ID);
+ Fls_Global.status = MEMIF_UNINIT;
+ Fls_Global.jobResultType = MEMIF_JOB_PENDING;
+ uint32 returnCode;
+ Fls_EraseBlockType eraseBlocks;
+ // TODO: FLS_E_PARAM_CONFIG
+ Fls_Global.config = ConfigPtr;
+
+#if (FLS_AC_LOAD_ON_JOB_START == STD_ON )
+ /* Copy fls routines to RAM */
+ memcpy(__FLS_ERASE_RAM__,__FLS_ERASE_ROM__, (size_t)&__FLS_SIZE__);
+
+#endif
+
+
+ returnCode = FlashInit( &ssdConfig );
+
+ // Lock shadow row..
+ eraseBlocks.lowEnabledBlocks = 0;
+ eraseBlocks.midEnabledBlocks = 0;
+ eraseBlocks.highEnabledBlocks = 0;
+ eraseBlocks.shadowBlocks = 1;
+
+ Fls_H7F_SetLock(&eraseBlocks,1);
+
+ Fls_Global.status = MEMIF_IDLE;
+ Fls_Global.jobResultType = MEMIF_JOB_OK;
+ return;
+}
+
+/* TargetAddress always from 0 to FLS_TOTAL_SIZE */
+Std_ReturnType Fls_Erase( MemIf_AddressType TargetAddress,
+ MemIf_LengthType Length )
+{
+ uint32 block;
+ uint32 sBlock;
+ uint32 rem;
+ Fls_EraseBlockType eraseBlock;
+ Fls_EraseInfoType eraseInfo;
+ uint32 pc;
+
+ FLS_VALIDATE_STATUS_UNINIT_W_RV(Fls_Global.status, FLS_ERASE_ID, E_NOT_OK);
+ FLS_VALIDATE_STATUS_BUSY_W_RV(Fls_Global.status, FLS_ERASE_ID, E_NOT_OK);
+ FLS_VALIDATE_PARAM_ADDRESS_SECTOR_W_RV(TargetAddress, FLS_ERASE_ID, E_NOT_OK);
+ FLS_VALIDATE_PARAM_LENGTH_SECTOR_W_RV(TargetAddress, Length, FLS_ERASE_ID, E_NOT_OK);
+
+ // Always check if status is not busy
+ if (Fls_Global.status == MEMIF_BUSY )
+ return E_NOT_OK;
+
+ // TargetAddress
+ sBlock = address_to_block(TargetAddress,&rem);
+
+ if( (sBlock == (-1)) || (rem!=0) ) {
+ DET_REPORTERROR(MODULE_ID_FLS,0,0x0,FLS_E_PARAM_ADDRESS );
+ return E_NOT_OK;
+ }
+
+ block = address_to_block(TargetAddress+Length,&rem);
+
+ // Check if we trying to erase a partition that we are executing in
+ pc = Fls_GetPc();
+ if( (pc >= FLS_BASE_ADDRESS) && ( pc <= (FLS_BASE_ADDRESS + FLS_TOTAL_SIZE) ) ) {
+ // In flash erase
+ uint32 pcBlock = address_to_block(pc,&rem);
+ uint8 *partMap = Fls_Global.config->FlsBlockToPartitionMap;
+
+ if( (partMap[pcBlock] >= partMap[sBlock]) && (partMap[pcBlock] <= partMap[block]) ) {
+// if( address_to_block(pc,&rem) == Fls_Global.config->FlsBlockToPartitionMap[block] ) {
+ // Can't erase and in the same partition we are executing
+ assert(0);
+ }
+ }
+
+ Fls_Global.status = MEMIF_BUSY;
+ Fls_Global.jobResultType = MEMIF_JOB_PENDING;
+ Fls_Global.jobType = FLS_JOB_ERASE;
+
+ address_to_erase_blocks(&eraseBlock,TargetAddress,Length);
+
+ eraseBlock.shadowBlocks = 0;
+ // Unlock
+ Fls_H7F_SetLock(&eraseBlock,0);
+
+ eraseInfo.state = 0; // Always set this
+
+
+
+ Fls_H7F_FlashErase ( &ssdConfig ,
+ 0, // shadowFlag...
+ eraseBlock.lowEnabledBlocks,
+ eraseBlock.midEnabledBlocks,
+ eraseBlock.highEnabledBlocks,
+ &eraseInfo
+ );
+ return E_OK;
+}
+
+
+Std_ReturnType Fls_Write ( MemIf_AddressType TargetAddress,
+ const uint8 *SourceAddressPtr,
+ MemIf_LengthType Length )
+{
+ Fls_EraseBlockType eraseBlock;
+
+ FLS_VALIDATE_STATUS_UNINIT_W_RV(Fls_Global.status, FLS_WRITE_ID, E_NOT_OK);
+ FLS_VALIDATE_STATUS_BUSY_W_RV(Fls_Global.status, FLS_WRITE_ID, E_NOT_OK);
+ FLS_VALIDATE_PARAM_ADDRESS_PAGE_W_RV(TargetAddress, FLS_WRITE_ID, E_NOT_OK);
+ FLS_VALIDATE_PARAM_LENGTH_PAGE_W_RV(TargetAddress, Length, FLS_WRITE_ID, E_NOT_OK);
+ FLS_VALIDATE_PARAM_DATA_W_RV(SourceAddressPtr, FLS_WRITE_ID, E_NOT_OK)
+
+ // Always check if status is not busy
+ if (Fls_Global.status == MEMIF_BUSY )
+ return E_NOT_OK;
+
+ // Destination is FLS_BASE_ADDRESS + TargetAddress
+ Fls_Global.jobResultType = MEMIF_JOB_PENDING;
+ Fls_Global.status = MEMIF_BUSY;
+ Fls_Global.jobType = FLS_JOB_WRITE;
+
+ // Fill in the required fields for programming...
+ Fls_Global.flashWriteInfo.source = (uint32)SourceAddressPtr;
+ Fls_Global.flashWriteInfo.dest = TargetAddress;
+ Fls_Global.flashWriteInfo.size = Length;
+
+ // unlock flash....
+ address_to_erase_blocks(&eraseBlock,TargetAddress,Length);
+ eraseBlock.shadowBlocks = 0;
+ Fls_H7F_SetLock(&eraseBlock,0);
+
+ return E_OK;
+}
+
+#if ( FLS_CANCEL_API == STD_ON )
+void Fls_Cancel( void )
+{
+ /* API NOT SUPPORTED */
+}
+#endif
+
+
+#if ( FLS_GET_STATUS_API == STD_ON )
+MemIf_StatusType Fls_GetStatus( void )
+{
+ return Fls_Global.status;
+}
+#endif
+
+
+#if ( FLS_GET_JOB_RESULT_API == STD_ON )
+MemIf_JobResultType Fls_GetJobResult( void )
+{
+ return Fls_Global.jobResultType;
+}
+#endif
+
+void Fls_MainFunction( void )
+{
+ uint32 flashStatus;
+ int result;
+ if( Fls_Global.jobResultType == MEMIF_JOB_PENDING ) {
+ switch(Fls_Global.jobType) {
+ case FLS_JOB_COMPARE:
+ // NOT implemented. Hardware error = FLS_E_COMPARE_FAILED
+ // ( we are reading directly from flash so it makes no sense )
+
+ result = memcmp(Fls_Global.targetAddr,(void *)Fls_Global.sourceAddr,Fls_Global.length);
+ if( result == 0 ) {
+ Fls_Global.jobResultType = MEMIF_JOB_OK;
+ } else {
+ Fls_Global.jobResultType = MEMIF_JOB_FAILED;
+ }
+ Fls_Global.status = MEMIF_IDLE;
+ Fls_Global.jobType = FLS_JOB_NONE;
+
+ break;
+ case FLS_JOB_ERASE:
+ {
+// uint32 failAddress;
+// uint32 failData;
+
+ flashStatus = Fls_H7F_EraseStatus(&ssdConfig);
+ if( flashStatus == H7F_OK ) {
+ Fls_EraseBlockType blocks;
+ // Lock all.
+ blocks.highEnabledBlocks = (-1UL);
+ blocks.midEnabledBlocks = (-1UL);
+ blocks.highEnabledBlocks = (-1UL);
+ blocks.shadowBlocks = (-1UL);
+
+ Fls_H7F_SetLock(&blocks,1);
+
+ Fls_Global.jobResultType = MEMIF_JOB_OK;
+ Fls_Global.jobType = FLS_JOB_NONE;
+ Fls_Global.status = MEMIF_IDLE;
+ FEE_JOB_END_NOTIFICATION();
+ } else if( flashStatus == H7F_BUSY ) {
+ /* Busy, Do nothing */
+ } else {
+ // Error
+ Fls_Global.jobResultType = MEMIF_JOB_FAILED;
+ Fls_Global.jobType = FLS_JOB_NONE;
+ Fls_Global.status = MEMIF_IDLE;
+ DET_REPORTERROR(MODULE_ID_FLS,0, 0x6, FLS_E_WRITE_FAILED );
+ FEE_JOB_ERROR_NOTIFICATION();
+ }
+ break;
+ }
+ case FLS_JOB_READ:
+
+ // NOT implemented. Hardware error = FLS_E_READ_FAILED
+ // ( we are reading directly from flash so it makes no sense )
+ memcpy(Fls_Global.targetAddr,(void *)Fls_Global.sourceAddr,Fls_Global.length);
+ Fls_Global.jobResultType = MEMIF_JOB_OK;
+ Fls_Global.status = MEMIF_IDLE;
+ Fls_Global.jobType = FLS_JOB_NONE;
+ break;
+ case FLS_JOB_WRITE:
+ {
+ // NOT implemented. Hardware error = FLS_E_READ_FAILED
+
+ flashStatus = Fls_H7F_Program( &ssdConfig,&Fls_Global.flashWriteInfo);
+
+ if( flashStatus == H7F_OK ) {
+ Fls_EraseBlockType blocks;
+ blocks.highEnabledBlocks = (-1UL);
+ blocks.midEnabledBlocks = (-1UL);
+ blocks.highEnabledBlocks = (-1UL);
+ blocks.shadowBlocks = (-1UL);
+
+ // Lock all
+ Fls_H7F_SetLock(&blocks,1);
+
+ Fls_Global.jobResultType = MEMIF_JOB_OK;
+ Fls_Global.jobType = FLS_JOB_NONE;
+ Fls_Global.status = MEMIF_IDLE;
+ FEE_JOB_END_NOTIFICATION();
+ } else if( flashStatus == H7F_BUSY ) {
+ /* Busy, Do nothing */
+ } else {
+ // Error
+ Fls_Global.jobResultType = MEMIF_JOB_FAILED;
+ Fls_Global.jobType = FLS_JOB_NONE;
+ Fls_Global.status = MEMIF_IDLE;
+ DET_REPORTERROR(MODULE_ID_FLS,0, 0x6, FLS_E_WRITE_FAILED );
+ FEE_JOB_ERROR_NOTIFICATION();
+ }
+
+ break;
+ }
+ case FLS_JOB_NONE:
+ assert(0);
+ break;
+ }
+ }
+}
+
+Std_ReturnType Fls_Read ( MemIf_AddressType SourceAddress,
+ uint8 *TargetAddressPtr,
+ MemIf_LengthType Length )
+{
+ FLS_VALIDATE_STATUS_UNINIT_W_RV(Fls_Global.status, FLS_READ_ID, E_NOT_OK);
+ FLS_VALIDATE_STATUS_BUSY_W_RV(Fls_Global.status, FLS_READ_ID, E_NOT_OK);
+ FLS_VALIDATE_PARAM_ADDRESS_PAGE_W_RV(SourceAddress, FLS_READ_ID, E_NOT_OK);
+ FLS_VALIDATE_PARAM_LENGTH_PAGE_W_RV(SourceAddress, Length, FLS_READ_ID, E_NOT_OK);
+ FLS_VALIDATE_PARAM_DATA_W_RV((void*)SourceAddress, FLS_READ_ID, E_NOT_OK)
+
+ // Always check if status is not busy
+ if (Fls_Global.status == MEMIF_BUSY )
+ return E_NOT_OK;
+
+ Fls_Global.status = MEMIF_BUSY;
+ Fls_Global.jobResultType = MEMIF_JOB_PENDING;
+ Fls_Global.jobType = FLS_JOB_READ;
+
+ Fls_Global.sourceAddr = SourceAddress;
+ Fls_Global.targetAddr = TargetAddressPtr;
+ Fls_Global.length = Length;
+
+ return E_OK;
+}
+
+#if ( FLS_COMPARE_API == STD_ON )
+Std_ReturnType Fls_Compare( MemIf_AddressType SourceAddress,
+ uint8 *TargetAddressPtr,
+ MemIf_LengthType Length )
+{
+ FLS_VALIDATE_STATUS_UNINIT_W_RV(Fls_Global.status, FLS_COMPARE_ID, E_NOT_OK);
+ FLS_VALIDATE_STATUS_BUSY_W_RV(Fls_Global.status, FLS_COMPARE_ID, E_NOT_OK);
+ FLS_VALIDATE_PARAM_ADDRESS_PAGE_W_RV(SourceAddress, FLS_COMPARE_ID, E_NOT_OK);
+ FLS_VALIDATE_PARAM_LENGTH_PAGE_W_RV(SourceAddress, Length, FLS_COMPARE_ID, E_NOT_OK);
+ FLS_VALIDATE_PARAM_DATA_W_RV((void*)SourceAddress,FLS_COMPARE_ID, E_NOT_OK)
+
+ // Always check if status is not busy
+ if (Fls_Global.status == MEMIF_BUSY )
+ return E_NOT_OK;
+
+ Fls_Global.status = MEMIF_BUSY;
+ Fls_Global.jobResultType = MEMIF_JOB_PENDING;
+ Fls_Global.jobType = FLS_JOB_COMPARE;
+
+ Fls_Global.sourceAddr = SourceAddress;
+ Fls_Global.targetAddr = TargetAddressPtr;
+ Fls_Global.length = Length;
+
+ return E_OK;
+}
+#endif
+
+#if ( FLS_SET_MODE_API == STD_ON )
+void Fls_SetMode( MemIf_ModeType Mode )
+{
+ /* API NOT SUPPORTED */
+}
+#endif
+
+void Fls_GetVersionInfo( Std_VersionInfoType *VersioninfoPtr )
+{
+ memcpy(VersioninfoPtr, &_Fls_VersionInfo, sizeof(Std_VersionInfoType));
+}
+
+
+
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+/*************************************************************************\r
+ * (c) Copyright Motorola 2005, All Rights Reserved *\r
+ *************************************************************************\r
+ * *\r
+ * Motorola reserves the right to make changes without further notice *\r
+ * to any product herein to improve reliability, function or design. *\r
+ * Motorola does not assume any liability arising out of the *\r
+ * application or use of any product, circuit, or software described *\r
+ * herein; neither does it convey any license under its patent rights *\r
+ * nor the rights of others. *\r
+ * *\r
+ * Motorola products are not designed, intended, or authorized for *\r
+ * use as components in systems intended for surgical implant into *\r
+ * the body, or other applications intended to support life, or for *\r
+ * any other application in which the failure of the Motorola product *\r
+ * could create a situation where personal injury or death may occur. *\r
+ * *\r
+ * Should Buyer purchase or use Motorola products for any such *\r
+ * unintended or unauthorized application, Buyer shall indemnify and *\r
+ * hold Motorola and its officers, employees, subsidiaries, *\r
+ * affiliates, and distributors harmless against all claims costs, *\r
+ * damages, and expenses, and reasonable attorney fees arising out *\r
+ * of, directly or indirectly, any claim of personal injury or death *\r
+ * associated with such unintended or unauthorized use, even if such *\r
+ * claim alleges that Motorola was negligent regarding the design *\r
+ * or manufacture of the part. *\r
+ * *\r
+ * Motorola and the Motorola logo* are registered trademarks of *\r
+ * Motorola Ltd. *\r
+ * *\r
+ *************************************************************************/\r
+\r
+/* This file is a a copy and modification of a freescale driver */\r
+\r
+#include "ssd_types.h"\r
+#include "ssd_h7f.h"\r
+#include <string.h>\r
+#include <assert.h>\r
+#include "Fls_H7F.h"\r
+#include "mpc55xx.h"\r
+\r
+\r
+UINT32 FlashInit ( PSSD_CONFIG pSSDConfig )\r
+{\r
+ register UINT32 returnCode; /* return code */\r
+ UINT32 MCRAddress; /* address of H7FMCR register */\r
+ UINT32 MCRValue; /* content of H7FMCR register */\r
+ UINT32 temp; /* temporary variable */\r
+\r
+ MCRAddress = pSSDConfig->h7fRegBase + H7F_MCR;\r
+ MCRValue = H7F_REG_READ (MCRAddress);\r
+\r
+ /* If MCR-STOP = 1, return directly with error code */\r
+ if (MCRValue & H7F_MCR_STOP)\r
+ {\r
+ returnCode = H7F_ERROR_STOP;\r
+ goto EXIT;\r
+ }\r
+#if 0\r
+ /* read and check the MASK */\r
+ /* use returnCode temporarily */\r
+ returnCode = H7F_REG_READ (SIU_MIDR);\r
+\r
+ if ((returnCode >> 16) == 0x5554)\r
+ {\r
+ /* if MPC5554 part, check the mask number */\r
+ if ( !((UINT16)returnCode > 3) &&\r
+ !(((UINT16)returnCode == 3) &&\r
+ ((H7F_REG_READ (pSSDConfig->shadowRowBase + 0xC8) == 0x4C4A4F4E) ||\r
+ (H7F_REG_READ (pSSDConfig->shadowRowBase + 0xE8) == 0x4C4A4F4E))))\r
+ {\r
+ returnCode = H7F_ERROR_PARTID;\r
+ goto EXIT;\r
+ }\r
+ }\r
+\r
+ if (returnCode == 0x55340000)\r
+ {\r
+ /* cannot work for MPC5534 rev0 silicon */\r
+ returnCode = H7F_ERROR_PARTID;\r
+ goto EXIT;\r
+ }\r
+#endif\r
+ /* Check MCR-EER and MCR-RWE bits */\r
+ returnCode = (MCRValue & (H7F_MCR_EER|H7F_MCR_RWE)) >> 14;\r
+ if (returnCode)\r
+ {\r
+ /* read the shadow row keyword to release the bus transfer error */\r
+ /* this is a software workaround for some H7F revision. */\r
+ temp = *(VUINT32 *)(pSSDConfig->shadowRowBase + 0xE0);\r
+ }\r
+\r
+ /* Check MCR-BBEPE and MCR-EPE bits */\r
+ returnCode |= ((~MCRValue) & (H7F_MCR_BBEPE|H7F_MCR_EPE)) >> 10;\r
+\r
+ pSSDConfig->midBlockNum = 0;\r
+ pSSDConfig->highBlockNum = 0;\r
+\r
+ /* Number of blocks in low address space and fill into SSD_CONFIG structure */\r
+ temp = (MCRValue & H7F_MCR_LAS) >> 20;\r
+\r
+ /* Number of blocks in low address space and fill into SSD_CONFIG structure\r
+ * LAS = 0: lowBlockNum = 2;\r
+ * LAS = 1: lowBlockNum = 4;\r
+ * LAS = 2: lowBlockNum = 8;\r
+ * LAS = 3: lowBlockNum = 16;\r
+ * LAS = 4: lowBlockNum = 10;\r
+ * LAS = 5: lowBlockNum = 12;\r
+ * LAS = 6: lowBlockNum = 6;\r
+ *******************************************************************************\r
+ * Special configurations\r
+ * SFS = 1, SIZE = 0, LAS = 2, MAS = 0: lowBlockNum = 4 and Flash size = 128KB;\r
+ * SFS = 1, SIZE = 1, LAS = *, MAS = 1: midBlockNum = 4 and Flash size = 320KB;\r
+ */\r
+\r
+ if (temp < 4)\r
+ {\r
+ pSSDConfig->lowBlockNum = ((UINT32)0x00000002) << temp;\r
+ }\r
+ else if (4 == temp)\r
+ {\r
+ pSSDConfig->lowBlockNum = 10;\r
+ }\r
+ else if (5 == temp)\r
+ {\r
+ pSSDConfig->lowBlockNum = 12;\r
+ }\r
+ else if (6 == temp)\r
+ {\r
+ pSSDConfig->lowBlockNum = 6;\r
+ }\r
+\r
+ /* Check if SFS bit is set to 1 */\r
+ if (MCRValue & H7F_MCR_SFS)\r
+ {\r
+ if (MCRValue & H7F_MCR_SIZE) /* SIZE = 1 */\r
+ {\r
+ pSSDConfig->mainArraySize = 0x00050000; /* Flash size is 320KB */\r
+ pSSDConfig->midBlockNum = 4; /* Mid address space: 4-16KB blocks */\r
+ }\r
+ else /* SIZE = 0 */\r
+ {\r
+ pSSDConfig->mainArraySize = 0x00020000; /* Flash size is 128KB */\r
+ /* Low address space: 2-16KB blocks and 2-48KB blocks */\r
+ pSSDConfig->lowBlockNum = 4;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Main array space size */\r
+ temp = 0x00040000 * ( ((MCRValue & H7F_MCR_SIZE) >> 24) + 1);\r
+ pSSDConfig->mainArraySize = temp;\r
+\r
+ /* Determine the number of blocks in middle address space and fill into SSD_CONFIG structure */\r
+ if ( temp > 0x00040000)\r
+ {\r
+ pSSDConfig->midBlockNum = 2 * (((MCRValue & H7F_MCR_MAS) >> 16) + 1);\r
+ }\r
+\r
+ /* Determine the number of blocks in high address space and fill into SSD_CONFIG structure */\r
+ if ( temp > 0x00080000 )\r
+ {\r
+ /* (mainArraySize - 512K) / 128K */\r
+ pSSDConfig->highBlockNum = (temp - 0x00080000) >> 17;\r
+ }\r
+ }\r
+\r
+EXIT:\r
+ if (pSSDConfig->BDMEnable)\r
+ {\r
+ //asm ( "mr r3,returnCode" ); /* save the return code to R3 */\r
+ asm ( "sc " ); /* generate system call interrupt */\r
+ }\r
+\r
+ return returnCode;\r
+}\r
+\r
+\r
+#define ERASE_STATE_START 0\r
+#define ERASE_STATE_ERASING 1\r
+\r
+\r
+UINT32 Fls_H7F_FlashErase ( PSSD_CONFIG pSSDConfig,\r
+ BOOL shadowFlag,\r
+ UINT32 lowEnabledBlocks,\r
+ UINT32 midEnabledBlocks,\r
+ UINT32 highEnabledBlocks,\r
+ Fls_EraseInfoType *eraseInfo)\r
+{\r
+ register UINT32 returnCode; /* return code */\r
+ UINT32 h7fRegBase; /* base address of H7F registers */\r
+ UINT32 MCRAddress; /* address of H7FMCR register */\r
+ UINT32 LMSAddress; /* address of H7FLMS register */\r
+ UINT32 MCRValue; /* content of H7FMCR register */\r
+ UINT32 interlockWriteAddress; /* interlock write address */\r
+\r
+\r
+ if( eraseInfo->state == ERASE_STATE_ERASING ) {\r
+ UINT32 status;\r
+ status = Fls_H7F_EraseStatus(pSSDConfig);\r
+ if( status == H7F_OK )\r
+ eraseInfo->state = ERASE_STATE_START;\r
+\r
+ return status;\r
+ }\r
+\r
+\r
+ h7fRegBase = pSSDConfig->h7fRegBase;\r
+ MCRAddress = h7fRegBase + H7F_MCR;\r
+ MCRValue = H7F_REG_READ (MCRAddress);\r
+ LMSAddress = h7fRegBase + H7F_LMS;\r
+\r
+ /* program and/or erase operation in progress */\r
+ if (MCRValue & (H7F_MCR_PGM | H7F_MCR_ERS))\r
+ {\r
+ returnCode = H7F_ERROR_BUSY;\r
+ goto EXIT;\r
+ }\r
+\r
+ /* interlock write address: shadow row block key address */\r
+ /* it will be modified to mainArrayBase in case of erasing main array */\r
+ interlockWriteAddress = pSSDConfig->shadowRowBase + 0xE0;\r
+\r
+ /* Check MCR-EER and MCR-RWE bit */\r
+ if (MCRValue & (H7F_MCR_EER | H7F_MCR_RWE))\r
+ {\r
+ /* read shadow row block key address to clear bus transfer error */\r
+ /* this is a software workaround for some H7F revision. */\r
+ /* use returnCode temporarily */\r
+ returnCode = *(VUINT32 *)interlockWriteAddress;\r
+ }\r
+\r
+ /* initialize returnCode */\r
+ returnCode = H7F_OK;\r
+\r
+ if (!shadowFlag)\r
+ {\r
+ /* erase the main array blocks */\r
+ interlockWriteAddress = pSSDConfig->mainArrayBase;\r
+\r
+ /* mask off reserved bits for low address space */\r
+ lowEnabledBlocks &= 0xFFFFFFFF >> (32 - pSSDConfig->lowBlockNum);\r
+\r
+ /* mask off reserved bits for mid address space */\r
+ lowEnabledBlocks |= (midEnabledBlocks & (0xFFFFFFFF >> (32 - pSSDConfig->midBlockNum))) << 16;\r
+\r
+ /* mask off reserved bits for high address space */\r
+ highEnabledBlocks &= 0xFFFFFFFF >> (32 - pSSDConfig->highBlockNum);\r
+\r
+ if ( !(lowEnabledBlocks | highEnabledBlocks) )\r
+ {\r
+ /* no blocks to be erased */\r
+ goto EXIT;\r
+ }\r
+\r
+ /* set the block selection registers */\r
+ H7F_REG_WRITE (LMSAddress, lowEnabledBlocks);\r
+ H7F_REG_WRITE (h7fRegBase + H7F_HBS, highEnabledBlocks);\r
+ }\r
+\r
+ /* set MCR-ERS to start erase operation */\r
+ H7FMCR_BIT_SET (MCRAddress, H7F_MCR_ERS);\r
+\r
+ /* interlock write */\r
+ *( (UINT32 *)interlockWriteAddress ) = 0xFFFFFFFF;\r
+\r
+ /* write a 1 to MCR-EHV */\r
+ H7FMCR_BIT_SET (MCRAddress, H7F_MCR_EHV);\r
+\r
+ /* This is where the freescale driver ends */\r
+ eraseInfo->state = ERASE_STATE_ERASING;\r
+\r
+EXIT:\r
+ if (pSSDConfig->BDMEnable)\r
+ {\r
+ //asm ( "mr r3,returnCode" ); /* save the return code to R3 */\r
+ asm ( "sc " ); /* generate system call interrupt */\r
+ }\r
+\r
+ return returnCode;\r
+}\r
+\r
+\r
+\r
+UINT32 Fls_H7F_EraseStatus ( PSSD_CONFIG pSSDConfig )\r
+{\r
+\r
+ UINT32 h7fRegBase; /* base address of H7F registers */\r
+ UINT32 MCRAddress; /* address of H7FMCR register */\r
+ UINT32 pfb_cr_val; /* value of PFB_CR register */\r
+ UINT32 returnCode;\r
+\r
+ h7fRegBase = pSSDConfig->h7fRegBase;\r
+ MCRAddress = h7fRegBase + H7F_MCR;\r
+\r
+ returnCode = H7F_OK;\r
+\r
+ /* wait until MCR-DONE set */\r
+ if( !(H7F_REG_READ (MCRAddress) & H7F_MCR_DONE) )\r
+ {\r
+ return 0x1000; // Ehh, busy\r
+ }\r
+\r
+ /* clear MCR-EHV bit */\r
+ H7FMCR_BIT_CLEAR (MCRAddress, H7F_MCR_EHV);\r
+\r
+ /* confirm MCR-PEG = 1 */\r
+ if ( !(H7F_REG_READ (MCRAddress) & H7F_MCR_PEG) )\r
+ {\r
+ returnCode = H7F_ERROR_EGOOD;\r
+ }\r
+\r
+ /* save PFB_CR */\r
+ pfb_cr_val = H7F_REG_READ(h7fRegBase + PFB_CR);\r
+\r
+ /* invalidate the PFBIU line read buffer */\r
+ H7F_REG_BIT_CLEAR (h7fRegBase + PFB_CR, PFB_CR_BFEN);\r
+\r
+ /* clear MCR-ERS bit */\r
+ H7FMCR_BIT_CLEAR (MCRAddress, H7F_MCR_ERS);\r
+\r
+ /* invalidate the PFBIU line read buffer */\r
+ H7F_REG_BIT_SET (h7fRegBase + PFB_CR, PFB_CR_BFEN);\r
+\r
+ /* restore PFB_CR */\r
+ H7F_REG_WRITE(h7fRegBase + PFB_CR, pfb_cr_val);\r
+\r
+//EXIT:\r
+ if (pSSDConfig->BDMEnable)\r
+ {\r
+ //asm ( "mr r3,returnCode" ); /* save the return code to R3 */\r
+ asm ( "sc " ); /* generate system call interrupt */\r
+ }\r
+\r
+ return returnCode;\r
+}\r
+\r
+\r
+// First state.... init stuff\r
+#define STATE_INIT 0\r
+//\r
+#define STATE_PROGRAMMING 1\r
+//#define STATE_WAIT_DONE 2\r
+\r
+#if 0\r
+UINT32 FlashProgram ( PSSD_CONFIG pSSDConfig,\r
+ UINT32 dest,\r
+ UINT32 size,\r
+ UINT32 source,\r
+ void(*CallBack)(void)\r
+ )\r
+#endif\r
+\r
+\r
+#define MY_BUSY 0x1000\r
+\r
+static UINT32 Fls_H7F_ProgramPage( PSSD_CONFIG pSSDConfig, Fls_ProgInfoType *pInfo );\r
+static UINT32 Fls_H7F_ProgramStatus ( PSSD_CONFIG pSSDConfig, Fls_ProgInfoType *pInfo );\r
+static UINT32 Fls_H7F_ProgramInit( PSSD_CONFIG pSSDConfig, Fls_ProgInfoType *pInfo );\r
+\r
+UINT32 Fls_H7F_Program ( PSSD_CONFIG pSSDConfig, Fls_ProgInfoType *pInfo )\r
+{\r
+ UINT32 returnCode; /* return code */\r
+\r
+ switch( pInfo->state ) {\r
+ case STATE_INIT:\r
+ returnCode = Fls_H7F_ProgramInit(pSSDConfig,pInfo);\r
+ if( returnCode == H7F_OK ) {\r
+ returnCode = Fls_H7F_ProgramPage(pSSDConfig,pInfo);\r
+ }\r
+ pInfo->state = STATE_PROGRAMMING;\r
+ break;\r
+ case STATE_PROGRAMMING:\r
+ returnCode = Fls_H7F_ProgramStatus(pSSDConfig,pInfo);\r
+ break;\r
+ default:\r
+ assert(0);\r
+ break;\r
+ }\r
+\r
+ return returnCode;\r
+}\r
+\r
+static UINT32 Fls_H7F_ProgramInit( PSSD_CONFIG pSSDConfig, Fls_ProgInfoType *pInfo ) {\r
+\r
+\r
+ UINT32 returnCode;\r
+ // UINT32 sourceIndex; /* source address index */\r
+ UINT32 MCRAddress; /* address of H7FMCR register */\r
+ UINT32 MCRValue; /* content of H7FMCR register */\r
+\r
+ UINT32 shadowRowEnd; /* shadow row base + shadow size */\r
+ UINT32 mainArrayEnd; /* main array base + main array size */\r
+ // UINT32 temp; /* dest + size, or size / H7F_DWORD_SIZE */\r
+ // UINT32 pageSize; /* page size depending on flash type */\r
+\r
+ UINT8 rangeType; /* position of the program memory range */\r
+ /* rangeType = 1 - shadow row */\r
+ /* rangeType = 2 - main array */\r
+\r
+ // UINT32 pfb_cr_val; /* value of PFB_CR register */\r
+ returnCode = H7F_OK;\r
+ pInfo->pageSize = 16; /* default setting is 16 bytes */\r
+ MCRAddress = pSSDConfig->h7fRegBase + H7F_MCR;\r
+\r
+ /* Check alignments */\r
+ if ( (((pInfo->dest | pInfo->size) % H7F_DWORD_SIZE) != 0) ||\r
+ ((pInfo->source % H7F_WORD_SIZE) != 0))\r
+ {\r
+ returnCode = H7F_ERROR_ALIGNMENT;\r
+ goto EXIT;\r
+ }\r
+\r
+ /* The flash range should fall within either shadow row or main array */\r
+ shadowRowEnd = pSSDConfig->shadowRowBase + pSSDConfig->shadowRowSize;\r
+ mainArrayEnd = pSSDConfig->mainArrayBase + pSSDConfig->mainArraySize;\r
+ pInfo->temp = pInfo->dest + pInfo->size;\r
+\r
+ if ((pInfo->dest >= pSSDConfig->shadowRowBase) && (pInfo->dest < shadowRowEnd) &&\r
+ (pInfo->size <= pSSDConfig->shadowRowSize) && (pInfo->temp <= shadowRowEnd))\r
+ {\r
+ /* fall in shadow row */\r
+ rangeType = 1;\r
+ }\r
+ else if ((pInfo->dest >= pSSDConfig->mainArrayBase) && (pInfo->dest < mainArrayEnd) &&\r
+ (pInfo->size <= pSSDConfig->mainArraySize) && (pInfo->temp <= mainArrayEnd))\r
+ {\r
+ /* fall in main array */\r
+ rangeType = 2;\r
+ }\r
+ else\r
+ {\r
+ returnCode = H7F_ERROR_RANGE;\r
+ goto EXIT;\r
+ }\r
+\r
+ /* Anything to program? */\r
+ if ( !pInfo->size )\r
+ goto EXIT;\r
+\r
+ MCRValue = H7F_REG_READ (MCRAddress);\r
+\r
+ /* Cases that program operation can start:\r
+ 1. no program and erase sequence:\r
+ (PGM low and ERS low)\r
+ 2. erase suspend with EHV low on main array and try to program main array\r
+ (PGM low, PEAS low, ERS high, ESUS high, EHV low, and rangeType = 2)\r
+\r
+ Cases that program operation cannot start:\r
+ 1. program in progress (PGM high);\r
+ 2. program not in progress (PGM low):\r
+ a. erase in progress but not in suspend state;\r
+ b. erase in suspend state on main array but try to program shadow row;\r
+ c. erase suspend on shadow row; */\r
+\r
+ if ( !( (!(MCRValue & (H7F_MCR_PGM | H7F_MCR_ERS))) ||\r
+ (!(MCRValue & (H7F_MCR_PGM | H7F_MCR_PEAS | H7F_MCR_EHV)) &&\r
+ ((MCRValue & (H7F_MCR_ERS | H7F_MCR_ESUS)) == (H7F_MCR_ERS | H7F_MCR_ESUS)) &&\r
+ (rangeType == 2)) ) )\r
+ {\r
+ returnCode = H7F_ERROR_BUSY;\r
+ goto EXIT;\r
+ }\r
+\r
+ /* Check MCR-EER and MCR-RWE bit */\r
+ if (MCRValue & (H7F_MCR_EER | H7F_MCR_RWE))\r
+ {\r
+ /* use shadow row to release bus error */\r
+ pInfo->temp = *(VUINT32 *)(pSSDConfig->shadowRowBase + 0xE0);\r
+ }\r
+\r
+ /* Set MCR-PGM to start program operation */\r
+ H7FMCR_BIT_SET (MCRAddress, H7F_MCR_PGM);\r
+\r
+ /* number of double words */\r
+ pInfo->temp = pInfo->size / H7F_DWORD_SIZE;\r
+\r
+ /* determine the page size */\r
+ if (pSSDConfig->pageSize == H7FA_PAGE_SIZE)\r
+ {\r
+ /* H7Fa page size is 32 bytes */\r
+ pInfo->pageSize = 32;\r
+ }\r
+ else if(pSSDConfig->pageSize == H7FB_PAGE_SIZE)\r
+ {\r
+ /* H7Fb page size is 16 bytes */\r
+ /* this is also the default setting */\r
+ /*\r
+ pInfo->pageSize = 16;\r
+ */\r
+ }\r
+\r
+ pInfo->sourceIndex = 1;\r
+#if 0\r
+ if( FlashProgramPage_r(pSSDConfig,pInfo) == H7F_BUSY ) {\r
+ return H7F_BUSY; /* busy */\r
+ }\r
+\r
+ returnCode = FlashProgramStatus_r ( pSSDConfig, pInfo );\r
+#endif\r
+EXIT:\r
+ if (pSSDConfig->BDMEnable)\r
+ {\r
+ //asm ( "mr r3,returnCode" ); /* save the return code to R3 */\r
+ asm ( "sc " ); /* generate system call interrupt */\r
+ }\r
+\r
+\r
+ return returnCode;\r
+}\r
+\r
+/**\r
+ * Programs a flash page. Assumes that FlashProgram_r() is called before.\r
+ * Subsequent calls are made to this function until the programming operation is done\r
+ *\r
+ * @param pSSDConfig Flash configuration\r
+ * @param pInfo Structure used by the page programmer. It's initially filled in by FlashProgram_r()\r
+ *\r
+ * @returns Status of the flash programming. See ssd_h7f. for more information. 0x1000 added\r
+ * as return value when the device is busy\r
+\r
+ */\r
+\r
+static UINT32 Fls_H7F_ProgramPage( PSSD_CONFIG pSSDConfig, Fls_ProgInfoType *pInfo ) {\r
+\r
+ UINT32 returnCode = 0;\r
+\r
+ UINT32 MCRAddress = pSSDConfig->h7fRegBase + H7F_MCR;\r
+\r
+ /* Program data page by page, with special attention to incomplete page */\r
+ if( pInfo->sourceIndex <= pInfo->temp ) {\r
+ /* Programming write */\r
+ *(UINT64 *)pInfo->dest = *(UINT64 *)pInfo->source;\r
+\r
+ /* Update pInfo->source index */\r
+ pInfo->dest += H7F_DWORD_SIZE;\r
+ pInfo->source += H7F_DWORD_SIZE;\r
+\r
+ /* Is it time to do page programming? */\r
+ if ( ((pInfo->dest % pInfo->pageSize) == 0) || (pInfo->sourceIndex == pInfo->temp) )\r
+ {\r
+ /* Set MCR-EHV bit */\r
+ H7FMCR_BIT_SET (MCRAddress, H7F_MCR_EHV);\r
+ }\r
+ returnCode = H7F_BUSY;\r
+ }\r
+\r
+ return returnCode;\r
+}\r
+\r
+\r
+/**\r
+ * Returns the status of the flash programming\r
+ *\r
+ */\r
+\r
+UINT32 Fls_H7F_ProgramStatus ( PSSD_CONFIG pSSDConfig, Fls_ProgInfoType *pInfo ) {\r
+\r
+ UINT32 MCRAddress; /* address of H7FMCR register */\r
+ UINT32 pfb_cr_val;\r
+ UINT32 returnCode = H7F_OK;\r
+\r
+ MCRAddress = pSSDConfig->h7fRegBase + H7F_MCR;\r
+\r
+ /* Wait until MCR-DONE set */\r
+ if ( !(H7F_REG_READ (MCRAddress) & H7F_MCR_DONE) )\r
+ {\r
+ return H7F_BUSY;\r
+ }\r
+\r
+ /* Confirm MCR-PEG = 1 */\r
+ if ( !(H7F_REG_READ (MCRAddress) & H7F_MCR_PEG) )\r
+ {\r
+ /* Clear MCR-EHV bit */\r
+ H7FMCR_BIT_CLEAR (MCRAddress, H7F_MCR_EHV);\r
+\r
+ returnCode = H7F_ERROR_PGOOD;\r
+ goto EXIT_EHV;\r
+ }\r
+\r
+ /* Clear MCR-EHV bit */\r
+ H7FMCR_BIT_CLEAR (MCRAddress, H7F_MCR_EHV);\r
+ pInfo->sourceIndex++;\r
+\r
+ returnCode = Fls_H7F_ProgramPage( pSSDConfig,pInfo );\r
+ if( (returnCode) == H7F_BUSY ) {\r
+ return H7F_BUSY;\r
+ }\r
+\r
+ /* Clear MCR-PGM bit */\r
+ H7FMCR_BIT_CLEAR (MCRAddress, H7F_MCR_PGM);\r
+\r
+ /* save PFB_CR */\r
+ pfb_cr_val = H7F_REG_READ(pSSDConfig->h7fRegBase + PFB_CR);\r
+\r
+ /* Invalidate the PFBIU line read buffer */\r
+ H7F_REG_BIT_CLEAR (pSSDConfig->h7fRegBase + PFB_CR, PFB_CR_BFEN);\r
+\r
+ /* Invalidate the PFBIU line read buffer */\r
+ H7F_REG_BIT_SET (pSSDConfig->h7fRegBase + PFB_CR, PFB_CR_BFEN);\r
+\r
+ /* restore PFB_CR */\r
+ H7F_REG_WRITE(pSSDConfig->h7fRegBase + PFB_CR, pfb_cr_val);\r
+\r
+ // Clear our struct....\r
+ memset( pInfo,0x0,sizeof(Fls_ProgInfoType) );\r
+\r
+EXIT_EHV:\r
+ return returnCode;\r
+}\r
+\r
+#define FLASH_LMLR_PASSWORD 0xA1A11111 /* Low/Mid address lock enabled password */\r
+#define FLASH_HLR_PASSWORD 0xB2B22222 /* High address lock enabled password */\r
+#define FLASH_SLMLR_PASSWORD 0xC3C33333 /* Secondary low and middle address lock enabled password */\r
+\r
+/* TODO: use PSSD_CONFIG ( regbase, etc instead of hardcoded FLASH ) */\r
+\r
+\r
+/**\r
+ * Function that handles the locks bits the flash. Handled bits\r
+ * are LLOCK, MLOCK, SLOCK, HLOCK\r
+ * Secondary locks are NOT supported.\r
+ *\r
+ * @param blocks - Blocks to set lock or unlock.\r
+ * @param logic - A '1' interpretes 1 in blocks as lock, A '0' as unlock\r
+ */\r
+void Fls_H7F_SetLock ( Fls_EraseBlockType *blocks, UINT8 logic )\r
+{\r
+ vuint32_t *reg;\r
+ struct FLASH_tag *flashHw = &FLASH;\r
+\r
+ if( (blocks->lowEnabledBlocks != 0 ) ||\r
+ (blocks->midEnabledBlocks != 0 ) ||\r
+ (blocks->shadowBlocks != 0 ) )\r
+ {\r
+ reg = &(flashHw->LMLR.R);\r
+\r
+ // Check if sector is locked\r
+ if( !(*reg & 0x80000000 )) {\r
+ // Unlock the sector with password\r
+ *reg = FLASH_LMLR_PASSWORD;\r
+ }\r
+\r
+ // set/clear them\r
+ if( logic ) {\r
+ *reg |= ((blocks->midEnabledBlocks<<16)& H7F_LML_MLOCK) +\r
+ (blocks->lowEnabledBlocks & H7F_LML_LLOCK) +\r
+ (blocks->shadowBlocks & H7F_LML_SLOCK);\r
+ } else {\r
+ *reg &= ((~blocks->midEnabledBlocks<<16) & H7F_LML_MLOCK) |\r
+ ((~blocks->lowEnabledBlocks) & H7F_LML_LLOCK) |\r
+ ((~blocks->shadowBlocks) & H7F_LML_SLOCK) ;\r
+ }\r
+ }\r
+#if 0\r
+ else {\r
+ reg = &(flashHw->LMLR.R);\r
+ // Set all\r
+ *reg |= 0x8003003f;\r
+ }\r
+#endif\r
+\r
+ if( (blocks->highEnabledBlocks != 0 )) {\r
+ reg = &(flashHw->HLR.R);\r
+\r
+ if( !(*reg & 0x80000000 )) {\r
+ // Unlock\r
+ *reg = FLASH_HLR_PASSWORD;\r
+ }\r
+ // clear\r
+ // *reg &= ~(H7F_HBL_HBLOCK);\r
+ // Set\r
+ if( logic ) {\r
+ *reg |= ((blocks->highEnabledBlocks)& H7F_HBL_HBLOCK);\r
+ } else {\r
+ *reg &= ((~blocks->highEnabledBlocks)& H7F_HBL_HBLOCK);\r
+ }\r
+ }\r
+#if 0\r
+ else {\r
+ reg = &(flashHw->HLR.R);\r
+ // Set all\r
+ *reg |= 0x800000ff;\r
+ }\r
+#endif\r
+}\r
+\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef FLS_H7F_H_\r
+#define FLS_H7F_H_\r
+\r
+#define FLS_ERASE_SECTION __attribute__ ((section (".fls_erase")));\r
+#define FLS_WRITE_SECTION __attribute__ ((section (".fls_write")));\r
+\r
+#define H7F_BUSY 0x1000\r
+\r
+typedef struct {\r
+ UINT32 dest;\r
+ UINT32 size;\r
+ UINT32 source;\r
+ UINT32 pageSize;\r
+ UINT32 sourceIndex;\r
+ UINT32 temp;\r
+ UINT32 state;\r
+} Fls_ProgInfoType;\r
+\r
+typedef struct {\r
+ UINT32 state;\r
+} Fls_EraseInfoType;\r
+\r
+typedef struct {\r
+ UINT32 lowEnabledBlocks;\r
+ UINT32 midEnabledBlocks;\r
+ UINT32 highEnabledBlocks;\r
+ // 1 - primary, 2 - secondary\r
+ UINT32 shadowBlocks;\r
+} Fls_EraseBlockType;\r
+\r
+// TODO : document API\r
+UINT32 Fls_H7F_FlashErase ( PSSD_CONFIG pSSDConfig,\r
+ BOOL shadowFlag,\r
+ UINT32 lowEnabledBlocks,\r
+ UINT32 midEnabledBlocks,\r
+ UINT32 highEnabledBlocks,\r
+ Fls_EraseInfoType *eraseInfo) FLS_ERASE_SECTION;\r
+\r
+UINT32 Fls_H7F_EraseStatus ( PSSD_CONFIG pSSDConfig ) FLS_ERASE_SECTION ;\r
+\r
+UINT32 Fls_H7F_Program ( PSSD_CONFIG pSSDConfig, Fls_ProgInfoType *pInfo ) FLS_WRITE_SECTION ;\r
+\r
+void Fls_H7F_SetLock(Fls_EraseBlockType*,UINT8);\r
+\r
+#endif /*FLS_H7F_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*\r
+ * timer.c\r
+ *\r
+ * Created on: 2009-jan-17\r
+ * Author: mahi\r
+ */\r
+\r
+#include "Os.h"\r
+#include "sys.h"\r
+#include "pcb.h"\r
+#include "internal.h"\r
+\r
+/**\r
+ * Init of free running timer.\r
+ */\r
+void Frt_Init( void ) {\r
+ TaskType tid;\r
+ tid = Os_CreateIsr(OsTick,6/*prio*/,"OsTick");\r
+ IntCtrl_AttachIsr2(tid,NULL,7);\r
+}\r
+\r
+/**\r
+ *\r
+ *
+ * @param period_ticks How long the period in timer ticks should be. The timer\r
+ * on PowerPC often driver by the CPU clock or some platform clock.\r
+ *
+ */\r
+void Frt_Start(uint32_t period_ticks) {\r
+ uint32_t tmp;\r
+\r
+ // Enable the TB\r
+ tmp = get_spr(SPR_HID0);\r
+ tmp |= HID0_TBEN;\r
+ set_spr(SPR_HID0, tmp);\r
+\r
+ /* Initialize the Decrementer */\r
+ set_spr(SPR_DEC, period_ticks);\r
+ set_spr(SPR_DECAR, period_ticks);\r
+\r
+ /* Set autoreload */\r
+ tmp = get_spr(SPR_TCR);\r
+ tmp |= TCR_ARE;\r
+ set_spr(SPR_TCR, tmp);\r
+\r
+ /* Enable notification */\r
+ tmp = get_spr(SPR_TCR);\r
+ tmp |= TCR_DIE;\r
+ set_spr(SPR_TCR, tmp );\r
+}\r
+\r
+/**\r
+ * ???\r
+ * TODO: This function just subtract the max value?! ok??\r
+ *
+ * @return
+ */\r
+\r
+uint32_t Frt_GetTimeElapsed( void )\r
+{\r
+ uint32_t timer = get_spr(SPR_DECAR) - get_spr(SPR_DEC);\r
+ return (timer);\r
+}\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include "Std_Types.h"\r
+#include "Gpt.h"\r
+#include "Cpu.h"\r
+#include <assert.h>\r
+#include <string.h>\r
+#include "mpc55xx.h"\r
+#include "Mcu.h"\r
+#include "Trace.h"\r
+#include "Det.h"\r
+\r
+// Implementation specific\r
+\r
+#if ( GPT_DEV_ERROR_DETECT == STD_ON )\r
+#define VALIDATE(_exp,_api,_err ) \\r
+ if( !(_exp) ) { \\r
+ Det_ReportError(MODULE_ID_GPT,0,_api,_err); \\r
+ return; \\r
+ }\r
+\r
+#define VALIDATE_W_RV(_exp,_api,_err,_rv ) \\r
+ if( !(_exp) ) { \\r
+ Det_ReportError(MODULE_ID_GPT,0,_api,_err); \\r
+ return (_rv); \\r
+ }\r
+\r
+#define VALID_CHANNEL(_ch) ( Gpt_Global.configured & (1<<(_ch)) )\r
+\r
+#else\r
+#define VALIDATE(_exp,_api,_err )\r
+#define VALIDATE_W_RV(_exp,_api,_err,_rv )\r
+#endif\r
+\r
+typedef enum\r
+{\r
+ GPT_STATE_STOPPED = 0,\r
+ GPT_STATE_STARTED,\r
+} Gpt_StateType;\r
+\r
+/**\r
+ * Type that holds all global data for Gpt\r
+ */\r
+typedef struct\r
+{\r
+ // Set if Gpt_Init() have been called\r
+ boolean initRun;\r
+\r
+ // Our config\r
+ const Gpt_ConfigType *config;\r
+\r
+ uint8 wakeupEnabled;\r
+\r
+ // One bit for each channel that is configured.\r
+ // Used to determine if validity of a channel\r
+ // 1 - configured\r
+ // 0 - NOT configured\r
+ uint32 configured;\r
+\r
+ // Maps the a channel id to a configured channel id\r
+ uint8 channelMap[GPT_CHANNEL_CNT];\r
+\r
+} Gpt_GlobalType;\r
+\r
+/**\r
+ * Type that holds data that are specific for a channel\r
+ */\r
+typedef struct\r
+{\r
+ Gpt_StateType state;\r
+} Gpt_UnitType;\r
+\r
+Gpt_UnitType Gpt_Unit[GPT_CHANNEL_CNT];\r
+\r
+// Global config\r
+Gpt_GlobalType Gpt_Global;\r
+\r
+//-------------------------------------------------------------------\r
+\r
+\r
+/**\r
+ * ISR helper-function that handles the HW channels( 0 to 8 )\r
+ *\r
+ * @param channel - Channel that the raised the interrupt\r
+ */\r
+\r
+static void Gpt_IsrCh(Gpt_ChannelType channel)\r
+{\r
+ const Gpt_ConfigType *config;\r
+ int confCh;\r
+\r
+ confCh = Gpt_Global.channelMap[channel];\r
+ assert(confCh != GPT_CHANNEL_ILL);\r
+\r
+ config = &Gpt_Global.config[confCh];\r
+\r
+ if (config->GptChannelMode == GPT_MODE_ONESHOT)\r
+ {\r
+ // Disable the channel\r
+ PIT.EN.R &= ~(1<<channel);\r
+\r
+ Gpt_Unit[channel].state = GPT_STATE_STOPPED;\r
+ }\r
+ config->GptNotification();\r
+\r
+ // Clear interrupt\r
+ PIT.FLG.R = (1<<channel); // Added by Mattias 2009-01\r
+}\r
+\r
+//-------------------------------------------------------------------\r
+// Macro that counts leading zeroes.\r
+#define CNTLZW_INV(x) (31-cntlzw(x))\r
+\r
+/**\r
+ * ISR that handles all interrupts to the PIT channels\r
+ * ( NOT the decrementer )\r
+ */\r
+\r
+static void Gpt_Isr(void)\r
+{\r
+ uint32 flgMask= PIT.FLG.R;\r
+ uint8 chNr = 0;\r
+\r
+ // Loop over all interrupts\r
+ for (; flgMask; flgMask&=~(1<<chNr))\r
+ {\r
+ // Find first channel that is requesting service.\r
+ chNr = CNTLZW_INV(flgMask);\r
+ Gpt_IsrCh(chNr);\r
+ // Clear interrupt\r
+ PIT.FLG.R = (1<<chNr);\r
+ }\r
+}\r
+\r
+//-------------------------------------------------------------------\r
+\r
+void Gpt_Init(const Gpt_ConfigType *config)\r
+{\r
+ uint32_t i=0;\r
+ const Gpt_ConfigType *cfg;\r
+ VALIDATE( (Gpt_Global.initRun == STD_OFF), GPT_INIT_SERVICE_ID, GPT_E_ALREADY_INITIALIZED );\r
+#if defined(GPT_VARIANT_PB)\r
+ VALIDATE( (config != NULL ), GPT_INIT_SERVICE_ID, GPT_E_PARAM_CONFIG );\r
+#elif defined(GPT_VARIANT_PC)\r
+ // We don't support GPT_VARIANT_PC\r
+ assert(0);\r
+#endif\r
+ Gpt_ChannelType ch;\r
+\r
+ for (i=0; i<GPT_CHANNEL_CNT; i++)\r
+ {\r
+ Gpt_Global.channelMap[i] = GPT_CHANNEL_ILL;\r
+ }\r
+\r
+ i = 0;\r
+ cfg = config;\r
+ while (cfg->GptChannelId != GPT_CHANNEL_ILL)\r
+ {\r
+ ch = cfg->GptChannelId;\r
+\r
+ // Assign the configuration channel used later..\r
+ Gpt_Global.channelMap[cfg->GptChannelId] = i;\r
+ Gpt_Global.configured |= (1<<ch);\r
+\r
+ if (ch <= GPT_CHANNEL_PIT_8)\r
+ {\r
+ if (cfg->GptNotification != NULL)\r
+ {\r
+ IntCtrl_InstallVector(Gpt_Isr, PIT_PITFLG_RTIF + ch, 1, CPU_Z1);\r
+ }\r
+ }\r
+#if defined(USE_KERNEL)\r
+ // Don't install if we use kernel.. it handles that.\r
+#else\r
+ else if (ch == GPT_CHANNEL_DEC)\r
+ {\r
+ // Decrementer event is default an exception. Use software interrupt 7 as wrapper.\r
+ IntCtrl_InstallVector(config[i].GptNotification, INTC_SSCIR0_CLR7, 1, CPU_Z1);\r
+ }\r
+#endif\r
+\r
+ cfg++;\r
+ i++;\r
+ }\r
+\r
+ Gpt_Global.config = config;\r
+\r
+ Gpt_Global.initRun = STD_ON;\r
+ PIT.CTRL.B.MDIS = 0;\r
+}\r
+\r
+//-------------------------------------------------------------------\r
+\r
+#if GPT_DEINIT_API == STD_ON\r
+void Gpt_DeInit(void)\r
+{\r
+ Gpt_ChannelType channel;\r
+ VALIDATE( (Gpt_Global.initRun == STD_ON), GPT_DEINIT_SERVICE_ID, GPT_E_UNINIT );\r
+ for (channel=0; channel<GPT_CHANNEL_CNT; channel++) // Validate that all channels have been stopped\r
+ {\r
+ VALIDATE( (Gpt_Unit[channel].state == GPT_STATE_STOPPED), GPT_DEINIT_SERVICE_ID, GPT_E_BUSY );\r
+ Gpt_StopTimer(channel); // Should this be done here?\r
+ }\r
+ Gpt_Global.initRun = STD_OFF;\r
+ Gpt_Global.configured = 0;\r
+ //_config.config = NULL;\r
+}\r
+#endif\r
+\r
+//-------------------------------------------------------------------\r
+// period is in "ticks" !!\r
+void Gpt_StartTimer(Gpt_ChannelType channel, Gpt_ValueType period_ticks)\r
+{\r
+ uint32_t tmp;\r
+ int confCh;\r
+\r
+ VALIDATE( (Gpt_Global.initRun == STD_ON), GPT_STARTTIMER_SERVICE_ID, GPT_E_UNINIT );\r
+ VALIDATE( VALID_CHANNEL(channel), GPT_STARTTIMER_SERVICE_ID, GPT_E_PARAM_CHANNEL );\r
+ VALIDATE( (Gpt_Unit[channel].state == GPT_STATE_STOPPED), GPT_STARTTIMER_SERVICE_ID, GPT_E_BUSY );\r
+ // GPT_E_PARAM_VALUE, all have 32-bit so no need to check\r
+\r
+ DEBUG(DEBUG_HIGH, "Gpt_StartTimer ch=%d, period=%d [ticks]\n", channel, period_ticks);\r
+\r
+ confCh = Gpt_Global.channelMap[channel];\r
+\r
+ if (channel <= GPT_CHANNEL_PIT_8)\r
+ {\r
+ uint32 *tlval = (uint32 *)&PIT.TLVAL0;\r
+ uint32 *tval = (uint32 *)&PIT.TVAL0;\r
+\r
+ tlval[channel] = period_ticks;\r
+ tval[channel] = period_ticks;\r
+\r
+ // always select interrupt\r
+ if (channel != GPT_CHANNEL_RTI)\r
+ {\r
+ PIT.INTSEL.R |= ( 1 << channel );\r
+ }\r
+\r
+ // Make sure that no interrupt is pending.\r
+ PIT.FLG.R = ( 1 << channel );\r
+\r
+ // Enable timer\r
+ PIT.EN.R |= ( 1 << channel );\r
+ }\r
+ else if (channel == GPT_CHANNEL_DEC)\r
+ {\r
+ // Enable the TB\r
+ tmp = get_spr(SPR_HID0);\r
+ tmp |= HID0_TBEN;\r
+ set_spr(SPR_HID0,tmp);\r
+\r
+ /* Initialize the Decrementer */\r
+ set_spr(SPR_DEC, period_ticks);\r
+ set_spr(SPR_DECAR, period_ticks);\r
+\r
+ if( Gpt_Global.config[confCh].GptChannelMode == GPT_MODE_CONTINUOUS )\r
+ {\r
+ /* Set autoreload */\r
+ tmp = get_spr(SPR_TCR);\r
+ tmp |= TCR_ARE;\r
+ set_spr(SPR_TCR,tmp);\r
+ }\r
+ }\r
+\r
+ if( Gpt_Global.config[confCh].GptNotification != NULL )\r
+ {\r
+ // GPT275\r
+ Gpt_EnableNotification(channel);\r
+ }\r
+\r
+ Gpt_Unit[channel].state = GPT_STATE_STARTED;\r
+}\r
+\r
+void Gpt_StopTimer(Gpt_ChannelType channel)\r
+{\r
+\r
+ VALIDATE( (Gpt_Global.initRun == STD_ON), GPT_STOPTIMER_SERVICE_ID, GPT_E_UNINIT );\r
+ VALIDATE( VALID_CHANNEL(channel), GPT_STOPTIMER_SERVICE_ID, GPT_E_PARAM_CHANNEL );\r
+\r
+ if (channel <= GPT_CHANNEL_PIT_8)\r
+ {\r
+ // Disable timer\r
+ PIT.EN.R &= ~( 1 << channel );\r
+ }\r
+ else if (channel == GPT_CHANNEL_DEC)\r
+ {\r
+ uint32 tb;\r
+ tb = get_spr(SPR_HID0);\r
+ tb &= ~HID0_TBEN;\r
+ set_spr(SPR_HID0,tb);\r
+ }\r
+\r
+ Gpt_DisableNotification(channel);\r
+ Gpt_Unit[channel].state = GPT_STATE_STOPPED;\r
+}\r
+\r
+#if ( GPT_TIME_REMAINING_API == STD_ON )\r
+\r
+Gpt_ValueType Gpt_GetTimeRemaining(Gpt_ChannelType channel)\r
+{\r
+ VALIDATE_W_RV( (Gpt_Global.initRun == STD_ON), GPT_GETTIMEREMAINING_SERVICE_ID, GPT_E_UNINIT, 0 );\r
+ VALIDATE_W_RV( VALID_CHANNEL(channel),GPT_GETTIMEREMAINING_SERVICE_ID, GPT_E_PARAM_CHANNEL, 0 );\r
+ VALIDATE_W_RV( (Gpt_Unit[channel].state == GPT_STATE_STARTED), GPT_GETTIMEREMAINING_SERVICE_ID, GPT_E_NOT_STARTED, 0 );\r
+ Gpt_ValueType remaining;\r
+\r
+ if (channel <= GPT_CHANNEL_PIT_8)\r
+ {\r
+ uint32 *tval = (uint32 *)&PIT.TVAL0;\r
+ // Time remaining is the time until it hits 0, so just return the current timer value\r
+ remaining = tval[channel];\r
+ }\r
+ else if (channel == GPT_CHANNEL_DEC)\r
+ {\r
+ remaining = get_spr(SPR_DEC);\r
+ }\r
+\r
+return remaining;\r
+}\r
+#endif\r
+\r
+#if ( GPT_TIME_ELAPSED_API == STD_ON )\r
+Gpt_ValueType Gpt_GetTimeElapsed(Gpt_ChannelType channel)\r
+{\r
+ Gpt_ValueType timer;\r
+\r
+ VALIDATE_W_RV( (Gpt_Global.initRun == STD_ON), GPT_GETTIMEELAPSED_SERVICE_ID, GPT_E_UNINIT ,0 );\r
+ VALIDATE_W_RV( VALID_CHANNEL(channel),GPT_GETTIMEELAPSED_SERVICE_ID, GPT_E_PARAM_CHANNEL, 0 );\r
+ VALIDATE_W_RV( (Gpt_Unit[channel].state == GPT_STATE_STARTED),GPT_GETTIMEELAPSED_SERVICE_ID, GPT_E_NOT_STARTED, 0 );\r
+\r
+ // NOTE!\r
+ // These little creatures count down\r
+\r
+ if (channel <= GPT_CHANNEL_PIT_8)\r
+ {\r
+ uint32 *tval = (uint32 *)&PIT.TVAL0;\r
+ uint32 *tlval = (uint32 *)&PIT.TLVAL0;\r
+ timer = tlval[channel] - tval[channel];\r
+ }\r
+ else if (channel == GPT_CHANNEL_DEC)\r
+ {\r
+ timer = get_spr(SPR_DECAR) - get_spr(SPR_DEC);\r
+ }\r
+\r
+ return (timer);\r
+}\r
+#endif\r
+\r
+#if ( GPT_ENABLE_DISABLE_NOTIFICATION_API == STD_ON )\r
+void Gpt_EnableNotification(Gpt_ChannelType channel)\r
+{\r
+\r
+ VALIDATE( (Gpt_Global.initRun == STD_ON), 0x7, GPT_E_UNINIT );\r
+ VALIDATE( VALID_CHANNEL(channel),0x7, GPT_E_PARAM_CHANNEL );\r
+\r
+ if (channel <= GPT_CHANNEL_PIT_8)\r
+ {\r
+ // enable interrupts\r
+ PIT.INTEN.R |= ( 1 << channel );\r
+ }\r
+ else if (channel == GPT_CHANNEL_DEC)\r
+ {\r
+ uint32 tmp;\r
+ tmp = get_spr(SPR_TCR);\r
+ tmp |= TCR_DIE;\r
+ set_spr(SPR_TCR, tmp );\r
+ }\r
+}\r
+\r
+void Gpt_DisableNotification(Gpt_ChannelType channel)\r
+{\r
+\r
+ VALIDATE( (Gpt_Global.initRun == STD_ON), 0x8, GPT_E_UNINIT );\r
+ VALIDATE( VALID_CHANNEL(channel),0x8, GPT_E_PARAM_CHANNEL );\r
+\r
+ if (channel <= GPT_CHANNEL_PIT_8)\r
+ {\r
+ PIT.INTEN.R &= ~( 1 << channel );\r
+ }\r
+ else if (channel == GPT_CHANNEL_DEC)\r
+ {\r
+ uint32 tmp;\r
+ tmp = get_spr(SPR_TCR);\r
+ tmp &= ~TCR_DIE;\r
+ set_spr(SPR_TCR, tmp );\r
+ }\r
+\r
+ return;\r
+}\r
+\r
+#endif\r
+\r
+#if ( GPT_WAKEUP_FUNCTIONALITY_API == STD_ON )\r
+\r
+void Gpt_SetMode(Gpt_ModeType mode)\r
+{\r
+ int i;\r
+\r
+ VALIDATE( (Gpt_Global.initRun == STD_ON), GPT_SETMODE_SERVIVCE_ID, GPT_E_UNINIT );\r
+ VALIDATE( ( mode <= GPT_MODE_SLEEP ), GPT_SETMODE_SERVIVCE_ID, GPT_E_PARAM_MODE );\r
+\r
+ if (mode == GPT_MODE_NORMAL)\r
+ {\r
+ PIT.CTRL.B.MDIS = 0;\r
+ // Do NOT restart channels\r
+ }\r
+ else if (mode == GPT_MODE_SLEEP)\r
+ {\r
+\r
+ PIT.CTRL.B.MDIS = 1;\r
+ // Disable all but RTI\r
+ for (i= 0; i <= GPT_CHANNEL_PIT_8; i++)\r
+ {\r
+ Gpt_StopTimer(i);\r
+ }\r
+ }\r
+}\r
+\r
+void Gpt_DisableWakeup(Gpt_ChannelType channel)\r
+{\r
+ VALIDATE( (Gpt_Global.initRun == STD_ON), GPT_DISABLEWAKEUP_SERVICE_ID, GPT_E_UNINIT );\r
+ VALIDATE( VALID_CHANNEL(channel), GPT_DISABLEWAKEUP_SERVICE_ID, GPT_E_PARAM_CHANNEL );\r
+ // Only RTI have system wakeup\r
+ if (channel == GPT_CHANNEL_RTI)\r
+ {\r
+ Gpt_Global.wakeupEnabled = STD_OFF;\r
+ }\r
+ else\r
+ {\r
+ // TODO:\r
+ //assert(0);\r
+ }\r
+}\r
+\r
+void Gpt_EnableWakeup(Gpt_ChannelType channel)\r
+{\r
+ VALIDATE( (Gpt_Global.initRun == STD_ON), GPT_ENABLEWAKEUP_SERVICE_ID, GPT_E_UNINIT );\r
+ VALIDATE( VALID_CHANNEL(channel),GPT_ENABLEWAKEUP_SERVICE_ID, GPT_E_PARAM_CHANNEL );\r
+ if (channel == GPT_CHANNEL_RTI)\r
+ {\r
+ Gpt_Global.wakeupEnabled = STD_ON;\r
+ }\r
+ else\r
+ {\r
+ // TODO:\r
+ //assert(0);\r
+ }\r
+}\r
+\r
+void Gpt_Cbk_CheckWakeup(EcuM_WakeupSourceType wakeupSource)\r
+{\r
+\r
+}\r
+\r
+#endif\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include "Lin.h"\r
+#include "LinIf_Cbk.h"\r
+#include "mpc55xx.h"\r
+#include "Det.h"\r
+#include "Mcu.h"\r
+#include <stdlib.h>\r
+#include <string.h>\r
+#include "LinIf_Cbk.h"\r
+\r
+#define ESCI(exp) (volatile struct ESCI_tag *)(0xFFFA0000 + (0x4000 * exp))\r
+\r
+// LIN145: Reset -> LIN_UNINIT: After reset, the Lin module shall set its state to LIN_UNINIT.\r
+static Lin_DriverStatusType LinDriverStatus = LIN_UNINIT;\r
+\r
+static Lin_StatusType LinChannelStatus[LIN_CONTROLLER_CNT];\r
+static Lin_StatusType LinChannelOrderedStatus[LIN_CONTROLLER_CNT];\r
+\r
+static uint8* TxPtr[LIN_CONTROLLER_CNT];\r
+static uint8* TxCurrPtr[LIN_CONTROLLER_CNT];\r
+static uint8 TxSize[LIN_CONTROLLER_CNT];\r
+static uint8* RxPtr[LIN_CONTROLLER_CNT];\r
+static uint8* RxCurrPtr[LIN_CONTROLLER_CNT];\r
+static uint8 RxSize[LIN_CONTROLLER_CNT];\r
+\r
+/* Development error macros. */\r
+#if ( LIN_DEV_ERROR_DETECT == STD_ON )\r
+#define VALIDATE(_exp,_api,_err ) \\r
+ if( !(_exp) ) { \\r
+ Det_ReportError(MODULE_ID_LIN,0,_api,_err); \\r
+ return; \\r
+ }\r
+\r
+#define VALIDATE_W_RV(_exp,_api,_err,_rv ) \\r
+ if( !(_exp) ) { \\r
+ Det_ReportError(MODULE_ID_LIN,0,_api,_err); \\r
+ return (_rv); \\r
+ }\r
+#else\r
+#define VALIDATE(_exp,_api,_err )\r
+#define VALIDATE_W_RV(_exp,_api,_err,_rv )\r
+#endif\r
+\r
+typedef volatile union\r
+{\r
+ uint32_t R;\r
+ struct {\r
+ uint32_t PID:8;\r
+ uint32_t :24;\r
+ } B1;\r
+ struct {\r
+ uint32_t L:8;\r
+ uint32_t :24;\r
+ } B2;\r
+ struct {\r
+ uint32_t HDCHK:1;\r
+ uint32_t CSUM:1;\r
+ uint32_t CRC:1;\r
+ uint32_t TX:1;\r
+ uint32_t TN:1;\r
+ uint32_t :24;\r
+ } B3;\r
+ struct {\r
+ uint32_t T:8;\r
+ uint32_t :24;\r
+ } B4;\r
+ struct {\r
+ uint32_t D:8;\r
+ uint32_t :24;\r
+ } B5;\r
+}LinLTRType;\r
+\r
+typedef volatile union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TDRE:1;\r
+ vuint32_t TC:1;\r
+ vuint32_t RDRF:1;\r
+ vuint32_t IDLE:1;\r
+ vuint32_t OR:1;\r
+ vuint32_t NF:1;\r
+ vuint32_t FE:1;\r
+ vuint32_t PF:1;\r
+ vuint32_t:3;\r
+ vuint32_t BERR:1;\r
+ vuint32_t:3;\r
+ vuint32_t RAF:1;\r
+ vuint32_t RXRDY:1;\r
+ vuint32_t TXRDY:1;\r
+ vuint32_t LWAKE:1;\r
+ vuint32_t STO:1;\r
+ vuint32_t PBERR:1;\r
+ vuint32_t CERR:1;\r
+ vuint32_t CKERR:1;\r
+ vuint32_t FRC:1;\r
+ vuint32_t:7;\r
+ vuint32_t OVFL:1;\r
+ } B;\r
+} LinSRtype; /* Status Register */\r
+\r
+\r
+void LinInterrupt(uint8 Channel)\r
+{\r
+ volatile struct ESCI_tag * esciHw = ESCI(Channel);\r
+ LinSRtype sr, tmp;\r
+ LinLTRType tmpLtr;\r
+\r
+ sr.R = esciHw->SR.R;\r
+\r
+ // Clear flags\r
+ tmp.R = 0;\r
+ if(sr.B.TXRDY == 1)\r
+ {\r
+ tmp.B.TXRDY = 1;\r
+ }\r
+ if(sr.B.RXRDY == 1)\r
+ {\r
+ tmp.B.RXRDY = 1;\r
+ }\r
+ if(sr.B.TC == 1)\r
+ {\r
+ tmp.B.TC = 1;\r
+ }\r
+ if(sr.B.RDRF == 1)\r
+ {\r
+ tmp.B.RDRF = 1;\r
+ }\r
+ if(sr.B.IDLE == 1)\r
+ {\r
+ tmp.B.IDLE = 1;\r
+ }\r
+ if(sr.B.OVFL == 1)\r
+ {\r
+ tmp.B.OVFL = 1;\r
+ }\r
+ if(sr.B.FRC == 1)\r
+ {\r
+ tmp.B.FRC = 1;\r
+ }\r
+ esciHw->SR.R = tmp.R;\r
+ esciHw->LCR.B.TXIE = 0; // Always disable Tx Interrupt\r
+\r
+ // TX\r
+ if (LinChannelStatus[Channel]==LIN_TX_BUSY) {\r
+ // Maybe transmit next byte\r
+ if (TxSize[Channel] > 0 && sr.B.TXRDY) {\r
+ tmpLtr.R = 0; // Clear\r
+ tmpLtr.B4.T = *TxCurrPtr[Channel];\r
+ TxCurrPtr[Channel]++; TxSize[Channel]--;\r
+ esciHw->LCR.B.TXIE = 1; // Enable tx irq\r
+ esciHw->LTR.R=tmpLtr.R; // write to transmit reg\r
+ }\r
+ else {\r
+ if(sr.B.FRC == 1){\r
+ //Transmission complete\r
+ if (LinChannelOrderedStatus[Channel]==LIN_CH_SLEEP){\r
+ LinChannelStatus[Channel] = LIN_CH_SLEEP;\r
+ LinChannelOrderedStatus[Channel]=LIN_CH_OPERATIONAL;\r
+ }else {\r
+ LinChannelStatus[Channel] = LIN_TX_OK;\r
+ }\r
+ esciHw->LCR.B.TXIE = 0; // Disable tx irq\r
+ }\r
+ else{\r
+ if (LinChannelOrderedStatus[Channel]==LIN_CH_SLEEP){\r
+ LinChannelStatus[Channel] = LIN_CH_SLEEP;\r
+ LinChannelOrderedStatus[Channel]=LIN_CH_OPERATIONAL;\r
+ }else {\r
+ LinChannelStatus[Channel] = LIN_TX_ERROR;\r
+ }\r
+ }\r
+ }\r
+ } //RX\r
+ else if (LinChannelStatus[Channel]==LIN_RX_BUSY) {\r
+ // Maybe receive next byte\r
+ if (RxSize[Channel] > 0 && sr.B.RXRDY) {\r
+ tmpLtr.R = esciHw->LRR.R;\r
+ *RxCurrPtr[Channel] = tmpLtr.B5.D;\r
+ RxCurrPtr[Channel]++; RxSize[Channel]--;\r
+ } else if (RxSize[Channel] == 0 && sr.B.FRC == 1){\r
+ //receive complete\r
+ LinChannelStatus[Channel] = LIN_RX_OK;\r
+ esciHw->LCR.B.RXIE = 0; // Disable Rx Interrupt\r
+ esciHw->LCR.B.FCIE = 0; // Disable Rx Interrupt\r
+ }\r
+ }\r
+\r
+ // Error handling\r
+ if(sr.B.OR || sr.B.NF || sr.B.FE || sr.B.PF || sr.B.BERR || sr.B.STO || sr.B.PBERR ||\r
+ sr.B.CERR || sr.B.CKERR || sr.B.OVFL) {\r
+ static uint32 errCnt=0;\r
+ errCnt++;\r
+ if(LinChannelStatus[Channel]==LIN_RX_BUSY){\r
+ LinChannelStatus[Channel] = LIN_RX_ERROR;\r
+ }else if (LinChannelStatus[Channel]==LIN_TX_BUSY){\r
+ LinChannelStatus[Channel] = LIN_TX_ERROR;\r
+ }\r
+\r
+ // Resynchronize driver and clear all errors\r
+ esciHw->LCR.B.LRES = 1; // LIN Resynchronize. First set then cleared\r
+ esciHw->LCR.B.LRES = 0; // LIN Resynchronize. First set then cleared\r
+ // Clear flags\r
+ esciHw->SR.R=0xffffffff;\r
+ }\r
+}\r
+\r
+static void LinInterruptA()\r
+{\r
+ LinInterrupt(LIN_CTRL_A);\r
+}\r
+static void LinInterruptB()\r
+{\r
+ LinInterrupt(LIN_CTRL_B);\r
+}\r
+static void LinInterruptC()\r
+{\r
+ LinInterrupt(LIN_CTRL_C);\r
+}\r
+static void LinInterruptD()\r
+{\r
+ LinInterrupt(LIN_CTRL_D);\r
+}\r
+static void LinInterruptE()\r
+{\r
+ LinInterrupt(LIN_CTRL_E);\r
+}\r
+static void LinInterruptF()\r
+{\r
+ LinInterrupt(LIN_CTRL_F);\r
+}\r
+static void LinInterruptG()\r
+{\r
+ LinInterrupt(LIN_CTRL_G);\r
+}\r
+static void LinInterruptH()\r
+{\r
+ LinInterrupt(LIN_CTRL_H);\r
+}\r
+\r
+static const void const * aIntFnc[] = {LinInterruptA,\r
+ LinInterruptB,\r
+ LinInterruptC,\r
+ LinInterruptD,\r
+ LinInterruptE,\r
+ LinInterruptF,\r
+ LinInterruptG,\r
+ LinInterruptH,};\r
+\r
+void Lin_Init( const Lin_ConfigType* Config )\r
+{\r
+ uint8 i;\r
+\r
+ VALIDATE( (LinDriverStatus == LIN_UNINIT), LIN_INIT_SERVICE_ID, LIN_E_STATE_TRANSITION );\r
+ //VALIDATE( (Config!=0), LIN_INIT_SERVICE_ID, LIN_E_INVALID_POINTER );\r
+\r
+ for (i=0;i<LIN_CONTROLLER_CNT;i++)\r
+ {\r
+ // LIN171: On entering the state LIN_INIT, the Lin module shall set each channel into\r
+ // state LIN_CH_UNINIT.\r
+ LinChannelStatus[i] = LIN_CH_UNINIT;\r
+ LinChannelOrderedStatus[i]=LIN_CH_OPERATIONAL;\r
+ TxPtr[i] = 0;\r
+ TxCurrPtr[i] = 0;\r
+ TxSize[i] = 0;\r
+ RxPtr[i] = 0;\r
+ RxCurrPtr[i] = 0;\r
+ RxSize[i] = 0;\r
+ }\r
+\r
+ //LIN146: LIN_UNINIT -> LIN_INIT: The Lin module shall transition from LIN_UNINIT\r
+ // to LIN_INIT when the function Lin_Init is called.\r
+ LinDriverStatus = LIN_INIT;\r
+}\r
+void Lin_DeInit()\r
+{\r
+ uint8 i;\r
+\r
+ // Make sure all allocated buffers are freed\r
+ for (i=0;i<LIN_CONTROLLER_CNT;i++)\r
+ {\r
+ if (RxPtr[i] != 0) {\r
+ free(RxPtr[i]);\r
+ }\r
+ if (TxPtr[i] != 0) {\r
+ free(TxPtr[i]);\r
+ }\r
+ }\r
+ LinDriverStatus = LIN_UNINIT;\r
+}\r
+\r
+void Lin_WakeupValidation( void )\r
+{\r
+\r
+}\r
+\r
+void Lin_InitChannel( uint8 Channel, const Lin_ChannelConfigType* Config )\r
+{\r
+ volatile struct ESCI_tag * esciHw = ESCI(Channel);\r
+ enum\r
+ {\r
+ LIN_PRIO = 3\r
+ };\r
+\r
+ VALIDATE( (Config!=0), LIN_INIT_CHANNEL_SERVICE_ID, LIN_E_INVALID_POINTER );\r
+ VALIDATE( (LinDriverStatus != LIN_UNINIT), LIN_INIT_CHANNEL_SERVICE_ID, LIN_E_UNINIT );\r
+ VALIDATE( (Channel < LIN_CONTROLLER_CNT), LIN_INIT_CHANNEL_SERVICE_ID, LIN_E_INVALID_CHANNEL );\r
+\r
+ // Install the interrupt\r
+ if (Channel > 3)\r
+ {\r
+ IntCtrl_InstallVector(aIntFnc[Channel],SCI_E_COMB + Channel,LIN_PRIO,CPU_Z1);\r
+ }\r
+ else\r
+ {\r
+ IntCtrl_InstallVector(aIntFnc[Channel],SCI_A_COMB + Channel,LIN_PRIO,CPU_Z1);\r
+ }\r
+\r
+ esciHw->CR2.B.MDIS = 0;/* The module is enabled by writing the ESCIx_CR2[MDIS] bit to 0. */\r
+\r
+ esciHw->CR1.B.RE = 1;\r
+ esciHw->CR1.B.M = 0; /* The data format bit ESCIx_CR1[M], is set to 0 (8 data bits), and the parity is disabled (PE = 0).*/\r
+ esciHw->CR1.B.PE = 0;\r
+ esciHw->CR1.B.TIE = 0; /*ESCIx_CR1[TIE], ESCIx_CR1[TCIE], ESCIx_CR1[RIE] interrupt enable bits should be inactive.*/\r
+ esciHw->CR1.B.TCIE = 0;\r
+ esciHw->CR1.B.RIE = 0;\r
+ /* Set up ESCIx_CR1 for LIN */\r
+ /*\r
+ * SCI Baud Rate. Used by the counter to determine the baud rate of the eSCI.\r
+ * The formula for calculating the baud rate is:\r
+ *\r
+ * eSCI system clock\r
+ * SCI baud rate = -----------------------\r
+ * 16 × SBR\r
+ *\r
+ * where SBR can contain a value from 1 to 8191. After reset, the baud generator\r
+ * is disabled until the TE bit or the RE bit is set for the first time. The baud\r
+ * rate generator is disabled when SBR = 0x0.\r
+ */\r
+ esciHw->CR1.B.SBR = McuE_GetPeripheralClock(Config->LinClockRef)/(16*Config->LinChannelBaudRate);\r
+ esciHw->LCR.B.LIN = 1; /* Instead, the LIN interrupts should be used.Switch eSCI to LIN mode (ESCIx_LCR[LIN] = 1).*/\r
+\r
+ esciHw->CR2.B.BRK13 = 1;/* The LIN standard requires that the break character always be 13 bits long\r
+ (ESCIx_CR2[BRK13] = 1). The eSCI will work with BRK13=0, but it will violate LIN 2.0. */\r
+\r
+ esciHw->LCR.B.LDBG = 0;/*Normally, bit errors should cause the LIN FSM to reset, stop driving the bus immediately, and stop\r
+ further DMA requests until the BERR flag has been cleared. Set ESCIx_LCR[LDBG] = 0,*/\r
+ esciHw->LCR.B.STIE = 1; // Enable some fault irq's\r
+ esciHw->LCR.B.PBIE = 1;\r
+ esciHw->LCR.B.CKIE = 1;\r
+ esciHw->LCR.B.OFIE = 1;\r
+\r
+ esciHw->CR2.B.SBSTP = 1;/*ESCIx_CR2[SBSTP] = 1, and ESCIx_CR2[BSTP] = 1 to accomplish these functions.*/\r
+ esciHw->CR2.B.BSTP = 1;\r
+\r
+ esciHw->CR2.B.FBR = 1; // Fast bit error detection provides superior error checking, so ESCIx_CR2[FBR] should be set;\r
+ esciHw->CR2.B.BESM13 = 1; // normally it will be used with ESCIx_CR2[BESM13] = 1.*/\r
+\r
+ /* The error indicators NF, FE, BERR, STO, PBERR, CERR, CKERR, and OVFL should be enabled. */\r
+ /* TODO Should we have these interrupts or check the status register? */\r
+ /*Initially a wakeup character may need to be transmitted on the LIN bus, so that the LIN slaves\r
+ activate.*/\r
+\r
+ esciHw->CR1.B.TE = 1; /* Both transmitter and receiver are enabled (ESCIx_CR1[TE] = 1, ESCIx_CR1[RE] = 1). */\r
+\r
+ LinChannelStatus[Channel]=LIN_CH_OPERATIONAL;\r
+}\r
+\r
+void Lin_DeInitChannel( uint8 Channel )\r
+{\r
+ volatile struct ESCI_tag * esciHw = ESCI(Channel);\r
+ VALIDATE( (Channel < LIN_CONTROLLER_CNT), LIN_DEINIT_CHANNEL_SERVICE_ID, LIN_E_INVALID_CHANNEL );\r
+\r
+ //LIN178: The function Lin_DeInitChannel shall only be executable when the LIN\r
+ //channel state-machine is in state LIN_CH_OPERATIONAL.\r
+ if(LinChannelStatus[Channel] != LIN_CH_UNINIT){\r
+ esciHw->CR2.B.MDIS = 1;/* The module is disabled by writing the ESCIx_CR2[MDIS] bit to 1. */\r
+\r
+ if (RxPtr[Channel] != 0) {\r
+ free(RxPtr[Channel]);\r
+ }\r
+ if (TxPtr[Channel] != 0) {\r
+ free(TxPtr[Channel]);\r
+ }\r
+\r
+ LinChannelStatus[Channel]=LIN_CH_UNINIT;\r
+ }\r
+}\r
+\r
+Std_ReturnType Lin_SendHeader( uint8 Channel, Lin_PduType* PduInfoPtr )\r
+{\r
+ LinSRtype tmp;\r
+ LinLTRType tmpLtr;\r
+ volatile struct ESCI_tag * esciHw = ESCI(Channel);\r
+\r
+ // LIN021\r
+ imask_t state = McuE_EnterCriticalSection();\r
+ if(LinChannelStatus[Channel] == LIN_TX_BUSY || LinChannelStatus[Channel] == LIN_TX_ERROR ||\r
+ LinChannelStatus[Channel] == LIN_RX_BUSY || LinChannelStatus[Channel] == LIN_RX_ERROR){\r
+ LinChannelStatus[Channel]=LIN_CH_OPERATIONAL;\r
+ esciHw->LCR.B.LRES = 1; // LIN Resynchronize. First set then cleared\r
+ esciHw->LCR.B.LRES = 0; // LIN Resynchronize. First set then cleared\r
+ esciHw->LCR.B.TXIE = 0; // Disable tx irq\r
+ esciHw->LCR.B.RXIE = 0; // Disable Rx Interrupt\r
+ esciHw->LCR.B.FCIE = 0; // Disable Rx Interrupt\r
+ // Clear flags\r
+ esciHw->SR.R=0xffffffff;\r
+ }\r
+ McuE_ExitCriticalSection(state);\r
+\r
+\r
+ VALIDATE_W_RV( (LinDriverStatus != LIN_UNINIT), LIN_SEND_HEADER_SERVICE_ID, LIN_E_UNINIT, E_NOT_OK);\r
+ VALIDATE_W_RV( (LinChannelStatus[Channel] != LIN_CH_UNINIT), LIN_SEND_HEADER_SERVICE_ID, LIN_E_CHANNEL_UNINIT, E_NOT_OK);\r
+ VALIDATE_W_RV( (Channel < LIN_CONTROLLER_CNT), LIN_SEND_HEADER_SERVICE_ID, LIN_E_INVALID_CHANNEL, E_NOT_OK);\r
+ //Send header is used to wake the net in this implementation(no actual header is sent\r
+ // VALIDATE_W_RV( (LinChannelStatus[Channel] != LIN_CH_SLEEP), LIN_SEND_HEADER_SERVICE_ID, LIN_E_STATE_TRANSITION, E_NOT_OK);\r
+ VALIDATE_W_RV( (PduInfoPtr != NULL), LIN_SEND_HEADER_SERVICE_ID, LIN_E_INVALID_POINTER, E_NOT_OK);\r
+\r
+ // Byte 1\r
+ tmpLtr.R = 0; // Clear\r
+ tmpLtr.B1.PID = PduInfoPtr->Pid;\r
+ tmp.R = 0; // Clear ready flag before send\r
+ tmp.B.TXRDY = 1;\r
+ esciHw->SR.R = tmp.R;\r
+ esciHw->LTR.R=tmpLtr.R; // write to transmit reg\r
+\r
+ // Byte 2\r
+ tmpLtr.R = 0; // Clear\r
+ tmpLtr.B2.L = PduInfoPtr->DI;\r
+ tmp.R = 0; // Clear ready flag before send\r
+ tmp.B.TXRDY = 1;\r
+ esciHw->SR.R = tmp.R;\r
+ esciHw->LTR.R=tmpLtr.R; // write to transmit reg\r
+\r
+ // Byte 3\r
+ tmpLtr.R = 0; // Clear\r
+ if (PduInfoPtr->Cs == LIN_ENHANCED_CS){ //Frame identifiers 60 (0x3C) to 61 (0x3D) shall always use classic checksum\r
+ tmpLtr.B3.HDCHK = 1;\r
+ }\r
+ tmpLtr.B3.CSUM = 1; // Append checksum to TX frame or verify for a RX\r
+ tmpLtr.B3.CRC = 0; // Append two CRC bytes(Not LIN standard)\r
+ if (PduInfoPtr->Drc == LIN_MASTER_RESPONSE)\r
+ {\r
+ LinChannelStatus[Channel]=LIN_TX_BUSY;\r
+ tmpLtr.B3.TX = 1; // TX frame\r
+ tmpLtr.B3.TN = 0; // Timeout not valid for TX\r
+ tmp.R = 0; // Clear ready flag before send\r
+ tmp.B.TXRDY = 1;\r
+ esciHw->SR.R = tmp.R;\r
+ esciHw->LCR.B.FCIE = 1; // // Enable frame complete\r
+ esciHw->LCR.B.TXIE = 1; // Enable tx irq\r
+ if (PduInfoPtr->DI > 0){\r
+ if (TxPtr[Channel] != 0) {\r
+ free(TxPtr[Channel]);\r
+ }\r
+ TxCurrPtr[Channel] = TxPtr[Channel] = (uint8 *)malloc(PduInfoPtr->DI);\r
+ TxSize[Channel] = PduInfoPtr->DI;\r
+ memcpy(TxPtr[Channel],PduInfoPtr->SduPtr,PduInfoPtr->DI);\r
+ }\r
+ esciHw->LTR.R=tmpLtr.R; // write to transmit reg\r
+ }\r
+\r
+\r
+ else\r
+ {\r
+ LinChannelStatus[Channel]=LIN_RX_BUSY;\r
+ if (RxPtr[Channel] != 0) {\r
+ free(RxPtr[Channel]);\r
+ }\r
+ RxCurrPtr[Channel] = RxPtr[Channel] = (uint8 *)malloc(PduInfoPtr->DI);\r
+ RxSize[Channel] = PduInfoPtr->DI;\r
+\r
+ tmpLtr.B3.TX = 0; // RX frame\r
+ tmpLtr.B3.TN = (10*PduInfoPtr->DI + 45)*1.4; // Timeout. (10 × NDATA + 45) × 1.4 according to LIN1.3\r
+ esciHw->LTR.R=tmpLtr.R; // write to transmit reg\r
+ // Byte 4 for RX\r
+ tmpLtr.R = 0; // Clear\r
+ tmpLtr.B4.T = (10*PduInfoPtr->DI + 45)*1.4; // Timeout. (10 × NDATA + 45) × 1.4 according to LIN1.3\r
+ tmp.R = 0; // Clear ready flag before send\r
+ tmp.B.TXRDY = 1;\r
+ esciHw->SR.R = tmp.R;\r
+ esciHw->LTR.R=tmpLtr.R; // write to transmit reg\r
+ esciHw->LCR.B.FCIE = 1; // Enable frame complete\r
+ esciHw->LCR.B.RXIE = 1; // Enable rx irq\r
+ }\r
+\r
+ return E_OK;\r
+}\r
+\r
+Std_ReturnType Lin_SendResponse( uint8 Channel, Lin_PduType* PduInfoPtr )\r
+{\r
+ VALIDATE_W_RV( (LinDriverStatus != LIN_UNINIT), LIN_SEND_RESPONSE_SERVICE_ID, LIN_E_UNINIT, E_NOT_OK);\r
+ VALIDATE_W_RV( (LinChannelStatus[Channel] != LIN_CH_UNINIT), LIN_SEND_RESPONSE_SERVICE_ID, LIN_E_CHANNEL_UNINIT, E_NOT_OK);\r
+ VALIDATE_W_RV( (Channel < LIN_CONTROLLER_CNT), LIN_SEND_RESPONSE_SERVICE_ID, LIN_E_INVALID_CHANNEL, E_NOT_OK);\r
+ VALIDATE_W_RV( (LinChannelStatus[Channel] != LIN_CH_SLEEP), LIN_SEND_RESPONSE_SERVICE_ID, LIN_E_STATE_TRANSITION, E_NOT_OK);\r
+ VALIDATE_W_RV( (PduInfoPtr != NULL), LIN_SEND_RESPONSE_SERVICE_ID, LIN_E_INVALID_POINTER, E_NOT_OK);\r
+\r
+ // The response is sent from within the header in this implementation since this is a master only implementation\r
+ return E_OK;\r
+}\r
+\r
+Std_ReturnType Lin_GoToSleep( uint8 Channel )\r
+{\r
+ volatile struct ESCI_tag * esciHw = ESCI(Channel);\r
+ Lin_PduType PduInfo;\r
+ uint8 data[8] = {0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF};\r
+\r
+ VALIDATE_W_RV( (LinDriverStatus != LIN_UNINIT), LIN_GO_TO_SLEEP_SERVICE_ID, LIN_E_UNINIT, E_NOT_OK);\r
+ VALIDATE_W_RV( (LinChannelStatus[Channel] != LIN_CH_UNINIT), LIN_GO_TO_SLEEP_SERVICE_ID, LIN_E_CHANNEL_UNINIT, E_NOT_OK);\r
+ VALIDATE_W_RV( (Channel < LIN_CONTROLLER_CNT), LIN_GO_TO_SLEEP_SERVICE_ID, LIN_E_INVALID_CHANNEL, E_NOT_OK);\r
+ VALIDATE_W_RV( (LinChannelStatus[Channel] != LIN_CH_SLEEP), LIN_GO_TO_SLEEP_SERVICE_ID, LIN_E_STATE_TRANSITION, E_NOT_OK);\r
+\r
+ if (LinChannelOrderedStatus[Channel]!=LIN_CH_SLEEP){\r
+ LinChannelOrderedStatus[Channel]=LIN_CH_SLEEP;\r
+\r
+ PduInfo.Cs = LIN_CLASSIC_CS;\r
+ PduInfo.Pid = 0x3C;\r
+ PduInfo.SduPtr = data;\r
+ PduInfo.DI = 8;\r
+ PduInfo.Drc = LIN_MASTER_RESPONSE;\r
+\r
+ Lin_SendHeader(Channel, &PduInfo);\r
+ Lin_SendResponse(Channel, &PduInfo);\r
+\r
+ esciHw->LCR.B.WUIE = 1; // enable wake-up irq\r
+ }\r
+ return E_OK;\r
+}\r
+\r
+Std_ReturnType Lin_GoToSleepInternal( uint8 Channel )\r
+{\r
+ VALIDATE_W_RV( (LinDriverStatus != LIN_UNINIT), LIN_GO_TO_SLEEP_INTERNAL_SERVICE_ID, LIN_E_UNINIT, E_NOT_OK);\r
+ VALIDATE_W_RV( (LinChannelStatus[Channel] != LIN_CH_UNINIT), LIN_GO_TO_SLEEP_INTERNAL_SERVICE_ID, LIN_E_CHANNEL_UNINIT, E_NOT_OK);\r
+ VALIDATE_W_RV( (Channel < LIN_CONTROLLER_CNT), LIN_GO_TO_SLEEP_INTERNAL_SERVICE_ID, LIN_E_INVALID_CHANNEL, E_NOT_OK);\r
+ VALIDATE_W_RV( (LinChannelStatus[Channel] != LIN_CH_SLEEP), LIN_GO_TO_SLEEP_INTERNAL_SERVICE_ID, LIN_E_STATE_TRANSITION, E_NOT_OK);\r
+ Lin_GoToSleep(Channel);\r
+ return E_OK;\r
+}\r
+\r
+Std_ReturnType Lin_WakeUp( uint8 Channel )\r
+{\r
+ volatile struct ESCI_tag * esciHw = ESCI(Channel);\r
+ Lin_PduType PduInfo;\r
+ uint8 data[2] = {0xFF,0xFF};\r
+\r
+ VALIDATE_W_RV( (LinDriverStatus != LIN_UNINIT), LIN_WAKE_UP_SERVICE_ID, LIN_E_UNINIT, E_NOT_OK);\r
+ VALIDATE_W_RV( (LinChannelStatus[Channel] != LIN_CH_UNINIT), LIN_WAKE_UP_SERVICE_ID, LIN_E_CHANNEL_UNINIT, E_NOT_OK);\r
+ VALIDATE_W_RV( (Channel < LIN_CONTROLLER_CNT), LIN_WAKE_UP_SERVICE_ID, LIN_E_INVALID_CHANNEL, E_NOT_OK);\r
+ VALIDATE_W_RV( (LinChannelStatus[Channel] == LIN_CH_SLEEP), LIN_WAKE_UP_SERVICE_ID, LIN_E_STATE_TRANSITION, E_NOT_OK);\r
+\r
+ esciHw->LCR.B.WUIE = 0; // disable wake-up irq\r
+ esciHw->LCR.B.WU = 1; // send wake up\r
+ esciHw->LCR.B.WUD0 = 1; // delimiter time\r
+ esciHw->LCR.B.WUD1 = 0; // delimiter time\r
+\r
+ // Just send any header to trigger the wakeup signal\r
+ PduInfo.Cs = LIN_CLASSIC_CS;\r
+ PduInfo.Pid = 0x00;\r
+ PduInfo.SduPtr = data;\r
+ PduInfo.DI = 2;\r
+ PduInfo.Drc = LIN_SLAVE_RESPONSE;\r
+ Lin_SendHeader(Channel, &PduInfo);\r
+\r
+ LinChannelStatus[Channel]=LIN_CH_OPERATIONAL;\r
+ return E_OK;\r
+}\r
+\r
+Lin_StatusType Lin_GetStatus( uint8 Channel, uint8** Lin_SduPtr )\r
+{\r
+ VALIDATE_W_RV( (LinDriverStatus != LIN_UNINIT), LIN_GETSTATUS_SERVICE_ID, LIN_E_UNINIT, E_NOT_OK);\r
+ VALIDATE_W_RV( (LinChannelStatus[Channel] != LIN_CH_UNINIT), LIN_GETSTATUS_SERVICE_ID, LIN_E_CHANNEL_UNINIT, E_NOT_OK);\r
+ VALIDATE_W_RV( (Channel < LIN_CONTROLLER_CNT), LIN_GETSTATUS_SERVICE_ID, LIN_E_INVALID_CHANNEL, E_NOT_OK);\r
+ VALIDATE_W_RV( (Lin_SduPtr!=NULL), LIN_GETSTATUS_SERVICE_ID, LIN_E_INVALID_POINTER, E_NOT_OK);\r
+\r
+ imask_t state = McuE_EnterCriticalSection();\r
+ Lin_StatusType res = LinChannelStatus[Channel];\r
+ // We can only check for valid sdu ptr when LIN_RX_OK\r
+ if(LinChannelStatus[Channel] == LIN_RX_OK || LinChannelStatus[Channel] == LIN_RX_ERROR){\r
+ *Lin_SduPtr = RxPtr[Channel];\r
+ LinChannelStatus[Channel]=LIN_CH_OPERATIONAL;\r
+ } else if(LinChannelStatus[Channel] == LIN_TX_OK || LinChannelStatus[Channel] == LIN_TX_ERROR){\r
+ LinChannelStatus[Channel]=LIN_CH_OPERATIONAL;\r
+ }\r
+ McuE_ExitCriticalSection(state);\r
+ return res;\r
+}\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include <assert.h>\r
+#include <string.h>\r
+#include "Std_Types.h"\r
+#include "Mcu.h"\r
+#include "Det.h"\r
+#include "mpc55xx.h"\r
+#include "Cpu.h"\r
+#include "Ramlog.h"\r
+#include "Os.h"\r
+#include "int_ctrl.h"\r
+\r
+//#define USE_TRACE 1\r
+//#define USE_DEBUG 1\r
+#include "Trace.h"\r
+\r
+#define SYSCLOCK_SELECT_PLL 0x2\r
+\r
+#if defined(CFG_MPC5567)\r
+#define CALC_SYSTEM_CLOCK(_extal,_emfd,_eprediv,_erfd) \\r
+ ( (_extal) * ((_emfd)+4) / (((_eprediv)+1)*(1<<(_erfd))) )\r
+#else\r
+#define CALC_SYSTEM_CLOCK(_extal,_emfd,_eprediv,_erfd) \\r
+ ( (_extal) * ((_emfd)+16) / (((_eprediv)+1)*((_erfd)+1)) )\r
+#endif\r
+\r
+typedef void (*vfunc_t)();\r
+\r
+/* Function declarations. */\r
+static void Mcu_ConfigureFlash(void);\r
+\r
+\r
+typedef struct {\r
+ uint32 lossOfLockCnt;\r
+ uint32 lossOfClockCnt;\r
+} Mcu_Stats;\r
+\r
+/**\r
+ * Type that holds all global data for Mcu\r
+ */\r
+typedef struct\r
+{\r
+ // Set if Mcu_Init() have been called\r
+ boolean initRun;\r
+\r
+ // Our config\r
+ const Mcu_ConfigType *config;\r
+\r
+ Mcu_ClockType clockSetting;\r
+\r
+ Mcu_Stats stats;\r
+\r
+} Mcu_GlobalType;\r
+\r
+/* Development error macros. */\r
+#if ( MCU_DEV_ERROR_DETECT == STD_ON )\r
+#define VALIDATE(_exp,_api,_err ) \\r
+ if( !(_exp) ) { \\r
+ Det_ReportError(MODULE_ID_MCU,0,_api,_err); \\r
+ return; \\r
+ }\r
+\r
+#define VALIDATE_W_RV(_exp,_api,_err,_rv ) \\r
+ if( !(_exp) ) { \\r
+ Det_ReportError(MODULE_ID_MCU,0,_api,_err); \\r
+ return (_rv); \\r
+ }\r
+#else\r
+#define VALIDATE(_exp,_api,_err )\r
+#define VALIDATE_W_RV(_exp,_api,_err,_rv )\r
+#endif\r
+\r
+// Global config\r
+Mcu_GlobalType Mcu_Global =\r
+{\r
+ .initRun = 0,\r
+ .config = &McuConfigData[0],\r
+};\r
+\r
+//-------------------------------------------------------------------\r
+\r
+static void Mcu_LossOfLock( void ) {\r
+#if ( MCU_DEV_ERROR_DETECT == STD_ON )\r
+ /* Should report MCU_E_CLOCK_FAILURE with DEM here.... but\r
+ * we do the next best thing. Report with Det with API = 0\r
+ */\r
+ Det_ReportError(MODULE_ID_MCU,0,0,MCU_E_PLL_NOT_LOCKED);\r
+#endif\r
+\r
+ Mcu_Global.stats.lossOfLockCnt++;\r
+ // Clear interrupt\r
+ FMPLL.SYNSR.B.LOLF = 1;\r
+\r
+}\r
+\r
+//-------------------------------------------------------------------\r
+static void Mcu_LossOfCLock( void ) {\r
+\r
+ /* Should report MCU_E_CLOCK_FAILURE with DEM here */\r
+\r
+ Mcu_Global.stats.lossOfClockCnt++;\r
+ // Clear interrupt\r
+ FMPLL.SYNSR.B.LOCF = 1;\r
+}\r
+\r
+\r
+#define SPR_PIR 286\r
+#define SPR_PVR 287\r
+\r
+#define CORE_PVR_E200Z1 0x81440000UL\r
+#define CORE_PVR_E200Z0 0x81710000UL\r
+#define CORE_PVR_E200Z6 0x81170000UL\r
+\r
+\r
+typedef struct {\r
+ char *name;\r
+ uint32 pvr;\r
+} core_info_t;\r
+\r
+typedef struct {\r
+ char *name;\r
+ uint32 pvr;\r
+} cpu_info_t;\r
+\r
+cpu_info_t cpu_info_list[] =\r
+{\r
+#if defined(CFG_MPC5516)\r
+ {\r
+ .name = "MPC5516",\r
+ .pvr = CORE_PVR_E200Z1,\r
+ },\r
+ {\r
+ .name = "MPC5516",\r
+ .pvr = CORE_PVR_E200Z0,\r
+ },\r
+#elif defined(CFG_MPC5567)\r
+ {\r
+ .name = "MPC5567",\r
+ .pvr = CORE_PVR_E200Z6,\r
+ }\r
+#endif\r
+};\r
+\r
+core_info_t core_info_list[] = {\r
+#if defined(CFG_MPC5516)\r
+ {\r
+ .name = "CORE_E200Z1",\r
+ .pvr = CORE_PVR_E200Z1,\r
+ },\r
+ {\r
+ .name = "CORE_E200Z1",\r
+ .pvr = CORE_PVR_E200Z1,\r
+ },\r
+#elif defined(CFG_MPC5567)\r
+ {\r
+ .name = "CORE_E200Z6",\r
+ .pvr = CORE_PVR_E200Z6,\r
+ }\r
+#endif\r
+};\r
+\r
+// TODO: move\r
+#if !defined(ARRAY_SIZE)\r
+#define ARRAY_SIZE(_x) (sizeof(_x)/sizeof((_x)[0]))\r
+#endif\r
+\r
+static cpu_info_t *Mcu_IdentifyCpu(uint32 pvr)\r
+{\r
+ int i;\r
+ for (i = 0; i < ARRAY_SIZE(cpu_info_list); i++) {\r
+ if (cpu_info_list[i].pvr == pvr) {\r
+ return &cpu_info_list[i];\r
+ }\r
+ }\r
+\r
+ return NULL;\r
+}\r
+\r
+static core_info_t *Mcu_IdentifyCore(uint32 pvr)\r
+{\r
+ int i;\r
+ for (i = 0; i < ARRAY_SIZE(core_info_list); i++) {\r
+ if (core_info_list[i].pvr == pvr) {\r
+ return &core_info_list[i];\r
+ }\r
+ }\r
+\r
+ return NULL;\r
+}\r
+\r
+\r
+static uint32 Mcu_CheckCpu( void ) {\r
+\r
+ uint32 pvr;\r
+ uint32 pir;\r
+ cpu_info_t *cpuType;\r
+ core_info_t *coreType;\r
+\r
+ // We have to registers to read here, PIR and PVR\r
+\r
+ pir = get_spr(SPR_PIR);\r
+ pvr = get_spr(SPR_PVR);\r
+\r
+ cpuType = Mcu_IdentifyCpu(pvr);\r
+ coreType = Mcu_IdentifyCore(pvr);\r
+\r
+ if( (cpuType == NULL) || (coreType == NULL) ) {\r
+ // Just hang\r
+ while(1);\r
+ }\r
+\r
+ //DEBUG(DEBUG_HIGH,"/drivers/mcu: Cpu: %s( 0x%08x )\n",cpuType->name,pvr);\r
+ //DEBUG(DEBUG_HIGH,"/drivers/mcu: Core: %s( 0x%08x )\n",coreType->name,pvr);\r
+\r
+ return 0;\r
+}\r
+\r
+\r
+//-------------------------------------------------------------------\r
+\r
+void Mcu_Init(const Mcu_ConfigType *configPtr)\r
+{\r
+ VALIDATE( ( NULL != configPtr ), MCU_INIT_SERVICE_ID, MCU_E_PARAM_CONFIG );\r
+\r
+ if( !SIMULATOR() ) {\r
+ Mcu_CheckCpu();\r
+ }\r
+\r
+ memset(&Mcu_Global.stats,0,sizeof(Mcu_Global.stats));\r
+\r
+\r
+ //\r
+ // Setup memories\r
+ //\r
+ Mcu_ConfigureFlash();\r
+\r
+ Irq_Enable();\r
+\r
+ Mcu_Global.config = configPtr;\r
+ Mcu_Global.initRun = 1;\r
+\r
+ if( Mcu_Global.config->McuClockSrcFailureNotification == TRUE ){\r
+ // Enable loss of lock interrupt\r
+\r
+ IntCtrl_AttachIsr1(Mcu_LossOfLock, NULL, PLL_SYNSR_LOLF,10 );\r
+#if defined(CFG_MPC5516)\r
+// FMPLL.SYNCR.B.LOCIRQ = 1; TODO: Kolla denna bortkommentering med MÃ¥rten.\r
+ FMPLL.ESYNCR2.B.LOLIRQ = 1;\r
+#elif defined(CFG_MPC5554) || defined(CFG_MPC5567)\r
+ FMPLL.SYNCR.B.LOLIRQ = 1;\r
+#endif\r
+ IntCtrl_AttachIsr1(Mcu_LossOfCLock, NULL, PLL_SYNSR_LOCF,10 );\r
+#if defined(CFG_MPC5516)\r
+// FMPLL.SYNCR.B.LOCIRQ = 1; TODO: Kolla denna bortkommentering med MÃ¥rten.\r
+ FMPLL.ESYNCR2.B.LOCIRQ = 1;\r
+#elif defined(CFG_MPC5554) || defined(CFG_MPC5567)\r
+ FMPLL.SYNCR.B.LOCIRQ = 1;\r
+#endif\r
+ }\r
+}\r
+//-------------------------------------------------------------------\r
+\r
+void Mcu_DeInit()\r
+{\r
+ Mcu_Global.initRun = FALSE; // Very simple Deinit. Should we do more?\r
+}\r
+\r
+//-------------------------------------------------------------------\r
+Std_ReturnType Mcu_InitRamSection(const Mcu_RamSectionType RamSection)\r
+{\r
+ VALIDATE_W_RV( ( 1 == Mcu_Global.initRun ), MCU_INITRAMSECTION_SERVICE_ID, MCU_E_UNINIT, E_NOT_OK );\r
+ VALIDATE_W_RV( ( RamSection <= Mcu_Global.config->McuRamSectors ), MCU_INITRAMSECTION_SERVICE_ID, MCU_E_PARAM_RAMSECTION, E_NOT_OK );\r
+\r
+ /* NOT SUPPORTED, reason: no support for external RAM */\r
+\r
+ return E_OK;\r
+}\r
+\r
+\r
+\r
+//-------------------------------------------------------------------\r
+\r
+Std_ReturnType Mcu_InitClock(const Mcu_ClockType ClockSetting)\r
+{\r
+ Mcu_ClockSettingConfigType *clockSettingsPtr;\r
+ VALIDATE_W_RV( ( 1 == Mcu_Global.initRun ), MCU_INITCLOCK_SERVICE_ID, MCU_E_UNINIT, E_NOT_OK );\r
+ VALIDATE_W_RV( ( ClockSetting < Mcu_Global.config->McuClockSettings ), MCU_INITCLOCK_SERVICE_ID, MCU_E_PARAM_CLOCK, E_NOT_OK );\r
+\r
+ Mcu_Global.clockSetting = ClockSetting;\r
+ clockSettingsPtr = &Mcu_Global.config->McuClockSettingConfig[Mcu_Global.clockSetting];\r
+\r
+\r
+ // TODO: find out if the 5554 really works like the 5516 here\r
+ // All three (16, 54, 67) used to run the same code here though, so i'm sticking it with 5516\r
+#if defined(CFG_MPC5516) || defined(CFG_MPC5554)\r
+ /* 5516clock info:\r
+ * Fsys - System frequency ( CPU + all periperals? )\r
+ *\r
+ * Fsys = EXTAL_FREQ *( (emfd+16) / ( (eprediv+1) * ( erfd+1 )) ) )\r
+ */\r
+ // Check ranges...\r
+ assert((clockSettingsPtr->PllEmfd>=32) && (clockSettingsPtr->PllEmfd<=132));\r
+ assert( (clockSettingsPtr->PllEprediv!=6) &&\r
+ (clockSettingsPtr->PllEprediv!=8) &&\r
+ (clockSettingsPtr->PllEprediv<10) );\r
+ assert( clockSettingsPtr->PllErfd & 1); // Must be odd\r
+#elif defined(CFG_MPC5567)\r
+ /* 5567 clock info:\r
+ * Fsys = EXTAL_FREQ *( (emfd+4) / ( (eprediv+1) * ( 2^erfd )) ) )\r
+ */\r
+ // Check ranges...\r
+ assert(clockSettingsPtr->PllEmfd < 16);\r
+ assert(clockSettingsPtr->PllEprediv <= 4);\r
+ assert(clockSettingsPtr->PllErfd < 8);\r
+#endif\r
+\r
+\r
+#if defined(USE_DEBUG)\r
+ {\r
+ uint32 extal = Mcu_Global.config->McuClockSettingConfig[Mcu_Global.clockSetting].McuClockReferencePoint;\r
+ uint32 f_sys;\r
+\r
+ f_sys = CALC_SYSTEM_CLOCK( extal,\r
+ clockSettingsPtr->PllEmfd,\r
+ clockSettingsPtr->PllEprediv,\r
+ clockSettingsPtr->PllErfd );\r
+\r
+ //DEBUG(DEBUG_HIGH,"/drivers/mcu: F_sys will be:%08d Hz\n",f_sys);\r
+ }\r
+#endif\r
+\r
+#if defined(CFG_MPC5516)\r
+ // External crystal PLL mode.\r
+ FMPLL.ESYNCR1.B.CLKCFG = 7; //TODO: Hur ställa detta för 5567?\r
+\r
+ // Write pll parameters.\r
+ FMPLL.ESYNCR1.B.EPREDIV = clockSettingsPtr->PllEprediv;\r
+ FMPLL.ESYNCR1.B.EMFD = clockSettingsPtr->PllEmfd;\r
+ FMPLL.ESYNCR2.B.ERFD = clockSettingsPtr->PllErfd;\r
+\r
+ // Connect SYSCLK to FMPLL\r
+ SIU.SYSCLK.B.SYSCLKSEL = SYSCLOCK_SELECT_PLL;\r
+#elif defined(CFG_MPC5554) || defined(CFG_MPC5567)\r
+ // Partially following the steps in MPC5567 RM..\r
+ FMPLL.SYNCR.B.DEPTH = 0;\r
+ FMPLL.SYNCR.B.LOLRE = 0;\r
+ FMPLL.SYNCR.B.LOLIRQ = 0;\r
+\r
+ FMPLL.SYNCR.B.PREDIV = clockSettingsPtr->PllEprediv;\r
+ FMPLL.SYNCR.B.MFD = clockSettingsPtr->PllEmfd;\r
+ FMPLL.SYNCR.B.RFD = clockSettingsPtr->PllErfd;\r
+\r
+ // Wait for PLL to sync.\r
+ while (Mcu_GetPllStatus() != MCU_PLL_LOCKED)\r
+ ;\r
+\r
+ FMPLL.SYNCR.B.LOLIRQ = 1;\r
+#endif\r
+\r
+ return E_OK;\r
+}\r
+\r
+//-------------------------------------------------------------------\r
+\r
+void Mcu_DistributePllClock(void)\r
+{\r
+ VALIDATE( ( 1 == Mcu_Global.initRun ), MCU_DISTRIBUTEPLLCLOCK_SERVICE_ID, MCU_E_UNINIT );\r
+ VALIDATE( ( FMPLL.SYNSR.B.LOCK == 1 ), MCU_DISTRIBUTEPLLCLOCK_SERVICE_ID, MCU_E_PLL_NOT_LOCKED );\r
+\r
+ /* NOT IMPLEMENTED due to pointless function on this hardware */\r
+\r
+}\r
+\r
+//-------------------------------------------------------------------\r
+\r
+Mcu_PllStatusType Mcu_GetPllStatus(void)\r
+{\r
+ VALIDATE_W_RV( ( 1 == Mcu_Global.initRun ), MCU_GETPLLSTATUS_SERVICE_ID, MCU_E_UNINIT, MCU_PLL_STATUS_UNDEFINED );\r
+ Mcu_PllStatusType rv;\r
+\r
+ if( !SIMULATOR() )\r
+ {\r
+ if ( !FMPLL.SYNSR.B.LOCK )\r
+ {\r
+ rv = MCU_PLL_UNLOCKED;\r
+ } else\r
+ {\r
+ rv = MCU_PLL_LOCKED;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* We are running on instruction set simulator. PLL is then always in sync... */\r
+ rv = MCU_PLL_LOCKED;\r
+ }\r
+\r
+ return rv;\r
+}\r
+\r
+//-------------------------------------------------------------------\r
+\r
+Mcu_ResetType Mcu_GetResetReason(void)\r
+{\r
+ Mcu_ResetType rv;\r
+\r
+ VALIDATE_W_RV( ( 1 == Mcu_Global.initRun ), MCU_GETRESETREASON_SERVICE_ID, MCU_E_UNINIT, MCU_RESET_UNDEFINED );\r
+\r
+ if( SIU.RSR.B.SSRS ) {\r
+ rv = MCU_SW_RESET;\r
+ } else if( SIU.RSR.B.WDRS ) {\r
+ rv = MCU_WATCHDOG_RESET;\r
+ } else if( SIU.RSR.B.PORS || SIU.RSR.B.ERS ) {\r
+ rv = MCU_POWER_ON_RESET;\r
+ } else {\r
+ rv = MCU_RESET_UNDEFINED;\r
+ }\r
+\r
+ return rv;\r
+}\r
+\r
+//-------------------------------------------------------------------\r
+\r
+Mcu_RawResetType Mcu_GetResetRawValue(void)\r
+{\r
+ VALIDATE_W_RV( ( 1 == Mcu_Global.initRun ), MCU_GETRESETREASON_SERVICE_ID, MCU_E_UNINIT, MCU_GETRESETRAWVALUE_UNINIT_RV );\r
+\r
+ if( !Mcu_Global.initRun ) {\r
+ return MCU_GETRESETRAWVALUE_UNINIT_RV;\r
+ }\r
+\r
+ return SIU.RSR.R;\r
+}\r
+\r
+//-------------------------------------------------------------------\r
+\r
+#if ( MCU_PERFORM_RESET_API == STD_ON )\r
+void Mcu_PerformReset(void)\r
+{\r
+ VALIDATE( ( 1 == Mcu_Global.initRun ), MCU_PERFORMRESET_SERVICE_ID, MCU_E_UNINIT );\r
+\r
+ // Reset\r
+ SIU.SRCR.B.SSR = 1;\r
+\r
+}\r
+#endif\r
+\r
+//-------------------------------------------------------------------\r
+\r
+void Mcu_SetMode(const Mcu_ModeType McuMode)\r
+{\r
+ VALIDATE( ( 1 == Mcu_Global.initRun ), MCU_SETMODE_SERVICE_ID, MCU_E_UNINIT );\r
+ VALIDATE( ( McuMode <= Mcu_Global.config->McuNumberOfMcuModes ), MCU_SETMODE_SERVICE_ID, MCU_E_PARAM_MODE );\r
+ (void) McuMode;\r
+\r
+ /* NOT SUPPORTED */\r
+}\r
+\r
+//-------------------------------------------------------------------\r
+\r
+/**\r
+ * Get the system clock in Hz. It calculates the clock from the\r
+ * different register settings in HW.\r
+ */\r
+uint32_t McuE_GetSystemClock(void)\r
+{\r
+ /*\r
+ * System clock calculation\r
+ *\r
+ * 5516 - f_sys = extal * (emfd+16) / ( (eprediv+1) * ( erfd+1 ));\r
+ * 5567 - f_sys = extal * (emfd+4) / ( (eprediv+1) * ( 2^erfd ));\r
+ */\r
+#if defined(CFG_MPC5516)\r
+ uint32_t eprediv = FMPLL.ESYNCR1.B.EPREDIV;\r
+ uint32_t emfd = FMPLL.ESYNCR1.B.EMFD;\r
+ uint32_t erfd = FMPLL.ESYNCR2.B.ERFD;\r
+#elif defined(CFG_MPC5554) || defined(CFG_MPC5567)\r
+ uint32_t eprediv = FMPLL.SYNCR.B.PREDIV;\r
+ uint32_t emfd = FMPLL.SYNCR.B.MFD;\r
+ uint32_t erfd = FMPLL.SYNCR.B.RFD;\r
+#endif\r
+ uint32_t f_sys;\r
+ uint32 extal = Mcu_Global.config->McuClockSettingConfig[Mcu_Global.clockSetting].McuClockReferencePoint;\r
+\r
+ f_sys = CALC_SYSTEM_CLOCK(extal,emfd,eprediv,erfd);\r
+\r
+ return f_sys;\r
+}\r
+\r
+imask_t McuE_EnterCriticalSection()\r
+{\r
+ uint32_t msr = get_msr();\r
+ Irq_Disable();\r
+ return msr;\r
+}\r
+\r
+void McuE_ExitCriticalSection(uint32_t old_state)\r
+{\r
+ set_msr(old_state);\r
+}\r
+\r
+/**\r
+ * Get the peripheral clock in Hz for a specific device\r
+ */\r
+\r
+uint32_t McuE_GetPeripheralClock(McuE_PeriperalClock_t type)\r
+{\r
+#if defined(CFG_MPC5567)\r
+ // No peripheral dividers on 5567.\r
+ return McuE_GetSystemClock();\r
+#else\r
+ uint32_t sysClock = McuE_GetSystemClock();\r
+ vuint32_t prescaler;\r
+\r
+\r
+ // See table 3.1, section 3.4.5 Peripheral Clock dividers\r
+ switch (type)\r
+ {\r
+ case PERIPHERAL_CLOCK_FLEXCAN_A:\r
+ case PERIPHERAL_CLOCK_DSPI_A:\r
+#if defined(CFG_MPC5516)\r
+ prescaler = SIU.SYSCLK.B.LPCLKDIV0;\r
+ break;\r
+#endif\r
+\r
+ case PERIPHERAL_CLOCK_PIT:\r
+ case PERIPHERAL_CLOCK_ESCI_A:\r
+ case PERIPHERAL_CLOCK_IIC_A:\r
+#if defined(CFG_MPC5516)\r
+ prescaler = SIU.SYSCLK.B.LPCLKDIV1;\r
+ break;\r
+#endif\r
+\r
+ case PERIPHERAL_CLOCK_FLEXCAN_B:\r
+ case PERIPHERAL_CLOCK_FLEXCAN_C:\r
+ case PERIPHERAL_CLOCK_FLEXCAN_D:\r
+ case PERIPHERAL_CLOCK_FLEXCAN_E:\r
+ case PERIPHERAL_CLOCK_FLEXCAN_F:\r
+#if defined(CFG_MPC5516)\r
+ prescaler = SIU.SYSCLK.B.LPCLKDIV2;\r
+ break;\r
+#endif\r
+\r
+ case PERIPHERAL_CLOCK_DSPI_B:\r
+ case PERIPHERAL_CLOCK_DSPI_C:\r
+ case PERIPHERAL_CLOCK_DSPI_D:\r
+#if defined(CFG_MPC5516)\r
+ prescaler = SIU.SYSCLK.B.LPCLKDIV3;\r
+ break;\r
+#endif\r
+\r
+ case PERIPHERAL_CLOCK_ESCI_B:\r
+ case PERIPHERAL_CLOCK_ESCI_C:\r
+ case PERIPHERAL_CLOCK_ESCI_D:\r
+ case PERIPHERAL_CLOCK_ESCI_E:\r
+ case PERIPHERAL_CLOCK_ESCI_F:\r
+ case PERIPHERAL_CLOCK_ESCI_G:\r
+ case PERIPHERAL_CLOCK_ESCI_H:\r
+#if defined(CFG_MPC5516)\r
+ prescaler = SIU.SYSCLK.B.LPCLKDIV4;\r
+ break;\r
+#endif\r
+\r
+ case PERIPHERAL_CLOCK_EMIOS:\r
+#if defined(CFG_MPC5516)\r
+ prescaler = SIU.SYSCLK.B.LPCLKDIV5;\r
+ break;\r
+#endif\r
+\r
+ case PERIPHERAL_CLOCK_MLB:\r
+#if defined(CFG_MPC5516)\r
+ prescaler = SIU.SYSCLK.B.LPCLKDIV6;\r
+ break;\r
+#endif\r
+\r
+ default:\r
+ assert(0);\r
+ break;\r
+ }\r
+\r
+ return sysClock/(1<<prescaler);\r
+#endif\r
+}\r
+\r
+\r
+/**\r
+ * Function to setup the internal flash for optimal performance\r
+ */\r
+\r
+static void Mcu_ConfigureFlash(void)\r
+{\r
+ /* These flash settings increases the CPU performance of 7 times compared\r
+ to reset default settings!! */\r
+\r
+#if defined(CFG_MPC5516)\r
+ /* Disable pipelined reads when flash options are changed. */\r
+ FLASH.MCR.B.PRD = 1;\r
+\r
+ /* Enable master prefetch for e200z1 and eDMA. */\r
+ FLASH.PFCRP0.B.M0PFE = 1;\r
+ FLASH.PFCRP0.B.M2PFE = 1;\r
+\r
+ /* Address pipelining control. Must be set to the same value as RWSC. */\r
+ FLASH.PFCRP0.B.APC = 2;\r
+ FLASH.PFCRP0.B.RWSC = 2;\r
+\r
+ /* Write wait states. */\r
+ FLASH.PFCRP0.B.WWSC = 1;\r
+\r
+ /* Enable data prefetch. */\r
+ FLASH.PFCRP0.B.DPFEN = 1;\r
+\r
+ /* Enable instruction prefetch. */\r
+ FLASH.PFCRP0.B.IPFEN = 1;\r
+\r
+ /* Prefetch algorithm. */\r
+ /* TODO: Ask Freescale about this option. */\r
+ FLASH.PFCRP0.B.PFLIM = 2;\r
+\r
+ /* Enable line read buffers. */\r
+ FLASH.PFCRP0.B.BFEN = 1;\r
+\r
+ /* Enable pipelined reads again. */\r
+ FLASH.MCR.B.PRD = 0;\r
+#elif defined(CFG_MPC5554) || defined(CFG_MPC5567)\r
+ //TODO: Lägg till flash för mpc5554 &67\r
+#endif\r
+}\r
+\r
+void McuE_EnableInterrupts(void)\r
+{\r
+ Irq_Enable();\r
+}\r
+\r
+void McuE_DisableInterrupts(void)\r
+{\r
+ Irq_Disable();\r
+}\r
--- /dev/null
+\r
+#define _ASSEMBLER_\r
+#include "asm_ppc.h"\r
+#include "asm_book_e.h"\r
+#ifdef USE_KERNEL\r
+#include "asm_offset.h"\r
+#endif\r
+\r
+#define INTC_IACKR 0xfff48010\r
+#define INTC_EOIR 0xfff48018\r
+\r
+#define SIU_MIDR 0xfffe8004\r
+#define SIMULATOR(_reg,_inst,_label) \\r
+ lis _reg, SIU_MIDR@ha; \\r
+ lwz _reg, SIU_MIDR@l(_reg); \\r
+ cmpwi 0,_reg,0; \\r
+ _inst _label;\r
+\r
+\r
+ .extern intc_vector_tbl\r
+\r
+ .section .text\r
+//---------------------------------------------------------------\r
+// just a small decrementer exception to trigger soft interrupt\r
+// in the INTC( simluator addon )\r
+\r
+\r
+ #define INTC_SSCIR7 0xFFF48027\r
+ .global dec_exception\r
+\r
+dec_exception:\r
+ stwu r3,-8(sp)\r
+ stw r4,4(sp)\r
+\r
+ # ack dec int\r
+ lis r3,0x0800\r
+ mtspr SPR_TSR,r3\r
+\r
+ # Set soft int\r
+ li r4,2\r
+ lis r3, INTC_SSCIR7@ha\r
+ stb r4, INTC_SSCIR7@l(r3)\r
+\r
+ lwz r3,0(sp)\r
+ lwz r4,4(sp)\r
+ addi sp,sp,8\r
+ rfi\r
+\r
+\r
+EXCEPTION_CSRRx(exception_IVOR0,320) //#CRITICAL_INPUT_EXCEPTION\r
+EXCEPTION_CSRRx(exception_IVOR1,321) //#MACHINE_CHECK_EXCEPTION\r
+EXCEPTION_SRRx(exception_IVOR2,322) //#DATA_STORAGE_EXCEPTION\r
+EXCEPTION_SRRx(exception_IVOR3,323) //#INSTRUCTION_STORAGE_EXCEPTION\r
+// IVOR4, defined elsewhere\r
+EXCEPTION_SRRx(exception_IVOR5,325) //#ALIGNMENT_EXCEPTION\r
+EXCEPTION_SRRx(exception_IVOR6,326) //#PROGRAM_EXCEPTION\r
+EXCEPTION_SRRx(exception_IVOR7,327) //#FLOATING_POINT_EXCEPTION\r
+EXCEPTION_SRRx(exception_IVOR8,328) //#SYSTEM_CALL_EXCEPTION)\r
+EXCEPTION_SRRx(exception_IVOR9,329)\r
+// IVOR10, defined elsewhere\r
+EXCEPTION_SRRx(exception_IVOR11,331) //#FIXED_INTERVAL_TIMER_EXCEPTION\r
+EXCEPTION_SRRx(exception_IVOR12,332) //#WATCHDOG_TIMER_EXCEPTION\r
+EXCEPTION_SRRx(exception_IVOR13,333) //#DATA_TLB_EXCEPTION\r
+EXCEPTION_SRRx(exception_IVOR14,334) //#INSTRUCTION_TLB_EXCEPTION\r
+\r
+\r
+//\r
+// EXC_FRAME\r
+// VGPR_FRAME\r
+// NVGPR_FRAME\r
+//\r
+\r
+ .global exception_IVOR4\r
+ .global os_lc_restore\r
+ .balign 16\r
+exception_IVOR4:\r
+\r
+ SAVE_WORK_AND_MORE\r
+ // Save registers NOT preserved by functions\r
+ SAVE_VGPR(1,C_SIZE);\r
+ // Save registers preserved by functions\r
+ addi r1,r1,C_SIZE\r
+ SAVE_NVGPR(1,0);\r
+ addi r1,r1,-C_SIZE\r
+\r
+ // TODO: Why 0, can't remember\r
+ li r3,0\r
+ stw r3,EXC_VECTOR_OFF(r4)\r
+ mr r4,r1 // save stack\r
+\r
+#ifdef USE_KERNEL\r
+ li r3,LC_PATTERN\r
+ stw r3,C_CONTEXT_OFF(sp)\r
+\r
+ // Switch to interrupt stack if at depth 0\r
+ LOAD_IND_32(3,os_sys+SYS_INT_NEST_CNT)\r
+ cmpli 0,r3,0\r
+ bne- on_int_stack\r
+ // Load the interrupt stack\r
+ LOAD_IND_32(sp,os_sys+SYS_INT_STACK)\r
+on_int_stack:\r
+\r
+#endif\r
+\r
+ lis r3, IntCtrl_Entry@h\r
+ ori r3, r3,IntCtrl_Entry@l\r
+\r
+ mtlr r3\r
+ mr r3,r4 /* "old" stack as arg1 */\r
+ blrl\r
+\r
+#ifdef USE_KERNEL\r
+// Set the retun value as new stack\r
+ mr sp,r3\r
+#endif\r
+ addi r1,r1,C_SIZE\r
+ RESTORE_NVGPR(1,0)\r
+ addi r1,r1,-C_SIZE\r
+ RESTORE_VGPR(1,C_SIZE)\r
+\r
+ RESTORE_WORK_AND_MORE\r
+ rfi\r
+\r
+bad_int:\r
+ b bad_int\r
+\r
+# Force this jump table to this address to match the\r
+# value written to z1 IVPR\r
+.section ".exception_tbl","ax"\r
+.balign 0x0800 //TODO: 1000 eller 800?\r
+.global exception_tbl\r
+\r
+# The .skip directive aligns the branch instructions\r
+# to the irq vector offsets\r
+exception_tbl:\r
+ b exception_IVOR0\r
+ .skip +0xc\r
+ b exception_IVOR1\r
+ .skip +0xc\r
+ b exception_IVOR2\r
+ .skip +0xc\r
+ b exception_IVOR3\r
+ .skip +0xc\r
+ b exception_IVOR4\r
+ .skip +0xc\r
+ b exception_IVOR5\r
+ .skip +0xc\r
+ b exception_IVOR6\r
+ .skip +0xc\r
+ b exception_IVOR7\r
+ .skip +0xc\r
+ b exception_IVOR8\r
+ .skip +0xc\r
+ b exception_IVOR9\r
+ .skip +0xc\r
+ b dec_exception\r
+ //b exception_IVOR10\r
+ .skip +0xc\r
+ b exception_IVOR11\r
+ .skip +0xc\r
+ b exception_IVOR12\r
+ .skip +0xc\r
+ b exception_IVOR13\r
+ .skip +0xc\r
+ b exception_IVOR14\r
+ .skip +0xc\r
+ b bad_int\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include "typedefs.h"\r
+#include "asm_book_e.h"\r
+#include "mpc55xx.h"\r
+#if !defined(USE_KERNEL)\r
+#include "Mcu.h"\r
+#endif\r
+#include <assert.h>\r
+//#include <stdio.h>\r
+\r
+#if defined(USE_KERNEL)\r
+#include "pcb.h"\r
+#include "sys.h"\r
+#include "internal.h"\r
+#include "task_i.h"\r
+#include "hooks.h"\r
+#include "swap.h"\r
+\r
+#define INTC_SSCIR0_CLR7 7\r
+#define MLB_SERVICE_REQUEST 293\r
+#define CRITICAL_INPUT_EXCEPTION 320\r
+#define DEBUG_EXCEPTION 335\r
+#define NUMBER_OF_INTERRUPTS_AND_EXCEPTIONS 336\r
+\r
+#include "Trace.h"\r
+#endif\r
+\r
+static void dump_exception_regs( uint32_t *regs );\r
+\r
+typedef void (*f_t)( uint32_t *);\r
+typedef void (*func_t)();\r
+\r
+#if defined(USE_KERNEL)\r
+extern void * intc_vector_tbl[NUMBER_OF_INTERRUPTS_AND_EXCEPTIONS];\r
+extern uint8 intc_type_tbl[NUMBER_OF_INTERRUPTS_AND_EXCEPTIONS];\r
+#else\r
+extern func_t intc_vector_tbl[];\r
+#endif\r
+\r
+/* Handle INTC\r
+ *\r
+ * When we get here we have saved\r
+ * - exception frame\r
+ * - VGPR\r
+ * - ?\r
+ *\r
+ * */\r
+\r
+\r
+\r
+void IntCtrl_AttachIsr1( void (*entry)(void), void *int_ctrl, uint32_t vector,uint8_t prio) {\r
+#if defined(CFG_MPC5516)\r
+ uint8_t cpu = 0; /* 0- cpu Z1, 1-CPU Z0(slave) */\r
+#endif\r
+\r
+ intc_vector_tbl[vector] = (void *)entry;\r
+ intc_type_tbl[vector] = PROC_ISR1;\r
+\r
+ if (vector <= MLB_SERVICE_REQUEST) {\r
+#if defined(CFG_MPC5516)\r
+ INTC.PSR[vector].B.PRC_SEL = cpu;\r
+#endif\r
+ INTC.PSR[vector].B.PRI = prio;\r
+\r
+ } else if ((vector >= CRITICAL_INPUT_EXCEPTION) && (vector\r
+ <= DEBUG_EXCEPTION)) {\r
+ } else {\r
+ /* Invalid vector! */\r
+ assert(0);\r
+ }\r
+\r
+}\r
+\r
+void IntCtrl_AttachIsr2(TaskType tid,void *int_ctrl,uint32_t vector ) {\r
+#if defined(CFG_MPC5516)\r
+ uint8_t cpu = 0; /* 0- cpu Z1, 1-CPU Z0(slave) */\r
+#endif\r
+ pcb_t *pcb;\r
+\r
+ pcb = os_find_task(tid);\r
+ intc_vector_tbl[vector] = (void *)pcb;\r
+ intc_type_tbl[vector] = PROC_ISR2;\r
+\r
+ if (vector <= MLB_SERVICE_REQUEST) {\r
+#if defined(CFG_MPC5516)\r
+ INTC.PSR[vector].B.PRC_SEL = cpu;\r
+#endif\r
+ INTC.PSR[vector].B.PRI = pcb->prio;\r
+\r
+ } else if ((vector >= CRITICAL_INPUT_EXCEPTION) && (vector\r
+ <= DEBUG_EXCEPTION)) {\r
+ } else {\r
+ /* Invalid vector! */\r
+ assert(0);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ *\r
+ * USE_KERNEL\r
+ * Following must be done before coming here:\r
+ * - Swapped to interrupt stack, or???\r
+ *\r
+ * @param stack Ptr to current stack. The context just saved\r
+ * can be access with positive offsets.\r
+ */\r
+\r
+void *mcu_intc( uint32_t *stack ) {\r
+ uint32_t vector;\r
+\r
+#if defined(CFG_MPC5516)\r
+ struct INTC_tag *intc = &INTC;\r
+#else\r
+ volatile struct INTC_tag *intc = &INTC;\r
+#endif\r
+\r
+#if defined(USE_KERNEL)\r
+ struct pcb_s *pcb;\r
+ struct pcb_s *preempted_pcb;\r
+#else\r
+ func_t t;\r
+#endif\r
+\r
+ // Check for exception\r
+ if( stack[EXC_VECTOR_OFF/sizeof(uint32_t)]>=CRITICAL_INPUT_EXCEPTION )\r
+ {\r
+ vector = stack[EXC_VECTOR_OFF/sizeof(uint32_t)];\r
+ }\r
+ else\r
+ {\r
+#if defined(CFG_MPC5516)\r
+ vector = (intc->IACKR_PRC0.B.INTVEC_PRC0);\r
+#else\r
+ vector = (intc->IACKR.B.INTVEC);\r
+#endif\r
+ // save the vector for later\r
+ stack[EXC_VECTOR_OFF/sizeof(uint32_t)] = vector;\r
+\r
+ // Check for software interrupt\r
+ if((uint32_t)vector<=INTC_SSCIR0_CLR7)\r
+ {\r
+ // Clear soft int\r
+ intc->SSCIR[vector].B.CLR = 1;\r
+ }\r
+ }\r
+\r
+#if defined(USE_KERNEL)\r
+\r
+ os_sys.int_nest_cnt++;\r
+\r
+ if( intc_type_tbl[vector] == PROC_ISR1 ) {\r
+ // It's a function, just call it.\r
+ ((func_t)intc_vector_tbl[vector])();\r
+ } else {\r
+ // It's a PCB\r
+\r
+ // Save info for preemted pcb\r
+ preempted_pcb = get_curr_pcb();\r
+ preempted_pcb->stack.curr = stack;\r
+ preempted_pcb->state = ST_READY;\r
+ os_isr_printf(D_TASK,"Preempted %s\n",preempted_pcb->name);\r
+\r
+ POSTTASKHOOK();\r
+\r
+ pcb = intc_vector_tbl[vector];\r
+ pcb->state = ST_RUNNING;\r
+ set_curr_pcb(pcb);\r
+\r
+ PRETASKHOOK();\r
+\r
+ // We should not get here if we're SCHEDULING_NONE\r
+ if( pcb->scheduling == SCHEDULING_NONE) {\r
+ // TODO:\r
+ // assert(0);\r
+ while(1);\r
+ }\r
+ //Irq_Enable(); // Added by Mattias\r
+ //Irq_Enable();\r
+ pcb->entry();\r
+ Irq_Disable();\r
+ }\r
+\r
+ pcb->state = ST_SUSPENDED;\r
+ POSTTASKHOOK();\r
+\r
+ // write 0 to pop INTC stack\r
+\r
+#if defined(CFG_MPC5516)\r
+ intc->EOIR_PRC0.R = 0;\r
+#else\r
+ intc->EOIR.R = 0;\r
+#endif\r
+ --os_sys.int_nest_cnt;\r
+\r
+ // TODO: Check stack check marker....\r
+ // We have preempted a task\r
+ if( (os_sys.int_nest_cnt == 0) ) { //&& is_idle_task() ) {\r
+ /* If we get here:\r
+ * - the preempted task is saved with large context.\r
+ * - We are on interrupt stack..( this function )\r
+ *\r
+ * if we find a new task:\r
+ * - just switch in the new context( don't save the old because\r
+ * its already saved )\r
+ *\r
+ */\r
+ pcb_t *new_pcb;\r
+ new_pcb = os_find_top_prio_proc();\r
+ if( new_pcb != preempted_pcb ) {\r
+ os_isr_printf(D_TASK,"Found candidate %s\n",new_pcb->name);\r
+//#warning os_swap_context_to should call the pretaskswaphook\r
+ os_swap_context_to(NULL,new_pcb);\r
+ } else {\r
+ if( new_pcb == NULL ) {\r
+ assert(0);\r
+ }\r
+ preempted_pcb->state = ST_RUNNING;\r
+ set_curr_pcb(preempted_pcb);\r
+ }\r
+ }\r
+\r
+ return stack;\r
+\r
+#else\r
+ //read address\r
+ t = (func_t)intc_vector_tbl[vector];\r
+\r
+ if( t == ((void *)0) )\r
+ {\r
+ while(1);\r
+ }\r
+\r
+ // Enable nestling interrupts\r
+ Irq_Enable();\r
+ t();\r
+ Irq_Disable();\r
+\r
+ if( vector < INTC_NUMBER_OF_INTERRUPTS )\r
+ {\r
+ // write 0 to pop INTC stack\r
+ intc->EOIR_PRC0.R = 0;\r
+ }\r
+ return NULL;\r
+#endif\r
+}\r
+\r
+void dummy (void);\r
+\r
+// Critical Input Interrupt\r
+void IVOR0Exception (uint32_t *regs)\r
+{\r
+// srr0 = get_spr(SPR_SRR0);\r
+// srr1 = get_spr(SPR_SRR0);\r
+// ExceptionSave(srr0,srr1,esr,mcsr,dear;)\r
+ // CSRR0, CSSR1\r
+ // Nothing more\r
+ dump_exception_regs(regs);\r
+ while (1);\r
+}\r
+\r
+// Machine check\r
+void IVOR1Exception (uint32_t *regs)\r
+{\r
+ // CSRR0, CSSR1\r
+ // MCSR - Source of machine check\r
+ dump_exception_regs(regs);\r
+ while (1);\r
+}\r
+// Data Storage Interrupt\r
+void IVOR2Exception (uint32_t *regs)\r
+{\r
+ // SRR0, SRR1\r
+ // ESR - lots of stuff\r
+ dump_exception_regs(regs);\r
+ while (1);\r
+}\r
+\r
+// Instruction Storage Interrupt\r
+void IVOR3Exception (uint32_t *regs)\r
+{\r
+ // SRR0, SRR1\r
+ // ESR - lots of stuff\r
+ dump_exception_regs(regs);\r
+ while (1);\r
+}\r
+\r
+// Alignment Interrupt\r
+void IVOR5Exception (uint32_t *regs)\r
+{\r
+ // SRR0, SRR1\r
+ // ESR - lots of stuff\r
+ // DEAR - Address of load store that caused the exception\r
+ dump_exception_regs(regs);\r
+ while (1);\r
+}\r
+\r
+// Program Interrupt\r
+void IVOR6Exception (uint32_t *regs)\r
+{\r
+ // SRR0, SRR1\r
+ // ESR - lots of stuff\r
+ dump_exception_regs(regs);\r
+ while (1);\r
+}\r
+\r
+// Floating point unavailable\r
+void IVOR7Exception (uint32_t *regs)\r
+{\r
+ // SRR0, SRR1\r
+ dump_exception_regs(regs);\r
+ while (1);\r
+}\r
+\r
+// System call\r
+void IVOR8Exception (uint32_t *regs)\r
+{\r
+ // SRR0, SRR1\r
+ // ESR\r
+ dump_exception_regs(regs);\r
+ while (1);\r
+}\r
+\r
+// Aux processor Unavailable\r
+void IVOR9Exception (uint32_t *regs)\r
+{\r
+ // Does not happen on e200\r
+ dump_exception_regs(regs);\r
+ while (1);\r
+}\r
+#if 0\r
+// Decrementer\r
+void IVOR10Exception (uint32_t *regs)\r
+{\r
+ // SRR0, SRR1\r
+ while (1);\r
+}\r
+#endif\r
+\r
+// FIT\r
+void IVOR11Exception (uint32_t *regs)\r
+{\r
+ // SRR0, SRR1\r
+ dump_exception_regs(regs);\r
+ while (1);\r
+}\r
+\r
+// Watchdog Timer\r
+void IVOR12Exception (uint32_t *regs)\r
+{\r
+ // SRR0, SRR1\r
+ dump_exception_regs(regs);\r
+ while (1);\r
+}\r
+\r
+// Data TLB Error Interrupt\r
+void IVOR13Exception (uint32_t *regs)\r
+{\r
+#if 0\r
+ uint32_t srr0,srr1,esr,dear;\r
+\r
+ srr0 = regs[SC_GPRS_SIZE+(EXC_SRR0_OFF/4)];\r
+ srr1 = regs[SC_GPRS_SIZE+(EXC_SRR1_OFF/4)];\r
+ esr = regs[SC_GPRS_SIZE+(EXC_ESR_OFF/4)];\r
+ dear = regs[SC_GPRS_SIZE+(EXC_DEAR_OFF/4)];\r
+ dump_exception_regs(regs);\r
+#endif\r
+\r
+ // SRR0, SRR1\r
+ // ESR - lots\r
+ // DEAR -\r
+ while (1);\r
+}\r
+\r
+// Instruction TLB Error Interupt\r
+void IVOR14Exception (uint32_t *regs)\r
+{\r
+ // SRR0, SRR1\r
+ // ESR - MIF set, All others cleared\r
+ dump_exception_regs(regs);\r
+ while (1);\r
+}\r
+\r
+void IVOR15Exception (uint32_t *regs)\r
+{\r
+ // Debug\r
+ dump_exception_regs(regs);\r
+ while (1);\r
+}\r
+\r
+#if defined(CFG_CONSOLE_T32) || defined(CFG_CONSOLE_WINIDEA)\r
+\r
+typedef struct {\r
+ uint32_t sp;\r
+ uint32_t bc; // backchain\r
+ uint32_t pad;\r
+ uint32_t srr0;\r
+ uint32_t srr1;\r
+ uint32_t lr;\r
+ uint32_t ctr;\r
+ uint32_t xer;\r
+ uint32_t cr;\r
+ uint32_t esr;\r
+ uint32_t mcsr;\r
+ uint32_t dear;\r
+ uint32_t vector;\r
+ uint32_t r3;\r
+ uint32_t r4;\r
+} exc_stack_t;\r
+\r
+\r
+\r
+static void dump_exception_regs( uint32_t *regs ) {\r
+ exc_stack_t *r = (exc_stack_t *)regs;\r
+\r
+dbg_printf("sp %08x srr0 %08x srr1 %08x\n",r->sp,r->srr0,r->srr1);\r
+dbg_printf("lr %08x ctr %08x xer %08x\n",r->lr,r->ctr,r->xer);\r
+dbg_printf("cr %08x esr %08x mcsr %08x\n",r->cr,r->esr,r->mcsr);\r
+dbg_printf("dear %08x vec %08x r3 %08x\n",r->dear,r->vector,r->r3);\r
+dbg_printf("r4 %08x\n",r->r4);\r
+}\r
+\r
+#else\r
+static void dump_exception_regs( uint32_t *regs ) {\r
+}\r
+#endif\r
+\r
+#if !defined(USE_KERNEL)\r
+func_t intc_vector_tbl[NUMBER_OF_INTERRUPTS_AND_EXCEPTIONS] __attribute__ ((aligned (0x800))) = {\r
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 00 - 04 */\r
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 05 - 09 */\r
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 10 - 14 */\r
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 15 - 19 */\r
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 20 - 24 */\r
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 25 - 29 */\r
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 30 - 34 */\r
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 35 - 39 */\r
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 40 - 44 */\r
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 45 - 49 */\r
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 50 - 54 */\r
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 55 - 59 */\r
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 60 - 64 */\r
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 55 - 69 */\r
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 70 - 74 */\r
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 75 - 79 */\r
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 80 - 84 */\r
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 85 - 89 */\r
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 90 - 94 */\r
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 95 - 99 */\r
+\r
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 100 - 104 */\r
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 105 - 109 */\r
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 110 - 114 */\r
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 115 - 119 */\r
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 120 - 124 */\r
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 125 - 129 */\r
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 130 - 134 */\r
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 135 - 139 */\r
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 140 - 144 */\r
+ dummy, dummy, dummy, dummy, dummy /* PIT1 */, /* ISRs 145 - 149 */\r
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 150 - 154 */\r
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 155 - 159 */\r
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 160 - 164 */\r
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 155 - 169 */\r
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 170 - 174 */\r
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 175 - 179 */\r
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 180 - 184 */\r
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 185 - 189 */\r
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 190 - 194 */\r
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 195 - 199 */\r
+\r
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 200 - 204 */\r
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 205 - 209 */\r
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 210 - 214 */\r
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 215 - 219 */\r
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 220 - 224 */\r
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 225 - 229 */\r
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 230 - 234 */\r
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 235 - 239 */\r
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 240 - 244 */\r
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 245 - 249 */\r
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 250 - 254 */\r
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 255 - 259 */\r
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 260 - 264 */\r
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 255 - 269 */\r
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 270 - 274 */\r
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 275 - 279 */\r
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 280 - 284 */\r
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 285 - 289 */\r
+ dummy, dummy, dummy, dummy, /* ISRs 290 - 293 */\r
+\r
+ /* Some reserved vectors between INC interrupts and exceptions. */\r
+ dummy, /* INTC_NUMBER_OF_INTERRUPTS */\r
+\r
+ dummy, dummy, dummy, dummy, dummy,\r
+ dummy, dummy, dummy, dummy, dummy,\r
+ dummy, dummy, dummy, dummy, dummy,\r
+ dummy, dummy, dummy, dummy, dummy,\r
+ dummy, dummy, dummy, dummy, dummy,\r
+\r
+ IVOR0Exception, /* CRITICAL_INPUT_EXCEPTION, */\r
+ IVOR1Exception, /* MACHINE_CHECK_EXCEPTION */\r
+ IVOR2Exception, /* DATA_STORAGE_EXCEPTION */\r
+ IVOR3Exception, /* INSTRUCTION_STORAGE_EXCEPTION */\r
+ dummy, /* EXTERNAL_INTERRUPT */\r
+ /* This is the place where the "normal" interrupts will hit the CPU... */\r
+ IVOR5Exception, /* ALIGNMENT_EXCEPTION */\r
+ IVOR6Exception, /* PROGRAM_EXCEPTION */\r
+ IVOR7Exception, /* FLOATING_POINT_EXCEPTION */\r
+ IVOR8Exception, /* SYSTEM_CALL_EXCEPTION */\r
+ dummy, /* AUX_EXCEPTION Not implemented in MPC5516. */\r
+ dummy, /* DECREMENTER_EXCEPTION */\r
+ IVOR11Exception, /* FIXED_INTERVAL_TIMER_EXCEPTION */\r
+ IVOR12Exception, /* WATCHDOG_TIMER_EXCEPTION */\r
+ IVOR13Exception, /* DATA_TLB_EXCEPTION */\r
+ IVOR14Exception, /* INSTRUCTION_TLB_EXCEPTION */\r
+ IVOR15Exception, /* DEBUG_EXCEPTION */\r
+};\r
+\r
+void dummy (void) {\r
+ while (1){\r
+ /* TODO: Rename and check for what spurious interrupt have happend */\r
+ };\r
+ }\r
+\r
+#endif\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include "Std_Types.h"\r
+#include "Port.h"\r
+#include "mpc55xx.h"\r
+#include <string.h>\r
+#include "Det.h"\r
+#include "Cpu.h"\r
+/* SHORT ON HW\r
+ * Have a bunch of ports:\r
+ * - PAxx, input only port\r
+ * - PBxx to PKxx, i/o ports\r
+ * where xx is 0 to 15\r
+ * Regs:\r
+ * PCRx( Pad Config Register ) - register function(in, out, pull up/down, etc )\r
+ * 0 - 15 : Port A\r
+ * 16 - 43 : Port B to J\r
+ * 144-145 : Port K\r
+ * GPD0( Pin Data Output Registers ) -\r
+ *\r
+ */\r
+\r
+static Port_StateType _portState = PORT_UNINITIALIZED;\r
+\r
+#if (PORT_DEV_ERROR_DETECT)\r
+#define VALIDATE_PARAM_CONFIG(_ptr,_api) \\r
+ if( (_ptr)==((void *)0) ) { \\r
+ Det_ReportError(MODULE_ID_PORT, 0, _api, PORT_E_PARAM_CONFIG ); \\r
+ goto cleanup; \\r
+ }\r
+\r
+#define VALIDATE_STATE_INIT(_api)\\r
+ if(PORT_INITIALIZED!=_portState){\\r
+ Det_ReportError(MODULE_ID_PORT, 0, _api, PORT_E_UNINIT ); \\r
+ goto cleanup; \\r
+ }\r
+\r
+#define VALIDATE_PARAM_PIN(_pin, _api)\\r
+ if(_pin>sizeof(SIU.PCR)){\\r
+ Det_ReportError(MODULE_ID_PORT, 0, _api, PORT_E_PARAM_PIN ); \\r
+ goto cleanup; \\r
+ }\r
+#else\r
+#define VALIDATE_PARAM_CONFIG(_ptr,_api)\r
+#define VALIDATE_STATE_INIT(_api)\r
+#define VALIDATE_PARAM_PIN(_api)\r
+#endif\r
+\r
+static Std_VersionInfoType _Port_VersionInfo =\r
+{\r
+ .vendorID = (uint16)1,\r
+ .moduleID = (uint16)1,\r
+ .instanceID = (uint8)1,\r
+ .sw_major_version = (uint8)PORT_SW_MAJOR_VERSION,\r
+ .sw_minor_version = (uint8)PORT_SW_MINOR_VERSION,\r
+ .sw_patch_version = (uint8)PORT_SW_PATCH_VERSION,\r
+ .ar_major_version = (uint8)PORT_AR_MAJOR_VERSION,\r
+ .ar_minor_version = (uint8)PORT_AR_MINOR_VERSION,\r
+ .ar_patch_version = (uint8)PORT_AR_PATCH_VERSION,\r
+};\r
+const Port_ConfigType * _configPtr = &PortConfigData;\r
+void Port_Init(const Port_ConfigType *configType)\r
+{\r
+ VALIDATE_PARAM_CONFIG(configType, PORT_INIT_ID);\r
+\r
+ // Pointers to the register memory areas\r
+ vuint16_t * padConfig = &(SIU.PCR[0].R);\r
+ vuint8_t * outConfig = &(SIU.GPDO[0].R);\r
+// vuint8_t * inConfig = &(SIU.GPDI[0].R);\r
+\r
+ // Copy config to register areas\r
+ memcpy((void *)outConfig, configType->outConfig, configType->outCnt);\r
+ memcpy((void *)padConfig, configType->padConfig, configType->padCnt);\r
+ //memcpy((void *)inConfig, configType->inConfig, configType->inCnt);\r
+ _portState = PORT_INITIALIZED;\r
+ _configPtr = configType;\r
+ cleanup: return;\r
+}\r
+\r
+#if ( PORT_PIN_DIRECTION_CHANGES_ALLOWED == STD_ON )\r
+void Port_SetPinDirection( Port_PinType pin, Port_PinDirectionType direction )\r
+{\r
+ VALIDATE_STATE_INIT(PORT_SET_PIN_DIRECTION_ID);\r
+ VALIDATE_PARAM_PIN(pin, PORT_SET_PIN_DIRECTION_ID);\r
+ unsigned long state;\r
+\r
+ if (direction==PORT_PIN_IN)\r
+ {\r
+ state = _Irq_Disable_save(); // Lock interrupts\r
+ SIU.PCR[pin].B.IBE = 1;\r
+ SIU.PCR[pin].B.OBE = 0;\r
+ _Irq_Disable_restore(state); // Restore interrups\r
+ }\r
+ else\r
+ {\r
+ state = _Irq_Disable_save(); // Lock interrupts\r
+ SIU.PCR[pin].B.IBE = 0;\r
+ SIU.PCR[pin].B.OBE = 1;\r
+ _Irq_Disable_restore(state); // Restore interrups\r
+ }\r
+cleanup:return;\r
+}\r
+\r
+void Port_RefreshPortDirection( void )\r
+{\r
+ VALIDATE_STATE_INIT(PORT_REFRESH_PORT_DIRECTION_ID);\r
+ vuint16_t * pcrPtr = &(SIU.PCR[0].R);\r
+ const uint16_t * padCfgPtr = _configPtr->padConfig;\r
+ uint16_t bitMask = IBE_ENABLE|OBE_ENABLE;\r
+ int i;\r
+ unsigned long state;\r
+ for (i=0; i < sizeof(SIU.PCR); i++)\r
+ {\r
+ state = _Irq_Disable_save(); // Lock interrupts\r
+ *pcrPtr = (*pcrPtr & ~bitMask) | (*padCfgPtr & bitMask);\r
+ _Irq_Disable_restore(state); // Restore interrups\r
+ pcrPtr++;\r
+ padCfgPtr++;\r
+ }\r
+\r
+ cleanup:return;\r
+}\r
+#endif\r
+\r
+#if PORT_VERSION_INFO_API == STD_ON\r
+void Port_GetVersionInfo(Std_VersionInfoType* versionInfo)\r
+{\r
+ VALIDATE_STATE_INIT(PORT_GET_VERSION_INFO_ID);\r
+ memcpy(versionInfo, &_Port_VersionInfo, sizeof(Std_VersionInfoType));\r
+ cleanup: return;\r
+}\r
+#endif\r
+\r
+void Port_SetPinMode(Port_PinType Pin, Port_PinModeType Mode)\r
+{\r
+ VALIDATE_STATE_INIT(PORT_SET_PIN_MODE_ID);\r
+ //The pad configuration registers (SIU_PCR) in the SIU allow software control of the static electrical\r
+ //characteristics of external pins. The PCRs can select the multiplexed function of a pin, selection of pullup\r
+ //or pulldown devices, the slew rate of I/O signals, open drain mode for output pins, and hysteresis.\r
+ SIU.PCR[Pin].R = Mode; // Put the selected mode to the PCR register\r
+ cleanup: return;\r
+}\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*\r
+ * Pwm.c\r
+ *\r
+ * TODO: Implement DMA support for PWM\r
+ * TODO: Test PWM for MPC5567 and MPC5554\r
+ *\r
+ * Created on: 2009-jul-09\r
+ * Author: nian\r
+ */\r
+\r
+//#define USE_KERNEL\r
+\r
+#include <assert.h>\r
+#include <string.h>\r
+\r
+#include "Pwm.h"\r
+#include "MemMap.h"\r
+//#include "SchM_Pwm.h"\r
+#include "Det.h"\r
+#ifdef CFG_MPC5516\r
+#include "mpc5516.h"\r
+#elif defined(CFG_MPC5567)\r
+#include "mpc5567.h"\r
+#endif\r
+#if defined(USE_KERNEL)\r
+#include "Os.h"\r
+#endif\r
+#include "Mcu.h"\r
+\r
+#if PWM_DEV_EROR_DETECT==ON\r
+ #define PWM_VALIDATE(_exp, _errid) \\r
+ if (!(_exp)) { \\r
+ Pwm_ReportError(_errid); \\r
+ return; \\r
+ }\r
+ #define Pwm_VALIDATE_CHANNEL(_ch) PWM_VALIDATE(_ch <= 15, PWM_E_PARAM_CHANNEL)\r
+ #define Pwm_VALIDATE_INITIALIZED() PWM_VALIDATE(Pwm_ModuleState == PWM_STATE_INITIALIZED, PWM_E_UNINIT)\r
+ #define Pwm_VALIDATE_UNINITIALIZED() PWM_VALIDATE(Pwm_ModuleState != PWM_STATE_INITIALIZED, PWM_E_ALREADY_INITIALIZED)\r
+#else\r
+ #define Pwm_VALIDATE_CHANNEL(ch)\r
+ #define Pwm_VALIDATE_INITIALIZED()\r
+ #define Pwm_VALIDATE_UNINITIALIZED()\r
+#endif\r
+\r
+\r
+typedef enum {\r
+ PWM_STATE_UNINITIALIZED, PWM_STATE_INITIALIZED\r
+} Pwm_ModuleStateType;\r
+\r
+static Pwm_ModuleStateType Pwm_ModuleState = PWM_STATE_UNINITIALIZED;\r
+\r
+// Run-time variables\r
+typedef struct {\r
+ Pwm_ChannelClassType Class;\r
+\r
+ #if PWM_NOTIFICATION_SUPPORTED==ON\r
+ Pwm_NotificationHandlerType NotificationRoutine;\r
+ Pwm_EdgeNotificationType NotificationState;\r
+ #endif\r
+} Pwm_ChannelStructType;\r
+\r
+// We use Pwm_ChannelType as index here\r
+Pwm_ChannelStructType ChannelRuntimeStruct[16];\r
+\r
+/* Local functions */\r
+void inline Pwm_InitChannel(Pwm_ChannelType Channel);\r
+void inline Pwm_DeInitChannel(Pwm_ChannelType Channel);\r
+\r
+#if PWM_NOTIFICATION_SUPPORTED==ON\r
+static void Pwm_Isr(void);\r
+#endif\r
+\r
+void Pwm_Init(const Pwm_ConfigType* ConfigPtr) {\r
+ Pwm_ChannelType channel_iterator;\r
+\r
+ Pwm_VALIDATE_UNINITIALIZED();\r
+ #if PWM_DEV_EROR_DETECT==ON\r
+ /*\r
+ * PWM046: If development error detection is enabled for the Pwm module,\r
+ * the function Pwm_Init shall raise development error PWM_E_PARAM_CONFIG\r
+ * if ConfigPtr is a null pointer.\r
+ *\r
+ * PWM120: For pre-compile and link-time configuration variants, a NULL\r
+ * pointer shall be passed to the initialization routine. In this case the\r
+ * check for this NULL pointer has to be omitted.\r
+ */\r
+ #if PWM_STATICALLY_CONFIGURED==OFF\r
+ if (ConfigPtr == NULL) {\r
+ Pwm_ReportError(PWM_E_PARAM_CONFIG);\r
+ return;\r
+ }\r
+ #endif\r
+ #endif\r
+\r
+ #if PWM_NOTIFICATION_SUPPORTED==ON\r
+ // Create a task for our interrupt service routine.\r
+ TaskType tid = Os_CreateIsr(Pwm_Isr, PWM_ISR_PRIORITY /*prio*/, "PwmIsr");\r
+ #endif\r
+\r
+ /* Clock scaler uses system clock (~64MHz) as source, so prescaler 64 => 1MHz. */\r
+ EMIOS.MCR.B.GPRE = PWM_PRESCALER - 1;\r
+\r
+ /* Enable eMIOS clock */\r
+ EMIOS.MCR.B.GPREN = 1;\r
+\r
+ /* Stop channels when in debug mode */\r
+ EMIOS.MCR.B.FRZ = PWM_FREEZE_ENABLE;\r
+\r
+ /* Use global time base */\r
+ EMIOS.MCR.B.GTBE = 1;\r
+\r
+ Pwm_ModuleState = PWM_STATE_INITIALIZED;\r
+\r
+ for (channel_iterator = 0; channel_iterator < PWM_NUMBER_OF_CHANNELS; channel_iterator++) {\r
+ Pwm_ChannelType channel = ConfigPtr->Channels[channel_iterator].channel;\r
+\r
+ // Set up the registers in hw\r
+ memcpy((void*) &EMIOS.CH[channel],\r
+ (void*) &ConfigPtr->Channels[channel_iterator].r,\r
+ sizeof(Pwm_ChannelRegisterType));\r
+\r
+ #if PWM_NOTIFICATION_SUPPORTED==ON\r
+ /*\r
+ * PWM052: The function Pwm_Init shall disable all notifications.\r
+ *\r
+ * This is now implemented in the configuration macro.\r
+ */\r
+ // Pwm_DisableNotification(channel);\r
+\r
+ // Install ISR\r
+ IntCtrl_AttachIsr2(tid, NULL, EMISOS200_FLAG_F0 + channel);\r
+ ChannelRuntimeStruct[channel].NotificationRoutine\r
+ = ConfigPtr->NotificationHandlers[channel_iterator];\r
+ #endif\r
+ }\r
+}\r
+\r
+#if PWM_DEINIT_API==ON\r
+\r
+// TODO: Test that this function in fact turns the channel off.\r
+void inline Pwm_DeInitChannel(Pwm_ChannelType Channel) {\r
+ Pwm_VALIDATE_CHANNEL(Channel);\r
+ Pwm_VALIDATE_INITIALIZED();\r
+\r
+ Pwm_SetOutputToIdle(Channel);\r
+\r
+ #ifdef CFG_MPC5516\r
+ // Set the disable bit for this channel\r
+ EMIOS.UCDIS.R |= (1 << (31 - Channel));\r
+ #endif\r
+\r
+ /*\r
+ * PWM052: The function Pwm_DeInit shall disable all notifications.\r
+ */\r
+ #if PWM_NOTIFICATION_SUPPORTED==ON\r
+ Pwm_DisableNotification(Channel);\r
+ #endif\r
+}\r
+\r
+void Pwm_DeInit() {\r
+ /* TODO: Implement Pwm_DeInit() */\r
+ Pwm_ChannelType channel_iterator;\r
+\r
+ Pwm_VALIDATE_INITIALIZED();\r
+\r
+ for (channel_iterator = 0; channel_iterator < PWM_NUMBER_OF_CHANNELS; channel_iterator++) {\r
+ Pwm_DeInitChannel(channel_iterator);\r
+\r
+ }\r
+\r
+ // Disable module\r
+ EMIOS.MCR.B.MDIS = 1;\r
+\r
+ Pwm_ModuleState = PWM_STATE_UNINITIALIZED;\r
+}\r
+#endif\r
+\r
+void Pwm_GetVersionInfo(Std_VersionInfoType* VersionInfo) {\r
+ /* TODO: Implement Pwm_GetVersionInfo */\r
+}\r
+\r
+/*\r
+ * PWM083: The function Pwm_SetPeriodAndDuty shall be pre compile time\r
+ * changeable ON/OFF by the configuration parameter PwmSetPeriodAndDuty.\r
+ */\r
+#if PWM_SET_PERIOD_AND_DUTY==ON\r
+ void Pwm_SetPeriodAndDuty(Pwm_ChannelType Channel, Pwm_PeriodType Period,\r
+ Pwm_DutyCycleType DutyCycle) {\r
+\r
+ Pwm_VALIDATE_INITIALIZED();\r
+ Pwm_VALIDATE_CHANNEL(Channel);\r
+ PWM_VALIDATE(ChannelRuntimeStruct[Channel].Class == PWM_VARIABLE_PERIOD, PWM_E_PERIOD_UNCHANGEABLE);\r
+\r
+ uint16 leading_edge_position = (uint16) (((uint32) Period\r
+ * (uint32) DutyCycle) >> 15);\r
+\r
+\r
+\r
+ /* Timer instant for leading edge */\r
+ EMIOS.CH[Channel].CADR.R = leading_edge_position;\r
+\r
+ /* Timer instant for the period to restart */\r
+ EMIOS.CH[Channel].CBDR.R = Period;\r
+\r
+ }\r
+#endif\r
+\r
+\r
+/**\r
+ * PWM013: The function Pwm_SetDutyCycle shall set the duty cycle of the PWM\r
+ * channel.\r
+ *\r
+ * @TODO: How to conform with PWM018: "The driver shall forbid the spike on the PWM output signal"?\r
+ *\r
+ * @param Channel PWM channel to use. 0 <= Channel < PWM_NUMBER_OF_CHANNELS <= 16\r
+ * @param DutyCycle 0 <= DutyCycle <= 0x8000\r
+ */\r
+void Pwm_SetDutyCycle(Pwm_ChannelType Channel, Pwm_DutyCycleType DutyCycle) {\r
+\r
+ uint16 leading_edge_position = (uint16) ((EMIOS.CH[Channel].CBDR.R\r
+ * (uint32) DutyCycle) >> 15);\r
+\r
+\r
+ Pwm_VALIDATE_INITIALIZED();\r
+ Pwm_VALIDATE_CHANNEL(Channel);\r
+\r
+ /* Timer instant for leading edge */\r
+\r
+ /*\r
+ * PWM017: The function Pwm_SetDutyCycle shall update the duty cycle at\r
+ * the end of the period if supported by the implementation and configured\r
+ * with PwmDutycycleUpdatedEndperiod. [ This is achieved in hardware since\r
+ * the A and B registers are double buffered ]\r
+ *\r
+ * PWM014: The function Pwm_SetDutyCycle shall set the output state according\r
+ * to the configured polarity parameter [which is already set from\r
+ * Pwm_InitChannel], when the duty parameter is 0% [=0] or 100% [=0x8000].\r
+ */\r
+ if (DutyCycle == Pwm_100_Procent || DutyCycle == Pwm_0_Procent) {\r
+ EMIOS.CH[Channel].CADR.R = 0;\r
+\r
+ } else {\r
+ EMIOS.CH[Channel].CADR.R = leading_edge_position;\r
+\r
+ }\r
+}\r
+\r
+void Pwm_SetOutputToIdle(Pwm_ChannelType Channel) {\r
+ Pwm_VALIDATE_CHANNEL(Channel);\r
+ Pwm_VALIDATE_INITIALIZED();\r
+\r
+ /* TODO: Make Pwm_SetOutputToIdle sensitive to PwmIdleState (currently uses PwmPolarity) */\r
+ EMIOS.CH[Channel].CADR.R = 0;\r
+}\r
+\r
+/*\r
+ * PWM085: The function Pwm_GetOutputState shall be pre compile configurable\r
+ * ON/OFF by the configuration parameter PwmGetOutputState\r
+ */\r
+#if PWM_GET_OUTPUT_STATE==ON\r
+ /*\r
+ * PWM022: The function Pwm_GetOutputState shall read the internal state\r
+ * of the PWM output signal and return it.\r
+ */\r
+ Pwm_OutputStateType Pwm_GetOutputState(Pwm_ChannelType Channel) {\r
+\r
+\r
+\r
+ // We need to return something, even in presence of errors\r
+ if (Channel >= 16) {\r
+ Pwm_ReportError(PWM_E_PARAM_CHANNEL);\r
+\r
+ /*\r
+ * Accordingly to PWM025, we should return PWM_LOW on failure.\r
+ */\r
+ return PWM_LOW;\r
+\r
+ } else if (Pwm_ModuleState != PWM_STATE_INITIALIZED) {\r
+ Pwm_ReportError(PWM_E_UNINIT);\r
+\r
+ /*\r
+ * Accordingly to PWM025, we should return PWM_LOW on failure.\r
+ */\r
+ return PWM_LOW;\r
+\r
+ }\r
+\r
+ return EMIOS.CH[Channel].CSR.B.UCOUT;\r
+\r
+ }\r
+#endif\r
+\r
+#if PWM_NOTIFICATION_SUPPORTED==ON\r
+ void Pwm_DisableNotification(Pwm_ChannelType Channel) {\r
+ Pwm_VALIDATE_CHANNEL(Channel);\r
+ Pwm_VALIDATE_INITIALIZED();\r
+\r
+ // Disable flags on this channel\r
+ EMIOS.CH[Channel].CCR.B.FEN = 0;\r
+ }\r
+\r
+ void Pwm_EnableNotification(Pwm_ChannelType Channel,\r
+ Pwm_EdgeNotificationType Notification) {\r
+ Pwm_VALIDATE_CHANNEL(Channel);\r
+ Pwm_VALIDATE_INITIALIZED();\r
+\r
+ ChannelRuntimeStruct[Channel].NotificationState = Notification;\r
+\r
+ // Enable flags on this channel\r
+ EMIOS.CH[Channel].CCR.B.FEN = 1;\r
+ }\r
+\r
+ static void Pwm_Isr(void) {\r
+ // Find out which channel that triggered the interrupt\r
+#ifdef CFG_MPC5516\r
+ uint32_t flagmask = EMIOS.GFLAG.R;\r
+#elif defined(CFG_MPC5567)\r
+ uint32_t flagmask = EMIOS.GFR.R;\r
+#endif\r
+\r
+ // There are 24 channels specified in the global flag register, but\r
+ // we only listen to the first 16 as only these support OPWM\r
+ for (Pwm_ChannelType emios_ch = 0; emios_ch < 16; emios_ch++) {\r
+ if (flagmask & (1 << emios_ch)) {\r
+\r
+ if (ChannelRuntimeStruct[emios_ch].NotificationRoutine != NULL && EMIOS.CH[emios_ch].CCR.B.FEN) {\r
+\r
+ Pwm_EdgeNotificationType notification = ChannelRuntimeStruct[emios_ch].NotificationState;\r
+ if (notification == PWM_BOTH_EDGES ||\r
+ notification == EMIOS.CH[emios_ch].CSR.B.UCOUT) {\r
+ ChannelRuntimeStruct[emios_ch].NotificationRoutine();\r
+ }\r
+ }\r
+\r
+ // Clear interrupt\r
+ EMIOS.CH[emios_ch].CSR.B.FLAG = 1;\r
+ }\r
+ }\r
+ }\r
+\r
+#endif /* PWM_NOTIFICATION_SUPPORED == ON */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+
+/* CONFIGURATION NOTES
+ * ------------------------------------------------------------------
+ * The configuration for this module should be supplied by
+ * the users of it ( see 10.4 Configuration concept )
+ *
+ * ALT configuration method:
+ * The method that is used today keeps the configuration in the spi_cfg files.
+ * That is not good..
+ *
+ * Could do something like:
+ * SPI_ADD_CONFIG(Eep_SpiConfig)
+ * in each place a configuration needs to be added to Spi.
+ * The macro adds the pointer to a ptr list( .spi_config section )
+ *
+ * Problems: Sequence/job ID's must be global
+ * --> Hhmm skip this for now, gets VERY complicated
+ *
+ */
+
+/* IMPLEMENTATION NOTES
+ * -----------------------------------------------
+ * - This driver implements SPI_LEVEL_DELIVERED = 2 but with a number
+ * of restrictions. See REQ. below for more information.
+ *
+ * - A sequence may use different CS's if the controller is the same.
+ * ( All jobs that belongs to a sequence MUST share the same controller )
+ *
+ * - The driver uses Spi_DataType as uint8. This means that an 16-bit address have
+ * a length of 2 when setting upASetting async/sync mode is not supported
+ * ( Spi_SetAsyncMode(), SPI188, etc )
+ * - Cancel API is NOT supported
+ * ( SPI_CANCEL_API must be STD_OFF )
+ *
+ * - It's not obvious how to use different modes. My interpretation:
+ *
+ * Sync
+ * Always blocking in Spi_SyncTranmit()
+ *
+ * Async and INTERRUPT
+ *
+ * Async and POLLING
+ * Not supported since
+ *
+ * - Some sequence charts
+ *
+ *
+ * == Sync ==
+ * WriteSeq ISR WriteJob MainFunction_Driving
+ * -------------------------------------------------
+ * | |
+ * ------>
+ * ---------------->
+ * <---------------
+ * ( for each job we will now get an interrupt that write's the next job)
+ * ----->
+ * <-----
+ * ...
+ * <-----
+ *
+ * == Async and INTERRUPT ==
+ *
+ * ------>
+ * ---------------->
+ * <---------------
+ * <-----
+ * ( for each job we will now get an interrupt that write's the next job)
+ * ----->
+ * <-----
+ * ....
+ *
+ *
+ * == Async and POLLING ==
+ * ( Not supported yet )
+ *
+ * ------>
+ * ---------------->
+ * <---------------
+ * <-----
+ * ( for each job in the sequence the sequence must be repeated )
+ * ---------------------------------->
+ * <-----------------
+ * ------>
+ * <-----
+ * ------------------>
+ * <----------------------------------
+ * ...
+ *
+ *
+ */
+
+/* HW INFO
+ * -----------------------------------------------
+ * 4 DSPI modules, A,B,C and D
+ * 7 CTAR's for each module.( data-width, baudrate )
+ *
+ */
+
+/* NOTIFICATION INFORMATION
+ * -----------------------------------------------
+ *
+ * There's a LOT of status and notification in this module....
+ *
+ * Job1 Job2
+ * |---------------|---------------|
+ * JN JN,SN
+ * Status IDLE BUSY BUSY IDLE
+ * HwStatus IDLE BUSY BUSY IDLE
+ * JobResult JOB_OK JOB_PENDING JOB_PENDING JOB_OK,SPI_JOB_FAILED
+ * SeqResult SEQ_OK SEQ_PENDING SEQ_PENDING SEQ_OK,SEQ_FAILED,SEQ_CANCELLED
+ *
+ */
+
+
+#include "Spi.h"
+#include "mpc55xx.h"
+//#include <stdio.h>
+#include "Mcu.h"
+#include "math.h"
+#include "Dma.h"
+#include <assert.h>
+#include <limits.h>
+#include "Det.h"
+#include <stdlib.h>
+
+//#define USE_TRACE 1
+//#define USE_DEBUG 1
+#undef DEBUG_LVL
+#define DEBUG_LVL DEBUG_HIGH
+#include "Trace.h"
+
+#define MODULE_NAME "/driver/Spi"
+
+#define ARRAY_SIZE(_x) (sizeof(_x) / sizeof((_x)[0]))
+
+#define GET_SPI_HW_PTR(_unit) \
+ ((struct DSPI_tag *)(0xFFF90000 + 0x4000*(_unit)))
+
+#define GET_SPI_UNIT_PTR(_unit) &Spi_Unit[_unit]
+
+#define ENABLE_EOQ_INTERRUPT(_spi_hw) _spi_hw->RSER.B.EOQFRE = 1
+#define DISABLE_EOQ_INTERRUPT(_spi_hw) _spi_hw->RSER.B.EOQFRE = 0
+
+/* Development error macros. */
+#if ( SPI_DEV_ERROR_DETECT == STD_ON )
+#define VALIDATE(_exp,_api,_err ) \
+ if( !(_exp) ) { \
+ Det_ReportError(MODULE_ID_SPI,0,_api,_err); \
+ return; \
+ }
+
+#define VALIDATE_W_RV(_exp,_api,_err,_rv ) \
+ if( !(_exp) ) { \
+ Det_ReportError(MODULE_ID_SPI,0,_api,_err); \
+ return (_rv); \
+ }
+#else
+#define VALIDATE(_exp,_api,_err )
+#define VALIDATE_W_RV(_exp,_api,_err,_rv )
+#endif
+
+#define NOT_VALID (-1)
+
+typedef union
+{
+ vuint32_t R;
+ struct {
+ vuint32_t CONT:1;
+ vuint32_t CTAS:3;
+ vuint32_t EOQ:1;
+ vuint32_t CTCNT:1;
+ vuint32_t:4;
+ vuint32_t PCS5:1;
+ vuint32_t PCS4:1;
+ vuint32_t PCS3:1;
+ vuint32_t PCS2:1;
+ vuint32_t PCS1:1;
+ vuint32_t PCS0:1;
+ vuint32_t TXDATA:16;
+ } B;
+}SPICommandType;
+
+typedef SPICommandType Spi_CommandType;
+
+
+
+/* Templates for Rx/Tx DMA structures */
+struct tcd_t Spi_DmaTx =
+{
+
+ .SADDR = 0,
+ .SMOD = 0,
+ .SSIZE = DMA_TRANSFER_SIZE_32BITS,
+ .DMOD = 0,
+ .DSIZE = DMA_TRANSFER_SIZE_32BITS,
+ .SOFF = 4,
+ .NBYTES = 4,
+ .SLAST = 0,
+ .DADDR = 0,
+ .CITERE_LINK = 0,
+ .CITER = 0,
+ .DOFF = 0,
+ .DLAST_SGA = 0,
+ .BITERE_LINK = 0,
+ .BITER = 0,
+ .BWC = 0,
+ .MAJORLINKCH = 0,
+ .DONE = 0,
+ .ACTIVE = 0,
+ .MAJORE_LINK = 0,
+ .E_SG = 0,
+ .D_REQ = 0,
+ .INT_HALF = 0,
+ .INT_MAJ = 0,
+ .START = 0
+};
+
+struct tcd_t Spi_DmaRx =
+{
+ .SADDR = 0,
+ .SMOD = 0,
+ .SSIZE = DMA_TRANSFER_SIZE_32BITS,
+ .DMOD = 0,
+ .DSIZE = DMA_TRANSFER_SIZE_32BITS,
+ .SOFF = 0,
+ .NBYTES = 4,
+ .SLAST = 0,
+ .DADDR = 0,
+ .CITERE_LINK = 0,
+ .CITER = 1,
+ .DOFF = 4,
+ .DLAST_SGA = 0,
+ .BITERE_LINK = 0,
+ .BITER = 1,
+ .BWC = 0,
+ .MAJORLINKCH = 0,
+ .DONE = 0,
+ .ACTIVE = 0,
+ .MAJORE_LINK = 0,
+ .E_SG = 0,
+ .D_REQ = 0,
+ .INT_HALF = 0,
+#if defined(__DMA_INT)
+ .INT_MAJ = 1,
+#else
+ .INT_MAJ = 0,
+#endif
+ .START = 0
+};
+
+#define GET_HW(_channel) ( struct DSPI_tag *)((uint32)&DSPI_A + 0x4000 * _channel )
+
+
+
+typedef struct {
+ // Pointer to source buffer
+ const Spi_DataType *src;
+ // Pointer to destination buffer
+ Spi_DataType *dest;
+ // Number of elements of Spi_DataType in destination buffer
+ Spi_NumberOfDataType length;
+ // Set if the buffer is configured.
+ // Used for sanity check
+ _Bool active;
+} Spi_EbType;
+
+typedef enum {
+ SPI_ASYNC,
+ SPI_SYNC,
+} Spi_CallTypeType;
+
+
+Spi_EbType Spi_Eb[SPI_MAX_CHANNEL];
+
+typedef struct {
+ // this channel is assigned to this CTAR
+ uint8 ctarId;
+} Spi_ChannelInfoType;
+
+Spi_ChannelInfoType Spi_ChannelInfo[SPI_MAX_CHANNEL];
+
+// E2 read = cmd + addr + data = 1 + 2 + 64 ) = 67 ~ 72
+#define SPI_INTERNAL_MTU 72
+
+/**
+ * This structure represents a controller unit
+ */
+typedef struct {
+
+ // Tx DMA channel information
+ Dma_ChannelType dmaTxChannel;
+ struct tcd_t dmaTxTCD;
+
+ // Rx DMA channel information
+ Dma_ChannelType dmaRxChannel;
+ struct tcd_t dmaRxTCD;
+
+ // Pointed to by SADDR of DMA
+ Spi_CommandType txQueue[SPI_INTERNAL_MTU];
+ // Pointed to by DADDR of DMA
+ uint32 rxQueue[SPI_INTERNAL_MTU];
+
+ // current index for data when sending
+ // mostly here for debug purposes( since it could be local )
+ uint32 txCurrIndex;
+
+ // Helper array to assign CTAR's
+ uint32 channelCodes[7];
+
+ // Status for this unit
+ Spi_StatusType status;
+
+ // The current job
+ const Spi_JobConfigType *currJob;
+ // Points array of jobs current
+ const uint32 *currJobIndexPtr;
+ // The Sequence
+ const Spi_SequenceConfigType *currSeqPtr;
+
+ // Used by sync call to check when a job is done
+ // volatile _Bool done;
+
+ // 1 - if the current job is sync. 0 - if not
+ Spi_CallTypeType callType;
+} Spi_UnitType;
+
+typedef struct {
+ Spi_SeqResultType seqResult;
+} Spi_SeqUnitType;
+
+typedef struct {
+ Spi_JobResultType jobResult;
+} Spi_JobUnitType;
+
+typedef struct {
+ // Initially FALSE set to TRUE if Spi_Init() have been called
+ boolean initRun;
+
+ // Pointer to the configuration
+ const Spi_ConfigType *configPtr;
+
+ // Pointer to the external buffers
+ Spi_EbType *extBufPtr;
+
+ Spi_ChannelInfoType *channelInfo;
+
+ // Mask if the HW unit is configured or not
+ uint32 spiHwConfigured;
+
+ Spi_AsyncModeType asyncMode;
+
+ /* This is a bunch of debug counters. */
+ uint32 totalNbrOfTranfers;
+ uint32 totalNbrOfStartedJobs;
+ /* Counters for busy waiting for DSPI and DMA. */
+ uint32 totalNbrOfWaitTXRXS;
+ uint32 totalNbrOfWaitRxDMA;
+
+} Spi_GlobalType;
+
+
+//
+// Instances
+//
+Spi_GlobalType Spi_Global = {
+ .initRun = FALSE,
+ .asyncMode = SPI_INTERRUPT_MODE, // TODO: according to SPI151 it should be polling
+};
+
+Spi_UnitType Spi_Unit[4];
+Spi_SeqUnitType Spi_SeqUnit[SPI_MAX_SEQUENCE];
+Spi_JobUnitType Spi_JobUnit[SPI_MAX_JOB];
+
+static void Spi_Isr( uint32 );
+
+static void Spi_Isr_A( void ) { Spi_Isr(DSPI_CTRL_A); }
+static void Spi_Isr_B( void ) { Spi_Isr(DSPI_CTRL_B); }
+static void Spi_Isr_C( void ) { Spi_Isr(DSPI_CTRL_C); }
+static void Spi_Isr_D( void ) { Spi_Isr(DSPI_CTRL_D); }
+
+typedef struct Spi_IsrInfo {
+ void (*entry)(void);
+ IrqType vector;
+ uint8_t priority;
+ Cpu_t cpu;
+} Spi_IsrInfoType;
+
+
+Spi_IsrInfoType Spi_Isr_Info[] = {
+{
+ .entry = Spi_Isr_A,
+ .vector = DSPI_A_ISR_EOQF,
+ .priority = 1,
+ .cpu = CPU_Z1,
+},
+{
+ .entry = Spi_Isr_B,
+ .vector = DSPI_B_ISR_EOQF,
+ .priority = 1,
+ .cpu = CPU_Z1,
+},
+{
+ .entry = Spi_Isr_C,
+ .vector = DSPI_C_ISR_EOQF,
+ .priority = 1,
+ .cpu = CPU_Z1,
+},
+{
+ .entry = Spi_Isr_D,
+ .vector = DSPI_D_ISR_EOQF,
+ .priority = 1,
+ .cpu = CPU_Z1,
+},
+};
+
+#if 0
+static void Spi_Isr_DMA( void )
+{
+ // Clear interrupt
+ Dma_ClearInterrupt(5);
+}
+#endif
+
+
+static void Spi_JobWrite( Spi_JobType jobIndex );
+
+
+
+static void Spi_SetJobResult( Spi_JobType Job, Spi_JobResultType result )
+{
+ Spi_JobUnit[Job].jobResult = result;
+}
+
+static void Spi_SetHWUnitStatus(Spi_HWUnitType HWUnit,Spi_StatusType status )
+{
+ Spi_Unit[HWUnit].status = status;
+}
+
+/**
+ * Get external Ptr to device from index
+ *
+ * @param deviceType The device index.
+ * @return Ptr to the external device
+ */
+
+static inline const Spi_ExternalDeviceType *Spi_GetExternalDevicePtrFromIndex( Spi_ExternalDeviceTypeType deviceType ) {
+ return (&(Spi_Global.configPtr->SpiExternalDevice[(deviceType)]));
+}
+
+/**
+ * Get configuration job ptr from job index
+ * @param jobIndex the job
+ * @return Ptr to the job configuration
+ */
+static const Spi_JobConfigType *Spi_GetJobPtrFromIndex( Spi_JobType jobIndex ) {
+ return &Spi_Global.configPtr->SpiJobConfig[jobIndex];
+}
+
+/**
+ * Get sequence ptr from sequence index
+ * @param seqIndex the sequence
+ * @return Ptr to the sequence configuration
+ */
+static const Spi_SequenceConfigType *Spi_GetSeqPtrFromIndex( Spi_SequenceType SeqIndex ) {
+ return &Spi_Global.configPtr->SpiSequenceConfig[SeqIndex];
+}
+
+/**
+ * Get unit ptr from unit index
+ * @param unit the unit
+ * @return Ptr to the SPI unit
+ */
+static Spi_UnitType *Spi_GetUnitPtrFromIndex( uint32 unit ) {
+ return &Spi_Unit[unit];
+}
+
+/**
+ * Function to see if two sequences share jobs
+ * @param seq - Seqence 1
+ * @param seq - Seqence 2
+ * @return 0 - if the don't share any jobs
+ * !=0 - if they share jobs
+ */
+
+static boolean Spi_ShareJobs(Spi_SequenceType seq1, Spi_SequenceType seq2 ) {
+ uint32 seqMask1 = 0;
+ uint32 seqMask2 = 0;
+ const uint32 *jobPtr;
+ const Spi_SequenceConfigType *seqConfig;
+
+ // Search for jobs in sequence 1
+ seqConfig = Spi_GetSeqPtrFromIndex(seq1);
+ jobPtr = &seqConfig->JobAssignment[0];
+
+ while( *jobPtr != NOT_VALID ) {
+ assert(*jobPtr<31);
+ seqMask1 |= (1<<*jobPtr);
+ jobPtr++;
+ }
+
+ // Search for jobs in sequence 2
+ seqConfig = Spi_GetSeqPtrFromIndex(seq2);
+ jobPtr = &seqConfig->JobAssignment[0];
+
+ while( *jobPtr != NOT_VALID ) {
+ assert(*jobPtr<31);
+ seqMask2 |= (1<<*jobPtr);
+ jobPtr++;
+ }
+
+ return (seqMask1 & seqMask2 );
+}
+
+//-------------------------------------------------------------------
+
+/**
+ * Sets a result for a sequence
+ *
+ * @param Sequence The sequence to set the result for
+ * @param result The result to set.
+ */
+static void Spi_SetSequenceResult(Spi_SequenceType Sequence, Spi_SeqResultType result ) {
+ Spi_SeqUnit[Sequence].seqResult = result;
+}
+
+//-------------------------------------------------------------------
+
+
+/**
+ * Gets the next job to do
+ *
+ * @param spiUnit The SPI unit
+ * @return The job ID. -1 if no more jobs
+ */
+static uint32 Spi_GetNextJob(Spi_UnitType *spiUnit ) {
+ spiUnit->currJobIndexPtr++;
+ return *(spiUnit->currJobIndexPtr);
+}
+//-------------------------------------------------------------------
+
+/**
+ * Schedules next job to do( calls Spi_jobWrite() or not )
+ *
+ * @param spiUnit The SPI unit
+ */
+static int Spi_WriteNextJob( Spi_UnitType *spiUnit ) {
+ uint32 nextJob;
+ // Re-cap.
+ // - Jobs have the controller
+ // - Sequences can we interruptible between jobs.
+ // But
+ // According to SPI086 you can't share a job with a sequence that
+ // is in SPI_SEQ_PENDING ( that happens first thing at Spi_AsyncTranmit() )
+ //
+ // So, I no clue what to use the priority thing for :(
+
+ nextJob = Spi_GetNextJob(spiUnit);
+ if( nextJob == NOT_VALID) {
+ return NOT_VALID;
+
+ } else {
+ // Schedule next job
+ Spi_JobWrite(nextJob);
+ }
+ return 0;
+}
+
+//-------------------------------------------------------------------
+
+/**
+ * Function to handle things after a transmit on the SPI is finished.
+ * It copies data from it't local buffers to the buffers pointer to
+ * by the external buffers
+ *
+ * @param spiUnit Ptr to a SPI unit
+ */
+
+static int Spi_PostTransmit( Spi_UnitType *spiUnit ) {
+ _Bool printedSomeThing = 0;
+
+ /* Stop the channels */
+ Dma_StopChannel (spiUnit->dmaTxChannel);
+ Dma_StopChannel (spiUnit->dmaRxChannel);
+
+ ramlog_str("PostTransmit Job: ");
+ ramlog_dec(spiUnit->currJob->SpiJobId);
+ ramlog_str("\n");
+
+ /* Copy data from RX queue to the external buffer( if a<uny ) */
+ {
+ int j=0;
+ int currIndex =0;
+ int channelIndex;
+ const Spi_ChannelConfigType *chConfig;
+ Spi_EbType *extChBuff;
+ int gotTx;
+ int sentTx;
+
+ // Check that we got the number of bytes we sent
+ sentTx = spiUnit->txCurrIndex+1;
+ gotTx = (Dma_GetTcd(spiUnit->dmaRxChannel)->DADDR - (uint32)&spiUnit->rxQueue[0])/sizeof(uint32);
+
+ if( sentTx != gotTx ) {
+ // Something failed
+ DEBUG(DEBUG_LOW,"%s: Expected %d bytes. Got %d bytes\n ",MODULE_NAME,sentTx, gotTx );
+ return (-1);
+ } else {
+ ramlog_str("Rx ");
+ ramlog_dec(gotTx);
+ ramlog_str(" Bytes\n");
+ DEBUG(DEBUG_LOW,"%s: Got %d bytes\n",MODULE_NAME,gotTx);
+ }
+
+
+ // Find the channels for this job
+ while( (channelIndex = spiUnit->currJob->ChannelAssignment[j++]) != NOT_VALID)
+ {
+ chConfig = &Spi_Global.configPtr->SpiChannelConfig[channelIndex];
+
+ /* Check configuration error */
+#if ( SPI_CHANNEL_BUFFERS_ALLOWED == 1 )
+ assert( chConfig->SpiChannelType == SPI_EB );
+#endif
+
+ // Send the channels that are setup with external buffers
+ // Get the external buffer for this channel
+ extChBuff = &Spi_Global.extBufPtr[channelIndex];
+ if( extChBuff->dest != NULL ) {
+ // Note! No support for >8 "data"
+ for(int k=0;k<extChBuff->length;k++) {
+ extChBuff->dest[k] = spiUnit->rxQueue[currIndex++];
+ DEBUG(DEBUG_LOW," %02x ",extChBuff->dest[k]);
+ printedSomeThing = 1;
+ }
+
+ } else {
+ if( chConfig->SpiDataWidth > 8 ) {
+ currIndex += (extChBuff->length/2);
+ } else {
+ currIndex += extChBuff->length;
+ }
+ }
+ }
+ if( printedSomeThing )
+ DEBUG(DEBUG_LOW,"\n");
+ }
+
+ return 0;
+}
+
+//-------------------------------------------------------------------
+
+/**
+ * ISR for End of Queue interrupt
+ *
+ * @param unit The HW unit it happend on
+ */
+static void Spi_Isr( uint32 unit ) {
+ struct DSPI_tag *spiHw = GET_SPI_HW_PTR(unit);
+ Spi_UnitType *spiUnit = GET_SPI_UNIT_PTR(unit);
+ int rv;
+
+ ramlog_str("Spi_Isr\n");
+
+ // This may seem pretty stupid to wait for the controller
+ // to shutdown here, but there seems to be no other way to do this.
+ // Reasons:
+ // - Waiting for DMA rx/tx hits earlier than EOQ.
+ // - Other interrupts from SPI all hit earlier than EOQ.
+
+ // TODO: We could implement a timeout here and fail the job
+ // if this never happens.
+
+ // This is the busy wait when called from a non-interrupt context
+ while (spiHw->SR.B.TXRXS) {
+ Spi_Global.totalNbrOfWaitTXRXS++;
+ }
+
+ // To be 100% sure also wait for the DMA transfer to complete.
+ while(!Dma_ChannelDone (Spi_Global.configPtr->SpiHwConfig[unit].RxDmaChannel))
+ {
+ Spi_Global.totalNbrOfWaitRxDMA++;
+ }
+
+ /* Halt DSPI unit until we are ready for next transfer. */
+ spiHw->MCR.B.HALT = 1;
+ spiHw->SR.B.EOQF = 1;
+
+ Spi_Global.totalNbrOfTranfers++;
+
+ // Disable EOQ interrupts
+ // NOTE!
+ // This does NOT clear the interrupt request.
+ // That can only be done by clearing( setting ) the EOQ
+ // bit.. but that also triggers a new transfer.
+ //
+ // ALT
+ // A possibility could be to use the HALT bit instead of
+ // using this trick, but hey, this works
+
+ DISABLE_EOQ_INTERRUPT(spiHw);
+
+ // Update external buffers
+ rv = Spi_PostTransmit(spiUnit);
+
+ // Call notification end
+ if(spiUnit->currJob->SpiJobEndNotification != NULL ) {
+ spiUnit->currJob->SpiJobEndNotification();
+ }
+
+ if( rv == (-1) )
+ {
+ // Fail both job and sequence
+ Spi_SetHWUnitStatus(unit,SPI_IDLE);
+ Spi_SetJobResult(spiUnit->currJob->SpiJobId,SPI_JOB_FAILED);
+ Spi_SetSequenceResult(spiUnit->currSeqPtr->SpiSequenceId,SPI_SEQ_FAILED);
+ }
+ else
+ {
+
+ // The job is at least done..
+ Spi_SetJobResult(spiUnit->currJob->SpiJobId,SPI_JOB_OK);
+
+ // WriteNextJob should
+ // 1. Update the JobResult to SPI_JOB_OK
+ // 2. Update the HWUnit status to IDLE
+
+ if( Spi_WriteNextJob(spiUnit) == (-1))
+ {
+ // No more jobs, so set HwUnit and sequence IDLE/OK also.
+ Spi_SetHWUnitStatus(unit,SPI_IDLE);
+ Spi_SetSequenceResult(spiUnit->currSeqPtr->SpiSequenceId, SPI_SEQ_OK);
+
+ if( spiUnit->currSeqPtr->SpiSeqEndNotification != NULL ) {
+ spiUnit->currSeqPtr->SpiSeqEndNotification();
+ }
+
+ Spi_SetHWUnitStatus(unit,SPI_IDLE);
+
+ /* We are now ready for next transfer. */
+ spiHw->MCR.B.HALT = 1;
+
+ ramlog_str("NO more jobs\n");
+ } else {
+ ramlog_str("More jobs\n");
+ }
+ }
+
+ ramlog_str("Spi_Isr END\n");
+}
+
+//-------------------------------------------------------------------
+
+Std_ReturnType Spi_WriteIB( Spi_ChannelType Channel, const Spi_DataType *DataBufferPtr ){
+ VALIDATE_W_RV( ( TRUE == Spi_Global.initRun ), SPI_WRITEIB_SERVICE_ID, SPI_E_UNINIT, E_NOT_OK );
+ VALIDATE_W_RV( ( Channel<SPI_MAX_CHANNEL ), SPI_WRITEIB_SERVICE_ID, SPI_E_PARAM_CHANNEL, E_NOT_OK );
+ VALIDATE_W_RV( ( DataBufferPtr != NULL ), SPI_WRITEIB_SERVICE_ID, SPI_E_PARAM_CHANNEL, E_NOT_OK );
+ VALIDATE_W_RV( ( SPI_IB==Spi_Global.configPtr->SpiChannelConfig[Channel].SpiChannelType ),\
+ SPI_WRITEIB_SERVICE_ID, SPI_E_PARAM_CHANNEL, E_NOT_OK );
+ Std_ReturnType rv = E_NOT_OK;
+ return rv;
+}
+
+/* Clock tables */
+uint32 clk_table_asc[] = {2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536 };
+uint32 clk_table_cssck[] = {2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536 };
+uint16 clk_table_br[] = {2,4,6,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768 };
+uint8 clk_table_pasc[] = { 1,3,5,7 };
+uint8 clk_table_pcssck[] = { 1,3,5,7 };
+uint8 clk_table_pbr[] = { 2,3,5,7 };
+
+/**
+ * Function to setup CTAR's from configuration
+ * @param spiHw - Pointer to HW SPI device
+ * @param extDev - Pointer to external device configuration
+ * @param ctar_unit - The ctar unit number to setup
+ * @param width - The width in bits of the data to send with the CTAR
+ */
+static void Spi_SetupCTAR( Spi_HWUnitType unit,
+ const Spi_ExternalDeviceType *extDev,
+ Spi_ChannelType ctar_unit,
+ uint8 width )
+{
+ uint32 clock;
+ uint32 pre_br;
+ int i;
+ int j;
+ uint32 tmp;
+
+ struct DSPI_tag *spiHw = GET_SPI_HW_PTR(unit);
+ /* BAUDRATE CALCULATION
+ * -----------------------------
+ * Baudrate = Fsys/ PBR * ( 1+ DBR) / BR
+ * PBR range: 2 to 7
+ * DBR range: 0 to 1
+ * BR : 2 to 32768
+ *
+ * To make this easy set DBR = 0 and PBR=2
+ * --> BR=Fsys/(Baudrate.* 2 )
+ *
+ */
+ clock = McuE_GetPeripheralClock(Spi_Global.configPtr->SpiHwConfig[unit].PeripheralClock);
+ DEBUG(DEBUG_MEDIUM,"%s: Peripheral clock at %d Mhz\n",MODULE_NAME,clock);
+
+ DEBUG(DEBUG_MEDIUM,"%s: Want to run at %d Mhz\n",MODULE_NAME,extDev->SpiBaudrate);
+
+ spiHw->CTAR[ctar_unit].B.DBR = 0;
+ spiHw->CTAR[ctar_unit].B.PBR = 0; // 2
+ pre_br = clock/(extDev->SpiBaudrate*clk_table_pbr[spiHw->CTAR[ctar_unit].B.PBR]);
+
+ // find closest lesser
+ for(i=0;i<sizeof(clk_table_br)/sizeof(clk_table_br[0]);i++) {
+ if( clk_table_br[i] >= pre_br ) {
+ break;
+ }
+ }
+
+ assert(i>=0);
+ // Set it
+ spiHw->CTAR[ctar_unit].B.BR = i;
+
+ DEBUG(DEBUG_LOW,"%s: CLK %d Mhz\n",MODULE_NAME,
+ clock / clk_table_pbr[spiHw->CTAR[ctar_unit].B.PBR] *
+ ( 1 + spiHw->CTAR[ctar_unit].B.DBR)/clk_table_br[spiHw->CTAR[ctar_unit].B.BR]);
+
+
+ /* For other timings autosar only specifies SpiTimeClk2Cs == "After SCK delay"
+ * in Freescale language. The dumb thing is that this should be a relative time
+ * to the clock. Not fixed.
+ * Autosar specifies 0.0--100.0 ms(float)
+ * Our intepretation is 0--1000000 ns (uint32)
+ *
+ * AFTER SCK DELAY:
+ * -----------------------------
+ * Tasc = 1/Fsys * PASC * ASC [s]
+ *
+ * Assume the Tasc get's here in ns( typical range is ~10ns )
+ */
+
+ // Calc the PASC * ASC value...
+ tmp = extDev->SpiTimeClk2Cs * (clock / 1000000 );
+
+ // Nothing fancy here...
+ {
+ int best_i=0;
+ int best_j=0;
+ int b_value = INT_MAX;
+ int tt;
+
+
+ // Find the best match of Prescaler and Scaler value
+ for(i=0;i<ARRAY_SIZE(clk_table_pasc);i++) {
+ for(j=0;j<ARRAY_SIZE(clk_table_asc);j++) {
+ tt = abs((int)clk_table_pasc[i]*clk_table_asc[j]*1000 - tmp);
+ if( tt < b_value ) {
+ best_i = i; best_j = j; b_value = tt;
+ }
+ }
+ }
+
+ /* After SCK delay. */
+ spiHw->CTAR[ctar_unit].B.PASC = best_i;
+ spiHw->CTAR[ctar_unit].B.ASC = best_j;
+ }
+
+
+ DEBUG(DEBUG_MEDIUM,"%s: Timing: Tasc %d ns\n",MODULE_NAME,
+ clk_table_pasc[spiHw->CTAR[ctar_unit].B.PASC] *
+ clk_table_asc[spiHw->CTAR[ctar_unit].B.ASC] * 1000/ (clock/1000000) );
+
+
+
+ /* The PCS to SCK delay is the delay between the assertion of PCS and
+ * the first edge the SCK.
+ *
+ * PCS TO SCK DELAY:
+ * -----------------------------
+ * Tcsc = 1/Fsys * PCSSCK * CSSCK [s]
+ */
+
+ // Calc the PCSSCK * CSSCK value...
+ tmp = extDev->SpiTimeCs2Clk * (clock / 1000000 );
+
+ // Nothing fancy here...
+ {
+ int best_i=0;
+ int best_j=0;
+ int b_value = INT_MAX;
+ int tt;
+
+ // Find the best match of Prescaler and Scaler value
+ for(i=0;i<ARRAY_SIZE(clk_table_pcssck);i++) {
+ for(j=0;j<ARRAY_SIZE(clk_table_cssck);j++) {
+ tt = abs((int)clk_table_pcssck[i]*clk_table_cssck[j]*1000 - tmp);
+ if( tt < b_value ) {
+ best_i = i; best_j = j; b_value = tt;
+ }
+ }
+ }
+
+ /* PCS to SCK delay */
+ spiHw->CTAR[ctar_unit].B.PCSSCK = best_i;
+ spiHw->CTAR[ctar_unit].B.CSSCK = best_j;
+ }
+
+
+ DEBUG(DEBUG_MEDIUM,"%s: Timing: Tcsc %d ns\n",MODULE_NAME,
+ clk_table_pcssck[spiHw->CTAR[ctar_unit].B.PCSSCK] *
+ clk_table_cssck[spiHw->CTAR[ctar_unit].B.CSSCK]*1000/(clock/1000000));
+
+
+ /* Time that PCS is high between transfers */
+ spiHw->CTAR[ctar_unit].B.PDT = 2;
+ spiHw->CTAR[ctar_unit].B.DT = 2;
+
+ DEBUG(DEBUG_MEDIUM,"%s: Timing: Tdt %d ns\n",MODULE_NAME,
+ clk_table_pasc[spiHw->CTAR[ctar_unit].B.PDT] *
+ clk_table_asc[spiHw->CTAR[ctar_unit].B.DT]*1000/(clock/1000000));
+
+ /* Data is transferred MSB first */
+ spiHw->CTAR[ctar_unit].B.LSBFE = 0;
+
+ /* Set mode */
+ spiHw->CTAR[ctar_unit].B.FMSZ = width - 1;
+ spiHw->CTAR[ctar_unit].B.CPHA = ( extDev->SpiDataShiftEdge == SPI_EDGE_LEADING ) ? 0 : 1;
+ spiHw->CTAR[ctar_unit].B.CPOL = ( extDev->SpiCsPolarity == STD_LOW ) ? 0 : 1;
+
+ // This the ACTIVE polarity. Freescale have inactive polarity
+ if( extDev->SpiCsPolarity == STD_HIGH ) {
+ spiHw->MCR.R &= ~(1 <<(16+extDev->SpiCsIdentifier));
+ } else {
+ spiHw->MCR.R |= (1 <<(16+extDev->SpiCsIdentifier));
+ }
+}
+
+//-------------------------------------------------------------------
+
+static void Spi_InitController( uint32 unit ) {
+ struct DSPI_tag *spiHw = GET_SPI_HW_PTR(unit);
+ Spi_UnitType *spiUnit = GET_SPI_UNIT_PTR(unit);
+
+ /* Module configuration register. */
+ /* Master mode. */
+ spiHw->MCR.B.MSTR = 1;
+ /* No freeze. Run SPI when debugger is stopped. */
+ spiHw->MCR.B.FRZ = 0;
+ /* PSC5 as regular CS. */
+ spiHw->MCR.B.PCSSE = 0;
+
+ /* Enable FIFO's. */
+ spiHw->MCR.B.DIS_RXF = 1;
+ spiHw->MCR.B.DIS_TXF = 1;
+
+ /* Set all active low. */
+ spiHw->MCR.B.PCSIS0 = 1;
+ spiHw->MCR.B.PCSIS1 = 1;
+ spiHw->MCR.B.PCSIS2 = 1;
+ spiHw->MCR.B.PCSIS3 = 1;
+ spiHw->MCR.B.PCSIS4 = 1;
+ spiHw->MCR.B.PCSIS5 = 1;
+
+ /* DMA TX FIFO fill. */
+ spiHw->RSER.B.TFFFRE = 1;
+ spiHw->RSER.B.TFFFDIRS = 1;
+
+ /* DMA RX FIFO drain. */
+ spiHw->RSER.B.RFDFRE = 1;
+ spiHw->RSER.B.RFDFDIRS = 1;
+
+ // Setup CTAR's channel codes..
+ for(int i=0;i<7;i++) {
+ spiUnit->channelCodes[i] = NOT_VALID;
+ }
+
+ /* Force to stopped state. */
+ spiHw->MCR.B.HALT = 1;
+
+ spiHw->SR.B.EOQF = 1;
+
+ /* Enable clocks. */
+ spiHw->MCR.B.MDIS = 0;
+
+#if defined(__DMA_INT)
+ IntCtrl_InstallVector(Spi_Isr_DMA, 16 , 1, CPU_Z1);
+#endif
+
+ // Install EOFQ int..
+ IntCtrl_InstallVector(Spi_Isr_Info[unit].entry, Spi_Isr_Info[unit].vector,
+ Spi_Global.configPtr->SpiHwConfig[unit].IsrPriority, Spi_Isr_Info[unit].cpu);
+}
+
+//-------------------------------------------------------------------
+
+static void Spi_DmaSetup(uint32 unit ) {
+
+ struct tcd_t *tcd;
+
+ tcd = &Spi_Unit[unit].dmaTxTCD;
+ *tcd = Spi_DmaTx;
+ tcd->SADDR = (uint32)Spi_Unit[unit].txQueue;
+ tcd->DADDR = (uint32)&(GET_SPI_HW_PTR(unit)->PUSHR.R);
+
+ Dma_StopChannel(Spi_Unit[unit].dmaTxChannel);
+ Dma_CheckConfig();
+
+ // CITER and BITER set when we send
+ tcd = &Spi_Unit[unit].dmaRxTCD;
+ *tcd = Spi_DmaRx;
+ tcd->SADDR = (uint32)&(GET_SPI_HW_PTR(unit)->POPR.R);
+ tcd->DADDR = (uint32)Spi_Unit[unit].rxQueue;
+
+ Dma_StopChannel(Spi_Unit[unit].dmaRxChannel);
+ Dma_CheckConfig();
+
+}
+
+//-------------------------------------------------------------------
+
+void Spi_Init( const Spi_ConfigType *ConfigPtr ) {
+
+ const Spi_JobConfigType *jobConfig2;
+ Spi_Global.configPtr = ConfigPtr;
+ Spi_Global.extBufPtr = Spi_Eb;
+// Spi_Global.currSeq = NOT_VALID;
+
+ // Set all sequence results to OK
+ for(int i=0;i<SPI_MAX_SEQUENCE;i++) {
+ Spi_SetSequenceResult(i,SPI_SEQ_OK);
+ }
+
+ // Figure out what HW controllers that are used
+ for(int j=0;j<Spi_GetJobCnt();j++){
+ jobConfig2 = &Spi_Global.configPtr->SpiJobConfig[j];
+ Spi_Global.spiHwConfigured |= (1<<jobConfig2->SpiHwUnit);
+ }
+
+
+ // Initialize controllers used
+ {
+ uint32 confMask;
+ uint8 confNr;
+
+ confMask = Spi_Global.spiHwConfigured;
+
+ for (; confMask; confMask&=~(1<<confNr)) {
+ confNr = ilog2(confMask);
+ DEBUG(DEBUG_LOW,"%s:Configured HW controller %d\n",MODULE_NAME,confNr);
+ Spi_InitController(confNr);
+ Spi_SetHWUnitStatus(confNr,SPI_IDLE);
+
+ // DMA init...
+ //
+
+ /* Make sure that this channel shall be used. */
+ assert (ConfigPtr->SpiHwConfig[confNr].Activated);
+
+ Spi_Unit[confNr].dmaTxChannel = ConfigPtr->SpiHwConfig[confNr].TxDmaChannel;
+ Spi_Unit[confNr].dmaRxChannel = ConfigPtr->SpiHwConfig[confNr].RxDmaChannel;
+ Spi_DmaSetup(confNr);
+
+ }
+ }
+
+
+ /* Setup CTARS, configuration */
+ {
+ Spi_UnitType *spiUnit;
+
+ int j = 0;
+ int k;
+ int l;
+ uint32 channelCode;
+ int channelIndex;
+
+ const Spi_JobConfigType *jobConfig;
+ const Spi_ChannelConfigType *chConfig;
+
+ for(j=0;j<Spi_GetJobCnt();j++){
+ jobConfig = &Spi_Global.configPtr->SpiJobConfig[j];
+ spiUnit = GET_SPI_UNIT_PTR( jobConfig->SpiHwUnit );
+
+ // Also find the controllers used while we are at it
+ Spi_Global.spiHwConfigured |= (1<<jobConfig->SpiHwUnit);
+
+ // ..and set the job status
+ Spi_SetJobResult(j,SPI_JOB_OK);
+
+ l=0;
+ // Go through all the jobs and it's channels to setup CTAS
+ // A job have the same physical controller ( SpiHwUnit )
+ while( (channelIndex = jobConfig->ChannelAssignment[l++]) != NOT_VALID) {
+ chConfig = &Spi_Global.configPtr->SpiChannelConfig[channelIndex];
+
+ // Form a channel code from
+ // <external_device_id><channel width>
+ channelCode = ((jobConfig->DeviceAssignment<<8) + chConfig->SpiDataWidth);
+
+ for(k=0;k<7;k++) {
+ if( spiUnit->channelCodes[k] == channelCode ) {
+ Spi_ChannelInfo[channelIndex].ctarId = k;
+ DEBUG(DEBUG_LOW,"%s: Channel %d re-uses CTAR %d@%d . device=%d,width=%d\n",MODULE_NAME,channelIndex,k,jobConfig->SpiHwUnit,jobConfig->DeviceAssignment,chConfig->SpiDataWidth);
+ // already in list, break
+ break;
+ }
+
+ if( spiUnit->channelCodes[k] == NOT_VALID) {
+ // Add to list
+ spiUnit->channelCodes[k] = channelCode;
+ // Assign the CTAR index to channel info..
+ DEBUG(DEBUG_LOW,"%s: Channel %d uses CTAR %d@%d . device=%d,width=%d\n",MODULE_NAME,channelIndex,k,jobConfig->SpiHwUnit,jobConfig->DeviceAssignment,chConfig->SpiDataWidth);
+
+ Spi_SetupCTAR( jobConfig->SpiHwUnit,
+ Spi_GetExternalDevicePtrFromIndex( jobConfig->DeviceAssignment ),
+ k,
+ chConfig->SpiDataWidth );
+
+ Spi_ChannelInfo[channelIndex].ctarId = k;
+ break;
+ }
+ }
+ }
+ }
+ }
+
+ Spi_Global.initRun = TRUE;
+}
+
+//-------------------------------------------------------------------
+
+Std_ReturnType Spi_DeInit( void ){
+ struct DSPI_tag *spiHw;
+ uint32 confMask;
+ uint8 confNr;
+
+ VALIDATE_W_RV( ( TRUE == Spi_Global.initRun ), SPI_DEINIT_SERVICE_ID, SPI_E_UNINIT, E_NOT_OK );
+ if( Spi_GetStatus()==SPI_BUSY )
+ return E_NOT_OK;
+
+ // Disable the HW modules ( SPI021 )
+ confMask = Spi_Global.spiHwConfigured;
+
+ // Disable the SPI hw
+ for (; confMask; confMask&=~(1<<confNr)) {
+ confNr = ilog2(confMask);
+ spiHw = GET_SPI_HW_PTR(confNr);
+ // Disable the hardware..
+ spiHw->MCR.B.MDIS = 1;
+
+ Spi_InitController(confNr);
+ Spi_SetHWUnitStatus(confNr,SPI_IDLE);
+ }
+
+ // SPI022
+ Spi_Global.configPtr = NULL;
+ Spi_Global.initRun = FALSE;
+
+
+ return E_OK;
+}
+
+//-------------------------------------------------------------------
+
+/**
+ * Write a job to the SPI bus
+ *
+ * @param jobIndex The job to write to the SPI bus
+ */
+static void Spi_JobWrite( Spi_JobType jobIndex ) {
+
+ const Spi_JobConfigType *jobConfig;
+ const Spi_ChannelConfigType *chConfig;
+ Spi_EbType *extChBuff;
+ Spi_CommandType cmd;
+ Spi_UnitType *spiUnit;
+
+ int k = 0;
+ int j = 0;
+ int channelIndex;
+ struct DSPI_tag *spiHw;
+
+ cmd.R = 0;
+
+ // Grab some things that may be of use..
+ jobConfig = &Spi_Global.configPtr->SpiJobConfig[jobIndex];
+ spiUnit = GET_SPI_UNIT_PTR( jobConfig->SpiHwUnit );
+
+ // Be really sure that we are done with previous send
+ spiHw = GET_SPI_HW_PTR(jobConfig->SpiHwUnit);
+
+ spiUnit->txCurrIndex = 0;
+ spiUnit->currJob = jobConfig;
+
+ Spi_SetHWUnitStatus(jobConfig->SpiHwUnit,SPI_BUSY);
+ Spi_SetJobResult(jobIndex,SPI_JOB_PENDING);
+
+ j = 0;
+
+ // Find the channels for this job
+ while( (channelIndex = jobConfig->ChannelAssignment[j++]) != NOT_VALID)
+ {
+ chConfig = &Spi_Global.configPtr->SpiChannelConfig[channelIndex];
+
+ /* Check configuration error */
+#if ( SPI_CHANNEL_BUFFERS_ALLOWED == 1 )
+ assert( chConfig->SpiChannelType == SPI_EB );
+#endif
+
+ // Send the channels that are setup with external buffers
+ // Get the external buffer for this channel
+ extChBuff = &Spi_Global.extBufPtr[channelIndex];
+
+ if( extChBuff->active == 0 ) {
+ dbg_printf("Err:External buffer %d@job %d not setup\n",channelIndex,jobIndex);
+ assert(0);
+ }
+
+ // Start to fill the SPI queue for the DMA:
+ for(k=0;k<extChBuff->length;k++) {
+ uint32 csId = Spi_Global.configPtr->SpiExternalDevice[jobConfig->DeviceAssignment].SpiCsIdentifier;
+ // Build cmd
+ cmd.B.CONT = 1; // Channels should keep CS active
+ // ( A job must assert CS continuously)
+ cmd.R |= (1 <<(16+csId)); // Set PCS
+ cmd.B.EOQ = 0;
+ cmd.B.CTAS = Spi_ChannelInfo[channelIndex].ctarId;
+ if( extChBuff->src != NULL ) {
+ if( chConfig->SpiDataWidth > 8 ) {
+ cmd.B.TXDATA = (extChBuff->src[k]<<8)+(extChBuff->src[k+1]&0xff);
+ k++;
+ } else {
+ cmd.B.TXDATA = extChBuff->src[k];
+ }
+ } else {
+ cmd.B.TXDATA = chConfig->SpiDefaultData;
+ }
+
+ // Just keep on filling the tx queue
+ spiUnit->txQueue[spiUnit->txCurrIndex++].R = cmd.R;
+ }
+ } /*while( channelIndex == */
+
+ // send last part
+ cmd.B.CONT = 0; // CS high
+ cmd.B.EOQ = 1; // last in queue
+ spiUnit->txQueue[--spiUnit->txCurrIndex].R = cmd.R;
+
+ // Set the length of the data to send
+ spiUnit->dmaTxTCD.CITER = spiUnit->txCurrIndex + 1;
+ spiUnit->dmaTxTCD.BITER = spiUnit->txCurrIndex + 1;
+
+ Spi_Global.totalNbrOfStartedJobs++;
+
+ ramlog_str("Job: ");
+ ramlog_dec(jobIndex);
+ ramlog_str(" Cnt: ");
+ ramlog_dec(spiUnit->txCurrIndex+1);
+ ramlog_str("\n");
+
+ DEBUG(DEBUG_LOW,"%s:Tx Job:%d cnt:%d first data:%04x\n",MODULE_NAME,jobIndex,spiUnit->txCurrIndex+1,spiUnit->txQueue[0].B.TXDATA);
+
+ {
+ uint32 unit = jobConfig->SpiHwUnit;
+
+ Spi_UnitType *spiUnit = GET_SPI_UNIT_PTR(unit);
+ struct DSPI_tag *spiHw = GET_SPI_HW_PTR(unit);
+
+
+ Dma_ConfigureChannel ((struct tcd_t *)&spiUnit->dmaTxTCD, spiUnit->dmaTxChannel);
+ Dma_ConfigureChannel ((struct tcd_t *)&spiUnit->dmaRxTCD, spiUnit->dmaRxChannel );
+ /* Flush TX/Rx FIFO. Ref. man. 23.5.1 step 8 */
+ spiHw->MCR.B.CLR_RXF = 1;
+ spiHw->MCR.B.CLR_TXF = 1;
+
+ Dma_StartChannel (spiUnit->dmaRxChannel);
+ Dma_StartChannel (spiUnit->dmaTxChannel);
+
+ // Step 9. Clear TCNT
+ spiHw->TCR.B.TCNT = 0;
+
+ if( ( Spi_Global.asyncMode == SPI_INTERRUPT_MODE ) &&
+ ( spiUnit->callType == SPI_ASYNC ) )
+ {
+ ENABLE_EOQ_INTERRUPT(spiHw);
+ } else {
+ DISABLE_EOQ_INTERRUPT(spiHw);
+ }
+
+ /* This will trig a new transfer. Ref. man. 23.5.1 step 11 */
+ spiHw->SR.B.EOQF = 1;
+ spiHw->MCR.B.HALT = 0;
+
+ // Since it's not obvious on how to tell when a SPI sequence
+ // is sent, keep things below to what things have been tested.
+ #if 0
+ /* Wait for transfer to complete. */
+ while (!spiHw->SR.B.EOQF) { arrggg++; }
+ while (spiHw->SR.B.TXRXS) { arrggg2++;}
+ while( EDMA.TCD[spiUnit->dmaRxChannel].ACTIVE ) {;}
+
+ #endif
+
+ }
+
+}
+
+void Spi_PrintSeqInfo(const Spi_SequenceConfigType *seqConfigPtr ) {
+ int i=0;
+ uint32 job;
+ DEBUG(DEBUG_HIGH,"%s: Seq: %d:",MODULE_NAME,seqConfigPtr->SpiSequenceId);
+
+ while( (job = seqConfigPtr->JobAssignment[i]) != (-1) ) {
+ DEBUG(DEBUG_HIGH,"%d ",job);
+ i++;
+ }
+ DEBUG(DEBUG_HIGH,"\n");
+}
+
+
+/**
+ * Write a sequence to the SPI bus
+ *
+ * @param seqIndex The sequence
+ * @param sync 1 - make the call sync. 0 - make the call async
+ */
+static void Spi_SeqWrite( Spi_SequenceType seqIndex, Spi_CallTypeType sync ) {
+
+ const Spi_SequenceConfigType *seqConfig;
+ const Spi_JobConfigType *jobConfig;
+ Spi_UnitType *spiUnit;
+ Spi_JobType jobIndex;
+
+
+ seqConfig = Spi_GetSeqPtrFromIndex(seqIndex);
+ jobIndex = seqConfig->JobAssignment[0];
+ jobConfig = Spi_GetJobPtrFromIndex(jobIndex);
+
+ spiUnit = Spi_GetUnitPtrFromIndex(jobConfig->SpiHwUnit);
+ // Fill in the required fields for job and sequence..
+ spiUnit->currJobIndexPtr = &seqConfig->JobAssignment[0];
+ spiUnit->callType = sync;
+ spiUnit->currSeqPtr = seqConfig;
+
+ Spi_SetSequenceResult(seqIndex, SPI_SEQ_PENDING);
+
+ // Setup interrupt for end of queue
+ if( ( Spi_Global.asyncMode == SPI_INTERRUPT_MODE ) &&
+ ( spiUnit->callType == SPI_ASYNC ) )
+ {
+ DEBUG(DEBUG_MEDIUM,"%s: async/interrupt mode\n",MODULE_NAME);
+ } else {
+ DEBUG(DEBUG_MEDIUM,"%s: sync/polled mode\n",MODULE_NAME);
+ }
+
+#if defined(USE_DEBUG) && ( DEBUG_LVL <= DEBUG_HIGH )
+ Spi_PrintSeqInfo( seqConfig );
+#endif
+
+ Spi_JobWrite(jobIndex);
+
+ if( spiUnit->callType == SPI_SYNC ) {
+ while( Spi_GetSequenceResult(seqIndex) == SPI_SEQ_PENDING ) {
+ Spi_Isr(jobConfig->SpiHwUnit);
+ }
+ }
+
+}
+
+//-------------------------------------------------------------------
+static _Bool Spi_AnyPendingJobs(Spi_SequenceType Sequence ) {
+
+ // Check that we don't share any jobs with another sequence that is SPI_SEQ_PENDING
+ for(int i=0;i<SPI_MAX_SEQUENCE;i++) {
+ if( i==Sequence ) {
+ continue;
+ }
+
+ if( Spi_GetSequenceResult(i) == SPI_SEQ_PENDING ) {
+ // We have found a pending sequence... check that we don't share any jobs
+ // with that sequence, SPI086
+ if( Spi_ShareJobs(Sequence,i) ) {
+ return 1;
+ }
+ }
+ }
+
+ return 0;
+}
+
+//-------------------------------------------------------------------
+
+Std_ReturnType Spi_SyncTransmit( Spi_SequenceType Sequence ) {
+
+ VALIDATE_W_RV( ( TRUE == Spi_Global.initRun ), SPI_SYNCTRANSMIT_SERVICE_ID, SPI_E_UNINIT, E_NOT_OK );
+ VALIDATE_W_RV( ( SPI_MAX_SEQUENCE>Sequence ), SPI_SYNCTRANSMIT_SERVICE_ID, SPI_E_PARAM_SEQ, E_NOT_OK );
+ Std_ReturnType rv = E_OK;
+
+ if( Spi_GetSequenceResult(Sequence) == SPI_SEQ_PENDING ) {
+ DEBUG(DEBUG_LOW,"%s: Spi_AsyncTransmit() is PENDING\n",MODULE_NAME);
+ return E_NOT_OK; // SPI157
+ }
+
+ assert(Spi_GetSequenceResult(Sequence) == SPI_SEQ_OK);
+
+ if( Spi_AnyPendingJobs(Sequence) ) {
+ return E_NOT_OK;
+ }
+
+ Spi_SeqWrite(Sequence, SPI_SYNC );
+
+ return rv;
+}
+
+
+//-------------------------------------------------------------------
+
+Std_ReturnType Spi_AsyncTransmit( Spi_SequenceType Sequence ) {
+ VALIDATE_W_RV( ( TRUE == Spi_Global.initRun ), SPI_ASYNCTRANSMIT_SERVICE_ID, SPI_E_UNINIT, E_NOT_OK );
+ VALIDATE_W_RV( ( SPI_MAX_SEQUENCE>Sequence ), SPI_ASYNCTRANSMIT_SERVICE_ID, SPI_E_PARAM_SEQ, E_NOT_OK );
+
+ if( Spi_GetSequenceResult(Sequence) == SPI_SEQ_PENDING ) {
+ DEBUG(DEBUG_LOW,"%s: Spi_AsyncTransmit() is PENDING\n",MODULE_NAME);
+ return E_NOT_OK; // SPI157
+ }
+
+ assert(Spi_GetSequenceResult(Sequence) == SPI_SEQ_OK);
+
+ if( Spi_AnyPendingJobs(Sequence) ) {
+ return E_NOT_OK;
+ }
+
+ DEBUG(DEBUG_LOW,"%s: Starting seq: %d\n",MODULE_NAME,Sequence);
+
+ Spi_SeqWrite(Sequence, SPI_ASYNC );
+
+ return E_OK;
+}
+
+
+//-------------------------------------------------------------------
+
+
+Std_ReturnType Spi_ReadIB( Spi_ChannelType Channel, Spi_DataType *const DataBufferPtr ) {
+ VALIDATE_W_RV( ( TRUE == Spi_Global.initRun ), SPI_READIB_SERVICE_ID, SPI_E_UNINIT, E_NOT_OK );
+ VALIDATE_W_RV( ( Channel<SPI_MAX_CHANNEL ), SPI_READIB_SERVICE_ID, SPI_E_PARAM_CHANNEL, E_NOT_OK );
+ VALIDATE_W_RV( ( SPI_IB<Spi_Global.configPtr->SpiChannelConfig[Channel].SpiChannelType ),\
+ SPI_READIB_SERVICE_ID, SPI_E_PARAM_CHANNEL, E_NOT_OK );
+
+ /* NOT SUPPORTED */
+
+ Std_ReturnType rv = E_NOT_OK;
+ return rv;
+}
+
+//-------------------------------------------------------------------
+
+Std_ReturnType Spi_SetupEB( Spi_ChannelType Channel,
+ const Spi_DataType* SrcDataBufferPtr,
+ Spi_DataType* DesDataBufferPtr,
+ Spi_NumberOfDataType Length )
+{
+ VALIDATE_W_RV( ( TRUE == Spi_Global.initRun ), SPI_SETUPEB_SERVICE_ID, SPI_E_UNINIT, E_NOT_OK );
+ VALIDATE_W_RV( ( Channel<SPI_MAX_CHANNEL ), SPI_SETUPEB_SERVICE_ID, SPI_E_PARAM_CHANNEL, E_NOT_OK );
+#if ( SPI_CHANNEL_BUFFERS_ALLOWED == 1 )
+ VALIDATE_W_RV( ( SPI_EB==Spi_Global.configPtr->SpiChannelConfig[Channel].SpiChannelType ),\
+ SPI_SETUPEB_SERVICE_ID, SPI_E_PARAM_CHANNEL, E_NOT_OK );
+#endif
+// SPI067
+ VALIDATE_W_RV( ( Length<=Spi_Global.configPtr->SpiChannelConfig[Channel].SpiEbMaxLength ),\
+ SPI_SETUPEB_SERVICE_ID, SPI_E_PARAM_CHANNEL, E_NOT_OK );
+
+ Spi_EbType *extChBuff= &Spi_Global.extBufPtr[Channel];
+ const Spi_ChannelConfigType *chConfig = &Spi_Global.configPtr->SpiChannelConfig[Channel];
+
+ if( chConfig->SpiChannelType == SPI_EB ) {
+ extChBuff->src = SrcDataBufferPtr;
+ extChBuff->dest = DesDataBufferPtr;
+ extChBuff->length = Length;
+ extChBuff->active = 1;
+ } else {
+ /* NOT SUPPORTED */
+ assert(0);
+ while(1);
+ }
+
+ return E_OK;
+}
+
+//-------------------------------------------------------------------
+
+Spi_StatusType Spi_GetStatus( void ) {
+ VALIDATE_W_RV( ( TRUE == Spi_Global.initRun ), SPI_GETSTATUS_SERVICE_ID, SPI_E_UNINIT, E_NOT_OK );
+
+ if( !Spi_Global.initRun ) {
+ return SPI_UNINIT;
+ }
+
+ // Check all sequences if they have any job pending
+ for(int i=0;i<SPI_MAX_SEQUENCE;i++) {
+ if( Spi_GetSequenceResult(i)==SPI_SEQ_PENDING ) {
+ return SPI_BUSY;
+ }
+ }
+
+ return SPI_IDLE;
+}
+
+//-------------------------------------------------------------------
+
+
+Spi_JobResultType Spi_GetJobResult ( Spi_JobType Job ) {
+ VALIDATE_W_RV( ( TRUE == Spi_Global.initRun ), SPI_GETJOBRESULT_SERVICE_ID, SPI_E_UNINIT, SPI_JOB_FAILED );
+ VALIDATE_W_RV( ( SPI_MAX_JOB<Job ), SPI_GETJOBRESULT_SERVICE_ID, SPI_E_PARAM_JOB, SPI_JOB_FAILED );
+
+ return Spi_JobUnit[Job].jobResult;
+}
+
+//-------------------------------------------------------------------
+
+
+Spi_SeqResultType Spi_GetSequenceResult(Spi_SequenceType Sequence ) {
+ Spi_SeqResultType rv;
+
+ VALIDATE_W_RV( ( TRUE == Spi_Global.initRun ), SPI_GETSEQUENCERESULT_SERVICE_ID, SPI_E_UNINIT, SPI_SEQ_FAILED );
+ VALIDATE_W_RV( ( SPI_MAX_SEQUENCE>Sequence ), SPI_GETSEQUENCERESULT_SERVICE_ID, SPI_E_PARAM_SEQ, SPI_SEQ_FAILED );
+
+ rv = Spi_SeqUnit[Sequence].seqResult;
+
+ return rv;
+}
+
+//-------------------------------------------------------------------
+
+Spi_StatusType Spi_GetHWUnitStatus(Spi_HWUnitType HWUnit) {
+ VALIDATE_W_RV( ( TRUE == Spi_Global.initRun ), SPI_GETHWUNITSTATUS_SERVICE_ID, SPI_E_UNINIT, E_NOT_OK );
+
+ return Spi_Unit[HWUnit].status;
+}
+
+//-------------------------------------------------------------------
+
+#if (SPI_CANCEL_API == STD_ON )
+void Spi_Cancel( Spi_SequenceType Sequence ) {
+ VALIDATE( ( TRUE == Spi_Global.initRun ), SPI_CANCEL_SERVICE_ID, SPI_E_UNINIT );
+ VALIDATE( ( SPI_MAX_SEQUENCE<Sequence ), SPI_CANCEL_SERVICE_ID, SPI_E_PARAM_SEQ );
+
+ /* NOT SUPPORTED */
+}
+#endif
+
+//-------------------------------------------------------------------
+
+
+#if ( SPI_LEVEL_DELIVERED == 2) // SPI154
+
+Std_ReturnType Spi_SetAsyncMode( Spi_AsyncModeType Mode ) {
+ VALIDATE_W_RV( ( TRUE == Spi_Global.initRun ), SPI_SETASYNCMODE_SERVICE_ID, SPI_E_UNINIT, E_NOT_OK );
+
+ // Note!
+ // Not really sure by whom this function is supposed to be called by.
+ // The users of SPI(e2,flash,etc) should probably not use this.
+
+ for(int i=0;i<SPI_MAX_SEQUENCE;i++) {
+ if( Spi_GetSequenceResult(i) == SPI_SEQ_PENDING ) {
+ return E_NOT_OK;
+ }
+ }
+
+ Spi_Global.asyncMode = Mode;
+
+ return E_OK;
+}
+#endif
+
+//-------------------------------------------------------------------
+
+void Spi_MainFunction_Handling( void ) {
+ /* NOT SUPPORTED */
+}
+
+//-------------------------------------------------------------------
+
+void Spi_MainFunction_Driving( void ) {
+ struct DSPI_tag *spiHw;
+ uint32 confMask;
+ uint8 confNr;
+ Spi_UnitType *spiUnit;
+
+ // TODO: check that the queue is empty.. if so do the next job.
+ if( Spi_Global.asyncMode == SPI_POLLING_MODE ) {
+ confMask = Spi_Global.spiHwConfigured;
+
+ for (; confMask; confMask&=~(1<<confNr)) {
+ confNr = ilog2(confMask);
+ spiHw = GET_SPI_HW_PTR(confNr);
+
+ if( Spi_GetHWUnitStatus(confNr) == SPI_BUSY ) {
+ if (spiHw->SR.B.TXRXS) {
+ // Still not done..
+ } else {
+ spiUnit = GET_SPI_UNIT_PTR(confNr);
+ Spi_Isr(confNr);
+ }
+ }
+ }
+ }
+}
+
+
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*\r
+ * Wdg.c\r
+ *\r
+ * Created on: 2009-jul-22\r
+ * Author: rosa\r
+ */\r
+\r
+\r
+#include "mpc55xx.h"\r
+#include "mcu.h"\r
+void StartWatchdog(void)\r
+{\r
+ // Setup watchdog\r
+ // R0 = 0 Not read only\r
+ // SWRWH = 0 SWT stops counting if the processor core is halted.\r
+ // SWE = 1 SWT is enabled.\r
+ // SWRI = 2 If a time-out occurs, the SWT generates a system reset.\r
+ // SWT = 24 For SWT = n, then time-out period = 2^n system clock cycles, n = 8 9,..., 31.\r
+ // SWT = 24 => period = 262144 clock cycles ( 254ms @ 66MHz )\r
+#if defined(CFG_MPC5567)\r
+ ECSM.SWTCR.R = 0x00D8;;\r
+#else\r
+ MCM.SWTCR.R = 0x00D8;\r
+#endif\r
+}\r
+\r
+void StopWatchdog(void)\r
+{\r
+ // Stop the watchdog\r
+ // R0 = 0 Not read only\r
+ // SWRWH = 0 SWT stops counting if the processor core is halted.\r
+ // SWE = 0 SWT is disabled.\r
+ // SWRI = 2 If a time-out occurs, the SWT generates a system reset.\r
+ // SWT = 19 For SWT = n, then time-out period = 2^n system clock cycles, n = 8 9,..., 31.\r
+ // SWT = 19 => period = 524288 clock cycles ( 8.7ms @ 60MHz )\r
+#if defined(CFG_MPC5567)\r
+ ECSM.SWTCR.R = 0x0059;;\r
+#else\r
+ MCM.SWTCR.R = 0x0059;\r
+#endif\r
+}\r
+\r
+\r
+/* This function services the internal Watchdog timer */\r
+void KickWatchdog(void)\r
+{\r
+ uint32 prevIEN;\r
+\r
+ prevIEN = McuE_EnterCriticalSection();\r
+\r
+// According to MPC55xx manual:\r
+// To prevent the watchdog timer from interrupting or resetting\r
+// the SWTSR must be serviced by performing the following sequence:\r
+// 1. Write 0x55 to the SWTSR.\r
+// 2. Write 0xAA to the SWTSR.\r
+#if defined(CFG_MPC5567)\r
+ ECSM.SWTSR.R = 0x55;\r
+ ECSM.SWTSR.R = 0xAA;\r
+#else\r
+ MCM.SWTSR.R = 0x55;\r
+ MCM.SWTSR.R = 0xAA;\r
+#endif\r
+ McuE_ExitCriticalSection(prevIEN);\r
+}\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*\r
+ * Wdg.h\r
+ *\r
+ * Created on: 2009-jul-22\r
+ * Author: rosa\r
+ */\r
+\r
+#ifndef WDG_H_\r
+#define WDG_H_\r
+\r
+void StartWatchdog(void);\r
+void StopWatchdog(void);\r
+void KickWatchdog(void);\r
+\r
+#endif /* WDG_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include "WdgM.h"\r
+#include "Mcu.h"\r
+\r
+const WdgM_ConfigType *wdgMConfigPtr;\r
+static WdgM_SupervisedStatusType WdgM_GlobalSupervisionStatus = WDBG_ALIVE_OK;\r
+\r
+Std_ReturnType WdgM_UpdateAliveCounter (WdgM_SupervisedEntityIdType SEid)\r
+{\r
+ Wdgm_SupervisionType *supervisionPtr = &(wdgMConfigPtr->Wdgm_SupervisionPtr)[SEid];\r
+\r
+ if (supervisionPtr->ActivationStatus == WDBG_SUPERVISION_ENABLED)\r
+ {\r
+ supervisionPtr->AliveCounter++;\r
+ }\r
+ return (E_OK);\r
+}\r
+\r
+Std_ReturnType WdgM_ActivateAliveSupervision (WdgM_SupervisedEntityIdType SEid)\r
+{\r
+ Wdgm_SupervisionType *supervisionPtr = &(wdgMConfigPtr->Wdgm_SupervisionPtr)[SEid];\r
+\r
+ supervisionPtr->ActivationStatus = WDBG_SUPERVISION_ENABLED;\r
+\r
+ return (E_OK);\r
+}\r
+\r
+Std_ReturnType WdgM_DeactivateAliveSupervision (WdgM_SupervisedEntityIdType SEid)\r
+{\r
+ Wdgm_SupervisionType *supervisionPtr = &(wdgMConfigPtr->Wdgm_SupervisionPtr)[SEid];\r
+\r
+ supervisionPtr->ActivationStatus = WDBG_SUPERVISION_DISABLED;\r
+ return (E_OK);\r
+}\r
+\r
+void WdgM_Init(const WdgM_ConfigType *ConfigPtr)\r
+{\r
+ WdgM_SupervisedEntityIdType SEid;\r
+ Wdgm_SupervisionType *supervisionPtr;\r
+ WdgM_SupervisedEntityType* supervisedEntityPtr;\r
+\r
+ for (SEid = 0; SEid < WDBG_NBR_OF_ALIVE_SIGNALS; SEid++)\r
+ {\r
+ supervisionPtr = &(ConfigPtr->Wdgm_SupervisionPtr)[SEid];\r
+ supervisedEntityPtr = (WdgM_SupervisedEntityType*)&(ConfigPtr->WdgM_SupervisedEntityPtr)[SEid];\r
+ supervisionPtr->ActivationStatus = supervisedEntityPtr->WdgM_ActivationStatus;\r
+ }\r
+ wdgMConfigPtr = ConfigPtr;\r
+\r
+}\r
+\r
+void WdgM_MainFunction_AliveSupervision (void)\r
+{\r
+ WdgM_SupervisedEntityIdType SEid;\r
+ Wdgm_SupervisionType *supervisionPtr;\r
+ const WdgM_SupervisedEntityType *entityPtr;\r
+ WdgM_SupervisionCounterType aliveCalc, nSC, nAl, eai;\r
+ WdgM_SupervisedStatusType maxLocal = WDBG_ALIVE_OK;\r
+ static WdgM_SupervisionCounterType expiredSupervisionCycles = 0;\r
+\r
+ for (SEid = 0; SEid < WDBG_NBR_OF_ALIVE_SIGNALS; SEid++)\r
+ {\r
+ supervisionPtr = &(wdgMConfigPtr->Wdgm_SupervisionPtr)[SEid];\r
+ entityPtr = &(wdgMConfigPtr->WdgM_SupervisedEntityPtr)[SEid];\r
+\r
+ if (WDBG_SUPERVISION_ENABLED == supervisionPtr->ActivationStatus)\r
+ {\r
+ supervisionPtr->SupervisionCycle++;\r
+ /* Only perform supervision on the reference cycle. */\r
+ if (supervisionPtr->SupervisionCycle == entityPtr->WdgM_SupervisionReferenceCycle)\r
+ {\r
+ /* Alive algorithm. *\r
+ * n (Al) - n(SC) + EAI == 0 */\r
+ if (entityPtr->WdgM_ExpectedAliveIndications > entityPtr->WdgM_SupervisionReferenceCycle)\r
+ {\r
+ /* Scenario A */\r
+ eai = -entityPtr->WdgM_ExpectedAliveIndications + 1;\r
+\r
+ }\r
+ else\r
+ {\r
+ /* Scenario B */\r
+ eai = entityPtr->WdgM_SupervisionReferenceCycle - 1;\r
+ }\r
+ nSC = supervisionPtr->SupervisionCycle;\r
+ nAl = supervisionPtr->AliveCounter;\r
+ aliveCalc = nAl - nSC + eai;\r
+\r
+ if ((aliveCalc <= entityPtr->WdgM_MaxMargin) &&\r
+ (aliveCalc >= -entityPtr->WdgM_MinMargin))\r
+ {\r
+ /* Entity alive OK. */\r
+ supervisionPtr->SupervisionStatus = WDBG_ALIVE_OK;\r
+ }\r
+ else\r
+ {\r
+ /* Entity alive NOK. */\r
+ supervisionPtr->SupervisionStatus = WDBG_ALIVE_FAILED;\r
+ if (WDBG_ALIVE_FAILED > maxLocal)\r
+ {\r
+ maxLocal = WDBG_ALIVE_FAILED;\r
+ }\r
+ }\r
+\r
+ if (WDBG_ALIVE_FAILED == supervisionPtr->SupervisionStatus)\r
+ {\r
+ if (supervisionPtr->NbrOfFailedRefCycles > entityPtr->WdgM_FailedSupervisionReferenceCycleTolerance)\r
+ {\r
+ supervisionPtr->SupervisionStatus = WDBG_ALIVE_EXPIRED;\r
+ if (WDBG_ALIVE_EXPIRED > maxLocal)\r
+ {\r
+ maxLocal = WDBG_ALIVE_EXPIRED;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ supervisionPtr->NbrOfFailedRefCycles++;\r
+ }\r
+ }\r
+\r
+ /* Reset counters. */\r
+ supervisionPtr->SupervisionCycle = 0;\r
+ supervisionPtr->AliveCounter = 0;\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Try to heal global status. */\r
+ if (WDBG_ALIVE_EXPIRED != WdgM_GlobalSupervisionStatus)\r
+ {\r
+ WdgM_GlobalSupervisionStatus = maxLocal;\r
+ }\r
+ else\r
+ {\r
+ WdgM_GlobalSupervisionStatus = WDBG_ALIVE_EXPIRED;\r
+ }\r
+\r
+ if (WDBG_ALIVE_EXPIRED == WdgM_GlobalSupervisionStatus)\r
+ {\r
+ expiredSupervisionCycles++;\r
+ }\r
+\r
+ if (expiredSupervisionCycles >= wdgMConfigPtr->WdgM_ExpiredSupervisionCycleTolerance)\r
+ {\r
+ WdgM_GlobalSupervisionStatus = WDBG_ALIVE_STOPPED;\r
+ }\r
+}\r
+\r
+boolean WdgM_IsAlive(void)\r
+{\r
+\r
+ if ( WDBG_ALIVE_STOPPED > WdgM_GlobalSupervisionStatus )\r
+ {\r
+ return (TRUE);\r
+ }\r
+ else\r
+ {\r
+ return (FALSE);\r
+ }\r
+}\r
+\r
+void WdgM_MainFunction_Trigger (void)\r
+{\r
+ if ( WdgM_IsAlive() )\r
+ {\r
+ KickWatchdog();\r
+ }\r
+}\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include "WdgM_Cfg.h"\r
+\r
+Std_ReturnType WdgM_UpdateAliveCounter (WdgM_SupervisedEntityIdType SEid);\r
+Std_ReturnType WdgM_ActivateAliveSupervision (WdgM_SupervisedEntityIdType SEid);\r
+Std_ReturnType WdgM_DeactivateAliveSupervision (WdgM_SupervisedEntityIdType SEid);\r
+void WdgM_Init(const WdgM_ConfigType* ConfigPtr);\r
+void WdgM_MainFunction_AliveSupervision (void);\r
+void WdgM_MainFunction_Trigger (void);\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+#ifndef WDGM_CFG_H_\r
+#define WDGM_CFG_H_\r
+\r
+#include "Std_Types.h"\r
+#include "WdgM_Lcfg.h"\r
+\r
+typedef enum\r
+{\r
+ WDBG_ALIVE_OK,\r
+ WDBG_ALIVE_FAILED,\r
+ WDBG_ALIVE_EXPIRED,\r
+ WDBG_ALIVE_STOPPED,\r
+ WDBG_ALIVE_DEACTIVATED,\r
+}WdgM_SupervisedStatusType;\r
+\r
+typedef enum\r
+{\r
+ WDBG_SUPERVISION_DISABLED,\r
+ WDBG_SUPERVISION_ENABLED\r
+}WdgM_ActivationStatusType;\r
+\r
+typedef int16_t WdgM_SupervisionCounterType ;\r
+\r
+typedef struct\r
+{\r
+ WdgM_SupervisionCounterType AliveCounter;\r
+ WdgM_SupervisionCounterType SupervisionCycle;\r
+ WdgM_SupervisedStatusType SupervisionStatus;\r
+ WdgM_SupervisionCounterType NbrOfFailedRefCycles;\r
+ WdgM_ActivationStatusType ActivationStatus;\r
+}Wdgm_SupervisionType;\r
+\r
+typedef struct\r
+{\r
+ const WdgM_SupervisedEntityIdType WdgM_SupervisedEntityID;\r
+ const WdgM_ActivationStatusType WdgM_ActivationStatus;\r
+ const WdgM_SupervisionCounterType WdgM_ExpectedAliveIndications;\r
+ const WdgM_SupervisionCounterType WdgM_SupervisionReferenceCycle;\r
+ const WdgM_SupervisionCounterType WdgM_FailedSupervisionReferenceCycleTolerance;\r
+ const WdgM_SupervisionCounterType WdgM_MinMargin;\r
+ const WdgM_SupervisionCounterType WdgM_MaxMargin;\r
+}WdgM_SupervisedEntityType;\r
+\r
+typedef struct\r
+{\r
+ uint16 WdgM_SupervisionCycle;\r
+ uint16 WdgM_NumberOfSupervisedEntities;\r
+ uint16 WdgM_ExpiredSupervisionCycleTolerance;\r
+ const WdgM_SupervisedEntityType *WdgM_SupervisedEntityPtr;\r
+ Wdgm_SupervisionType *Wdgm_SupervisionPtr;\r
+}WdgM_ConfigType;\r
+\r
+extern const WdgM_ConfigType WdgMAliveSupervision;\r
+\r
+#endif /* WDGM_CFG_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef H7F_TYPES_H_\r
+#define H7F_TYPES_H_\r
+\r
+\r
+#endif /*H7F_TYPES_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/**************************************************************************\r
+ * FILE NAME: $RCSfile: mpc5500_spr.h,v $ COPYRIGHT (c) Freescale 2005 *\r
+ * DESCRIPTION: All Rights Reserved *\r
+ * This file contain all of the SPR register and bit field definitions *\r
+ * for MPC5500 products. There are no address assignments for the SPR *\r
+ * registers. Instead, the bit field structures are only assigned. *\r
+ * SPR register numbers are also assigned. *\r
+ *========================================================================*\r
+ * ORIGINAL AUTHOR: Glenn Jackson *\r
+ * $Log: mpc5500_spr.h,v $\r
+ * Revision 1.5 2006/08/30 09:06:42 r54088\r
+ * L1SCR0, Bit field changed from DPP to DPB to align with documentation.\r
+ *\r
+ * Revision 1.4 2006/08/10 16:08:04 r54088\r
+ * L1CSR0[WAM] & L1CSR0[CORG] Added\r
+ *\r
+ * Revision 1.3 2005/02/22 13:49:32 r47354\r
+ * Made the same as file currently on extranet.\r
+ * Changed _MPC5554_SPR_ to _MPC5500_SPR_.\r
+ * Changed to Freescale copyrigh/discimer.\r
+ *\r
+ * Revision 1.2 2005/02/22 13:06:16 r47354\r
+ * Prepend all Special Purpose Register names with "SPR_" to prevent issues when using this file with mpc5553/4.h\r
+ *\r
+ * Revision 1.1 2005/02/22 10:55:20 r47354\r
+ * Initial revision. Based on mpc5554_spr.h\r
+ *........................................................................*\r
+ * 0.01 G. Jackson 13/Nov/03 Initial version of file for SPR *\r
+ * registers in the MPC5554. *\r
+ * Based on SoC version 0.7. *\r
+ * 1.0 G. Jackson 23/Jan/04 Replaced MASnVAL with MASnCVAL to *\r
+ * maintain unique function defintions. *\r
+ * 1.1 G. Jackson 19/Jul/04 #endif note placed after _MPC5554_SPR_ *\r
+ * #ifndef and #define. *\r
+ * Changed structures to typedefs that *\r
+ * would be instantiated by customer *\r
+ * definition later in code. *\r
+ * 1.2 G.Jackson 14/Sep/04 Added SPR_ prefixes for unique names. *\r
+ **************************************************************************/\r
+\r
+/* >>>>NOTE! this file describes fixed special purpose registers. */\r
+/* Please do not edit it directly!<<<< */\r
+\r
+#ifndef _MPC5500_SPR_\r
+#define _MPC5500_SPR_\r
+/* This ifndef has a corresponding #endif at the bottom of this file */\r
+/* so that it will only be included once. */\r
+\r
+#include "typedefs.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/********************************************/\r
+/* Example instantiation and use: */\r
+/* union CRVAL my_cr; */\r
+/* my_cr.B.CR0 = 1; */\r
+/* my_cr.R = 0x10000000 */\r
+/********************************************/\r
+\r
+\r
+\r
+/****************************************************************************/\r
+/* CPU REGISTERS: General Registers */\r
+/****************************************************************************/\r
+ union SPR_CRVAL {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CR0:4;\r
+ vuint32_t CR1:4;\r
+ vuint32_t CR2:4;\r
+ vuint32_t CR3:4;\r
+ vuint32_t CR4:4;\r
+ vuint32_t CR5:4;\r
+ vuint32_t CR6:4;\r
+ vuint32_t CR7:4;\r
+ } B;\r
+ };\r
+\r
+ union SPR_LRVAL {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t LINKADDRESS:32;\r
+ } B;\r
+ };\r
+\r
+ union SPR_CTRVAL {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t COUNTVALUE:32;\r
+ } B;\r
+ };\r
+\r
+ union SPR_XERVAL {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t SO:1;\r
+ vuint32_t OV:1;\r
+ vuint32_t CA:1;\r
+ vuint32_t :22;\r
+ vuint32_t BYTECNT:7;\r
+ } B;\r
+ };\r
+\r
+\r
+/****************************************************************************/\r
+/* CPU REGISTERS: Processor Control Registers */\r
+/****************************************************************************/\r
+ union SPR_MSRVAL {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :5;\r
+ vuint32_t UCLE:1;\r
+ vuint32_t SPE:1;\r
+ vuint32_t :6;\r
+ vuint32_t WE:1;\r
+ vuint32_t CE:1;\r
+ vuint32_t :1;\r
+ vuint32_t EE:1;\r
+ vuint32_t PR:1;\r
+ vuint32_t FP:1;\r
+ vuint32_t ME:1;\r
+ vuint32_t FE0:1;\r
+ vuint32_t :1;\r
+ vuint32_t DE:1;\r
+ vuint32_t FE1:1;\r
+ vuint32_t :2;\r
+ vuint32_t IS:1;\r
+ vuint32_t DS:1;\r
+ vuint32_t :4;\r
+ } B;\r
+ };\r
+\r
+ union SPR_PIRVAL {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :24;\r
+ vuint32_t ID:8;\r
+ } B;\r
+ };\r
+\r
+ union SPR_PVRVAL {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MFGID:4;\r
+ vuint32_t :2;\r
+ vuint32_t TYPE:6;\r
+ vuint32_t VER:4;\r
+ vuint32_t MGBUSE:8;\r
+ vuint32_t MJRREV:4;\r
+ vuint32_t MGBID:4;\r
+ } B;\r
+ };\r
+\r
+ union SPR_SVRVAL {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t SYSVER:32;\r
+ } B;\r
+ };\r
+\r
+ union SPR_HID0VAL {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t EMCP:1;\r
+ vuint32_t :5;\r
+ vuint32_t BPRED:2;\r
+ vuint32_t DOZE:1;\r
+ vuint32_t NAP:1;\r
+ vuint32_t SLEEP:1;\r
+ vuint32_t :3;\r
+ vuint32_t ICR:1;\r
+ vuint32_t NHR:1;\r
+ vuint32_t :1;\r
+ vuint32_t TBEN:1;\r
+ vuint32_t SEL_TBCLK:1;\r
+ vuint32_t DCLREE:1;\r
+ vuint32_t DCLRCE:1;\r
+ vuint32_t CICLRDE:1;\r
+ vuint32_t MCCLRDE:1;\r
+ vuint32_t DAPUEN:1;\r
+ vuint32_t :8;\r
+ } B;\r
+ };\r
+\r
+ union SPR_HID1VAL {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :24;\r
+ vuint32_t ATS:1;\r
+ vuint32_t :7;\r
+ } B;\r
+ };\r
+\r
+/****************************************************************************/\r
+/* CPU REGISTERS: TIMERS */\r
+/****************************************************************************/\r
+\r
+ union SPR_TBLVAL {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TBLVALUE:32;\r
+ } B;\r
+ };\r
+\r
+ union SPR_TBUVAL {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TBUVALUE:32;\r
+ } B;\r
+ };\r
+\r
+ union SPR_TCRVAL {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t WP:2;\r
+ vuint32_t WRC:2;\r
+ vuint32_t WIE:1;\r
+ vuint32_t DIE:1;\r
+ vuint32_t FP:2;\r
+ vuint32_t FIE:1;\r
+ vuint32_t ARE:1;\r
+ vuint32_t :1;\r
+ vuint32_t WPEXT:4;\r
+ vuint32_t FPEXT:4;\r
+ vuint32_t :13;\r
+ } B;\r
+ };\r
+\r
+ union SPR_TSRVAL {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t ENW:1;\r
+ vuint32_t WIS:1;\r
+ vuint32_t WRS:2;\r
+ vuint32_t DIS:1;\r
+ vuint32_t FIS:1;\r
+ vuint32_t :26;\r
+ } B;\r
+ };\r
+\r
+\r
+ union SPR_DECVAL {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DECVALUE:32;\r
+ } B;\r
+ };\r
+\r
+ union SPR_DECARVAL {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DECARVALUE:32;\r
+ } B;\r
+ };\r
+\r
+\r
+\r
+/****************************************************************************/\r
+/* CPU REGISTERS: MMU */\r
+/****************************************************************************/\r
+ union SPR_PID0VAL {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :24;\r
+ vuint32_t PID:8;\r
+ } B;\r
+ };\r
+\r
+ union SPR_MMUCSR0VAL {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :30;\r
+ vuint32_t TLBCAM_FI:1;\r
+ vuint32_t:1;\r
+ } B;\r
+ };\r
+\r
+ union SPR_MMUCFGVAL {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:17;\r
+ vuint32_t NPIDS:4;\r
+ vuint32_t PIDSIZE:5;\r
+ vuint32_t:2;\r
+ vuint32_t NLTBS:2;\r
+ vuint32_t MAVN:2;\r
+ } B;\r
+ };\r
+\r
+ union SPR_TLB0CFGVAL {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t ASSOC:8;\r
+ vuint32_t MINSIZE:4;\r
+ vuint32_t MAXSIZE:4;\r
+ vuint32_t IPROT:1;\r
+ vuint32_t AVAIL:1;\r
+ vuint32_t :2;\r
+ vuint32_t NENTRY:12;\r
+ } B;\r
+ };\r
+\r
+ union SPR_TLB1CFGVAL {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t ASSOC:8;\r
+ vuint32_t MINSIZE:4;\r
+ vuint32_t MAXSIZE:4;\r
+ vuint32_t IPROT:1;\r
+ vuint32_t AVAIL:1;\r
+ vuint32_t :2;\r
+ vuint32_t NENTRY:12;\r
+ } B;\r
+ };\r
+\r
+ union SPR_MAS0CVAL {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:2;\r
+ vuint32_t TLBSEL:2;\r
+ vuint32_t:7;\r
+ vuint32_t ESELCAM:5;\r
+ vuint32_t:11;\r
+ vuint32_t NVCAM:5;\r
+ } B;\r
+ };\r
+\r
+ union SPR_MAS1CVAL {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t VALID:1;\r
+ vuint32_t IPROT:1;\r
+ vuint32_t:6;\r
+ vuint32_t TID:8;\r
+ vuint32_t:3;\r
+ vuint32_t TS:1;\r
+ vuint32_t TSIZ:4;\r
+ vuint32_t:8;\r
+ } B;\r
+ };\r
+\r
+ union SPR_MAS2CVAL {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t EPN:20; /* Effective Page Number */\r
+ vuint32_t:7;\r
+ vuint32_t W:1; /* Write through required; */\r
+ /* 0=write back; 1=write through */\r
+ vuint32_t I:1; /* Cache Inhibit; 0=not inhibited */\r
+ vuint32_t M:1; /* Memory coherence; 0=not required */\r
+ vuint32_t G:1; /* Gaurded; 0=not gaurded */\r
+ vuint32_t E:1; /* Endianess; 0=Big; 1=Little */\r
+ } B;\r
+ };\r
+\r
+ union SPR_MAS3CVAL {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t RPN:20; /* Real Page Number */\r
+ vuint32_t:2;\r
+ vuint32_t U0:1; /* User bits [0:3] */\r
+ vuint32_t U1:1;\r
+ vuint32_t U2:1;\r
+ vuint32_t U3:1;\r
+ vuint32_t UX:1; /* Permission bits */\r
+ vuint32_t SX:1;\r
+ vuint32_t UW:1;\r
+ vuint32_t SW:1;\r
+ vuint32_t UR:1;\r
+ vuint32_t SR:1;\r
+ } B;\r
+ };\r
+\r
+ union SPR_MAS4CVAL {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:2;\r
+ vuint32_t TLBSELD:2;\r
+ vuint32_t:10;\r
+ vuint32_t TIDSELD:2;\r
+ vuint32_t:4;\r
+ vuint32_t TSIZED:4;\r
+ vuint32_t :3;\r
+ vuint32_t WD:1;\r
+ vuint32_t ID:1;\r
+ vuint32_t MD:1;\r
+ vuint32_t GD:1;\r
+ vuint32_t ED:1;\r
+ } B;\r
+ };\r
+\r
+ union SPR_MAS6CVAL {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:8;\r
+ vuint32_t SPID:8;\r
+ vuint32_t:15;\r
+ vuint32_t SAS:1;\r
+ } B;\r
+ };\r
+\r
+/****************************************************************************/\r
+/* CPU REGISTERS: CACHE */\r
+/****************************************************************************/\r
+ union SPR_L1CFG0VAL { /* Read only register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CARCH:2; /* Cache Architecture; 01=Unified */\r
+ vuint32_t CWPA:1; /* Cache way partitioning available =1 */\r
+ vuint32_t CFAHA:1; /* Cache Flush by all avail; 0=not */\r
+ vuint32_t CFISWA:1; /* Cache Flush Inv by set & way avail=1 */\r
+ vuint32_t :2;\r
+ vuint32_t CBSIZE:2; /* Block Size 00=32 bytes */\r
+ vuint32_t CREPL:2; /* Replacement Policy 10=pseudo round robin */\r
+ vuint32_t CLA:1; /* Line locking APU; 1=avail */\r
+ vuint32_t CPA:1; /* Parity available 1=avail */\r
+ vuint32_t CNWAY:8; /* Num of ways; 0x03=4way, 0x07=8way */\r
+ vuint32_t CSIZE:11; /* Size; 0x008=8KB, 0x010=16KB,0x020=32KB */\r
+ } B;\r
+ }; /* Read only register */\r
+\r
+\r
+ union SPR_L1CSR0VAL {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t WID:4;\r
+ vuint32_t WDD:4;\r
+ vuint32_t AWD:1;\r
+ vuint32_t AWDD:1;\r
+ vuint32_t WAM:1;\r
+ vuint32_t CWM:1;\r
+ vuint32_t DPB:1;\r
+ vuint32_t DSB:1;\r
+ vuint32_t DSTR:1;\r
+ vuint32_t CPE:1;\r
+ vuint32_t :5;\r
+ vuint32_t CUL:1;\r
+ vuint32_t CLO:1;\r
+ vuint32_t CLFC:1;\r
+ vuint32_t :3; \r
+ vuint32_t CORG:1; \r
+ vuint32_t :1;\r
+ vuint32_t CABT:1;\r
+ vuint32_t CINV:1;\r
+ vuint32_t CE:1;\r
+ } B;\r
+ };\r
+\r
+ union SPR_L1FINV0VAL {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :5;\r
+ vuint32_t CWAY:3;\r
+ vuint32_t :12;\r
+ vuint32_t CSET:7;\r
+ vuint32_t :3;\r
+ vuint32_t CCMD:2;\r
+ } B;\r
+ };\r
+\r
+/****************************************************************************/\r
+/* CPU REGISTERS: APU */\r
+/****************************************************************************/\r
+ union SPR_SPEFSCRVAL { /* Status and Control of SPE instructions */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t SOVH:1;\r
+ vuint32_t OVH:1;\r
+ vuint32_t FGH:1;\r
+ vuint32_t FXH:1;\r
+ vuint32_t FINVH:1;\r
+ vuint32_t FDBZH:1;\r
+ vuint32_t FUNFH:1;\r
+ vuint32_t FOVFH:1;\r
+ vuint32_t :2;\r
+ vuint32_t FINXS:1;\r
+ vuint32_t FINVS:1;\r
+ vuint32_t FDBZS:1;\r
+ vuint32_t FUNFS:1;\r
+ vuint32_t FOVFS:1;\r
+ vuint32_t MODE:1;\r
+ vuint32_t SOV:1;\r
+ vuint32_t OV:1;\r
+ vuint32_t FG:1;\r
+ vuint32_t FX:1;\r
+ vuint32_t FINV:1;\r
+ vuint32_t FDBZ:1;\r
+ vuint32_t FUNF:1;\r
+ vuint32_t FOVF:1;\r
+ vuint32_t :1;\r
+ vuint32_t FINXE:1;\r
+ vuint32_t FINVE:1;\r
+ vuint32_t FDBZE:1;\r
+ vuint32_t FUNFE:1;\r
+ vuint32_t FOVFE:1;\r
+ vuint32_t FRMC:2;\r
+ } B;\r
+ };\r
+\r
+/****************************************************************************/\r
+/* CPU REGISTERS: Exception Handling/Control Registers */\r
+/****************************************************************************/\r
+ union SPR_SPRGVAL { /* There are [8] entries for this tag */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t SPRDATA:32;\r
+ } B;\r
+ };\r
+\r
+ union SPR_USPRG0VAL {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t USPR0DATA:32;\r
+ } B;\r
+ };\r
+\r
+ union SPR_SRR0VAL {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t NXTADDR:32;\r
+ } B;\r
+ };\r
+\r
+ union SPR_SRR1VAL {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MSRSTATE:32;\r
+ } B;\r
+ };\r
+\r
+ union SPR_CSRR0VAL {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CRITNXTADDR:32;\r
+ } B;\r
+ };\r
+\r
+ union SPR_CSRR1VAL {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CRITMSRSTATE:32;\r
+ } B;\r
+ };\r
+\r
+ union SPR_DSRR0VAL {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DBGNXTADDR:32;\r
+ } B;\r
+ };\r
+\r
+ union SPR_DSRR1VAL {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DBGMSRSTATE:32;\r
+ } B;\r
+ };\r
+\r
+ union SPR_DEARVAL {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DATEFADDR:16;\r
+ vuint32_t :16;\r
+ } B;\r
+ };\r
+\r
+ union SPR_ESRVAL {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :4;\r
+ vuint32_t PIL:1;\r
+ vuint32_t PPR:1;\r
+ vuint32_t PTR:1;\r
+ vuint32_t FP:1;\r
+ vuint32_t ST:1;\r
+ vuint32_t :1;\r
+ vuint32_t DLK:1;\r
+ vuint32_t ILK:1;\r
+ vuint32_t AP:1;\r
+ vuint32_t PUO:1;\r
+ vuint32_t BO:1;\r
+ vuint32_t PIE:1;\r
+ vuint32_t :8;\r
+ vuint32_t SPE:1;\r
+ vuint32_t :6;\r
+ vuint32_t XTE:1;\r
+ } B;\r
+ };\r
+\r
+\r
+ union SPR_MCSRVAL {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MCP:1;\r
+ vuint32_t :1;\r
+ vuint32_t CP_PERR:1;\r
+ vuint32_t CPERR:1;\r
+ vuint32_t EXCP_ERR:1;\r
+ vuint32_t :24;\r
+ vuint32_t BUS_WRERR:1;\r
+ vuint32_t :2;\r
+ } B;\r
+ };\r
+\r
+ union SPR_IVPRVAL {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t VECBASE:16;\r
+ vuint32_t :16;\r
+ } B;\r
+ };\r
+\r
+ /* Note: IVOR0 is not supported by the MPC5554 */\r
+ union SPR_IVORVAL { /* There are [16] entries for this tag */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t VECOFFSET:12;\r
+ vuint32_t :4;\r
+ } B;\r
+ };\r
+\r
+ union SPR_IVOR32VAL {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t VECOFFSET:12;\r
+ vuint32_t :4;\r
+ } B;\r
+ };\r
+\r
+ union SPR_IVOR33VAL {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t VECOFFSET:12;\r
+ vuint32_t :4;\r
+ } B;\r
+ };\r
+\r
+ union SPR_IVOR34VAL {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t :16;\r
+ vuint32_t VECOFFSET:12;\r
+ vuint32_t :4;\r
+ } B;\r
+ };\r
+\r
+/****************************************************************************/\r
+/* CPU REGISTERS: DEBUG */\r
+/****************************************************************************/\r
+ union {\r
+ vuint32_t R;\r
+ struct SPR_DBCR0VAL {\r
+ vuint32_t EDM:1;\r
+ vuint32_t IDM:1;\r
+ vuint32_t RST:2;\r
+ vuint32_t ICMP:1;\r
+ vuint32_t BRT:1;\r
+ vuint32_t IRPT:1;\r
+ vuint32_t TRAP:1;\r
+ vuint32_t IAC1:1;\r
+ vuint32_t IAC2:1;\r
+ vuint32_t IAC3:1;\r
+ vuint32_t IAC4:1;\r
+ vuint32_t DAC1:2;\r
+ vuint32_t DAC2:2;\r
+ vuint32_t RET:1;\r
+ vuint32_t :4;\r
+ vuint32_t DEVT1:1;\r
+ vuint32_t DEVT2:1;\r
+ vuint32_t DCNT1:1;\r
+ vuint32_t DCNT2:1;\r
+ vuint32_t CIRPT:1;\r
+ vuint32_t CRET:1;\r
+ vuint32_t :4;\r
+ vuint32_t FT:1;\r
+ } B;\r
+ };\r
+\r
+ union SPR_DBCR1VAL {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t IAC1US:2;\r
+ vuint32_t IAC1ER:2;\r
+ vuint32_t IAC2US:2;\r
+ vuint32_t IAC2ER:2;\r
+ vuint32_t IAC12M:2;\r
+ vuint32_t :6;\r
+ vuint32_t IAC3US:2;\r
+ vuint32_t IAC3ER:2;\r
+ vuint32_t IAC4US:2;\r
+ vuint32_t IAC4ER:2;\r
+ vuint32_t IAC34M:2;\r
+ vuint32_t :6;\r
+ } B;\r
+ };\r
+\r
+ union SPR_DBCR2VAL {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DIAC1US:2;\r
+ vuint32_t DIAC1ER:2;\r
+ vuint32_t DIAC2US:2;\r
+ vuint32_t DIAC2ER:2;\r
+ vuint32_t DIAC12M:2;\r
+ vuint32_t DAC1LNK:2;\r
+ vuint32_t DAC2LNK:2;\r
+ vuint32_t :20;\r
+ } B;\r
+ };\r
+\r
+ union SPR_DBCR3VAL {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DEVT1C1:1;\r
+ vuint32_t DEVT2C1:1;\r
+ vuint32_t ICMPC1:1;\r
+ vuint32_t IAC1C1:1;\r
+ vuint32_t IAC2C1:1;\r
+ vuint32_t IAC3C1:1;\r
+ vuint32_t IAC4C1:1;\r
+ vuint32_t DAC1RC1:1;\r
+ vuint32_t DAC1WC1:1;\r
+ vuint32_t DAC2RC1:1;\r
+ vuint32_t DAC2WC1:1;\r
+ vuint32_t IRPTC1:1;\r
+ vuint32_t RETC1:1;\r
+ vuint32_t DEVT1C2:1;\r
+ vuint32_t DEVT2C2:1;\r
+ vuint32_t ICMPC2:1;\r
+ vuint32_t IAC1C2:1;\r
+ vuint32_t IAC2C2:1;\r
+ vuint32_t IAC3C2:1;\r
+ vuint32_t IAC4C2:1;\r
+ vuint32_t DAC1RC2:1;\r
+ vuint32_t DAC1WC2:1;\r
+ vuint32_t DAC2RC2:1;\r
+ vuint32_t DAC2WC2:1;\r
+ vuint32_t DEVT1T1:1;\r
+ vuint32_t DEVT2T1:1;\r
+ vuint32_t IAC1T1:1;\r
+ vuint32_t IAC3T1:1;\r
+ vuint32_t DAC1RT1:1;\r
+ vuint32_t DAC1WT1:1;\r
+ vuint32_t CNT2T1:1;\r
+ vuint32_t CONFIG:1;\r
+ } B;\r
+ };\r
+\r
+ union SPR_DBSRVAL {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t IDE:1;\r
+ vuint32_t UDE:1;\r
+ vuint32_t MRR:2;\r
+ vuint32_t ICMP:1;\r
+ vuint32_t BRT:1;\r
+ vuint32_t IRPT:1;\r
+ vuint32_t TRAP:1;\r
+ vuint32_t IAC1:1;\r
+ vuint32_t IAC2:1;\r
+ vuint32_t IAC3:1;\r
+ vuint32_t IAC4:1;\r
+ vuint32_t DAC1R:1;\r
+ vuint32_t DAC1W:1;\r
+ vuint32_t DAC2R:1;\r
+ vuint32_t DAC2W:1;\r
+ vuint32_t RET:1;\r
+ vuint32_t :4;\r
+ vuint32_t DEVT1:1;\r
+ vuint32_t DEVT2:1;\r
+ vuint32_t DCNT1:1;\r
+ vuint32_t DCNT2:1;\r
+ vuint32_t CIRPT:1;\r
+ vuint32_t CRET:1;\r
+ vuint32_t :4;\r
+ vuint32_t CNT1RG:1;\r
+ } B;\r
+ };\r
+\r
+ union SPR_DBCNTVAL {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CNT1:16;\r
+ vuint32_t CNT2:16;\r
+ } B;\r
+ };\r
+\r
+ union SPR_IAC1VAL {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t INSTADDR:30;\r
+ vuint32_t :2;\r
+ } B;\r
+ };\r
+\r
+ union SPR_IAC2VAL {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t INSTADDR:30;\r
+ vuint32_t :2;\r
+ } B;\r
+ };\r
+\r
+ union SPR_IAC3VAL {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t INSTADDR:30;\r
+ vuint32_t :2;\r
+ } B;\r
+ };\r
+\r
+ union SPR_IAC4VAL {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t INSTADDR:30;\r
+ vuint32_t :2;\r
+ } B;\r
+ };\r
+\r
+\r
+ union SPR_DAC1VAL {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DATTADDR:32;\r
+ } B;\r
+ };\r
+\r
+ union SPR_DAC2VAL {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DATTADDR:32;\r
+ } B;\r
+ };\r
+\r
+\r
+\r
+/*****************************************************/\r
+/* Define instances of modules */\r
+/* with special register numbers */\r
+/*****************************************************/\r
+\r
+// The CR register does not have an SPR#\r
+// The GPR registers do not have an SPR#\r
+// The MSR register does not have an SPR#\r
+\r
+#define SPR_LR 8\r
+#define SPR_CTR 9\r
+#define SPR_XER 1\r
+\r
+#define SPR_PIR 286\r
+#define SPR_PVR 287\r
+#define SPR_SVR 1023\r
+#define SPR_HID0 1008\r
+#define SPR_HID1 1009\r
+\r
+#define SPR_TBL 284\r
+#define SPR_TBU 285\r
+#define SPR_TCR 340\r
+#define SPR_TSR 336\r
+#define SPR_DEC 22\r
+#define SPR_DECAR 54\r
+\r
+#define SPR_PID0 48\r
+#define SPR_MMUCSR0 1012\r
+#define SPR_MMUCFG 1015\r
+#define SPR_TLB0CFG 688\r
+#define SPR_TLB1CFG 689\r
+#define SPR_MAS0 624\r
+#define SPR_MAS1 625\r
+#define SPR_MAS2 626\r
+#define SPR_MAS3 627\r
+#define SPR_MAS4 628\r
+#define SPR_MAS6 630\r
+\r
+#define SPR_L1CFG0 515\r
+#define SPR_L1CSR0 1010\r
+#define SPR_L1FINV0 1016\r
+\r
+#define SPR_SPEFSCR 512\r
+\r
+#define SPR_SPRG0 272\r
+#define SPR_SPRG1 273\r
+#define SPR_SPRG2 274\r
+#define SPR_SPRG3 275\r
+#define SPR_SPRG4 276\r
+#define SPR_SPRG5 277\r
+#define SPR_SPRG6 278\r
+#define SPR_SPRG7 279\r
+#define SPR_USPRG0 256\r
+#define SPR_SRR0 26\r
+#define SPR_SRR1 27\r
+#define SPR_CSRR0 58\r
+#define SPR_CSRR1 59\r
+#define SPR_DSRR0 574\r
+#define SPR_DSRR1 575\r
+#define SPR_ESR 62\r
+#define SPR_MCSR 572\r
+#define SPR_DEAR 61\r
+#define SPR_IVPR 63\r
+#define SPR_IVOR0 400\r
+#define SPR_IVOR1 401\r
+#define SPR_IVOR2 402\r
+#define SPR_IVOR3 403\r
+#define SPR_IVOR4 404\r
+#define SPR_IVOR5 405\r
+#define SPR_IVOR6 406\r
+#define SPR_IVOR7 407\r
+#define SPR_IVOR8 408\r
+#define SPR_IVOR9 409\r
+#define SPR_IVOR10 410\r
+#define SPR_IVOR11 411\r
+#define SPR_IVOR12 412\r
+#define SPR_IVOR13 413\r
+#define SPR_IVOR14 414\r
+#define SPR_IVOR15 415\r
+#define SPR_IVOR32 528\r
+#define SPR_IVOR33 529\r
+#define SPR_IVOR34 530\r
+\r
+#define SPR_DBCR0 308\r
+#define SPR_DBCR1 309\r
+#define SPR_DBCR2 310\r
+#define SPR_DBCR3 561\r
+#define SPR_DBSR 304\r
+#define SPR_DBCNT 562\r
+#define SPR_IAC1 312\r
+#define SPR_IAC2 313\r
+#define SPR_IAC3 314\r
+#define SPR_IAC4 315\r
+#define SPR_DAC1 316\r
+#define SPR_DAC2 317\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* ends inclusion of #ifndef __MPC5500_SPR_ for one instantiation */\r
+\r
+/*********************************************************************\r
+ *\r
+ * Copyright:\r
+ * Freescale Semiconductor, INC. All Rights Reserved.\r
+ * You are hereby granted a copyright license to use, modify, and\r
+ * distribute the SOFTWARE so long as this entire notice is\r
+ * retained without alteration in any modified and/or redistributed\r
+ * versions, and that such modified versions are clearly identified\r
+ * as such. No licenses are granted by implication, estoppel or\r
+ * otherwise under any patents or trademarks of Freescale\r
+ * Semiconductor, Inc. This software is provided on an "AS IS"\r
+ * basis and without warranty.\r
+ *\r
+ * To the maximum extent permitted by applicable law, Freescale\r
+ * Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,\r
+ * INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A\r
+ * PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH\r
+ * REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF)\r
+ * AND ANY ACCOMPANYING WRITTEN MATERIALS.\r
+ *\r
+ * To the maximum extent permitted by applicable law, IN NO EVENT\r
+ * SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER\r
+ * (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,\r
+ * BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER\r
+ * PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.\r
+ *\r
+ * Freescale Semiconductor assumes no responsibility for the\r
+ * maintenance and support of this software\r
+ *\r
+ ********************************************************************/\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/**************************************************************************/\r
+/* FILE NAME: mpc5516.h COPYRIGHT (c) Freescale 2007 */\r
+/* VERSION: 1.0 All Rights Reserved */\r
+/* */\r
+/* DESCRIPTION: */\r
+/* This file contain all of the register and bit field definitions for */\r
+/* MPC5567. */\r
+/*========================================================================*/\r
+/* UPDATE HISTORY */\r
+/* REV AUTHOR DATE DESCRIPTION OF CHANGE */\r
+/* --- ----------- --------- --------------------- */\r
+/* 1.0 M. Stewart 05/Feb/07 Initial version. */\r
+/**************************************************************************/\r
+/*>>>>NOTE! this file is auto-generated please do not edit it!<<<<*/\r
+\r
+#ifndef _MPC5516_H_\r
+#define _MPC5516_H_\r
+\r
+#define MPC5516 1\r
+\r
+#include "typedefs.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+#ifdef __MWERKS__\r
+#pragma push\r
+#pragma ANSI_strict off\r
+#endif\r
+\r
+/****************************************************************************/\r
+/* MODULE : CRP */\r
+/****************************************************************************/\r
+ struct CRP_tag {\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:12;\r
+ vuint32_t KIRCEN:1;\r
+ vuint32_t XOSCEN:1;\r
+ vuint32_t:1;\r
+ vuint32_t KOSCEN:1;\r
+ vuint32_t TRIM32IRC:8;\r
+ vuint32_t TRIMIRC:8;\r
+ } B;\r
+ } CLKSRC; //Clock Source Register\r
+\r
+ uint32_t crp_reserved1[3];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CNTEN:1;\r
+ vuint32_t RTCIE:1;\r
+ vuint32_t RTCF:1;\r
+ vuint32_t ROVREN:1;\r
+ vuint32_t RTCVAL:12;\r
+ vuint32_t APIEN:1;\r
+ vuint32_t APIIE:1;\r
+ vuint32_t APIF:1;\r
+ vuint32_t CLKSEL:2;\r
+ vuint32_t ROVRF:1;\r
+ vuint32_t APIVAL:10;\r
+ } B;\r
+ } RTCSC; //RTC Status and Control Register\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:5;\r
+ vuint32_t RTCCNT:27;\r
+ } B;\r
+ } RTCCNT; //RTC Counter Register\r
+\r
+ uint32_t crp_reserved2[6];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:27;\r
+ vuint32_t MTEST:1;\r
+ vuint32_t LVIDIS:1;\r
+ vuint32_t VTRIM:3;\r
+ } B;\r
+ } VREGSC; //VREG Trim Satus and Control Register\r
+\r
+ uint32_t crp_reserved3[3];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t WKPSEL7:4;\r
+ vuint32_t WKPSEL6:4;\r
+ vuint32_t WKPSEL5:4;\r
+ vuint32_t WKPSEL4:4;\r
+ vuint32_t WKPSEL3:4;\r
+ vuint32_t WKPSEL2:4;\r
+ vuint32_t WKPSEL1:4;\r
+ vuint32_t WKPSEL0:4;\r
+ } B;\r
+ } WKPINSEL; //Wakeup Pin Source Select Register\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t WKPDET7:2;\r
+ vuint32_t WKPDET6:2;\r
+ vuint32_t WKPDET5:2;\r
+ vuint32_t WKPDET4:2;\r
+ vuint32_t WKPDET3:2;\r
+ vuint32_t WKPDET2:2;\r
+ vuint32_t WKPDET1:2;\r
+ vuint32_t WKPDET0:2;\r
+ vuint32_t:5;\r
+ vuint32_t RTCOVREN:1;\r
+ vuint32_t RTCWKEN:1; /* switched two fields JRichard 16MAY2007*/\r
+ vuint32_t APIWKEN:1;\r
+ vuint32_t:7;\r
+ vuint32_t WKCLKSEL:1;\r
+ } B;\r
+ } WKSE; //Wakeup Source Enable Register \r
+\r
+ /* } WKE; //Wakeup Source Enable Register */\r
+ \r
+\r
+ uint32_t crp_reserved4[2];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t Z1VEC:30;\r
+ vuint32_t Z1RST:1;\r
+ vuint32_t VLE:1;\r
+ } B;\r
+ } Z1VEC; //Z1 Reset Vector Register\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t Z0VEC:30;\r
+ vuint32_t Z0RST:1;\r
+ vuint32_t:1;\r
+ } B;\r
+ } Z0VEC; //Z0 Reset Vector Register\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t RECPTR:30;\r
+ vuint32_t FASTREC:1;\r
+ vuint32_t:1;\r
+ } B;\r
+ } RECPRTR; //Reset Recovery Pointer Register\r
+\r
+ uint32_t crp_reserved5;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t SLEEPF:1;\r
+ vuint32_t STOPF:1;\r
+ vuint32_t:3;\r
+ vuint32_t WKRTCF:1;\r
+ vuint32_t WKAPIF:1;\r
+ vuint32_t WKRLLOVRF:1;\r
+ vuint32_t PWKSRCF:8;\r
+ vuint32_t SLEEP:1;\r
+ vuint32_t STOP:1;\r
+ vuint32_t:1;\r
+ vuint32_t PKREL:1; /* JRichard */\r
+ //vuint32_t PKREN:1; /* JRichard */\r
+ \r
+ vuint32_t STOP12EN:1;\r
+ vuint32_t RAMSEL:3;\r
+ vuint32_t PWKSRIE:8;\r
+ } B;\r
+ } PSCR; //Power Status and Control Register\r
+\r
+ uint32_t crp_reserved6[3];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t LVI5IE:1;\r
+ vuint32_t LVI5HIE:1;\r
+ vuint32_t LVI5F:1;\r
+ vuint32_t LVI5HF:1;\r
+ vuint32_t LVILOCK:1;\r
+ vuint32_t LVI5RE:1;\r
+ vuint32_t:26;\r
+ } B;\r
+ } LVISC; //LVI Status and Control Register\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : DMAMUX */\r
+/****************************************************************************/\r
+ struct DMAMUX_tag {\r
+ union {\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t ENBL:1;\r
+ vuint8_t TRIG:1;\r
+ vuint8_t SOURCE:6;\r
+ } B;\r
+ } CHCONFIG[16]; /* DMA Channel Configuration Register */\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : DSPI */\r
+/****************************************************************************/\r
+ struct DSPI_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MSTR:1;\r
+ vuint32_t CONT_SCKE:1;\r
+ vuint32_t DCONF:2;\r
+ vuint32_t FRZ:1;\r
+ vuint32_t MTFE:1;\r
+ vuint32_t PCSSE:1;\r
+ vuint32_t ROOE:1;\r
+ vuint32_t:2;\r
+ vuint32_t PCSIS5:1;\r
+ vuint32_t PCSIS4:1;\r
+ vuint32_t PCSIS3:1;\r
+ vuint32_t PCSIS2:1;\r
+ vuint32_t PCSIS1:1;\r
+ vuint32_t PCSIS0:1;\r
+ vuint32_t DOZE:1;\r
+ vuint32_t MDIS:1;\r
+ vuint32_t DIS_TXF:1;\r
+ vuint32_t DIS_RXF:1;\r
+ vuint32_t CLR_TXF:1;\r
+ vuint32_t CLR_RXF:1;\r
+ vuint32_t SMPL_PT:2;\r
+ vuint32_t:7;\r
+ vuint32_t HALT:1;\r
+ } B;\r
+ } MCR; /* Module Configuration Register */\r
+\r
+ uint32_t dspi_reserved1;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TCNT:16;\r
+ vuint32_t:16;\r
+ } B;\r
+ } TCR;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DBR:1;\r
+ vuint32_t FMSZ:4;\r
+ vuint32_t CPOL:1;\r
+ vuint32_t CPHA:1;\r
+ vuint32_t LSBFE:1;\r
+ vuint32_t PCSSCK:2;\r
+ vuint32_t PASC:2;\r
+ vuint32_t PDT:2;\r
+ vuint32_t PBR:2;\r
+ vuint32_t CSSCK:4;\r
+ vuint32_t ASC:4;\r
+ vuint32_t DT:4;\r
+ vuint32_t BR:4;\r
+ } B;\r
+ } CTAR[8]; /* Clock and Transfer Attributes Registers */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TCF:1;\r
+ vuint32_t TXRXS:1;\r
+ vuint32_t:1;\r
+ vuint32_t EOQF:1;\r
+ vuint32_t TFUF:1;\r
+ vuint32_t:1;\r
+ vuint32_t TFFF:1;\r
+ vuint32_t:5;\r
+ vuint32_t RFOF:1;\r
+ vuint32_t:1;\r
+ vuint32_t RFDF:1;\r
+ vuint32_t:1;\r
+ vuint32_t TXCTR:4;\r
+ vuint32_t TXNXTPTR:4;\r
+ vuint32_t RXCTR:4;\r
+ vuint32_t POPNXTPTR:4;\r
+ } B;\r
+ } SR; /* Status Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TCFRE:1;\r
+ vuint32_t:2;\r
+ vuint32_t EOQFRE:1;\r
+ vuint32_t TFUFRE:1;\r
+ vuint32_t:1;\r
+ vuint32_t TFFFRE:1;\r
+ vuint32_t TFFFDIRS:1;\r
+ vuint32_t:4;\r
+ vuint32_t RFOFRE:1;\r
+ vuint32_t:1;\r
+ vuint32_t RFDFRE:1;\r
+ vuint32_t RFDFDIRS:1;\r
+ vuint32_t:16;\r
+ } B;\r
+ } RSER; /* DMA/Interrupt Request Select and Enable Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CONT:1;\r
+ vuint32_t CTAS:3;\r
+ vuint32_t EOQ:1;\r
+ vuint32_t CTCNT:1;\r
+ vuint32_t:4;\r
+ vuint32_t PCS5:1;\r
+ vuint32_t PCS4:1;\r
+ vuint32_t PCS3:1;\r
+ vuint32_t PCS2:1;\r
+ vuint32_t PCS1:1;\r
+ vuint32_t PCS0:1;\r
+ vuint32_t TXDATA:16;\r
+ } B;\r
+ } PUSHR; /* PUSH TX FIFO Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t RXDATA:16;\r
+ } B;\r
+ } POPR; /* POP RX FIFO Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TXCMD:16;\r
+ vuint32_t TXDATA:16;\r
+ } B;\r
+ } TXFR[4]; /* Transmit FIFO Registers */\r
+\r
+ vuint32_t DSPI_reserved_txf[12];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t RXDATA:16;\r
+ } B;\r
+ } RXFR[4]; /* Transmit FIFO Registers */\r
+\r
+ vuint32_t DSPI_reserved_rxf[12];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MTOE:1;\r
+ vuint32_t:1;\r
+ vuint32_t MTOCNT:6;\r
+ vuint32_t:4;\r
+ vuint32_t TXSS:1;\r
+ vuint32_t TPOL:1;\r
+ vuint32_t TRRE:1;\r
+ vuint32_t CID:1;\r
+ vuint32_t DCONT:1;\r
+ vuint32_t DSICTAS:3;\r
+ vuint32_t:6;\r
+ vuint32_t DPCS5:1;\r
+ vuint32_t DPCS4:1;\r
+ vuint32_t DPCS3:1;\r
+ vuint32_t DPCS2:1;\r
+ vuint32_t DPCS1:1;\r
+ vuint32_t DPCS0:1;\r
+ } B;\r
+ } DSICR; /* DSI Configuration Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t SER_DATA:16;\r
+ } B;\r
+ } SDR; /* DSI Serialization Data Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t ASER_DATA:16;\r
+ } B;\r
+ } ASDR; /* DSI Alternate Serialization Data Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t COMP_DATA:16;\r
+ } B;\r
+ } COMPR; /* DSI Transmit Comparison Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t DESER_DATA:16;\r
+ } B;\r
+ } DDR; /* DSI deserialization Data Register */\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : External Bus Interface (EBI) */\r
+/****************************************************************************/\r
+ struct CS_tag {\r
+ union { /* Base Register Bank */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BA:17;\r
+ vuint32_t:3;\r
+ vuint32_t PS:1;\r
+ vuint32_t:4;\r
+ vuint32_t BL:1;\r
+ vuint32_t WEBS:1;\r
+ vuint32_t TBDIP:1;\r
+ vuint32_t:2;\r
+ vuint32_t BI:1;\r
+ vuint32_t V:1;\r
+ } B;\r
+ } BR;\r
+\r
+ union { /* Option Register Bank */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t AM:17;\r
+ vuint32_t:7;\r
+ vuint32_t SCY:4;\r
+ vuint32_t:1;\r
+ vuint32_t BSCY:2;\r
+ vuint32_t:1;\r
+ } B;\r
+ } OR;\r
+ };\r
+\r
+ struct EBI_tag {\r
+ union { /* Module Configuration Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:5;\r
+ vuint32_t SIZEEN:1;\r
+ vuint32_t SIZE:2;\r
+ vuint32_t:8;\r
+ vuint32_t ACGE:1;\r
+ vuint32_t EXTM:1;\r
+ vuint32_t EARB:1;\r
+ vuint32_t EARP:2;\r
+ vuint32_t:4;\r
+ vuint32_t MDIS:1;\r
+ vuint32_t:5;\r
+ vuint32_t DBM:1;\r
+ } B;\r
+ } MCR;\r
+\r
+ uint32_t EBI_reserved1;\r
+\r
+ union { /* Transfer Error Status Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:30;\r
+ vuint32_t TEAF:1;\r
+ vuint32_t BMTF:1;\r
+ } B;\r
+ } TESR;\r
+\r
+ union { /* Bus Monitor Control Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t BMT:8;\r
+ vuint32_t BME:1;\r
+ vuint32_t:7;\r
+ } B;\r
+ } BMCR;\r
+\r
+ struct CS_tag CS[4];\r
+\r
+ uint32_t EBI_reserved2[4];\r
+\r
+ /* Calibration registers */\r
+ struct CS_tag CAL_CS[4];\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : eDMA */\r
+/****************************************************************************/\r
+ struct EDMA_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:23;\r
+ vuint32_t GRP0PRI:1;\r
+ vuint32_t:4;\r
+ vuint32_t ERGA:1;\r
+ vuint32_t ERCA:1;\r
+ vuint32_t EDBG:1;\r
+ vuint32_t:1;\r
+ } B;\r
+ } CR; /* Control Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t VLD:1;\r
+ vuint32_t:15;\r
+ vuint32_t GPE:1;\r
+ vuint32_t CPE:1;\r
+ vuint32_t ERRCHN:6;\r
+ vuint32_t SAE:1;\r
+ vuint32_t SOE:1;\r
+ vuint32_t DAE:1;\r
+ vuint32_t DOE:1;\r
+ vuint32_t NCE:1;\r
+ vuint32_t SGE:1;\r
+ vuint32_t SBE:1;\r
+ vuint32_t DBE:1;\r
+ } B;\r
+ } ESR; /* Error Status Register */\r
+\r
+ int32_t EDMA_reserved1;\r
+ int8_t EDMA_reserved5; /* JRichard 26MAR2007 */\r
+\r
+ union {\r
+ //vuint32_t R; /* JRichard 26MAR2007 */\r
+ vuint16_t R;\r
+ struct {\r
+ //vuint32_t:16; /* JRichard 26MAR2007 changed all bits to vuint16's */\r
+ vuint16_t ERQ15:1;\r
+ vuint16_t ERQ14:1;\r
+ vuint16_t ERQ13:1;\r
+ vuint16_t ERQ12:1;\r
+ vuint16_t ERQ11:1;\r
+ vuint16_t ERQ10:1;\r
+ vuint16_t ERQ09:1;\r
+ vuint16_t ERQ08:1;\r
+ vuint16_t ERQ07:1;\r
+ vuint16_t ERQ06:1;\r
+ vuint16_t ERQ05:1;\r
+ vuint16_t ERQ04:1;\r
+ vuint16_t ERQ03:1;\r
+ vuint16_t ERQ02:1;\r
+ vuint16_t ERQ01:1;\r
+ vuint16_t ERQ00:1;\r
+ } B;\r
+ } ERQRL; /* DMA Enable Request Register Low */\r
+\r
+ int32_t EDMA_reserved2;\r
+ int8_t EDMA_reserved6; /* JRichard 26MAR2007 */\r
+\r
+ union {\r
+ //vuint32_t R; /* JRichard 26MAR2007*/\r
+ vuint16_t R;\r
+ struct {\r
+ //vuint32_t:16; /* JRichard 26MAR2007 changed all bits to vuint16's */\r
+ vuint16_t EEI15:1;\r
+ vuint16_t EEI14:1;\r
+ vuint16_t EEI13:1;\r
+ vuint16_t EEI12:1;\r
+ vuint16_t EEI11:1;\r
+ vuint16_t EEI10:1;\r
+ vuint16_t EEI09:1;\r
+ vuint16_t EEI08:1;\r
+ vuint16_t EEI07:1;\r
+ vuint16_t EEI06:1;\r
+ vuint16_t EEI05:1;\r
+ vuint16_t EEI04:1;\r
+ vuint16_t EEI03:1;\r
+ vuint16_t EEI02:1;\r
+ vuint16_t EEI01:1;\r
+ vuint16_t EEI00:1;\r
+ } B;\r
+ } EEIRL; /* DMA Enable Error Interrupt Register Low */\r
+\r
+ union {\r
+ vuint8_t R;\r
+ vuint8_t B;\r
+ } SERQR; /* DMA Set Enable Request Register */\r
+\r
+ union {\r
+ vuint8_t R;\r
+ vuint8_t B;\r
+ } CERQR; /* DMA Clear Enable Request Register */\r
+\r
+ union {\r
+ vuint8_t R;\r
+ vuint8_t B;\r
+ } SEEIR; /* DMA Set Enable Error Interrupt Register */\r
+\r
+ union {\r
+ vuint8_t R;\r
+ vuint8_t B;\r
+ } CEEIR; /* DMA Clear Enable Error Interrupt Register */\r
+\r
+ union {\r
+ vuint8_t R;\r
+ vuint8_t B;\r
+ } CIRQR; /* DMA Clear Interrupt Request Register */\r
+\r
+ union {\r
+ vuint8_t R;\r
+ vuint8_t B;\r
+ } CER; /* DMA Clear error Register */\r
+\r
+ union {\r
+ vuint8_t R;\r
+ vuint8_t B;\r
+ } SSBR; /* Set Start Bit Register */\r
+\r
+ union {\r
+ vuint8_t R;\r
+ vuint8_t B;\r
+ } CDSBR; /* Clear Done Status Bit Register */\r
+\r
+ int32_t EDMA_reserved3;\r
+ int8_t EDMA_reserved7; /* JRichard 26MAR2007 */\r
+\r
+ union {\r
+ //vuint32_t R; /* JRichard 26MAR2007*/\r
+ vuint16_t R;\r
+ struct {\r
+ //vuint32_t:16; /* JRichard 26MAR2007 changed all bits to vuint16's */\r
+ vuint16_t INT15:1;\r
+ vuint16_t INT14:1;\r
+ vuint16_t INT13:1;\r
+ vuint16_t INT12:1;\r
+ vuint16_t INT11:1;\r
+ vuint16_t INT10:1;\r
+ vuint16_t INT09:1;\r
+ vuint16_t INT08:1;\r
+ vuint16_t INT07:1;\r
+ vuint16_t INT06:1;\r
+ vuint16_t INT05:1;\r
+ vuint16_t INT04:1;\r
+ vuint16_t INT03:1;\r
+ vuint16_t INT02:1;\r
+ vuint16_t INT01:1;\r
+ vuint16_t INT00:1;\r
+ } B;\r
+ } IRQRL; /* DMA Interrupt Request Low */\r
+\r
+ int32_t EDMA_reserved4;\r
+ int8_t EDMA_reserved8; /* JRichard 26MAR2007 */\r
+\r
+ union {\r
+ //vuint32_t R; /* JRichard 26MAR2007*/\r
+ vuint16_t R;\r
+ struct {\r
+ //vuint32_t:16; /* JRichard 26MAR2007 changed all bits to vuint16's */\r
+ vuint16_t ERR15:1;\r
+ vuint16_t ERR14:1;\r
+ vuint16_t ERR13:1;\r
+ vuint16_t ERR12:1;\r
+ vuint16_t ERR11:1;\r
+ vuint16_t ERR10:1;\r
+ vuint16_t ERR09:1;\r
+ vuint16_t ERR08:1;\r
+ vuint16_t ERR07:1;\r
+ vuint16_t ERR06:1;\r
+ vuint16_t ERR05:1;\r
+ vuint16_t ERR04:1;\r
+ vuint16_t ERR03:1;\r
+ vuint16_t ERR02:1;\r
+ vuint16_t ERR01:1;\r
+ vuint16_t ERR00:1;\r
+ } B;\r
+ } ERL; /* DMA Error Low */\r
+\r
+ uint32_t edma_reserved1[52];\r
+\r
+ union {\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t ECP:1;\r
+ vuint8_t:1;\r
+ vuint8_t GRPPRI:2;\r
+ vuint8_t CHPRI:4;\r
+ } B;\r
+ } CPR[16]; /* Channel n Priority */\r
+\r
+ uint32_t edma_reserved2[956];\r
+\r
+/****************************************************************************/\r
+/* DMA2 Transfer Control Descriptor */\r
+/****************************************************************************/\r
+\r
+ struct tcd_t { /*for "standard" format TCDs (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=0 && EDMA.EMLM=0 ) */\r
+ vuint32_t SADDR; /* source address */\r
+\r
+ vuint16_t SMOD:5; /* source address modulo */\r
+ vuint16_t SSIZE:3; /* source transfer size */\r
+ vuint16_t DMOD:5; /* destination address modulo */\r
+ vuint16_t DSIZE:3; /* destination transfer size */\r
+ vint16_t SOFF; /* signed source address offset */\r
+\r
+ vuint32_t NBYTES; /* inner (\93minor\94) byte count */\r
+\r
+ vint32_t SLAST; /* last destination address adjustment, or\r
+\r
+ scatter/gather address (if e_sg = 1) */\r
+ vuint32_t DADDR; /* destination address */\r
+\r
+ vuint16_t CITERE_LINK:1;\r
+ vuint16_t CITER:15;\r
+\r
+ vint16_t DOFF; /* signed destination address offset */\r
+\r
+ vint32_t DLAST_SGA;\r
+\r
+ vuint16_t BITERE_LINK:1; /* beginning ("major") iteration count */\r
+ vuint16_t BITER:15;\r
+\r
+ vuint16_t BWC:2; /* bandwidth control */\r
+ vuint16_t MAJORLINKCH:6; /* enable channel-to-channel link */\r
+ vuint16_t DONE:1; /* channel done */\r
+ vuint16_t ACTIVE:1; /* channel active */\r
+ vuint16_t MAJORE_LINK:1; /* enable channel-to-channel link */\r
+ vuint16_t E_SG:1; /* enable scatter/gather descriptor */\r
+ vuint16_t D_REQ:1; /* disable ipd_req when done */\r
+ vuint16_t INT_HALF:1; /* interrupt on citer = (biter >> 1) */\r
+ vuint16_t INT_MAJ:1; /* interrupt on major loop completion */\r
+ vuint16_t START:1; /* explicit channel start */\r
+ } TCD[16]; /* transfer_control_descriptor */\r
+\r
+ };\r
+\r
+ struct EDMA_TCD_alt1_tag { /*for alternate format TCDs (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=1 ) */\r
+\r
+ struct tcd_alt1_t {\r
+ vuint32_t SADDR; /* source address */\r
+\r
+ vuint16_t SMOD:5; /* source address modulo */\r
+ vuint16_t SSIZE:3; /* source transfer size */\r
+ vuint16_t DMOD:5; /* destination address modulo */\r
+ vuint16_t DSIZE:3; /* destination transfer size */\r
+ vint16_t SOFF; /* signed source address offset */\r
+\r
+ vuint32_t NBYTES; /* inner (\93minor\94) byte count */\r
+\r
+ vint32_t SLAST; /* last destination address adjustment, or\r
+\r
+ scatter/gather address (if e_sg = 1) */\r
+ vuint32_t DADDR; /* destination address */\r
+\r
+ vuint16_t CITERE_LINK:1;\r
+ vuint16_t CITERLINKCH:6;\r
+ vuint16_t CITER:9;\r
+\r
+ vint16_t DOFF; /* signed destination address offset */\r
+\r
+ vint32_t DLAST_SGA;\r
+\r
+ vuint16_t BITERE_LINK:1; /* beginning (\93major\94) iteration count */\r
+ vuint16_t BITERLINKCH:6;\r
+ vuint16_t BITER:9;\r
+\r
+ vuint16_t BWC:2; /* bandwidth control */\r
+ vuint16_t MAJORLINKCH:6; /* enable channel-to-channel link */\r
+ vuint16_t DONE:1; /* channel done */\r
+ vuint16_t ACTIVE:1; /* channel active */\r
+ vuint16_t MAJORE_LINK:1; /* enable channel-to-channel link */\r
+ vuint16_t E_SG:1; /* enable scatter/gather descriptor */\r
+ vuint16_t D_REQ:1; /* disable ipd_req when done */\r
+ vuint16_t INT_HALF:1; /* interrupt on citer = (biter >> 1) */\r
+ vuint16_t INT_MAJ:1; /* interrupt on major loop completion */\r
+ vuint16_t START:1; /* explicit channel start */\r
+ } TCD[16]; /* transfer_control_descriptor */\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : EMIOS */\r
+/****************************************************************************/\r
+ struct EMIOS_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DOZEEN:1;\r
+ vuint32_t MDIS:1;\r
+ vuint32_t FRZ:1;\r
+ vuint32_t GTBE:1;\r
+ vuint32_t ETB:1;\r
+ vuint32_t GPREN:1;\r
+ vuint32_t:6;\r
+ vuint32_t SRV:4;\r
+ vuint32_t GPRE:8;\r
+ vuint32_t:8;\r
+ } B;\r
+ } MCR; /* Module Configuration Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:8;\r
+ vuint32_t F23:1;\r
+ vuint32_t F22:1;\r
+ vuint32_t F21:1;\r
+ vuint32_t F20:1;\r
+ vuint32_t F19:1;\r
+ vuint32_t F18:1;\r
+ vuint32_t F17:1;\r
+ vuint32_t F16:1;\r
+ vuint32_t F15:1;\r
+ vuint32_t F14:1;\r
+ vuint32_t F13:1;\r
+ vuint32_t F12:1;\r
+ vuint32_t F11:1;\r
+ vuint32_t F10:1;\r
+ vuint32_t F9:1;\r
+ vuint32_t F8:1;\r
+ vuint32_t F7:1;\r
+ vuint32_t F6:1;\r
+ vuint32_t F5:1;\r
+ vuint32_t F4:1;\r
+ vuint32_t F3:1;\r
+ vuint32_t F2:1;\r
+ vuint32_t F1:1;\r
+ vuint32_t F0:1;\r
+ } B;\r
+ } GFLAG; /* Global FLAG Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:8;\r
+ vuint32_t OU23:1;\r
+ vuint32_t OU22:1;\r
+ vuint32_t OU21:1;\r
+ vuint32_t OU20:1;\r
+ vuint32_t OU19:1;\r
+ vuint32_t OU18:1;\r
+ vuint32_t OU17:1;\r
+ vuint32_t OU16:1;\r
+ vuint32_t OU15:1;\r
+ vuint32_t OU14:1;\r
+ vuint32_t OU13:1;\r
+ vuint32_t OU12:1;\r
+ vuint32_t OU11:1;\r
+ vuint32_t OU10:1;\r
+ vuint32_t OU9:1;\r
+ vuint32_t OU8:1;\r
+ vuint32_t OU7:1;\r
+ vuint32_t OU6:1;\r
+ vuint32_t OU5:1;\r
+ vuint32_t OU4:1;\r
+ vuint32_t OU3:1;\r
+ vuint32_t OU2:1;\r
+ vuint32_t OU1:1;\r
+ vuint32_t OU0:1;\r
+ } B;\r
+ } OUDIS; /* Output Update Disable Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } UCDIS; /* Disable Channel Register */\r
+\r
+ uint32_t emios_reserved1[4];\r
+\r
+ struct {\r
+ union {\r
+ vuint32_t R; /* Channel A Data Register */\r
+ //} A;\r
+ } CADR; /* JRichard */\r
+\r
+ union {\r
+ vuint32_t R; /* Channel B Data Register */\r
+ //} B;\r
+ } CBDR; /* JRichard */\r
+\r
+ union {\r
+ vuint32_t R; /* Channel Counter Register */\r
+ //} CNT;\r
+ } CCNTR; /* JRichard */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t FREN:1;\r
+ vuint32_t ODIS:1;\r
+ vuint32_t ODISSL:2;\r
+ vuint32_t UCPRE:2;\r
+ vuint32_t UCPREN:1;\r
+// vuint32_t UCPEN:1; /* JRichard 16MAY2007 */\r
+ vuint32_t DMA:1;\r
+ vuint32_t:1;\r
+ vuint32_t IF:4;\r
+ vuint32_t FCK:1;\r
+ vuint32_t FEN:1;\r
+ vuint32_t:3;\r
+ vuint32_t FORCMA:1;\r
+ vuint32_t FORCMB:1;\r
+ vuint32_t:1;\r
+ vuint32_t BSL:2;\r
+ vuint32_t EDSEL:1;\r
+ vuint32_t EDPOL:1;\r
+ vuint32_t MODE:7;\r
+ } B;\r
+ } CCR; /* Channel Control Register */\r
+ //} C; /* Channel Control Register */ /* JRichard*/\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t OVR:1;\r
+ vuint32_t:15;\r
+ vuint32_t OVFL:1;\r
+ vuint32_t:12;\r
+ vuint32_t UCIN:1;\r
+ vuint32_t UCOUT:1;\r
+ vuint32_t FLAG:1;\r
+ } B;\r
+ } CSR;\r
+ //} S; /* JRichard Channel Status Register */\r
+\r
+ union {\r
+ vuint32_t R; /* Alternate Channel A Data Register */\r
+ } ALTA;\r
+\r
+ uint32_t emios_channel_reserved[2];\r
+\r
+ } CH[24];\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : EQADC */\r
+/****************************************************************************/\r
+ struct EQADC_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:27;\r
+ vuint32_t ESSIE:2;\r
+ vuint32_t:1;\r
+ vuint32_t DBG:2;\r
+ } B;\r
+ } MCR; /* Module Configuration Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } TST; /* Test Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:6;\r
+ vuint32_t NMF:26;\r
+ } B;\r
+ } NMSFR; /* Null Message Send Format Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:28;\r
+ vuint32_t DFL:4;\r
+ } B;\r
+ } ETDFR; /* External Trigger Digital Filter Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CFPUSH:32;\r
+ } B;\r
+ } CFPR[6]; /* CFIFO Push Registers */\r
+\r
+ uint32_t eqadc_reserved1;\r
+\r
+ uint32_t eqadc_reserved2;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t RFPOP:16;\r
+ } B;\r
+ } RFPR[6]; /* Result FIFO Pop Registers */\r
+\r
+ uint32_t eqadc_reserved3;\r
+\r
+ uint32_t eqadc_reserved4;\r
+\r
+ union {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:5;\r
+ vuint16_t SSE:1;\r
+ vuint16_t CFINV:1;\r
+ vuint16_t:1;\r
+ vuint16_t MODE:4;\r
+ vuint16_t:4;\r
+ } B;\r
+ } CFCR[6]; /* CFIFO Control Registers */\r
+\r
+ uint32_t eqadc_reserved5;\r
+\r
+ union {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t NCIE:1;\r
+ vuint16_t TORIE:1;\r
+ vuint16_t PIE:1;\r
+ vuint16_t EOQIE:1;\r
+ vuint16_t CFUIE:1;\r
+ vuint16_t:1;\r
+ vuint16_t CFFE:1;\r
+ vuint16_t CFFS:1;\r
+ vuint16_t:4;\r
+ vuint16_t RFOIE:1;\r
+ vuint16_t:1;\r
+ vuint16_t RFDE:1;\r
+ vuint16_t RFDS:1;\r
+ } B;\r
+ } IDCR[6]; /* Interrupt and DMA Control Registers */\r
+\r
+ uint32_t eqadc_reserved6;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t NCF:1;\r
+ vuint32_t TORF:1;\r
+ vuint32_t PF:1;\r
+ vuint32_t EOQF:1;\r
+ vuint32_t CFUF:1;\r
+ vuint32_t SSS:1;\r
+ vuint32_t CFFF:1;\r
+ vuint32_t:5;\r
+ vuint32_t RFOF:1;\r
+ vuint32_t:1;\r
+ vuint32_t RFDF:1;\r
+ vuint32_t:1;\r
+ vuint32_t CFCTR:4;\r
+ vuint32_t TNXTPTR:4;\r
+ vuint32_t RFCTR:4;\r
+ vuint32_t POPNXTPTR:4;\r
+ } B;\r
+ } FISR[6]; /* FIFO and Interrupt Status Registers */\r
+\r
+ uint32_t eqadc_reserved7;\r
+\r
+ uint32_t eqadc_reserved8;\r
+\r
+ union {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:5;\r
+ vuint16_t TCCF:11;\r
+ } B;\r
+ } CFTCR[6]; /* CFIFO Transfer Counter Registers */\r
+\r
+ uint32_t eqadc_reserved9;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CFS0:2;\r
+ vuint32_t CFS1:2;\r
+ vuint32_t CFS2:2;\r
+ vuint32_t CFS3:2;\r
+ vuint32_t CFS4:2;\r
+ vuint32_t CFS5:2;\r
+ vuint32_t:5;\r
+ vuint32_t LCFTCB0:4;\r
+ vuint32_t TC_LCFTCB0:11;\r
+ } B;\r
+ } CFSSR0; /* CFIFO Status Register 0 */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CFS0:2;\r
+ vuint32_t CFS1:2;\r
+ vuint32_t CFS2:2;\r
+ vuint32_t CFS3:2;\r
+ vuint32_t CFS4:2;\r
+ vuint32_t CFS5:2;\r
+ vuint32_t:5;\r
+ vuint32_t LCFTCB1:4;\r
+ vuint32_t TC_LCFTCB1:11;\r
+ } B;\r
+ } CFSSR1; /* CFIFO Status Register 1 */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CFS0:2;\r
+ vuint32_t CFS1:2;\r
+ vuint32_t CFS2:2;\r
+ vuint32_t CFS3:2;\r
+ vuint32_t CFS4:2;\r
+ vuint32_t CFS5:2;\r
+ vuint32_t:4;\r
+ vuint32_t ECBNI:1;\r
+ vuint32_t LCFTSSI:4;\r
+ vuint32_t TC_LCFTSSI:11;\r
+ } B;\r
+ } CFSSR2; /* CFIFO Status Register 2 */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CFS0:2;\r
+ vuint32_t CFS1:2;\r
+ vuint32_t CFS2:2;\r
+ vuint32_t CFS3:2;\r
+ vuint32_t CFS4:2;\r
+ vuint32_t CFS5:2;\r
+ vuint32_t:20;\r
+ } B;\r
+ } CFSR;\r
+\r
+ uint32_t eqadc_reserved11;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:21;\r
+ vuint32_t MDT:3;\r
+ vuint32_t:4;\r
+ vuint32_t BR:4;\r
+ } B;\r
+ } SSICR; /* SSI Control Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t RDV:1;\r
+ vuint32_t:5;\r
+ vuint32_t RDATA:26;\r
+ } B;\r
+ } SSIRDR; /* SSI Recieve Data Register */\r
+\r
+ uint32_t eqadc_reserved12[17];\r
+\r
+ struct {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:32;\r
+ } B;\r
+ } R[4];\r
+\r
+ uint32_t eqadc_reserved13[12];\r
+\r
+ } CF[6];\r
+\r
+ uint32_t eqadc_reserved14[32];\r
+\r
+ struct {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:32;\r
+ } B;\r
+ } R[4];\r
+\r
+ uint32_t eqadc_reserved15[12];\r
+\r
+ } RF[6];\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : eSCI */\r
+/****************************************************************************/\r
+ struct ESCI_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:3;\r
+ vuint32_t SBR:13;\r
+ vuint32_t LOOPS:1;\r
+ vuint32_t:1;\r
+ vuint32_t RSRC:1;\r
+ vuint32_t M:1;\r
+ vuint32_t WAKE:1;\r
+ vuint32_t ILT:1;\r
+ vuint32_t PE:1;\r
+ vuint32_t PT:1;\r
+ vuint32_t TIE:1;\r
+ vuint32_t TCIE:1;\r
+ vuint32_t RIE:1;\r
+ vuint32_t ILIE:1;\r
+ vuint32_t TE:1;\r
+ vuint32_t RE:1;\r
+ vuint32_t RWU:1;\r
+ vuint32_t SBK:1;\r
+ } B;\r
+ } CR1; /* Control Register 1 */\r
+\r
+ union {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t MDIS:1;\r
+ vuint16_t FBR:1;\r
+ vuint16_t BSTP:1;\r
+ vuint16_t IEBERR:1;\r
+ vuint16_t RXDMA:1;\r
+ vuint16_t TXDMA:1;\r
+ vuint16_t BRK13:1;\r
+ vuint16_t:1;\r
+ vuint16_t BESM13:1;\r
+ vuint16_t SBSTP:1;\r
+ vuint16_t:2;\r
+ vuint16_t ORIE:1;\r
+ vuint16_t NFIE:1;\r
+ vuint16_t FEIE:1;\r
+ vuint16_t PFIE:1;\r
+ } B;\r
+ } CR2; /* Control Register 2 */\r
+\r
+ union {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t R8:1;\r
+ vuint16_t T8:1;\r
+ vuint16_t:6;\r
+ vuint8_t D;\r
+ } B;\r
+ } DR; /* Data Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TDRE:1;\r
+ vuint32_t TC:1;\r
+ vuint32_t RDRF:1;\r
+ vuint32_t IDLE:1;\r
+ vuint32_t OR:1;\r
+ vuint32_t NF:1;\r
+ vuint32_t FE:1;\r
+ vuint32_t PF:1;\r
+ vuint32_t:3;\r
+ vuint32_t BERR:1;\r
+ vuint32_t:3;\r
+ vuint32_t RAF:1;\r
+ vuint32_t RXRDY:1;\r
+ vuint32_t TXRDY:1;\r
+ vuint32_t LWAKE:1;\r
+ vuint32_t STO:1;\r
+ vuint32_t PBERR:1;\r
+ vuint32_t CERR:1;\r
+ vuint32_t CKERR:1;\r
+ vuint32_t FRC:1;\r
+ vuint32_t:7;\r
+ vuint32_t OVFL:1;\r
+ } B;\r
+ } SR; /* Status Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t LRES:1;\r
+ vuint32_t WU:1;\r
+ vuint32_t WUD0:1;\r
+ vuint32_t WUD1:1;\r
+ vuint32_t LDBG:1;\r
+ vuint32_t DSF:1;\r
+ vuint32_t PRTY:1;\r
+ vuint32_t LIN:1;\r
+ vuint32_t RXIE:1;\r
+ vuint32_t TXIE:1;\r
+ vuint32_t WUIE:1;\r
+ vuint32_t STIE:1;\r
+ vuint32_t PBIE:1;\r
+ vuint32_t CIE:1;\r
+ vuint32_t CKIE:1;\r
+ vuint32_t FCIE:1;\r
+ vuint32_t:7;\r
+ vuint32_t OFIE:1;\r
+ vuint32_t:8;\r
+ } B;\r
+ } LCR; /* LIN Control Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } LTR; /* LIN Transmit Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } LRR; /* LIN Recieve Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } LPR; /* LIN CRC Polynom Register */\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : FLASH */\r
+/****************************************************************************/\r
+ struct FLASH_tag {\r
+ union { /* Module Configuration Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:3;\r
+ vuint32_t SFS:1;\r
+ vuint32_t SIZE:4;\r
+ vuint32_t:1;\r
+ vuint32_t LAS:3;\r
+ vuint32_t:3;\r
+ vuint32_t MAS:1;\r
+ vuint32_t EER:1;\r
+ vuint32_t RWE:1;\r
+ vuint32_t BBEPE:1;\r
+ vuint32_t EPE:1;\r
+ vuint32_t PEAS:1;\r
+ vuint32_t DONE:1;\r
+ vuint32_t PEG:1;\r
+ vuint32_t:1;\r
+ vuint32_t PRD:1;\r
+ vuint32_t STOP:1;\r
+ vuint32_t:1;\r
+ vuint32_t PGM:1;\r
+ vuint32_t PSUS:1;\r
+ vuint32_t ERS:1;\r
+ vuint32_t ESUS:1;\r
+ vuint32_t EHV:1;\r
+ } B;\r
+ } MCR;\r
+\r
+ union { /* LML Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t LME:1;\r
+ vuint32_t:10;\r
+ vuint32_t SLOCK:1;\r
+ vuint32_t:2;\r
+ vuint32_t MLOCK:2;\r
+ vuint32_t:8;\r
+ vuint32_t LLOCK:8;\r
+ } B;\r
+ } LMLR;\r
+ //} LML; /* JRichard 7MAR2007 */\r
+\r
+ union { /* HL Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t HBE:1;\r
+ vuint32_t:27;\r
+ vuint32_t HBLOCK:4;\r
+ } B;\r
+ } HLR;\r
+ //} HBL; /* JRichard 7MAR2007 */\r
+\r
+ union { /* SLML Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t SLE:1;\r
+ vuint32_t:10;\r
+ vuint32_t SSLOCK:1;\r
+ vuint32_t:2;\r
+ vuint32_t SMLOCK:2;\r
+ vuint32_t:8;\r
+ vuint32_t SLLOCK:8;\r
+ } B;\r
+ } SLMLR;\r
+ //} SLL; /* JRichard 7MAR2007 */\r
+\r
+ union { /* LMS Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:14;\r
+ vuint32_t MSEL:2;\r
+ vuint32_t:8;\r
+ vuint32_t LSEL:8;\r
+ } B;\r
+ } LMSR;\r
+ //} LMS; /* JRichard 7MAR2007 */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:28;\r
+ vuint32_t HBSEL:4;\r
+ } B;\r
+ } HSR;\r
+ //} HBS; /* JRichard 7MAR2007 */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:10;\r
+ vuint32_t ADDR:19;\r
+ vuint32_t:3;\r
+ } B;\r
+ } ADR;\r
+\r
+ union { /* Platform Flash Configuration Register for Port 0 */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t LBCFG:4;\r
+ vuint32_t ARB:1;\r
+ vuint32_t PRI:1;\r
+ vuint32_t:2;\r
+ vuint32_t M7PFE:1;\r
+ vuint32_t M6PFE:1;\r
+ vuint32_t M5PFE:1;\r
+ vuint32_t M4PFE:1;\r
+ vuint32_t M3PFE:1;\r
+ vuint32_t M2PFE:1;\r
+ vuint32_t M1PFE:1;\r
+ vuint32_t M0PFE:1;\r
+ vuint32_t APC:3;\r
+ vuint32_t WWSC:2;\r
+ vuint32_t RWSC:3;\r
+ vuint32_t:1;\r
+ vuint32_t DPFEN:1;\r
+ vuint32_t:1;\r
+ vuint32_t IPFEN:1;\r
+ vuint32_t:1;\r
+ vuint32_t PFLIM:2;\r
+ vuint32_t BFEN:1;\r
+ } B;\r
+ } PFCRP0;\r
+\r
+ union { /* Platform Flash Configuration Register for Port 1 */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t LBCFG:4;\r
+ vuint32_t:4;\r
+ vuint32_t M7PFE:1;\r
+ vuint32_t M6PFE:1;\r
+ vuint32_t M5PFE:1;\r
+ vuint32_t M4PFE:1;\r
+ vuint32_t M3PFE:1;\r
+ vuint32_t M2PFE:1;\r
+ vuint32_t M1PFE:1;\r
+ vuint32_t M0PFE:1;\r
+ vuint32_t APC:3;\r
+ vuint32_t WWSC:2;\r
+ vuint32_t RWSC:3;\r
+ vuint32_t:1;\r
+ vuint32_t DPFEN:1;\r
+ vuint32_t:1;\r
+ vuint32_t IPFEN:1;\r
+ vuint32_t:1;\r
+ vuint32_t PFLIM:2;\r
+ vuint32_t BFEN:1;\r
+ } B;\r
+ } PFCRP1;\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : FlexCAN */\r
+/****************************************************************************/\r
+ struct FLEXCAN_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MDIS:1;\r
+ vuint32_t FRZ:1;\r
+ vuint32_t FEN:1;\r
+ vuint32_t HALT:1;\r
+ vuint32_t NOTRDY:1;\r
+ vuint32_t WAKMSK:1;\r
+ vuint32_t SOFTRST:1;\r
+ vuint32_t FRZACK:1;\r
+ vuint32_t SUPV:1;\r
+ vuint32_t SLFWAK:1;\r
+ vuint32_t WRNEN:1;\r
+ vuint32_t LPMACK:1;\r
+ vuint32_t WAKSRC:1;\r
+ vuint32_t DOZE:1;\r
+ vuint32_t SRXDIS:1;\r
+ vuint32_t BCC:1;\r
+ vuint32_t:2;\r
+ vuint32_t LPRIO_EN:1;\r
+ vuint32_t AEN:1;\r
+ vuint32_t:2;\r
+ vuint32_t IDAM:2;\r
+ vuint32_t:2;\r
+ vuint32_t MAXMB:6;\r
+ } B;\r
+ } MCR; /* Module Configuration Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PRESDIV:8;\r
+ vuint32_t RJW:2;\r
+ vuint32_t PSEG1:3;\r
+ vuint32_t PSEG2:3;\r
+ vuint32_t BOFFMSK:1;\r
+ vuint32_t ERRMSK:1;\r
+ vuint32_t CLKSRC:1;\r
+ vuint32_t LPB:1;\r
+ vuint32_t TWRNMSK:1;\r
+ vuint32_t RWRNMSK:1;\r
+ vuint32_t:2;\r
+ vuint32_t SMP:1;\r
+ vuint32_t BOFFREC:1;\r
+ vuint32_t TSYN:1;\r
+ vuint32_t LBUF:1;\r
+ vuint32_t LOM:1;\r
+ vuint32_t PROPSEG:3;\r
+ } B;\r
+ } CR; /* Control Register */\r
+ //} CTRL; /* Control Register */ /* JRichard */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } TIMER; /* Free Running Timer */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:21;\r
+ vuint32_t TRD:1;\r
+ vuint32_t BITCLS:1;\r
+ vuint32_t DSCACK:1;\r
+ vuint32_t:8;\r
+ } B;\r
+ } TCR; /* Test Configuration Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MI:32;\r
+ } B;\r
+ } RXGMASK; /* RX Global Mask */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MI:32;\r
+ } B;\r
+ } RX14MASK; /* RX 14 Mask */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MI:32;\r
+ } B;\r
+ } RX15MASK; /* RX 15 Mask */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t RXECNT:8;\r
+ vuint32_t TXECNT:8;\r
+ } B;\r
+ } ECR; /* Error Counter Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:14;\r
+ vuint32_t TWRNINT:1;\r
+ vuint32_t RWRNINT:1;\r
+ vuint32_t BIT1ERR:1;\r
+ vuint32_t BIT0ERR:1;\r
+ vuint32_t ACKERR:1;\r
+ vuint32_t CRCERR:1;\r
+ vuint32_t FRMERR:1;\r
+ vuint32_t STFERR:1;\r
+ vuint32_t TXWRN:1;\r
+ vuint32_t RXWRN:1;\r
+ vuint32_t IDLE:1;\r
+ vuint32_t TXRX:1;\r
+ vuint32_t FLTCONF:2;\r
+ vuint32_t:1;\r
+ vuint32_t BOFFINT:1;\r
+ vuint32_t ERRINT:1;\r
+ vuint32_t WAKINT:1;\r
+ } B;\r
+ } ESR; /* Error and Status Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BUF63M:1;\r
+ vuint32_t BUF62M:1;\r
+ vuint32_t BUF61M:1;\r
+ vuint32_t BUF60M:1;\r
+ vuint32_t BUF59M:1;\r
+ vuint32_t BUF58M:1;\r
+ vuint32_t BUF57M:1;\r
+ vuint32_t BUF56M:1;\r
+ vuint32_t BUF55M:1;\r
+ vuint32_t BUF54M:1;\r
+ vuint32_t BUF53M:1;\r
+ vuint32_t BUF52M:1;\r
+ vuint32_t BUF51M:1;\r
+ vuint32_t BUF50M:1;\r
+ vuint32_t BUF49M:1;\r
+ vuint32_t BUF48M:1;\r
+ vuint32_t BUF47M:1;\r
+ vuint32_t BUF46M:1;\r
+ vuint32_t BUF45M:1;\r
+ vuint32_t BUF44M:1;\r
+ vuint32_t BUF43M:1;\r
+ vuint32_t BUF42M:1;\r
+ vuint32_t BUF41M:1;\r
+ vuint32_t BUF40M:1;\r
+ vuint32_t BUF39M:1;\r
+ vuint32_t BUF38M:1;\r
+ vuint32_t BUF37M:1;\r
+ vuint32_t BUF36M:1;\r
+ vuint32_t BUF35M:1;\r
+ vuint32_t BUF34M:1;\r
+ vuint32_t BUF33M:1;\r
+ vuint32_t BUF32M:1;\r
+ } B;\r
+ } IMRH; /* Interruput Masks Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BUF31M:1;\r
+ vuint32_t BUF30M:1;\r
+ vuint32_t BUF29M:1;\r
+ vuint32_t BUF28M:1;\r
+ vuint32_t BUF27M:1;\r
+ vuint32_t BUF26M:1;\r
+ vuint32_t BUF25M:1;\r
+ vuint32_t BUF24M:1;\r
+ vuint32_t BUF23M:1;\r
+ vuint32_t BUF22M:1;\r
+ vuint32_t BUF21M:1;\r
+ vuint32_t BUF20M:1;\r
+ vuint32_t BUF19M:1;\r
+ vuint32_t BUF18M:1;\r
+ vuint32_t BUF17M:1;\r
+ vuint32_t BUF16M:1;\r
+ vuint32_t BUF15M:1;\r
+ vuint32_t BUF14M:1;\r
+ vuint32_t BUF13M:1;\r
+ vuint32_t BUF12M:1;\r
+ vuint32_t BUF11M:1;\r
+ vuint32_t BUF10M:1;\r
+ vuint32_t BUF9M:1;\r
+ vuint32_t BUF8M:1;\r
+ vuint32_t BUF7M:1;\r
+ vuint32_t BUF6M:1;\r
+ vuint32_t BUF5M:1;\r
+ vuint32_t BUF4M:1;\r
+ vuint32_t BUF3M:1;\r
+ vuint32_t BUF2M:1;\r
+ vuint32_t BUF1M:1;\r
+ vuint32_t BUF0M:1;\r
+ } B;\r
+ } IMRL; /* Interruput Masks Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BUF63I:1;\r
+ vuint32_t BUF62I:1;\r
+ vuint32_t BUF61I:1;\r
+ vuint32_t BUF60I:1;\r
+ vuint32_t BUF59I:1;\r
+ vuint32_t BUF58I:1;\r
+ vuint32_t BUF57I:1;\r
+ vuint32_t BUF56I:1;\r
+ vuint32_t BUF55I:1;\r
+ vuint32_t BUF54I:1;\r
+ vuint32_t BUF53I:1;\r
+ vuint32_t BUF52I:1;\r
+ vuint32_t BUF51I:1;\r
+ vuint32_t BUF50I:1;\r
+ vuint32_t BUF49I:1;\r
+ vuint32_t BUF48I:1;\r
+ vuint32_t BUF47I:1;\r
+ vuint32_t BUF46I:1;\r
+ vuint32_t BUF45I:1;\r
+ vuint32_t BUF44I:1;\r
+ vuint32_t BUF43I:1;\r
+ vuint32_t BUF42I:1;\r
+ vuint32_t BUF41I:1;\r
+ vuint32_t BUF40I:1;\r
+ vuint32_t BUF39I:1;\r
+ vuint32_t BUF38I:1;\r
+ vuint32_t BUF37I:1;\r
+ vuint32_t BUF36I:1;\r
+ vuint32_t BUF35I:1;\r
+ vuint32_t BUF34I:1;\r
+ vuint32_t BUF33I:1;\r
+ vuint32_t BUF32I:1;\r
+ } B;\r
+ } IFRH; /* Interruput Flag Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BUF31I:1;\r
+ vuint32_t BUF30I:1;\r
+ vuint32_t BUF29I:1;\r
+ vuint32_t BUF28I:1;\r
+ vuint32_t BUF27I:1;\r
+ vuint32_t BUF26I:1;\r
+ vuint32_t BUF25I:1;\r
+ vuint32_t BUF24I:1;\r
+ vuint32_t BUF23I:1;\r
+ vuint32_t BUF22I:1;\r
+ vuint32_t BUF21I:1;\r
+ vuint32_t BUF20I:1;\r
+ vuint32_t BUF19I:1;\r
+ vuint32_t BUF18I:1;\r
+ vuint32_t BUF17I:1;\r
+ vuint32_t BUF16I:1;\r
+ vuint32_t BUF15I:1;\r
+ vuint32_t BUF14I:1;\r
+ vuint32_t BUF13I:1;\r
+ vuint32_t BUF12I:1;\r
+ vuint32_t BUF11I:1;\r
+ vuint32_t BUF10I:1;\r
+ vuint32_t BUF09I:1;\r
+ vuint32_t BUF08I:1;\r
+ vuint32_t BUF07I:1;\r
+ vuint32_t BUF06I:1;\r
+ vuint32_t BUF05I:1;\r
+ vuint32_t BUF04I:1;\r
+ vuint32_t BUF03I:1;\r
+ vuint32_t BUF02I:1;\r
+ vuint32_t BUF01I:1;\r
+ vuint32_t BUF00I:1;\r
+/* vuint32_t BUF9I:1;\r
+ vuint32_t BUF8I:1;\r
+ vuint32_t BUF7I:1;\r
+ vuint32_t BUF6I:1;\r
+ vuint32_t BUF5I:1;\r
+ vuint32_t BUF4I:1;\r
+ vuint32_t BUF3I:1;\r
+ vuint32_t BUF2I:1;\r
+ vuint32_t BUF1I:1;\r
+ vuint32_t BUF0I:1; // JRichard changed per mpc5554.h BUF0-->BUF00 etc.\r
+*/ } B;\r
+ } IFRL; /* Interruput Flag Register */\r
+\r
+ uint32_t FLEXCAN_reserved2[19];\r
+\r
+ struct canbuf_t {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:4;\r
+ vuint32_t CODE:4;\r
+ vuint32_t:1;\r
+ vuint32_t SRR:1;\r
+ vuint32_t IDE:1;\r
+ vuint32_t RTR:1;\r
+ vuint32_t LENGTH:4;\r
+ vuint32_t TIMESTAMP:16;\r
+ } B;\r
+ } CS;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PRIO:3;\r
+ vuint32_t STD_ID:11;\r
+ vuint32_t EXT_ID:18;\r
+ } B;\r
+ } ID;\r
+\r
+ union {\r
+ //vuint8_t B[8]; /* Data buffer in Bytes (8 bits) */\r
+ //vuint16_t H[4]; /* Data buffer in Half-words (16 bits) */\r
+ vuint32_t W[2]; /* Data buffer in words (32 bits) */\r
+ //vuint32_t R[2]; /* Data buffer in words (32 bits) */\r
+ } DATA;\r
+\r
+ } BUF[64];\r
+ //} MB[64]; /* JRichard */\r
+\r
+ uint32_t FLEXCAN_reserved3[256];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MI:32;\r
+ } B;\r
+ } RXIMR[64]; /* RX Individual Mask Registers */\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : FMPLL */\r
+/****************************************************************************/\r
+ struct FMPLL_tag {\r
+ union { /* JRichard */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:1;\r
+ vuint32_t PREDIV:3;\r
+ vuint32_t MFD:5;\r
+ vuint32_t:1;\r
+ vuint32_t RFD:3;\r
+ vuint32_t LOCEN:1;\r
+ vuint32_t LOLRE:1;\r
+ vuint32_t LOCRE:1;\r
+ vuint32_t DISCLK:1;\r
+ vuint32_t LOLIRQ:1;\r
+ vuint32_t LOCIRQ:1;\r
+ vuint32_t RATE:1;\r
+ vuint32_t DEPTH:2;\r
+ vuint32_t EXP:10;\r
+ } B;\r
+ } SYNCR;\r
+ //int32_t FMPLL_reserved1; /* JRichard */\r
+\r
+ union { /* Synthesiser Status Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:22;\r
+ vuint32_t LOLF:1;\r
+ vuint32_t LOC:1;\r
+ vuint32_t MODE:1;\r
+ vuint32_t PLLSEL:1;\r
+ vuint32_t PLLREF:1;\r
+ vuint32_t LOCKS:1;\r
+ vuint32_t LOCK:1;\r
+ vuint32_t LOCF:1;\r
+ vuint32_t CALDONE:1;\r
+ vuint32_t CALPASS:1;\r
+ } B;\r
+ } SYNSR;\r
+ \r
+ \r
+ \r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t EMODE:1;\r
+ vuint32_t CLKCFG:3;\r
+ vuint32_t:8;\r
+ vuint32_t EPREDIV:4;\r
+ vuint32_t:8;\r
+ vuint32_t EMFD:8;\r
+ } B;\r
+ } ESYNCR1;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:8;\r
+ vuint32_t LOCEN:1;\r
+ vuint32_t LOLRE:1;\r
+ vuint32_t LOCRE:1;\r
+ vuint32_t LOLIRQ:1;\r
+ vuint32_t LOCIRQ:1;\r
+ vuint32_t:1;\r
+ vuint32_t ERATE:2;\r
+ vuint32_t:5;\r
+ vuint32_t EDEPTH:3;\r
+ vuint32_t:2;\r
+ vuint32_t ERFD:6;\r
+ } B;\r
+ } ESYNCR2;\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : i2c */\r
+/****************************************************************************/\r
+ struct I2C_tag {\r
+ union {\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t ADR:7;\r
+ vuint8_t:1;\r
+ } B;\r
+ } IBAD; /* Module Bus Address Register */\r
+\r
+ union {\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t IBC:8;\r
+ } B;\r
+ } IBFD; /* Module Bus Frequency Register */\r
+\r
+ union {\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t MDIS:1;\r
+ vuint8_t IBIE:1;\r
+ vuint8_t MS:1;\r
+ vuint8_t TX:1;\r
+ vuint8_t NOACK:1;\r
+ vuint8_t RSTA:1;\r
+ vuint8_t DMAEN:1;\r
+ vuint8_t IBDOZE:1;\r
+ } B;\r
+ } IBCR; /* Module Bus Control Register */\r
+\r
+ union {\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t TCF:1;\r
+ vuint8_t IAAS:1;\r
+ vuint8_t IBB:1;\r
+ vuint8_t IBAL:1;\r
+ vuint8_t:1;\r
+ vuint8_t SRW:1;\r
+ vuint8_t IBIF:1;\r
+ vuint8_t RXAK:1;\r
+ } B;\r
+ } IBSR; /* Module Status Register */\r
+\r
+ union {\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t DATA:8;\r
+ } B;\r
+ } IBDR; /* Module Data Register */\r
+\r
+ union {\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t BIIE:1;\r
+ vuint8_t:7;\r
+ } B;\r
+ } IBIC; /* Module Interrupt Configuration Register */\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : INTC */\r
+/****************************************************************************/\r
+ struct INTC_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:18;\r
+ vuint32_t VTES_PRC1:1;\r
+ vuint32_t:4;\r
+ vuint32_t HVEN_PRC1:1;\r
+ vuint32_t:2;\r
+ vuint32_t VTES_PRC0:1;\r
+ vuint32_t:4;\r
+ vuint32_t HVEN_PRC0:1;\r
+ } B;\r
+ } MCR; /* Module Configuration Register */\r
+\r
+ int32_t INTC_reserved1;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:28;\r
+ vuint32_t PRI:4;\r
+ } B;\r
+ } CPR_PRC0; /* Processor 0 Current Priority Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:28;\r
+ vuint32_t PRI:4;\r
+ } B;\r
+ } CPR_PRC1; /* Processor 1 Current Priority Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t VTBA_PRC0:21;\r
+ vuint32_t INTVEC_PRC0:9;\r
+ vuint32_t:2;\r
+ } B;\r
+ } IACKR_PRC0; /* Processor 0 Interrupt Acknowledge Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t VTBA_PRC1:21;\r
+ vuint32_t INTVEC_PRC1:9;\r
+ vuint32_t:2;\r
+ } B;\r
+ } IACKR_PRC1; /* Processor 1 Interrupt Acknowledge Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:32;\r
+ } B;\r
+ } EOIR_PRC0; /* Processor 0 End of Interrupt Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:32;\r
+ } B;\r
+ } EOIR_PRC1; /* Processor 1 End of Interrupt Register */\r
+\r
+ union {\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t:6;\r
+ vuint8_t SET:1;\r
+ vuint8_t CLR:1;\r
+ } B;\r
+ } SSCIR[8]; /* Software Set/Clear Interruput Register */\r
+\r
+ uint32_t intc_reserved2[6];\r
+\r
+ union {\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t PRC_SEL:2;\r
+ vuint8_t:2;\r
+ vuint8_t PRI:4;\r
+ } B;\r
+ } PSR[294]; /* Software Set/Clear Interrupt Register */\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : MCM */\r
+/****************************************************************************/\r
+ struct MCM_tag {\r
+\r
+ uint32_t mcm_reserved1[5];\r
+\r
+ uint16_t mcm_reserved2;\r
+\r
+ union {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t RO:1;\r
+ vuint16_t:6;\r
+ vuint16_t SWRWH:1;\r
+ vuint16_t SWE:1;\r
+ vuint16_t SWRI:2;\r
+ vuint16_t SWT:5;\r
+ } B;\r
+ } SWTCR; //Software Watchdog Timer Control\r
+\r
+ uint8_t mcm_reserved3[3];\r
+\r
+ union {\r
+ vuint8_t R;\r
+ } SWTSR; //SWT Service Register\r
+\r
+ uint8_t mcm_reserved4[3];\r
+\r
+ union {\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t:7;\r
+ vuint8_t SWTIC:1;\r
+ } B;\r
+ } SWTIR; //SWT Interrupt Register\r
+\r
+ uint32_t mcm_reserved5[1];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PRI:1;\r
+ vuint32_t:31;\r
+ } B;\r
+ } MUDCR; //Misc. User Defined Control Register\r
+\r
+ uint32_t mcm_reserved6[6];\r
+ uint8_t mcm_reserved7[3];\r
+\r
+ union {\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t:6;\r
+ vuint8_t ERNCR:1;\r
+ vuint8_t EFNCR:1;\r
+ } B;\r
+ } ECR; //ECC Configuration Register\r
+\r
+ uint8_t mcm_reserved8[3];\r
+\r
+ union {\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t:6;\r
+ vuint8_t RNCE:1;\r
+ vuint8_t FNCE:1;\r
+ } B;\r
+ } ESR; //ECC Status Register\r
+\r
+ uint16_t mcm_reserved9;\r
+\r
+ union {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:6;\r
+ vuint16_t FRCNCI:1;\r
+ vuint16_t FR1NCI:1;\r
+ vuint16_t:1;\r
+ vuint16_t ERRBIT:7;\r
+ } B;\r
+ } EEGR; //ECC Error Generation Register\r
+\r
+ uint32_t mcm_reserved10;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } FEAR; //Flash ECC Address Register\r
+\r
+ uint16_t mcm_reserved11;\r
+\r
+ union {\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t:4;\r
+ vuint8_t FEMR:4;\r
+ } B;\r
+ } FEMR; //Flash ECC Master Register\r
+\r
+ union {\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t WRITE:1;\r
+ vuint8_t SIZE:3;\r
+ vuint8_t PROTECTION:4;\r
+ } B;\r
+ } FEAT; //Flash ECC Attributes Register\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } FEDRH; //Flash ECC Data High Register\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } FEDRL; //Flash ECC Data Low Register\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t REAR:32;\r
+ } B;\r
+ } REAR; //RAM ECC Address\r
+\r
+ uint8_t mcm_reserved12;\r
+\r
+ union {\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t RESR:8;\r
+ } B;\r
+ } RESR; //RAM ECC Syndrome\r
+\r
+ union {\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t:4;\r
+ vuint8_t REMR:4;\r
+ } B;\r
+ } REMR; //RAM ECC Master\r
+\r
+ union {\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t WRITE:1;\r
+ vuint8_t SIZE:3;\r
+ vuint8_t PROTECTION:1;\r
+ } B;\r
+ } REAT; // RAM ECC Attributes Register\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } REDRH; //RAM ECC Data High Register\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } REDRL; //RAMECC Data Low Register\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : MPU */\r
+/****************************************************************************/\r
+ struct MPU_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MSTR:8;\r
+ vuint32_t:4;\r
+ vuint32_t HRL:4;\r
+ vuint32_t NSP:4;\r
+ vuint32_t NGRD:4;\r
+ vuint32_t:7;\r
+ vuint32_t VLD:1;\r
+ } B;\r
+ } CESR; /* Module Control/Error Status Register */\r
+\r
+ uint32_t mpu_reserved1[3];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t EADDR:32;\r
+ } B;\r
+ } EAR0;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t EACD:16;\r
+ vuint32_t EPID:8;\r
+ vuint32_t EMN:4;\r
+ vuint32_t EATTR:3;\r
+ vuint32_t ERW:1;\r
+ } B;\r
+ } EDR0;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t EADDR:32;\r
+ } B;\r
+ } EAR1;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t EACD:16;\r
+ vuint32_t EPID:8;\r
+ vuint32_t EMN:4;\r
+ vuint32_t EATTR:3;\r
+ vuint32_t ERW:1;\r
+ } B;\r
+ } EDR1;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t EADDR:32;\r
+ } B;\r
+ } EAR2;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t EACD:16;\r
+ vuint32_t EPID:8;\r
+ vuint32_t EMN:4;\r
+ vuint32_t EATTR:3;\r
+ vuint32_t ERW:1;\r
+ } B;\r
+ } EDR2;\r
+\r
+ uint32_t mpu_reserved2[246];\r
+\r
+ struct {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t SRTADDR:27;\r
+ vuint32_t:5;\r
+ } B;\r
+ } WORD0; /* Region Descriptor n Word 0 */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t ENDADDR:27;\r
+ vuint32_t:5;\r
+ } B;\r
+ } WORD1; /* Region Descriptor n Word 1 */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:6;\r
+ vuint32_t M4RE0:1;\r
+ vuint32_t M4WE:1;\r
+ vuint32_t M3PE:1;\r
+ vuint32_t M3SM:2;\r
+ vuint32_t M3UM:3;\r
+ vuint32_t M2PE:1;\r
+ vuint32_t M2SM:2;\r
+ vuint32_t M2UM:3;\r
+ vuint32_t M1PE:1;\r
+ vuint32_t M1SM:2;\r
+ vuint32_t M1UM:3;\r
+ vuint32_t M0PE:1;\r
+ vuint32_t M0SM:2;\r
+ vuint32_t M0UM:3;\r
+ } B;\r
+ } WORD2; /* Region Descriptor n Word 2 */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PID:8;\r
+ vuint32_t PIDMASK:8;\r
+ vuint32_t:15;\r
+ vuint32_t VLD:1;\r
+ } B;\r
+ } WORD3; /* Region Descriptor n Word 3 */\r
+\r
+ } RGD[16];\r
+\r
+ uint32_t mpu_reserved3[192];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:6;\r
+ vuint32_t M4RE:1;\r
+ vuint32_t M4WE:1;\r
+ vuint32_t M3PE:1;\r
+ vuint32_t M3SM:2;\r
+ vuint32_t M3UM:3;\r
+ vuint32_t M2PE:1;\r
+ vuint32_t M2SM:2;\r
+ vuint32_t M2UM:3;\r
+ vuint32_t M1PE:1;\r
+ vuint32_t M1SM:2;\r
+ vuint32_t M1UM:3;\r
+ vuint32_t M0PE:1;\r
+ vuint32_t M0SM:2;\r
+ vuint32_t M0UM:3;\r
+ } B;\r
+ } RGDAAC[16]; /* Region Descriptor Alternate Access Control n */\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : pit */\r
+/****************************************************************************/\r
+ struct PIT_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:8;\r
+ vuint32_t TSV:24;\r
+ } B;\r
+ } TLVAL0;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TSV:32;\r
+ } B;\r
+ } TLVAL1;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TSV:32;\r
+ } B;\r
+ } TLVAL2;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TSV:32;\r
+ } B;\r
+ } TLVAL3;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TSV:32;\r
+ } B;\r
+ } TLVAL4;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TSV:32;\r
+ } B;\r
+ } TLVAL5;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TSV:32;\r
+ } B;\r
+ } TLVAL6;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TSV:32;\r
+ } B;\r
+ } TLVAL7;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TSV:32;\r
+ } B;\r
+ } TLVAL8;\r
+\r
+ uint32_t pit_reserved1[23];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:8;\r
+ vuint32_t TVL:24;\r
+ } B;\r
+ } TVAL0;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TVL:32;\r
+ } B;\r
+ } TVAL1;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TVL:32;\r
+ } B;\r
+ } TVAL2;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TVL:32;\r
+ } B;\r
+ } TVAL3;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TVL:32;\r
+ } B;\r
+ } TVAL4;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TVL:32;\r
+ } B;\r
+ } TVAL5;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TVL:32;\r
+ } B;\r
+ } TVAL6;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TVL:32;\r
+ } B;\r
+ } TVAL7;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TVL:32;\r
+ } B;\r
+ } TVAL8;\r
+\r
+ uint32_t pit_reserved2[23];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:27;\r
+ vuint32_t TIF4:1;\r
+ vuint32_t TIF3:1;\r
+ vuint32_t TIF2:1;\r
+ vuint32_t TIF1:1;\r
+ vuint32_t RTIF:1;\r
+ } B;\r
+ } FLG;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:27;\r
+ vuint32_t TIE4:1;\r
+ vuint32_t TIE3:1;\r
+ vuint32_t TIE2:1;\r
+ vuint32_t TIE1:1;\r
+ vuint32_t RTIE:1;\r
+ } B;\r
+ } INTEN;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:27;\r
+ vuint32_t ISEL4:1;\r
+ vuint32_t ISEL3:1;\r
+ vuint32_t ISEL2:1;\r
+ vuint32_t ISEL1:1;\r
+ vuint32_t:1;\r
+ } B;\r
+ } INTSEL;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:21;\r
+ vuint32_t PEN10:1;\r
+ vuint32_t PEN9:1;\r
+ vuint32_t PEN8:1;\r
+ vuint32_t PEN7:1;\r
+ vuint32_t PEN6:1;\r
+ vuint32_t PEN5:1;\r
+ vuint32_t PEN4:1;\r
+ vuint32_t PEN3:1;\r
+ vuint32_t PEN2:1;\r
+ vuint32_t PEN1:1;\r
+ vuint32_t PEN0:1;\r
+ } B;\r
+ } EN;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:6;\r
+ vuint32_t DOZE:1;\r
+ vuint32_t MDIS:1;\r
+ vuint32_t:24;\r
+ } B;\r
+ } CTRL;\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : sem4 */\r
+/****************************************************************************/\r
+ struct SEMA4_tag {\r
+ union {\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t:6;\r
+ vuint8_t GTFSM:2;\r
+ } B;\r
+ } GATE[16]; /* Gate n Register */\r
+\r
+ uint32_t sema4_reserved1[12];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t INE0:1;\r
+ vuint32_t INE1:1;\r
+ vuint32_t INE2:1;\r
+ vuint32_t INE3:1;\r
+ vuint32_t INE4:1;\r
+ vuint32_t INE5:1;\r
+ vuint32_t INE6:1;\r
+ vuint32_t INE7:1;\r
+ vuint32_t INE8:1;\r
+ vuint32_t INE9:1;\r
+ vuint32_t INE10:1;\r
+ vuint32_t INE11:1;\r
+ vuint32_t INE12:1;\r
+ vuint32_t INE13:1;\r
+ vuint32_t INE14:1;\r
+ vuint32_t INE15:1;\r
+ vuint32_t:16;\r
+ } B;\r
+ } CP0INE;\r
+\r
+ uint32_t sema4_reserved2[1];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t INE0:1;\r
+ vuint32_t INE1:1;\r
+ vuint32_t INE2:1;\r
+ vuint32_t INE3:1;\r
+ vuint32_t INE4:1;\r
+ vuint32_t INE5:1;\r
+ vuint32_t INE6:1;\r
+ vuint32_t INE7:1;\r
+ vuint32_t INE8:1;\r
+ vuint32_t INE9:1;\r
+ vuint32_t INE10:1;\r
+ vuint32_t INE11:1;\r
+ vuint32_t INE12:1;\r
+ vuint32_t INE13:1;\r
+ vuint32_t INE14:1;\r
+ vuint32_t INE15:1;\r
+ vuint32_t:16;\r
+ } B;\r
+ } CP1INE;\r
+\r
+ uint32_t sema4_reserved3[13];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t GN0:1;\r
+ vuint32_t GN1:1;\r
+ vuint32_t GN2:1;\r
+ vuint32_t GN3:1;\r
+ vuint32_t GN4:1;\r
+ vuint32_t GN5:1;\r
+ vuint32_t GN6:1;\r
+ vuint32_t GN7:1;\r
+ vuint32_t GN8:1;\r
+ vuint32_t GN9:1;\r
+ vuint32_t GN10:1;\r
+ vuint32_t GN11:1;\r
+ vuint32_t GN12:1;\r
+ vuint32_t GN13:1;\r
+ vuint32_t GN14:1;\r
+ vuint32_t GN15:1;\r
+ vuint32_t:16;\r
+ } B;\r
+ } CP0NTF;\r
+\r
+ uint32_t sema4_reserved4[1];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t GN0:1;\r
+ vuint32_t GN1:1;\r
+ vuint32_t GN2:1;\r
+ vuint32_t GN3:1;\r
+ vuint32_t GN4:1;\r
+ vuint32_t GN5:1;\r
+ vuint32_t GN6:1;\r
+ vuint32_t GN7:1;\r
+ vuint32_t GN8:1;\r
+ vuint32_t GN9:1;\r
+ vuint32_t GN10:1;\r
+ vuint32_t GN11:1;\r
+ vuint32_t GN12:1;\r
+ vuint32_t GN13:1;\r
+ vuint32_t GN14:1;\r
+ vuint32_t GN15:1;\r
+ vuint32_t:16;\r
+ } B;\r
+ } CP1NTF;\r
+\r
+ uint32_t sema4_reserved5[29];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:2;\r
+ vuint32_t RSTGSM:2;\r
+ vuint32_t:1;\r
+ vuint32_t RSTGMS:3;\r
+ vuint32_t RSTGTN:8;\r
+ vuint32_t:16;\r
+ } B;\r
+ } RSTGT;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:2;\r
+ vuint32_t RSTNSM:2;\r
+ vuint32_t:1;\r
+ vuint32_t RSTNMS:3;\r
+ vuint32_t RSTNTN:8;\r
+ vuint32_t:16;\r
+ } B;\r
+ } RSTNTF;\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : SIU */\r
+/****************************************************************************/\r
+ struct SIU_tag {\r
+ int32_t SIU_reserved0;\r
+\r
+ union { /* MCU ID Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PARTNUM:16;\r
+ vuint32_t PKG:4;\r
+ //vuint32_t MASKNUM:16;\r
+ vuint32_t MASKNUM:12;\r
+ } B;\r
+ } MIDR;\r
+\r
+ int32_t SIU_reserved1;\r
+\r
+ union { /* Reset Status Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PORS:1;\r
+ vuint32_t ERS:1;\r
+ vuint32_t LLRS:1;\r
+ vuint32_t LCRS:1;\r
+ vuint32_t WDRS:1;\r
+ vuint32_t CRS0:1;\r
+ vuint32_t CRS1:1;\r
+ vuint32_t:7;\r
+ vuint32_t SSRS:1;\r
+ vuint32_t:14;\r
+ vuint32_t BOOTCFG:2;\r
+ vuint32_t:1;\r
+ } B;\r
+ } RSR;\r
+\r
+ union { /* System Reset Control Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t SSR:1;\r
+ vuint32_t:15;\r
+ vuint32_t CRE0:1;\r
+ vuint32_t CRE1:1;\r
+ vuint32_t:6;\r
+ vuint32_t SSRL:1;\r
+ vuint32_t:7;\r
+ } B;\r
+ } SRCR;\r
+\r
+ union { /* External Interrupt Status Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t NMI0:1;\r
+ vuint32_t NMI1:1;\r
+ vuint32_t:14;\r
+ vuint32_t EIF15:1;\r
+ vuint32_t EIF14:1;\r
+ vuint32_t EIF13:1;\r
+ vuint32_t EIF12:1;\r
+ vuint32_t EIF11:1;\r
+ vuint32_t EIF10:1;\r
+ vuint32_t EIF9:1;\r
+ vuint32_t EIF8:1;\r
+ vuint32_t EIF7:1;\r
+ vuint32_t EIF6:1;\r
+ vuint32_t EIF5:1;\r
+ vuint32_t EIF4:1;\r
+ vuint32_t EIF3:1;\r
+ vuint32_t EIF2:1;\r
+ vuint32_t EIF1:1;\r
+ vuint32_t EIF0:1;\r
+ } B;\r
+ } EISR;\r
+\r
+ union { /* DMA/Interrupt Request Enable Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t NRE0:1;\r
+ vuint32_t NRE1:1;\r
+ vuint32_t:14;\r
+ vuint32_t EIRE15:1;\r
+ vuint32_t EIRE14:1;\r
+ vuint32_t EIRE13:1;\r
+ vuint32_t EIRE12:1;\r
+ vuint32_t EIRE11:1;\r
+ vuint32_t EIRE10:1;\r
+ vuint32_t EIRE9:1;\r
+ vuint32_t EIRE8:1;\r
+ vuint32_t EIRE7:1;\r
+ vuint32_t EIRE6:1;\r
+ vuint32_t EIRE5:1;\r
+ vuint32_t EIRE4:1;\r
+ vuint32_t EIRE3:1;\r
+ vuint32_t EIRE2:1;\r
+ vuint32_t EIRE1:1;\r
+ vuint32_t EIRE0:1;\r
+ } B;\r
+ } DIRER;\r
+\r
+ union { /* DMA/Interrupt Select Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:28;\r
+ vuint32_t DIRS3:1;\r
+ vuint32_t DIRS2:1;\r
+ vuint32_t DIRS1:1;\r
+ vuint32_t DIRS0:1;\r
+ } B;\r
+ } DIRSR;\r
+\r
+ union { /* Overrun Status Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t OVF15:1;\r
+ vuint32_t OVF14:1;\r
+ vuint32_t OVF13:1;\r
+ vuint32_t OVF12:1;\r
+ vuint32_t OVF11:1;\r
+ vuint32_t OVF10:1;\r
+ vuint32_t OVF9:1;\r
+ vuint32_t OVF8:1;\r
+ vuint32_t OVF7:1;\r
+ vuint32_t OVF6:1;\r
+ vuint32_t OVF5:1;\r
+ vuint32_t OVF4:1;\r
+ vuint32_t OVF3:1;\r
+ vuint32_t OVF2:1;\r
+ vuint32_t OVF1:1;\r
+ vuint32_t OVF0:1;\r
+ } B;\r
+ } OSR;\r
+\r
+ union { /* Overrun Request Enable Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t ORE15:1;\r
+ vuint32_t ORE14:1;\r
+ vuint32_t ORE13:1;\r
+ vuint32_t ORE12:1;\r
+ vuint32_t ORE11:1;\r
+ vuint32_t ORE10:1;\r
+ vuint32_t ORE9:1;\r
+ vuint32_t ORE8:1;\r
+ vuint32_t ORE7:1;\r
+ vuint32_t ORE6:1;\r
+ vuint32_t ORE5:1;\r
+ vuint32_t ORE4:1;\r
+ vuint32_t ORE3:1;\r
+ vuint32_t ORE2:1;\r
+ vuint32_t ORE1:1;\r
+ vuint32_t ORE0:1;\r
+ } B;\r
+ } ORER;\r
+\r
+ union { /* External IRQ Rising-Edge Event Enable Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t NREE0:1;\r
+ vuint32_t NREE1:1;\r
+ vuint32_t:14;\r
+ vuint32_t IREE15:1;\r
+ vuint32_t IREE14:1;\r
+ vuint32_t IREE13:1;\r
+ vuint32_t IREE12:1;\r
+ vuint32_t IREE11:1;\r
+ vuint32_t IREE10:1;\r
+ vuint32_t IREE9:1;\r
+ vuint32_t IREE8:1;\r
+ vuint32_t IREE7:1;\r
+ vuint32_t IREE6:1;\r
+ vuint32_t IREE5:1;\r
+ vuint32_t IREE4:1;\r
+ vuint32_t IREE3:1;\r
+ vuint32_t IREE2:1;\r
+ vuint32_t IREE1:1;\r
+ vuint32_t IREE0:1;\r
+ } B;\r
+ } IREER;\r
+\r
+ union { /* External IRQ Falling-Edge Event Enable Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t NFEE0:1;\r
+ vuint32_t NFEE1:1;\r
+ vuint32_t:14;\r
+ vuint32_t IFEE15:1;\r
+ vuint32_t IFEE14:1;\r
+ vuint32_t IFEE13:1;\r
+ vuint32_t IFEE12:1;\r
+ vuint32_t IFEE11:1;\r
+ vuint32_t IFEE10:1;\r
+ vuint32_t IFEE9:1;\r
+ vuint32_t IFEE8:1;\r
+ vuint32_t IFEE7:1;\r
+ vuint32_t IFEE6:1;\r
+ vuint32_t IFEE5:1;\r
+ vuint32_t IFEE4:1;\r
+ vuint32_t IFEE3:1;\r
+ vuint32_t IFEE2:1;\r
+ vuint32_t IFEE1:1;\r
+ vuint32_t IFEE0:1;\r
+ } B;\r
+ } IFEER;\r
+\r
+ union { /* External IRQ Digital Filter Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:28;\r
+ vuint32_t DFL:4;\r
+ } B;\r
+ } IDFR;\r
+\r
+ union { /* External IRQ Filtered Input Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t FI15:1;\r
+ vuint32_t FI14:1;\r
+ vuint32_t FI13:1;\r
+ vuint32_t FI12:1;\r
+ vuint32_t FI11:1;\r
+ vuint32_t FI10:1;\r
+ vuint32_t FI9:1;\r
+ vuint32_t FI8:1;\r
+ vuint32_t FI7:1;\r
+ vuint32_t FI6:1;\r
+ vuint32_t FI5:1;\r
+ vuint32_t FI4:1;\r
+ vuint32_t FI3:1;\r
+ vuint32_t FI2:1;\r
+ vuint32_t FI1:1;\r
+ vuint32_t FI0:1;\r
+ } B;\r
+ } IFIR;\r
+\r
+ int32_t SIU_reserved2;\r
+ int32_t SIU_reserved11;\r
+\r
+ union { /* Pad Configuration Registers */\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:4;\r
+ vuint16_t PA:2;\r
+ vuint16_t OBE:1;\r
+ vuint16_t IBE:1;\r
+ vuint16_t:2;\r
+ vuint16_t ODE:1;\r
+ vuint16_t HYS:1;\r
+ vuint16_t SEC:2;\r
+ vuint16_t WPE:1;\r
+ vuint16_t WPS:1;\r
+ } B;\r
+ } PCR[146];\r
+\r
+ int32_t SIU_reserved3[295];\r
+\r
+ union { /* GPIO Pin Data Output Registers */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t:7;\r
+ vuint8_t PDO:1;\r
+ } B;\r
+ } GPDO[146];\r
+\r
+ int32_t SIU_reserved4[91];\r
+\r
+ union { /* GPIO Pin Data Input Registers */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t:7;\r
+ vuint8_t PDI:1;\r
+ } B;\r
+ } GPDI[146];\r
+\r
+ int32_t SIU_reserved5[27];\r
+\r
+ union { /* IMUX Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TSEL3:2;\r
+ vuint32_t TSEL2:2;\r
+ vuint32_t TSEL1:2;\r
+ vuint32_t TSEL0:2;\r
+ vuint32_t:24;\r
+ } B;\r
+ } ISEL0;\r
+\r
+ union { /* IMUX Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t ESEL15:2;\r
+ vuint32_t ESEL14:2;\r
+ vuint32_t ESEL13:2;\r
+ vuint32_t ESEL12:2;\r
+ vuint32_t ESEL11:2;\r
+ vuint32_t ESEL10:2;\r
+ vuint32_t ESEL9:2;\r
+ vuint32_t ESEL8:2;\r
+ vuint32_t ESEL7:2;\r
+ vuint32_t ESEL6:2;\r
+ vuint32_t ESEL5:2;\r
+ vuint32_t ESEL4:2;\r
+ vuint32_t ESEL3:2;\r
+ vuint32_t ESEL2:2;\r
+ vuint32_t ESEL1:2;\r
+ vuint32_t ESEL0:2;\r
+ } B;\r
+ } ISEL1;\r
+\r
+ union { /* IMUX Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t SELEMIOS15:2;\r
+ vuint32_t SELEMIOS14:2;\r
+ vuint32_t SELEMIOS13:2;\r
+ vuint32_t SELEMIOS12:2;\r
+ vuint32_t SELEMIOS11:2;\r
+ vuint32_t SELEMIOS10:2;\r
+ vuint32_t SELEMIOS9:2;\r
+ vuint32_t SELEMIOS8:2;\r
+ vuint32_t SELEMIOS7:2;\r
+ vuint32_t SELEMIOS6:2;\r
+ vuint32_t SELEMIOS5:2;\r
+ vuint32_t SELEMIOS4:2;\r
+ vuint32_t SELEMIOS3:2;\r
+ vuint32_t SELEMIOS2:2;\r
+ vuint32_t SELEMIOS1:2;\r
+ vuint32_t SELEMIOS0:2;\r
+ } B;\r
+ } ISEL2;\r
+\r
+ int32_t SIU_reserved6[29];\r
+\r
+ union { /* Chip Configuration Register Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:14;\r
+ vuint32_t MATCH:1;\r
+ vuint32_t DISNEX:1;\r
+ vuint32_t:16;\r
+ } B;\r
+ } CCR;\r
+\r
+ union { /* External Clock Configuration Register Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:30;\r
+ vuint32_t EBDF:2;\r
+ } B;\r
+ } ECCR;\r
+\r
+ union { /* Compare A High Register */\r
+ vuint32_t R;\r
+ } CMPAH;\r
+\r
+ union { /* Compare A Low Register */\r
+ vuint32_t R;\r
+ } CMPAL;\r
+\r
+ union { /* Compare B High Register */\r
+ vuint32_t R;\r
+ } CMPBH;\r
+\r
+ union { /* Compare B Low Register */\r
+ vuint32_t R;\r
+ } CMPBL;\r
+\r
+ int32_t SIU_reserved7[2];\r
+\r
+ union { /* System CLock Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t SYSCLKSEL:2;\r
+ vuint32_t SYSCLKDIV:2;\r
+ vuint32_t SWTCLKSEL:1;\r
+ vuint32_t:11;\r
+ vuint32_t LPCLKDIV7:2;\r
+ vuint32_t LPCLKDIV6:2;\r
+ vuint32_t LPCLKDIV5:2;\r
+ vuint32_t LPCLKDIV4:2;\r
+ vuint32_t LPCLKDIV3:2;\r
+ vuint32_t LPCLKDIV2:2;\r
+ vuint32_t LPCLKDIV1:2;\r
+ vuint32_t LPCLKDIV0:2;\r
+ } B;\r
+ } SYSCLK;\r
+\r
+ union { /* Halt Register */\r
+ vuint32_t R;\r
+ } HLT;\r
+\r
+ union { /* Halt Acknowledge Register */\r
+ vuint32_t R;\r
+ } HLTACK;\r
+\r
+ int32_t SIU_reserved8[149];\r
+\r
+ union { /* Parallel GPIO Pin Data Output Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PA:16;\r
+ vuint32_t PB:16;\r
+ } B;\r
+ } PGPDO0;\r
+\r
+ union { /* Parallel GPIO Pin Data Output Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PC:16;\r
+ vuint32_t PD:16;\r
+ } B;\r
+ } PGPDO1;\r
+\r
+ union { /* Parallel GPIO Pin Data Output Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PE:16;\r
+ vuint32_t PF:16;\r
+ } B;\r
+ } PGPDO2;\r
+\r
+ union { /* Parallel GPIO Pin Data Output Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PG:16;\r
+ vuint32_t PH:16;\r
+ } B;\r
+ } PGPDO3;\r
+\r
+ union { /* Parallel GPIO Pin Data Output Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PJ:16;\r
+ vuint32_t PK:2;\r
+ vuint32_t:14;\r
+ } B;\r
+ } PGPDO4;\r
+\r
+ int32_t SIU_reserved9[11];\r
+\r
+ union { /* Parallel GPIO Pin Data Input Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PA:16;\r
+ vuint32_t PB:16;\r
+ } B;\r
+ } PGPDI0;\r
+\r
+ union { /* Parallel GPIO Pin Data Input Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PC:16;\r
+ vuint32_t PD:16;\r
+ } B;\r
+ } PGPDI1;\r
+\r
+ union { /* Parallel GPIO Pin Data Input Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PE:16;\r
+ vuint32_t PF:16;\r
+ } B;\r
+ } PGPDI2;\r
+\r
+ union { /* Parallel GPIO Pin Data Input Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PG:16;\r
+ vuint32_t PH:16;\r
+ } B;\r
+ } PGPDI3;\r
+\r
+ union { /* Parallel GPIO Pin Data Input Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PJ:16;\r
+ vuint32_t PK:2;\r
+ vuint32_t:14;\r
+ } B;\r
+ } PGPDI4;\r
+\r
+ int32_t SIU_reserved10[11];\r
+\r
+ union { /* Masked Parallel GPIO Pin Data Input Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PA_MASK:16;\r
+ vuint32_t PA:16;\r
+ } B;\r
+ } MPGPDO0;\r
+\r
+ union { /* Masked Parallel GPIO Pin Data Input Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PB_MASK:16;\r
+ vuint32_t PB:16;\r
+ } B;\r
+ } MPGPDO1;\r
+\r
+ union { /* Masked Parallel GPIO Pin Data Input Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PC_MASK:16;\r
+ vuint32_t PC:16;\r
+ } B;\r
+ } MPGPDO2;\r
+\r
+ union { /* Masked Parallel GPIO Pin Data Input Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PD_MASK:16;\r
+ vuint32_t PD:16;\r
+ } B;\r
+ } MPGPDO3;\r
+\r
+ union { /* Masked Parallel GPIO Pin Data Input Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PE_MASK:16;\r
+ vuint32_t PE:16;\r
+ } B;\r
+ } MPGPDO4;\r
+\r
+ union { /* Masked Parallel GPIO Pin Data Input Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PF_MASK:16;\r
+ vuint32_t PF:16;\r
+ } B;\r
+ } MPGPDO5;\r
+\r
+ union { /* Masked Parallel GPIO Pin Data Input Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PG_MASK:16;\r
+ vuint32_t PG:16;\r
+ } B;\r
+ } MPGPDO6;\r
+\r
+ union { /* Masked Parallel GPIO Pin Data Input Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PH_MASK:16;\r
+ vuint32_t PH:16;\r
+ } B;\r
+ } MPGPDO7;\r
+\r
+ union { /* Masked Parallel GPIO Pin Data Input Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PJ_MASK:16;\r
+ vuint32_t PJ:16;\r
+ } B;\r
+ } MPGPDO8;\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : FlexRay */\r
+/****************************************************************************/\r
+\r
+ typedef union uMVR {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t CHIVER:8; /* CHI Version Number */\r
+ vuint16_t PEVER:8; /* PE Version Number */\r
+ } B;\r
+ } MVR_t;\r
+\r
+ typedef union uMCR {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t MEN:1; /* module enable */\r
+ vuint16_t:1;\r
+ vuint16_t SCMD:1; /* single channel mode */\r
+ vuint16_t CHB:1; /* channel B enable */\r
+ vuint16_t CHA:1; /* channel A enable */\r
+ vuint16_t SFFE:1; /* synchronization frame filter enable */\r
+ vuint16_t:5;\r
+ vuint16_t CLKSEL:1; /* protocol engine clock source select */\r
+ vuint16_t PRESCALE:3; /* protocol engine clock prescaler */\r
+ vuint16_t:1;\r
+ } B;\r
+ } MCR_t;\r
+ typedef union uSTBSCR {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t WMD:1; /* write mode */\r
+ vuint16_t STBSSEL:7; /* strobe signal select */\r
+ vuint16_t:3;\r
+ vuint16_t ENB:1; /* strobe signal enable */\r
+ vuint16_t:2;\r
+ vuint16_t STBPSEL:2; /* strobe port select */\r
+ } B;\r
+ } STBSCR_t;\r
+ typedef union uSTBPCR {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:12;\r
+ vuint16_t STB3EN:1; /* strobe port enable */\r
+ vuint16_t STB2EN:1; /* strobe port enable */\r
+ vuint16_t STB1EN:1; /* strobe port enable */\r
+ vuint16_t STB0EN:1; /* strobe port enable */\r
+ } B;\r
+ } STBPCR_t;\r
+\r
+ typedef union uMBDSR {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:1;\r
+ vuint16_t MBSEG2DS:7; /* message buffer segment 2 data size */\r
+ vuint16_t:1;\r
+ vuint16_t MBSEG1DS:7; /* message buffer segment 1 data size */\r
+ } B;\r
+ } MBDSR_t;\r
+\r
+ typedef union uMBSSUTR {\r
+ vuint16_t R;\r
+ struct {\r
+\r
+ vuint16_t:2;\r
+ vuint16_t LAST_MB_SEG1:6; /* last message buffer control register for message buffer segment 1 */\r
+ vuint16_t:2;\r
+ vuint16_t LAST_MB_UTIL:6; /* last message buffer utilized */\r
+ } B;\r
+ } MBSSUTR_t;\r
+\r
+ typedef union uPOCR {\r
+ vuint16_t R;\r
+ vuint8_t byte[2];\r
+ struct {\r
+ vuint16_t WME:1; /* write mode external correction command */\r
+ vuint16_t:3;\r
+ vuint16_t EOC_AP:2; /* external offset correction application */\r
+ vuint16_t ERC_AP:2; /* external rate correction application */\r
+ vuint16_t BSY:1; /* command write busy / write mode command */\r
+ vuint16_t:3;\r
+ vuint16_t POCCMD:4; /* protocol command */\r
+ } B;\r
+ } POCR_t;\r
+/* protocol commands */\r
+ typedef union uGIFER {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t MIF:1; /* module interrupt flag */\r
+ vuint16_t PRIF:1; /* protocol interrupt flag */\r
+ vuint16_t CHIF:1; /* CHI interrupt flag */\r
+ vuint16_t WKUPIF:1; /* wakeup interrupt flag */\r
+ vuint16_t FNEBIF:1; /* receive FIFO channel B not empty interrupt flag */\r
+ vuint16_t FNEAIF:1; /* receive FIFO channel A not empty interrupt flag */\r
+ vuint16_t RBIF:1; /* receive message buffer interrupt flag */\r
+ vuint16_t TBIF:1; /* transmit buffer interrupt flag */\r
+ vuint16_t MIE:1; /* module interrupt enable */\r
+ vuint16_t PRIE:1; /* protocol interrupt enable */\r
+ vuint16_t CHIE:1; /* CHI interrupt enable */\r
+ vuint16_t WKUPIE:1; /* wakeup interrupt enable */\r
+ vuint16_t FNEBIE:1; /* receive FIFO channel B not empty interrupt enable */\r
+ vuint16_t FNEAIE:1; /* receive FIFO channel A not empty interrupt enable */\r
+ vuint16_t RBIE:1; /* receive message buffer interrupt enable */\r
+ vuint16_t TBIE:1; /* transmit buffer interrupt enable */\r
+ } B;\r
+ } GIFER_t;\r
+ typedef union uPIFR0 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t FATLIF:1; /* fatal protocol error interrupt flag */\r
+ vuint16_t INTLIF:1; /* internal protocol error interrupt flag */\r
+ vuint16_t ILCFIF:1; /* illegal protocol configuration flag */\r
+ vuint16_t CSAIF:1; /* cold start abort interrupt flag */\r
+ vuint16_t MRCIF:1; /* missing rate correctio interrupt flag */\r
+ vuint16_t MOCIF:1; /* missing offset correctio interrupt flag */\r
+ vuint16_t CCLIF:1; /* clock correction limit reached interrupt flag */\r
+ vuint16_t MXSIF:1; /* max sync frames detected interrupt flag */\r
+ vuint16_t MTXIF:1; /* media access test symbol received flag */\r
+ vuint16_t LTXBIF:1; /* pdLatestTx violation on channel B interrupt flag */\r
+ vuint16_t LTXAIF:1; /* pdLatestTx violation on channel A interrupt flag */\r
+ vuint16_t TBVBIF:1; /* Transmission across boundary on channel B Interrupt Flag */\r
+ vuint16_t TBVAIF:1; /* Transmission across boundary on channel A Interrupt Flag */\r
+ vuint16_t TI2IF:1; /* timer 2 expired interrupt flag */\r
+ vuint16_t TI1IF:1; /* timer 1 expired interrupt flag */\r
+ vuint16_t CYSIF:1; /* cycle start interrupt flag */\r
+ } B;\r
+ } PIFR0_t;\r
+ typedef union uPIFR1 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t EMCIF:1; /* error mode changed interrupt flag */\r
+ vuint16_t IPCIF:1; /* illegal protocol command interrupt flag */\r
+ vuint16_t PECFIF:1; /* protocol engine communication failure interrupt flag */\r
+ vuint16_t PSCIF:1; /* Protocol State Changed Interrupt Flag */\r
+ vuint16_t SSI3IF:1; /* slot status counter incremented interrupt flag */\r
+ vuint16_t SSI2IF:1; /* slot status counter incremented interrupt flag */\r
+ vuint16_t SSI1IF:1; /* slot status counter incremented interrupt flag */\r
+ vuint16_t SSI0IF:1; /* slot status counter incremented interrupt flag */\r
+ vuint16_t:2;\r
+ vuint16_t EVTIF:1; /* even cycle table written interrupt flag */\r
+ vuint16_t ODTIF:1; /* odd cycle table written interrupt flag */\r
+ vuint16_t:4;\r
+ } B;\r
+ } PIFR1_t;\r
+ typedef union uPIER0 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t FATLIE:1; /* fatal protocol error interrupt enable */\r
+ vuint16_t INTLIE:1; /* internal protocol error interrupt interrupt enable */\r
+ vuint16_t ILCFIE:1; /* illegal protocol configuration interrupt enable */\r
+ vuint16_t CSAIE:1; /* cold start abort interrupt enable */\r
+ vuint16_t MRCIE:1; /* missing rate correctio interrupt enable */\r
+ vuint16_t MOCIE:1; /* missing offset correctio interrupt enable */\r
+ vuint16_t CCLIE:1; /* clock correction limit reached interrupt enable */\r
+ vuint16_t MXSIE:1; /* max sync frames detected interrupt enable */\r
+ vuint16_t MTXIE:1; /* media access test symbol received interrupt enable */\r
+ vuint16_t LTXBIE:1; /* pdLatestTx violation on channel B interrupt enable */\r
+ vuint16_t LTXAIE:1; /* pdLatestTx violation on channel A interrupt enable */\r
+ vuint16_t TBVBIE:1; /* Transmission across boundary on channel B Interrupt enable */\r
+ vuint16_t TBVAIE:1; /* Transmission across boundary on channel A Interrupt enable */\r
+ vuint16_t TI2IE:1; /* timer 2 expired interrupt enable */\r
+ vuint16_t TI1IE:1; /* timer 1 expired interrupt enable */\r
+ vuint16_t CYSIE:1; /* cycle start interrupt enable */\r
+ } B;\r
+ } PIER0_t;\r
+ typedef union uPIER1 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t EMCIE:1; /* error mode changed interrupt enable */\r
+ vuint16_t IPCIE:1; /* illegal protocol command interrupt enable */\r
+ vuint16_t PECFIE:1; /* protocol engine communication failure interrupt enable */\r
+ vuint16_t PSCIE:1; /* Protocol State Changed Interrupt enable */\r
+ vuint16_t SSI3IE:1; /* slot status counter incremented interrupt enable */\r
+ vuint16_t SSI2IE:1; /* slot status counter incremented interrupt enable */\r
+ vuint16_t SSI1IE:1; /* slot status counter incremented interrupt enable */\r
+ vuint16_t SSI0IE:1; /* slot status counter incremented interrupt enable */\r
+ vuint16_t:2;\r
+ vuint16_t EVTIE:1; /* even cycle table written interrupt enable */\r
+ vuint16_t ODTIE:1; /* odd cycle table written interrupt enable */\r
+ vuint16_t:4;\r
+ } B;\r
+ } PIER1_t;\r
+ typedef union uCHIERFR {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t FRLBEF:1; /* flame lost channel B error flag */\r
+ vuint16_t FRLAEF:1; /* frame lost channel A error flag */\r
+ vuint16_t PCMIEF:1; /* command ignored error flag */\r
+ vuint16_t FOVBEF:1; /* receive FIFO overrun channel B error flag */\r
+ vuint16_t FOVAEF:1; /* receive FIFO overrun channel A error flag */\r
+ vuint16_t MSBEF:1; /* message buffer search error flag */\r
+ vuint16_t MBUEF:1; /* message buffer utilization error flag */\r
+ vuint16_t LCKEF:1; /* lock error flag */\r
+ vuint16_t DBLEF:1; /* double transmit message buffer lock error flag */\r
+ vuint16_t SBCFEF:1; /* system bus communication failure error flag */\r
+ vuint16_t FIDEF:1; /* frame ID error flag */\r
+ vuint16_t DPLEF:1; /* dynamic payload length error flag */\r
+ vuint16_t SPLEF:1; /* static payload length error flag */\r
+ vuint16_t NMLEF:1; /* network management length error flag */\r
+ vuint16_t NMFEF:1; /* network management frame error flag */\r
+ vuint16_t ILSAEF:1; /* illegal access error flag */\r
+ } B;\r
+ } CHIERFR_t;\r
+ typedef union uMBIVEC {\r
+ vuint16_t R;\r
+ struct {\r
+\r
+ vuint16_t:2;\r
+ vuint16_t TBIVEC:6; /* transmit buffer interrupt vector */\r
+ vuint16_t:2;\r
+ vuint16_t RBIVEC:6; /* receive buffer interrupt vector */\r
+ } B;\r
+ } MBIVEC_t;\r
+\r
+ typedef union uPSR0 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t ERRMODE:2; /* error mode */\r
+ vuint16_t SLOTMODE:2; /* slot mode */\r
+ vuint16_t:1;\r
+ vuint16_t PROTSTATE:3; /* protocol state */\r
+ vuint16_t SUBSTATE:4; /* protocol sub state */\r
+ vuint16_t:1;\r
+ vuint16_t WAKEUPSTATUS:3; /* wakeup status */\r
+ } B;\r
+ } PSR0_t;\r
+\r
+/* protocol states */\r
+/* protocol sub-states */\r
+/* wakeup status */\r
+ typedef union uPSR1 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t CSAA:1; /* cold start attempt abort flag */\r
+ vuint16_t SCP:1; /* cold start path */\r
+ vuint16_t:1;\r
+ vuint16_t REMCSAT:5; /* remanining coldstart attempts */\r
+ vuint16_t CPN:1; /* cold start noise path */\r
+ vuint16_t HHR:1; /* host halt request pending */\r
+ vuint16_t FRZ:1; /* freeze occured */\r
+ vuint16_t APTAC:5; /* allow passive to active counter */\r
+ } B;\r
+ } PSR1_t;\r
+ typedef union uPSR2 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t NBVB:1; /* NIT boundary violation on channel B */\r
+ vuint16_t NSEB:1; /* NIT syntax error on channel B */\r
+ vuint16_t STCB:1; /* symbol window transmit conflict on channel B */\r
+ vuint16_t SBVB:1; /* symbol window boundary violation on channel B */\r
+ vuint16_t SSEB:1; /* symbol window syntax error on channel B */\r
+ vuint16_t MTB:1; /* media access test symbol MTS received on channel B */\r
+ vuint16_t NBVA:1; /* NIT boundary violation on channel A */\r
+ vuint16_t NSEA:1; /* NIT syntax error on channel A */\r
+ vuint16_t STCA:1; /* symbol window transmit conflict on channel A */\r
+ vuint16_t SBVA:1; /* symbol window boundary violation on channel A */\r
+ vuint16_t SSEA:1; /* symbol window syntax error on channel A */\r
+ vuint16_t MTA:1; /* media access test symbol MTS received on channel A */\r
+ vuint16_t CLKCORRFAILCNT:4; /* clock correction failed counter */\r
+ } B;\r
+ } PSR2_t;\r
+ typedef union uPSR3 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:2;\r
+ vuint16_t WUB:1; /* wakeup symbol received on channel B */\r
+ vuint16_t ABVB:1; /* aggregated boundary violation on channel B */\r
+ vuint16_t AACB:1; /* aggregated additional communication on channel B */\r
+ vuint16_t ACEB:1; /* aggregated content error on channel B */\r
+ vuint16_t ASEB:1; /* aggregated syntax error on channel B */\r
+ vuint16_t AVFB:1; /* aggregated valid frame on channel B */\r
+ vuint16_t:2;\r
+ vuint16_t WUA:1; /* wakeup symbol received on channel A */\r
+ vuint16_t ABVA:1; /* aggregated boundary violation on channel A */\r
+ vuint16_t AACA:1; /* aggregated additional communication on channel A */\r
+ vuint16_t ACEA:1; /* aggregated content error on channel A */\r
+ vuint16_t ASEA:1; /* aggregated syntax error on channel A */\r
+ vuint16_t AVFA:1; /* aggregated valid frame on channel A */\r
+ } B;\r
+ } PSR3_t;\r
+ typedef union uCIFRR {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:8;\r
+ vuint16_t MIFR:1; /* module interrupt flag */\r
+ vuint16_t PRIFR:1; /* protocol interrupt flag */\r
+ vuint16_t CHIFR:1; /* CHI interrupt flag */\r
+ vuint16_t WUPIFR:1; /* wakeup interrupt flag */\r
+ vuint16_t FNEBIFR:1; /* receive fifo channel B no empty interrupt flag */\r
+ vuint16_t FNEAIFR:1; /* receive fifo channel A no empty interrupt flag */\r
+ vuint16_t RBIFR:1; /* receive message buffer interrupt flag */\r
+ vuint16_t TBIFR:1; /* transmit buffer interrupt flag */\r
+ } B;\r
+ } CIFRR_t;\r
+ typedef union uSFCNTR {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t SFEVB:4; /* sync frames channel B, even cycle */\r
+ vuint16_t SFEVA:4; /* sync frames channel A, even cycle */\r
+ vuint16_t SFODB:4; /* sync frames channel B, odd cycle */\r
+ vuint16_t SFODA:4; /* sync frames channel A, odd cycle */\r
+ } B;\r
+ } SFCNTR_t;\r
+\r
+ typedef union uSFTCCSR {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t ELKT:1; /* even cycle tables lock and unlock trigger */\r
+ vuint16_t OLKT:1; /* odd cycle tables lock and unlock trigger */\r
+ vuint16_t CYCNUM:6; /* cycle number */\r
+ vuint16_t ELKS:1; /* even cycle tables lock status */\r
+ vuint16_t OLKS:1; /* odd cycle tables lock status */\r
+ vuint16_t EVAL:1; /* even cycle tables valid */\r
+ vuint16_t OVAL:1; /* odd cycle tables valid */\r
+ vuint16_t:1;\r
+ vuint16_t OPT:1; /*one pair trigger */\r
+ vuint16_t SDVEN:1; /* sync frame deviation table enable */\r
+ vuint16_t SIDEN:1; /* sync frame ID table enable */\r
+ } B;\r
+ } SFTCCSR_t;\r
+ typedef union uSFIDRFR {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:6;\r
+ vuint16_t SYNFRID:10; /* sync frame rejection ID */\r
+ } B;\r
+ } SFIDRFR_t;\r
+\r
+ typedef union uTICCR {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:2;\r
+ vuint16_t T2CFG:1; /* timer 2 configuration */\r
+ vuint16_t T2REP:1; /* timer 2 repetitive mode */\r
+ vuint16_t:1;\r
+ vuint16_t T2SP:1; /* timer 2 stop */\r
+ vuint16_t T2TR:1; /* timer 2 trigger */\r
+ vuint16_t T2ST:1; /* timer 2 state */\r
+ vuint16_t:3;\r
+ vuint16_t T1REP:1; /* timer 1 repetitive mode */\r
+ vuint16_t:1;\r
+ vuint16_t T1SP:1; /* timer 1 stop */\r
+ vuint16_t T1TR:1; /* timer 1 trigger */\r
+ vuint16_t T1ST:1; /* timer 1 state */\r
+\r
+ } B;\r
+ } TICCR_t;\r
+ typedef union uTI1CYSR {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:2;\r
+ vuint16_t TI1CYCVAL:6; /* timer 1 cycle filter value */\r
+ vuint16_t:2;\r
+ vuint16_t TI1CYCMSK:6; /* timer 1 cycle filter mask */\r
+\r
+ } B;\r
+ } TI1CYSR_t;\r
+\r
+ typedef union uSSSR {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t WMD:1; /* write mode */\r
+ vuint16_t:1;\r
+ vuint16_t SEL:2; /* static slot number */\r
+ vuint16_t:1;\r
+ vuint16_t SLOTNUMBER:11; /* selector */\r
+ } B;\r
+ } SSSR_t;\r
+\r
+ typedef union uSSCCR {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t WMD:1; /* write mode */\r
+ vuint16_t:1;\r
+ vuint16_t SEL:2; /* selector */\r
+ vuint16_t:1;\r
+ vuint16_t CNTCFG:2; /* counter configuration */\r
+ vuint16_t MCY:1; /* multi cycle selection */\r
+ vuint16_t VFR:1; /* valid frame selection */\r
+ vuint16_t SYF:1; /* sync frame selection */\r
+ vuint16_t NUF:1; /* null frame selection */\r
+ vuint16_t SUF:1; /* startup frame selection */\r
+ vuint16_t STATUSMASK:4; /* slot status mask */\r
+ } B;\r
+ } SSCCR_t;\r
+ typedef union uSSR {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t VFB:1; /* valid frame on channel B */\r
+ vuint16_t SYB:1; /* valid sync frame on channel B */\r
+ vuint16_t NFB:1; /* valid null frame on channel B */\r
+ vuint16_t SUB:1; /* valid startup frame on channel B */\r
+ vuint16_t SEB:1; /* syntax error on channel B */\r
+ vuint16_t CEB:1; /* content error on channel B */\r
+ vuint16_t BVB:1; /* boundary violation on channel B */\r
+ vuint16_t TCB:1; /* tx conflict on channel B */\r
+ vuint16_t VFA:1; /* valid frame on channel A */\r
+ vuint16_t SYA:1; /* valid sync frame on channel A */\r
+ vuint16_t NFA:1; /* valid null frame on channel A */\r
+ vuint16_t SUA:1; /* valid startup frame on channel A */\r
+ vuint16_t SEA:1; /* syntax error on channel A */\r
+ vuint16_t CEA:1; /* content error on channel A */\r
+ vuint16_t BVA:1; /* boundary violation on channel A */\r
+ vuint16_t TCA:1; /* tx conflict on channel A */\r
+ } B;\r
+ } SSR_t;\r
+ typedef union uMTSCFR {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t MTE:1; /* media access test symbol transmission enable */\r
+ vuint16_t:1;\r
+ vuint16_t CYCCNTMSK:6; /* cycle counter mask */\r
+ vuint16_t:2;\r
+ vuint16_t CYCCNTVAL:6; /* cycle counter value */\r
+ } B;\r
+ } MTSCFR_t;\r
+\r
+ typedef union uRSBIR {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t WMD:1; /* write mode */\r
+ vuint16_t:1;\r
+ vuint16_t SEL:2; /* selector */\r
+ vuint16_t:5;\r
+ vuint16_t RSBIDX:7; /* receive shadow buffer index */\r
+ } B;\r
+ } RSBIR_t;\r
+\r
+ typedef union uRFDSR {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t FIFODEPTH:8; /* fifo depth */\r
+ vuint16_t:1;\r
+ vuint16_t ENTRYSIZE:7; /* entry size */\r
+ } B;\r
+ } RFDSR_t;\r
+\r
+ typedef union uRFRFCFR {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t WMD:1; /* write mode */\r
+ vuint16_t IBD:1; /* interval boundary */\r
+ vuint16_t SEL:2; /* filter number */\r
+ vuint16_t:1;\r
+ vuint16_t SID:11; /* slot ID */\r
+ } B;\r
+ } RFRFCFR_t;\r
+\r
+ typedef union uRFRFCTR {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:4;\r
+ vuint16_t F3MD:1; /* filter mode */\r
+ vuint16_t F2MD:1; /* filter mode */\r
+ vuint16_t F1MD:1; /* filter mode */\r
+ vuint16_t F0MD:1; /* filter mode */\r
+ vuint16_t:4;\r
+ vuint16_t F3EN:1; /* filter enable */\r
+ vuint16_t F2EN:1; /* filter enable */\r
+ vuint16_t F1EN:1; /* filter enable */\r
+ vuint16_t F0EN:1; /* filter enable */\r
+ } B;\r
+ } RFRFCTR_t;\r
+ typedef union uPCR0 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t ACTION_POINT_OFFSET:6;\r
+ vuint16_t STATIC_SLOT_LENGTH:10;\r
+ } B;\r
+ } PCR0_t;\r
+\r
+ typedef union uPCR1 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:2;\r
+ vuint16_t MACRO_AFTER_FIRST_STATIC_SLOT:14;\r
+ } B;\r
+ } PCR1_t;\r
+\r
+ typedef union uPCR2 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t MINISLOT_AFTER_ACTION_POINT:6;\r
+ vuint16_t NUMBER_OF_STATIC_SLOTS:10;\r
+ } B;\r
+ } PCR2_t;\r
+\r
+ typedef union uPCR3 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t WAKEUP_SYMBOL_RX_LOW:6;\r
+ vuint16_t MINISLOT_ACTION_POINT_OFFSET:5;\r
+ vuint16_t COLDSTART_ATTEMPTS:5;\r
+ } B;\r
+ } PCR3_t;\r
+\r
+ typedef union uPCR4 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t CAS_RX_LOW_MAX:7;\r
+ vuint16_t WAKEUP_SYMBOL_RX_WINDOW:9;\r
+ } B;\r
+ } PCR4_t;\r
+\r
+ typedef union uPCR5 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t TSS_TRANSMITTER:4;\r
+ vuint16_t WAKEUP_SYMBOL_TX_LOW:6;\r
+ vuint16_t WAKEUP_SYMBOL_RX_IDLE:6;\r
+ } B;\r
+ } PCR5_t;\r
+\r
+ typedef union uPCR6 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:1;\r
+ vuint16_t SYMBOL_WINDOW_AFTER_ACTION_POINT:8;\r
+ vuint16_t MACRO_INITIAL_OFFSET_A:7;\r
+ } B;\r
+ } PCR6_t;\r
+\r
+ typedef union uPCR7 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t DECODING_CORRECTION_B:9;\r
+ vuint16_t MICRO_PER_MACRO_NOM_HALF:7;\r
+ } B;\r
+ } PCR7_t;\r
+\r
+ typedef union uPCR8 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t MAX_WITHOUT_CLOCK_CORRECTION_FATAL:4;\r
+ vuint16_t MAX_WITHOUT_CLOCK_CORRECTION_PASSIVE:4;\r
+ vuint16_t WAKEUP_SYMBOL_TX_IDLE:8;\r
+ } B;\r
+ } PCR8_t;\r
+\r
+ typedef union uPCR9 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t MINISLOT_EXISTS:1;\r
+ vuint16_t SYMBOL_WINDOW_EXISTS:1;\r
+ vuint16_t OFFSET_CORRECTION_OUT:14;\r
+ } B;\r
+ } PCR9_t;\r
+\r
+ typedef union uPCR10 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t SINGLE_SLOT_ENABLED:1;\r
+ vuint16_t WAKEUP_CHANNEL:1;\r
+ vuint16_t MACRO_PER_CYCLE:14;\r
+ } B;\r
+ } PCR10_t;\r
+\r
+ typedef union uPCR11 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t KEY_SLOT_USED_FOR_STARTUP:1;\r
+ vuint16_t KEY_SLOT_USED_FOR_SYNC:1;\r
+ vuint16_t OFFSET_CORRECTION_START:14;\r
+ } B;\r
+ } PCR11_t;\r
+\r
+ typedef union uPCR12 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t ALLOW_PASSIVE_TO_ACTIVE:5;\r
+ vuint16_t KEY_SLOT_HEADER_CRC:11;\r
+ } B;\r
+ } PCR12_t;\r
+\r
+ typedef union uPCR13 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t FIRST_MINISLOT_ACTION_POINT_OFFSET:6;\r
+ vuint16_t STATIC_SLOT_AFTER_ACTION_POINT:10;\r
+ } B;\r
+ } PCR13_t;\r
+\r
+ typedef union uPCR14 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t RATE_CORRECTION_OUT:11;\r
+ vuint16_t LISTEN_TIMEOUT_H:5;\r
+ } B;\r
+ } PCR14_t;\r
+\r
+ typedef union uPCR15 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t LISTEN_TIMEOUT_L:16;\r
+ } B;\r
+ } PCR15_t;\r
+\r
+ typedef union uPCR16 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t MACRO_INITIAL_OFFSET_B:7;\r
+ vuint16_t NOISE_LISTEN_TIMEOUT_H:9;\r
+ } B;\r
+ } PCR16_t;\r
+\r
+ typedef union uPCR17 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t NOISE_LISTEN_TIMEOUT_L:16;\r
+ } B;\r
+ } PCR17_t;\r
+\r
+ typedef union uPCR18 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t WAKEUP_PATTERN:6;\r
+ vuint16_t KEY_SLOT_ID:10;\r
+ } B;\r
+ } PCR18_t;\r
+\r
+ typedef union uPCR19 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t DECODING_CORRECTION_A:9;\r
+ vuint16_t PAYLOAD_LENGTH_STATIC:7;\r
+ } B;\r
+ } PCR19_t;\r
+\r
+ typedef union uPCR20 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t MICRO_INITIAL_OFFSET_B:8;\r
+ vuint16_t MICRO_INITIAL_OFFSET_A:8;\r
+ } B;\r
+ } PCR20_t;\r
+\r
+ typedef union uPCR21 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t EXTERN_RATE_CORRECTION:3;\r
+ vuint16_t LATEST_TX:13;\r
+ } B;\r
+ } PCR21_t;\r
+\r
+ typedef union uPCR22 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:1;\r
+ vuint16_t COMP_ACCEPTED_STARTUP_RANGE_A:11;\r
+ vuint16_t MICRO_PER_CYCLE_H:4;\r
+ } B;\r
+ } PCR22_t;\r
+\r
+ typedef union uPCR23 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t micro_per_cycle_l:16;\r
+ } B;\r
+ } PCR23_t;\r
+\r
+ typedef union uPCR24 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t CLUSTER_DRIFT_DAMPING:5;\r
+ vuint16_t MAX_PAYLOAD_LENGTH_DYNAMIC:7;\r
+ vuint16_t MICRO_PER_CYCLE_MIN_H:4;\r
+ } B;\r
+ } PCR24_t;\r
+\r
+ typedef union uPCR25 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t MICRO_PER_CYCLE_MIN_L:16;\r
+ } B;\r
+ } PCR25_t;\r
+\r
+ typedef union uPCR26 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t ALLOW_HALT_DUE_TO_CLOCK:1;\r
+ vuint16_t COMP_ACCEPTED_STARTUP_RANGE_B:11;\r
+ vuint16_t MICRO_PER_CYCLE_MAX_H:4;\r
+ } B;\r
+ } PCR26_t;\r
+\r
+ typedef union uPCR27 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t MICRO_PER_CYCLE_MAX_L:16;\r
+ } B;\r
+ } PCR27_t;\r
+\r
+ typedef union uPCR28 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t DYNAMIC_SLOT_IDLE_PHASE:2;\r
+ vuint16_t MACRO_AFTER_OFFSET_CORRECTION:14;\r
+ } B;\r
+ } PCR28_t;\r
+\r
+ typedef union uPCR29 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t EXTERN_OFFSET_CORRECTION:3;\r
+ vuint16_t MINISLOTS_MAX:13;\r
+ } B;\r
+ } PCR29_t;\r
+\r
+ typedef union uPCR30 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:12;\r
+ vuint16_t SYNC_NODE_MAX:4;\r
+ } B;\r
+ } PCR30_t;\r
+\r
+ typedef struct uMSG_BUFF_CCS {\r
+ union {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:1;\r
+ vuint16_t MCM:1; /* message buffer commit mode */\r
+ vuint16_t MBT:1; /* message buffer type */\r
+ vuint16_t MTD:1; /* message buffer direction */\r
+ vuint16_t CMT:1; /* commit for transmission */\r
+ vuint16_t EDT:1; /* enable / disable trigger */\r
+ vuint16_t LCKT:1; /* lock request trigger */\r
+ vuint16_t MBIE:1; /* message buffer interrupt enable */\r
+ vuint16_t:3;\r
+ vuint16_t DUP:1; /* data updated */\r
+ vuint16_t DVAL:1; /* data valid */\r
+ vuint16_t EDS:1; /* lock status */\r
+ vuint16_t LCKS:1; /* enable / disable status */\r
+ vuint16_t MBIF:1; /* message buffer interrupt flag */\r
+ } B;\r
+ } MBCCSR;\r
+ union {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t MTM:1; /* message buffer transmission mode */\r
+ vuint16_t CHNLA:1; /* channel assignement */\r
+ vuint16_t CHNLB:1; /* channel assignement */\r
+ vuint16_t CCFE:1; /* cycle counter filter enable */\r
+ vuint16_t CCFMSK:6; /* cycle counter filter mask */\r
+ vuint16_t CCFVAL:6; /* cycle counter filter value */\r
+ } B;\r
+ } MBCCFR;\r
+ union {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:5;\r
+ vuint16_t FID:11; /* frame ID */\r
+ } B;\r
+ } MBFIDR;\r
+\r
+ union {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:9;\r
+ vuint16_t MBIDX:7; /* message buffer index */\r
+ } B;\r
+ } MBIDXR;\r
+ } MSG_BUFF_CCS_t;\r
+ typedef union uSYSBADHR {\r
+ vuint16_t R;\r
+ } SYSBADHR_t;\r
+ typedef union uSYSBADLR {\r
+ vuint16_t R;\r
+ } SYSBADLR_t;\r
+ typedef union uPADR {\r
+ vuint16_t R;\r
+ } PADR_t;\r
+ typedef union uPDAR {\r
+ vuint16_t R;\r
+ } PDAR_t;\r
+ typedef union uCASERCR {\r
+ vuint16_t R;\r
+ } CASERCR_t;\r
+ typedef union uCBSERCR {\r
+ vuint16_t R;\r
+ } CBSERCR_t;\r
+ typedef union uCYCTR {\r
+ vuint16_t R;\r
+ } CYCTR_t;\r
+ typedef union uMTCTR {\r
+ vuint16_t R;\r
+ } MTCTR_t;\r
+ typedef union uSLTCTAR {\r
+ vuint16_t R;\r
+ } SLTCTAR_t;\r
+ typedef union uSLTCTBR {\r
+ vuint16_t R;\r
+ } SLTCTBR_t;\r
+ typedef union uRTCORVR {\r
+ vuint16_t R;\r
+ } RTCORVR_t;\r
+ typedef union uOFCORVR {\r
+ vuint16_t R;\r
+ } OFCORVR_t;\r
+ typedef union uSFTOR {\r
+ vuint16_t R;\r
+ } SFTOR_t;\r
+ typedef union uSFIDAFVR {\r
+ vuint16_t R;\r
+ } SFIDAFVR_t;\r
+ typedef union uSFIDAFMR {\r
+ vuint16_t R;\r
+ } SFIDAFMR_t;\r
+ typedef union uNMVR {\r
+ vuint16_t R;\r
+ } NMVR_t;\r
+ typedef union uNMVLR {\r
+ vuint16_t R;\r
+ } NMVLR_t;\r
+ typedef union uT1MTOR {\r
+ vuint16_t R;\r
+ } T1MTOR_t;\r
+ typedef union uTI2CR0 {\r
+ vuint16_t R;\r
+ } TI2CR0_t;\r
+ typedef union uTI2CR1 {\r
+ vuint16_t R;\r
+ } TI2CR1_t;\r
+ typedef union uSSCR {\r
+ vuint16_t R;\r
+ } SSCR_t;\r
+ typedef union uRFSR {\r
+ vuint16_t R;\r
+ } RFSR_t;\r
+ typedef union uRFSIR {\r
+ vuint16_t R;\r
+ } RFSIR_t;\r
+ typedef union uRFARIR {\r
+ vuint16_t R;\r
+ } RFARIR_t;\r
+ typedef union uRFBRIR {\r
+ vuint16_t R;\r
+ } RFBRIR_t;\r
+ typedef union uRFMIDAFVR {\r
+ vuint16_t R;\r
+ } RFMIDAFVR_t;\r
+ typedef union uRFMIAFMR {\r
+ vuint16_t R;\r
+ } RFMIAFMR_t;\r
+ typedef union uRFFIDRFVR {\r
+ vuint16_t R;\r
+ } RFFIDRFVR_t;\r
+ typedef union uRFFIDRFMR {\r
+ vuint16_t R;\r
+ } RFFIDRFMR_t;\r
+ typedef union uLDTXSLAR {\r
+ vuint16_t R;\r
+ } LDTXSLAR_t;\r
+ typedef union uLDTXSLBR {\r
+ vuint16_t R;\r
+ } LDTXSLBR_t;\r
+\r
+ typedef struct FR_tag {\r
+ volatile MVR_t MVR; /*module version register *//*0 */\r
+ volatile MCR_t MCR; /*module configuration register *//*2 */\r
+ volatile SYSBADHR_t SYSBADHR; /*system memory base address high register *//*4 */\r
+ volatile SYSBADLR_t SYSBADLR; /*system memory base address low register *//*6 */\r
+ volatile STBSCR_t STBSCR; /*strobe signal control register *//*8 */\r
+ volatile STBPCR_t STBPCR; /*strobe port control register *//*A */\r
+ volatile MBDSR_t MBDSR; /*message buffer data size register *//*C */\r
+ volatile MBSSUTR_t MBSSUTR; /*message buffer segment size and utilization register *//*E */\r
+ volatile PADR_t PADR; /*PE address register *//*10 */\r
+ volatile PDAR_t PDAR; /*PE data register *//*12 */\r
+ volatile POCR_t POCR; /*Protocol operation control register *//*14 */\r
+ volatile GIFER_t GIFER; /*global interrupt flag and enable register *//*16 */\r
+ volatile PIFR0_t PIFR0; /*protocol interrupt flag register 0 *//*18 */\r
+ volatile PIFR1_t PIFR1; /*protocol interrupt flag register 1 *//*1A */\r
+ volatile PIER0_t PIER0; /*protocol interrupt enable register 0 *//*1C */\r
+ volatile PIER1_t PIER1; /*protocol interrupt enable register 1 *//*1E */\r
+ volatile CHIERFR_t CHIERFR; /*CHI error flag register *//*20 */\r
+ volatile MBIVEC_t MBIVEC; /*message buffer interrupt vector register *//*22 */\r
+ volatile CASERCR_t CASERCR; /*channel A status error counter register *//*24 */\r
+ volatile CBSERCR_t CBSERCR; /*channel B status error counter register *//*26 */\r
+ volatile PSR0_t PSR0; /*protocol status register 0 *//*28 */\r
+ volatile PSR1_t PSR1; /*protocol status register 1 *//*2A */\r
+ volatile PSR2_t PSR2; /*protocol status register 2 *//*2C */\r
+ volatile PSR3_t PSR3; /*protocol status register 3 *//*2E */\r
+ volatile MTCTR_t MTCTR; /*macrotick counter register *//*30 */\r
+ volatile CYCTR_t CYCTR; /*cycle counter register *//*32 */\r
+ volatile SLTCTAR_t SLTCTAR; /*slot counter channel A register *//*34 */\r
+ volatile SLTCTBR_t SLTCTBR; /*slot counter channel B register *//*36 */\r
+ volatile RTCORVR_t RTCORVR; /*rate correction value register *//*38 */\r
+ volatile OFCORVR_t OFCORVR; /*offset correction value register *//*3A */\r
+ volatile CIFRR_t CIFRR; /*combined interrupt flag register *//*3C */\r
+ vuint16_t reserved3[1]; /*3E */\r
+ volatile SFCNTR_t SFCNTR; /*sync frame counter register *//*40 */\r
+ volatile SFTOR_t SFTOR; /*sync frame table offset register *//*42 */\r
+ volatile SFTCCSR_t SFTCCSR; /*sync frame table configuration, control, status register *//*44 */\r
+ volatile SFIDRFR_t SFIDRFR; /*sync frame ID rejection filter register *//*46 */\r
+ volatile SFIDAFVR_t SFIDAFVR; /*sync frame ID acceptance filter value regiater *//*48 */\r
+ volatile SFIDAFMR_t SFIDAFMR; /*sync frame ID acceptance filter mask register *//*4A */\r
+ volatile NMVR_t NMVR[6]; /*network management vector registers (12 bytes) *//*4C */\r
+ volatile NMVLR_t NMVLR; /*network management vector length register *//*58 */\r
+ volatile TICCR_t TICCR; /*timer configuration and control register *//*5A */\r
+ volatile TI1CYSR_t TI1CYSR; /*timer 1 cycle set register *//*5C */\r
+ volatile T1MTOR_t T1MTOR; /*timer 1 macrotick offset register *//*5E */\r
+ volatile TI2CR0_t TI2CR0; /*timer 2 configuration register 0 *//*60 */\r
+ volatile TI2CR1_t TI2CR1; /*timer 2 configuration register 1 *//*62 */\r
+ volatile SSSR_t SSSR; /*slot status selection register *//*64 */\r
+ volatile SSCCR_t SSCCR; /*slot status counter condition register *//*66 */\r
+ volatile SSR_t SSR[8]; /*slot status registers 0-7 *//*68 */\r
+ volatile SSCR_t SSCR[4]; /*slot status counter registers 0-3 *//*78 */\r
+ volatile MTSCFR_t MTSACFR; /*mts a config register *//*80 */\r
+ volatile MTSCFR_t MTSBCFR; /*mts b config register *//*82 */\r
+ volatile RSBIR_t RSBIR; /*receive shadow buffer index register *//*84 */\r
+ volatile RFSR_t RFSR; /*receive fifo selection register *//*86 */\r
+ volatile RFSIR_t RFSIR; /*receive fifo start index register *//*88 */\r
+ volatile RFDSR_t RFDSR; /*receive fifo depth and size register *//*8A */\r
+ volatile RFARIR_t RFARIR; /*receive fifo a read index register *//*8C */\r
+ volatile RFBRIR_t RFBRIR; /*receive fifo b read index register *//*8E */\r
+ volatile RFMIDAFVR_t RFMIDAFVR; /*receive fifo message ID acceptance filter value register *//*90 */\r
+ volatile RFMIAFMR_t RFMIAFMR; /*receive fifo message ID acceptance filter mask register *//*92 */\r
+ volatile RFFIDRFVR_t RFFIDRFVR; /*receive fifo frame ID rejection filter value register *//*94 */\r
+ volatile RFFIDRFMR_t RFFIDRFMR; /*receive fifo frame ID rejection filter mask register *//*96 */\r
+ volatile RFRFCFR_t RFRFCFR; /*receive fifo range filter configuration register *//*98 */\r
+ volatile RFRFCTR_t RFRFCTR; /*receive fifo range filter control register *//*9A */\r
+ volatile LDTXSLAR_t LDTXSLAR; /*last dynamic transmit slot channel A register *//*9C */\r
+ volatile LDTXSLBR_t LDTXSLBR; /*last dynamic transmit slot channel B register *//*9E */\r
+ volatile PCR0_t PCR0; /*protocol configuration register 0 *//*A0 */\r
+ volatile PCR1_t PCR1; /*protocol configuration register 1 *//*A2 */\r
+ volatile PCR2_t PCR2; /*protocol configuration register 2 *//*A4 */\r
+ volatile PCR3_t PCR3; /*protocol configuration register 3 *//*A6 */\r
+ volatile PCR4_t PCR4; /*protocol configuration register 4 *//*A8 */\r
+ volatile PCR5_t PCR5; /*protocol configuration register 5 *//*AA */\r
+ volatile PCR6_t PCR6; /*protocol configuration register 6 *//*AC */\r
+ volatile PCR7_t PCR7; /*protocol configuration register 7 *//*AE */\r
+ volatile PCR8_t PCR8; /*protocol configuration register 8 *//*B0 */\r
+ volatile PCR9_t PCR9; /*protocol configuration register 9 *//*B2 */\r
+ volatile PCR10_t PCR10; /*protocol configuration register 10 *//*B4 */\r
+ volatile PCR11_t PCR11; /*protocol configuration register 11 *//*B6 */\r
+ volatile PCR12_t PCR12; /*protocol configuration register 12 *//*B8 */\r
+ volatile PCR13_t PCR13; /*protocol configuration register 13 *//*BA */\r
+ volatile PCR14_t PCR14; /*protocol configuration register 14 *//*BC */\r
+ volatile PCR15_t PCR15; /*protocol configuration register 15 *//*BE */\r
+ volatile PCR16_t PCR16; /*protocol configuration register 16 *//*C0 */\r
+ volatile PCR17_t PCR17; /*protocol configuration register 17 *//*C2 */\r
+ volatile PCR18_t PCR18; /*protocol configuration register 18 *//*C4 */\r
+ volatile PCR19_t PCR19; /*protocol configuration register 19 *//*C6 */\r
+ volatile PCR20_t PCR20; /*protocol configuration register 20 *//*C8 */\r
+ volatile PCR21_t PCR21; /*protocol configuration register 21 *//*CA */\r
+ volatile PCR22_t PCR22; /*protocol configuration register 22 *//*CC */\r
+ volatile PCR23_t PCR23; /*protocol configuration register 23 *//*CE */\r
+ volatile PCR24_t PCR24; /*protocol configuration register 24 *//*D0 */\r
+ volatile PCR25_t PCR25; /*protocol configuration register 25 *//*D2 */\r
+ volatile PCR26_t PCR26; /*protocol configuration register 26 *//*D4 */\r
+ volatile PCR27_t PCR27; /*protocol configuration register 27 *//*D6 */\r
+ volatile PCR28_t PCR28; /*protocol configuration register 28 *//*D8 */\r
+ volatile PCR29_t PCR29; /*protocol configuration register 29 *//*DA */\r
+ volatile PCR30_t PCR30; /*protocol configuration register 30 *//*DC */\r
+ vuint16_t reserved2[17];\r
+ volatile MSG_BUFF_CCS_t MBCCS[128]; /* message buffer configuration, control & status registers 0-31 *//*100 */\r
+ } FR_tag_t;\r
+\r
+ typedef union uF_HEADER /* frame header */\r
+ {\r
+ struct {\r
+ vuint16_t:5;\r
+ vuint16_t HDCRC:11; /* Header CRC */\r
+ vuint16_t:2;\r
+ vuint16_t CYCCNT:6; /* Cycle Count */\r
+ vuint16_t:1;\r
+ vuint16_t PLDLEN:7; /* Payload Length */\r
+ vuint16_t:1;\r
+ vuint16_t PPI:1; /* Payload Preamble Indicator */\r
+ vuint16_t NUF:1; /* Null Frame Indicator */\r
+ vuint16_t SYF:1; /* Sync Frame Indicator */\r
+ vuint16_t SUF:1; /* Startup Frame Indicator */\r
+ vuint16_t FID:11; /* Frame ID */\r
+ } B;\r
+ vuint16_t WORDS[3];\r
+ } F_HEADER_t;\r
+ typedef union uS_STSTUS /* slot status */\r
+ {\r
+ struct {\r
+ vuint16_t VFB:1; /* Valid Frame on channel B */\r
+ vuint16_t SYB:1; /* Sync Frame Indicator channel B */\r
+ vuint16_t NFB:1; /* Null Frame Indicator channel B */\r
+ vuint16_t SUB:1; /* Startup Frame Indicator channel B */\r
+ vuint16_t SEB:1; /* Syntax Error on channel B */\r
+ vuint16_t CEB:1; /* Content Error on channel B */\r
+ vuint16_t BVB:1; /* Boundary Violation on channel B */\r
+ vuint16_t CH:1; /* Channel */\r
+ vuint16_t VFA:1; /* Valid Frame on channel A */\r
+ vuint16_t SYA:1; /* Sync Frame Indicator channel A */\r
+ vuint16_t NFA:1; /* Null Frame Indicator channel A */\r
+ vuint16_t SUA:1; /* Startup Frame Indicator channel A */\r
+ vuint16_t SEA:1; /* Syntax Error on channel A */\r
+ vuint16_t CEA:1; /* Content Error on channel A */\r
+ vuint16_t BVA:1; /* Boundary Violation on channel A */\r
+ vuint16_t:1;\r
+ } RX;\r
+ struct {\r
+ vuint16_t VFB:1; /* Valid Frame on channel B */\r
+ vuint16_t SYB:1; /* Sync Frame Indicator channel B */\r
+ vuint16_t NFB:1; /* Null Frame Indicator channel B */\r
+ vuint16_t SUB:1; /* Startup Frame Indicator channel B */\r
+ vuint16_t SEB:1; /* Syntax Error on channel B */\r
+ vuint16_t CEB:1; /* Content Error on channel B */\r
+ vuint16_t BVB:1; /* Boundary Violation on channel B */\r
+ vuint16_t TCB:1; /* Tx Conflict on channel B */\r
+ vuint16_t VFA:1; /* Valid Frame on channel A */\r
+ vuint16_t SYA:1; /* Sync Frame Indicator channel A */\r
+ vuint16_t NFA:1; /* Null Frame Indicator channel A */\r
+ vuint16_t SUA:1; /* Startup Frame Indicator channel A */\r
+ vuint16_t SEA:1; /* Syntax Error on channel A */\r
+ vuint16_t CEA:1; /* Content Error on channel A */\r
+ vuint16_t BVA:1; /* Boundary Violation on channel A */\r
+ vuint16_t TCA:1; /* Tx Conflict on channel A */\r
+ } TX;\r
+ vuint16_t R;\r
+ } S_STATUS_t;\r
+\r
+ typedef struct uMB_HEADER /* message buffer header */\r
+ {\r
+ F_HEADER_t FRAME_HEADER;\r
+ vuint16_t DATA_OFFSET;\r
+ S_STATUS_t SLOT_STATUS;\r
+ } MB_HEADER_t;\r
+\r
+/* Define memories */\r
+\r
+#define SRAM_START 0x40000000\r
+#define SRAM_SIZE 0x10000\r
+#define SRAM_END 0x4000FFFF\r
+\r
+#define FLASH_START 0x0\r
+#define FLASH_SIZE 0x100000\r
+#define FLASH_END 0xFFFFF\r
+\r
+/* Define instances of modules */\r
+//#define PBRIDGE_A (*( struct PBRIDGE_A_tag *) 0xC3F00000)\r
+#define MPU (*( struct MPU_tag *) 0xFFF10000)\r
+#define SEMA4 (*( struct SEMA4_tag *) 0xFFF14000)\r
+\r
+#define MCM (*( struct MCM_tag *) 0xFFF40000)\r
+#define EDMA (*( struct EDMA_tag *) 0xFFF44000)\r
+#define INTC (*( struct INTC_tag *) 0xFFF48000)\r
+\r
+#define EQADC (*( struct EQADC_tag *) 0xFFF80000)\r
+\r
+#define I2C (*( struct I2C_tag *) 0xFFF88000)\r
+\r
+#define DSPI_A (*( struct DSPI_tag *) 0xFFF90000)\r
+#define DSPI_B (*( struct DSPI_tag *) 0xFFF94000)\r
+#define DSPI_C (*( struct DSPI_tag *) 0xFFF98000)\r
+#define DSPI_D (*( struct DSPI_tag *) 0xFFF9C000)\r
+\r
+#define ESCI_A (*( struct ESCI_tag *) 0xFFFA0000)\r
+#define ESCI_B (*( struct ESCI_tag *) 0xFFFA4000)\r
+#define ESCI_C (*( struct ESCI_tag *) 0xFFFA8000)\r
+#define ESCI_D (*( struct ESCI_tag *) 0xFFFAC000)\r
+#define ESCI_E (*( struct ESCI_tag *) 0xFFFB0000)\r
+#define ESCI_F (*( struct ESCI_tag *) 0xFFFB4000)\r
+#define ESCI_G (*( struct ESCI_tag *) 0xFFFB8000)\r
+#define ESCI_H (*( struct ESCI_tag *) 0xFFFBC000)\r
+\r
+#define CAN_A (*( struct FLEXCAN_tag *) 0xFFFC0000)\r
+#define CAN_B (*( struct FLEXCAN_tag *) 0xFFFC4000)\r
+#define CAN_C (*( struct FLEXCAN_tag *) 0xFFFC8000)\r
+#define CAN_D (*( struct FLEXCAN_tag *) 0xFFFCC000)\r
+#define CAN_E (*( struct FLEXCAN_tag *) 0xFFFD0000)\r
+#define CAN_F (*( struct FLEXCAN_tag *) 0xFFFD4000)\r
+#define FR (*( struct FR_tag *) 0xFFFD8000)\r
+#define DMAMUX (*( struct DMAMUX_tag *) 0xFFFDC000)\r
+#define PIT (*( struct PIT_tag *) 0xFFFE0000)\r
+#define EMIOS (*( struct EMIOS_tag *) 0xFFFE4000)\r
+#define SIU (*( struct SIU_tag *) 0xFFFE8000)\r
+#define CRP (*( struct CRP_tag *) 0xFFFEC000)\r
+#define FMPLL (*( struct FMPLL_tag *) 0xFFFF0000)\r
+#define EBI (*( struct EBI_tag *) 0xFFFF4000)\r
+#define FLASH (*( struct FLASH_tag *) 0xFFFF8000)\r
+\r
+#ifdef __MWERKS__\r
+#pragma pop\r
+#endif\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+#endif /* ifdef _MPC5516_H */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/**************************************************************************/\r
+/* FILE NAME: mpc5554.h COPYRIGHT (c) Freescale 2007 */\r
+/* VERSION: 1.7 All Rights Reserved */\r
+/* */\r
+/* DESCRIPTION: */\r
+/* This file contain all of the register and bit field definitions for */\r
+/* MPC5554. */\r
+/*========================================================================*/\r
+/* UPDATE HISTORY */\r
+/* REV AUTHOR DATE DESCRIPTION OF CHANGE */\r
+/* --- ----------- --------- --------------------- */\r
+/* 0.01 J. Loeliger 03/Mar/03 Initial version of file for MPC5554. */\r
+/* Based on SoC version 0.7. */\r
+/* 0.02 J. Loeliger 05/Mar/03 All registers and bit fields now */\r
+/* defined. */\r
+/* 0.03 J. Loeliger 05/May/03 Updated to current spec., fixed several*/\r
+/* bugs and naming/formating issues. */\r
+/* 0.04 J. Loeliger 16/May/03 More fixes and naming/formating issues.*/\r
+/* 0.05 J. Loeliger 19/Aug/03 Updated for latest documentation. */\r
+/* 0.06 J. Loeliger 03/Sep/03 Changed to include motint.h */\r
+/* Updated many register names. */\r
+/* 0.07 J. Loeliger 04/Nov/03 Changed to include typedefs.h and more */\r
+/* register name updates. */\r
+/* 0.08 J. Loeliger 25/Feb/04 Added MetroWerks #pragmas. */\r
+/* Updated for user manual 1.0 */\r
+/* 0.09 J. Loeliger 27/Feb/04 Updated eDMA tcd section and some more */\r
+/* bit field names to match user's man. */\r
+/* 0.10 J. Loeliger 01/Apr/04 Fixed register spacing in ADC and eTPU */\r
+/* 0.11 J. Loeliger 16/Jun/04 Many fixes and updated to user's */\r
+/* manual, also some testing done. */\r
+/* 0.12 J. Loeliger 25/Jun/04 Fixed problems in edma and eTPU. */\r
+/* 0.13 J. Loeliger 16/Jul/04 Fixed mistake in FlexCAN TIMER size and*/\r
+/* changed eTPU memory defs to start with*/\r
+/* ETPU_ */\r
+/* 0.14 J. Loeliger 17/Nov/04 Added ETPU_CODE_RAM definition. */\r
+/* All code moved to CVS repository. */\r
+/* Updated copyright to Freescale. */\r
+/* Added new SCMOFFDATAR register to eTPU*/\r
+/* Fixed REDCR_A&B bit fields in eTPU. */\r
+/* Added new DBR bit in CTAR for DSPI. */\r
+/* 0.15 J. Loeliger 29/Nov/04 Added support for new eTPU util funcs. */\r
+/* Added bit fields for FlexCAN buffer ID*/\r
+/* 0.16 J. Loeliger 01/Dec/04 Corrected comments in release 0.16. */\r
+/* 0.17 J. Loeliger 02/Dec/04 Moved eTPU variable definitions to a */\r
+/* seperate new file. */\r
+/* Removed SIU variable the GPIO */\r
+/* routines do not need it. */\r
+/* 1.0 G.Emerson 22/Feb/05 No real changes to this file. */\r
+/* Joint generation with mpc5553.h */\r
+/* 1.1 G. Emerson 6/Jun/05 Changes to SIU to allow for upward */\r
+/* expansion of PCR/GPDI/GPDO */\r
+/* Added #defines for memory sizes etc */\r
+/* 1.2 G. Emerson 21/Sep/05 PBRIDGES fixes */\r
+/* 1.3 G. Emerson 03/Jan/06 Pbridge MPCR/PACR/OPACR now generic */\r
+/* XBAR MPR now generic */\r
+/* ECSM has FSBMCR on all integrations */\r
+/* 1.4 G. Emerson 24/Jan/06 Make Pbridges, XBAR, Flash BIU */\r
+/* integration specific */\r
+/* 1.5 S. Mathieson 28/Jul/06 Split out unused bit to support build */\r
+/* process. No real change. */\r
+/* 1.6 S. Mathieson 30/Aug/06 SPR: L1SCR0, updated bit name from DPP */\r
+/* to DPB to align with documentation. */\r
+/* 1.7 S. Mathieson 26/Feb/07 eDMA TCD format updated to include */\r
+/* alternate configuration. INTC, */\r
+/* correction to the number of PSR */\r
+/* registers. */\r
+/**************************************************************************/\r
+/*>>>>NOTE! this file is auto-generated please do not edit it!<<<<*/\r
+\r
+#ifndef _MPC5554_H_\r
+#define _MPC5554_H_\r
+\r
+#include "typedefs.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+#ifdef __MWERKS__\r
+#pragma push\r
+#pragma ANSI_strict off\r
+#endif\r
+\r
+/****************************************************************************/\r
+/* MODULE : PBRIDGE_A Peripheral Bridge */\r
+/****************************************************************************/\r
+ struct PBRIDGE_A_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MBW0:1;\r
+ vuint32_t MTR0:1;\r
+ vuint32_t MTW0:1;\r
+ vuint32_t MPL0:1;\r
+ vuint32_t MBW1:1;\r
+ vuint32_t MTR1:1;\r
+ vuint32_t MTW1:1;\r
+ vuint32_t MPL1:1;\r
+ vuint32_t MBW2:1;\r
+ vuint32_t MTR2:1;\r
+ vuint32_t MTW2:1;\r
+ vuint32_t MPL2:1;\r
+ vuint32_t MBW3:1;\r
+ vuint32_t MTR3:1;\r
+ vuint32_t MTW3:1;\r
+ vuint32_t MPL3:1;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+ } B;\r
+ } MPCR; /* Master Privilege Control Register */\r
+\r
+ uint32_t pbridge_a_reserved2[7];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BW0:1;\r
+ vuint32_t SP0:1;\r
+ vuint32_t WP0:1;\r
+ vuint32_t TP0:1;\r
+ vuint32_t:28;\r
+ } B;\r
+ } PACR0;\r
+\r
+ uint32_t pbridge_a_reserved3[7];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BW0:1;\r
+ vuint32_t SP0:1;\r
+ vuint32_t WP0:1;\r
+ vuint32_t TP0:1;\r
+ vuint32_t BW1:1;\r
+ vuint32_t SP1:1;\r
+ vuint32_t WP1:1;\r
+ vuint32_t TP1:1;\r
+ vuint32_t BW2:1;\r
+ vuint32_t SP2:1;\r
+ vuint32_t WP2:1;\r
+ vuint32_t TP2:1;\r
+ vuint32_t:4;\r
+ vuint32_t BW4:1;\r
+ vuint32_t SP4:1;\r
+ vuint32_t WP4:1;\r
+ vuint32_t TP4:1;\r
+ vuint32_t:12;\r
+ } B;\r
+ } OPACR0;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+\r
+ vuint32_t BW0:1; /* EMIOS */\r
+ vuint32_t SP0:1;\r
+ vuint32_t WP0:1;\r
+ vuint32_t TP0:1;\r
+\r
+ vuint32_t:28;\r
+ } B;\r
+ } OPACR1;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BW0:1;\r
+ vuint32_t SP0:1;\r
+ vuint32_t WP0:1;\r
+ vuint32_t TP0:1;\r
+ vuint32_t:4;\r
+ vuint32_t BW2:1;\r
+ vuint32_t SP2:1;\r
+ vuint32_t WP2:1;\r
+ vuint32_t TP2:1;\r
+ vuint32_t BW3:1;\r
+ vuint32_t SP3:1;\r
+ vuint32_t WP3:1;\r
+ vuint32_t TP3:1;\r
+ vuint32_t BW4:1;\r
+ vuint32_t SP4:1;\r
+ vuint32_t WP4:1;\r
+ vuint32_t TP4:1;\r
+ vuint32_t:12;\r
+ } B;\r
+ } OPACR2;\r
+\r
+ };\r
+\r
+/****************************************************************************/\r
+/* MODULE : PBRIDGE_B Peripheral Bridge */\r
+/****************************************************************************/\r
+ struct PBRIDGE_B_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MBW0:1;\r
+ vuint32_t MTR0:1;\r
+ vuint32_t MTW0:1;\r
+ vuint32_t MPL0:1;\r
+ vuint32_t MBW1:1;\r
+ vuint32_t MTR1:1;\r
+ vuint32_t MTW1:1;\r
+ vuint32_t MPL1:1;\r
+ vuint32_t MBW2:1;\r
+ vuint32_t MTR2:1;\r
+ vuint32_t MTW2:1;\r
+ vuint32_t MPL2:1;\r
+ vuint32_t MBW3:1;\r
+ vuint32_t MTR3:1;\r
+ vuint32_t MTW3:1;\r
+ vuint32_t MPL3:1;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+ } B;\r
+ } MPCR; /* Master Privilege Control Register */\r
+\r
+ uint32_t pbridge_b_reserved2[7];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BW0:1;\r
+ vuint32_t SP0:1;\r
+ vuint32_t WP0:1;\r
+ vuint32_t TP0:1;\r
+ vuint32_t BW1:1;\r
+ vuint32_t SP1:1;\r
+ vuint32_t WP1:1;\r
+ vuint32_t TP1:1;\r
+ vuint32_t:24;\r
+ } B;\r
+ } PACR0;\r
+\r
+ uint32_t pbridge_b_reserved3;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BW0:1;\r
+ vuint32_t SP0:1;\r
+ vuint32_t WP0:1;\r
+ vuint32_t TP0:1;\r
+ vuint32_t BW1:1;\r
+ vuint32_t SP1:1;\r
+ vuint32_t WP1:1;\r
+ vuint32_t TP1:1;\r
+ vuint32_t BW2:1;\r
+ vuint32_t SP2:1;\r
+ vuint32_t WP2:1;\r
+ vuint32_t TP2:1;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:16;\r
+\r
+ } B;\r
+ } PACR2;\r
+\r
+ uint32_t pbridge_b_reserved4[5];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BW0:1;\r
+ vuint32_t SP0:1;\r
+ vuint32_t WP0:1;\r
+ vuint32_t TP0:1;\r
+ vuint32_t:12;\r
+\r
+ vuint32_t BW4:1; /* DSPI_A */\r
+ vuint32_t SP4:1;\r
+ vuint32_t WP4:1;\r
+ vuint32_t TP4:1;\r
+\r
+ vuint32_t BW5:1; /* DSPI_B */\r
+ vuint32_t SP5:1;\r
+ vuint32_t WP5:1;\r
+ vuint32_t TP5:1;\r
+\r
+ vuint32_t BW6:1;\r
+ vuint32_t SP6:1;\r
+ vuint32_t WP6:1;\r
+ vuint32_t TP6:1;\r
+ vuint32_t BW7:1;\r
+ vuint32_t SP7:1;\r
+ vuint32_t WP7:1;\r
+ vuint32_t TP7:1;\r
+ } B;\r
+ } OPACR0;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t BW4:1;\r
+ vuint32_t SP4:1;\r
+ vuint32_t WP4:1;\r
+ vuint32_t TP4:1;\r
+\r
+ vuint32_t BW5:1; /* ESCI_B */\r
+ vuint32_t SP5:1;\r
+ vuint32_t WP5:1;\r
+ vuint32_t TP5:1;\r
+\r
+ vuint32_t:8;\r
+ } B;\r
+ } OPACR1;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BW0:1;\r
+ vuint32_t SP0:1;\r
+ vuint32_t WP0:1;\r
+ vuint32_t TP0:1;\r
+\r
+ vuint32_t BW1:1; /* CAN_B */\r
+ vuint32_t SP1:1;\r
+ vuint32_t WP1:1;\r
+ vuint32_t TP1:1;\r
+\r
+ vuint32_t BW2:1;\r
+ vuint32_t SP2:1;\r
+ vuint32_t WP2:1;\r
+ vuint32_t TP2:1;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:12;\r
+ } B;\r
+ } OPACR2;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:24;\r
+ vuint32_t BW7:1;\r
+ vuint32_t SP7:1;\r
+ vuint32_t WP7:1;\r
+ vuint32_t TP7:1;\r
+ } B;\r
+ } OPACR3;\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : FMPLL */\r
+/****************************************************************************/\r
+ struct FMPLL_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:1;\r
+ vuint32_t PREDIV:3;\r
+ vuint32_t MFD:5;\r
+ vuint32_t:1;\r
+ vuint32_t RFD:3;\r
+ vuint32_t LOCEN:1;\r
+ vuint32_t LOLRE:1;\r
+ vuint32_t LOCRE:1;\r
+ vuint32_t DISCLK:1;\r
+ vuint32_t LOLIRQ:1;\r
+ vuint32_t LOCIRQ:1;\r
+ vuint32_t RATE:1;\r
+ vuint32_t DEPTH:2;\r
+ vuint32_t EXP:10;\r
+ } B;\r
+ } SYNCR;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:22;\r
+ vuint32_t LOLF:1;\r
+ vuint32_t LOC:1;\r
+ vuint32_t MODE:1;\r
+ vuint32_t PLLSEL:1;\r
+ vuint32_t PLLREF:1;\r
+ vuint32_t LOCKS:1;\r
+ vuint32_t LOCK:1;\r
+ vuint32_t LOCF:1;\r
+ vuint32_t CALDONE:1;\r
+ vuint32_t CALPASS:1;\r
+ } B;\r
+ } SYNSR;\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : External Bus Interface (EBI) */\r
+/****************************************************************************/\r
+ struct CS_tag {\r
+ union { /* Base Register Bank */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BA:17;\r
+ vuint32_t:3;\r
+ vuint32_t PS:1;\r
+ vuint32_t:4;\r
+ vuint32_t BL:1;\r
+ vuint32_t WEBS:1;\r
+ vuint32_t TBDIP:1;\r
+ vuint32_t:2;\r
+ vuint32_t BI:1;\r
+ vuint32_t V:1;\r
+ } B;\r
+ } BR;\r
+\r
+ union { /* Option Register Bank */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t AM:17;\r
+ vuint32_t:7;\r
+ vuint32_t SCY:4;\r
+ vuint32_t:1;\r
+ vuint32_t BSCY:2;\r
+ vuint32_t:1;\r
+ } B;\r
+ } OR;\r
+ };\r
+ struct EBI_tag {\r
+ union { /* Module Configuration Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:5;\r
+ vuint32_t SIZEEN:1;\r
+ vuint32_t SIZE:2;\r
+ vuint32_t:8;\r
+ vuint32_t ACGE:1;\r
+ vuint32_t EXTM:1;\r
+ vuint32_t EARB:1;\r
+ vuint32_t EARP:2;\r
+ vuint32_t:4;\r
+ vuint32_t MDIS:1;\r
+ vuint32_t:5;\r
+ vuint32_t DBM:1;\r
+ } B;\r
+ } MCR;\r
+\r
+ uint32_t EBI_reserved1;\r
+\r
+ union { /* Transfer Error Status Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:30;\r
+ vuint32_t TEAF:1;\r
+ vuint32_t BMTF:1;\r
+ } B;\r
+ } TESR;\r
+\r
+ union { /* Bus Monitor Control Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t BMT:8;\r
+ vuint32_t BME:1;\r
+ vuint32_t:7;\r
+ } B;\r
+ } BMCR;\r
+\r
+ struct CS_tag CS[4];\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : FLASH */\r
+/****************************************************************************/\r
+ struct FLASH_tag {\r
+ union { /* Module Configuration Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:4;\r
+ vuint32_t SIZE:4;\r
+ vuint32_t:1;\r
+ vuint32_t LAS:3;\r
+ vuint32_t:3;\r
+ vuint32_t MAS:1;\r
+ vuint32_t EER:1;\r
+ vuint32_t RWE:1;\r
+ vuint32_t BBEPE:1;\r
+ vuint32_t EPE:1;\r
+ vuint32_t PEAS:1;\r
+ vuint32_t DONE:1;\r
+ vuint32_t PEG:1;\r
+\r
+ vuint32_t:2;\r
+\r
+ vuint32_t STOP:1;\r
+ vuint32_t:1;\r
+ vuint32_t PGM:1;\r
+ vuint32_t PSUS:1;\r
+ vuint32_t ERS:1;\r
+ vuint32_t ESUS:1;\r
+ vuint32_t EHV:1;\r
+ } B;\r
+ } MCR;\r
+\r
+ union { /* LML Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t LME:1;\r
+ vuint32_t:10;\r
+ vuint32_t SLOCK:1;\r
+ vuint32_t MLOCK:4;\r
+ vuint32_t LLOCK:16;\r
+ } B;\r
+ } LMLR;\r
+\r
+ union { /* HL Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t HBE:1;\r
+ vuint32_t:3;\r
+ vuint32_t HBLOCK:28;\r
+ } B;\r
+ } HLR;\r
+\r
+ union { /* SLML Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t SLE:1;\r
+ vuint32_t:10;\r
+ vuint32_t SSLOCK:1;\r
+ vuint32_t SMLOCK:4;\r
+ vuint32_t SLLOCK:16;\r
+ } B;\r
+ } SLMLR;\r
+\r
+ union { /* LMS Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:12;\r
+ vuint32_t MSEL:4;\r
+ vuint32_t LSEL:16;\r
+ } B;\r
+ } LMSR;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:4;\r
+ vuint32_t HBSEL:28;\r
+ } B;\r
+ } HSR;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:10;\r
+ vuint32_t ADDR:19;\r
+ vuint32_t:3;\r
+ } B;\r
+ } AR;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+\r
+ vuint32_t:11;\r
+\r
+ vuint32_t:1;\r
+\r
+ vuint32_t M3PFE:1;\r
+ vuint32_t M2PFE:1;\r
+ vuint32_t M1PFE:1;\r
+ vuint32_t M0PFE:1;\r
+ vuint32_t APC:3;\r
+ vuint32_t WWSC:2;\r
+ vuint32_t RWSC:3;\r
+\r
+ vuint32_t DPFEN:2;\r
+ vuint32_t IPFEN:2;\r
+\r
+ vuint32_t PFLIM:3;\r
+ vuint32_t BFEN:1;\r
+ } B;\r
+ } BIUCR;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+\r
+ vuint32_t:22;\r
+\r
+ vuint32_t:2;\r
+\r
+ vuint32_t M3AP:2;\r
+ vuint32_t M2AP:2;\r
+ vuint32_t M1AP:2;\r
+ vuint32_t M0AP:2;\r
+ } B;\r
+ } BIUAPR;\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : SIU */\r
+/****************************************************************************/\r
+ struct SIU_tag {\r
+ int32_t SIU_reserved0;\r
+\r
+ union { /* MCU ID Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PARTNUM:16;\r
+ vuint32_t MASKNUM:16;\r
+ } B;\r
+ } MIDR;\r
+ int32_t SIU_reserved00;\r
+\r
+ union { /* Reset Status Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PORS:1;\r
+ vuint32_t ERS:1;\r
+ vuint32_t LLRS:1;\r
+ vuint32_t LCRS:1;\r
+ vuint32_t WDRS:1;\r
+ vuint32_t CRS:1;\r
+ vuint32_t:8;\r
+ vuint32_t SSRS:1;\r
+ vuint32_t SERF:1;\r
+ vuint32_t WKPCFG:1;\r
+ vuint32_t:12;\r
+ vuint32_t BOOTCFG:2;\r
+ vuint32_t RGF:1;\r
+ } B;\r
+ } RSR;\r
+\r
+ union { /* System Reset Control Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t SSR:1;\r
+ vuint32_t SER:1;\r
+ vuint32_t:14;\r
+ vuint32_t CRE:1;\r
+ vuint32_t:15;\r
+ } B;\r
+ } SRCR;\r
+\r
+ union { /* External Interrupt Status Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t EIF15:1;\r
+ vuint32_t EIF14:1;\r
+ vuint32_t EIF13:1;\r
+ vuint32_t EIF12:1;\r
+ vuint32_t EIF11:1;\r
+ vuint32_t EIF10:1;\r
+ vuint32_t EIF9:1;\r
+ vuint32_t EIF8:1;\r
+ vuint32_t EIF7:1;\r
+ vuint32_t EIF6:1;\r
+ vuint32_t EIF5:1;\r
+ vuint32_t EIF4:1;\r
+ vuint32_t EIF3:1;\r
+ vuint32_t EIF2:1;\r
+ vuint32_t EIF1:1;\r
+ vuint32_t EIF0:1;\r
+ } B;\r
+ } EISR;\r
+\r
+ union { /* DMA/Interrupt Request Enable Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t EIRE15:1;\r
+ vuint32_t EIRE14:1;\r
+ vuint32_t EIRE13:1;\r
+ vuint32_t EIRE12:1;\r
+ vuint32_t EIRE11:1;\r
+ vuint32_t EIRE10:1;\r
+ vuint32_t EIRE9:1;\r
+ vuint32_t EIRE8:1;\r
+ vuint32_t EIRE7:1;\r
+ vuint32_t EIRE6:1;\r
+ vuint32_t EIRE5:1;\r
+ vuint32_t EIRE4:1;\r
+ vuint32_t EIRE3:1;\r
+ vuint32_t EIRE2:1;\r
+ vuint32_t EIRE1:1;\r
+ vuint32_t EIRE0:1;\r
+ } B;\r
+ } DIRER;\r
+\r
+ union { /* DMA/Interrupt Select Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:28;\r
+ vuint32_t DIRS3:1;\r
+ vuint32_t DIRS2:1;\r
+ vuint32_t DIRS1:1;\r
+ vuint32_t DIRS0:1;\r
+ } B;\r
+ } DIRSR;\r
+\r
+ union { /* Overrun Status Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t OVF15:1;\r
+ vuint32_t OVF14:1;\r
+ vuint32_t OVF13:1;\r
+ vuint32_t OVF12:1;\r
+ vuint32_t OVF11:1;\r
+ vuint32_t OVF10:1;\r
+ vuint32_t OVF9:1;\r
+ vuint32_t OVF8:1;\r
+ vuint32_t OVF7:1;\r
+ vuint32_t OVF6:1;\r
+ vuint32_t OVF5:1;\r
+ vuint32_t OVF4:1;\r
+ vuint32_t OVF3:1;\r
+ vuint32_t OVF2:1;\r
+ vuint32_t OVF1:1;\r
+ vuint32_t OVF0:1;\r
+ } B;\r
+ } OSR;\r
+\r
+ union { /* Overrun Request Enable Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t ORE15:1;\r
+ vuint32_t ORE14:1;\r
+ vuint32_t ORE13:1;\r
+ vuint32_t ORE12:1;\r
+ vuint32_t ORE11:1;\r
+ vuint32_t ORE10:1;\r
+ vuint32_t ORE9:1;\r
+ vuint32_t ORE8:1;\r
+ vuint32_t ORE7:1;\r
+ vuint32_t ORE6:1;\r
+ vuint32_t ORE5:1;\r
+ vuint32_t ORE4:1;\r
+ vuint32_t ORE3:1;\r
+ vuint32_t ORE2:1;\r
+ vuint32_t ORE1:1;\r
+ vuint32_t ORE0:1;\r
+ } B;\r
+ } ORER;\r
+\r
+ union { /* External IRQ Rising-Edge Event Enable Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t IREE15:1;\r
+ vuint32_t IREE14:1;\r
+ vuint32_t IREE13:1;\r
+ vuint32_t IREE12:1;\r
+ vuint32_t IREE11:1;\r
+ vuint32_t IREE10:1;\r
+ vuint32_t IREE9:1;\r
+ vuint32_t IREE8:1;\r
+ vuint32_t IREE7:1;\r
+ vuint32_t IREE6:1;\r
+ vuint32_t IREE5:1;\r
+ vuint32_t IREE4:1;\r
+ vuint32_t IREE3:1;\r
+ vuint32_t IREE2:1;\r
+ vuint32_t IREE1:1;\r
+ vuint32_t IREE0:1;\r
+ } B;\r
+ } IREER;\r
+\r
+ union { /* External IRQ Falling-Edge Event Enable Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t IFEE15:1;\r
+ vuint32_t IFEE14:1;\r
+ vuint32_t IFEE13:1;\r
+ vuint32_t IFEE12:1;\r
+ vuint32_t IFEE11:1;\r
+ vuint32_t IFEE10:1;\r
+ vuint32_t IFEE9:1;\r
+ vuint32_t IFEE8:1;\r
+ vuint32_t IFEE7:1;\r
+ vuint32_t IFEE6:1;\r
+ vuint32_t IFEE5:1;\r
+ vuint32_t IFEE4:1;\r
+ vuint32_t IFEE3:1;\r
+ vuint32_t IFEE2:1;\r
+ vuint32_t IFEE1:1;\r
+ vuint32_t IFEE0:1;\r
+ } B;\r
+ } IFEER;\r
+\r
+ union { /* External IRQ Digital Filter Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:28;\r
+ vuint32_t DFL:4;\r
+ } B;\r
+ } IDFR;\r
+\r
+ int32_t SIU_reserved1[3];\r
+\r
+ union { /* Pad Configuration Registers */\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:3;\r
+ vuint16_t PA:3;\r
+ vuint16_t OBE:1;\r
+ vuint16_t IBE:1;\r
+ vuint16_t DSC:2;\r
+ vuint16_t ODE:1;\r
+ vuint16_t HYS:1;\r
+ vuint16_t SRC:2;\r
+ vuint16_t WPE:1;\r
+ vuint16_t WPS:1;\r
+ } B;\r
+ } PCR[512];\r
+\r
+ int16_t SIU_reserved_0[224];\r
+\r
+ union { /* GPIO Pin Data Output Registers */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t:7;\r
+ vuint8_t PDO:1;\r
+ } B;\r
+ } GPDO[256];\r
+\r
+ int32_t SIU_reserved_3[64];\r
+\r
+ union { /* GPIO Pin Data Input Registers */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t:7;\r
+ vuint8_t PDI:1;\r
+ } B;\r
+ } GPDI[256];\r
+\r
+ union { /* IMUX Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TSEL5:2;\r
+ vuint32_t TSEL4:2;\r
+ vuint32_t TSEL3:2;\r
+ vuint32_t TSEL2:2;\r
+ vuint32_t TSEL1:2;\r
+ vuint32_t TSEL0:2;\r
+ vuint32_t:20;\r
+ } B;\r
+ } ETISR;\r
+\r
+ union { /* IMUX Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t ESEL15:2;\r
+ vuint32_t ESEL14:2;\r
+ vuint32_t ESEL13:2;\r
+ vuint32_t ESEL12:2;\r
+ vuint32_t ESEL11:2;\r
+ vuint32_t ESEL10:2;\r
+ vuint32_t ESEL9:2;\r
+ vuint32_t ESEL8:2;\r
+ vuint32_t ESEL7:2;\r
+ vuint32_t ESEL6:2;\r
+ vuint32_t ESEL5:2;\r
+ vuint32_t ESEL4:2;\r
+ vuint32_t ESEL3:2;\r
+ vuint32_t ESEL2:2;\r
+ vuint32_t ESEL1:2;\r
+ vuint32_t ESEL0:2;\r
+ } B;\r
+ } EIISR;\r
+\r
+ union { /* IMUX Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t SINSELA:2;\r
+ vuint32_t SSSELA:2;\r
+ vuint32_t SCKSELA:2;\r
+ vuint32_t TRIGSELA:2;\r
+ vuint32_t SINSELB:2;\r
+ vuint32_t SSSELB:2;\r
+ vuint32_t SCKSELB:2;\r
+ vuint32_t TRIGSELB:2;\r
+ vuint32_t SINSELC:2;\r
+ vuint32_t SSSELC:2;\r
+ vuint32_t SCKSELC:2;\r
+ vuint32_t TRIGSELC:2;\r
+ vuint32_t SINSELD:2;\r
+ vuint32_t SSSELD:2;\r
+ vuint32_t SCKSELD:2;\r
+ vuint32_t TRIGSELD:2;\r
+ } B;\r
+ } DISR;\r
+\r
+ int32_t SIU_reserved2[29];\r
+\r
+ union { /* Chip Configuration Register Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:14;\r
+ vuint32_t MATCH:1;\r
+ vuint32_t DISNEX:1;\r
+ vuint32_t:16;\r
+ } B;\r
+ } CCR;\r
+\r
+ union { /* External Clock Configuration Register Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:18;\r
+ vuint32_t ENGDIV:6;\r
+ vuint32_t:4;\r
+ vuint32_t EBTS:1;\r
+ vuint32_t:1;\r
+ vuint32_t EBDF:2;\r
+ } B;\r
+ } ECCR;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } CARH;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } CARL;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } CBRH;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } CBRL;\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : EMIOS */\r
+/****************************************************************************/\r
+ struct EMIOS_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:1;\r
+ vuint32_t MDIS:1;\r
+ vuint32_t FRZ:1;\r
+ vuint32_t GTBE:1;\r
+ vuint32_t ETB:1;\r
+ vuint32_t GPREN:1;\r
+ vuint32_t:6;\r
+ vuint32_t SRV:4;\r
+ vuint32_t GPRE:8;\r
+ vuint32_t:8;\r
+ } B;\r
+ } MCR; /* Module Configuration Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:8;\r
+ vuint32_t F23:1;\r
+ vuint32_t F22:1;\r
+ vuint32_t F21:1;\r
+ vuint32_t F20:1;\r
+ vuint32_t F19:1;\r
+ vuint32_t F18:1;\r
+ vuint32_t F17:1;\r
+ vuint32_t F16:1;\r
+ vuint32_t F15:1;\r
+ vuint32_t F14:1;\r
+ vuint32_t F13:1;\r
+ vuint32_t F12:1;\r
+ vuint32_t F11:1;\r
+ vuint32_t F10:1;\r
+ vuint32_t F9:1;\r
+ vuint32_t F8:1;\r
+ vuint32_t F7:1;\r
+ vuint32_t F6:1;\r
+ vuint32_t F5:1;\r
+ vuint32_t F4:1;\r
+ vuint32_t F3:1;\r
+ vuint32_t F2:1;\r
+ vuint32_t F1:1;\r
+ vuint32_t F0:1;\r
+ } B;\r
+ } GFR; /* Global FLAG Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:8;\r
+ vuint32_t OU23:1;\r
+ vuint32_t OU22:1;\r
+ vuint32_t OU21:1;\r
+ vuint32_t OU20:1;\r
+ vuint32_t OU19:1;\r
+ vuint32_t OU18:1;\r
+ vuint32_t OU17:1;\r
+ vuint32_t OU16:1;\r
+ vuint32_t OU15:1;\r
+ vuint32_t OU14:1;\r
+ vuint32_t OU13:1;\r
+ vuint32_t OU12:1;\r
+ vuint32_t OU11:1;\r
+ vuint32_t OU10:1;\r
+ vuint32_t OU9:1;\r
+ vuint32_t OU8:1;\r
+ vuint32_t OU7:1;\r
+ vuint32_t OU6:1;\r
+ vuint32_t OU5:1;\r
+ vuint32_t OU4:1;\r
+ vuint32_t OU3:1;\r
+ vuint32_t OU2:1;\r
+ vuint32_t OU1:1;\r
+ vuint32_t OU0:1;\r
+ } B;\r
+ } OUDR; /* Output Update Disable Register */\r
+\r
+ uint32_t emios_reserved[5];\r
+\r
+ struct {\r
+ union {\r
+ vuint32_t R; /* Channel A Data Register */\r
+ } CADR;\r
+\r
+ union {\r
+ vuint32_t R; /* Channel B Data Register */\r
+ } CBDR;\r
+\r
+ union {\r
+ vuint32_t R; /* Channel Counter Register */\r
+ } CCNTR;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t FREN:1;\r
+ vuint32_t ODIS:1;\r
+ vuint32_t ODISSL:2;\r
+ vuint32_t UCPRE:2;\r
+ vuint32_t UCPREN:1;\r
+ vuint32_t DMA:1;\r
+ vuint32_t:1;\r
+ vuint32_t IF:4;\r
+ vuint32_t FCK:1;\r
+ vuint32_t FEN:1;\r
+ vuint32_t:3;\r
+ vuint32_t FORCMA:1;\r
+ vuint32_t FORCMB:1;\r
+ vuint32_t:1;\r
+ vuint32_t BSL:2;\r
+ vuint32_t EDSEL:1;\r
+ vuint32_t EDPOL:1;\r
+ vuint32_t MODE:7;\r
+ } B;\r
+ } CCR; /* Channel Control Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t OVR:1;\r
+ vuint32_t:15;\r
+ vuint32_t OVFL:1;\r
+ vuint32_t:12;\r
+ vuint32_t UCIN:1;\r
+ vuint32_t UCOUT:1;\r
+ vuint32_t FLAG:1;\r
+ } B;\r
+ } CSR; /* Channel Status Register */\r
+ uint32_t emios_channel_reserved[3];\r
+\r
+ } CH[24];\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE :ETPU */\r
+/****************************************************************************/\r
+\r
+/***************************Configuration Registers**************************/\r
+\r
+ struct ETPU_tag {\r
+ union { /* MODULE CONFIGURATION REGISTER */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t GEC:1; /* Global Exception Clear */\r
+ vuint32_t:3;\r
+ vuint32_t MGE1:1; /* Microcode Global Exception-ETPU_A */\r
+\r
+ vuint32_t MGE2:1; /* Microcode Global Exception-ETPU_B */\r
+\r
+ vuint32_t ILF1:1; /* Illegal Instruction Flag-ETPU_A */\r
+\r
+ vuint32_t ILF2:1; /* Illegal Instruction Flag-ETPU_B */\r
+\r
+ vuint32_t:3;\r
+ vuint32_t SCMSIZE:5; /* Shared Code Memory size */\r
+ vuint32_t:5;\r
+ vuint32_t SCMMISF:1; /* SCM MISC Flag */\r
+ vuint32_t SCMMISEN:1; /* SCM MISC Enable */\r
+ vuint32_t:2;\r
+ vuint32_t VIS:1; /* SCM Visability */\r
+ vuint32_t:5;\r
+ vuint32_t GTBE:1; /* Global Time Base Enable */\r
+ } B;\r
+ } MCR;\r
+\r
+ union { /* COHERENT DUAL-PARAMETER CONTROL */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t STS:1; /* Start Status bit */\r
+ vuint32_t CTBASE:5; /* Channel Transfer Base */\r
+ vuint32_t PBASE:10; /* Parameter Buffer Base Address */\r
+ vuint32_t PWIDTH:1; /* Parameter Width */\r
+ vuint32_t PARAM0:7; /* Channel Parameter 0 */\r
+ vuint32_t WR:1;\r
+ vuint32_t PARAM1:7; /* Channel Parameter 1 */\r
+ } B;\r
+ } CDCR;\r
+\r
+ uint32_t etpu_reserved1;\r
+\r
+ union { /* MISC Compare Register */\r
+ uint32_t R;\r
+ } MISCCMPR;\r
+\r
+ union { /* SCM off-range Date Register */\r
+ uint32_t R;\r
+ } SCMOFFDATAR;\r
+\r
+ union { /* ETPU_A Configuration Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t FEND:1; /* Force END */\r
+ vuint32_t MDIS:1; /* Low power Stop */\r
+ vuint32_t:1;\r
+ vuint32_t STF:1; /* Stop Flag */\r
+ vuint32_t:4;\r
+ vuint32_t HLTF:1; /* Halt Mode Flag */\r
+ vuint32_t:4;\r
+ vuint32_t FPSCK:3; /* Filter Prescaler Clock Control */\r
+ vuint32_t CDFC:2;\r
+ vuint32_t:9;\r
+ vuint32_t ETB:5; /* Entry Table Base */\r
+ } B;\r
+ } ECR_A;\r
+\r
+ union { /* ETPU_B Configuration Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t FEND:1; /* Force END */\r
+ vuint32_t MDIS:1; /* Low power Stop */\r
+ vuint32_t:1;\r
+ vuint32_t STF:1; /* Stop Flag */\r
+ vuint32_t:4;\r
+ vuint32_t HLTF:1; /* Halt Mode Flag */\r
+ vuint32_t:4;\r
+ vuint32_t FPSCK:3; /* Filter Prescaler Clock Control */\r
+ vuint32_t CDFC:2;\r
+ vuint32_t:9;\r
+ vuint32_t ETB:5; /* Entry Table Base */\r
+ } B;\r
+ } ECR_B;\r
+\r
+ uint32_t etpu_reserved4;\r
+\r
+ union { /* ETPU_A Timebase Configuration Register */\r
+ uint32_t R;\r
+ struct {\r
+ uint32_t TCR2CTL:3; /* TCR2 Clock/Gate Control */\r
+ uint32_t TCRCF:2; /* TCRCLK Signal Filter Control */\r
+ uint32_t:1;\r
+ uint32_t AM:1; /* Angle Mode */\r
+ uint32_t:3;\r
+ uint32_t TCR2P:6; /* TCR2 Prescaler Control */\r
+ uint32_t TCR1CTL:2; /* TCR1 Clock/Gate Control */\r
+ uint32_t:6;\r
+ uint32_t TCR1P:8; /* TCR1 Prescaler Control */\r
+ } B;\r
+ } TBCR_A;\r
+\r
+ union { /* ETPU_A TCR1 Visibility Register */\r
+ vuint32_t R;\r
+ } TB1R_A;\r
+\r
+ union { /* ETPU_A TCR2 Visibility Register */\r
+ vuint32_t R;\r
+ } TB2R_A;\r
+\r
+ union { /* ETPU_A STAC Configuration Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t REN1:1; /* Resource Enable TCR1 */\r
+ vuint32_t RSC1:1; /* Resource Control TCR1 */\r
+ vuint32_t:2;\r
+ vuint32_t SERVER_ID1:4;\r
+ vuint32_t:4;\r
+ vuint32_t SRV1:4; /* Resource Server Slot */\r
+ vuint32_t REN2:1; /* Resource Enable TCR2 */\r
+ vuint32_t RSC2:1; /* Resource Control TCR2 */\r
+ vuint32_t:2;\r
+ vuint32_t SERVER_ID2:4;\r
+ vuint32_t:4;\r
+ vuint32_t SRV2:4; /* Resource Server Slot */\r
+ } B;\r
+ } REDCR_A;\r
+\r
+ uint32_t etpu_reserved5[4];\r
+\r
+ union { /* ETPU_B Timebase Configuration Register */\r
+ uint32_t R;\r
+ struct {\r
+ uint32_t TCR2CTL:3; /* TCR2 Clock/Gate Control */\r
+ uint32_t TCRCF:2; /* TCRCLK Signal Filter Control */\r
+ uint32_t:1;\r
+ uint32_t AM:1; /* Angle Mode */\r
+ uint32_t:3;\r
+ uint32_t TCR2P:6; /* TCR2 Prescaler Control */\r
+ uint32_t TCR1CTL:2; /* TCR1 Clock/Gate Control */\r
+ uint32_t:6;\r
+ uint32_t TCR1P:8; /* TCR1 Prescaler Control */\r
+ } B;\r
+ } TBCR_B;\r
+\r
+ union { /* ETPU_B TCR1 Visibility Register */\r
+ vuint32_t R;\r
+ } TB1R_B;\r
+\r
+ union { /* ETPU_B TCR2 Visibility Register */\r
+ vuint32_t R;\r
+ } TB2R_B;\r
+\r
+ union { /* ETPU_B STAC Configuration Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t REN1:1; /* Resource Enable TCR1 */\r
+ vuint32_t RSC1:1; /* Resource Control TCR1 */\r
+ vuint32_t:2;\r
+ vuint32_t SERVER_ID1:4;\r
+ vuint32_t:4;\r
+ vuint32_t SRV1:4; /* Resource Server Slot */\r
+ vuint32_t REN2:1; /* Resource Enable TCR2 */\r
+ vuint32_t RSC2:1; /* Resource Control TCR2 */\r
+ vuint32_t:2;\r
+ vuint32_t SERVER_ID2:4;\r
+ vuint32_t:4;\r
+ vuint32_t SRV2:4; /* Resource Server Slot */\r
+ } B;\r
+ } REDCR_B;\r
+\r
+ uint32_t etpu_reserved7[108];\r
+\r
+/*****************************Status and Control Registers**************************/\r
+\r
+ union { /* ETPU_A Channel Interrut Status */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CIS31:1; /* Channel 31 Interrut Status */\r
+ vuint32_t CIS30:1; /* Channel 30 Interrut Status */\r
+ vuint32_t CIS29:1; /* Channel 29 Interrut Status */\r
+ vuint32_t CIS28:1; /* Channel 28 Interrut Status */\r
+ vuint32_t CIS27:1; /* Channel 27 Interrut Status */\r
+ vuint32_t CIS26:1; /* Channel 26 Interrut Status */\r
+ vuint32_t CIS25:1; /* Channel 25 Interrut Status */\r
+ vuint32_t CIS24:1; /* Channel 24 Interrut Status */\r
+ vuint32_t CIS23:1; /* Channel 23 Interrut Status */\r
+ vuint32_t CIS22:1; /* Channel 22 Interrut Status */\r
+ vuint32_t CIS21:1; /* Channel 21 Interrut Status */\r
+ vuint32_t CIS20:1; /* Channel 20 Interrut Status */\r
+ vuint32_t CIS19:1; /* Channel 19 Interrut Status */\r
+ vuint32_t CIS18:1; /* Channel 18 Interrut Status */\r
+ vuint32_t CIS17:1; /* Channel 17 Interrut Status */\r
+ vuint32_t CIS16:1; /* Channel 16 Interrut Status */\r
+ vuint32_t CIS15:1; /* Channel 15 Interrut Status */\r
+ vuint32_t CIS14:1; /* Channel 14 Interrut Status */\r
+ vuint32_t CIS13:1; /* Channel 13 Interrut Status */\r
+ vuint32_t CIS12:1; /* Channel 12 Interrut Status */\r
+ vuint32_t CIS11:1; /* Channel 11 Interrut Status */\r
+ vuint32_t CIS10:1; /* Channel 10 Interrut Status */\r
+ vuint32_t CIS9:1; /* Channel 9 Interrut Status */\r
+ vuint32_t CIS8:1; /* Channel 8 Interrut Status */\r
+ vuint32_t CIS7:1; /* Channel 7 Interrut Status */\r
+ vuint32_t CIS6:1; /* Channel 6 Interrut Status */\r
+ vuint32_t CIS5:1; /* Channel 5 Interrut Status */\r
+ vuint32_t CIS4:1; /* Channel 4 Interrut Status */\r
+ vuint32_t CIS3:1; /* Channel 3 Interrut Status */\r
+ vuint32_t CIS2:1; /* Channel 2 Interrut Status */\r
+ vuint32_t CIS1:1; /* Channel 1 Interrut Status */\r
+ vuint32_t CIS0:1; /* Channel 0 Interrut Status */\r
+ } B;\r
+ } CISR_A;\r
+\r
+ union { /* ETPU_B Channel Interruput Status */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CIS31:1; /* Channel 31 Interrut Status */\r
+ vuint32_t CIS30:1; /* Channel 30 Interrut Status */\r
+ vuint32_t CIS29:1; /* Channel 29 Interrut Status */\r
+ vuint32_t CIS28:1; /* Channel 28 Interrut Status */\r
+ vuint32_t CIS27:1; /* Channel 27 Interrut Status */\r
+ vuint32_t CIS26:1; /* Channel 26 Interrut Status */\r
+ vuint32_t CIS25:1; /* Channel 25 Interrut Status */\r
+ vuint32_t CIS24:1; /* Channel 24 Interrut Status */\r
+ vuint32_t CIS23:1; /* Channel 23 Interrut Status */\r
+ vuint32_t CIS22:1; /* Channel 22 Interrut Status */\r
+ vuint32_t CIS21:1; /* Channel 21 Interrut Status */\r
+ vuint32_t CIS20:1; /* Channel 20 Interrut Status */\r
+ vuint32_t CIS19:1; /* Channel 19 Interrut Status */\r
+ vuint32_t CIS18:1; /* Channel 18 Interrut Status */\r
+ vuint32_t CIS17:1; /* Channel 17 Interrut Status */\r
+ vuint32_t CIS16:1; /* Channel 16 Interrut Status */\r
+ vuint32_t CIS15:1; /* Channel 15 Interrut Status */\r
+ vuint32_t CIS14:1; /* Channel 14 Interrut Status */\r
+ vuint32_t CIS13:1; /* Channel 13 Interrut Status */\r
+ vuint32_t CIS12:1; /* Channel 12 Interrut Status */\r
+ vuint32_t CIS11:1; /* Channel 11 Interrut Status */\r
+ vuint32_t CIS10:1; /* Channel 10 Interrut Status */\r
+ vuint32_t CIS9:1; /* Channel 9 Interrut Status */\r
+ vuint32_t CIS8:1; /* Channel 8 Interrut Status */\r
+ vuint32_t CIS7:1; /* Channel 7 Interrut Status */\r
+ vuint32_t CIS6:1; /* Channel 6 Interrut Status */\r
+ vuint32_t CIS5:1; /* Channel 5 Interrut Status */\r
+ vuint32_t CIS4:1; /* Channel 4 Interrut Status */\r
+ vuint32_t CIS3:1; /* Channel 3 Interrut Status */\r
+ vuint32_t CIS2:1; /* Channel 2 Interrut Status */\r
+ vuint32_t CIS1:1; /* Channel 1 Interrupt Status */\r
+ vuint32_t CIS0:1; /* Channel 0 Interrupt Status */\r
+ } B;\r
+ } CISR_B;\r
+\r
+ uint32_t etpu_reserved9[2];\r
+\r
+ union { /* ETPU_A Data Transfer Request Status */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DTRS31:1; /* Channel 31 Data Transfer Request Status */\r
+ vuint32_t DTRS30:1; /* Channel 30 Data Transfer Request Status */\r
+ vuint32_t DTRS29:1; /* Channel 29 Data Transfer Request Status */\r
+ vuint32_t DTRS28:1; /* Channel 28 Data Transfer Request Status */\r
+ vuint32_t DTRS27:1; /* Channel 27 Data Transfer Request Status */\r
+ vuint32_t DTRS26:1; /* Channel 26 Data Transfer Request Status */\r
+ vuint32_t DTRS25:1; /* Channel 25 Data Transfer Request Status */\r
+ vuint32_t DTRS24:1; /* Channel 24 Data Transfer Request Status */\r
+ vuint32_t DTRS23:1; /* Channel 23 Data Transfer Request Status */\r
+ vuint32_t DTRS22:1; /* Channel 22 Data Transfer Request Status */\r
+ vuint32_t DTRS21:1; /* Channel 21 Data Transfer Request Status */\r
+ vuint32_t DTRS20:1; /* Channel 20 Data Transfer Request Status */\r
+ vuint32_t DTRS19:1; /* Channel 19 Data Transfer Request Status */\r
+ vuint32_t DTRS18:1; /* Channel 18 Data Transfer Request Status */\r
+ vuint32_t DTRS17:1; /* Channel 17 Data Transfer Request Status */\r
+ vuint32_t DTRS16:1; /* Channel 16 Data Transfer Request Status */\r
+ vuint32_t DTRS15:1; /* Channel 15 Data Transfer Request Status */\r
+ vuint32_t DTRS14:1; /* Channel 14 Data Transfer Request Status */\r
+ vuint32_t DTRS13:1; /* Channel 13 Data Transfer Request Status */\r
+ vuint32_t DTRS12:1; /* Channel 12 Data Transfer Request Status */\r
+ vuint32_t DTRS11:1; /* Channel 11 Data Transfer Request Status */\r
+ vuint32_t DTRS10:1; /* Channel 10 Data Transfer Request Status */\r
+ vuint32_t DTRS9:1; /* Channel 9 Data Transfer Request Status */\r
+ vuint32_t DTRS8:1; /* Channel 8 Data Transfer Request Status */\r
+ vuint32_t DTRS7:1; /* Channel 7 Data Transfer Request Status */\r
+ vuint32_t DTRS6:1; /* Channel 6 Data Transfer Request Status */\r
+ vuint32_t DTRS5:1; /* Channel 5 Data Transfer Request Status */\r
+ vuint32_t DTRS4:1; /* Channel 4 Data Transfer Request Status */\r
+ vuint32_t DTRS3:1; /* Channel 3 Data Transfer Request Status */\r
+ vuint32_t DTRS2:1; /* Channel 2 Data Transfer Request Status */\r
+ vuint32_t DTRS1:1; /* Channel 1 Data Transfer Request Status */\r
+ vuint32_t DTRS0:1; /* Channel 0 Data Transfer Request Status */\r
+ } B;\r
+ } CDTRSR_A;\r
+\r
+ union { /* ETPU_B Data Transfer Request Status */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DTRS31:1; /* Channel 31 Data Transfer Request Status */\r
+ vuint32_t DTRS30:1; /* Channel 30 Data Transfer Request Status */\r
+ vuint32_t DTRS29:1; /* Channel 29 Data Transfer Request Status */\r
+ vuint32_t DTRS28:1; /* Channel 28 Data Transfer Request Status */\r
+ vuint32_t DTRS27:1; /* Channel 27 Data Transfer Request Status */\r
+ vuint32_t DTRS26:1; /* Channel 26 Data Transfer Request Status */\r
+ vuint32_t DTRS25:1; /* Channel 25 Data Transfer Request Status */\r
+ vuint32_t DTRS24:1; /* Channel 24 Data Transfer Request Status */\r
+ vuint32_t DTRS23:1; /* Channel 23 Data Transfer Request Status */\r
+ vuint32_t DTRS22:1; /* Channel 22 Data Transfer Request Status */\r
+ vuint32_t DTRS21:1; /* Channel 21 Data Transfer Request Status */\r
+ vuint32_t DTRS20:1; /* Channel 20 Data Transfer Request Status */\r
+ vuint32_t DTRS19:1; /* Channel 19 Data Transfer Request Status */\r
+ vuint32_t DTRS18:1; /* Channel 18 Data Transfer Request Status */\r
+ vuint32_t DTRS17:1; /* Channel 17 Data Transfer Request Status */\r
+ vuint32_t DTRS16:1; /* Channel 16 Data Transfer Request Status */\r
+ vuint32_t DTRS15:1; /* Channel 15 Data Transfer Request Status */\r
+ vuint32_t DTRS14:1; /* Channel 14 Data Transfer Request Status */\r
+ vuint32_t DTRS13:1; /* Channel 13 Data Transfer Request Status */\r
+ vuint32_t DTRS12:1; /* Channel 12 Data Transfer Request Status */\r
+ vuint32_t DTRS11:1; /* Channel 11 Data Transfer Request Status */\r
+ vuint32_t DTRS10:1; /* Channel 10 Data Transfer Request Status */\r
+ vuint32_t DTRS9:1; /* Channel 9 Data Transfer Request Status */\r
+ vuint32_t DTRS8:1; /* Channel 8 Data Transfer Request Status */\r
+ vuint32_t DTRS7:1; /* Channel 7 Data Transfer Request Status */\r
+ vuint32_t DTRS6:1; /* Channel 6 Data Transfer Request Status */\r
+ vuint32_t DTRS5:1; /* Channel 5 Data Transfer Request Status */\r
+ vuint32_t DTRS4:1; /* Channel 4 Data Transfer Request Status */\r
+ vuint32_t DTRS3:1; /* Channel 3 Data Transfer Request Status */\r
+ vuint32_t DTRS2:1; /* Channel 2 Data Transfer Request Status */\r
+ vuint32_t DTRS1:1; /* Channel 1 Data Transfer Request Status */\r
+ vuint32_t DTRS0:1; /* Channel 0 Data Transfer Request Status */\r
+ } B;\r
+ } CDTRSR_B;\r
+\r
+ uint32_t etpu_reserved11[2];\r
+\r
+ union { /* ETPU_A Interruput Overflow Status */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CIOS31:1; /* Channel 31 Interruput Overflow Status */\r
+ vuint32_t CIOS30:1; /* Channel 30 Interruput Overflow Status */\r
+ vuint32_t CIOS29:1; /* Channel 29 Interruput Overflow Status */\r
+ vuint32_t CIOS28:1; /* Channel 28 Interruput Overflow Status */\r
+ vuint32_t CIOS27:1; /* Channel 27 Interruput Overflow Status */\r
+ vuint32_t CIOS26:1; /* Channel 26 Interruput Overflow Status */\r
+ vuint32_t CIOS25:1; /* Channel 25 Interruput Overflow Status */\r
+ vuint32_t CIOS24:1; /* Channel 24 Interruput Overflow Status */\r
+ vuint32_t CIOS23:1; /* Channel 23 Interruput Overflow Status */\r
+ vuint32_t CIOS22:1; /* Channel 22 Interruput Overflow Status */\r
+ vuint32_t CIOS21:1; /* Channel 21 Interruput Overflow Status */\r
+ vuint32_t CIOS20:1; /* Channel 20 Interruput Overflow Status */\r
+ vuint32_t CIOS19:1; /* Channel 19 Interruput Overflow Status */\r
+ vuint32_t CIOS18:1; /* Channel 18 Interruput Overflow Status */\r
+ vuint32_t CIOS17:1; /* Channel 17 Interruput Overflow Status */\r
+ vuint32_t CIOS16:1; /* Channel 16 Interruput Overflow Status */\r
+ vuint32_t CIOS15:1; /* Channel 15 Interruput Overflow Status */\r
+ vuint32_t CIOS14:1; /* Channel 14 Interruput Overflow Status */\r
+ vuint32_t CIOS13:1; /* Channel 13 Interruput Overflow Status */\r
+ vuint32_t CIOS12:1; /* Channel 12 Interruput Overflow Status */\r
+ vuint32_t CIOS11:1; /* Channel 11 Interruput Overflow Status */\r
+ vuint32_t CIOS10:1; /* Channel 10 Interruput Overflow Status */\r
+ vuint32_t CIOS9:1; /* Channel 9 Interruput Overflow Status */\r
+ vuint32_t CIOS8:1; /* Channel 8 Interruput Overflow Status */\r
+ vuint32_t CIOS7:1; /* Channel 7 Interruput Overflow Status */\r
+ vuint32_t CIOS6:1; /* Channel 6 Interruput Overflow Status */\r
+ vuint32_t CIOS5:1; /* Channel 5 Interruput Overflow Status */\r
+ vuint32_t CIOS4:1; /* Channel 4 Interruput Overflow Status */\r
+ vuint32_t CIOS3:1; /* Channel 3 Interruput Overflow Status */\r
+ vuint32_t CIOS2:1; /* Channel 2 Interruput Overflow Status */\r
+ vuint32_t CIOS1:1; /* Channel 1 Interruput Overflow Status */\r
+ vuint32_t CIOS0:1; /* Channel 0 Interruput Overflow Status */\r
+ } B;\r
+ } CIOSR_A;\r
+\r
+ union { /* ETPU_B Interruput Overflow Status */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CIOS31:1; /* Channel 31 Interruput Overflow Status */\r
+ vuint32_t CIOS30:1; /* Channel 30 Interruput Overflow Status */\r
+ vuint32_t CIOS29:1; /* Channel 29 Interruput Overflow Status */\r
+ vuint32_t CIOS28:1; /* Channel 28 Interruput Overflow Status */\r
+ vuint32_t CIOS27:1; /* Channel 27 Interruput Overflow Status */\r
+ vuint32_t CIOS26:1; /* Channel 26 Interruput Overflow Status */\r
+ vuint32_t CIOS25:1; /* Channel 25 Interruput Overflow Status */\r
+ vuint32_t CIOS24:1; /* Channel 24 Interruput Overflow Status */\r
+ vuint32_t CIOS23:1; /* Channel 23 Interruput Overflow Status */\r
+ vuint32_t CIOS22:1; /* Channel 22 Interruput Overflow Status */\r
+ vuint32_t CIOS21:1; /* Channel 21 Interruput Overflow Status */\r
+ vuint32_t CIOS20:1; /* Channel 20 Interruput Overflow Status */\r
+ vuint32_t CIOS19:1; /* Channel 19 Interruput Overflow Status */\r
+ vuint32_t CIOS18:1; /* Channel 18 Interruput Overflow Status */\r
+ vuint32_t CIOS17:1; /* Channel 17 Interruput Overflow Status */\r
+ vuint32_t CIOS16:1; /* Channel 16 Interruput Overflow Status */\r
+ vuint32_t CIOS15:1; /* Channel 15 Interruput Overflow Status */\r
+ vuint32_t CIOS14:1; /* Channel 14 Interruput Overflow Status */\r
+ vuint32_t CIOS13:1; /* Channel 13 Interruput Overflow Status */\r
+ vuint32_t CIOS12:1; /* Channel 12 Interruput Overflow Status */\r
+ vuint32_t CIOS11:1; /* Channel 11 Interruput Overflow Status */\r
+ vuint32_t CIOS10:1; /* Channel 10 Interruput Overflow Status */\r
+ vuint32_t CIOS9:1; /* Channel 9 Interruput Overflow Status */\r
+ vuint32_t CIOS8:1; /* Channel 8 Interruput Overflow Status */\r
+ vuint32_t CIOS7:1; /* Channel 7 Interruput Overflow Status */\r
+ vuint32_t CIOS6:1; /* Channel 6 Interruput Overflow Status */\r
+ vuint32_t CIOS5:1; /* Channel 5 Interruput Overflow Status */\r
+ vuint32_t CIOS4:1; /* Channel 4 Interruput Overflow Status */\r
+ vuint32_t CIOS3:1; /* Channel 3 Interruput Overflow Status */\r
+ vuint32_t CIOS2:1; /* Channel 2 Interruput Overflow Status */\r
+ vuint32_t CIOS1:1; /* Channel 1 Interruput Overflow Status */\r
+ vuint32_t CIOS0:1; /* Channel 0 Interruput Overflow Status */\r
+ } B;\r
+ } CIOSR_B;\r
+\r
+ uint32_t etpu_reserved13[2];\r
+\r
+ union { /* ETPU_A Data Transfer Overflow Status */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DTROS31:1; /* Channel 31 Data Transfer Overflow Status */\r
+ vuint32_t DTROS30:1; /* Channel 30 Data Transfer Overflow Status */\r
+ vuint32_t DTROS29:1; /* Channel 29 Data Transfer Overflow Status */\r
+ vuint32_t DTROS28:1; /* Channel 28 Data Transfer Overflow Status */\r
+ vuint32_t DTROS27:1; /* Channel 27 Data Transfer Overflow Status */\r
+ vuint32_t DTROS26:1; /* Channel 26 Data Transfer Overflow Status */\r
+ vuint32_t DTROS25:1; /* Channel 25 Data Transfer Overflow Status */\r
+ vuint32_t DTROS24:1; /* Channel 24 Data Transfer Overflow Status */\r
+ vuint32_t DTROS23:1; /* Channel 23 Data Transfer Overflow Status */\r
+ vuint32_t DTROS22:1; /* Channel 22 Data Transfer Overflow Status */\r
+ vuint32_t DTROS21:1; /* Channel 21 Data Transfer Overflow Status */\r
+ vuint32_t DTROS20:1; /* Channel 20 Data Transfer Overflow Status */\r
+ vuint32_t DTROS19:1; /* Channel 19 Data Transfer Overflow Status */\r
+ vuint32_t DTROS18:1; /* Channel 18 Data Transfer Overflow Status */\r
+ vuint32_t DTROS17:1; /* Channel 17 Data Transfer Overflow Status */\r
+ vuint32_t DTROS16:1; /* Channel 16 Data Transfer Overflow Status */\r
+ vuint32_t DTROS15:1; /* Channel 15 Data Transfer Overflow Status */\r
+ vuint32_t DTROS14:1; /* Channel 14 Data Transfer Overflow Status */\r
+ vuint32_t DTROS13:1; /* Channel 13 Data Transfer Overflow Status */\r
+ vuint32_t DTROS12:1; /* Channel 12 Data Transfer Overflow Status */\r
+ vuint32_t DTROS11:1; /* Channel 11 Data Transfer Overflow Status */\r
+ vuint32_t DTROS10:1; /* Channel 10 Data Transfer Overflow Status */\r
+ vuint32_t DTROS9:1; /* Channel 9 Data Transfer Overflow Status */\r
+ vuint32_t DTROS8:1; /* Channel 8 Data Transfer Overflow Status */\r
+ vuint32_t DTROS7:1; /* Channel 7 Data Transfer Overflow Status */\r
+ vuint32_t DTROS6:1; /* Channel 6 Data Transfer Overflow Status */\r
+ vuint32_t DTROS5:1; /* Channel 5 Data Transfer Overflow Status */\r
+ vuint32_t DTROS4:1; /* Channel 4 Data Transfer Overflow Status */\r
+ vuint32_t DTROS3:1; /* Channel 3 Data Transfer Overflow Status */\r
+ vuint32_t DTROS2:1; /* Channel 2 Data Transfer Overflow Status */\r
+ vuint32_t DTROS1:1; /* Channel 1 Data Transfer Overflow Status */\r
+ vuint32_t DTROS0:1; /* Channel 0 Data Transfer Overflow Status */\r
+ } B;\r
+ } CDTROSR_A;\r
+\r
+ union { /* ETPU_B Data Transfer Overflow Status */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DTROS31:1; /* Channel 31 Data Transfer Overflow Status */\r
+ vuint32_t DTROS30:1; /* Channel 30 Data Transfer Overflow Status */\r
+ vuint32_t DTROS29:1; /* Channel 29 Data Transfer Overflow Status */\r
+ vuint32_t DTROS28:1; /* Channel 28 Data Transfer Overflow Status */\r
+ vuint32_t DTROS27:1; /* Channel 27 Data Transfer Overflow Status */\r
+ vuint32_t DTROS26:1; /* Channel 26 Data Transfer Overflow Status */\r
+ vuint32_t DTROS25:1; /* Channel 25 Data Transfer Overflow Status */\r
+ vuint32_t DTROS24:1; /* Channel 24 Data Transfer Overflow Status */\r
+ vuint32_t DTROS23:1; /* Channel 23 Data Transfer Overflow Status */\r
+ vuint32_t DTROS22:1; /* Channel 22 Data Transfer Overflow Status */\r
+ vuint32_t DTROS21:1; /* Channel 21 Data Transfer Overflow Status */\r
+ vuint32_t DTROS20:1; /* Channel 20 Data Transfer Overflow Status */\r
+ vuint32_t DTROS19:1; /* Channel 19 Data Transfer Overflow Status */\r
+ vuint32_t DTROS18:1; /* Channel 18 Data Transfer Overflow Status */\r
+ vuint32_t DTROS17:1; /* Channel 17 Data Transfer Overflow Status */\r
+ vuint32_t DTROS16:1; /* Channel 16 Data Transfer Overflow Status */\r
+ vuint32_t DTROS15:1; /* Channel 15 Data Transfer Overflow Status */\r
+ vuint32_t DTROS14:1; /* Channel 14 Data Transfer Overflow Status */\r
+ vuint32_t DTROS13:1; /* Channel 13 Data Transfer Overflow Status */\r
+ vuint32_t DTROS12:1; /* Channel 12 Data Transfer Overflow Status */\r
+ vuint32_t DTROS11:1; /* Channel 11 Data Transfer Overflow Status */\r
+ vuint32_t DTROS10:1; /* Channel 10 Data Transfer Overflow Status */\r
+ vuint32_t DTROS9:1; /* Channel 9 Data Transfer Overflow Status */\r
+ vuint32_t DTROS8:1; /* Channel 8 Data Transfer Overflow Status */\r
+ vuint32_t DTROS7:1; /* Channel 7 Data Transfer Overflow Status */\r
+ vuint32_t DTROS6:1; /* Channel 6 Data Transfer Overflow Status */\r
+ vuint32_t DTROS5:1; /* Channel 5 Data Transfer Overflow Status */\r
+ vuint32_t DTROS4:1; /* Channel 4 Data Transfer Overflow Status */\r
+ vuint32_t DTROS3:1; /* Channel 3 Data Transfer Overflow Status */\r
+ vuint32_t DTROS2:1; /* Channel 2 Data Transfer Overflow Status */\r
+ vuint32_t DTROS1:1; /* Channel 1 Data Transfer Overflow Status */\r
+ vuint32_t DTROS0:1; /* Channel 0 Data Transfer Overflow Status */\r
+ } B;\r
+ } CDTROSR_B;\r
+\r
+ uint32_t etpu_reserved15[2];\r
+\r
+ union { /* ETPU_A Channel Interruput Enable */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CIE31:1; /* Channel 31 Interruput Enable */\r
+ vuint32_t CIE30:1; /* Channel 30 Interruput Enable */\r
+ vuint32_t CIE29:1; /* Channel 29 Interruput Enable */\r
+ vuint32_t CIE28:1; /* Channel 28 Interruput Enable */\r
+ vuint32_t CIE27:1; /* Channel 27 Interruput Enable */\r
+ vuint32_t CIE26:1; /* Channel 26 Interruput Enable */\r
+ vuint32_t CIE25:1; /* Channel 25 Interruput Enable */\r
+ vuint32_t CIE24:1; /* Channel 24 Interruput Enable */\r
+ vuint32_t CIE23:1; /* Channel 23 Interruput Enable */\r
+ vuint32_t CIE22:1; /* Channel 22 Interruput Enable */\r
+ vuint32_t CIE21:1; /* Channel 21 Interruput Enable */\r
+ vuint32_t CIE20:1; /* Channel 20 Interruput Enable */\r
+ vuint32_t CIE19:1; /* Channel 19 Interruput Enable */\r
+ vuint32_t CIE18:1; /* Channel 18 Interruput Enable */\r
+ vuint32_t CIE17:1; /* Channel 17 Interruput Enable */\r
+ vuint32_t CIE16:1; /* Channel 16 Interruput Enable */\r
+ vuint32_t CIE15:1; /* Channel 15 Interruput Enable */\r
+ vuint32_t CIE14:1; /* Channel 14 Interruput Enable */\r
+ vuint32_t CIE13:1; /* Channel 13 Interruput Enable */\r
+ vuint32_t CIE12:1; /* Channel 12 Interruput Enable */\r
+ vuint32_t CIE11:1; /* Channel 11 Interruput Enable */\r
+ vuint32_t CIE10:1; /* Channel 10 Interruput Enable */\r
+ vuint32_t CIE9:1; /* Channel 9 Interruput Enable */\r
+ vuint32_t CIE8:1; /* Channel 8 Interruput Enable */\r
+ vuint32_t CIE7:1; /* Channel 7 Interruput Enable */\r
+ vuint32_t CIE6:1; /* Channel 6 Interruput Enable */\r
+ vuint32_t CIE5:1; /* Channel 5 Interruput Enable */\r
+ vuint32_t CIE4:1; /* Channel 4 Interruput Enable */\r
+ vuint32_t CIE3:1; /* Channel 3 Interruput Enable */\r
+ vuint32_t CIE2:1; /* Channel 2 Interruput Enable */\r
+ vuint32_t CIE1:1; /* Channel 1 Interruput Enable */\r
+ vuint32_t CIE0:1; /* Channel 0 Interruput Enable */\r
+ } B;\r
+ } CIER_A;\r
+\r
+ union { /* ETPU_B Channel Interruput Enable */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CIE31:1; /* Channel 31 Interruput Enable */\r
+ vuint32_t CIE30:1; /* Channel 30 Interruput Enable */\r
+ vuint32_t CIE29:1; /* Channel 29 Interruput Enable */\r
+ vuint32_t CIE28:1; /* Channel 28 Interruput Enable */\r
+ vuint32_t CIE27:1; /* Channel 27 Interruput Enable */\r
+ vuint32_t CIE26:1; /* Channel 26 Interruput Enable */\r
+ vuint32_t CIE25:1; /* Channel 25 Interruput Enable */\r
+ vuint32_t CIE24:1; /* Channel 24 Interruput Enable */\r
+ vuint32_t CIE23:1; /* Channel 23 Interruput Enable */\r
+ vuint32_t CIE22:1; /* Channel 22 Interruput Enable */\r
+ vuint32_t CIE21:1; /* Channel 21 Interruput Enable */\r
+ vuint32_t CIE20:1; /* Channel 20 Interruput Enable */\r
+ vuint32_t CIE19:1; /* Channel 19 Interruput Enable */\r
+ vuint32_t CIE18:1; /* Channel 18 Interruput Enable */\r
+ vuint32_t CIE17:1; /* Channel 17 Interruput Enable */\r
+ vuint32_t CIE16:1; /* Channel 16 Interruput Enable */\r
+ vuint32_t CIE15:1; /* Channel 15 Interruput Enable */\r
+ vuint32_t CIE14:1; /* Channel 14 Interruput Enable */\r
+ vuint32_t CIE13:1; /* Channel 13 Interruput Enable */\r
+ vuint32_t CIE12:1; /* Channel 12 Interruput Enable */\r
+ vuint32_t CIE11:1; /* Channel 11 Interruput Enable */\r
+ vuint32_t CIE10:1; /* Channel 10 Interruput Enable */\r
+ vuint32_t CIE9:1; /* Channel 9 Interruput Enable */\r
+ vuint32_t CIE8:1; /* Channel 8 Interruput Enable */\r
+ vuint32_t CIE7:1; /* Channel 7 Interruput Enable */\r
+ vuint32_t CIE6:1; /* Channel 6 Interruput Enable */\r
+ vuint32_t CIE5:1; /* Channel 5 Interruput Enable */\r
+ vuint32_t CIE4:1; /* Channel 4 Interruput Enable */\r
+ vuint32_t CIE3:1; /* Channel 3 Interruput Enable */\r
+ vuint32_t CIE2:1; /* Channel 2 Interruput Enable */\r
+ vuint32_t CIE1:1; /* Channel 1 Interruput Enable */\r
+ vuint32_t CIE0:1; /* Channel 0 Interruput Enable */\r
+ } B;\r
+ } CIER_B;\r
+\r
+ uint32_t etpu_reserved17[2];\r
+\r
+ union { /* ETPU_A Channel Data Transfer Request Enable */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DTRE31:1; /* Channel 31 Data Transfer Request Enable */\r
+ vuint32_t DTRE30:1; /* Channel 30 Data Transfer Request Enable */\r
+ vuint32_t DTRE29:1; /* Channel 29 Data Transfer Request Enable */\r
+ vuint32_t DTRE28:1; /* Channel 28 Data Transfer Request Enable */\r
+ vuint32_t DTRE27:1; /* Channel 27 Data Transfer Request Enable */\r
+ vuint32_t DTRE26:1; /* Channel 26 Data Transfer Request Enable */\r
+ vuint32_t DTRE25:1; /* Channel 25 Data Transfer Request Enable */\r
+ vuint32_t DTRE24:1; /* Channel 24 Data Transfer Request Enable */\r
+ vuint32_t DTRE23:1; /* Channel 23 Data Transfer Request Enable */\r
+ vuint32_t DTRE22:1; /* Channel 22 Data Transfer Request Enable */\r
+ vuint32_t DTRE21:1; /* Channel 21 Data Transfer Request Enable */\r
+ vuint32_t DTRE20:1; /* Channel 20 Data Transfer Request Enable */\r
+ vuint32_t DTRE19:1; /* Channel 19 Data Transfer Request Enable */\r
+ vuint32_t DTRE18:1; /* Channel 18 Data Transfer Request Enable */\r
+ vuint32_t DTRE17:1; /* Channel 17 Data Transfer Request Enable */\r
+ vuint32_t DTRE16:1; /* Channel 16 Data Transfer Request Enable */\r
+ vuint32_t DTRE15:1; /* Channel 15 Data Transfer Request Enable */\r
+ vuint32_t DTRE14:1; /* Channel 14 Data Transfer Request Enable */\r
+ vuint32_t DTRE13:1; /* Channel 13 Data Transfer Request Enable */\r
+ vuint32_t DTRE12:1; /* Channel 12 Data Transfer Request Enable */\r
+ vuint32_t DTRE11:1; /* Channel 11 Data Transfer Request Enable */\r
+ vuint32_t DTRE10:1; /* Channel 10 Data Transfer Request Enable */\r
+ vuint32_t DTRE9:1; /* Channel 9 Data Transfer Request Enable */\r
+ vuint32_t DTRE8:1; /* Channel 8 Data Transfer Request Enable */\r
+ vuint32_t DTRE7:1; /* Channel 7 Data Transfer Request Enable */\r
+ vuint32_t DTRE6:1; /* Channel 6 Data Transfer Request Enable */\r
+ vuint32_t DTRE5:1; /* Channel 5 Data Transfer Request Enable */\r
+ vuint32_t DTRE4:1; /* Channel 4 Data Transfer Request Enable */\r
+ vuint32_t DTRE3:1; /* Channel 3 Data Transfer Request Enable */\r
+ vuint32_t DTRE2:1; /* Channel 2 Data Transfer Request Enable */\r
+ vuint32_t DTRE1:1; /* Channel 1 Data Transfer Request Enable */\r
+ vuint32_t DTRE0:1; /* Channel 0 Data Transfer Request Enable */\r
+ } B;\r
+ } CDTRER_A;\r
+\r
+ union { /* ETPU_B Channel Data Transfer Request Enable */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DTRE31:1; /* Channel 31 Data Transfer Request Enable */\r
+ vuint32_t DTRE30:1; /* Channel 30 Data Transfer Request Enable */\r
+ vuint32_t DTRE29:1; /* Channel 29 Data Transfer Request Enable */\r
+ vuint32_t DTRE28:1; /* Channel 28 Data Transfer Request Enable */\r
+ vuint32_t DTRE27:1; /* Channel 27 Data Transfer Request Enable */\r
+ vuint32_t DTRE26:1; /* Channel 26 Data Transfer Request Enable */\r
+ vuint32_t DTRE25:1; /* Channel 25 Data Transfer Request Enable */\r
+ vuint32_t DTRE24:1; /* Channel 24 Data Transfer Request Enable */\r
+ vuint32_t DTRE23:1; /* Channel 23 Data Transfer Request Enable */\r
+ vuint32_t DTRE22:1; /* Channel 22 Data Transfer Request Enable */\r
+ vuint32_t DTRE21:1; /* Channel 21 Data Transfer Request Enable */\r
+ vuint32_t DTRE20:1; /* Channel 20 Data Transfer Request Enable */\r
+ vuint32_t DTRE19:1; /* Channel 19 Data Transfer Request Enable */\r
+ vuint32_t DTRE18:1; /* Channel 18 Data Transfer Request Enable */\r
+ vuint32_t DTRE17:1; /* Channel 17 Data Transfer Request Enable */\r
+ vuint32_t DTRE16:1; /* Channel 16 Data Transfer Request Enable */\r
+ vuint32_t DTRE15:1; /* Channel 15 Data Transfer Request Enable */\r
+ vuint32_t DTRE14:1; /* Channel 14 Data Transfer Request Enable */\r
+ vuint32_t DTRE13:1; /* Channel 13 Data Transfer Request Enable */\r
+ vuint32_t DTRE12:1; /* Channel 12 Data Transfer Request Enable */\r
+ vuint32_t DTRE11:1; /* Channel 11 Data Transfer Request Enable */\r
+ vuint32_t DTRE10:1; /* Channel 10 Data Transfer Request Enable */\r
+ vuint32_t DTRE9:1; /* Channel 9 Data Transfer Request Enable */\r
+ vuint32_t DTRE8:1; /* Channel 8 Data Transfer Request Enable */\r
+ vuint32_t DTRE7:1; /* Channel 7 Data Transfer Request Enable */\r
+ vuint32_t DTRE6:1; /* Channel 6 Data Transfer Request Enable */\r
+ vuint32_t DTRE5:1; /* Channel 5 Data Transfer Request Enable */\r
+ vuint32_t DTRE4:1; /* Channel 4 Data Transfer Request Enable */\r
+ vuint32_t DTRE3:1; /* Channel 3 Data Transfer Request Enable */\r
+ vuint32_t DTRE2:1; /* Channel 2 Data Transfer Request Enable */\r
+ vuint32_t DTRE1:1; /* Channel 1 Data Transfer Request Enable */\r
+ vuint32_t DTRE0:1; /* Channel 0 Data Transfer Request Enable */\r
+ } B;\r
+ } CDTRER_B;\r
+\r
+ uint32_t etpu_reserved20[10];\r
+ union { /* ETPU_A Channel Pending Service Status */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t SR31:1; /* Channel 31 Pending Service Status */\r
+ vuint32_t SR30:1; /* Channel 30 Pending Service Status */\r
+ vuint32_t SR29:1; /* Channel 29 Pending Service Status */\r
+ vuint32_t SR28:1; /* Channel 28 Pending Service Status */\r
+ vuint32_t SR27:1; /* Channel 27 Pending Service Status */\r
+ vuint32_t SR26:1; /* Channel 26 Pending Service Status */\r
+ vuint32_t SR25:1; /* Channel 25 Pending Service Status */\r
+ vuint32_t SR24:1; /* Channel 24 Pending Service Status */\r
+ vuint32_t SR23:1; /* Channel 23 Pending Service Status */\r
+ vuint32_t SR22:1; /* Channel 22 Pending Service Status */\r
+ vuint32_t SR21:1; /* Channel 21 Pending Service Status */\r
+ vuint32_t SR20:1; /* Channel 20 Pending Service Status */\r
+ vuint32_t SR19:1; /* Channel 19 Pending Service Status */\r
+ vuint32_t SR18:1; /* Channel 18 Pending Service Status */\r
+ vuint32_t SR17:1; /* Channel 17 Pending Service Status */\r
+ vuint32_t SR16:1; /* Channel 16 Pending Service Status */\r
+ vuint32_t SR15:1; /* Channel 15 Pending Service Status */\r
+ vuint32_t SR14:1; /* Channel 14 Pending Service Status */\r
+ vuint32_t SR13:1; /* Channel 13 Pending Service Status */\r
+ vuint32_t SR12:1; /* Channel 12 Pending Service Status */\r
+ vuint32_t SR11:1; /* Channel 11 Pending Service Status */\r
+ vuint32_t SR10:1; /* Channel 10 Pending Service Status */\r
+ vuint32_t SR9:1; /* Channel 9 Pending Service Status */\r
+ vuint32_t SR8:1; /* Channel 8 Pending Service Status */\r
+ vuint32_t SR7:1; /* Channel 7 Pending Service Status */\r
+ vuint32_t SR6:1; /* Channel 6 Pending Service Status */\r
+ vuint32_t SR5:1; /* Channel 5 Pending Service Status */\r
+ vuint32_t SR4:1; /* Channel 4 Pending Service Status */\r
+ vuint32_t SR3:1; /* Channel 3 Pending Service Status */\r
+ vuint32_t SR2:1; /* Channel 2 Pending Service Status */\r
+ vuint32_t SR1:1; /* Channel 1 Pending Service Status */\r
+ vuint32_t SR0:1; /* Channel 0 Pending Service Status */\r
+ } B;\r
+ } CPSSR_A;\r
+\r
+ union { /* ETPU_B Channel Pending Service Status */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t SR31:1; /* Channel 31 Pending Service Status */\r
+ vuint32_t SR30:1; /* Channel 30 Pending Service Status */\r
+ vuint32_t SR29:1; /* Channel 29 Pending Service Status */\r
+ vuint32_t SR28:1; /* Channel 28 Pending Service Status */\r
+ vuint32_t SR27:1; /* Channel 27 Pending Service Status */\r
+ vuint32_t SR26:1; /* Channel 26 Pending Service Status */\r
+ vuint32_t SR25:1; /* Channel 25 Pending Service Status */\r
+ vuint32_t SR24:1; /* Channel 24 Pending Service Status */\r
+ vuint32_t SR23:1; /* Channel 23 Pending Service Status */\r
+ vuint32_t SR22:1; /* Channel 22 Pending Service Status */\r
+ vuint32_t SR21:1; /* Channel 21 Pending Service Status */\r
+ vuint32_t SR20:1; /* Channel 20 Pending Service Status */\r
+ vuint32_t SR19:1; /* Channel 19 Pending Service Status */\r
+ vuint32_t SR18:1; /* Channel 18 Pending Service Status */\r
+ vuint32_t SR17:1; /* Channel 17 Pending Service Status */\r
+ vuint32_t SR16:1; /* Channel 16 Pending Service Status */\r
+ vuint32_t SR15:1; /* Channel 15 Pending Service Status */\r
+ vuint32_t SR14:1; /* Channel 14 Pending Service Status */\r
+ vuint32_t SR13:1; /* Channel 13 Pending Service Status */\r
+ vuint32_t SR12:1; /* Channel 12 Pending Service Status */\r
+ vuint32_t SR11:1; /* Channel 11 Pending Service Status */\r
+ vuint32_t SR10:1; /* Channel 10 Pending Service Status */\r
+ vuint32_t SR9:1; /* Channel 9 Pending Service Status */\r
+ vuint32_t SR8:1; /* Channel 8 Pending Service Status */\r
+ vuint32_t SR7:1; /* Channel 7 Pending Service Status */\r
+ vuint32_t SR6:1; /* Channel 6 Pending Service Status */\r
+ vuint32_t SR5:1; /* Channel 5 Pending Service Status */\r
+ vuint32_t SR4:1; /* Channel 4 Pending Service Status */\r
+ vuint32_t SR3:1; /* Channel 3 Pending Service Status */\r
+ vuint32_t SR2:1; /* Channel 2 Pending Service Status */\r
+ vuint32_t SR1:1; /* Channel 1 Pending Service Status */\r
+ vuint32_t SR0:1; /* Channel 0 Pending Service Status */\r
+ } B;\r
+ } CPSSR_B;\r
+\r
+ uint32_t etpu_reserved20a[2];\r
+\r
+ union { /* ETPU_A Channel Service Status */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t SS31:1; /* Channel 31 Service Status */\r
+ vuint32_t SS30:1; /* Channel 30 Service Status */\r
+ vuint32_t SS29:1; /* Channel 29 Service Status */\r
+ vuint32_t SS28:1; /* Channel 28 Service Status */\r
+ vuint32_t SS27:1; /* Channel 27 Service Status */\r
+ vuint32_t SS26:1; /* Channel 26 Service Status */\r
+ vuint32_t SS25:1; /* Channel 25 Service Status */\r
+ vuint32_t SS24:1; /* Channel 24 Service Status */\r
+ vuint32_t SS23:1; /* Channel 23 Service Status */\r
+ vuint32_t SS22:1; /* Channel 22 Service Status */\r
+ vuint32_t SS21:1; /* Channel 21 Service Status */\r
+ vuint32_t SS20:1; /* Channel 20 Service Status */\r
+ vuint32_t SS19:1; /* Channel 19 Service Status */\r
+ vuint32_t SS18:1; /* Channel 18 Service Status */\r
+ vuint32_t SS17:1; /* Channel 17 Service Status */\r
+ vuint32_t SS16:1; /* Channel 16 Service Status */\r
+ vuint32_t SS15:1; /* Channel 15 Service Status */\r
+ vuint32_t SS14:1; /* Channel 14 Service Status */\r
+ vuint32_t SS13:1; /* Channel 13 Service Status */\r
+ vuint32_t SS12:1; /* Channel 12 Service Status */\r
+ vuint32_t SS11:1; /* Channel 11 Service Status */\r
+ vuint32_t SS10:1; /* Channel 10 Service Status */\r
+ vuint32_t SS9:1; /* Channel 9 Service Status */\r
+ vuint32_t SS8:1; /* Channel 8 Service Status */\r
+ vuint32_t SS7:1; /* Channel 7 Service Status */\r
+ vuint32_t SS6:1; /* Channel 6 Service Status */\r
+ vuint32_t SS5:1; /* Channel 5 Service Status */\r
+ vuint32_t SS4:1; /* Channel 4 Service Status */\r
+ vuint32_t SS3:1; /* Channel 3 Service Status */\r
+ vuint32_t SS2:1; /* Channel 2 Service Status */\r
+ vuint32_t SS1:1; /* Channel 1 Service Status */\r
+ vuint32_t SS0:1; /* Channel 0 Service Status */\r
+ } B;\r
+ } CSSR_A;\r
+\r
+ union { /* ETPU_B Channel Service Status */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t SS31:1; /* Channel 31 Service Status */\r
+ vuint32_t SS30:1; /* Channel 30 Service Status */\r
+ vuint32_t SS29:1; /* Channel 29 Service Status */\r
+ vuint32_t SS28:1; /* Channel 28 Service Status */\r
+ vuint32_t SS27:1; /* Channel 27 Service Status */\r
+ vuint32_t SS26:1; /* Channel 26 Service Status */\r
+ vuint32_t SS25:1; /* Channel 25 Service Status */\r
+ vuint32_t SS24:1; /* Channel 24 Service Status */\r
+ vuint32_t SS23:1; /* Channel 23 Service Status */\r
+ vuint32_t SS22:1; /* Channel 22 Service Status */\r
+ vuint32_t SS21:1; /* Channel 21 Service Status */\r
+ vuint32_t SS20:1; /* Channel 20 Service Status */\r
+ vuint32_t SS19:1; /* Channel 19 Service Status */\r
+ vuint32_t SS18:1; /* Channel 18 Service Status */\r
+ vuint32_t SS17:1; /* Channel 17 Service Status */\r
+ vuint32_t SS16:1; /* Channel 16 Service Status */\r
+ vuint32_t SS15:1; /* Channel 15 Service Status */\r
+ vuint32_t SS14:1; /* Channel 14 Service Status */\r
+ vuint32_t SS13:1; /* Channel 13 Service Status */\r
+ vuint32_t SS12:1; /* Channel 12 Service Status */\r
+ vuint32_t SS11:1; /* Channel 11 Service Status */\r
+ vuint32_t SS10:1; /* Channel 10 Service Status */\r
+ vuint32_t SS9:1; /* Channel 9 Service Status */\r
+ vuint32_t SS8:1; /* Channel 8 Service Status */\r
+ vuint32_t SS7:1; /* Channel 7 Service Status */\r
+ vuint32_t SS6:1; /* Channel 6 Service Status */\r
+ vuint32_t SS5:1; /* Channel 5 Service Status */\r
+ vuint32_t SS4:1; /* Channel 4 Service Status */\r
+ vuint32_t SS3:1; /* Channel 3 Service Status */\r
+ vuint32_t SS2:1; /* Channel 2 Service Status */\r
+ vuint32_t SS1:1; /* Channel 1 Service Status */\r
+ vuint32_t SS0:1; /* Channel 0 Service Status */\r
+ } B;\r
+ } CSSR_B;\r
+\r
+ uint32_t etpu_reserved23[90];\r
+\r
+/*****************************Channels********************************/\r
+\r
+ struct {\r
+ union {\r
+ vuint32_t R; /* Channel Configuration Register */\r
+ struct {\r
+ vuint32_t CIE:1; /* Channel Interruput Enable */\r
+ vuint32_t DTRE:1; /* Data Transfer Request Enable */\r
+ vuint32_t CPR:2; /* Channel Priority */\r
+ vuint32_t:3;\r
+ vuint32_t ETCS:1; /* Entry Table Condition Select */\r
+ vuint32_t:3;\r
+ vuint32_t CFS:5; /* Channel Function Select */\r
+ vuint32_t ODIS:1; /* Output disable */\r
+ vuint32_t OPOL:1; /* output polarity */\r
+ vuint32_t:3;\r
+ vuint32_t CPBA:11; /* Channel Parameter Base Address */\r
+ } B;\r
+ } CR;\r
+ union {\r
+ vuint32_t R; /* Channel Status Control Register */\r
+ struct {\r
+ vuint32_t CIS:1; /* Channel Interruput Status */\r
+ vuint32_t CIOS:1; /* Channel Interruput Overflow Status */\r
+ vuint32_t:6;\r
+ vuint32_t DTRS:1; /* Data Transfer Status */\r
+ vuint32_t DTROS:1; /* Data Transfer Overflow Status */\r
+ vuint32_t:6;\r
+ vuint32_t IPS:1; /* Input Pin State */\r
+ vuint32_t OPS:1; /* Output Pin State */\r
+ vuint32_t OBE:1; /* Output Buffer Enable */\r
+ vuint32_t:11;\r
+ vuint32_t FM1:1; /* Function mode */\r
+ vuint32_t FM0:1; /* Function mode */\r
+ } B;\r
+ } SCR;\r
+ union {\r
+ vuint32_t R; /* Channel Host Service Request Register */\r
+ struct {\r
+ vuint32_t:29; /* Host Service Request */\r
+ vuint32_t HSR:3;\r
+ } B;\r
+ } HSRR;\r
+ uint32_t etpu_reserved23;\r
+ } CHAN[127];\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : XBAR CrossBar */\r
+/****************************************************************************/\r
+ struct XBAR_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:1;\r
+ vuint32_t MSTR2:3;\r
+ vuint32_t:1;\r
+ vuint32_t MSTR1:3;\r
+ vuint32_t:1;\r
+ vuint32_t MSTR0:3;\r
+ } B;\r
+ } MPR0; /* Master Priority Register for Slave Port 0 */\r
+\r
+ uint32_t xbar_reserved1[3];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t RO:1;\r
+ vuint32_t:21;\r
+ vuint32_t ARB:2;\r
+ vuint32_t:2;\r
+ vuint32_t PCTL:2;\r
+ vuint32_t:1;\r
+ vuint32_t PARK:3;\r
+ } B;\r
+ } SGPCR0; /* General Purpose Control Register for Slave Port 0 */\r
+\r
+ uint32_t xbar_reserved2[59];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:1;\r
+ vuint32_t MSTR2:3;\r
+ vuint32_t:1;\r
+ vuint32_t MSTR1:3;\r
+ vuint32_t:1;\r
+ vuint32_t MSTR0:3;\r
+ } B;\r
+ } MPR1; /* Master Priority Register for Slave Port 1 */\r
+\r
+ uint32_t xbar_reserved3[3];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t RO:1;\r
+ vuint32_t:21;\r
+ vuint32_t ARB:2;\r
+ vuint32_t:2;\r
+ vuint32_t PCTL:2;\r
+ vuint32_t:1;\r
+ vuint32_t PARK:3;\r
+ } B;\r
+ } SGPCR1; /* General Purpose Control Register for Slave Port 1 */\r
+\r
+ uint32_t xbar_reserved4[123];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:1;\r
+ vuint32_t MSTR2:3;\r
+ vuint32_t:1;\r
+ vuint32_t MSTR1:3;\r
+ vuint32_t:1;\r
+ vuint32_t MSTR0:3;\r
+ } B;\r
+ } MPR3; /* Master Priority Register for Slave Port 3 */\r
+\r
+ uint32_t xbar_reserved5[3];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t RO:1;\r
+ vuint32_t:21;\r
+ vuint32_t ARB:2;\r
+ vuint32_t:2;\r
+ vuint32_t PCTL:2;\r
+ vuint32_t:1;\r
+ vuint32_t PARK:3;\r
+ } B;\r
+ } SGPCR3; /* General Purpose Control Register for Slave Port 3 */\r
+ uint32_t xbar_reserved6[187];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:1;\r
+ vuint32_t MSTR2:3;\r
+ vuint32_t:1;\r
+ vuint32_t MSTR1:3;\r
+ vuint32_t:1;\r
+ vuint32_t MSTR0:3;\r
+ } B;\r
+ } MPR6; /* Master Priority Register for Slave Port 6 */\r
+\r
+ uint32_t xbar_reserved7[3];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t RO:1;\r
+ vuint32_t:21;\r
+ vuint32_t ARB:2;\r
+ vuint32_t:2;\r
+ vuint32_t PCTL:2;\r
+ vuint32_t:1;\r
+ vuint32_t PARK:3;\r
+ } B;\r
+ } SGPCR6; /* General Purpose Control Register for Slave Port 6 */\r
+\r
+ uint32_t xbar_reserved8[59];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:1;\r
+ vuint32_t MSTR2:3;\r
+ vuint32_t:1;\r
+ vuint32_t MSTR1:3;\r
+ vuint32_t:1;\r
+ vuint32_t MSTR0:3;\r
+ } B;\r
+ } MPR7; /* Master Priority Register for Slave Port 7 */\r
+\r
+ uint32_t xbar_reserved9[3];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t RO:1;\r
+ vuint32_t:21;\r
+ vuint32_t ARB:2;\r
+ vuint32_t:2;\r
+ vuint32_t PCTL:2;\r
+ vuint32_t:1;\r
+ vuint32_t PARK:3;\r
+ } B;\r
+ } SGPCR7; /* General Purpose Control Register for Slave Port 7 */\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : ECSM */\r
+/****************************************************************************/\r
+ struct ECSM_tag {\r
+\r
+ uint32_t ecsm_reserved1[5];\r
+\r
+ uint16_t ecsm_reserved2;\r
+\r
+ union {\r
+ vuint16_t R;\r
+ } SWTCR; //Software Watchdog Timer Control\r
+\r
+ uint8_t ecsm_reserved3[3];\r
+\r
+ union {\r
+ vuint8_t R;\r
+ } SWTSR; //SWT Service Register\r
+\r
+ uint8_t ecsm_reserved4[3];\r
+\r
+ union {\r
+ vuint8_t R;\r
+ } SWTIR; //SWT Interrupt Register\r
+\r
+ uint32_t ecsm_reserved5a[1];\r
+ uint32_t ecsm_reserved5b[1];\r
+\r
+ uint32_t ecsm_reserved5c[6];\r
+\r
+ uint8_t ecsm_reserved6[3];\r
+\r
+ union {\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t:6;\r
+ vuint8_t ERNCR:1;\r
+ vuint8_t EFNCR:1;\r
+ } B;\r
+ } ECR; //ECC Configuration Register\r
+\r
+ uint8_t mcm_reserved8[3];\r
+\r
+ union {\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t:6;\r
+ vuint8_t RNCE:1;\r
+ vuint8_t FNCE:1;\r
+ } B;\r
+ } ESR; //ECC Status Register\r
+\r
+ uint16_t ecsm_reserved9;\r
+\r
+ union {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:6;\r
+ vuint16_t FRCNCI:1;\r
+ vuint16_t FR1NCI:1;\r
+ vuint16_t:1;\r
+ vuint16_t ERRBIT:7;\r
+ } B;\r
+ } EEGR; //ECC Error Generation Register\r
+\r
+ uint32_t ecsm_reserved10;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t FEAR:32;\r
+ } B;\r
+ } FEAR; //Flash ECC Address Register\r
+\r
+ uint16_t ecsm_reserved11;\r
+\r
+ union {\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t:4;\r
+ vuint8_t FEMR:4;\r
+ } B;\r
+ } FEMR; //Flash ECC Master Register\r
+\r
+ union {\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t WRITE:1;\r
+ vuint8_t SIZE:3;\r
+ vuint8_t PROT0:1;\r
+ vuint8_t PROT1:1;\r
+ vuint8_t PROT2:1;\r
+ vuint8_t PROT3:1;\r
+ } B;\r
+ } FEAT; //Flash ECC Attributes Register\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t FEDH:32;\r
+ } B;\r
+ } FEDRH; //Flash ECC Data High Register\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t FEDL:32;\r
+ } B;\r
+ } FEDRL; //Flash ECC Data Low Register\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t REAR:32;\r
+ } B;\r
+ } REAR; //RAM ECC Address\r
+\r
+ uint8_t ecsm_reserved12[2];\r
+\r
+ union {\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t:4;\r
+ vuint8_t REMR:4;\r
+ } B;\r
+ } REMR; //RAM ECC Master\r
+\r
+ union {\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t WRITE:1;\r
+ vuint8_t SIZE:3;\r
+ vuint8_t PROT0:1;\r
+ vuint8_t PROT1:1;\r
+ vuint8_t PROT2:1;\r
+ vuint8_t PROT3:1;\r
+ } B;\r
+ } REAT; // RAM ECC Attributes Register\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t REDH:32;\r
+ } B;\r
+ } REDRH; //RAM ECC Data High Register\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t REDL:32;\r
+ } B;\r
+ } REDRL; //RAMECC Data Low Register\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : eDMA */\r
+/****************************************************************************/\r
+ struct EDMA_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t GRP3PRI:2;\r
+ vuint32_t GRP2PRI:2;\r
+ vuint32_t GRP1PRI:2;\r
+ vuint32_t GRP0PRI:2;\r
+ vuint32_t:4;\r
+ vuint32_t ERGA:1;\r
+ vuint32_t ERCA:1;\r
+ vuint32_t EDBG:1;\r
+ vuint32_t EBW:1;\r
+ } B;\r
+ } CR; /* Control Register */\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t VLD:1;\r
+ vuint32_t:15;\r
+ vuint32_t GPE:1;\r
+ vuint32_t CPE:1;\r
+ vuint32_t ERRCHN:6;\r
+ vuint32_t SAE:1;\r
+ vuint32_t SOE:1;\r
+ vuint32_t DAE:1;\r
+ vuint32_t DOE:1;\r
+ vuint32_t NCE:1;\r
+ vuint32_t SGE:1;\r
+ vuint32_t SBE:1;\r
+ vuint32_t DBE:1;\r
+ } B;\r
+ } ESR; /* Error Status Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t ERQ63:1;\r
+ vuint32_t ERQ62:1;\r
+ vuint32_t ERQ61:1;\r
+ vuint32_t ERQ60:1;\r
+ vuint32_t ERQ59:1;\r
+ vuint32_t ERQ58:1;\r
+ vuint32_t ERQ57:1;\r
+ vuint32_t ERQ56:1;\r
+ vuint32_t ERQ55:1;\r
+ vuint32_t ERQ54:1;\r
+ vuint32_t ERQ53:1;\r
+ vuint32_t ERQ52:1;\r
+ vuint32_t ERQ51:1;\r
+ vuint32_t ERQ50:1;\r
+ vuint32_t ERQ49:1;\r
+ vuint32_t ERQ48:1;\r
+ vuint32_t ERQ47:1;\r
+ vuint32_t ERQ46:1;\r
+ vuint32_t ERQ45:1;\r
+ vuint32_t ERQ44:1;\r
+ vuint32_t ERQ43:1;\r
+ vuint32_t ERQ42:1;\r
+ vuint32_t ERQ41:1;\r
+ vuint32_t ERQ40:1;\r
+ vuint32_t ERQ39:1;\r
+ vuint32_t ERQ38:1;\r
+ vuint32_t ERQ37:1;\r
+ vuint32_t ERQ36:1;\r
+ vuint32_t ERQ35:1;\r
+ vuint32_t ERQ34:1;\r
+ vuint32_t ERQ33:1;\r
+ vuint32_t ERQ32:1;\r
+ } B;\r
+ } ERQRH; /* DMA Enable Request Register High */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t ERQ31:1;\r
+ vuint32_t ERQ30:1;\r
+ vuint32_t ERQ29:1;\r
+ vuint32_t ERQ28:1;\r
+ vuint32_t ERQ27:1;\r
+ vuint32_t ERQ26:1;\r
+ vuint32_t ERQ25:1;\r
+ vuint32_t ERQ24:1;\r
+ vuint32_t ERQ23:1;\r
+ vuint32_t ERQ22:1;\r
+ vuint32_t ERQ21:1;\r
+ vuint32_t ERQ20:1;\r
+ vuint32_t ERQ19:1;\r
+ vuint32_t ERQ18:1;\r
+ vuint32_t ERQ17:1;\r
+ vuint32_t ERQ16:1;\r
+ vuint32_t ERQ15:1;\r
+ vuint32_t ERQ14:1;\r
+ vuint32_t ERQ13:1;\r
+ vuint32_t ERQ12:1;\r
+ vuint32_t ERQ11:1;\r
+ vuint32_t ERQ10:1;\r
+ vuint32_t ERQ09:1;\r
+ vuint32_t ERQ08:1;\r
+ vuint32_t ERQ07:1;\r
+ vuint32_t ERQ06:1;\r
+ vuint32_t ERQ05:1;\r
+ vuint32_t ERQ04:1;\r
+ vuint32_t ERQ03:1;\r
+ vuint32_t ERQ02:1;\r
+ vuint32_t ERQ01:1;\r
+ vuint32_t ERQ00:1;\r
+ } B;\r
+ } ERQRL; /* DMA Enable Request Register Low */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t EEI63:1;\r
+ vuint32_t EEI62:1;\r
+ vuint32_t EEI61:1;\r
+ vuint32_t EEI60:1;\r
+ vuint32_t EEI59:1;\r
+ vuint32_t EEI58:1;\r
+ vuint32_t EEI57:1;\r
+ vuint32_t EEI56:1;\r
+ vuint32_t EEI55:1;\r
+ vuint32_t EEI54:1;\r
+ vuint32_t EEI53:1;\r
+ vuint32_t EEI52:1;\r
+ vuint32_t EEI51:1;\r
+ vuint32_t EEI50:1;\r
+ vuint32_t EEI49:1;\r
+ vuint32_t EEI48:1;\r
+ vuint32_t EEI47:1;\r
+ vuint32_t EEI46:1;\r
+ vuint32_t EEI45:1;\r
+ vuint32_t EEI44:1;\r
+ vuint32_t EEI43:1;\r
+ vuint32_t EEI42:1;\r
+ vuint32_t EEI41:1;\r
+ vuint32_t EEI40:1;\r
+ vuint32_t EEI39:1;\r
+ vuint32_t EEI38:1;\r
+ vuint32_t EEI37:1;\r
+ vuint32_t EEI36:1;\r
+ vuint32_t EEI35:1;\r
+ vuint32_t EEI34:1;\r
+ vuint32_t EEI33:1;\r
+ vuint32_t EEI32:1;\r
+ } B;\r
+ } EEIRH; /* DMA Enable Error Interrupt Register High */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t EEI31:1;\r
+ vuint32_t EEI30:1;\r
+ vuint32_t EEI29:1;\r
+ vuint32_t EEI28:1;\r
+ vuint32_t EEI27:1;\r
+ vuint32_t EEI26:1;\r
+ vuint32_t EEI25:1;\r
+ vuint32_t EEI24:1;\r
+ vuint32_t EEI23:1;\r
+ vuint32_t EEI22:1;\r
+ vuint32_t EEI21:1;\r
+ vuint32_t EEI20:1;\r
+ vuint32_t EEI19:1;\r
+ vuint32_t EEI18:1;\r
+ vuint32_t EEI17:1;\r
+ vuint32_t EEI16:1;\r
+ vuint32_t EEI15:1;\r
+ vuint32_t EEI14:1;\r
+ vuint32_t EEI13:1;\r
+ vuint32_t EEI12:1;\r
+ vuint32_t EEI11:1;\r
+ vuint32_t EEI10:1;\r
+ vuint32_t EEI09:1;\r
+ vuint32_t EEI08:1;\r
+ vuint32_t EEI07:1;\r
+ vuint32_t EEI06:1;\r
+ vuint32_t EEI05:1;\r
+ vuint32_t EEI04:1;\r
+ vuint32_t EEI03:1;\r
+ vuint32_t EEI02:1;\r
+ vuint32_t EEI01:1;\r
+ vuint32_t EEI00:1;\r
+ } B;\r
+ } EEIRL; /* DMA Enable Error Interrupt Register Low */\r
+ union {\r
+ vuint8_t R;\r
+ vuint8_t B;\r
+ } SERQR; /* DMA Set Enable Request Register */\r
+ union {\r
+ vuint8_t R;\r
+ vuint8_t B;\r
+ } CERQR; /* DMA Clear Enable Request Register */\r
+ union {\r
+ vuint8_t R;\r
+ vuint8_t B;\r
+ } SEEIR; /* DMA Set Enable Error Interrupt Register */\r
+ union {\r
+ vuint8_t R;\r
+ vuint8_t B;\r
+ } CEEIR; /* DMA Clear Enable Error Interrupt Register */\r
+ union {\r
+ vuint8_t R;\r
+ vuint8_t B;\r
+ } CIRQR; /* DMA Clear Interrupt Request Register */\r
+ union {\r
+ vuint8_t R;\r
+ vuint8_t B;\r
+ } CER; /* DMA Clear error Register */\r
+ union {\r
+ vuint8_t R;\r
+ vuint8_t B;\r
+ } SSBR; /* Set Start Bit Register */\r
+ union {\r
+ vuint8_t R;\r
+ vuint8_t B;\r
+ } CDSBR; /* Clear Done Status Bit Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t INT63:1;\r
+ vuint32_t INT62:1;\r
+ vuint32_t INT61:1;\r
+ vuint32_t INT60:1;\r
+ vuint32_t INT59:1;\r
+ vuint32_t INT58:1;\r
+ vuint32_t INT57:1;\r
+ vuint32_t INT56:1;\r
+ vuint32_t INT55:1;\r
+ vuint32_t INT54:1;\r
+ vuint32_t INT53:1;\r
+ vuint32_t INT52:1;\r
+ vuint32_t INT51:1;\r
+ vuint32_t INT50:1;\r
+ vuint32_t INT49:1;\r
+ vuint32_t INT48:1;\r
+ vuint32_t INT47:1;\r
+ vuint32_t INT46:1;\r
+ vuint32_t INT45:1;\r
+ vuint32_t INT44:1;\r
+ vuint32_t INT43:1;\r
+ vuint32_t INT42:1;\r
+ vuint32_t INT41:1;\r
+ vuint32_t INT40:1;\r
+ vuint32_t INT39:1;\r
+ vuint32_t INT38:1;\r
+ vuint32_t INT37:1;\r
+ vuint32_t INT36:1;\r
+ vuint32_t INT35:1;\r
+ vuint32_t INT34:1;\r
+ vuint32_t INT33:1;\r
+ vuint32_t INT32:1;\r
+ } B;\r
+ } IRQRH; /* DMA Interrupt Request High */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t INT31:1;\r
+ vuint32_t INT30:1;\r
+ vuint32_t INT29:1;\r
+ vuint32_t INT28:1;\r
+ vuint32_t INT27:1;\r
+ vuint32_t INT26:1;\r
+ vuint32_t INT25:1;\r
+ vuint32_t INT24:1;\r
+ vuint32_t INT23:1;\r
+ vuint32_t INT22:1;\r
+ vuint32_t INT21:1;\r
+ vuint32_t INT20:1;\r
+ vuint32_t INT19:1;\r
+ vuint32_t INT18:1;\r
+ vuint32_t INT17:1;\r
+ vuint32_t INT16:1;\r
+ vuint32_t INT15:1;\r
+ vuint32_t INT14:1;\r
+ vuint32_t INT13:1;\r
+ vuint32_t INT12:1;\r
+ vuint32_t INT11:1;\r
+ vuint32_t INT10:1;\r
+ vuint32_t INT09:1;\r
+ vuint32_t INT08:1;\r
+ vuint32_t INT07:1;\r
+ vuint32_t INT06:1;\r
+ vuint32_t INT05:1;\r
+ vuint32_t INT04:1;\r
+ vuint32_t INT03:1;\r
+ vuint32_t INT02:1;\r
+ vuint32_t INT01:1;\r
+ vuint32_t INT00:1;\r
+ } B;\r
+ } IRQRL; /* DMA Interrupt Request Low */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t ERR63:1;\r
+ vuint32_t ERR62:1;\r
+ vuint32_t ERR61:1;\r
+ vuint32_t ERR60:1;\r
+ vuint32_t ERR59:1;\r
+ vuint32_t ERR58:1;\r
+ vuint32_t ERR57:1;\r
+ vuint32_t ERR56:1;\r
+ vuint32_t ERR55:1;\r
+ vuint32_t ERR54:1;\r
+ vuint32_t ERR53:1;\r
+ vuint32_t ERR52:1;\r
+ vuint32_t ERR51:1;\r
+ vuint32_t ERR50:1;\r
+ vuint32_t ERR49:1;\r
+ vuint32_t ERR48:1;\r
+ vuint32_t ERR47:1;\r
+ vuint32_t ERR46:1;\r
+ vuint32_t ERR45:1;\r
+ vuint32_t ERR44:1;\r
+ vuint32_t ERR43:1;\r
+ vuint32_t ERR42:1;\r
+ vuint32_t ERR41:1;\r
+ vuint32_t ERR40:1;\r
+ vuint32_t ERR39:1;\r
+ vuint32_t ERR38:1;\r
+ vuint32_t ERR37:1;\r
+ vuint32_t ERR36:1;\r
+ vuint32_t ERR35:1;\r
+ vuint32_t ERR34:1;\r
+ vuint32_t ERR33:1;\r
+ vuint32_t ERR32:1;\r
+ } B;\r
+ } ERH; /* DMA Error High */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t ERR31:1;\r
+ vuint32_t ERR30:1;\r
+ vuint32_t ERR29:1;\r
+ vuint32_t ERR28:1;\r
+ vuint32_t ERR27:1;\r
+ vuint32_t ERR26:1;\r
+ vuint32_t ERR25:1;\r
+ vuint32_t ERR24:1;\r
+ vuint32_t ERR23:1;\r
+ vuint32_t ERR22:1;\r
+ vuint32_t ERR21:1;\r
+ vuint32_t ERR20:1;\r
+ vuint32_t ERR19:1;\r
+ vuint32_t ERR18:1;\r
+ vuint32_t ERR17:1;\r
+ vuint32_t ERR16:1;\r
+ vuint32_t ERR15:1;\r
+ vuint32_t ERR14:1;\r
+ vuint32_t ERR13:1;\r
+ vuint32_t ERR12:1;\r
+ vuint32_t ERR11:1;\r
+ vuint32_t ERR10:1;\r
+ vuint32_t ERR09:1;\r
+ vuint32_t ERR08:1;\r
+ vuint32_t ERR07:1;\r
+ vuint32_t ERR06:1;\r
+ vuint32_t ERR05:1;\r
+ vuint32_t ERR04:1;\r
+ vuint32_t ERR03:1;\r
+ vuint32_t ERR02:1;\r
+ vuint32_t ERR01:1;\r
+ vuint32_t ERR00:1;\r
+ } B;\r
+ } ERL; /* DMA Error Low */\r
+ uint32_t edma_reserved1[52];\r
+\r
+ union {\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t ECP:1;\r
+\r
+ vuint8_t:1;\r
+ vuint8_t GRPPRI:2;\r
+ vuint8_t CHPRI:4;\r
+\r
+ } B;\r
+ } CPR[64]; /* Channel n Priority */\r
+\r
+ uint32_t edma_reserved2[944];\r
+\r
+/****************************************************************************/\r
+/* DMA2 Transfer Control Descriptor */\r
+/****************************************************************************/\r
+\r
+ struct tcd_t { /*for "standard" format TCDs (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=0 && EDMA.EMLM=0 ) */\r
+ vuint32_t SADDR; /* source address */\r
+\r
+ vuint16_t SMOD:5; /* source address modulo */\r
+ vuint16_t SSIZE:3; /* source transfer size */\r
+ vuint16_t DMOD:5; /* destination address modulo */\r
+ vuint16_t DSIZE:3; /* destination transfer size */\r
+ vint16_t SOFF; /* signed source address offset */\r
+\r
+ vuint32_t NBYTES; /* inner (\93minor\94) byte count */\r
+\r
+ vint32_t SLAST; /* last destination address adjustment, or\r
+\r
+ scatter/gather address (if e_sg = 1) */\r
+ vuint32_t DADDR; /* destination address */\r
+\r
+ vuint16_t CITERE_LINK:1;\r
+ vuint16_t CITER:15;\r
+\r
+ vint16_t DOFF; /* signed destination address offset */\r
+\r
+ vint32_t DLAST_SGA;\r
+\r
+ vuint16_t BITERE_LINK:1; /* beginning ("major") iteration count */\r
+ vuint16_t BITER:15;\r
+\r
+ vuint16_t BWC:2; /* bandwidth control */\r
+ vuint16_t MAJORLINKCH:6; /* enable channel-to-channel link */\r
+ vuint16_t DONE:1; /* channel done */\r
+ vuint16_t ACTIVE:1; /* channel active */\r
+ vuint16_t MAJORE_LINK:1; /* enable channel-to-channel link */\r
+ vuint16_t E_SG:1; /* enable scatter/gather descriptor */\r
+ vuint16_t D_REQ:1; /* disable ipd_req when done */\r
+ vuint16_t INT_HALF:1; /* interrupt on citer = (biter >> 1) */\r
+ vuint16_t INT_MAJ:1; /* interrupt on major loop completion */\r
+ vuint16_t START:1; /* explicit channel start */\r
+ } TCD[64]; /* transfer_control_descriptor */\r
+\r
+ };\r
+\r
+ struct EDMA_TCD_alt1_tag { /*for alternate format TCDs (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=1 ) */\r
+\r
+ struct tcd_alt1_t {\r
+ vuint32_t SADDR; /* source address */\r
+\r
+ vuint16_t SMOD:5; /* source address modulo */\r
+ vuint16_t SSIZE:3; /* source transfer size */\r
+ vuint16_t DMOD:5; /* destination address modulo */\r
+ vuint16_t DSIZE:3; /* destination transfer size */\r
+ vint16_t SOFF; /* signed source address offset */\r
+\r
+ vuint32_t NBYTES; /* inner (\93minor\94) byte count */\r
+\r
+ vint32_t SLAST; /* last destination address adjustment, or\r
+\r
+ scatter/gather address (if e_sg = 1) */\r
+ vuint32_t DADDR; /* destination address */\r
+\r
+ vuint16_t CITERE_LINK:1;\r
+ vuint16_t CITERLINKCH:6;\r
+ vuint16_t CITER:9;\r
+\r
+ vint16_t DOFF; /* signed destination address offset */\r
+\r
+ vint32_t DLAST_SGA;\r
+\r
+ vuint16_t BITERE_LINK:1; /* beginning (\93major\94) iteration count */\r
+ vuint16_t BITERLINKCH:6;\r
+ vuint16_t BITER:9;\r
+\r
+ vuint16_t BWC:2; /* bandwidth control */\r
+ vuint16_t MAJORLINKCH:6; /* enable channel-to-channel link */\r
+ vuint16_t DONE:1; /* channel done */\r
+ vuint16_t ACTIVE:1; /* channel active */\r
+ vuint16_t MAJORE_LINK:1; /* enable channel-to-channel link */\r
+ vuint16_t E_SG:1; /* enable scatter/gather descriptor */\r
+ vuint16_t D_REQ:1; /* disable ipd_req when done */\r
+ vuint16_t INT_HALF:1; /* interrupt on citer = (biter >> 1) */\r
+ vuint16_t INT_MAJ:1; /* interrupt on major loop completion */\r
+ vuint16_t START:1; /* explicit channel start */\r
+ } TCD[64]; /* transfer_control_descriptor */\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : INTC */\r
+/****************************************************************************/\r
+ struct INTC_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:26;\r
+ vuint32_t VTES:1;\r
+ vuint32_t:4;\r
+ vuint32_t HVEN:1;\r
+ } B;\r
+ } MCR; /* Module Configuration Register */\r
+\r
+ int32_t INTC_reserved00;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:28;\r
+ vuint32_t PRI:4;\r
+ } B;\r
+ } CPR; /* Current Priority Register */\r
+\r
+ uint32_t intc_reserved1;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t VTBA:21;\r
+ vuint32_t INTVEC:9;\r
+ vuint32_t:2;\r
+ } B;\r
+ } IACKR; /* Interrupt Acknowledge Register */\r
+\r
+ uint32_t intc_reserved2;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:32;\r
+ } B;\r
+ } EOIR; /* End of Interrupt Register */\r
+\r
+ uint32_t intc_reserved3;\r
+\r
+ union {\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t:6;\r
+ vuint8_t SET:1;\r
+ vuint8_t CLR:1;\r
+ } B;\r
+ } SSCIR[8]; /* Software Set/Clear Interruput Register */\r
+\r
+ uint32_t intc_reserved4[6];\r
+\r
+ union {\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t:4;\r
+ vuint8_t PRI:4;\r
+ } B;\r
+ } PSR[358]; /* Software Set/Clear Interrupt Register */\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : EQADC */\r
+/****************************************************************************/\r
+ struct EQADC_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:27;\r
+ vuint32_t ESSIE:2;\r
+ vuint32_t:1;\r
+ vuint32_t DBG:2;\r
+ } B;\r
+ } MCR; /* Module Configuration Register */\r
+\r
+ int32_t EQADC_reserved00;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:6;\r
+ vuint32_t NMF:26;\r
+ } B;\r
+ } NMSFR; /* Null Message Send Format Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:28;\r
+ vuint32_t DFL:4;\r
+ } B;\r
+ } ETDFR; /* External Trigger Digital Filter Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CFPUSH:32;\r
+ } B;\r
+ } CFPR[6]; /* CFIFO Push Registers */\r
+\r
+ uint32_t eqadc_reserved1;\r
+\r
+ uint32_t eqadc_reserved2;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t RFPOP:16;\r
+ } B;\r
+ } RFPR[6]; /* Result FIFO Pop Registers */\r
+\r
+ uint32_t eqadc_reserved3;\r
+\r
+ uint32_t eqadc_reserved4;\r
+\r
+ union {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:5;\r
+ vuint16_t SSE:1;\r
+ vuint16_t CFINV:1;\r
+ vuint16_t:1;\r
+ vuint16_t MODE:4;\r
+ vuint16_t:4;\r
+ } B;\r
+ } CFCR[6]; /* CFIFO Control Registers */\r
+\r
+ uint32_t eqadc_reserved5;\r
+\r
+ union {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t NCIE:1;\r
+ vuint16_t TORIE:1;\r
+ vuint16_t PIE:1;\r
+ vuint16_t EOQIE:1;\r
+ vuint16_t CFUIE:1;\r
+ vuint16_t:1;\r
+ vuint16_t CFFE:1;\r
+ vuint16_t CFFS:1;\r
+ vuint16_t:4;\r
+ vuint16_t RFOIE:1;\r
+ vuint16_t:1;\r
+ vuint16_t RFDE:1;\r
+ vuint16_t RFDS:1;\r
+ } B;\r
+ } IDCR[6]; /* Interrupt and DMA Control Registers */\r
+\r
+ uint32_t eqadc_reserved6;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t NCF:1;\r
+ vuint32_t TORF:1;\r
+ vuint32_t PF:1;\r
+ vuint32_t EOQF:1;\r
+ vuint32_t CFUF:1;\r
+ vuint32_t SSS:1;\r
+ vuint32_t CFFF:1;\r
+ vuint32_t:5;\r
+ vuint32_t RFOF:1;\r
+ vuint32_t:1;\r
+ vuint32_t RFDF:1;\r
+ vuint32_t:1;\r
+ vuint32_t CFCTR:4;\r
+ vuint32_t TNXTPTR:4;\r
+ vuint32_t RFCTR:4;\r
+ vuint32_t POPNXTPTR:4;\r
+ } B;\r
+ } FISR[6]; /* FIFO and Interrupt Status Registers */\r
+\r
+ uint32_t eqadc_reserved7;\r
+\r
+ uint32_t eqadc_reserved8;\r
+\r
+ union {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:5;\r
+ vuint16_t TCCF:11;\r
+ } B;\r
+ } CFTCR[6]; /* CFIFO Transfer Counter Registers */\r
+\r
+ uint32_t eqadc_reserved9;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CFS0:2;\r
+ vuint32_t CFS1:2;\r
+ vuint32_t CFS2:2;\r
+ vuint32_t CFS3:2;\r
+ vuint32_t CFS4:2;\r
+ vuint32_t CFS5:2;\r
+ vuint32_t:5;\r
+ vuint32_t LCFTCB0:4;\r
+ vuint32_t TC_LCFTCB0:11;\r
+ } B;\r
+ } CFSSR0; /* CFIFO Status Register 0 */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CFS0:2;\r
+ vuint32_t CFS1:2;\r
+ vuint32_t CFS2:2;\r
+ vuint32_t CFS3:2;\r
+ vuint32_t CFS4:2;\r
+ vuint32_t CFS5:2;\r
+ vuint32_t:5;\r
+ vuint32_t LCFTCB1:4;\r
+ vuint32_t TC_LCFTCB1:11;\r
+ } B;\r
+ } CFSSR1; /* CFIFO Status Register 1 */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CFS0:2;\r
+ vuint32_t CFS1:2;\r
+ vuint32_t CFS2:2;\r
+ vuint32_t CFS3:2;\r
+ vuint32_t CFS4:2;\r
+ vuint32_t CFS5:2;\r
+ vuint32_t:4;\r
+ vuint32_t ECBNI:1;\r
+ vuint32_t LCFTSSI:4;\r
+ vuint32_t TC_LCFTSSI:11;\r
+ } B;\r
+ } CFSSR2; /* CFIFO Status Register 2 */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CFS0:2;\r
+ vuint32_t CFS1:2;\r
+ vuint32_t CFS2:2;\r
+ vuint32_t CFS3:2;\r
+ vuint32_t CFS4:2;\r
+ vuint32_t CFS5:2;\r
+ vuint32_t:20;\r
+ } B;\r
+ } CFSR;\r
+\r
+ uint32_t eqadc_reserved11;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:21;\r
+ vuint32_t MDT:3;\r
+ vuint32_t:4;\r
+ vuint32_t BR:4;\r
+ } B;\r
+ } SSICR; /* SSI Control Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t RDV:1;\r
+ vuint32_t:5;\r
+ vuint32_t RDATA:26;\r
+ } B;\r
+ } SSIRDR; /* SSI Recieve Data Register */\r
+\r
+ uint32_t eqadc_reserved12[17];\r
+\r
+ struct {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:32;\r
+ } B;\r
+ } R[4];\r
+\r
+ uint32_t eqadc_reserved13[12];\r
+\r
+ } CF[6];\r
+\r
+ uint32_t eqadc_reserved14[32];\r
+\r
+ struct {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:32;\r
+ } B;\r
+ } R[4];\r
+\r
+ uint32_t eqadc_reserved15[12];\r
+\r
+ } RF[6];\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : DSPI */\r
+/****************************************************************************/\r
+ struct DSPI_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MSTR:1;\r
+ vuint32_t CONT_SCKE:1;\r
+ vuint32_t DCONF:2;\r
+ vuint32_t FRZ:1;\r
+ vuint32_t MTFE:1;\r
+ vuint32_t PCSSE:1;\r
+ vuint32_t ROOE:1;\r
+ vuint32_t:2;\r
+ vuint32_t PCSIS5:1;\r
+ vuint32_t PCSIS4:1;\r
+ vuint32_t PCSIS3:1;\r
+ vuint32_t PCSIS2:1;\r
+ vuint32_t PCSIS1:1;\r
+ vuint32_t PCSIS0:1;\r
+ vuint32_t DOZE:1;\r
+ vuint32_t MDIS:1;\r
+ vuint32_t DIS_TXF:1;\r
+ vuint32_t DIS_RXF:1;\r
+ vuint32_t CLR_TXF:1;\r
+ vuint32_t CLR_RXF:1;\r
+ vuint32_t SMPL_PT:2;\r
+ vuint32_t:7;\r
+ vuint32_t HALT:1;\r
+ } B;\r
+ } MCR; /* Module Configuration Register */\r
+\r
+ uint32_t dspi_reserved1;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TCNT:16;\r
+ vuint32_t:16;\r
+ } B;\r
+ } TCR;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DBR:1;\r
+ vuint32_t FMSZ:4;\r
+ vuint32_t CPOL:1;\r
+ vuint32_t CPHA:1;\r
+ vuint32_t LSBFE:1;\r
+ vuint32_t PCSSCK:2;\r
+ vuint32_t PASC:2;\r
+ vuint32_t PDT:2;\r
+ vuint32_t PBR:2;\r
+ vuint32_t CSSCK:4;\r
+ vuint32_t ASC:4;\r
+ vuint32_t DT:4;\r
+ vuint32_t BR:4;\r
+ } B;\r
+ } CTAR[8]; /* Clock and Transfer Attributes Registers */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TCF:1;\r
+ vuint32_t TXRXS:1;\r
+ vuint32_t:1;\r
+ vuint32_t EOQF:1;\r
+ vuint32_t TFUF:1;\r
+ vuint32_t:1;\r
+ vuint32_t TFFF:1;\r
+ vuint32_t:5;\r
+ vuint32_t RFOF:1;\r
+ vuint32_t:1;\r
+ vuint32_t RFDF:1;\r
+ vuint32_t:1;\r
+ vuint32_t TXCTR:4;\r
+ vuint32_t TXNXTPTR:4;\r
+ vuint32_t RXCTR:4;\r
+ vuint32_t POPNXTPTR:4;\r
+ } B;\r
+ } SR; /* Status Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TCFRE:1;\r
+ vuint32_t:2;\r
+ vuint32_t EOQFRE:1;\r
+ vuint32_t TFUFRE:1;\r
+ vuint32_t:1;\r
+ vuint32_t TFFFRE:1;\r
+ vuint32_t TFFFDIRS:1;\r
+ vuint32_t:4;\r
+ vuint32_t RFOFRE:1;\r
+ vuint32_t:1;\r
+ vuint32_t RFDFRE:1;\r
+ vuint32_t RFDFDIRS:1;\r
+ vuint32_t:16;\r
+ } B;\r
+ } RSER; /* DMA/Interrupt Request Select and Enable Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CONT:1;\r
+ vuint32_t CTAS:3;\r
+ vuint32_t EOQ:1;\r
+ vuint32_t CTCNT:1;\r
+ vuint32_t:4;\r
+ vuint32_t PCS5:1;\r
+ vuint32_t PCS4:1;\r
+ vuint32_t PCS3:1;\r
+ vuint32_t PCS2:1;\r
+ vuint32_t PCS1:1;\r
+ vuint32_t PCS0:1;\r
+ vuint32_t TXDATA:16;\r
+ } B;\r
+ } PUSHR; /* PUSH TX FIFO Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t RXDATA:16;\r
+ } B;\r
+ } POPR; /* POP RX FIFO Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TXCMD:16;\r
+ vuint32_t TXDATA:16;\r
+ } B;\r
+ } TXFR[4]; /* Transmit FIFO Registers */\r
+\r
+ vuint32_t DSPI_reserved_txf[12];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t RXDATA:16;\r
+ } B;\r
+ } RXFR[4]; /* Transmit FIFO Registers */\r
+\r
+ vuint32_t DSPI_reserved_rxf[12];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MTOE:1;\r
+ vuint32_t:1;\r
+ vuint32_t MTOCNT:6;\r
+ vuint32_t:4;\r
+ vuint32_t TXSS:1;\r
+ vuint32_t TPOL:1;\r
+ vuint32_t TRRE:1;\r
+ vuint32_t CID:1;\r
+ vuint32_t DCONT:1;\r
+ vuint32_t DSICTAS:3;\r
+ vuint32_t:6;\r
+ vuint32_t DPCS5:1;\r
+ vuint32_t DPCS4:1;\r
+ vuint32_t DPCS3:1;\r
+ vuint32_t DPCS2:1;\r
+ vuint32_t DPCS1:1;\r
+ vuint32_t DPCS0:1;\r
+ } B;\r
+ } DSICR; /* DSI Configuration Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t SER_DATA:16;\r
+ } B;\r
+ } SDR; /* DSI Serialization Data Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t ASER_DATA:16;\r
+ } B;\r
+ } ASDR; /* DSI Alternate Serialization Data Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t COMP_DATA:16;\r
+ } B;\r
+ } COMPR; /* DSI Transmit Comparison Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t DESER_DATA:16;\r
+ } B;\r
+ } DDR; /* DSI deserialization Data Register */\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : eSCI */\r
+/****************************************************************************/\r
+ struct ESCI_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:3;\r
+ vuint32_t SBR:13;\r
+ vuint32_t LOOPS:1;\r
+ vuint32_t SCISDOZ:1;\r
+ vuint32_t RSRC:1;\r
+ vuint32_t M:1;\r
+ vuint32_t WAKE:1;\r
+ vuint32_t ILT:1;\r
+ vuint32_t PE:1;\r
+ vuint32_t PT:1;\r
+ vuint32_t TIE:1;\r
+ vuint32_t TCIE:1;\r
+ vuint32_t RIE:1;\r
+ vuint32_t ILIE:1;\r
+ vuint32_t TE:1;\r
+ vuint32_t RE:1;\r
+ vuint32_t RWU:1;\r
+ vuint32_t SBK:1;\r
+ } B;\r
+ } CR1; /* Control Register 1 */\r
+\r
+ union {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t MDIS:1;\r
+ vuint16_t FBR:1;\r
+ vuint16_t BSTP:1;\r
+ vuint16_t IEBERR:1;\r
+ vuint16_t RXDMA:1;\r
+ vuint16_t TXDMA:1;\r
+ vuint16_t BRK13:1;\r
+ vuint16_t:1;\r
+ vuint16_t BESM13:1;\r
+ vuint16_t SBSTP:1;\r
+ vuint16_t:2;\r
+ vuint16_t ORIE:1;\r
+ vuint16_t NFIE:1;\r
+ vuint16_t FEIE:1;\r
+ vuint16_t PFIE:1;\r
+ } B;\r
+ } CR2; /* Control Register 2 */\r
+\r
+ union {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t R8:1;\r
+ vuint16_t T8:1;\r
+ vuint16_t:6;\r
+ vuint8_t D;\r
+ } B;\r
+ } DR; /* Data Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TDRE:1;\r
+ vuint32_t TC:1;\r
+ vuint32_t RDRF:1;\r
+ vuint32_t IDLE:1;\r
+ vuint32_t OR:1;\r
+ vuint32_t NF:1;\r
+ vuint32_t FE:1;\r
+ vuint32_t PF:1;\r
+ vuint32_t:3;\r
+ vuint32_t BERR:1;\r
+ vuint32_t:3;\r
+ vuint32_t RAF:1;\r
+ vuint32_t RXRDY:1;\r
+ vuint32_t TXRDY:1;\r
+ vuint32_t LWAKE:1;\r
+ vuint32_t STO:1;\r
+ vuint32_t PBERR:1;\r
+ vuint32_t CERR:1;\r
+ vuint32_t CKERR:1;\r
+ vuint32_t FRC:1;\r
+ vuint32_t:7;\r
+ vuint32_t OVFL:1;\r
+ } B;\r
+ } SR; /* Status Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t LRES:1;\r
+ vuint32_t WU:1;\r
+ vuint32_t WUD0:1;\r
+ vuint32_t WUD1:1;\r
+ vuint32_t LDBG:1;\r
+ vuint32_t DSF:1;\r
+ vuint32_t PRTY:1;\r
+ vuint32_t LIN:1;\r
+ vuint32_t RXIE:1;\r
+ vuint32_t TXIE:1;\r
+ vuint32_t WUIE:1;\r
+ vuint32_t STIE:1;\r
+ vuint32_t PBIE:1;\r
+ vuint32_t CIE:1;\r
+ vuint32_t CKIE:1;\r
+ vuint32_t FCIE:1;\r
+ vuint32_t:7;\r
+ vuint32_t OFIE:1;\r
+ vuint32_t:8;\r
+ } B;\r
+ } LCR; /* LIN Control Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } LTR; /* LIN Transmit Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } LRR; /* LIN Recieve Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } LPR; /* LIN CRC Polynom Register */\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : FlexCAN */\r
+/****************************************************************************/\r
+ struct FLEXCAN2_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MDIS:1;\r
+ vuint32_t FRZ:1;\r
+ vuint32_t:1;\r
+ vuint32_t HALT:1;\r
+ vuint32_t NOTRDY:1;\r
+ vuint32_t:1;\r
+ vuint32_t SOFTRST:1;\r
+ vuint32_t FRZACK:1;\r
+ vuint32_t:1;\r
+ vuint32_t:1;\r
+\r
+ vuint32_t:1;\r
+\r
+ vuint32_t MDISACK:1;\r
+ vuint32_t:1;\r
+ vuint32_t:1;\r
+\r
+ vuint32_t:12;\r
+\r
+ vuint32_t MAXMB:6;\r
+ } B;\r
+ } MCR; /* Module Configuration Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PRESDIV:8;\r
+ vuint32_t RJW:2;\r
+ vuint32_t PSEG1:3;\r
+ vuint32_t PSEG2:3;\r
+ vuint32_t BOFFMSK:1;\r
+ vuint32_t ERRMSK:1;\r
+ vuint32_t CLKSRC:1;\r
+ vuint32_t LPB:1;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t SMP:1;\r
+ vuint32_t BOFFREC:1;\r
+ vuint32_t TSYN:1;\r
+ vuint32_t LBUF:1;\r
+ vuint32_t LOM:1;\r
+ vuint32_t PROPSEG:3;\r
+ } B;\r
+ } CR; /* Control Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } TIMER; /* Free Running Timer */\r
+ int32_t FLEXCAN_reserved00;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:3;\r
+ vuint32_t MI:29;\r
+ } B;\r
+ } RXGMASK; /* RX Global Mask */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:3;\r
+ vuint32_t MI:29;\r
+ } B;\r
+ } RX14MASK; /* RX 14 Mask */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:3;\r
+ vuint32_t MI:29;\r
+ } B;\r
+ } RX15MASK; /* RX 15 Mask */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t RXECNT:8;\r
+ vuint32_t TXECNT:8;\r
+ } B;\r
+ } ECR; /* Error Counter Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:14;\r
+\r
+ vuint32_t:2;\r
+\r
+ vuint32_t BIT1ERR:1;\r
+ vuint32_t BIT0ERR:1;\r
+ vuint32_t ACKERR:1;\r
+ vuint32_t CRCERR:1;\r
+ vuint32_t FRMERR:1;\r
+ vuint32_t STFERR:1;\r
+ vuint32_t TXWRN:1;\r
+ vuint32_t RXWRN:1;\r
+ vuint32_t IDLE:1;\r
+ vuint32_t TXRX:1;\r
+ vuint32_t FLTCONF:2;\r
+ vuint32_t:1;\r
+ vuint32_t BOFFINT:1;\r
+ vuint32_t ERRINT:1;\r
+ vuint32_t:1;\r
+ } B;\r
+ } ESR; /* Error and Status Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BUF63M:1;\r
+ vuint32_t BUF62M:1;\r
+ vuint32_t BUF61M:1;\r
+ vuint32_t BUF60M:1;\r
+ vuint32_t BUF59M:1;\r
+ vuint32_t BUF58M:1;\r
+ vuint32_t BUF57M:1;\r
+ vuint32_t BUF56M:1;\r
+ vuint32_t BUF55M:1;\r
+ vuint32_t BUF54M:1;\r
+ vuint32_t BUF53M:1;\r
+ vuint32_t BUF52M:1;\r
+ vuint32_t BUF51M:1;\r
+ vuint32_t BUF50M:1;\r
+ vuint32_t BUF49M:1;\r
+ vuint32_t BUF48M:1;\r
+ vuint32_t BUF47M:1;\r
+ vuint32_t BUF46M:1;\r
+ vuint32_t BUF45M:1;\r
+ vuint32_t BUF44M:1;\r
+ vuint32_t BUF43M:1;\r
+ vuint32_t BUF42M:1;\r
+ vuint32_t BUF41M:1;\r
+ vuint32_t BUF40M:1;\r
+ vuint32_t BUF39M:1;\r
+ vuint32_t BUF38M:1;\r
+ vuint32_t BUF37M:1;\r
+ vuint32_t BUF36M:1;\r
+ vuint32_t BUF35M:1;\r
+ vuint32_t BUF34M:1;\r
+ vuint32_t BUF33M:1;\r
+ vuint32_t BUF32M:1;\r
+ } B;\r
+ } IMRH; /* Interruput Masks Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BUF31M:1;\r
+ vuint32_t BUF30M:1;\r
+ vuint32_t BUF29M:1;\r
+ vuint32_t BUF28M:1;\r
+ vuint32_t BUF27M:1;\r
+ vuint32_t BUF26M:1;\r
+ vuint32_t BUF25M:1;\r
+ vuint32_t BUF24M:1;\r
+ vuint32_t BUF23M:1;\r
+ vuint32_t BUF22M:1;\r
+ vuint32_t BUF21M:1;\r
+ vuint32_t BUF20M:1;\r
+ vuint32_t BUF19M:1;\r
+ vuint32_t BUF18M:1;\r
+ vuint32_t BUF17M:1;\r
+ vuint32_t BUF16M:1;\r
+ vuint32_t BUF15M:1;\r
+ vuint32_t BUF14M:1;\r
+ vuint32_t BUF13M:1;\r
+ vuint32_t BUF12M:1;\r
+ vuint32_t BUF11M:1;\r
+ vuint32_t BUF10M:1;\r
+ vuint32_t BUF09M:1;\r
+ vuint32_t BUF08M:1;\r
+ vuint32_t BUF07M:1;\r
+ vuint32_t BUF06M:1;\r
+ vuint32_t BUF05M:1;\r
+ vuint32_t BUF04M:1;\r
+ vuint32_t BUF03M:1;\r
+ vuint32_t BUF02M:1;\r
+ vuint32_t BUF01M:1;\r
+ vuint32_t BUF00M:1;\r
+ } B;\r
+ } IMRL; /* Interruput Masks Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BUF63I:1;\r
+ vuint32_t BUF62I:1;\r
+ vuint32_t BUF61I:1;\r
+ vuint32_t BUF60I:1;\r
+ vuint32_t BUF59I:1;\r
+ vuint32_t BUF58I:1;\r
+ vuint32_t BUF57I:1;\r
+ vuint32_t BUF56I:1;\r
+ vuint32_t BUF55I:1;\r
+ vuint32_t BUF54I:1;\r
+ vuint32_t BUF53I:1;\r
+ vuint32_t BUF52I:1;\r
+ vuint32_t BUF51I:1;\r
+ vuint32_t BUF50I:1;\r
+ vuint32_t BUF49I:1;\r
+ vuint32_t BUF48I:1;\r
+ vuint32_t BUF47I:1;\r
+ vuint32_t BUF46I:1;\r
+ vuint32_t BUF45I:1;\r
+ vuint32_t BUF44I:1;\r
+ vuint32_t BUF43I:1;\r
+ vuint32_t BUF42I:1;\r
+ vuint32_t BUF41I:1;\r
+ vuint32_t BUF40I:1;\r
+ vuint32_t BUF39I:1;\r
+ vuint32_t BUF38I:1;\r
+ vuint32_t BUF37I:1;\r
+ vuint32_t BUF36I:1;\r
+ vuint32_t BUF35I:1;\r
+ vuint32_t BUF34I:1;\r
+ vuint32_t BUF33I:1;\r
+ vuint32_t BUF32I:1;\r
+ } B;\r
+ } IFRH; /* Interruput Flag Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BUF31I:1;\r
+ vuint32_t BUF30I:1;\r
+ vuint32_t BUF29I:1;\r
+ vuint32_t BUF28I:1;\r
+ vuint32_t BUF27I:1;\r
+ vuint32_t BUF26I:1;\r
+ vuint32_t BUF25I:1;\r
+ vuint32_t BUF24I:1;\r
+ vuint32_t BUF23I:1;\r
+ vuint32_t BUF22I:1;\r
+ vuint32_t BUF21I:1;\r
+ vuint32_t BUF20I:1;\r
+ vuint32_t BUF19I:1;\r
+ vuint32_t BUF18I:1;\r
+ vuint32_t BUF17I:1;\r
+ vuint32_t BUF16I:1;\r
+ vuint32_t BUF15I:1;\r
+ vuint32_t BUF14I:1;\r
+ vuint32_t BUF13I:1;\r
+ vuint32_t BUF12I:1;\r
+ vuint32_t BUF11I:1;\r
+ vuint32_t BUF10I:1;\r
+ vuint32_t BUF09I:1;\r
+ vuint32_t BUF08I:1;\r
+ vuint32_t BUF07I:1;\r
+ vuint32_t BUF06I:1;\r
+ vuint32_t BUF05I:1;\r
+ vuint32_t BUF04I:1;\r
+ vuint32_t BUF03I:1;\r
+ vuint32_t BUF02I:1;\r
+ vuint32_t BUF01I:1;\r
+ vuint32_t BUF00I:1;\r
+ } B;\r
+ } IFRL; /* Interruput Flag Register */\r
+\r
+ uint32_t flexcan2_reserved2[19];\r
+\r
+ struct canbuf_t {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:4;\r
+ vuint32_t CODE:4;\r
+ vuint32_t:1;\r
+ vuint32_t SRR:1;\r
+ vuint32_t IDE:1;\r
+ vuint32_t RTR:1;\r
+ vuint32_t LENGTH:4;\r
+ vuint32_t TIMESTAMP:16;\r
+ } B;\r
+ } CS;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:3;\r
+ vuint32_t STD_ID:11;\r
+ vuint32_t EXT_ID:18;\r
+ } B;\r
+ } ID;\r
+\r
+ union {\r
+ vuint8_t B[8]; /* Data buffer in Bytes (8 bits) */\r
+ vuint16_t H[4]; /* Data buffer in Half-words (16 bits) */\r
+ vuint32_t W[2]; /* Data buffer in words (32 bits) */\r
+ vuint32_t R[2]; /* Data buffer in words (32 bits) */\r
+ } DATA;\r
+\r
+ } BUF[64];\r
+ };\r
+\r
+/* Define memories */\r
+\r
+#define SRAM_START 0x40000000\r
+#define SRAM_SIZE 0x10000\r
+#define SRAM_END 0x4000FFFF\r
+\r
+#define FLASH_START 0x0\r
+#define FLASH_SIZE 0x200000\r
+#define FLASH_END 0x1FFFFF\r
+\r
+/* Define instances of modules */\r
+#define PBRIDGE_A (*( struct PBRIDGE_A_tag *) 0xC3F00000)\r
+#define FMPLL (*( struct FMPLL_tag *) 0xC3F80000)\r
+#define EBI (*( struct EBI_tag *) 0xC3F84000)\r
+#define FLASH (*( struct FLASH_tag *) 0xC3F88000)\r
+#define SIU (*( struct SIU_tag *) 0xC3F90000)\r
+\r
+#define EMIOS (*( struct EMIOS_tag *) 0xC3FA0000)\r
+#define ETPU (*( struct ETPU_tag *) 0xC3FC0000)\r
+#define ETPU_DATA_RAM (*( uint32_t *) 0xC3FC8000)\r
+#define ETPU_DATA_RAM_EXT (*( uint32_t *) 0xC3FCC000)\r
+#define ETPU_DATA_RAM_END 0xC3FC8BFC\r
+#define CODE_RAM (*( uint32_t *) 0xC3FD0000)\r
+#define ETPU_CODE_RAM (*( uint32_t *) 0xC3FD0000)\r
+\r
+#define PBRIDGE_B (*( struct PBRIDGE_B_tag *) 0xFFF00000)\r
+#define XBAR (*( struct XBAR_tag *) 0xFFF04000)\r
+#define ECSM (*( struct ECSM_tag *) 0xFFF40000)\r
+#define EDMA (*( struct EDMA_tag *) 0xFFF44000)\r
+#define INTC (*( struct INTC_tag *) 0xFFF48000)\r
+\r
+#define EQADC (*( struct EQADC_tag *) 0xFFF80000)\r
+\r
+#define DSPI_A (*( struct DSPI_tag *) 0xFFF90000)\r
+#define DSPI_B (*( struct DSPI_tag *) 0xFFF94000)\r
+#define DSPI_C (*( struct DSPI_tag *) 0xFFF98000)\r
+#define DSPI_D (*( struct DSPI_tag *) 0xFFF9C000)\r
+\r
+#define ESCI_A (*( struct ESCI_tag *) 0xFFFB0000)\r
+#define ESCI_B (*( struct ESCI_tag *) 0xFFFB4000)\r
+\r
+#define CAN_A (*( struct FLEXCAN2_tag *) 0xFFFC0000)\r
+#define CAN_B (*( struct FLEXCAN2_tag *) 0xFFFC4000)\r
+#define CAN_C (*( struct FLEXCAN2_tag *) 0xFFFC8000)\r
+\r
+#ifdef __MWERKS__\r
+#pragma pop\r
+#endif\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+#endif /* ifdef _MPC5554_H */\r
+/*********************************************************************\r
+ *\r
+ * Copyright:\r
+ * Freescale Semiconductor, INC. All Rights Reserved.\r
+ * You are hereby granted a copyright license to use, modify, and\r
+ * distribute the SOFTWARE so long as this entire notice is\r
+ * retained without alteration in any modified and/or redistributed\r
+ * versions, and that such modified versions are clearly identified\r
+ * as such. No licenses are granted by implication, estoppel or\r
+ * otherwise under any patents or trademarks of Freescale\r
+ * Semiconductor, Inc. This software is provided on an "AS IS"\r
+ * basis and without warranty.\r
+ *\r
+ * To the maximum extent permitted by applicable law, Freescale\r
+ * Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,\r
+ * INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A\r
+ * PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH\r
+ * REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF)\r
+ * AND ANY ACCOMPANYING WRITTEN MATERIALS.\r
+ *\r
+ * To the maximum extent permitted by applicable law, IN NO EVENT\r
+ * SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER\r
+ * (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,\r
+ * BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER\r
+ * PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.\r
+ *\r
+ * Freescale Semiconductor assumes no responsibility for the\r
+ * maintenance and support of this software\r
+ *\r
+ ********************************************************************/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/**************************************************************************\r
+ * FILE NAME: $RCSfile: mpc5554_vars.h,v $ COPYRIGHT (c) Freescale 2004 *\r
+ * DESCRIPTION: All Rights Reserved *\r
+ * Variables that define some features of the MPC5554. *\r
+ * !!!!This file must only be included once in every project!!!! *\r
+ *========================================================================*\r
+ * ORIGINAL AUTHOR: Jeff Loeliger [r12110] *\r
+ * $Log: mpc5554_vars.h,v $\r
+ * Revision 1.1 2004/12/02 13:45:26 r12110\r
+ * -First version of file.\r
+ *\r
+ **************************************************************************/\r
+\r
+/* eTPU characteristics definition */\r
+struct eTPU_struct *eTPU = (struct eTPU_struct *)0xC3FC0000;\r
+\r
+uint32_t fs_etpu_code_start = 0xC3FD0000;\r
+uint32_t fs_etpu_data_ram_start = 0xC3FC8000;\r
+uint32_t fs_etpu_data_ram_end = 0xC3FC8BFC;\r
+uint32_t fs_etpu_data_ram_ext = 0xC3FCC000;\r
+\r
+/*********************************************************************\r
+ *\r
+ * Copyright:\r
+ * Freescale Semiconductor, INC. All Rights Reserved.\r
+ * You are hereby granted a copyright license to use, modify, and\r
+ * distribute the SOFTWARE so long as this entire notice is\r
+ * retained without alteration in any modified and/or redistributed\r
+ * versions, and that such modified versions are clearly identified\r
+ * as such. No licenses are granted by implication, estoppel or\r
+ * otherwise under any patents or trademarks of Freescale\r
+ * Semiconductor, Inc. This software is provided on an "AS IS"\r
+ * basis and without warranty.\r
+ *\r
+ * To the maximum extent permitted by applicable law, Freescale\r
+ * Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,\r
+ * INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A\r
+ * PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH\r
+ * REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF)\r
+ * AND ANY ACCOMPANYING WRITTEN MATERIALS.\r
+ *\r
+ * To the maximum extent permitted by applicable law, IN NO EVENT\r
+ * SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER\r
+ * (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,\r
+ * BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER\r
+ * PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.\r
+ *\r
+ * Freescale Semiconductor assumes no responsibility for the\r
+ * maintenance and support of this software\r
+ *\r
+ ********************************************************************/\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/**************************************************************************/\r
+/* FILE NAME: mpc5567.h COPYRIGHT (c) Freescale 2007 */\r
+/* VERSION: 1.6 All Rights Reserved */\r
+/* */\r
+/* DESCRIPTION: */\r
+/* This file contain all of the register and bit field definitions for */\r
+/* MPC5567. */\r
+/*========================================================================*/\r
+/* UPDATE HISTORY */\r
+/* REV AUTHOR DATE DESCRIPTION OF CHANGE */\r
+/* --- ----------- --------- --------------------- */\r
+/* 1.0 G. Emerson 03/Jan/06 Initial version. */\r
+/* 1.1 G. Emerson 27/Mar/06 Fix issue with Flexcan BCC field. */\r
+/* 1.2 S. Mathieson 28/Jul/06 Change Flexcan BCC bit to MBFEN */\r
+/* Add Flexcan bits WRNEN, SRXDIS, */\r
+/* TWRNMSK, RWRNMSK,TWRNINT,RWRNINT */\r
+/* 1.3 S. Mathieson 30/Aug/06 SPR: L1SCR0, updated bit name from DPP */\r
+/* to DPB to align with documentation. */\r
+/* 1.4 S. Mathieson 26/Feb/07 eDMA TCD format updated to include */\r
+/* alternate configuration. */\r
+/* INTC, correction to the number of PSR */\r
+/* registers. */\r
+/* Updates to bitfield sizes in MBSSUTR, */\r
+/* MBIVEC, MBIDX & RSBIR. RSBIR, SELEC */\r
+/* changed to SEL & RFRFCFR, FNUM changed */\r
+/* to SEL to align with documentation. */\r
+/* Various register/ bitfield updates to */\r
+/* correct errors (MCR, TMODE bit removed.*/\r
+/* PADR register removed. PIER1, DRDIE bit*/\r
+/* removed & PIFR1, DRDIF removed. PCR1, */\r
+/* Filter bypass bit removed). */\r
+/* 1.5 S. Mathieson 25/Apr/07 SRAM size changed from 64K to 80K. */\r
+/* */\r
+/* 1.6 G. Emerson 26/Oct/07 All module instantiations now volatile */\r
+/* All registers/bit fields now volatile */\r
+/**************************************************************************/\r
+/*>>>>NOTE! this file is auto-generated please do not edit it!<<<<*/\r
+\r
+#ifndef _MPC5567_H_\r
+#define _MPC5567_H_\r
+\r
+#include "typedefs.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+#ifdef __MWERKS__\r
+#pragma push\r
+#pragma ANSI_strict off\r
+#endif\r
+\r
+/****************************************************************************/\r
+/* MODULE : PBRIDGE_A Peripheral Bridge */\r
+/****************************************************************************/\r
+ struct PBRIDGE_A_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MBW0:1;\r
+ vuint32_t MTR0:1;\r
+ vuint32_t MTW0:1;\r
+ vuint32_t MPL0:1;\r
+ vuint32_t MBW1:1;\r
+ vuint32_t MTR1:1;\r
+ vuint32_t MTW1:1;\r
+ vuint32_t MPL1:1;\r
+ vuint32_t MBW2:1;\r
+ vuint32_t MTR2:1;\r
+ vuint32_t MTW2:1;\r
+ vuint32_t MPL2:1;\r
+ vuint32_t MBW3:1;\r
+ vuint32_t MTR3:1;\r
+ vuint32_t MTW3:1;\r
+ vuint32_t MPL3:1;\r
+\r
+ vuint32_t MBW4:1; /* FEC */\r
+ vuint32_t MTR4:1;\r
+ vuint32_t MTW4:1;\r
+ vuint32_t MPL4:1;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t MBW6:1; /* FLEXRAY */\r
+ vuint32_t MTR6:1;\r
+ vuint32_t MTW6:1;\r
+ vuint32_t MPL6:1;\r
+\r
+ vuint32_t:4;\r
+ } B;\r
+ } MPCR; /* Master Privilege Control Register */\r
+\r
+ uint32_t pbridge_a_reserved2[7];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BW0:1;\r
+ vuint32_t SP0:1;\r
+ vuint32_t WP0:1;\r
+ vuint32_t TP0:1;\r
+ vuint32_t:28;\r
+ } B;\r
+ } PACR0;\r
+\r
+ uint32_t pbridge_a_reserved3[7];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BW0:1;\r
+ vuint32_t SP0:1;\r
+ vuint32_t WP0:1;\r
+ vuint32_t TP0:1;\r
+ vuint32_t BW1:1;\r
+ vuint32_t SP1:1;\r
+ vuint32_t WP1:1;\r
+ vuint32_t TP1:1;\r
+ vuint32_t BW2:1;\r
+ vuint32_t SP2:1;\r
+ vuint32_t WP2:1;\r
+ vuint32_t TP2:1;\r
+ vuint32_t:4;\r
+ vuint32_t BW4:1;\r
+ vuint32_t SP4:1;\r
+ vuint32_t WP4:1;\r
+ vuint32_t TP4:1;\r
+ vuint32_t:12;\r
+ } B;\r
+ } OPACR0;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+\r
+ vuint32_t BW0:1; /* EMIOS */\r
+ vuint32_t SP0:1;\r
+ vuint32_t WP0:1;\r
+ vuint32_t TP0:1;\r
+\r
+ vuint32_t:28;\r
+ } B;\r
+ } OPACR1;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BW0:1;\r
+ vuint32_t SP0:1;\r
+ vuint32_t WP0:1;\r
+ vuint32_t TP0:1;\r
+ vuint32_t:4;\r
+ vuint32_t BW2:1;\r
+ vuint32_t SP2:1;\r
+ vuint32_t WP2:1;\r
+ vuint32_t TP2:1;\r
+ vuint32_t BW3:1;\r
+ vuint32_t SP3:1;\r
+ vuint32_t WP3:1;\r
+ vuint32_t TP3:1;\r
+ vuint32_t BW4:1;\r
+ vuint32_t SP4:1;\r
+ vuint32_t WP4:1;\r
+ vuint32_t TP4:1;\r
+ vuint32_t:12;\r
+ } B;\r
+ } OPACR2;\r
+\r
+ };\r
+\r
+/****************************************************************************/\r
+/* MODULE : PBRIDGE_B Peripheral Bridge */\r
+/****************************************************************************/\r
+ struct PBRIDGE_B_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MBW0:1;\r
+ vuint32_t MTR0:1;\r
+ vuint32_t MTW0:1;\r
+ vuint32_t MPL0:1;\r
+ vuint32_t MBW1:1;\r
+ vuint32_t MTR1:1;\r
+ vuint32_t MTW1:1;\r
+ vuint32_t MPL1:1;\r
+ vuint32_t MBW2:1;\r
+ vuint32_t MTR2:1;\r
+ vuint32_t MTW2:1;\r
+ vuint32_t MPL2:1;\r
+ vuint32_t MBW3:1;\r
+ vuint32_t MTR3:1;\r
+ vuint32_t MTW3:1;\r
+ vuint32_t MPL3:1;\r
+\r
+ vuint32_t MBW4:1; /* FEC */\r
+ vuint32_t MTR4:1;\r
+ vuint32_t MTW4:1;\r
+ vuint32_t MPL4:1;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t MBW6:1; /* FLEXRAY */\r
+ vuint32_t MTR6:1;\r
+ vuint32_t MTW6:1;\r
+ vuint32_t MPL6:1;\r
+\r
+ vuint32_t:4;\r
+ } B;\r
+ } MPCR; /* Master Privilege Control Register */\r
+\r
+ uint32_t pbridge_b_reserved2[7];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BW0:1;\r
+ vuint32_t SP0:1;\r
+ vuint32_t WP0:1;\r
+ vuint32_t TP0:1;\r
+ vuint32_t BW1:1;\r
+ vuint32_t SP1:1;\r
+ vuint32_t WP1:1;\r
+ vuint32_t TP1:1;\r
+ vuint32_t:24;\r
+ } B;\r
+ } PACR0;\r
+\r
+ uint32_t pbridge_b_reserved3;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BW0:1;\r
+ vuint32_t SP0:1;\r
+ vuint32_t WP0:1;\r
+ vuint32_t TP0:1;\r
+ vuint32_t BW1:1;\r
+ vuint32_t SP1:1;\r
+ vuint32_t WP1:1;\r
+ vuint32_t TP1:1;\r
+ vuint32_t BW2:1;\r
+ vuint32_t SP2:1;\r
+ vuint32_t WP2:1;\r
+ vuint32_t TP2:1;\r
+\r
+ vuint32_t BW3:1; /* FEC */\r
+ vuint32_t SP3:1;\r
+ vuint32_t WP3:1;\r
+ vuint32_t TP3:1;\r
+\r
+ vuint32_t:16;\r
+\r
+ } B;\r
+ } PACR2;\r
+\r
+ uint32_t pbridge_b_reserved4[5];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BW0:1;\r
+ vuint32_t SP0:1;\r
+ vuint32_t WP0:1;\r
+ vuint32_t TP0:1;\r
+ vuint32_t:12;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t BW5:1; /* DSPI_B */\r
+ vuint32_t SP5:1;\r
+ vuint32_t WP5:1;\r
+ vuint32_t TP5:1;\r
+\r
+ vuint32_t BW6:1;\r
+ vuint32_t SP6:1;\r
+ vuint32_t WP6:1;\r
+ vuint32_t TP6:1;\r
+ vuint32_t BW7:1;\r
+ vuint32_t SP7:1;\r
+ vuint32_t WP7:1;\r
+ vuint32_t TP7:1;\r
+ } B;\r
+ } OPACR0;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t BW4:1;\r
+ vuint32_t SP4:1;\r
+ vuint32_t WP4:1;\r
+ vuint32_t TP4:1;\r
+\r
+ vuint32_t BW5:1; /* ESCI_B */\r
+ vuint32_t SP5:1;\r
+ vuint32_t WP5:1;\r
+ vuint32_t TP5:1;\r
+\r
+ vuint32_t:8;\r
+ } B;\r
+ } OPACR1;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BW0:1;\r
+ vuint32_t SP0:1;\r
+ vuint32_t WP0:1;\r
+ vuint32_t TP0:1;\r
+\r
+ vuint32_t BW1:1; /* CAN_B */\r
+ vuint32_t SP1:1;\r
+ vuint32_t WP1:1;\r
+ vuint32_t TP1:1;\r
+\r
+ vuint32_t BW2:1;\r
+ vuint32_t SP2:1;\r
+ vuint32_t WP2:1;\r
+ vuint32_t TP2:1;\r
+\r
+ vuint32_t BW3:1; /* CAN_D */\r
+ vuint32_t SP3:1;\r
+ vuint32_t WP3:1;\r
+ vuint32_t TP3:1;\r
+\r
+ vuint32_t BW4:1; /* CAN_E */\r
+ vuint32_t SP4:1;\r
+ vuint32_t WP4:1;\r
+ vuint32_t TP4:1;\r
+\r
+ vuint32_t:12;\r
+ } B;\r
+ } OPACR2;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+\r
+ vuint32_t BW0:1; /* FLEXRAY */\r
+ vuint32_t SP0:1;\r
+ vuint32_t WP0:1;\r
+ vuint32_t TP0:1;\r
+\r
+ vuint32_t:24;\r
+ vuint32_t BW7:1;\r
+ vuint32_t SP7:1;\r
+ vuint32_t WP7:1;\r
+ vuint32_t TP7:1;\r
+ } B;\r
+ } OPACR3;\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : FMPLL */\r
+/****************************************************************************/\r
+ struct FMPLL_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:1;\r
+ vuint32_t PREDIV:3;\r
+ vuint32_t MFD:5;\r
+ vuint32_t:1;\r
+ vuint32_t RFD:3;\r
+ vuint32_t LOCEN:1;\r
+ vuint32_t LOLRE:1;\r
+ vuint32_t LOCRE:1;\r
+ vuint32_t DISCLK:1;\r
+ vuint32_t LOLIRQ:1;\r
+ vuint32_t LOCIRQ:1;\r
+ vuint32_t RATE:1;\r
+ vuint32_t DEPTH:2;\r
+ vuint32_t EXP:10;\r
+ } B;\r
+ } SYNCR;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:22;\r
+ vuint32_t LOLF:1;\r
+ vuint32_t LOC:1;\r
+ vuint32_t MODE:1;\r
+ vuint32_t PLLSEL:1;\r
+ vuint32_t PLLREF:1;\r
+ vuint32_t LOCKS:1;\r
+ vuint32_t LOCK:1;\r
+ vuint32_t LOCF:1;\r
+ vuint32_t CALDONE:1;\r
+ vuint32_t CALPASS:1;\r
+ } B;\r
+ } SYNSR;\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : External Bus Interface (EBI) */\r
+/****************************************************************************/\r
+ struct CS_tag {\r
+ union { /* Base Register Bank */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BA:17;\r
+ vuint32_t:3;\r
+ vuint32_t PS:1;\r
+ vuint32_t:4;\r
+ vuint32_t BL:1;\r
+ vuint32_t WEBS:1;\r
+ vuint32_t TBDIP:1;\r
+ vuint32_t:2;\r
+ vuint32_t BI:1;\r
+ vuint32_t V:1;\r
+ } B;\r
+ } BR;\r
+\r
+ union { /* Option Register Bank */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t AM:17;\r
+ vuint32_t:7;\r
+ vuint32_t SCY:4;\r
+ vuint32_t:1;\r
+ vuint32_t BSCY:2;\r
+ vuint32_t:1;\r
+ } B;\r
+ } OR;\r
+ };\r
+\r
+ struct CAL_CS_tag {\r
+ union { /* Calibration Base Register Bank */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BA:17;\r
+ vuint32_t:3;\r
+ vuint32_t PS:1;\r
+ vuint32_t:4;\r
+ vuint32_t BL:1;\r
+ vuint32_t WEBS:1;\r
+ vuint32_t TBDIP:1;\r
+ vuint32_t:2;\r
+ vuint32_t BI:1;\r
+ vuint32_t V:1;\r
+ } B;\r
+ } BR;\r
+\r
+ union { /* Calibration Option Register Bank */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t AM:17;\r
+ vuint32_t:7;\r
+ vuint32_t SCY:4;\r
+ vuint32_t:1;\r
+ vuint32_t BSCY:2;\r
+ vuint32_t:1;\r
+ } B;\r
+ } OR;\r
+ };\r
+\r
+ struct EBI_tag {\r
+ union { /* Module Configuration Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:5;\r
+ vuint32_t SIZEEN:1;\r
+ vuint32_t SIZE:2;\r
+ vuint32_t:8;\r
+ vuint32_t ACGE:1;\r
+ vuint32_t EXTM:1;\r
+ vuint32_t EARB:1;\r
+ vuint32_t EARP:2;\r
+ vuint32_t:4;\r
+ vuint32_t MDIS:1;\r
+ vuint32_t:5;\r
+ vuint32_t DBM:1;\r
+ } B;\r
+ } MCR;\r
+\r
+ uint32_t EBI_reserved1;\r
+\r
+ union { /* Transfer Error Status Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:30;\r
+ vuint32_t TEAF:1;\r
+ vuint32_t BMTF:1;\r
+ } B;\r
+ } TESR;\r
+\r
+ union { /* Bus Monitor Control Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t BMT:8;\r
+ vuint32_t BME:1;\r
+ vuint32_t:7;\r
+ } B;\r
+ } BMCR;\r
+\r
+ struct CS_tag CS[4];\r
+\r
+/* Calibration registers */\r
+ uint32_t EBI_reserved2[4];\r
+ struct CAL_CS_tag CAL_CS[4];\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : FLASH */\r
+/****************************************************************************/\r
+ struct FLASH_tag {\r
+ union { /* Module Configuration Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:4;\r
+ vuint32_t SIZE:4;\r
+ vuint32_t:1;\r
+ vuint32_t LAS:3;\r
+ vuint32_t:3;\r
+ vuint32_t MAS:1;\r
+ vuint32_t EER:1;\r
+ vuint32_t RWE:1;\r
+ vuint32_t BBEPE:1;\r
+ vuint32_t EPE:1;\r
+ vuint32_t PEAS:1;\r
+ vuint32_t DONE:1;\r
+ vuint32_t PEG:1;\r
+\r
+ vuint32_t:2;\r
+\r
+ vuint32_t STOP:1;\r
+ vuint32_t:1;\r
+ vuint32_t PGM:1;\r
+ vuint32_t PSUS:1;\r
+ vuint32_t ERS:1;\r
+ vuint32_t ESUS:1;\r
+ vuint32_t EHV:1;\r
+ } B;\r
+ } MCR;\r
+\r
+ union { /* LML Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t LME:1;\r
+ vuint32_t:10;\r
+ vuint32_t SLOCK:1;\r
+ vuint32_t MLOCK:4;\r
+ vuint32_t LLOCK:16;\r
+ } B;\r
+ } LMLR;\r
+\r
+ union { /* HL Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t HBE:1;\r
+ vuint32_t:3;\r
+ vuint32_t HBLOCK:28;\r
+ } B;\r
+ } HLR;\r
+\r
+ union { /* SLML Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t SLE:1;\r
+ vuint32_t:10;\r
+ vuint32_t SSLOCK:1;\r
+ vuint32_t SMLOCK:4;\r
+ vuint32_t SLLOCK:16;\r
+ } B;\r
+ } SLMLR;\r
+\r
+ union { /* LMS Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:12;\r
+ vuint32_t MSEL:4;\r
+ vuint32_t LSEL:16;\r
+ } B;\r
+ } LMSR;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:4;\r
+ vuint32_t HBSEL:28;\r
+ } B;\r
+ } HSR;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:10;\r
+ vuint32_t ADDR:19;\r
+ vuint32_t:3;\r
+ } B;\r
+ } AR;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+\r
+ vuint32_t:9;\r
+ vuint32_t M6PFE:1; /* Flexray */\r
+ vuint32_t:1;\r
+\r
+ vuint32_t M4PFE:1; /* FEC */\r
+\r
+ vuint32_t M3PFE:1;\r
+ vuint32_t M2PFE:1;\r
+ vuint32_t M1PFE:1;\r
+ vuint32_t M0PFE:1;\r
+ vuint32_t APC:3;\r
+ vuint32_t WWSC:2;\r
+ vuint32_t RWSC:3;\r
+\r
+ vuint32_t DPFEN:2;\r
+ vuint32_t IPFEN:2;\r
+\r
+ vuint32_t PFLIM:3;\r
+ vuint32_t BFEN:1;\r
+ } B;\r
+ } BIUCR;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+\r
+ vuint32_t:18;\r
+ vuint32_t M6AP:2; /* Flexray */\r
+ vuint32_t:2;\r
+\r
+ vuint32_t M4AP:2; /* FEC */\r
+\r
+ vuint32_t M3AP:2;\r
+ vuint32_t M2AP:2;\r
+ vuint32_t M1AP:2;\r
+ vuint32_t M0AP:2;\r
+ } B;\r
+ } BIUAPR;\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : SIU */\r
+/****************************************************************************/\r
+ struct SIU_tag {\r
+ int32_t SIU_reserved0;\r
+\r
+ union { /* MCU ID Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PARTNUM:16;\r
+ vuint32_t MASKNUM:16;\r
+ } B;\r
+ } MIDR;\r
+ int32_t SIU_reserved00;\r
+\r
+ union { /* Reset Status Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PORS:1;\r
+ vuint32_t ERS:1;\r
+ vuint32_t LLRS:1;\r
+ vuint32_t LCRS:1;\r
+ vuint32_t WDRS:1;\r
+ vuint32_t CRS:1;\r
+ vuint32_t:8;\r
+ vuint32_t SSRS:1;\r
+ vuint32_t SERF:1;\r
+ vuint32_t WKPCFG:1;\r
+ vuint32_t:12;\r
+ vuint32_t BOOTCFG:2;\r
+ vuint32_t RGF:1;\r
+ } B;\r
+ } RSR;\r
+\r
+ union { /* System Reset Control Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t SSR:1;\r
+ vuint32_t SER:1;\r
+ vuint32_t:14;\r
+ vuint32_t CRE:1;\r
+ vuint32_t:15;\r
+ } B;\r
+ } SRCR;\r
+\r
+ union { /* External Interrupt Status Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t EIF15:1;\r
+ vuint32_t EIF14:1;\r
+ vuint32_t EIF13:1;\r
+ vuint32_t EIF12:1;\r
+ vuint32_t EIF11:1;\r
+ vuint32_t EIF10:1;\r
+ vuint32_t EIF9:1;\r
+ vuint32_t EIF8:1;\r
+ vuint32_t EIF7:1;\r
+ vuint32_t EIF6:1;\r
+ vuint32_t EIF5:1;\r
+ vuint32_t EIF4:1;\r
+ vuint32_t EIF3:1;\r
+ vuint32_t EIF2:1;\r
+ vuint32_t EIF1:1;\r
+ vuint32_t EIF0:1;\r
+ } B;\r
+ } EISR;\r
+\r
+ union { /* DMA/Interrupt Request Enable Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t EIRE15:1;\r
+ vuint32_t EIRE14:1;\r
+ vuint32_t EIRE13:1;\r
+ vuint32_t EIRE12:1;\r
+ vuint32_t EIRE11:1;\r
+ vuint32_t EIRE10:1;\r
+ vuint32_t EIRE9:1;\r
+ vuint32_t EIRE8:1;\r
+ vuint32_t EIRE7:1;\r
+ vuint32_t EIRE6:1;\r
+ vuint32_t EIRE5:1;\r
+ vuint32_t EIRE4:1;\r
+ vuint32_t EIRE3:1;\r
+ vuint32_t EIRE2:1;\r
+ vuint32_t EIRE1:1;\r
+ vuint32_t EIRE0:1;\r
+ } B;\r
+ } DIRER;\r
+\r
+ union { /* DMA/Interrupt Select Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:28;\r
+ vuint32_t DIRS3:1;\r
+ vuint32_t DIRS2:1;\r
+ vuint32_t DIRS1:1;\r
+ vuint32_t DIRS0:1;\r
+ } B;\r
+ } DIRSR;\r
+\r
+ union { /* Overrun Status Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t OVF15:1;\r
+ vuint32_t OVF14:1;\r
+ vuint32_t OVF13:1;\r
+ vuint32_t OVF12:1;\r
+ vuint32_t OVF11:1;\r
+ vuint32_t OVF10:1;\r
+ vuint32_t OVF9:1;\r
+ vuint32_t OVF8:1;\r
+ vuint32_t OVF7:1;\r
+ vuint32_t OVF6:1;\r
+ vuint32_t OVF5:1;\r
+ vuint32_t OVF4:1;\r
+ vuint32_t OVF3:1;\r
+ vuint32_t OVF2:1;\r
+ vuint32_t OVF1:1;\r
+ vuint32_t OVF0:1;\r
+ } B;\r
+ } OSR;\r
+\r
+ union { /* Overrun Request Enable Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t ORE15:1;\r
+ vuint32_t ORE14:1;\r
+ vuint32_t ORE13:1;\r
+ vuint32_t ORE12:1;\r
+ vuint32_t ORE11:1;\r
+ vuint32_t ORE10:1;\r
+ vuint32_t ORE9:1;\r
+ vuint32_t ORE8:1;\r
+ vuint32_t ORE7:1;\r
+ vuint32_t ORE6:1;\r
+ vuint32_t ORE5:1;\r
+ vuint32_t ORE4:1;\r
+ vuint32_t ORE3:1;\r
+ vuint32_t ORE2:1;\r
+ vuint32_t ORE1:1;\r
+ vuint32_t ORE0:1;\r
+ } B;\r
+ } ORER;\r
+\r
+ union { /* External IRQ Rising-Edge Event Enable Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t IREE15:1;\r
+ vuint32_t IREE14:1;\r
+ vuint32_t IREE13:1;\r
+ vuint32_t IREE12:1;\r
+ vuint32_t IREE11:1;\r
+ vuint32_t IREE10:1;\r
+ vuint32_t IREE9:1;\r
+ vuint32_t IREE8:1;\r
+ vuint32_t IREE7:1;\r
+ vuint32_t IREE6:1;\r
+ vuint32_t IREE5:1;\r
+ vuint32_t IREE4:1;\r
+ vuint32_t IREE3:1;\r
+ vuint32_t IREE2:1;\r
+ vuint32_t IREE1:1;\r
+ vuint32_t IREE0:1;\r
+ } B;\r
+ } IREER;\r
+\r
+ union { /* External IRQ Falling-Edge Event Enable Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t IFEE15:1;\r
+ vuint32_t IFEE14:1;\r
+ vuint32_t IFEE13:1;\r
+ vuint32_t IFEE12:1;\r
+ vuint32_t IFEE11:1;\r
+ vuint32_t IFEE10:1;\r
+ vuint32_t IFEE9:1;\r
+ vuint32_t IFEE8:1;\r
+ vuint32_t IFEE7:1;\r
+ vuint32_t IFEE6:1;\r
+ vuint32_t IFEE5:1;\r
+ vuint32_t IFEE4:1;\r
+ vuint32_t IFEE3:1;\r
+ vuint32_t IFEE2:1;\r
+ vuint32_t IFEE1:1;\r
+ vuint32_t IFEE0:1;\r
+ } B;\r
+ } IFEER;\r
+\r
+ union { /* External IRQ Digital Filter Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:28;\r
+ vuint32_t DFL:4;\r
+ } B;\r
+ } IDFR;\r
+\r
+ int32_t SIU_reserved1[3];\r
+\r
+ union { /* Pad Configuration Registers */\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:3;\r
+ vuint16_t PA:3;\r
+ vuint16_t OBE:1;\r
+ vuint16_t IBE:1;\r
+ vuint16_t DSC:2;\r
+ vuint16_t ODE:1;\r
+ vuint16_t HYS:1;\r
+ vuint16_t SRC:2;\r
+ vuint16_t WPE:1;\r
+ vuint16_t WPS:1;\r
+ } B;\r
+ } PCR[512];\r
+\r
+ int16_t SIU_reserved_0[224];\r
+\r
+ union { /* GPIO Pin Data Output Registers */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t:7;\r
+ vuint8_t PDO:1;\r
+ } B;\r
+ } GPDO[256];\r
+\r
+ int32_t SIU_reserved_3[64];\r
+\r
+ union { /* GPIO Pin Data Input Registers */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t:7;\r
+ vuint8_t PDI:1;\r
+ } B;\r
+ } GPDI[256];\r
+\r
+ union { /* IMUX Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TSEL5:2;\r
+ vuint32_t TSEL4:2;\r
+ vuint32_t TSEL3:2;\r
+ vuint32_t TSEL2:2;\r
+ vuint32_t TSEL1:2;\r
+ vuint32_t TSEL0:2;\r
+ vuint32_t:20;\r
+ } B;\r
+ } ETISR;\r
+\r
+ union { /* IMUX Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t ESEL15:2;\r
+ vuint32_t ESEL14:2;\r
+ vuint32_t ESEL13:2;\r
+ vuint32_t ESEL12:2;\r
+ vuint32_t ESEL11:2;\r
+ vuint32_t ESEL10:2;\r
+ vuint32_t ESEL9:2;\r
+ vuint32_t ESEL8:2;\r
+ vuint32_t ESEL7:2;\r
+ vuint32_t ESEL6:2;\r
+ vuint32_t ESEL5:2;\r
+ vuint32_t ESEL4:2;\r
+ vuint32_t ESEL3:2;\r
+ vuint32_t ESEL2:2;\r
+ vuint32_t ESEL1:2;\r
+ vuint32_t ESEL0:2;\r
+ } B;\r
+ } EIISR;\r
+\r
+ union { /* IMUX Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t SINSELA:2;\r
+ vuint32_t SSSELA:2;\r
+ vuint32_t SCKSELA:2;\r
+ vuint32_t TRIGSELA:2;\r
+ vuint32_t SINSELB:2;\r
+ vuint32_t SSSELB:2;\r
+ vuint32_t SCKSELB:2;\r
+ vuint32_t TRIGSELB:2;\r
+ vuint32_t SINSELC:2;\r
+ vuint32_t SSSELC:2;\r
+ vuint32_t SCKSELC:2;\r
+ vuint32_t TRIGSELC:2;\r
+ vuint32_t SINSELD:2;\r
+ vuint32_t SSSELD:2;\r
+ vuint32_t SCKSELD:2;\r
+ vuint32_t TRIGSELD:2;\r
+ } B;\r
+ } DISR;\r
+\r
+ int32_t SIU_reserved2[29];\r
+\r
+ union { /* Chip Configuration Register Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:14;\r
+ vuint32_t MATCH:1;\r
+ vuint32_t DISNEX:1;\r
+ vuint32_t:16;\r
+ } B;\r
+ } CCR;\r
+\r
+ union { /* External Clock Configuration Register Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:18;\r
+ vuint32_t ENGDIV:6;\r
+ vuint32_t:4;\r
+ vuint32_t EBTS:1;\r
+ vuint32_t:1;\r
+ vuint32_t EBDF:2;\r
+ } B;\r
+ } ECCR;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } CARH;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } CARL;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } CBRH;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } CBRL;\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : EMIOS */\r
+/****************************************************************************/\r
+ struct EMIOS_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:1;\r
+ vuint32_t MDIS:1;\r
+ vuint32_t FRZ:1;\r
+ vuint32_t GTBE:1;\r
+ vuint32_t ETB:1;\r
+ vuint32_t GPREN:1;\r
+ vuint32_t:6;\r
+ vuint32_t SRV:4;\r
+ vuint32_t GPRE:8;\r
+ vuint32_t:8;\r
+ } B;\r
+ } MCR; /* Module Configuration Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:8;\r
+ vuint32_t F23:1;\r
+ vuint32_t F22:1;\r
+ vuint32_t F21:1;\r
+ vuint32_t F20:1;\r
+ vuint32_t F19:1;\r
+ vuint32_t F18:1;\r
+ vuint32_t F17:1;\r
+ vuint32_t F16:1;\r
+ vuint32_t F15:1;\r
+ vuint32_t F14:1;\r
+ vuint32_t F13:1;\r
+ vuint32_t F12:1;\r
+ vuint32_t F11:1;\r
+ vuint32_t F10:1;\r
+ vuint32_t F9:1;\r
+ vuint32_t F8:1;\r
+ vuint32_t F7:1;\r
+ vuint32_t F6:1;\r
+ vuint32_t F5:1;\r
+ vuint32_t F4:1;\r
+ vuint32_t F3:1;\r
+ vuint32_t F2:1;\r
+ vuint32_t F1:1;\r
+ vuint32_t F0:1;\r
+ } B;\r
+ } GFR; /* Global FLAG Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:8;\r
+ vuint32_t OU23:1;\r
+ vuint32_t OU22:1;\r
+ vuint32_t OU21:1;\r
+ vuint32_t OU20:1;\r
+ vuint32_t OU19:1;\r
+ vuint32_t OU18:1;\r
+ vuint32_t OU17:1;\r
+ vuint32_t OU16:1;\r
+ vuint32_t OU15:1;\r
+ vuint32_t OU14:1;\r
+ vuint32_t OU13:1;\r
+ vuint32_t OU12:1;\r
+ vuint32_t OU11:1;\r
+ vuint32_t OU10:1;\r
+ vuint32_t OU9:1;\r
+ vuint32_t OU8:1;\r
+ vuint32_t OU7:1;\r
+ vuint32_t OU6:1;\r
+ vuint32_t OU5:1;\r
+ vuint32_t OU4:1;\r
+ vuint32_t OU3:1;\r
+ vuint32_t OU2:1;\r
+ vuint32_t OU1:1;\r
+ vuint32_t OU0:1;\r
+ } B;\r
+ } OUDR; /* Output Update Disable Register */\r
+\r
+ uint32_t emios_reserved[5];\r
+\r
+ struct {\r
+ union {\r
+ vuint32_t R; /* Channel A Data Register */\r
+ } CADR;\r
+\r
+ union {\r
+ vuint32_t R; /* Channel B Data Register */\r
+ } CBDR;\r
+\r
+ union {\r
+ vuint32_t R; /* Channel Counter Register */\r
+ } CCNTR;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t FREN:1;\r
+ vuint32_t ODIS:1;\r
+ vuint32_t ODISSL:2;\r
+ vuint32_t UCPRE:2;\r
+ vuint32_t UCPREN:1;\r
+ vuint32_t DMA:1;\r
+ vuint32_t:1;\r
+ vuint32_t IF:4;\r
+ vuint32_t FCK:1;\r
+ vuint32_t FEN:1;\r
+ vuint32_t:3;\r
+ vuint32_t FORCMA:1;\r
+ vuint32_t FORCMB:1;\r
+ vuint32_t:1;\r
+ vuint32_t BSL:2;\r
+ vuint32_t EDSEL:1;\r
+ vuint32_t EDPOL:1;\r
+ vuint32_t MODE:7;\r
+ } B;\r
+ } CCR; /* Channel Control Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t OVR:1;\r
+ vuint32_t:15;\r
+ vuint32_t OVFL:1;\r
+ vuint32_t:12;\r
+ vuint32_t UCIN:1;\r
+ vuint32_t UCOUT:1;\r
+ vuint32_t FLAG:1;\r
+ } B;\r
+ } CSR; /* Channel Status Register */\r
+\r
+ union {\r
+ vuint32_t R; /* Alternate Channel A Data Register */\r
+ } ALTCADR;\r
+\r
+ uint32_t emios_channel_reserved[2];\r
+\r
+ } CH[24];\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE :ETPU */\r
+/****************************************************************************/\r
+\r
+/***************************Configuration Registers**************************/\r
+\r
+ struct ETPU_tag {\r
+ union { /* MODULE CONFIGURATION REGISTER */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t GEC:1; /* Global Exception Clear */\r
+ vuint32_t:3;\r
+ vuint32_t MGE1:1; /* Microcode Global Exception-ETPU_A */\r
+\r
+ vuint32_t:1; /* For single ETPU implementations */\r
+\r
+ vuint32_t ILF1:1; /* Illegal Instruction Flag-ETPU_A */\r
+\r
+ vuint32_t:1; /* For single ETPU implementations */\r
+\r
+ vuint32_t:3;\r
+ vuint32_t SCMSIZE:5; /* Shared Code Memory size */\r
+ vuint32_t:5;\r
+ vuint32_t SCMMISF:1; /* SCM MISC Flag */\r
+ vuint32_t SCMMISEN:1; /* SCM MISC Enable */\r
+ vuint32_t:2;\r
+ vuint32_t VIS:1; /* SCM Visability */\r
+ vuint32_t:5;\r
+ vuint32_t GTBE:1; /* Global Time Base Enable */\r
+ } B;\r
+ } MCR;\r
+\r
+ union { /* COHERENT DUAL-PARAMETER CONTROL */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t STS:1; /* Start Status bit */\r
+ vuint32_t CTBASE:5; /* Channel Transfer Base */\r
+ vuint32_t PBASE:10; /* Parameter Buffer Base Address */\r
+ vuint32_t PWIDTH:1; /* Parameter Width */\r
+ vuint32_t PARAM0:7; /* Channel Parameter 0 */\r
+ vuint32_t WR:1;\r
+ vuint32_t PARAM1:7; /* Channel Parameter 1 */\r
+ } B;\r
+ } CDCR;\r
+\r
+ uint32_t etpu_reserved1;\r
+\r
+ union { /* MISC Compare Register */\r
+ vuint32_t R;\r
+ } MISCCMPR;\r
+\r
+ union { /* SCM off-range Date Register */\r
+ vuint32_t R;\r
+ } SCMOFFDATAR;\r
+\r
+ union { /* ETPU_A Configuration Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t FEND:1; /* Force END */\r
+ vuint32_t MDIS:1; /* Low power Stop */\r
+ vuint32_t:1;\r
+ vuint32_t STF:1; /* Stop Flag */\r
+ vuint32_t:4;\r
+ vuint32_t HLTF:1; /* Halt Mode Flag */\r
+ vuint32_t:4;\r
+ vuint32_t FPSCK:3; /* Filter Prescaler Clock Control */\r
+ vuint32_t CDFC:2;\r
+ vuint32_t:9;\r
+ vuint32_t ETB:5; /* Entry Table Base */\r
+ } B;\r
+ } ECR_A;\r
+ uint32_t etpu_reserved3; /* For single ETPU implementations */\r
+\r
+ uint32_t etpu_reserved4;\r
+\r
+ union { /* ETPU_A Timebase Configuration Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TCR2CTL:3; /* TCR2 Clock/Gate Control */\r
+ vuint32_t TCRCF:2; /* TCRCLK Signal Filter Control */\r
+ vuint32_t:1;\r
+ vuint32_t AM:1; /* Angle Mode */\r
+ vuint32_t:3;\r
+ vuint32_t TCR2P:6; /* TCR2 Prescaler Control */\r
+ vuint32_t TCR1CTL:2; /* TCR1 Clock/Gate Control */\r
+ vuint32_t:6;\r
+ vuint32_t TCR1P:8; /* TCR1 Prescaler Control */\r
+ } B;\r
+ } TBCR_A;\r
+\r
+ union { /* ETPU_A TCR1 Visibility Register */\r
+ vuint32_t R;\r
+ } TB1R_A;\r
+\r
+ union { /* ETPU_A TCR2 Visibility Register */\r
+ vuint32_t R;\r
+ } TB2R_A;\r
+\r
+ union { /* ETPU_A STAC Configuration Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t REN1:1; /* Resource Enable TCR1 */\r
+ vuint32_t RSC1:1; /* Resource Control TCR1 */\r
+ vuint32_t:2;\r
+ vuint32_t SERVER_ID1:4;\r
+ vuint32_t:4;\r
+ vuint32_t SRV1:4; /* Resource Server Slot */\r
+ vuint32_t REN2:1; /* Resource Enable TCR2 */\r
+ vuint32_t RSC2:1; /* Resource Control TCR2 */\r
+ vuint32_t:2;\r
+ vuint32_t SERVER_ID2:4;\r
+ vuint32_t:4;\r
+ vuint32_t SRV2:4; /* Resource Server Slot */\r
+ } B;\r
+ } REDCR_A;\r
+\r
+ uint32_t etpu_reserved5[4];\r
+ uint32_t etpu_reserved6[4]; /* For single ETPU implementations */\r
+\r
+ uint32_t etpu_reserved7[108];\r
+\r
+/*****************************Status and Control Registers**************************/\r
+\r
+ union { /* ETPU_A Channel Interrut Status */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CIS31:1; /* Channel 31 Interrut Status */\r
+ vuint32_t CIS30:1; /* Channel 30 Interrut Status */\r
+ vuint32_t CIS29:1; /* Channel 29 Interrut Status */\r
+ vuint32_t CIS28:1; /* Channel 28 Interrut Status */\r
+ vuint32_t CIS27:1; /* Channel 27 Interrut Status */\r
+ vuint32_t CIS26:1; /* Channel 26 Interrut Status */\r
+ vuint32_t CIS25:1; /* Channel 25 Interrut Status */\r
+ vuint32_t CIS24:1; /* Channel 24 Interrut Status */\r
+ vuint32_t CIS23:1; /* Channel 23 Interrut Status */\r
+ vuint32_t CIS22:1; /* Channel 22 Interrut Status */\r
+ vuint32_t CIS21:1; /* Channel 21 Interrut Status */\r
+ vuint32_t CIS20:1; /* Channel 20 Interrut Status */\r
+ vuint32_t CIS19:1; /* Channel 19 Interrut Status */\r
+ vuint32_t CIS18:1; /* Channel 18 Interrut Status */\r
+ vuint32_t CIS17:1; /* Channel 17 Interrut Status */\r
+ vuint32_t CIS16:1; /* Channel 16 Interrut Status */\r
+ vuint32_t CIS15:1; /* Channel 15 Interrut Status */\r
+ vuint32_t CIS14:1; /* Channel 14 Interrut Status */\r
+ vuint32_t CIS13:1; /* Channel 13 Interrut Status */\r
+ vuint32_t CIS12:1; /* Channel 12 Interrut Status */\r
+ vuint32_t CIS11:1; /* Channel 11 Interrut Status */\r
+ vuint32_t CIS10:1; /* Channel 10 Interrut Status */\r
+ vuint32_t CIS9:1; /* Channel 9 Interrut Status */\r
+ vuint32_t CIS8:1; /* Channel 8 Interrut Status */\r
+ vuint32_t CIS7:1; /* Channel 7 Interrut Status */\r
+ vuint32_t CIS6:1; /* Channel 6 Interrut Status */\r
+ vuint32_t CIS5:1; /* Channel 5 Interrut Status */\r
+ vuint32_t CIS4:1; /* Channel 4 Interrut Status */\r
+ vuint32_t CIS3:1; /* Channel 3 Interrut Status */\r
+ vuint32_t CIS2:1; /* Channel 2 Interrut Status */\r
+ vuint32_t CIS1:1; /* Channel 1 Interrut Status */\r
+ vuint32_t CIS0:1; /* Channel 0 Interrut Status */\r
+ } B;\r
+ } CISR_A;\r
+ uint32_t etpu_reserved8; /* For single ETPU implementations */\r
+\r
+ uint32_t etpu_reserved9[2];\r
+\r
+ union { /* ETPU_A Data Transfer Request Status */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DTRS31:1; /* Channel 31 Data Transfer Request Status */\r
+ vuint32_t DTRS30:1; /* Channel 30 Data Transfer Request Status */\r
+ vuint32_t DTRS29:1; /* Channel 29 Data Transfer Request Status */\r
+ vuint32_t DTRS28:1; /* Channel 28 Data Transfer Request Status */\r
+ vuint32_t DTRS27:1; /* Channel 27 Data Transfer Request Status */\r
+ vuint32_t DTRS26:1; /* Channel 26 Data Transfer Request Status */\r
+ vuint32_t DTRS25:1; /* Channel 25 Data Transfer Request Status */\r
+ vuint32_t DTRS24:1; /* Channel 24 Data Transfer Request Status */\r
+ vuint32_t DTRS23:1; /* Channel 23 Data Transfer Request Status */\r
+ vuint32_t DTRS22:1; /* Channel 22 Data Transfer Request Status */\r
+ vuint32_t DTRS21:1; /* Channel 21 Data Transfer Request Status */\r
+ vuint32_t DTRS20:1; /* Channel 20 Data Transfer Request Status */\r
+ vuint32_t DTRS19:1; /* Channel 19 Data Transfer Request Status */\r
+ vuint32_t DTRS18:1; /* Channel 18 Data Transfer Request Status */\r
+ vuint32_t DTRS17:1; /* Channel 17 Data Transfer Request Status */\r
+ vuint32_t DTRS16:1; /* Channel 16 Data Transfer Request Status */\r
+ vuint32_t DTRS15:1; /* Channel 15 Data Transfer Request Status */\r
+ vuint32_t DTRS14:1; /* Channel 14 Data Transfer Request Status */\r
+ vuint32_t DTRS13:1; /* Channel 13 Data Transfer Request Status */\r
+ vuint32_t DTRS12:1; /* Channel 12 Data Transfer Request Status */\r
+ vuint32_t DTRS11:1; /* Channel 11 Data Transfer Request Status */\r
+ vuint32_t DTRS10:1; /* Channel 10 Data Transfer Request Status */\r
+ vuint32_t DTRS9:1; /* Channel 9 Data Transfer Request Status */\r
+ vuint32_t DTRS8:1; /* Channel 8 Data Transfer Request Status */\r
+ vuint32_t DTRS7:1; /* Channel 7 Data Transfer Request Status */\r
+ vuint32_t DTRS6:1; /* Channel 6 Data Transfer Request Status */\r
+ vuint32_t DTRS5:1; /* Channel 5 Data Transfer Request Status */\r
+ vuint32_t DTRS4:1; /* Channel 4 Data Transfer Request Status */\r
+ vuint32_t DTRS3:1; /* Channel 3 Data Transfer Request Status */\r
+ vuint32_t DTRS2:1; /* Channel 2 Data Transfer Request Status */\r
+ vuint32_t DTRS1:1; /* Channel 1 Data Transfer Request Status */\r
+ vuint32_t DTRS0:1; /* Channel 0 Data Transfer Request Status */\r
+ } B;\r
+ } CDTRSR_A;\r
+ uint32_t etpu_reserved10; /* For single ETPU implementations */\r
+\r
+ uint32_t etpu_reserved11[2];\r
+\r
+ union { /* ETPU_A Interruput Overflow Status */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CIOS31:1; /* Channel 31 Interruput Overflow Status */\r
+ vuint32_t CIOS30:1; /* Channel 30 Interruput Overflow Status */\r
+ vuint32_t CIOS29:1; /* Channel 29 Interruput Overflow Status */\r
+ vuint32_t CIOS28:1; /* Channel 28 Interruput Overflow Status */\r
+ vuint32_t CIOS27:1; /* Channel 27 Interruput Overflow Status */\r
+ vuint32_t CIOS26:1; /* Channel 26 Interruput Overflow Status */\r
+ vuint32_t CIOS25:1; /* Channel 25 Interruput Overflow Status */\r
+ vuint32_t CIOS24:1; /* Channel 24 Interruput Overflow Status */\r
+ vuint32_t CIOS23:1; /* Channel 23 Interruput Overflow Status */\r
+ vuint32_t CIOS22:1; /* Channel 22 Interruput Overflow Status */\r
+ vuint32_t CIOS21:1; /* Channel 21 Interruput Overflow Status */\r
+ vuint32_t CIOS20:1; /* Channel 20 Interruput Overflow Status */\r
+ vuint32_t CIOS19:1; /* Channel 19 Interruput Overflow Status */\r
+ vuint32_t CIOS18:1; /* Channel 18 Interruput Overflow Status */\r
+ vuint32_t CIOS17:1; /* Channel 17 Interruput Overflow Status */\r
+ vuint32_t CIOS16:1; /* Channel 16 Interruput Overflow Status */\r
+ vuint32_t CIOS15:1; /* Channel 15 Interruput Overflow Status */\r
+ vuint32_t CIOS14:1; /* Channel 14 Interruput Overflow Status */\r
+ vuint32_t CIOS13:1; /* Channel 13 Interruput Overflow Status */\r
+ vuint32_t CIOS12:1; /* Channel 12 Interruput Overflow Status */\r
+ vuint32_t CIOS11:1; /* Channel 11 Interruput Overflow Status */\r
+ vuint32_t CIOS10:1; /* Channel 10 Interruput Overflow Status */\r
+ vuint32_t CIOS9:1; /* Channel 9 Interruput Overflow Status */\r
+ vuint32_t CIOS8:1; /* Channel 8 Interruput Overflow Status */\r
+ vuint32_t CIOS7:1; /* Channel 7 Interruput Overflow Status */\r
+ vuint32_t CIOS6:1; /* Channel 6 Interruput Overflow Status */\r
+ vuint32_t CIOS5:1; /* Channel 5 Interruput Overflow Status */\r
+ vuint32_t CIOS4:1; /* Channel 4 Interruput Overflow Status */\r
+ vuint32_t CIOS3:1; /* Channel 3 Interruput Overflow Status */\r
+ vuint32_t CIOS2:1; /* Channel 2 Interruput Overflow Status */\r
+ vuint32_t CIOS1:1; /* Channel 1 Interruput Overflow Status */\r
+ vuint32_t CIOS0:1; /* Channel 0 Interruput Overflow Status */\r
+ } B;\r
+ } CIOSR_A;\r
+ uint32_t etpu_reserved12; /* For single ETPU implementations */\r
+\r
+ uint32_t etpu_reserved13[2];\r
+\r
+ union { /* ETPU_A Data Transfer Overflow Status */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DTROS31:1; /* Channel 31 Data Transfer Overflow Status */\r
+ vuint32_t DTROS30:1; /* Channel 30 Data Transfer Overflow Status */\r
+ vuint32_t DTROS29:1; /* Channel 29 Data Transfer Overflow Status */\r
+ vuint32_t DTROS28:1; /* Channel 28 Data Transfer Overflow Status */\r
+ vuint32_t DTROS27:1; /* Channel 27 Data Transfer Overflow Status */\r
+ vuint32_t DTROS26:1; /* Channel 26 Data Transfer Overflow Status */\r
+ vuint32_t DTROS25:1; /* Channel 25 Data Transfer Overflow Status */\r
+ vuint32_t DTROS24:1; /* Channel 24 Data Transfer Overflow Status */\r
+ vuint32_t DTROS23:1; /* Channel 23 Data Transfer Overflow Status */\r
+ vuint32_t DTROS22:1; /* Channel 22 Data Transfer Overflow Status */\r
+ vuint32_t DTROS21:1; /* Channel 21 Data Transfer Overflow Status */\r
+ vuint32_t DTROS20:1; /* Channel 20 Data Transfer Overflow Status */\r
+ vuint32_t DTROS19:1; /* Channel 19 Data Transfer Overflow Status */\r
+ vuint32_t DTROS18:1; /* Channel 18 Data Transfer Overflow Status */\r
+ vuint32_t DTROS17:1; /* Channel 17 Data Transfer Overflow Status */\r
+ vuint32_t DTROS16:1; /* Channel 16 Data Transfer Overflow Status */\r
+ vuint32_t DTROS15:1; /* Channel 15 Data Transfer Overflow Status */\r
+ vuint32_t DTROS14:1; /* Channel 14 Data Transfer Overflow Status */\r
+ vuint32_t DTROS13:1; /* Channel 13 Data Transfer Overflow Status */\r
+ vuint32_t DTROS12:1; /* Channel 12 Data Transfer Overflow Status */\r
+ vuint32_t DTROS11:1; /* Channel 11 Data Transfer Overflow Status */\r
+ vuint32_t DTROS10:1; /* Channel 10 Data Transfer Overflow Status */\r
+ vuint32_t DTROS9:1; /* Channel 9 Data Transfer Overflow Status */\r
+ vuint32_t DTROS8:1; /* Channel 8 Data Transfer Overflow Status */\r
+ vuint32_t DTROS7:1; /* Channel 7 Data Transfer Overflow Status */\r
+ vuint32_t DTROS6:1; /* Channel 6 Data Transfer Overflow Status */\r
+ vuint32_t DTROS5:1; /* Channel 5 Data Transfer Overflow Status */\r
+ vuint32_t DTROS4:1; /* Channel 4 Data Transfer Overflow Status */\r
+ vuint32_t DTROS3:1; /* Channel 3 Data Transfer Overflow Status */\r
+ vuint32_t DTROS2:1; /* Channel 2 Data Transfer Overflow Status */\r
+ vuint32_t DTROS1:1; /* Channel 1 Data Transfer Overflow Status */\r
+ vuint32_t DTROS0:1; /* Channel 0 Data Transfer Overflow Status */\r
+ } B;\r
+ } CDTROSR_A;\r
+ uint32_t etpu_reserved14; /* For single ETPU implementations */\r
+\r
+ uint32_t etpu_reserved15[2];\r
+\r
+ union { /* ETPU_A Channel Interruput Enable */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CIE31:1; /* Channel 31 Interruput Enable */\r
+ vuint32_t CIE30:1; /* Channel 30 Interruput Enable */\r
+ vuint32_t CIE29:1; /* Channel 29 Interruput Enable */\r
+ vuint32_t CIE28:1; /* Channel 28 Interruput Enable */\r
+ vuint32_t CIE27:1; /* Channel 27 Interruput Enable */\r
+ vuint32_t CIE26:1; /* Channel 26 Interruput Enable */\r
+ vuint32_t CIE25:1; /* Channel 25 Interruput Enable */\r
+ vuint32_t CIE24:1; /* Channel 24 Interruput Enable */\r
+ vuint32_t CIE23:1; /* Channel 23 Interruput Enable */\r
+ vuint32_t CIE22:1; /* Channel 22 Interruput Enable */\r
+ vuint32_t CIE21:1; /* Channel 21 Interruput Enable */\r
+ vuint32_t CIE20:1; /* Channel 20 Interruput Enable */\r
+ vuint32_t CIE19:1; /* Channel 19 Interruput Enable */\r
+ vuint32_t CIE18:1; /* Channel 18 Interruput Enable */\r
+ vuint32_t CIE17:1; /* Channel 17 Interruput Enable */\r
+ vuint32_t CIE16:1; /* Channel 16 Interruput Enable */\r
+ vuint32_t CIE15:1; /* Channel 15 Interruput Enable */\r
+ vuint32_t CIE14:1; /* Channel 14 Interruput Enable */\r
+ vuint32_t CIE13:1; /* Channel 13 Interruput Enable */\r
+ vuint32_t CIE12:1; /* Channel 12 Interruput Enable */\r
+ vuint32_t CIE11:1; /* Channel 11 Interruput Enable */\r
+ vuint32_t CIE10:1; /* Channel 10 Interruput Enable */\r
+ vuint32_t CIE9:1; /* Channel 9 Interruput Enable */\r
+ vuint32_t CIE8:1; /* Channel 8 Interruput Enable */\r
+ vuint32_t CIE7:1; /* Channel 7 Interruput Enable */\r
+ vuint32_t CIE6:1; /* Channel 6 Interruput Enable */\r
+ vuint32_t CIE5:1; /* Channel 5 Interruput Enable */\r
+ vuint32_t CIE4:1; /* Channel 4 Interruput Enable */\r
+ vuint32_t CIE3:1; /* Channel 3 Interruput Enable */\r
+ vuint32_t CIE2:1; /* Channel 2 Interruput Enable */\r
+ vuint32_t CIE1:1; /* Channel 1 Interruput Enable */\r
+ vuint32_t CIE0:1; /* Channel 0 Interruput Enable */\r
+ } B;\r
+ } CIER_A;\r
+ uint32_t etpu_reserved16; /* For single ETPU implementations */\r
+\r
+ uint32_t etpu_reserved17[2];\r
+\r
+ union { /* ETPU_A Channel Data Transfer Request Enable */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DTRE31:1; /* Channel 31 Data Transfer Request Enable */\r
+ vuint32_t DTRE30:1; /* Channel 30 Data Transfer Request Enable */\r
+ vuint32_t DTRE29:1; /* Channel 29 Data Transfer Request Enable */\r
+ vuint32_t DTRE28:1; /* Channel 28 Data Transfer Request Enable */\r
+ vuint32_t DTRE27:1; /* Channel 27 Data Transfer Request Enable */\r
+ vuint32_t DTRE26:1; /* Channel 26 Data Transfer Request Enable */\r
+ vuint32_t DTRE25:1; /* Channel 25 Data Transfer Request Enable */\r
+ vuint32_t DTRE24:1; /* Channel 24 Data Transfer Request Enable */\r
+ vuint32_t DTRE23:1; /* Channel 23 Data Transfer Request Enable */\r
+ vuint32_t DTRE22:1; /* Channel 22 Data Transfer Request Enable */\r
+ vuint32_t DTRE21:1; /* Channel 21 Data Transfer Request Enable */\r
+ vuint32_t DTRE20:1; /* Channel 20 Data Transfer Request Enable */\r
+ vuint32_t DTRE19:1; /* Channel 19 Data Transfer Request Enable */\r
+ vuint32_t DTRE18:1; /* Channel 18 Data Transfer Request Enable */\r
+ vuint32_t DTRE17:1; /* Channel 17 Data Transfer Request Enable */\r
+ vuint32_t DTRE16:1; /* Channel 16 Data Transfer Request Enable */\r
+ vuint32_t DTRE15:1; /* Channel 15 Data Transfer Request Enable */\r
+ vuint32_t DTRE14:1; /* Channel 14 Data Transfer Request Enable */\r
+ vuint32_t DTRE13:1; /* Channel 13 Data Transfer Request Enable */\r
+ vuint32_t DTRE12:1; /* Channel 12 Data Transfer Request Enable */\r
+ vuint32_t DTRE11:1; /* Channel 11 Data Transfer Request Enable */\r
+ vuint32_t DTRE10:1; /* Channel 10 Data Transfer Request Enable */\r
+ vuint32_t DTRE9:1; /* Channel 9 Data Transfer Request Enable */\r
+ vuint32_t DTRE8:1; /* Channel 8 Data Transfer Request Enable */\r
+ vuint32_t DTRE7:1; /* Channel 7 Data Transfer Request Enable */\r
+ vuint32_t DTRE6:1; /* Channel 6 Data Transfer Request Enable */\r
+ vuint32_t DTRE5:1; /* Channel 5 Data Transfer Request Enable */\r
+ vuint32_t DTRE4:1; /* Channel 4 Data Transfer Request Enable */\r
+ vuint32_t DTRE3:1; /* Channel 3 Data Transfer Request Enable */\r
+ vuint32_t DTRE2:1; /* Channel 2 Data Transfer Request Enable */\r
+ vuint32_t DTRE1:1; /* Channel 1 Data Transfer Request Enable */\r
+ vuint32_t DTRE0:1; /* Channel 0 Data Transfer Request Enable */\r
+ } B;\r
+ } CDTRER_A;\r
+ uint32_t etpu_reserved19; /* For single ETPU implementations */\r
+\r
+ uint32_t etpu_reserved20[10];\r
+ union { /* ETPU_A Channel Pending Service Status */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t SR31:1; /* Channel 31 Pending Service Status */\r
+ vuint32_t SR30:1; /* Channel 30 Pending Service Status */\r
+ vuint32_t SR29:1; /* Channel 29 Pending Service Status */\r
+ vuint32_t SR28:1; /* Channel 28 Pending Service Status */\r
+ vuint32_t SR27:1; /* Channel 27 Pending Service Status */\r
+ vuint32_t SR26:1; /* Channel 26 Pending Service Status */\r
+ vuint32_t SR25:1; /* Channel 25 Pending Service Status */\r
+ vuint32_t SR24:1; /* Channel 24 Pending Service Status */\r
+ vuint32_t SR23:1; /* Channel 23 Pending Service Status */\r
+ vuint32_t SR22:1; /* Channel 22 Pending Service Status */\r
+ vuint32_t SR21:1; /* Channel 21 Pending Service Status */\r
+ vuint32_t SR20:1; /* Channel 20 Pending Service Status */\r
+ vuint32_t SR19:1; /* Channel 19 Pending Service Status */\r
+ vuint32_t SR18:1; /* Channel 18 Pending Service Status */\r
+ vuint32_t SR17:1; /* Channel 17 Pending Service Status */\r
+ vuint32_t SR16:1; /* Channel 16 Pending Service Status */\r
+ vuint32_t SR15:1; /* Channel 15 Pending Service Status */\r
+ vuint32_t SR14:1; /* Channel 14 Pending Service Status */\r
+ vuint32_t SR13:1; /* Channel 13 Pending Service Status */\r
+ vuint32_t SR12:1; /* Channel 12 Pending Service Status */\r
+ vuint32_t SR11:1; /* Channel 11 Pending Service Status */\r
+ vuint32_t SR10:1; /* Channel 10 Pending Service Status */\r
+ vuint32_t SR9:1; /* Channel 9 Pending Service Status */\r
+ vuint32_t SR8:1; /* Channel 8 Pending Service Status */\r
+ vuint32_t SR7:1; /* Channel 7 Pending Service Status */\r
+ vuint32_t SR6:1; /* Channel 6 Pending Service Status */\r
+ vuint32_t SR5:1; /* Channel 5 Pending Service Status */\r
+ vuint32_t SR4:1; /* Channel 4 Pending Service Status */\r
+ vuint32_t SR3:1; /* Channel 3 Pending Service Status */\r
+ vuint32_t SR2:1; /* Channel 2 Pending Service Status */\r
+ vuint32_t SR1:1; /* Channel 1 Pending Service Status */\r
+ vuint32_t SR0:1; /* Channel 0 Pending Service Status */\r
+ } B;\r
+ } CPSSR_A;\r
+ uint32_t etpu_reserved22; /* For single ETPU implementations */\r
+\r
+ uint32_t etpu_reserved20a[2];\r
+\r
+ union { /* ETPU_A Channel Service Status */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t SS31:1; /* Channel 31 Service Status */\r
+ vuint32_t SS30:1; /* Channel 30 Service Status */\r
+ vuint32_t SS29:1; /* Channel 29 Service Status */\r
+ vuint32_t SS28:1; /* Channel 28 Service Status */\r
+ vuint32_t SS27:1; /* Channel 27 Service Status */\r
+ vuint32_t SS26:1; /* Channel 26 Service Status */\r
+ vuint32_t SS25:1; /* Channel 25 Service Status */\r
+ vuint32_t SS24:1; /* Channel 24 Service Status */\r
+ vuint32_t SS23:1; /* Channel 23 Service Status */\r
+ vuint32_t SS22:1; /* Channel 22 Service Status */\r
+ vuint32_t SS21:1; /* Channel 21 Service Status */\r
+ vuint32_t SS20:1; /* Channel 20 Service Status */\r
+ vuint32_t SS19:1; /* Channel 19 Service Status */\r
+ vuint32_t SS18:1; /* Channel 18 Service Status */\r
+ vuint32_t SS17:1; /* Channel 17 Service Status */\r
+ vuint32_t SS16:1; /* Channel 16 Service Status */\r
+ vuint32_t SS15:1; /* Channel 15 Service Status */\r
+ vuint32_t SS14:1; /* Channel 14 Service Status */\r
+ vuint32_t SS13:1; /* Channel 13 Service Status */\r
+ vuint32_t SS12:1; /* Channel 12 Service Status */\r
+ vuint32_t SS11:1; /* Channel 11 Service Status */\r
+ vuint32_t SS10:1; /* Channel 10 Service Status */\r
+ vuint32_t SS9:1; /* Channel 9 Service Status */\r
+ vuint32_t SS8:1; /* Channel 8 Service Status */\r
+ vuint32_t SS7:1; /* Channel 7 Service Status */\r
+ vuint32_t SS6:1; /* Channel 6 Service Status */\r
+ vuint32_t SS5:1; /* Channel 5 Service Status */\r
+ vuint32_t SS4:1; /* Channel 4 Service Status */\r
+ vuint32_t SS3:1; /* Channel 3 Service Status */\r
+ vuint32_t SS2:1; /* Channel 2 Service Status */\r
+ vuint32_t SS1:1; /* Channel 1 Service Status */\r
+ vuint32_t SS0:1; /* Channel 0 Service Status */\r
+ } B;\r
+ } CSSR_A;\r
+ uint32_t etpu_reserved22a; /* For single ETPU implementations */\r
+\r
+ uint32_t etpu_reserved23[90];\r
+\r
+/*****************************Channels********************************/\r
+\r
+ struct {\r
+ union {\r
+ vuint32_t R; /* Channel Configuration Register */\r
+ struct {\r
+ vuint32_t CIE:1; /* Channel Interruput Enable */\r
+ vuint32_t DTRE:1; /* Data Transfer Request Enable */\r
+ vuint32_t CPR:2; /* Channel Priority */\r
+ vuint32_t:3;\r
+ vuint32_t ETCS:1; /* Entry Table Condition Select */\r
+ vuint32_t:3;\r
+ vuint32_t CFS:5; /* Channel Function Select */\r
+ vuint32_t ODIS:1; /* Output disable */\r
+ vuint32_t OPOL:1; /* output polarity */\r
+ vuint32_t:3;\r
+ vuint32_t CPBA:11; /* Channel Parameter Base Address */\r
+ } B;\r
+ } CR;\r
+ union {\r
+ vuint32_t R; /* Channel Status Control Register */\r
+ struct {\r
+ vuint32_t CIS:1; /* Channel Interruput Status */\r
+ vuint32_t CIOS:1; /* Channel Interruput Overflow Status */\r
+ vuint32_t:6;\r
+ vuint32_t DTRS:1; /* Data Transfer Status */\r
+ vuint32_t DTROS:1; /* Data Transfer Overflow Status */\r
+ vuint32_t:6;\r
+ vuint32_t IPS:1; /* Input Pin State */\r
+ vuint32_t OPS:1; /* Output Pin State */\r
+ vuint32_t OBE:1; /* Output Buffer Enable */\r
+ vuint32_t:11;\r
+ vuint32_t FM1:1; /* Function mode */\r
+ vuint32_t FM0:1; /* Function mode */\r
+ } B;\r
+ } SCR;\r
+ union {\r
+ vuint32_t R; /* Channel Host Service Request Register */\r
+ struct {\r
+ vuint32_t:29; /* Host Service Request */\r
+ vuint32_t HSR:3;\r
+ } B;\r
+ } HSRR;\r
+ uint32_t etpu_reserved23;\r
+ } CHAN[127];\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : XBAR CrossBar */\r
+/****************************************************************************/\r
+ struct XBAR_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:1;\r
+ vuint32_t MSTR6:3; /* FLEXRAY */\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:1;\r
+ vuint32_t MSTR3:3; /* FEC */\r
+\r
+ vuint32_t:1;\r
+ vuint32_t MSTR2:3;\r
+ vuint32_t:1;\r
+ vuint32_t MSTR1:3;\r
+ vuint32_t:1;\r
+ vuint32_t MSTR0:3;\r
+ } B;\r
+ } MPR0; /* Master Priority Register for Slave Port 0 */\r
+\r
+ uint32_t xbar_reserved1[3];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t RO:1;\r
+ vuint32_t:21;\r
+ vuint32_t ARB:2;\r
+ vuint32_t:2;\r
+ vuint32_t PCTL:2;\r
+ vuint32_t:1;\r
+ vuint32_t PARK:3;\r
+ } B;\r
+ } SGPCR0; /* General Purpose Control Register for Slave Port 0 */\r
+\r
+ uint32_t xbar_reserved2[59];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:1;\r
+ vuint32_t MSTR6:3; /* FLEXRAY */\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:1;\r
+ vuint32_t MSTR3:3; /* FEC */\r
+\r
+ vuint32_t:1;\r
+ vuint32_t MSTR2:3;\r
+ vuint32_t:1;\r
+ vuint32_t MSTR1:3;\r
+ vuint32_t:1;\r
+ vuint32_t MSTR0:3;\r
+ } B;\r
+ } MPR1; /* Master Priority Register for Slave Port 1 */\r
+\r
+ uint32_t xbar_reserved3[3];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t RO:1;\r
+ vuint32_t:21;\r
+ vuint32_t ARB:2;\r
+ vuint32_t:2;\r
+ vuint32_t PCTL:2;\r
+ vuint32_t:1;\r
+ vuint32_t PARK:3;\r
+ } B;\r
+ } SGPCR1; /* General Purpose Control Register for Slave Port 1 */\r
+\r
+ uint32_t xbar_reserved4[123];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:1;\r
+ vuint32_t MSTR6:3; /* FLEXRAY */\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:1;\r
+ vuint32_t MSTR3:3; /* FEC */\r
+\r
+ vuint32_t:1;\r
+ vuint32_t MSTR2:3;\r
+ vuint32_t:1;\r
+ vuint32_t MSTR1:3;\r
+ vuint32_t:1;\r
+ vuint32_t MSTR0:3;\r
+ } B;\r
+ } MPR3; /* Master Priority Register for Slave Port 3 */\r
+\r
+ uint32_t xbar_reserved5[3];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t RO:1;\r
+ vuint32_t:21;\r
+ vuint32_t ARB:2;\r
+ vuint32_t:2;\r
+ vuint32_t PCTL:2;\r
+ vuint32_t:1;\r
+ vuint32_t PARK:3;\r
+ } B;\r
+ } SGPCR3; /* General Purpose Control Register for Slave Port 3 */\r
+ uint32_t xbar_reserved6[187];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:1;\r
+ vuint32_t MSTR6:3; /* FLEXRAY */\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:1;\r
+ vuint32_t MSTR3:3; /* FEC */\r
+\r
+ vuint32_t:1;\r
+ vuint32_t MSTR2:3;\r
+ vuint32_t:1;\r
+ vuint32_t MSTR1:3;\r
+ vuint32_t:1;\r
+ vuint32_t MSTR0:3;\r
+ } B;\r
+ } MPR6; /* Master Priority Register for Slave Port 6 */\r
+\r
+ uint32_t xbar_reserved7[3];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t RO:1;\r
+ vuint32_t:21;\r
+ vuint32_t ARB:2;\r
+ vuint32_t:2;\r
+ vuint32_t PCTL:2;\r
+ vuint32_t:1;\r
+ vuint32_t PARK:3;\r
+ } B;\r
+ } SGPCR6; /* General Purpose Control Register for Slave Port 6 */\r
+\r
+ uint32_t xbar_reserved8[59];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:1;\r
+ vuint32_t MSTR6:3; /* FLEXRAY */\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:1;\r
+ vuint32_t MSTR3:3; /* FEC */\r
+\r
+ vuint32_t:1;\r
+ vuint32_t MSTR2:3;\r
+ vuint32_t:1;\r
+ vuint32_t MSTR1:3;\r
+ vuint32_t:1;\r
+ vuint32_t MSTR0:3;\r
+ } B;\r
+ } MPR7; /* Master Priority Register for Slave Port 7 */\r
+\r
+ uint32_t xbar_reserved9[3];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t RO:1;\r
+ vuint32_t:21;\r
+ vuint32_t ARB:2;\r
+ vuint32_t:2;\r
+ vuint32_t PCTL:2;\r
+ vuint32_t:1;\r
+ vuint32_t PARK:3;\r
+ } B;\r
+ } SGPCR7; /* General Purpose Control Register for Slave Port 7 */\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : ECSM */\r
+/****************************************************************************/\r
+ struct ECSM_tag {\r
+\r
+ uint32_t ecsm_reserved1[5];\r
+\r
+ uint16_t ecsm_reserved2;\r
+\r
+ union {\r
+ vuint16_t R;\r
+ } SWTCR; //Software Watchdog Timer Control\r
+\r
+ uint8_t ecsm_reserved3[3];\r
+\r
+ union {\r
+ vuint8_t R;\r
+ } SWTSR; //SWT Service Register\r
+\r
+ uint8_t ecsm_reserved4[3];\r
+\r
+ union {\r
+ vuint8_t R;\r
+ } SWTIR; //SWT Interrupt Register\r
+\r
+ uint32_t ecsm_reserved5a[1];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t FSBCR0:1;\r
+ vuint32_t FSBCR1:1;\r
+ vuint32_t FSBCR2:1;\r
+ vuint32_t FSBCR3:1;\r
+ vuint32_t FSBCR4:1;\r
+ vuint32_t FSBCR5:1;\r
+ vuint32_t FSBCR6:1;\r
+ vuint32_t FSBCR7:1;\r
+ vuint32_t RBEN:1;\r
+ vuint32_t WBEN:1;\r
+ vuint32_t ACCERR:1;\r
+ vuint32_t:21;\r
+ } B;\r
+ } FSBMCR; /* FEC System Bus Master Control Register */\r
+\r
+ uint32_t ecsm_reserved5c[6];\r
+\r
+ uint8_t ecsm_reserved6[3];\r
+\r
+ union {\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t:6;\r
+ vuint8_t ERNCR:1;\r
+ vuint8_t EFNCR:1;\r
+ } B;\r
+ } ECR; //ECC Configuration Register\r
+\r
+ uint8_t mcm_reserved8[3];\r
+\r
+ union {\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t:6;\r
+ vuint8_t RNCE:1;\r
+ vuint8_t FNCE:1;\r
+ } B;\r
+ } ESR; //ECC Status Register\r
+\r
+ uint16_t ecsm_reserved9;\r
+\r
+ union {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:6;\r
+ vuint16_t FRCNCI:1;\r
+ vuint16_t FR1NCI:1;\r
+ vuint16_t:1;\r
+ vuint16_t ERRBIT:7;\r
+ } B;\r
+ } EEGR; //ECC Error Generation Register\r
+\r
+ uint32_t ecsm_reserved10;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t FEAR:32;\r
+ } B;\r
+ } FEAR; //Flash ECC Address Register\r
+\r
+ uint16_t ecsm_reserved11;\r
+\r
+ union {\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t:4;\r
+ vuint8_t FEMR:4;\r
+ } B;\r
+ } FEMR; //Flash ECC Master Register\r
+\r
+ union {\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t WRITE:1;\r
+ vuint8_t SIZE:3;\r
+ vuint8_t PROT0:1;\r
+ vuint8_t PROT1:1;\r
+ vuint8_t PROT2:1;\r
+ vuint8_t PROT3:1;\r
+ } B;\r
+ } FEAT; //Flash ECC Attributes Register\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t FEDH:32;\r
+ } B;\r
+ } FEDRH; //Flash ECC Data High Register\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t FEDL:32;\r
+ } B;\r
+ } FEDRL; //Flash ECC Data Low Register\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t REAR:32;\r
+ } B;\r
+ } REAR; //RAM ECC Address\r
+\r
+ uint8_t ecsm_reserved12[2];\r
+\r
+ union {\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t:4;\r
+ vuint8_t REMR:4;\r
+ } B;\r
+ } REMR; //RAM ECC Master\r
+\r
+ union {\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t WRITE:1;\r
+ vuint8_t SIZE:3;\r
+ vuint8_t PROT0:1;\r
+ vuint8_t PROT1:1;\r
+ vuint8_t PROT2:1;\r
+ vuint8_t PROT3:1;\r
+ } B;\r
+ } REAT; // RAM ECC Attributes Register\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t REDH:32;\r
+ } B;\r
+ } REDRH; //RAM ECC Data High Register\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t REDL:32;\r
+ } B;\r
+ } REDRL; //RAMECC Data Low Register\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : eDMA */\r
+/****************************************************************************/\r
+ struct EDMA_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t GRP3PRI:2;\r
+ vuint32_t GRP2PRI:2;\r
+ vuint32_t GRP1PRI:2;\r
+ vuint32_t GRP0PRI:2;\r
+ vuint32_t:4;\r
+ vuint32_t ERGA:1;\r
+ vuint32_t ERCA:1;\r
+ vuint32_t EDBG:1;\r
+ vuint32_t EBW:1;\r
+ } B;\r
+ } CR; /* Control Register */\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t VLD:1;\r
+ vuint32_t:15;\r
+ vuint32_t GPE:1;\r
+ vuint32_t CPE:1;\r
+ vuint32_t ERRCHN:6;\r
+ vuint32_t SAE:1;\r
+ vuint32_t SOE:1;\r
+ vuint32_t DAE:1;\r
+ vuint32_t DOE:1;\r
+ vuint32_t NCE:1;\r
+ vuint32_t SGE:1;\r
+ vuint32_t SBE:1;\r
+ vuint32_t DBE:1;\r
+ } B;\r
+ } ESR; /* Error Status Register */\r
+ uint32_t edma_reserved_erqrh;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t ERQ31:1;\r
+ vuint32_t ERQ30:1;\r
+ vuint32_t ERQ29:1;\r
+ vuint32_t ERQ28:1;\r
+ vuint32_t ERQ27:1;\r
+ vuint32_t ERQ26:1;\r
+ vuint32_t ERQ25:1;\r
+ vuint32_t ERQ24:1;\r
+ vuint32_t ERQ23:1;\r
+ vuint32_t ERQ22:1;\r
+ vuint32_t ERQ21:1;\r
+ vuint32_t ERQ20:1;\r
+ vuint32_t ERQ19:1;\r
+ vuint32_t ERQ18:1;\r
+ vuint32_t ERQ17:1;\r
+ vuint32_t ERQ16:1;\r
+ vuint32_t ERQ15:1;\r
+ vuint32_t ERQ14:1;\r
+ vuint32_t ERQ13:1;\r
+ vuint32_t ERQ12:1;\r
+ vuint32_t ERQ11:1;\r
+ vuint32_t ERQ10:1;\r
+ vuint32_t ERQ09:1;\r
+ vuint32_t ERQ08:1;\r
+ vuint32_t ERQ07:1;\r
+ vuint32_t ERQ06:1;\r
+ vuint32_t ERQ05:1;\r
+ vuint32_t ERQ04:1;\r
+ vuint32_t ERQ03:1;\r
+ vuint32_t ERQ02:1;\r
+ vuint32_t ERQ01:1;\r
+ vuint32_t ERQ00:1;\r
+ } B;\r
+ } ERQRL; /* DMA Enable Request Register Low */\r
+ uint32_t edma_reserved_eeirh;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t EEI31:1;\r
+ vuint32_t EEI30:1;\r
+ vuint32_t EEI29:1;\r
+ vuint32_t EEI28:1;\r
+ vuint32_t EEI27:1;\r
+ vuint32_t EEI26:1;\r
+ vuint32_t EEI25:1;\r
+ vuint32_t EEI24:1;\r
+ vuint32_t EEI23:1;\r
+ vuint32_t EEI22:1;\r
+ vuint32_t EEI21:1;\r
+ vuint32_t EEI20:1;\r
+ vuint32_t EEI19:1;\r
+ vuint32_t EEI18:1;\r
+ vuint32_t EEI17:1;\r
+ vuint32_t EEI16:1;\r
+ vuint32_t EEI15:1;\r
+ vuint32_t EEI14:1;\r
+ vuint32_t EEI13:1;\r
+ vuint32_t EEI12:1;\r
+ vuint32_t EEI11:1;\r
+ vuint32_t EEI10:1;\r
+ vuint32_t EEI09:1;\r
+ vuint32_t EEI08:1;\r
+ vuint32_t EEI07:1;\r
+ vuint32_t EEI06:1;\r
+ vuint32_t EEI05:1;\r
+ vuint32_t EEI04:1;\r
+ vuint32_t EEI03:1;\r
+ vuint32_t EEI02:1;\r
+ vuint32_t EEI01:1;\r
+ vuint32_t EEI00:1;\r
+ } B;\r
+ } EEIRL; /* DMA Enable Error Interrupt Register Low */\r
+ union {\r
+ vuint8_t R;\r
+ vuint8_t B;\r
+ } SERQR; /* DMA Set Enable Request Register */\r
+ union {\r
+ vuint8_t R;\r
+ vuint8_t B;\r
+ } CERQR; /* DMA Clear Enable Request Register */\r
+ union {\r
+ vuint8_t R;\r
+ vuint8_t B;\r
+ } SEEIR; /* DMA Set Enable Error Interrupt Register */\r
+ union {\r
+ vuint8_t R;\r
+ vuint8_t B;\r
+ } CEEIR; /* DMA Clear Enable Error Interrupt Register */\r
+ union {\r
+ vuint8_t R;\r
+ vuint8_t B;\r
+ } CIRQR; /* DMA Clear Interrupt Request Register */\r
+ union {\r
+ vuint8_t R;\r
+ vuint8_t B;\r
+ } CER; /* DMA Clear error Register */\r
+ union {\r
+ vuint8_t R;\r
+ vuint8_t B;\r
+ } SSBR; /* Set Start Bit Register */\r
+ union {\r
+ vuint8_t R;\r
+ vuint8_t B;\r
+ } CDSBR; /* Clear Done Status Bit Register */\r
+ uint32_t edma_reserved_irqrh;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t INT31:1;\r
+ vuint32_t INT30:1;\r
+ vuint32_t INT29:1;\r
+ vuint32_t INT28:1;\r
+ vuint32_t INT27:1;\r
+ vuint32_t INT26:1;\r
+ vuint32_t INT25:1;\r
+ vuint32_t INT24:1;\r
+ vuint32_t INT23:1;\r
+ vuint32_t INT22:1;\r
+ vuint32_t INT21:1;\r
+ vuint32_t INT20:1;\r
+ vuint32_t INT19:1;\r
+ vuint32_t INT18:1;\r
+ vuint32_t INT17:1;\r
+ vuint32_t INT16:1;\r
+ vuint32_t INT15:1;\r
+ vuint32_t INT14:1;\r
+ vuint32_t INT13:1;\r
+ vuint32_t INT12:1;\r
+ vuint32_t INT11:1;\r
+ vuint32_t INT10:1;\r
+ vuint32_t INT09:1;\r
+ vuint32_t INT08:1;\r
+ vuint32_t INT07:1;\r
+ vuint32_t INT06:1;\r
+ vuint32_t INT05:1;\r
+ vuint32_t INT04:1;\r
+ vuint32_t INT03:1;\r
+ vuint32_t INT02:1;\r
+ vuint32_t INT01:1;\r
+ vuint32_t INT00:1;\r
+ } B;\r
+ } IRQRL; /* DMA Interrupt Request Low */\r
+ uint32_t edma_reserved_erh;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t ERR31:1;\r
+ vuint32_t ERR30:1;\r
+ vuint32_t ERR29:1;\r
+ vuint32_t ERR28:1;\r
+ vuint32_t ERR27:1;\r
+ vuint32_t ERR26:1;\r
+ vuint32_t ERR25:1;\r
+ vuint32_t ERR24:1;\r
+ vuint32_t ERR23:1;\r
+ vuint32_t ERR22:1;\r
+ vuint32_t ERR21:1;\r
+ vuint32_t ERR20:1;\r
+ vuint32_t ERR19:1;\r
+ vuint32_t ERR18:1;\r
+ vuint32_t ERR17:1;\r
+ vuint32_t ERR16:1;\r
+ vuint32_t ERR15:1;\r
+ vuint32_t ERR14:1;\r
+ vuint32_t ERR13:1;\r
+ vuint32_t ERR12:1;\r
+ vuint32_t ERR11:1;\r
+ vuint32_t ERR10:1;\r
+ vuint32_t ERR09:1;\r
+ vuint32_t ERR08:1;\r
+ vuint32_t ERR07:1;\r
+ vuint32_t ERR06:1;\r
+ vuint32_t ERR05:1;\r
+ vuint32_t ERR04:1;\r
+ vuint32_t ERR03:1;\r
+ vuint32_t ERR02:1;\r
+ vuint32_t ERR01:1;\r
+ vuint32_t ERR00:1;\r
+ } B;\r
+ } ERL; /* DMA Error Low */\r
+ uint32_t edma_reserved1[52];\r
+\r
+ union {\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t ECP:1;\r
+\r
+ vuint8_t:1;\r
+ vuint8_t GRPPRI:2;\r
+ vuint8_t CHPRI:4;\r
+\r
+ } B;\r
+ } CPR[64]; /* Channel n Priority */\r
+\r
+ uint32_t edma_reserved2[944];\r
+\r
+/****************************************************************************/\r
+/* DMA2 Transfer Control Descriptor */\r
+/****************************************************************************/\r
+\r
+ struct tcd_t { /*for "standard" format TCDs (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=0 && EDMA.EMLM=0 ) */\r
+ vuint32_t SADDR; /* source address */\r
+\r
+ vuint16_t SMOD:5; /* source address modulo */\r
+ vuint16_t SSIZE:3; /* source transfer size */\r
+ vuint16_t DMOD:5; /* destination address modulo */\r
+ vuint16_t DSIZE:3; /* destination transfer size */\r
+ vint16_t SOFF; /* signed source address offset */\r
+\r
+ vuint32_t NBYTES; /* inner (\93minor\94) byte count */\r
+\r
+ vint32_t SLAST; /* last destination address adjustment, or\r
+\r
+ scatter/gather address (if e_sg = 1) */\r
+ vuint32_t DADDR; /* destination address */\r
+\r
+ vuint16_t CITERE_LINK:1;\r
+ vuint16_t CITER:15;\r
+\r
+ vint16_t DOFF; /* signed destination address offset */\r
+\r
+ vint32_t DLAST_SGA;\r
+\r
+ vuint16_t BITERE_LINK:1; /* beginning ("major") iteration count */\r
+ vuint16_t BITER:15;\r
+\r
+ vuint16_t BWC:2; /* bandwidth control */\r
+ vuint16_t MAJORLINKCH:6; /* enable channel-to-channel link */\r
+ vuint16_t DONE:1; /* channel done */\r
+ vuint16_t ACTIVE:1; /* channel active */\r
+ vuint16_t MAJORE_LINK:1; /* enable channel-to-channel link */\r
+ vuint16_t E_SG:1; /* enable scatter/gather descriptor */\r
+ vuint16_t D_REQ:1; /* disable ipd_req when done */\r
+ vuint16_t INT_HALF:1; /* interrupt on citer = (biter >> 1) */\r
+ vuint16_t INT_MAJ:1; /* interrupt on major loop completion */\r
+ vuint16_t START:1; /* explicit channel start */\r
+ } TCD[64]; /* transfer_control_descriptor */\r
+\r
+ };\r
+\r
+ struct EDMA_TCD_alt1_tag { /*for alternate format TCDs (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=1 ) */\r
+\r
+ struct tcd_alt1_t {\r
+ vuint32_t SADDR; /* source address */\r
+\r
+ vuint16_t SMOD:5; /* source address modulo */\r
+ vuint16_t SSIZE:3; /* source transfer size */\r
+ vuint16_t DMOD:5; /* destination address modulo */\r
+ vuint16_t DSIZE:3; /* destination transfer size */\r
+ vint16_t SOFF; /* signed source address offset */\r
+\r
+ vuint32_t NBYTES; /* inner (\93minor\94) byte count */\r
+\r
+ vint32_t SLAST; /* last destination address adjustment, or\r
+\r
+ scatter/gather address (if e_sg = 1) */\r
+ vuint32_t DADDR; /* destination address */\r
+\r
+ vuint16_t CITERE_LINK:1;\r
+ vuint16_t CITERLINKCH:6;\r
+ vuint16_t CITER:9;\r
+\r
+ vint16_t DOFF; /* signed destination address offset */\r
+\r
+ vint32_t DLAST_SGA;\r
+\r
+ vuint16_t BITERE_LINK:1; /* beginning (\93major\94) iteration count */\r
+ vuint16_t BITERLINKCH:6;\r
+ vuint16_t BITER:9;\r
+\r
+ vuint16_t BWC:2; /* bandwidth control */\r
+ vuint16_t MAJORLINKCH:6; /* enable channel-to-channel link */\r
+ vuint16_t DONE:1; /* channel done */\r
+ vuint16_t ACTIVE:1; /* channel active */\r
+ vuint16_t MAJORE_LINK:1; /* enable channel-to-channel link */\r
+ vuint16_t E_SG:1; /* enable scatter/gather descriptor */\r
+ vuint16_t D_REQ:1; /* disable ipd_req when done */\r
+ vuint16_t INT_HALF:1; /* interrupt on citer = (biter >> 1) */\r
+ vuint16_t INT_MAJ:1; /* interrupt on major loop completion */\r
+ vuint16_t START:1; /* explicit channel start */\r
+ } TCD[64]; /* transfer_control_descriptor */\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : INTC */\r
+/****************************************************************************/\r
+ struct INTC_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:26;\r
+ vuint32_t VTES:1;\r
+ vuint32_t:4;\r
+ vuint32_t HVEN:1;\r
+ } B;\r
+ } MCR; /* Module Configuration Register */\r
+\r
+ int32_t INTC_reserved00;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:28;\r
+ vuint32_t PRI:4;\r
+ } B;\r
+ } CPR; /* Current Priority Register */\r
+\r
+ uint32_t intc_reserved1;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t VTBA:21;\r
+ vuint32_t INTVEC:9;\r
+ vuint32_t:2;\r
+ } B;\r
+ } IACKR; /* Interrupt Acknowledge Register */\r
+\r
+ uint32_t intc_reserved2;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:32;\r
+ } B;\r
+ } EOIR; /* End of Interrupt Register */\r
+\r
+ uint32_t intc_reserved3;\r
+\r
+ union {\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t:6;\r
+ vuint8_t SET:1;\r
+ vuint8_t CLR:1;\r
+ } B;\r
+ } SSCIR[8]; /* Software Set/Clear Interruput Register */\r
+\r
+ uint32_t intc_reserved4[6];\r
+\r
+ union {\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t:4;\r
+ vuint8_t PRI:4;\r
+ } B;\r
+ } PSR[358]; /* Software Set/Clear Interrupt Register */\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : EQADC */\r
+/****************************************************************************/\r
+ struct EQADC_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:27;\r
+ vuint32_t ESSIE:2;\r
+ vuint32_t:1;\r
+ vuint32_t DBG:2;\r
+ } B;\r
+ } MCR; /* Module Configuration Register */\r
+\r
+ int32_t EQADC_reserved00;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:6;\r
+ vuint32_t NMF:26;\r
+ } B;\r
+ } NMSFR; /* Null Message Send Format Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:28;\r
+ vuint32_t DFL:4;\r
+ } B;\r
+ } ETDFR; /* External Trigger Digital Filter Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CFPUSH:32;\r
+ } B;\r
+ } CFPR[6]; /* CFIFO Push Registers */\r
+\r
+ uint32_t eqadc_reserved1;\r
+\r
+ uint32_t eqadc_reserved2;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t RFPOP:16;\r
+ } B;\r
+ } RFPR[6]; /* Result FIFO Pop Registers */\r
+\r
+ uint32_t eqadc_reserved3;\r
+\r
+ uint32_t eqadc_reserved4;\r
+\r
+ union {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:5;\r
+ vuint16_t SSE:1;\r
+ vuint16_t CFINV:1;\r
+ vuint16_t:1;\r
+ vuint16_t MODE:4;\r
+ vuint16_t:4;\r
+ } B;\r
+ } CFCR[6]; /* CFIFO Control Registers */\r
+\r
+ uint32_t eqadc_reserved5;\r
+\r
+ union {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t NCIE:1;\r
+ vuint16_t TORIE:1;\r
+ vuint16_t PIE:1;\r
+ vuint16_t EOQIE:1;\r
+ vuint16_t CFUIE:1;\r
+ vuint16_t:1;\r
+ vuint16_t CFFE:1;\r
+ vuint16_t CFFS:1;\r
+ vuint16_t:4;\r
+ vuint16_t RFOIE:1;\r
+ vuint16_t:1;\r
+ vuint16_t RFDE:1;\r
+ vuint16_t RFDS:1;\r
+ } B;\r
+ } IDCR[6]; /* Interrupt and DMA Control Registers */\r
+\r
+ uint32_t eqadc_reserved6;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t NCF:1;\r
+ vuint32_t TORF:1;\r
+ vuint32_t PF:1;\r
+ vuint32_t EOQF:1;\r
+ vuint32_t CFUF:1;\r
+ vuint32_t SSS:1;\r
+ vuint32_t CFFF:1;\r
+ vuint32_t:5;\r
+ vuint32_t RFOF:1;\r
+ vuint32_t:1;\r
+ vuint32_t RFDF:1;\r
+ vuint32_t:1;\r
+ vuint32_t CFCTR:4;\r
+ vuint32_t TNXTPTR:4;\r
+ vuint32_t RFCTR:4;\r
+ vuint32_t POPNXTPTR:4;\r
+ } B;\r
+ } FISR[6]; /* FIFO and Interrupt Status Registers */\r
+\r
+ uint32_t eqadc_reserved7;\r
+\r
+ uint32_t eqadc_reserved8;\r
+\r
+ union {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:5;\r
+ vuint16_t TCCF:11;\r
+ } B;\r
+ } CFTCR[6]; /* CFIFO Transfer Counter Registers */\r
+\r
+ uint32_t eqadc_reserved9;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CFS0:2;\r
+ vuint32_t CFS1:2;\r
+ vuint32_t CFS2:2;\r
+ vuint32_t CFS3:2;\r
+ vuint32_t CFS4:2;\r
+ vuint32_t CFS5:2;\r
+ vuint32_t:5;\r
+ vuint32_t LCFTCB0:4;\r
+ vuint32_t TC_LCFTCB0:11;\r
+ } B;\r
+ } CFSSR0; /* CFIFO Status Register 0 */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CFS0:2;\r
+ vuint32_t CFS1:2;\r
+ vuint32_t CFS2:2;\r
+ vuint32_t CFS3:2;\r
+ vuint32_t CFS4:2;\r
+ vuint32_t CFS5:2;\r
+ vuint32_t:5;\r
+ vuint32_t LCFTCB1:4;\r
+ vuint32_t TC_LCFTCB1:11;\r
+ } B;\r
+ } CFSSR1; /* CFIFO Status Register 1 */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CFS0:2;\r
+ vuint32_t CFS1:2;\r
+ vuint32_t CFS2:2;\r
+ vuint32_t CFS3:2;\r
+ vuint32_t CFS4:2;\r
+ vuint32_t CFS5:2;\r
+ vuint32_t:4;\r
+ vuint32_t ECBNI:1;\r
+ vuint32_t LCFTSSI:4;\r
+ vuint32_t TC_LCFTSSI:11;\r
+ } B;\r
+ } CFSSR2; /* CFIFO Status Register 2 */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CFS0:2;\r
+ vuint32_t CFS1:2;\r
+ vuint32_t CFS2:2;\r
+ vuint32_t CFS3:2;\r
+ vuint32_t CFS4:2;\r
+ vuint32_t CFS5:2;\r
+ vuint32_t:20;\r
+ } B;\r
+ } CFSR;\r
+\r
+ uint32_t eqadc_reserved11;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:21;\r
+ vuint32_t MDT:3;\r
+ vuint32_t:4;\r
+ vuint32_t BR:4;\r
+ } B;\r
+ } SSICR; /* SSI Control Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t RDV:1;\r
+ vuint32_t:5;\r
+ vuint32_t RDATA:26;\r
+ } B;\r
+ } SSIRDR; /* SSI Recieve Data Register */\r
+\r
+ uint32_t eqadc_reserved12[17];\r
+\r
+ struct {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:32;\r
+ } B;\r
+ } R[4];\r
+\r
+ uint32_t eqadc_reserved13[12];\r
+\r
+ } CF[6];\r
+\r
+ uint32_t eqadc_reserved14[32];\r
+\r
+ struct {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:32;\r
+ } B;\r
+ } R[4];\r
+\r
+ uint32_t eqadc_reserved15[12];\r
+\r
+ } RF[6];\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : DSPI */\r
+/****************************************************************************/\r
+ struct DSPI_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MSTR:1;\r
+ vuint32_t CONT_SCKE:1;\r
+ vuint32_t DCONF:2;\r
+ vuint32_t FRZ:1;\r
+ vuint32_t MTFE:1;\r
+ vuint32_t PCSSE:1;\r
+ vuint32_t ROOE:1;\r
+ vuint32_t:2;\r
+ vuint32_t PCSIS5:1;\r
+ vuint32_t PCSIS4:1;\r
+ vuint32_t PCSIS3:1;\r
+ vuint32_t PCSIS2:1;\r
+ vuint32_t PCSIS1:1;\r
+ vuint32_t PCSIS0:1;\r
+ vuint32_t DOZE:1;\r
+ vuint32_t MDIS:1;\r
+ vuint32_t DIS_TXF:1;\r
+ vuint32_t DIS_RXF:1;\r
+ vuint32_t CLR_TXF:1;\r
+ vuint32_t CLR_RXF:1;\r
+ vuint32_t SMPL_PT:2;\r
+ vuint32_t:7;\r
+ vuint32_t HALT:1;\r
+ } B;\r
+ } MCR; /* Module Configuration Register */\r
+\r
+ uint32_t dspi_reserved1;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TCNT:16;\r
+ vuint32_t:16;\r
+ } B;\r
+ } TCR;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DBR:1;\r
+ vuint32_t FMSZ:4;\r
+ vuint32_t CPOL:1;\r
+ vuint32_t CPHA:1;\r
+ vuint32_t LSBFE:1;\r
+ vuint32_t PCSSCK:2;\r
+ vuint32_t PASC:2;\r
+ vuint32_t PDT:2;\r
+ vuint32_t PBR:2;\r
+ vuint32_t CSSCK:4;\r
+ vuint32_t ASC:4;\r
+ vuint32_t DT:4;\r
+ vuint32_t BR:4;\r
+ } B;\r
+ } CTAR[8]; /* Clock and Transfer Attributes Registers */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TCF:1;\r
+ vuint32_t TXRXS:1;\r
+ vuint32_t:1;\r
+ vuint32_t EOQF:1;\r
+ vuint32_t TFUF:1;\r
+ vuint32_t:1;\r
+ vuint32_t TFFF:1;\r
+ vuint32_t:5;\r
+ vuint32_t RFOF:1;\r
+ vuint32_t:1;\r
+ vuint32_t RFDF:1;\r
+ vuint32_t:1;\r
+ vuint32_t TXCTR:4;\r
+ vuint32_t TXNXTPTR:4;\r
+ vuint32_t RXCTR:4;\r
+ vuint32_t POPNXTPTR:4;\r
+ } B;\r
+ } SR; /* Status Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TCFRE:1;\r
+ vuint32_t:2;\r
+ vuint32_t EOQFRE:1;\r
+ vuint32_t TFUFRE:1;\r
+ vuint32_t:1;\r
+ vuint32_t TFFFRE:1;\r
+ vuint32_t TFFFDIRS:1;\r
+ vuint32_t:4;\r
+ vuint32_t RFOFRE:1;\r
+ vuint32_t:1;\r
+ vuint32_t RFDFRE:1;\r
+ vuint32_t RFDFDIRS:1;\r
+ vuint32_t:16;\r
+ } B;\r
+ } RSER; /* DMA/Interrupt Request Select and Enable Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CONT:1;\r
+ vuint32_t CTAS:3;\r
+ vuint32_t EOQ:1;\r
+ vuint32_t CTCNT:1;\r
+ vuint32_t:4;\r
+ vuint32_t PCS5:1;\r
+ vuint32_t PCS4:1;\r
+ vuint32_t PCS3:1;\r
+ vuint32_t PCS2:1;\r
+ vuint32_t PCS1:1;\r
+ vuint32_t PCS0:1;\r
+ vuint32_t TXDATA:16;\r
+ } B;\r
+ } PUSHR; /* PUSH TX FIFO Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t RXDATA:16;\r
+ } B;\r
+ } POPR; /* POP RX FIFO Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TXCMD:16;\r
+ vuint32_t TXDATA:16;\r
+ } B;\r
+ } TXFR[4]; /* Transmit FIFO Registers */\r
+\r
+ vuint32_t DSPI_reserved_txf[12];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t RXDATA:16;\r
+ } B;\r
+ } RXFR[4]; /* Transmit FIFO Registers */\r
+\r
+ vuint32_t DSPI_reserved_rxf[12];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MTOE:1;\r
+ vuint32_t:1;\r
+ vuint32_t MTOCNT:6;\r
+ vuint32_t:4;\r
+ vuint32_t TXSS:1;\r
+ vuint32_t TPOL:1;\r
+ vuint32_t TRRE:1;\r
+ vuint32_t CID:1;\r
+ vuint32_t DCONT:1;\r
+ vuint32_t DSICTAS:3;\r
+ vuint32_t:6;\r
+ vuint32_t DPCS5:1;\r
+ vuint32_t DPCS4:1;\r
+ vuint32_t DPCS3:1;\r
+ vuint32_t DPCS2:1;\r
+ vuint32_t DPCS1:1;\r
+ vuint32_t DPCS0:1;\r
+ } B;\r
+ } DSICR; /* DSI Configuration Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t SER_DATA:16;\r
+ } B;\r
+ } SDR; /* DSI Serialization Data Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t ASER_DATA:16;\r
+ } B;\r
+ } ASDR; /* DSI Alternate Serialization Data Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t COMP_DATA:16;\r
+ } B;\r
+ } COMPR; /* DSI Transmit Comparison Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t DESER_DATA:16;\r
+ } B;\r
+ } DDR; /* DSI deserialization Data Register */\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : eSCI */\r
+/****************************************************************************/\r
+ struct ESCI_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:3;\r
+ vuint32_t SBR:13;\r
+ vuint32_t LOOPS:1;\r
+ vuint32_t SCISDOZ:1;\r
+ vuint32_t RSRC:1;\r
+ vuint32_t M:1;\r
+ vuint32_t WAKE:1;\r
+ vuint32_t ILT:1;\r
+ vuint32_t PE:1;\r
+ vuint32_t PT:1;\r
+ vuint32_t TIE:1;\r
+ vuint32_t TCIE:1;\r
+ vuint32_t RIE:1;\r
+ vuint32_t ILIE:1;\r
+ vuint32_t TE:1;\r
+ vuint32_t RE:1;\r
+ vuint32_t RWU:1;\r
+ vuint32_t SBK:1;\r
+ } B;\r
+ } CR1; /* Control Register 1 */\r
+\r
+ union {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t MDIS:1;\r
+ vuint16_t FBR:1;\r
+ vuint16_t BSTP:1;\r
+ vuint16_t IEBERR:1;\r
+ vuint16_t RXDMA:1;\r
+ vuint16_t TXDMA:1;\r
+ vuint16_t BRK13:1;\r
+ vuint16_t:1;\r
+ vuint16_t BESM13:1;\r
+ vuint16_t SBSTP:1;\r
+ vuint16_t:2;\r
+ vuint16_t ORIE:1;\r
+ vuint16_t NFIE:1;\r
+ vuint16_t FEIE:1;\r
+ vuint16_t PFIE:1;\r
+ } B;\r
+ } CR2; /* Control Register 2 */\r
+\r
+ union {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t R8:1;\r
+ vuint16_t T8:1;\r
+ vuint16_t:6;\r
+ vuint8_t D;\r
+ } B;\r
+ } DR; /* Data Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TDRE:1;\r
+ vuint32_t TC:1;\r
+ vuint32_t RDRF:1;\r
+ vuint32_t IDLE:1;\r
+ vuint32_t OR:1;\r
+ vuint32_t NF:1;\r
+ vuint32_t FE:1;\r
+ vuint32_t PF:1;\r
+ vuint32_t:3;\r
+ vuint32_t BERR:1;\r
+ vuint32_t:3;\r
+ vuint32_t RAF:1;\r
+ vuint32_t RXRDY:1;\r
+ vuint32_t TXRDY:1;\r
+ vuint32_t LWAKE:1;\r
+ vuint32_t STO:1;\r
+ vuint32_t PBERR:1;\r
+ vuint32_t CERR:1;\r
+ vuint32_t CKERR:1;\r
+ vuint32_t FRC:1;\r
+ vuint32_t:7;\r
+ vuint32_t OVFL:1;\r
+ } B;\r
+ } SR; /* Status Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t LRES:1;\r
+ vuint32_t WU:1;\r
+ vuint32_t WUD0:1;\r
+ vuint32_t WUD1:1;\r
+ vuint32_t LDBG:1;\r
+ vuint32_t DSF:1;\r
+ vuint32_t PRTY:1;\r
+ vuint32_t LIN:1;\r
+ vuint32_t RXIE:1;\r
+ vuint32_t TXIE:1;\r
+ vuint32_t WUIE:1;\r
+ vuint32_t STIE:1;\r
+ vuint32_t PBIE:1;\r
+ vuint32_t CIE:1;\r
+ vuint32_t CKIE:1;\r
+ vuint32_t FCIE:1;\r
+ vuint32_t:7;\r
+ vuint32_t OFIE:1;\r
+ vuint32_t:8;\r
+ } B;\r
+ } LCR; /* LIN Control Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } LTR; /* LIN Transmit Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } LRR; /* LIN Recieve Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } LPR; /* LIN CRC Polynom Register */\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : FlexCAN */\r
+/****************************************************************************/\r
+ struct FLEXCAN2_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MDIS:1;\r
+ vuint32_t FRZ:1;\r
+ vuint32_t:1;\r
+ vuint32_t HALT:1;\r
+ vuint32_t NOTRDY:1;\r
+ vuint32_t:1;\r
+ vuint32_t SOFTRST:1;\r
+ vuint32_t FRZACK:1;\r
+ vuint32_t:1;\r
+ vuint32_t:1;\r
+\r
+ vuint32_t WRNEN:1;\r
+\r
+ vuint32_t MDISACK:1;\r
+ vuint32_t:1;\r
+ vuint32_t:1;\r
+\r
+ vuint32_t SRXDIS:1;\r
+ vuint32_t MBFEN:1;\r
+ vuint32_t:10;\r
+\r
+ vuint32_t MAXMB:6;\r
+ } B;\r
+ } MCR; /* Module Configuration Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PRESDIV:8;\r
+ vuint32_t RJW:2;\r
+ vuint32_t PSEG1:3;\r
+ vuint32_t PSEG2:3;\r
+ vuint32_t BOFFMSK:1;\r
+ vuint32_t ERRMSK:1;\r
+ vuint32_t CLKSRC:1;\r
+ vuint32_t LPB:1;\r
+\r
+ vuint32_t TWRNMSK:1;\r
+ vuint32_t RWRNMSK:1;\r
+ vuint32_t:2;\r
+\r
+ vuint32_t SMP:1;\r
+ vuint32_t BOFFREC:1;\r
+ vuint32_t TSYN:1;\r
+ vuint32_t LBUF:1;\r
+ vuint32_t LOM:1;\r
+ vuint32_t PROPSEG:3;\r
+ } B;\r
+ } CR; /* Control Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } TIMER; /* Free Running Timer */\r
+ int32_t FLEXCAN_reserved00;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:3;\r
+ vuint32_t MI:29;\r
+ } B;\r
+ } RXGMASK; /* RX Global Mask */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:3;\r
+ vuint32_t MI:29;\r
+ } B;\r
+ } RX14MASK; /* RX 14 Mask */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:3;\r
+ vuint32_t MI:29;\r
+ } B;\r
+ } RX15MASK; /* RX 15 Mask */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t RXECNT:8;\r
+ vuint32_t TXECNT:8;\r
+ } B;\r
+ } ECR; /* Error Counter Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:14;\r
+\r
+ vuint32_t TWRNINT:1;\r
+ vuint32_t RWRNINT:1;\r
+\r
+ vuint32_t BIT1ERR:1;\r
+ vuint32_t BIT0ERR:1;\r
+ vuint32_t ACKERR:1;\r
+ vuint32_t CRCERR:1;\r
+ vuint32_t FRMERR:1;\r
+ vuint32_t STFERR:1;\r
+ vuint32_t TXWRN:1;\r
+ vuint32_t RXWRN:1;\r
+ vuint32_t IDLE:1;\r
+ vuint32_t TXRX:1;\r
+ vuint32_t FLTCONF:2;\r
+ vuint32_t:1;\r
+ vuint32_t BOFFINT:1;\r
+ vuint32_t ERRINT:1;\r
+ vuint32_t:1;\r
+ } B;\r
+ } ESR; /* Error and Status Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BUF63M:1;\r
+ vuint32_t BUF62M:1;\r
+ vuint32_t BUF61M:1;\r
+ vuint32_t BUF60M:1;\r
+ vuint32_t BUF59M:1;\r
+ vuint32_t BUF58M:1;\r
+ vuint32_t BUF57M:1;\r
+ vuint32_t BUF56M:1;\r
+ vuint32_t BUF55M:1;\r
+ vuint32_t BUF54M:1;\r
+ vuint32_t BUF53M:1;\r
+ vuint32_t BUF52M:1;\r
+ vuint32_t BUF51M:1;\r
+ vuint32_t BUF50M:1;\r
+ vuint32_t BUF49M:1;\r
+ vuint32_t BUF48M:1;\r
+ vuint32_t BUF47M:1;\r
+ vuint32_t BUF46M:1;\r
+ vuint32_t BUF45M:1;\r
+ vuint32_t BUF44M:1;\r
+ vuint32_t BUF43M:1;\r
+ vuint32_t BUF42M:1;\r
+ vuint32_t BUF41M:1;\r
+ vuint32_t BUF40M:1;\r
+ vuint32_t BUF39M:1;\r
+ vuint32_t BUF38M:1;\r
+ vuint32_t BUF37M:1;\r
+ vuint32_t BUF36M:1;\r
+ vuint32_t BUF35M:1;\r
+ vuint32_t BUF34M:1;\r
+ vuint32_t BUF33M:1;\r
+ vuint32_t BUF32M:1;\r
+ } B;\r
+ } IMRH; /* Interruput Masks Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BUF31M:1;\r
+ vuint32_t BUF30M:1;\r
+ vuint32_t BUF29M:1;\r
+ vuint32_t BUF28M:1;\r
+ vuint32_t BUF27M:1;\r
+ vuint32_t BUF26M:1;\r
+ vuint32_t BUF25M:1;\r
+ vuint32_t BUF24M:1;\r
+ vuint32_t BUF23M:1;\r
+ vuint32_t BUF22M:1;\r
+ vuint32_t BUF21M:1;\r
+ vuint32_t BUF20M:1;\r
+ vuint32_t BUF19M:1;\r
+ vuint32_t BUF18M:1;\r
+ vuint32_t BUF17M:1;\r
+ vuint32_t BUF16M:1;\r
+ vuint32_t BUF15M:1;\r
+ vuint32_t BUF14M:1;\r
+ vuint32_t BUF13M:1;\r
+ vuint32_t BUF12M:1;\r
+ vuint32_t BUF11M:1;\r
+ vuint32_t BUF10M:1;\r
+ vuint32_t BUF09M:1;\r
+ vuint32_t BUF08M:1;\r
+ vuint32_t BUF07M:1;\r
+ vuint32_t BUF06M:1;\r
+ vuint32_t BUF05M:1;\r
+ vuint32_t BUF04M:1;\r
+ vuint32_t BUF03M:1;\r
+ vuint32_t BUF02M:1;\r
+ vuint32_t BUF01M:1;\r
+ vuint32_t BUF00M:1;\r
+ } B;\r
+ } IMRL; /* Interruput Masks Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BUF63I:1;\r
+ vuint32_t BUF62I:1;\r
+ vuint32_t BUF61I:1;\r
+ vuint32_t BUF60I:1;\r
+ vuint32_t BUF59I:1;\r
+ vuint32_t BUF58I:1;\r
+ vuint32_t BUF57I:1;\r
+ vuint32_t BUF56I:1;\r
+ vuint32_t BUF55I:1;\r
+ vuint32_t BUF54I:1;\r
+ vuint32_t BUF53I:1;\r
+ vuint32_t BUF52I:1;\r
+ vuint32_t BUF51I:1;\r
+ vuint32_t BUF50I:1;\r
+ vuint32_t BUF49I:1;\r
+ vuint32_t BUF48I:1;\r
+ vuint32_t BUF47I:1;\r
+ vuint32_t BUF46I:1;\r
+ vuint32_t BUF45I:1;\r
+ vuint32_t BUF44I:1;\r
+ vuint32_t BUF43I:1;\r
+ vuint32_t BUF42I:1;\r
+ vuint32_t BUF41I:1;\r
+ vuint32_t BUF40I:1;\r
+ vuint32_t BUF39I:1;\r
+ vuint32_t BUF38I:1;\r
+ vuint32_t BUF37I:1;\r
+ vuint32_t BUF36I:1;\r
+ vuint32_t BUF35I:1;\r
+ vuint32_t BUF34I:1;\r
+ vuint32_t BUF33I:1;\r
+ vuint32_t BUF32I:1;\r
+ } B;\r
+ } IFRH; /* Interruput Flag Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BUF31I:1;\r
+ vuint32_t BUF30I:1;\r
+ vuint32_t BUF29I:1;\r
+ vuint32_t BUF28I:1;\r
+ vuint32_t BUF27I:1;\r
+ vuint32_t BUF26I:1;\r
+ vuint32_t BUF25I:1;\r
+ vuint32_t BUF24I:1;\r
+ vuint32_t BUF23I:1;\r
+ vuint32_t BUF22I:1;\r
+ vuint32_t BUF21I:1;\r
+ vuint32_t BUF20I:1;\r
+ vuint32_t BUF19I:1;\r
+ vuint32_t BUF18I:1;\r
+ vuint32_t BUF17I:1;\r
+ vuint32_t BUF16I:1;\r
+ vuint32_t BUF15I:1;\r
+ vuint32_t BUF14I:1;\r
+ vuint32_t BUF13I:1;\r
+ vuint32_t BUF12I:1;\r
+ vuint32_t BUF11I:1;\r
+ vuint32_t BUF10I:1;\r
+ vuint32_t BUF09I:1;\r
+ vuint32_t BUF08I:1;\r
+ vuint32_t BUF07I:1;\r
+ vuint32_t BUF06I:1;\r
+ vuint32_t BUF05I:1;\r
+ vuint32_t BUF04I:1;\r
+ vuint32_t BUF03I:1;\r
+ vuint32_t BUF02I:1;\r
+ vuint32_t BUF01I:1;\r
+ vuint32_t BUF00I:1;\r
+ } B;\r
+ } IFRL; /* Interruput Flag Register */\r
+\r
+ uint32_t flexcan2_reserved2[19];\r
+\r
+ struct canbuf_t {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:4;\r
+ vuint32_t CODE:4;\r
+ vuint32_t:1;\r
+ vuint32_t SRR:1;\r
+ vuint32_t IDE:1;\r
+ vuint32_t RTR:1;\r
+ vuint32_t LENGTH:4;\r
+ vuint32_t TIMESTAMP:16;\r
+ } B;\r
+ } CS;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:3;\r
+ vuint32_t STD_ID:11;\r
+ vuint32_t EXT_ID:18;\r
+ } B;\r
+ } ID;\r
+\r
+ union {\r
+ vuint8_t B[8]; /* Data buffer in Bytes (8 bits) */\r
+ vuint16_t H[4]; /* Data buffer in Half-words (16 bits) */\r
+ vuint32_t W[2]; /* Data buffer in words (32 bits) */\r
+ vuint32_t R[2]; /* Data buffer in words (32 bits) */\r
+ } DATA;\r
+\r
+ } BUF[64];\r
+\r
+ uint32_t flexcan2_reserved3[256];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:3;\r
+ vuint32_t MI:29;\r
+ } B;\r
+ } RXIMR[64]; /* RX Individual Mask Registers */\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : FEC */\r
+/****************************************************************************/\r
+ struct FEC_tag {\r
+\r
+ uint32_t fec_reserved_start[0x1];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t HBERR:1;\r
+ vuint32_t BABR:1;\r
+ vuint32_t BABT:1;\r
+ vuint32_t GRA:1;\r
+ vuint32_t TXF:1;\r
+ vuint32_t TXB:1;\r
+ vuint32_t RXF:1;\r
+ vuint32_t RXB:1;\r
+ vuint32_t MII:1;\r
+ vuint32_t EBERR:1;\r
+ vuint32_t LC:1;\r
+ vuint32_t RL:1;\r
+ vuint32_t UN:1;\r
+ vuint32_t:19;\r
+ } B;\r
+ } EIR; /* Interrupt Event Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t HBERRM:1;\r
+ vuint32_t BABRM:1;\r
+ vuint32_t BABTM:1;\r
+ vuint32_t GRAM:1;\r
+ vuint32_t TXFM:1;\r
+ vuint32_t TXBM:1;\r
+ vuint32_t RXFM:1;\r
+ vuint32_t RXBM:1;\r
+ vuint32_t MIIM:1;\r
+ vuint32_t EBERRM:1;\r
+ vuint32_t LCM:1;\r
+ vuint32_t RLM:1;\r
+ vuint32_t UNM:1;\r
+ vuint32_t:19;\r
+ } B;\r
+ } EIMR; /* Interrupt Mask Register */\r
+\r
+ uint32_t fec_reserved_eimr;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:7;\r
+ vuint32_t R_DES_ACTIVE:1;\r
+ vuint32_t:24;\r
+ } B;\r
+ } RDAR; /* Receive Descriptor Active Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:7;\r
+ vuint32_t X_DES_ACTIVE:1;\r
+ vuint32_t:24;\r
+ } B;\r
+ } TDAR; /* Transmit Descriptor Active Register */\r
+\r
+ uint32_t fec_reserved_tdar[3];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:30;\r
+ vuint32_t ETHER_EN:1;\r
+ vuint32_t RESET:1;\r
+ } B;\r
+ } ECR; /* Ethernet Control Register */\r
+\r
+ uint32_t fec_reserved_ecr[6];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t ST:2;\r
+ vuint32_t CP:2;\r
+ vuint32_t PA:5;\r
+ vuint32_t RA:5;\r
+ vuint32_t TA:2;\r
+ vuint32_t DATA:16;\r
+ } B;\r
+ } MDATA; /* MII Data Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:24;\r
+ vuint32_t DIS_PREAMBLE:1;\r
+ vuint32_t MII_SPEED:6;\r
+ vuint32_t:1;\r
+ } B;\r
+ } MSCR; /* MII Speed Control Register */\r
+\r
+ uint32_t fec_reserved_mscr[7];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MIB_DISABLE:1;\r
+ vuint32_t MIB_IDLE:1;\r
+ vuint32_t:30;\r
+ } B;\r
+ } MIBC; /* MIB Control Register */\r
+\r
+ uint32_t fec_reserved_mibc[7];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:5;\r
+ vuint32_t MAX_FL:11;\r
+ vuint32_t:10;\r
+ vuint32_t FCE:1;\r
+ vuint32_t BC_REJ:1;\r
+ vuint32_t PROM:1;\r
+ vuint32_t MII_MODE:1;\r
+ vuint32_t DRT:1;\r
+ vuint32_t LOOP:1;\r
+ } B;\r
+ } RCR; /* Receive Control Register */\r
+\r
+ uint32_t fec_reserved_rcr[15];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:27;\r
+ vuint32_t RFC_PAUSE:1;\r
+ vuint32_t TFC_PAUSE:1;\r
+ vuint32_t FDEN:1;\r
+ vuint32_t HBC:1;\r
+ vuint32_t GTS:1;\r
+ } B;\r
+ } TCR; /* Transmit Control Register */\r
+\r
+ uint32_t fec_reserved_tcr[7];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PADDR1:32;\r
+ } B;\r
+ } PALR; /* Physical Address Low Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PADDR2:16;\r
+ vuint32_t TYPE:16;\r
+ } B;\r
+ } PAUR; /* Physical Address High + Type Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t OPCODE:16;\r
+ vuint32_t PAUSE_DUR:16;\r
+ } B;\r
+ } OPD; /* Opcode/Pause Duration Register */\r
+\r
+ uint32_t fec_reserved_opd[10];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t IADDR1:32;\r
+ } B;\r
+ } IAUR; /* Descriptor Individual Upper Address Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t IADDR2:32;\r
+ } B;\r
+ } IALR; /* Descriptor Individual Lower Address Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t GADDR1:32;\r
+ } B;\r
+ } GAUR; /* Descriptor Group Upper Address Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t GADDR2:32;\r
+ } B;\r
+ } GALR; /* Descriptor Group Lower Address Register */\r
+\r
+ uint32_t fec_reserved_galr[7];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:30;\r
+ vuint32_t X_WMRK:2;\r
+ } B;\r
+ } TFWR; /* FIFO Transmit FIFO Watermark Register */\r
+\r
+ uint32_t fec_reserved_tfwr;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:22;\r
+ vuint32_t R_BOUND:8;\r
+ vuint32_t:2;\r
+ } B;\r
+ } FRBR; /* FIFO Receive Bound Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:22;\r
+ vuint32_t R_FSTART:8;\r
+ vuint32_t:2;\r
+ } B;\r
+ } FRSR; /* FIFO Receive Start Register */\r
+\r
+ uint32_t fec_reserved_frsr[11];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t R_DES_START:30;\r
+ vuint32_t:2;\r
+ } B;\r
+ } ERDSR; /* Receive Descriptor Ring Start Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t X_DES_START:30;\r
+ vuint32_t:2;\r
+ } B;\r
+ } ETDSR; /* Transmit Descriptor Ring Start Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:21;\r
+ vuint32_t R_BUF_SIZE:7;\r
+ vuint32_t:4;\r
+ } B;\r
+ } EMRBR; /* Receive Buffer Size Register */\r
+\r
+ uint32_t fec_reserved_emrbr[29];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } RMON_T_DROP; /* Count of frames not counted correctly */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } RMON_T_PACKETS; /* RMON Tx packet count */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } RMON_T_BC_PKT; /* RMON Tx Broadcast Packets */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } RMON_T_MC_PKT; /* RMON Tx Multicast Packets */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } RMON_T_CRC_ALIGN; /* RMON Tx Packets w CRC/Align error */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } RMON_T_UNDERSIZE; /* RMON Tx Packets < 64 bytes, good crc */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } RMON_T_OVERSIZE; /* RMON Tx Packets > MAX_FL bytes, good crc */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } RMON_T_FRAG; /* RMON Tx Packets < 64 bytes, bad crc */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } RMON_T_JAB; /* RMON Tx Packets > MAX_FL bytes, bad crc */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } RMON_T_COL; /* RMON Tx collision count */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } RMON_T_P64; /* RMON Tx 64 byte packets */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } RMON_T_P65TO127; /* RMON Tx 65 to 127 byte packets */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } RMON_T_P128TO255; /* RMON Tx 128 to 255 byte packets */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } RMON_T_P256TO511; /* RMON Tx 256 to 511 byte packets */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } RMON_T_P512TO1023; /* RMON Tx 512 to 1023 byte packets */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } RMON_T_P1024TO2047; /* RMON Tx 1024 to 2047 byte packets */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } RMON_T_P_GTE2048; /* RMON Tx packets w > 2048 bytes */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } RMON_T_OCTETS; /* RMON Tx Octets */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } IEEE_T_DROP; /* Count of frames not counted correctly */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } IEEE_T_FRAME_OK; /* Frames Transmitted OK */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } IEEE_T_1COL; /* Frames Transmitted with Single Collision */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } IEEE_T_MCOL; /* Frames Transmitted with Multiple Collisions */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } IEEE_T_DEF; /* Frames Transmitted after Deferral Delay */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } IEEE_T_LCOL; /* Frames Transmitted with Late Collision */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } IEEE_T_EXCOL; /* Frames Transmitted with Excessive Collisions */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } IEEE_T_MACERR; /* Frames Transmitted with Tx FIFO Underrun */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } IEEE_T_CSERR; /* Frames Transmitted with Carrier Sense Error */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } IEEE_T_SQE; /* Frames Transmitted with SQE Error */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } IEEE_T_FDXFC; /* Flow Control Pause frames transmitted */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } IEEE_T_OCTETS_OK; /* Octet count for Frames Transmitted w/o Error */\r
+\r
+ uint32_t fec_reserved_rmon_t_octets_ok[2];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } RMON_R_DROP; /* Count of frames not counted correctly */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } RMON_R_PACKETS; /* RMON Rx packet count */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } RMON_R_BC_PKT; /* RMON Rx Broadcast Packets */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } RMON_R_MC_PKT; /* RMON Rx Multicast Packets */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } RMON_R_CRC_ALIGN; /* RMON Rx Packets w CRC/Align error */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } RMON_R_UNDERSIZE; /* RMON Rx Packets < 64 bytes, good crc */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } RMON_R_OVERSIZE; /* RMON Rx Packets > MAX_FL bytes, good crc */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } RMON_R_FRAG; /* RMON Rx Packets < 64 bytes, bad crc */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } RMON_R_JAB; /* RMON Rx Packets > MAX_FL bytes, bad crc */\r
+\r
+ uint32_t fec_reserved_rmon_r_jab;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } RMON_R_P64; /* RMON Rx 64 byte packets */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } RMON_R_P65TO127; /* RMON Rx 65 to 127 byte packets */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } RMON_R_P128TO255; /* RMON Rx 128 to 255 byte packets */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } RMON_R_P256TO511; /* RMON Rx 256 to 511 byte packets */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } RMON_R_P512TO1023; /* RMON Rx 512 to 1023 byte packets */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } RMON_R_P1024TO2047; /* RMON Rx 1024 to 2047 byte packets */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } RMON_R_P_GTE2048; /* RMON Rx packets w > 2048 bytes */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } RMON_R_OCTETS; /* RMON Rx Octets */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } IEEE_R_DROP; /* Count of frames not counted correctly */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } IEEE_R_FRAME_OK; /* Frames Received OK */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } IEEE_R_CRC; /* Frames Received with CRC Error */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } IEEE_R_ALIGN; /* Frames Received with Alignment Error */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } IEEE_R_MACERR; /* Receive Fifo Overflow count */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } IEEE_R_FDXFC; /* Flow Control Pause frames received */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } IEEE_R_OCTETS_OK; /* Octet count for Frames Rcvd w/o Error */\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : FlexRay */\r
+/****************************************************************************/\r
+\r
+ typedef union uMVR {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t CHIVER:8; /* CHI Version Number */\r
+ vuint16_t PEVER:8; /* PE Version Number */\r
+ } B;\r
+ } MVR_t;\r
+\r
+ typedef union uMCR {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t MEN:1; /* module enable */\r
+ vuint16_t:1;\r
+ vuint16_t SCMD:1; /* single channel mode */\r
+ vuint16_t CHB:1; /* channel B enable */\r
+ vuint16_t CHA:1; /* channel A enable */\r
+ vuint16_t SFFE:1; /* synchronization frame filter enable */\r
+ vuint16_t:5;\r
+ vuint16_t CLKSEL:1; /* protocol engine clock source select */\r
+ vuint16_t PRESCALE:3; /* protocol engine clock prescaler */\r
+ vuint16_t:1;\r
+ } B;\r
+ } MCR_t;\r
+ typedef union uSTBSCR {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t WMD:1; /* write mode */\r
+ vuint16_t STBSSEL:7; /* strobe signal select */\r
+ vuint16_t:3;\r
+ vuint16_t ENB:1; /* strobe signal enable */\r
+ vuint16_t:2;\r
+ vuint16_t STBPSEL:2; /* strobe port select */\r
+ } B;\r
+ } STBSCR_t;\r
+ typedef union uSTBPCR {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:12;\r
+ vuint16_t STB3EN:1; /* strobe port enable */\r
+ vuint16_t STB2EN:1; /* strobe port enable */\r
+ vuint16_t STB1EN:1; /* strobe port enable */\r
+ vuint16_t STB0EN:1; /* strobe port enable */\r
+ } B;\r
+ } STBPCR_t;\r
+\r
+ typedef union uMBDSR {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:1;\r
+ vuint16_t MBSEG2DS:7; /* message buffer segment 2 data size */\r
+ vuint16_t:1;\r
+ vuint16_t MBSEG1DS:7; /* message buffer segment 1 data size */\r
+ } B;\r
+ } MBDSR_t;\r
+ typedef union uMBSSUTR {\r
+ vuint16_t R;\r
+ struct {\r
+\r
+ vuint16_t:1;\r
+ vuint16_t LAST_MB_SEG1:7; /* last message buffer control register for message buffer segment 1 */\r
+ vuint16_t:1;\r
+ vuint16_t LAST_MB_UTIL:7; /* last message buffer utilized */\r
+ } B;\r
+ } MBSSUTR_t;\r
+\r
+ typedef union uPOCR {\r
+ vuint16_t R;\r
+ vuint8_t byte[2];\r
+ struct {\r
+ vuint16_t WME:1; /* write mode external correction command */\r
+ vuint16_t:3;\r
+ vuint16_t EOC_AP:2; /* external offset correction application */\r
+ vuint16_t ERC_AP:2; /* external rate correction application */\r
+ vuint16_t BSY:1; /* command write busy / write mode command */\r
+ vuint16_t:3;\r
+ vuint16_t POCCMD:4; /* protocol command */\r
+ } B;\r
+ } POCR_t;\r
+/* protocol commands */\r
+ typedef union uGIFER {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t MIF:1; /* module interrupt flag */\r
+ vuint16_t PRIF:1; /* protocol interrupt flag */\r
+ vuint16_t CHIF:1; /* CHI interrupt flag */\r
+ vuint16_t WKUPIF:1; /* wakeup interrupt flag */\r
+ vuint16_t FNEBIF:1; /* receive FIFO channel B not empty interrupt flag */\r
+ vuint16_t FNEAIF:1; /* receive FIFO channel A not empty interrupt flag */\r
+ vuint16_t RBIF:1; /* receive message buffer interrupt flag */\r
+ vuint16_t TBIF:1; /* transmit buffer interrupt flag */\r
+ vuint16_t MIE:1; /* module interrupt enable */\r
+ vuint16_t PRIE:1; /* protocol interrupt enable */\r
+ vuint16_t CHIE:1; /* CHI interrupt enable */\r
+ vuint16_t WKUPIE:1; /* wakeup interrupt enable */\r
+ vuint16_t FNEBIE:1; /* receive FIFO channel B not empty interrupt enable */\r
+ vuint16_t FNEAIE:1; /* receive FIFO channel A not empty interrupt enable */\r
+ vuint16_t RBIE:1; /* receive message buffer interrupt enable */\r
+ vuint16_t TBIE:1; /* transmit buffer interrupt enable */\r
+ } B;\r
+ } GIFER_t;\r
+ typedef union uPIFR0 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t FATLIF:1; /* fatal protocol error interrupt flag */\r
+ vuint16_t INTLIF:1; /* internal protocol error interrupt flag */\r
+ vuint16_t ILCFIF:1; /* illegal protocol configuration flag */\r
+ vuint16_t CSAIF:1; /* cold start abort interrupt flag */\r
+ vuint16_t MRCIF:1; /* missing rate correctio interrupt flag */\r
+ vuint16_t MOCIF:1; /* missing offset correctio interrupt flag */\r
+ vuint16_t CCLIF:1; /* clock correction limit reached interrupt flag */\r
+ vuint16_t MXSIF:1; /* max sync frames detected interrupt flag */\r
+ vuint16_t MTXIF:1; /* media access test symbol received flag */\r
+ vuint16_t LTXBIF:1; /* pdLatestTx violation on channel B interrupt flag */\r
+ vuint16_t LTXAIF:1; /* pdLatestTx violation on channel A interrupt flag */\r
+ vuint16_t TBVBIF:1; /* Transmission across boundary on channel B Interrupt Flag */\r
+ vuint16_t TBVAIF:1; /* Transmission across boundary on channel A Interrupt Flag */\r
+ vuint16_t TI2IF:1; /* timer 2 expired interrupt flag */\r
+ vuint16_t TI1IF:1; /* timer 1 expired interrupt flag */\r
+ vuint16_t CYSIF:1; /* cycle start interrupt flag */\r
+ } B;\r
+ } PIFR0_t;\r
+ typedef union uPIFR1 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t EMCIF:1; /* error mode changed interrupt flag */\r
+ vuint16_t IPCIF:1; /* illegal protocol command interrupt flag */\r
+ vuint16_t PECFIF:1; /* protocol engine communication failure interrupt flag */\r
+ vuint16_t PSCIF:1; /* Protocol State Changed Interrupt Flag */\r
+ vuint16_t SSI3IF:1; /* slot status counter incremented interrupt flag */\r
+ vuint16_t SSI2IF:1; /* slot status counter incremented interrupt flag */\r
+ vuint16_t SSI1IF:1; /* slot status counter incremented interrupt flag */\r
+ vuint16_t SSI0IF:1; /* slot status counter incremented interrupt flag */\r
+ vuint16_t:2;\r
+ vuint16_t EVTIF:1; /* even cycle table written interrupt flag */\r
+ vuint16_t ODTIF:1; /* odd cycle table written interrupt flag */\r
+ vuint16_t:4;\r
+ } B;\r
+ } PIFR1_t;\r
+ typedef union uPIER0 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t FATLIE:1; /* fatal protocol error interrupt enable */\r
+ vuint16_t INTLIE:1; /* internal protocol error interrupt interrupt enable */\r
+ vuint16_t ILCFIE:1; /* illegal protocol configuration interrupt enable */\r
+ vuint16_t CSAIE:1; /* cold start abort interrupt enable */\r
+ vuint16_t MRCIE:1; /* missing rate correctio interrupt enable */\r
+ vuint16_t MOCIE:1; /* missing offset correctio interrupt enable */\r
+ vuint16_t CCLIE:1; /* clock correction limit reached interrupt enable */\r
+ vuint16_t MXSIE:1; /* max sync frames detected interrupt enable */\r
+ vuint16_t MTXIE:1; /* media access test symbol received interrupt enable */\r
+ vuint16_t LTXBIE:1; /* pdLatestTx violation on channel B interrupt enable */\r
+ vuint16_t LTXAIE:1; /* pdLatestTx violation on channel A interrupt enable */\r
+ vuint16_t TBVBIE:1; /* Transmission across boundary on channel B Interrupt enable */\r
+ vuint16_t TBVAIE:1; /* Transmission across boundary on channel A Interrupt enable */\r
+ vuint16_t TI2IE:1; /* timer 2 expired interrupt enable */\r
+ vuint16_t TI1IE:1; /* timer 1 expired interrupt enable */\r
+ vuint16_t CYSIE:1; /* cycle start interrupt enable */\r
+ } B;\r
+ } PIER0_t;\r
+ typedef union uPIER1 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t EMCIE:1; /* error mode changed interrupt enable */\r
+ vuint16_t IPCIE:1; /* illegal protocol command interrupt enable */\r
+ vuint16_t PECFIE:1; /* protocol engine communication failure interrupt enable */\r
+ vuint16_t PSCIE:1; /* Protocol State Changed Interrupt enable */\r
+ vuint16_t SSI3IE:1; /* slot status counter incremented interrupt enable */\r
+ vuint16_t SSI2IE:1; /* slot status counter incremented interrupt enable */\r
+ vuint16_t SSI1IE:1; /* slot status counter incremented interrupt enable */\r
+ vuint16_t SSI0IE:1; /* slot status counter incremented interrupt enable */\r
+ vuint16_t:2;\r
+ vuint16_t EVTIE:1; /* even cycle table written interrupt enable */\r
+ vuint16_t ODTIE:1; /* odd cycle table written interrupt enable */\r
+ vuint16_t:4;\r
+ } B;\r
+ } PIER1_t;\r
+ typedef union uCHIERFR {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t FRLBEF:1; /* flame lost channel B error flag */\r
+ vuint16_t FRLAEF:1; /* frame lost channel A error flag */\r
+ vuint16_t PCMIEF:1; /* command ignored error flag */\r
+ vuint16_t FOVBEF:1; /* receive FIFO overrun channel B error flag */\r
+ vuint16_t FOVAEF:1; /* receive FIFO overrun channel A error flag */\r
+ vuint16_t MSBEF:1; /* message buffer search error flag */\r
+ vuint16_t MBUEF:1; /* message buffer utilization error flag */\r
+ vuint16_t LCKEF:1; /* lock error flag */\r
+ vuint16_t DBLEF:1; /* double transmit message buffer lock error flag */\r
+ vuint16_t SBCFEF:1; /* system bus communication failure error flag */\r
+ vuint16_t FIDEF:1; /* frame ID error flag */\r
+ vuint16_t DPLEF:1; /* dynamic payload length error flag */\r
+ vuint16_t SPLEF:1; /* static payload length error flag */\r
+ vuint16_t NMLEF:1; /* network management length error flag */\r
+ vuint16_t NMFEF:1; /* network management frame error flag */\r
+ vuint16_t ILSAEF:1; /* illegal access error flag */\r
+ } B;\r
+ } CHIERFR_t;\r
+ typedef union uMBIVEC {\r
+ vuint16_t R;\r
+ struct {\r
+\r
+ vuint16_t:1;\r
+ vuint16_t TBIVEC:7; /* transmit buffer interrupt vector */\r
+ vuint16_t:1;\r
+ vuint16_t RBIVEC:7; /* receive buffer interrupt vector */\r
+ } B;\r
+ } MBIVEC_t;\r
+\r
+ typedef union uPSR0 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t ERRMODE:2; /* error mode */\r
+ vuint16_t SLOTMODE:2; /* slot mode */\r
+ vuint16_t:1;\r
+ vuint16_t PROTSTATE:3; /* protocol state */\r
+ vuint16_t SUBSTATE:4; /* protocol sub state */\r
+ vuint16_t:1;\r
+ vuint16_t WAKEUPSTATUS:3; /* wakeup status */\r
+ } B;\r
+ } PSR0_t;\r
+\r
+/* protocol states */\r
+/* protocol sub-states */\r
+/* wakeup status */\r
+ typedef union uPSR1 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t CSAA:1; /* cold start attempt abort flag */\r
+ vuint16_t SCP:1; /* cold start path */\r
+ vuint16_t:1;\r
+ vuint16_t REMCSAT:5; /* remanining coldstart attempts */\r
+ vuint16_t CPN:1; /* cold start noise path */\r
+ vuint16_t HHR:1; /* host halt request pending */\r
+ vuint16_t FRZ:1; /* freeze occured */\r
+ vuint16_t APTAC:5; /* allow passive to active counter */\r
+ } B;\r
+ } PSR1_t;\r
+ typedef union uPSR2 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t NBVB:1; /* NIT boundary violation on channel B */\r
+ vuint16_t NSEB:1; /* NIT syntax error on channel B */\r
+ vuint16_t STCB:1; /* symbol window transmit conflict on channel B */\r
+ vuint16_t SBVB:1; /* symbol window boundary violation on channel B */\r
+ vuint16_t SSEB:1; /* symbol window syntax error on channel B */\r
+ vuint16_t MTB:1; /* media access test symbol MTS received on channel B */\r
+ vuint16_t NBVA:1; /* NIT boundary violation on channel A */\r
+ vuint16_t NSEA:1; /* NIT syntax error on channel A */\r
+ vuint16_t STCA:1; /* symbol window transmit conflict on channel A */\r
+ vuint16_t SBVA:1; /* symbol window boundary violation on channel A */\r
+ vuint16_t SSEA:1; /* symbol window syntax error on channel A */\r
+ vuint16_t MTA:1; /* media access test symbol MTS received on channel A */\r
+ vuint16_t CLKCORRFAILCNT:4; /* clock correction failed counter */\r
+ } B;\r
+ } PSR2_t;\r
+ typedef union uPSR3 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:2;\r
+ vuint16_t WUB:1; /* wakeup symbol received on channel B */\r
+ vuint16_t ABVB:1; /* aggregated boundary violation on channel B */\r
+ vuint16_t AACB:1; /* aggregated additional communication on channel B */\r
+ vuint16_t ACEB:1; /* aggregated content error on channel B */\r
+ vuint16_t ASEB:1; /* aggregated syntax error on channel B */\r
+ vuint16_t AVFB:1; /* aggregated valid frame on channel B */\r
+ vuint16_t:2;\r
+ vuint16_t WUA:1; /* wakeup symbol received on channel A */\r
+ vuint16_t ABVA:1; /* aggregated boundary violation on channel A */\r
+ vuint16_t AACA:1; /* aggregated additional communication on channel A */\r
+ vuint16_t ACEA:1; /* aggregated content error on channel A */\r
+ vuint16_t ASEA:1; /* aggregated syntax error on channel A */\r
+ vuint16_t AVFA:1; /* aggregated valid frame on channel A */\r
+ } B;\r
+ } PSR3_t;\r
+ typedef union uCIFRR {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:8;\r
+ vuint16_t MIFR:1; /* module interrupt flag */\r
+ vuint16_t PRIFR:1; /* protocol interrupt flag */\r
+ vuint16_t CHIFR:1; /* CHI interrupt flag */\r
+ vuint16_t WUPIFR:1; /* wakeup interrupt flag */\r
+ vuint16_t FNEBIFR:1; /* receive fifo channel B no empty interrupt flag */\r
+ vuint16_t FNEAIFR:1; /* receive fifo channel A no empty interrupt flag */\r
+ vuint16_t RBIFR:1; /* receive message buffer interrupt flag */\r
+ vuint16_t TBIFR:1; /* transmit buffer interrupt flag */\r
+ } B;\r
+ } CIFRR_t;\r
+ typedef union uSFCNTR {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t SFEVB:4; /* sync frames channel B, even cycle */\r
+ vuint16_t SFEVA:4; /* sync frames channel A, even cycle */\r
+ vuint16_t SFODB:4; /* sync frames channel B, odd cycle */\r
+ vuint16_t SFODA:4; /* sync frames channel A, odd cycle */\r
+ } B;\r
+ } SFCNTR_t;\r
+\r
+ typedef union uSFTCCSR {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t ELKT:1; /* even cycle tables lock and unlock trigger */\r
+ vuint16_t OLKT:1; /* odd cycle tables lock and unlock trigger */\r
+ vuint16_t CYCNUM:6; /* cycle number */\r
+ vuint16_t ELKS:1; /* even cycle tables lock status */\r
+ vuint16_t OLKS:1; /* odd cycle tables lock status */\r
+ vuint16_t EVAL:1; /* even cycle tables valid */\r
+ vuint16_t OVAL:1; /* odd cycle tables valid */\r
+ vuint16_t:1;\r
+ vuint16_t OPT:1; /*one pair trigger */\r
+ vuint16_t SDVEN:1; /* sync frame deviation table enable */\r
+ vuint16_t SIDEN:1; /* sync frame ID table enable */\r
+ } B;\r
+ } SFTCCSR_t;\r
+ typedef union uSFIDRFR {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:6;\r
+ vuint16_t SYNFRID:10; /* sync frame rejection ID */\r
+ } B;\r
+ } SFIDRFR_t;\r
+\r
+ typedef union uTICCR {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:2;\r
+ vuint16_t T2CFG:1; /* timer 2 configuration */\r
+ vuint16_t T2REP:1; /* timer 2 repetitive mode */\r
+ vuint16_t:1;\r
+ vuint16_t T2SP:1; /* timer 2 stop */\r
+ vuint16_t T2TR:1; /* timer 2 trigger */\r
+ vuint16_t T2ST:1; /* timer 2 state */\r
+ vuint16_t:3;\r
+ vuint16_t T1REP:1; /* timer 1 repetitive mode */\r
+ vuint16_t:1;\r
+ vuint16_t T1SP:1; /* timer 1 stop */\r
+ vuint16_t T1TR:1; /* timer 1 trigger */\r
+ vuint16_t T1ST:1; /* timer 1 state */\r
+\r
+ } B;\r
+ } TICCR_t;\r
+ typedef union uTI1CYSR {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:2;\r
+ vuint16_t TI1CYCVAL:6; /* timer 1 cycle filter value */\r
+ vuint16_t:2;\r
+ vuint16_t TI1CYCMSK:6; /* timer 1 cycle filter mask */\r
+\r
+ } B;\r
+ } TI1CYSR_t;\r
+\r
+ typedef union uSSSR {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t WMD:1; /* write mode */\r
+ vuint16_t:1;\r
+ vuint16_t SEL:2; /* static slot number */\r
+ vuint16_t:1;\r
+ vuint16_t SLOTNUMBER:11; /* selector */\r
+ } B;\r
+ } SSSR_t;\r
+\r
+ typedef union uSSCCR {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t WMD:1; /* write mode */\r
+ vuint16_t:1;\r
+ vuint16_t SEL:2; /* selector */\r
+ vuint16_t:1;\r
+ vuint16_t CNTCFG:2; /* counter configuration */\r
+ vuint16_t MCY:1; /* multi cycle selection */\r
+ vuint16_t VFR:1; /* valid frame selection */\r
+ vuint16_t SYF:1; /* sync frame selection */\r
+ vuint16_t NUF:1; /* null frame selection */\r
+ vuint16_t SUF:1; /* startup frame selection */\r
+ vuint16_t STATUSMASK:4; /* slot status mask */\r
+ } B;\r
+ } SSCCR_t;\r
+ typedef union uSSR {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t VFB:1; /* valid frame on channel B */\r
+ vuint16_t SYB:1; /* valid sync frame on channel B */\r
+ vuint16_t NFB:1; /* valid null frame on channel B */\r
+ vuint16_t SUB:1; /* valid startup frame on channel B */\r
+ vuint16_t SEB:1; /* syntax error on channel B */\r
+ vuint16_t CEB:1; /* content error on channel B */\r
+ vuint16_t BVB:1; /* boundary violation on channel B */\r
+ vuint16_t TCB:1; /* tx conflict on channel B */\r
+ vuint16_t VFA:1; /* valid frame on channel A */\r
+ vuint16_t SYA:1; /* valid sync frame on channel A */\r
+ vuint16_t NFA:1; /* valid null frame on channel A */\r
+ vuint16_t SUA:1; /* valid startup frame on channel A */\r
+ vuint16_t SEA:1; /* syntax error on channel A */\r
+ vuint16_t CEA:1; /* content error on channel A */\r
+ vuint16_t BVA:1; /* boundary violation on channel A */\r
+ vuint16_t TCA:1; /* tx conflict on channel A */\r
+ } B;\r
+ } SSR_t;\r
+ typedef union uMTSCFR {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t MTE:1; /* media access test symbol transmission enable */\r
+ vuint16_t:1;\r
+ vuint16_t CYCCNTMSK:6; /* cycle counter mask */\r
+ vuint16_t:2;\r
+ vuint16_t CYCCNTVAL:6; /* cycle counter value */\r
+ } B;\r
+ } MTSCFR_t;\r
+ typedef union uRSBIR {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t WMD:1; /* write mode */\r
+ vuint16_t:1;\r
+ vuint16_t SEL:2; /* selector */\r
+ vuint16_t:4;\r
+ vuint16_t RSBIDX:8; /* receive shadow buffer index */\r
+ } B;\r
+ } RSBIR_t;\r
+ typedef union uRFDSR {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t FIFODEPTH:8; /* fifo depth */\r
+ vuint16_t:1;\r
+ vuint16_t ENTRYSIZE:7; /* entry size */\r
+ } B;\r
+ } RFDSR_t;\r
+\r
+ typedef union uRFRFCFR {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t WMD:1; /* write mode */\r
+ vuint16_t IBD:1; /* interval boundary */\r
+ vuint16_t SEL:2; /* filter number */\r
+ vuint16_t:1;\r
+ vuint16_t SID:11; /* slot ID */\r
+ } B;\r
+ } RFRFCFR_t;\r
+\r
+ typedef union uRFRFCTR {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:4;\r
+ vuint16_t F3MD:1; /* filter mode */\r
+ vuint16_t F2MD:1; /* filter mode */\r
+ vuint16_t F1MD:1; /* filter mode */\r
+ vuint16_t F0MD:1; /* filter mode */\r
+ vuint16_t:4;\r
+ vuint16_t F3EN:1; /* filter enable */\r
+ vuint16_t F2EN:1; /* filter enable */\r
+ vuint16_t F1EN:1; /* filter enable */\r
+ vuint16_t F0EN:1; /* filter enable */\r
+ } B;\r
+ } RFRFCTR_t;\r
+ typedef union uPCR0 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t ACTION_POINT_OFFSET:6;\r
+ vuint16_t STATIC_SLOT_LENGTH:10;\r
+ } B;\r
+ } PCR0_t;\r
+\r
+ typedef union uPCR1 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:2;\r
+ vuint16_t MACRO_AFTER_FIRST_STATIC_SLOT:14;\r
+ } B;\r
+ } PCR1_t;\r
+\r
+ typedef union uPCR2 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t MINISLOT_AFTER_ACTION_POINT:6;\r
+ vuint16_t NUMBER_OF_STATIC_SLOTS:10;\r
+ } B;\r
+ } PCR2_t;\r
+\r
+ typedef union uPCR3 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t WAKEUP_SYMBOL_RX_LOW:6;\r
+ vuint16_t MINISLOT_ACTION_POINT_OFFSET:5;\r
+ vuint16_t COLDSTART_ATTEMPTS:5;\r
+ } B;\r
+ } PCR3_t;\r
+\r
+ typedef union uPCR4 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t CAS_RX_LOW_MAX:7;\r
+ vuint16_t WAKEUP_SYMBOL_RX_WINDOW:9;\r
+ } B;\r
+ } PCR4_t;\r
+\r
+ typedef union uPCR5 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t TSS_TRANSMITTER:4;\r
+ vuint16_t WAKEUP_SYMBOL_TX_LOW:6;\r
+ vuint16_t WAKEUP_SYMBOL_RX_IDLE:6;\r
+ } B;\r
+ } PCR5_t;\r
+\r
+ typedef union uPCR6 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:1;\r
+ vuint16_t SYMBOL_WINDOW_AFTER_ACTION_POINT:8;\r
+ vuint16_t MACRO_INITIAL_OFFSET_A:7;\r
+ } B;\r
+ } PCR6_t;\r
+\r
+ typedef union uPCR7 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t DECODING_CORRECTION_B:9;\r
+ vuint16_t MICRO_PER_MACRO_NOM_HALF:7;\r
+ } B;\r
+ } PCR7_t;\r
+\r
+ typedef union uPCR8 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t MAX_WITHOUT_CLOCK_CORRECTION_FATAL:4;\r
+ vuint16_t MAX_WITHOUT_CLOCK_CORRECTION_PASSIVE:4;\r
+ vuint16_t WAKEUP_SYMBOL_TX_IDLE:8;\r
+ } B;\r
+ } PCR8_t;\r
+\r
+ typedef union uPCR9 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t MINISLOT_EXISTS:1;\r
+ vuint16_t SYMBOL_WINDOW_EXISTS:1;\r
+ vuint16_t OFFSET_CORRECTION_OUT:14;\r
+ } B;\r
+ } PCR9_t;\r
+\r
+ typedef union uPCR10 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t SINGLE_SLOT_ENABLED:1;\r
+ vuint16_t WAKEUP_CHANNEL:1;\r
+ vuint16_t MACRO_PER_CYCLE:14;\r
+ } B;\r
+ } PCR10_t;\r
+\r
+ typedef union uPCR11 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t KEY_SLOT_USED_FOR_STARTUP:1;\r
+ vuint16_t KEY_SLOT_USED_FOR_SYNC:1;\r
+ vuint16_t OFFSET_CORRECTION_START:14;\r
+ } B;\r
+ } PCR11_t;\r
+\r
+ typedef union uPCR12 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t ALLOW_PASSIVE_TO_ACTIVE:5;\r
+ vuint16_t KEY_SLOT_HEADER_CRC:11;\r
+ } B;\r
+ } PCR12_t;\r
+\r
+ typedef union uPCR13 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t FIRST_MINISLOT_ACTION_POINT_OFFSET:6;\r
+ vuint16_t STATIC_SLOT_AFTER_ACTION_POINT:10;\r
+ } B;\r
+ } PCR13_t;\r
+\r
+ typedef union uPCR14 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t RATE_CORRECTION_OUT:11;\r
+ vuint16_t LISTEN_TIMEOUT_H:5;\r
+ } B;\r
+ } PCR14_t;\r
+\r
+ typedef union uPCR15 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t LISTEN_TIMEOUT_L:16;\r
+ } B;\r
+ } PCR15_t;\r
+\r
+ typedef union uPCR16 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t MACRO_INITIAL_OFFSET_B:7;\r
+ vuint16_t NOISE_LISTEN_TIMEOUT_H:9;\r
+ } B;\r
+ } PCR16_t;\r
+\r
+ typedef union uPCR17 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t NOISE_LISTEN_TIMEOUT_L:16;\r
+ } B;\r
+ } PCR17_t;\r
+\r
+ typedef union uPCR18 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t WAKEUP_PATTERN:6;\r
+ vuint16_t KEY_SLOT_ID:10;\r
+ } B;\r
+ } PCR18_t;\r
+\r
+ typedef union uPCR19 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t DECODING_CORRECTION_A:9;\r
+ vuint16_t PAYLOAD_LENGTH_STATIC:7;\r
+ } B;\r
+ } PCR19_t;\r
+\r
+ typedef union uPCR20 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t MICRO_INITIAL_OFFSET_B:8;\r
+ vuint16_t MICRO_INITIAL_OFFSET_A:8;\r
+ } B;\r
+ } PCR20_t;\r
+\r
+ typedef union uPCR21 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t EXTERN_RATE_CORRECTION:3;\r
+ vuint16_t LATEST_TX:13;\r
+ } B;\r
+ } PCR21_t;\r
+\r
+ typedef union uPCR22 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:1;\r
+ vuint16_t COMP_ACCEPTED_STARTUP_RANGE_A:11;\r
+ vuint16_t MICRO_PER_CYCLE_H:4;\r
+ } B;\r
+ } PCR22_t;\r
+\r
+ typedef union uPCR23 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t micro_per_cycle_l:16;\r
+ } B;\r
+ } PCR23_t;\r
+\r
+ typedef union uPCR24 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t CLUSTER_DRIFT_DAMPING:5;\r
+ vuint16_t MAX_PAYLOAD_LENGTH_DYNAMIC:7;\r
+ vuint16_t MICRO_PER_CYCLE_MIN_H:4;\r
+ } B;\r
+ } PCR24_t;\r
+\r
+ typedef union uPCR25 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t MICRO_PER_CYCLE_MIN_L:16;\r
+ } B;\r
+ } PCR25_t;\r
+\r
+ typedef union uPCR26 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t ALLOW_HALT_DUE_TO_CLOCK:1;\r
+ vuint16_t COMP_ACCEPTED_STARTUP_RANGE_B:11;\r
+ vuint16_t MICRO_PER_CYCLE_MAX_H:4;\r
+ } B;\r
+ } PCR26_t;\r
+\r
+ typedef union uPCR27 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t MICRO_PER_CYCLE_MAX_L:16;\r
+ } B;\r
+ } PCR27_t;\r
+\r
+ typedef union uPCR28 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t DYNAMIC_SLOT_IDLE_PHASE:2;\r
+ vuint16_t MACRO_AFTER_OFFSET_CORRECTION:14;\r
+ } B;\r
+ } PCR28_t;\r
+\r
+ typedef union uPCR29 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t EXTERN_OFFSET_CORRECTION:3;\r
+ vuint16_t MINISLOTS_MAX:13;\r
+ } B;\r
+ } PCR29_t;\r
+\r
+ typedef union uPCR30 {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:12;\r
+ vuint16_t SYNC_NODE_MAX:4;\r
+ } B;\r
+ } PCR30_t;\r
+\r
+ typedef struct uMSG_BUFF_CCS {\r
+ union {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:1;\r
+ vuint16_t MCM:1; /* message buffer commit mode */\r
+ vuint16_t MBT:1; /* message buffer type */\r
+ vuint16_t MTD:1; /* message buffer direction */\r
+ vuint16_t CMT:1; /* commit for transmission */\r
+ vuint16_t EDT:1; /* enable / disable trigger */\r
+ vuint16_t LCKT:1; /* lock request trigger */\r
+ vuint16_t MBIE:1; /* message buffer interrupt enable */\r
+ vuint16_t:3;\r
+ vuint16_t DUP:1; /* data updated */\r
+ vuint16_t DVAL:1; /* data valid */\r
+ vuint16_t EDS:1; /* lock status */\r
+ vuint16_t LCKS:1; /* enable / disable status */\r
+ vuint16_t MBIF:1; /* message buffer interrupt flag */\r
+ } B;\r
+ } MBCCSR;\r
+ union {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t MTM:1; /* message buffer transmission mode */\r
+ vuint16_t CHNLA:1; /* channel assignement */\r
+ vuint16_t CHNLB:1; /* channel assignement */\r
+ vuint16_t CCFE:1; /* cycle counter filter enable */\r
+ vuint16_t CCFMSK:6; /* cycle counter filter mask */\r
+ vuint16_t CCFVAL:6; /* cycle counter filter value */\r
+ } B;\r
+ } MBCCFR;\r
+ union {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:5;\r
+ vuint16_t FID:11; /* frame ID */\r
+ } B;\r
+ } MBFIDR;\r
+ union {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:8;\r
+ vuint16_t MBIDX:8; /* message buffer index */\r
+ } B;\r
+ } MBIDXR;\r
+ } MSG_BUFF_CCS_t;\r
+ typedef union uSYSBADHR {\r
+ vuint16_t R;\r
+ } SYSBADHR_t;\r
+ typedef union uSYSBADLR {\r
+ vuint16_t R;\r
+ } SYSBADLR_t;\r
+ typedef union uPDAR {\r
+ vuint16_t R;\r
+ } PDAR_t;\r
+ typedef union uCASERCR {\r
+ vuint16_t R;\r
+ } CASERCR_t;\r
+ typedef union uCBSERCR {\r
+ vuint16_t R;\r
+ } CBSERCR_t;\r
+ typedef union uCYCTR {\r
+ vuint16_t R;\r
+ } CYCTR_t;\r
+ typedef union uMTCTR {\r
+ vuint16_t R;\r
+ } MTCTR_t;\r
+ typedef union uSLTCTAR {\r
+ vuint16_t R;\r
+ } SLTCTAR_t;\r
+ typedef union uSLTCTBR {\r
+ vuint16_t R;\r
+ } SLTCTBR_t;\r
+ typedef union uRTCORVR {\r
+ vuint16_t R;\r
+ } RTCORVR_t;\r
+ typedef union uOFCORVR {\r
+ vuint16_t R;\r
+ } OFCORVR_t;\r
+ typedef union uSFTOR {\r
+ vuint16_t R;\r
+ } SFTOR_t;\r
+ typedef union uSFIDAFVR {\r
+ vuint16_t R;\r
+ } SFIDAFVR_t;\r
+ typedef union uSFIDAFMR {\r
+ vuint16_t R;\r
+ } SFIDAFMR_t;\r
+ typedef union uNMVR {\r
+ vuint16_t R;\r
+ } NMVR_t;\r
+ typedef union uNMVLR {\r
+ vuint16_t R;\r
+ } NMVLR_t;\r
+ typedef union uT1MTOR {\r
+ vuint16_t R;\r
+ } T1MTOR_t;\r
+ typedef union uTI2CR0 {\r
+ vuint16_t R;\r
+ } TI2CR0_t;\r
+ typedef union uTI2CR1 {\r
+ vuint16_t R;\r
+ } TI2CR1_t;\r
+ typedef union uSSCR {\r
+ vuint16_t R;\r
+ } SSCR_t;\r
+ typedef union uRFSR {\r
+ vuint16_t R;\r
+ } RFSR_t;\r
+ typedef union uRFSIR {\r
+ vuint16_t R;\r
+ } RFSIR_t;\r
+ typedef union uRFARIR {\r
+ vuint16_t R;\r
+ } RFARIR_t;\r
+ typedef union uRFBRIR {\r
+ vuint16_t R;\r
+ } RFBRIR_t;\r
+ typedef union uRFMIDAFVR {\r
+ vuint16_t R;\r
+ } RFMIDAFVR_t;\r
+ typedef union uRFMIAFMR {\r
+ vuint16_t R;\r
+ } RFMIAFMR_t;\r
+ typedef union uRFFIDRFVR {\r
+ vuint16_t R;\r
+ } RFFIDRFVR_t;\r
+ typedef union uRFFIDRFMR {\r
+ vuint16_t R;\r
+ } RFFIDRFMR_t;\r
+ typedef union uLDTXSLAR {\r
+ vuint16_t R;\r
+ } LDTXSLAR_t;\r
+ typedef union uLDTXSLBR {\r
+ vuint16_t R;\r
+ } LDTXSLBR_t;\r
+\r
+ typedef struct FR_tag {\r
+ volatile MVR_t MVR; /*module version register *//*0 */\r
+ volatile MCR_t MCR; /*module configuration register *//*2 */\r
+ volatile SYSBADHR_t SYSBADHR; /*system memory base address high register *//*4 */\r
+ volatile SYSBADLR_t SYSBADLR; /*system memory base address low register *//*6 */\r
+ volatile STBSCR_t STBSCR; /*strobe signal control register *//*8 */\r
+ volatile STBPCR_t STBPCR; /*strobe port control register *//*A */\r
+ volatile MBDSR_t MBDSR; /*message buffer data size register *//*C */\r
+ volatile MBSSUTR_t MBSSUTR; /*message buffer segment size and utilization register *//*E */\r
+ vuint16_t reserved3a[1]; /*10 */\r
+ volatile PDAR_t PDAR; /*PE data register *//*12 */\r
+ volatile POCR_t POCR; /*Protocol operation control register *//*14 */\r
+ volatile GIFER_t GIFER; /*global interrupt flag and enable register *//*16 */\r
+ volatile PIFR0_t PIFR0; /*protocol interrupt flag register 0 *//*18 */\r
+ volatile PIFR1_t PIFR1; /*protocol interrupt flag register 1 *//*1A */\r
+ volatile PIER0_t PIER0; /*protocol interrupt enable register 0 *//*1C */\r
+ volatile PIER1_t PIER1; /*protocol interrupt enable register 1 *//*1E */\r
+ volatile CHIERFR_t CHIERFR; /*CHI error flag register *//*20 */\r
+ volatile MBIVEC_t MBIVEC; /*message buffer interrupt vector register *//*22 */\r
+ volatile CASERCR_t CASERCR; /*channel A status error counter register *//*24 */\r
+ volatile CBSERCR_t CBSERCR; /*channel B status error counter register *//*26 */\r
+ volatile PSR0_t PSR0; /*protocol status register 0 *//*28 */\r
+ volatile PSR1_t PSR1; /*protocol status register 1 *//*2A */\r
+ volatile PSR2_t PSR2; /*protocol status register 2 *//*2C */\r
+ volatile PSR3_t PSR3; /*protocol status register 3 *//*2E */\r
+ volatile MTCTR_t MTCTR; /*macrotick counter register *//*30 */\r
+ volatile CYCTR_t CYCTR; /*cycle counter register *//*32 */\r
+ volatile SLTCTAR_t SLTCTAR; /*slot counter channel A register *//*34 */\r
+ volatile SLTCTBR_t SLTCTBR; /*slot counter channel B register *//*36 */\r
+ volatile RTCORVR_t RTCORVR; /*rate correction value register *//*38 */\r
+ volatile OFCORVR_t OFCORVR; /*offset correction value register *//*3A */\r
+ volatile CIFRR_t CIFRR; /*combined interrupt flag register *//*3C */\r
+ vuint16_t reserved3[1]; /*3E */\r
+ volatile SFCNTR_t SFCNTR; /*sync frame counter register *//*40 */\r
+ volatile SFTOR_t SFTOR; /*sync frame table offset register *//*42 */\r
+ volatile SFTCCSR_t SFTCCSR; /*sync frame table configuration, control, status register *//*44 */\r
+ volatile SFIDRFR_t SFIDRFR; /*sync frame ID rejection filter register *//*46 */\r
+ volatile SFIDAFVR_t SFIDAFVR; /*sync frame ID acceptance filter value regiater *//*48 */\r
+ volatile SFIDAFMR_t SFIDAFMR; /*sync frame ID acceptance filter mask register *//*4A */\r
+ volatile NMVR_t NMVR[6]; /*network management vector registers (12 bytes) *//*4C */\r
+ volatile NMVLR_t NMVLR; /*network management vector length register *//*58 */\r
+ volatile TICCR_t TICCR; /*timer configuration and control register *//*5A */\r
+ volatile TI1CYSR_t TI1CYSR; /*timer 1 cycle set register *//*5C */\r
+ volatile T1MTOR_t T1MTOR; /*timer 1 macrotick offset register *//*5E */\r
+ volatile TI2CR0_t TI2CR0; /*timer 2 configuration register 0 *//*60 */\r
+ volatile TI2CR1_t TI2CR1; /*timer 2 configuration register 1 *//*62 */\r
+ volatile SSSR_t SSSR; /*slot status selection register *//*64 */\r
+ volatile SSCCR_t SSCCR; /*slot status counter condition register *//*66 */\r
+ volatile SSR_t SSR[8]; /*slot status registers 0-7 *//*68 */\r
+ volatile SSCR_t SSCR[4]; /*slot status counter registers 0-3 *//*78 */\r
+ volatile MTSCFR_t MTSACFR; /*mts a config register *//*80 */\r
+ volatile MTSCFR_t MTSBCFR; /*mts b config register *//*82 */\r
+ volatile RSBIR_t RSBIR; /*receive shadow buffer index register *//*84 */\r
+ volatile RFSR_t RFSR; /*receive fifo selection register *//*86 */\r
+ volatile RFSIR_t RFSIR; /*receive fifo start index register *//*88 */\r
+ volatile RFDSR_t RFDSR; /*receive fifo depth and size register *//*8A */\r
+ volatile RFARIR_t RFARIR; /*receive fifo a read index register *//*8C */\r
+ volatile RFBRIR_t RFBRIR; /*receive fifo b read index register *//*8E */\r
+ volatile RFMIDAFVR_t RFMIDAFVR; /*receive fifo message ID acceptance filter value register *//*90 */\r
+ volatile RFMIAFMR_t RFMIAFMR; /*receive fifo message ID acceptance filter mask register *//*92 */\r
+ volatile RFFIDRFVR_t RFFIDRFVR; /*receive fifo frame ID rejection filter value register *//*94 */\r
+ volatile RFFIDRFMR_t RFFIDRFMR; /*receive fifo frame ID rejection filter mask register *//*96 */\r
+ volatile RFRFCFR_t RFRFCFR; /*receive fifo range filter configuration register *//*98 */\r
+ volatile RFRFCTR_t RFRFCTR; /*receive fifo range filter control register *//*9A */\r
+ volatile LDTXSLAR_t LDTXSLAR; /*last dynamic transmit slot channel A register *//*9C */\r
+ volatile LDTXSLBR_t LDTXSLBR; /*last dynamic transmit slot channel B register *//*9E */\r
+ volatile PCR0_t PCR0; /*protocol configuration register 0 *//*A0 */\r
+ volatile PCR1_t PCR1; /*protocol configuration register 1 *//*A2 */\r
+ volatile PCR2_t PCR2; /*protocol configuration register 2 *//*A4 */\r
+ volatile PCR3_t PCR3; /*protocol configuration register 3 *//*A6 */\r
+ volatile PCR4_t PCR4; /*protocol configuration register 4 *//*A8 */\r
+ volatile PCR5_t PCR5; /*protocol configuration register 5 *//*AA */\r
+ volatile PCR6_t PCR6; /*protocol configuration register 6 *//*AC */\r
+ volatile PCR7_t PCR7; /*protocol configuration register 7 *//*AE */\r
+ volatile PCR8_t PCR8; /*protocol configuration register 8 *//*B0 */\r
+ volatile PCR9_t PCR9; /*protocol configuration register 9 *//*B2 */\r
+ volatile PCR10_t PCR10; /*protocol configuration register 10 *//*B4 */\r
+ volatile PCR11_t PCR11; /*protocol configuration register 11 *//*B6 */\r
+ volatile PCR12_t PCR12; /*protocol configuration register 12 *//*B8 */\r
+ volatile PCR13_t PCR13; /*protocol configuration register 13 *//*BA */\r
+ volatile PCR14_t PCR14; /*protocol configuration register 14 *//*BC */\r
+ volatile PCR15_t PCR15; /*protocol configuration register 15 *//*BE */\r
+ volatile PCR16_t PCR16; /*protocol configuration register 16 *//*C0 */\r
+ volatile PCR17_t PCR17; /*protocol configuration register 17 *//*C2 */\r
+ volatile PCR18_t PCR18; /*protocol configuration register 18 *//*C4 */\r
+ volatile PCR19_t PCR19; /*protocol configuration register 19 *//*C6 */\r
+ volatile PCR20_t PCR20; /*protocol configuration register 20 *//*C8 */\r
+ volatile PCR21_t PCR21; /*protocol configuration register 21 *//*CA */\r
+ volatile PCR22_t PCR22; /*protocol configuration register 22 *//*CC */\r
+ volatile PCR23_t PCR23; /*protocol configuration register 23 *//*CE */\r
+ volatile PCR24_t PCR24; /*protocol configuration register 24 *//*D0 */\r
+ volatile PCR25_t PCR25; /*protocol configuration register 25 *//*D2 */\r
+ volatile PCR26_t PCR26; /*protocol configuration register 26 *//*D4 */\r
+ volatile PCR27_t PCR27; /*protocol configuration register 27 *//*D6 */\r
+ volatile PCR28_t PCR28; /*protocol configuration register 28 *//*D8 */\r
+ volatile PCR29_t PCR29; /*protocol configuration register 29 *//*DA */\r
+ volatile PCR30_t PCR30; /*protocol configuration register 30 *//*DC */\r
+ vuint16_t reserved2[17];\r
+ volatile MSG_BUFF_CCS_t MBCCS[128]; /* message buffer configuration, control & status registers 0-31 *//*100 */\r
+ } FR_tag_t;\r
+\r
+ typedef union uF_HEADER /* frame header */\r
+ {\r
+ struct {\r
+ vuint16_t:5;\r
+ vuint16_t HDCRC:11; /* Header CRC */\r
+ vuint16_t:2;\r
+ vuint16_t CYCCNT:6; /* Cycle Count */\r
+ vuint16_t:1;\r
+ vuint16_t PLDLEN:7; /* Payload Length */\r
+ vuint16_t:1;\r
+ vuint16_t PPI:1; /* Payload Preamble Indicator */\r
+ vuint16_t NUF:1; /* Null Frame Indicator */\r
+ vuint16_t SYF:1; /* Sync Frame Indicator */\r
+ vuint16_t SUF:1; /* Startup Frame Indicator */\r
+ vuint16_t FID:11; /* Frame ID */\r
+ } B;\r
+ vuint16_t WORDS[3];\r
+ } F_HEADER_t;\r
+ typedef union uS_STSTUS /* slot status */\r
+ {\r
+ struct {\r
+ vuint16_t VFB:1; /* Valid Frame on channel B */\r
+ vuint16_t SYB:1; /* Sync Frame Indicator channel B */\r
+ vuint16_t NFB:1; /* Null Frame Indicator channel B */\r
+ vuint16_t SUB:1; /* Startup Frame Indicator channel B */\r
+ vuint16_t SEB:1; /* Syntax Error on channel B */\r
+ vuint16_t CEB:1; /* Content Error on channel B */\r
+ vuint16_t BVB:1; /* Boundary Violation on channel B */\r
+ vuint16_t CH:1; /* Channel */\r
+ vuint16_t VFA:1; /* Valid Frame on channel A */\r
+ vuint16_t SYA:1; /* Sync Frame Indicator channel A */\r
+ vuint16_t NFA:1; /* Null Frame Indicator channel A */\r
+ vuint16_t SUA:1; /* Startup Frame Indicator channel A */\r
+ vuint16_t SEA:1; /* Syntax Error on channel A */\r
+ vuint16_t CEA:1; /* Content Error on channel A */\r
+ vuint16_t BVA:1; /* Boundary Violation on channel A */\r
+ vuint16_t:1;\r
+ } RX;\r
+ struct {\r
+ vuint16_t VFB:1; /* Valid Frame on channel B */\r
+ vuint16_t SYB:1; /* Sync Frame Indicator channel B */\r
+ vuint16_t NFB:1; /* Null Frame Indicator channel B */\r
+ vuint16_t SUB:1; /* Startup Frame Indicator channel B */\r
+ vuint16_t SEB:1; /* Syntax Error on channel B */\r
+ vuint16_t CEB:1; /* Content Error on channel B */\r
+ vuint16_t BVB:1; /* Boundary Violation on channel B */\r
+ vuint16_t TCB:1; /* Tx Conflict on channel B */\r
+ vuint16_t VFA:1; /* Valid Frame on channel A */\r
+ vuint16_t SYA:1; /* Sync Frame Indicator channel A */\r
+ vuint16_t NFA:1; /* Null Frame Indicator channel A */\r
+ vuint16_t SUA:1; /* Startup Frame Indicator channel A */\r
+ vuint16_t SEA:1; /* Syntax Error on channel A */\r
+ vuint16_t CEA:1; /* Content Error on channel A */\r
+ vuint16_t BVA:1; /* Boundary Violation on channel A */\r
+ vuint16_t TCA:1; /* Tx Conflict on channel A */\r
+ } TX;\r
+ vuint16_t R;\r
+ } S_STATUS_t;\r
+\r
+ typedef struct uMB_HEADER /* message buffer header */\r
+ {\r
+ F_HEADER_t FRAME_HEADER;\r
+ vuint16_t DATA_OFFSET;\r
+ S_STATUS_t SLOT_STATUS;\r
+ } MB_HEADER_t;\r
+\r
+/* Define memories */\r
+\r
+#define SRAM_START 0x40000000\r
+#define SRAM_SIZE 0x14000\r
+#define SRAM_END 0x40013FFF\r
+\r
+#define FLASH_START 0x0\r
+#define FLASH_SIZE 0x200000\r
+#define FLASH_END 0x1FFFFF\r
+\r
+/* Define instances of modules */\r
+#define PBRIDGE_A (*( volatile struct PBRIDGE_A_tag *) 0xC3F00000)\r
+#define FMPLL (*( volatile struct FMPLL_tag *) 0xC3F80000)\r
+#define EBI (*( volatile struct EBI_tag *) 0xC3F84000)\r
+#define FLASH (*( volatile struct FLASH_tag *) 0xC3F88000)\r
+#define SIU (*( volatile struct SIU_tag *) 0xC3F90000)\r
+\r
+#define EMIOS (*( volatile struct EMIOS_tag *) 0xC3FA0000)\r
+#define ETPU (*( volatile struct ETPU_tag *) 0xC3FC0000)\r
+#define ETPU_DATA_RAM (*( uint32_t *) 0xC3FC8000)\r
+#define ETPU_DATA_RAM_EXT (*( uint32_t *) 0xC3FCC000)\r
+#define ETPU_DATA_RAM_END 0xC3FC89FC\r
+#define CODE_RAM (*( uint32_t *) 0xC3FD0000)\r
+#define ETPU_CODE_RAM (*( uint32_t *) 0xC3FD0000)\r
+\r
+#define PBRIDGE_B (*( volatile struct PBRIDGE_B_tag *) 0xFFF00000)\r
+#define XBAR (*( volatile struct XBAR_tag *) 0xFFF04000)\r
+#define ECSM (*( volatile struct ECSM_tag *) 0xFFF40000)\r
+#define EDMA (*( volatile struct EDMA_tag *) 0xFFF44000)\r
+#define INTC (*( volatile struct INTC_tag *) 0xFFF48000)\r
+\r
+#define EQADC (*( volatile struct EQADC_tag *) 0xFFF80000)\r
+\r
+#define DSPI_B (*( volatile struct DSPI_tag *) 0xFFF94000)\r
+#define DSPI_C (*( volatile struct DSPI_tag *) 0xFFF98000)\r
+#define DSPI_D (*( volatile struct DSPI_tag *) 0xFFF9C000)\r
+\r
+#define ESCI_A (*( volatile struct ESCI_tag *) 0xFFFB0000)\r
+#define ESCI_B (*( volatile struct ESCI_tag *) 0xFFFB4000)\r
+\r
+#define CAN_A (*( volatile struct FLEXCAN2_tag *) 0xFFFC0000)\r
+#define CAN_B (*( volatile struct FLEXCAN2_tag *) 0xFFFC4000)\r
+#define CAN_C (*( volatile struct FLEXCAN2_tag *) 0xFFFC8000)\r
+#define CAN_D (*( volatile struct FLEXCAN2_tag *) 0xFFFCC000)\r
+#define CAN_E (*( volatile struct FLEXCAN2_tag *) 0xFFFD0000)\r
+\r
+#define FEC (*( volatile struct FEC_tag *) 0xFFF4C000)\r
+\r
+#define FR (*( volatile struct FR_tag *) 0xFFFE0000)\r
+\r
+#ifdef __MWERKS__\r
+#pragma pop\r
+#endif\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+#endif /* ifdef _MPC5567_H */\r
+/*********************************************************************\r
+ *\r
+ * Copyright:\r
+ * Freescale Semiconductor, INC. All Rights Reserved.\r
+ * You are hereby granted a copyright license to use, modify, and\r
+ * distribute the SOFTWARE so long as this entire notice is\r
+ * retained without alteration in any modified and/or redistributed\r
+ * versions, and that such modified versions are clearly identified\r
+ * as such. No licenses are granted by implication, estoppel or\r
+ * otherwise under any patents or trademarks of Freescale\r
+ * Semiconductor, Inc. This software is provided on an "AS IS"\r
+ * basis and without warranty.\r
+ *\r
+ * To the maximum extent permitted by applicable law, Freescale\r
+ * Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,\r
+ * INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A\r
+ * PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH\r
+ * REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF)\r
+ * AND ANY ACCOMPANYING WRITTEN MATERIALS.\r
+ *\r
+ * To the maximum extent permitted by applicable law, IN NO EVENT\r
+ * SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER\r
+ * (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,\r
+ * BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER\r
+ * PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.\r
+ *\r
+ * Freescale Semiconductor assumes no responsibility for the\r
+ * maintenance and support of this software\r
+ *\r
+ ********************************************************************/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/**************************************************************************\r
+ * FILE NAME: $RCSfile: typedefs.h,v $ COPYRIGHT (c) Freescale 2005 *\r
+ * DESCRIPTION: All Rights Reserved *\r
+ * This file defines all of the data types for the Motorola header file. *\r
+ *========================================================================*\r
+ * ORIGINAL AUTHOR: Jeff Loeliger (r12110) *\r
+ * $Log: typedefs.h,v $\r
+ * Revision 1.0 2007-06-14 15:54:36+02 b08931\r
+ * Initial revision\r
+ *\r
+ * Revision 1.0 2007-06-14 11:33:56+02 b08931\r
+ * Initial revision\r
+ *\r
+ * Revision 1.0 2007-06-13 15:12:03+02 b08931\r
+ * Initial revision\r
+ *\r
+ * Revision 1.0 2007-06-13 12:55:08+02 b08931\r
+ * Initial revision\r
+ *\r
+ * Revision 1.0 2007-06-13 10:08:35+02 b08931\r
+ * Initial revision\r
+ *\r
+ * Revision 1.0 2007-06-13 09:37:55+02 b08931\r
+ * Initial revision\r
+ *\r
+ * Revision 1.0 2007-06-12 14:50:33+02 b08931\r
+ * Initial revision\r
+ *\r
+ * Revision 1.0 2007-06-06 13:16:20+02 b08931\r
+ * Initial revision\r
+ *\r
+ * Revision 1.0 2007-04-19 13:13:10+02 b08931\r
+ * Initial revision\r
+ *\r
+ * Revision 1.4 2006/03/27 09:59:34 r47354\r
+ * change __GHS__ to __ghs__. As per bug 13213\r
+ *\r
+ * Revision 1.3 2005/02/22 13:09:38 r47354\r
+ * Fix copyright date.\r
+ *\r
+ * Revision 1.2 2004/11/17 12:43:12 r12110\r
+ * -Removed #ifdef DEBUG from around initial comment block.\r
+ *\r
+ * Revision 1.1 2004/11/17 12:38:48 r12110\r
+ * -Initial version checked into CVS.\r
+ * -Updated copyright from Motorola to Freescale.\r
+ *\r
+ *........................................................................*\r
+ * 0.1 J. Loeliger 17/Feb/03 Initial version of file. *\r
+ * 0.2 J. Loeliger 06/Mar/03 Added DCC support. *\r
+ * 0.3 J. Loeliger 07/May/03 Change to fully use ISO data types. *\r
+ * 0.4 J. Loeliger 17/Jun/03 Change name to motint.h and merge *\r
+ * MPC5500 and MAC7100 files. *\r
+ * 0.5 J. Loeliger 04/Nov/03 Changed name to typedefs.h. *\r
+ * 0.6 J. Loeliger 09/May/04 Changed to support GHS and GCC. *\r
+ **************************************************************************/\r
+\r
+#ifndef _TYPEDEFS_H_\r
+#define _TYPEDEFS_H_\r
+\r
+#if defined(__MWERKS__) //Metrowerk CodeWarrior\r
+ #include <stdint.h>\r
+\r
+ // Standard typedefs used by header files, based on ISO C standard\r
+ typedef volatile int8_t vint8_t;\r
+ typedef volatile uint8_t vuint8_t;\r
+\r
+ typedef volatile int16_t vint16_t;\r
+ typedef volatile uint16_t vuint16_t;\r
+\r
+ typedef volatile int32_t vint32_t;\r
+ typedef volatile uint32_t vuint32_t;\r
+\r
+#else\r
+#ifdef __ghs__ //GreenHills\r
+ #include <stdint.h>\r
+\r
+ // Standard typedefs used by header files, based on ISO C standard\r
+ typedef volatile int8_t vint8_t;\r
+ typedef volatile uint8_t vuint8_t;\r
+\r
+ typedef volatile int16_t vint16_t;\r
+ typedef volatile uint16_t vuint16_t;\r
+\r
+ typedef volatile int32_t vint32_t;\r
+ typedef volatile uint32_t vuint32_t;\r
+\r
+#else\r
+\r
+ // This is needed for compilers that don't have a stdint.h file\r
+#if 1\r
+ #include <stdint.h> \r
+#else\r
+ typedef signed char int8_t;\r
+ typedef unsigned char uint8_t;\r
+ typedef signed short int16_t;\r
+ typedef unsigned short uint16_t;\r
+ typedef signed int int32_t;\r
+ typedef unsigned int uint32_t;\r
+\r
+#endif\r
+ typedef volatile signed char vint8_t;\r
+ typedef volatile unsigned char vuint8_t;\r
+\r
+ typedef volatile signed short vint16_t;\r
+ typedef volatile unsigned short vuint16_t;\r
+\r
+ typedef volatile signed int vint32_t;\r
+ typedef volatile unsigned int vuint32_t; \r
+#endif\r
+#endif\r
+#endif\r
+\r
+/*********************************************************************\r
+ *\r
+ * Copyright:\r
+ * Freescale Semiconductor, INC. All Rights Reserved.\r
+ * You are hereby granted a copyright license to use, modify, and\r
+ * distribute the SOFTWARE so long as this entire notice is\r
+ * retained without alteration in any modified and/or redistributed\r
+ * versions, and that such modified versions are clearly identified\r
+ * as such. No licenses are granted by implication, estoppel or\r
+ * otherwise under any patents or trademarks of Freescale\r
+ * Semiconductor, Inc. This software is provided on an "AS IS"\r
+ * basis and without warranty.\r
+ *\r
+ * To the maximum extent permitted by applicable law, Freescale\r
+ * Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,\r
+ * INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A\r
+ * PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH\r
+ * REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF)\r
+ * AND ANY ACCOMPANYING WRITTEN MATERIALS.\r
+ *\r
+ * To the maximum extent permitted by applicable law, IN NO EVENT\r
+ * SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER\r
+ * (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,\r
+ * BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER\r
+ * PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.\r
+ *\r
+ * Freescale Semiconductor assumes no responsibility for the\r
+ * maintenance and support of this software\r
+ *\r
+ ********************************************************************/\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+#include "types.h"\r
+#include "Cpu.h"\r
+#include "asm_ppc.h"\r
+#include "asm_book_e.h"\r
+#include "sys.h"\r
+#include "arch.h"\r
+#include "task_i.h"\r
+#include "internal.h"\r
+#include "mpc55xx.h"\r
+#include <assert.h>\r
+\r
+#define USE_DEBUG\r
+#include "Trace.h"\r
+\r
+/**\r
+ * Function make sure that we switch to supervisor mode(rfi) before\r
+ * we call a task for the first time.\r
+ */\r
+void os_arch_first_call( void )\r
+{\r
+#if USE_MM_USER_MODE\r
+\r
+ // Assume that regs[0] is setup before and contains the settings\r
+ // to switch to user mode.\r
+ register uint32_t msr asm("r3") = os_sys.curr_pcb->regs[0];\r
+ register void *ea asm("r4") = (void *) os_sys.curr_pcb->entry;\r
+\r
+ // Do the switch\r
+ asm volatile(\r
+ "mtspr 26,%0;\r\t" // srr0\r
+ "mtspr 27,%1;\r\t" // srr1\r
+ "rfi;\r\t"\r
+ :\r
+ : "r" (ea), "r" (msr) );\r
+#else\r
+// TODO: This really depends on if scheduling policy\r
+ Irq_Enable();\r
+ os_sys.curr_pcb->entry();\r
+#endif\r
+}\r
+\r
+\r
+/* TODO: This actually gives the stack ptr here...not the callers stack ptr\r
+ * Should probably be a macro instead..... in some arch part..\r
+ */\r
+void *os_arch_get_stackptr( void ) {\r
+ void *stackp;\r
+ // Get stack ptr(r1) from current context\r
+ asm volatile(" mr %0,1":"=r" (stackp));\r
+\r
+ return stackp;\r
+}\r
+\r
+unsigned int os_arch_get_sc_size( void ) {\r
+ return SC_SIZE;\r
+}\r
+\r
+extern void os_arch_setup_context_asm( void *context,unsigned int msr);\r
+\r
+#define STACK_PATTERN 0x42\r
+
+#if 0
+\r
+_Bool os_arch_stack_endmark_ok( pcb_t *pcb ) {\r
+ uint8_t *end = pcb->stack.top;\r
+ return ( *end == STACK_PATTERN);\r
+}\r
+\r
+\r
+void *os_arch_get_stack_usage( pcb_t *pcb ) {\r
+\r
+ uint8_t *p = pcb->stack.curr;\r
+ uint8_t *end = pcb->stack.top;\r
+\r
+ while( (*end == STACK_PATTERN) && (end<p)) {\r
+ end++;\r
+ }\r
+ return (void *)end;\r
+}\r
+#endif\r
+
+\r
+// TODO: I have no clue why I wrote this????\r
+void os_arch_stack_to_small(pcb_t *pcb ,uint32_t size_min) {\r
+ pcb_t *t;\r
+ uint32_t min;\r
+\r
+ while(1) {\r
+ t = pcb;\r
+ min = size_min;\r
+ }\r
+}\r
+\r
+/*\r
+ * Stack grows from high -> low addresses\r
+ *\r
+\r
+ *\r
+ *\r
+\r
+\r
+ * ---------------- bottom of the stack( high address )\r
+ * small context\r
+ * ----------------\r
+ *\r
+ * ---------------- top of the stack( low address )\r
+ *\r
+ */\r
+\r
+void os_arch_setup_context( pcb_t *pcb ) {\r
+ uint32_t msr;\r
+ // Note! stack.curr already points to where to save the context\r
+\r
+ // Check that the stack size is enough\r
+ #define STACK_SIZE_MIN (SC_SIZE + 16*2 )\r
+ if( pcb->stack.size < (STACK_SIZE_MIN) ) {\r
+ os_arch_stack_to_small(pcb, STACK_SIZE_MIN);\r
+ }\r
+\r
+ // Fill stack with a nice pattern STACK_PATTERN\r
+ {\r
+ uint8_t *p = pcb->stack.curr;\r
+\r
+ assert(pcb->stack.curr>pcb->stack.top);\r
+\r
+ while(p > (uint8_t *)pcb->stack.top) {\r
+ --p;\r
+ *p = STACK_PATTERN;\r
+ }\r
+ }\r
+\r
+ msr = MSR_EE;\r
+\r
+#if defined(CFG_SPE)\r
+ msr |= MSR_SPE;\r
+#endif\r
+\r
+ if( !pcb->application->trusted ) {\r
+ // Non-trusted = User mode..\r
+ msr |= MSR_PR | MSR_DS | MSR_IS;\r
+ }\r
+ pcb->regs[0] = msr;\r
+\r
+ {\r
+ uint32_t *context = (uint32_t *)pcb->stack.curr;\r
+\r
+ context[C_CONTEXT_OFF/4] = SC_PATTERN;\r
+\r
+ /* Set LR to start function */\r
+ if( pcb->proc_type == PROC_EXTENDED ) {\r
+ context[C_LR_OFF/4] = (uint32_t)os_proc_start_extended;\r
+ } else if( pcb->proc_type == PROC_BASIC ) {\r
+ context[C_LR_OFF/4] = (uint32_t)os_proc_start_basic;\r
+ }\r
+ }\r
+}\r
+\r
+\r
+#define C_CONTEXT_OFF 12\r
+#define C_LR_OFF 16\r
+#define C_CR_OFF 20\r
+\r
+void os_arch_print_context( char *str, pcb_t *pcb ) {\r
+ uint32_t *stack;\r
+\r
+ dbg_printf("%s CONTEXT: %d\n",str, pcb->pid);\r
+ dbg_printf(" stack: curr=%08x top=%08x bottom=%08x\n",pcb->stack.curr, pcb->stack.top, pcb->stack.top+ pcb->stack.size);\r
+ stack = pcb->stack.curr;\r
+ dbg_printf(" val : context=%08x LR=%08x CR=%08x\n",\r
+ stack[C_CONTEXT_OFF/4],\r
+ stack[C_LR_OFF/4],\r
+ stack[C_CR_OFF/4]\r
+ );\r
+}\r
+\r
+\r
+void os_arch_init( void ) {\r
+#if defined(CFG_SPE)\r
+ uint32_t msr = get_msr();\r
+ msr |= MSR_SPE;\r
+ set_msr(msr);\r
+#endif\r
+}\r
+\r
+#define EXC_VECTOR_CRITICAL_INPUT_OFF 0\r
+#define EXC_VECTOR_MACHINE_CHECK_OFF 1\r
+#define EXC_VECTOR_PROGRAM_OFF 6\r
+#define EXC_VECTOR_DECREMENTER_OFF 10\r
+#define EXC_VECTOR_DATA_TLB_OFF 13\r
+#define EXC_VECTOR_INSTRUCTION_TLB_OFF 14\r
+\r
+\r
+typedef void (*exc_func_t)(uint32_t *);\r
+\r
+/* How do I construct the PTE table ??\r
+ *\r
+ * 1. Calculate the section sizes for each application\r
+ * ( objdump on the object file)\r
+ * 2. Generate a Table for each application\r
+ *\r
+ * OS207\r
+ * Trusted OS-applications CAN write to\r
+ *\r
+ * What do I do with the global data ???\r
+ *\r
+ *\r
+ */\r
+\r
+\r
+/* Move these somewhere else if we need the speed */\r
+void os_arch_data_tlb( uint32_t *regs ) {\r
+ uint32_t dear = regs[EXC_DEAR_OFF];\r
+ (void)dear;\r
+}\r
+\r
+void os_arch_instruction_tlb( uint32_t *regs ) {\r
+ uint32_t srr0 = regs[EXC_SRR0_OFF];\r
+ (void)srr0;\r
+ /* What information can I get here??\r
+ * - The pcb to MMU mapping ???\r
+ */\r
+\r
+ /* TODO: How do I construct the PTE(Page Table Entry) ??*/\r
+\r
+}\r
+\r
+void os_arch_exc_program( uint32_t *regs ) {\r
+ uint32_t esr = regs[EXC_ESR_OFF];\r
+\r
+ if( esr & ESR_PTR ) {\r
+ // Trap\r
+ if( !(regs[EXC_SRR1_OFF] & MSR_PR) ) {\r
+ // User -> Supervisor\r
+ regs[EXC_SRR1_OFF] |= MSR_PR;\r
+ }\r
+ }\r
+}\r
+\r
+\r
--- /dev/null
+\r
+/*\r
+ * IVOR4\r
+ * 1. Save stack frames: EXC, VGPR, NVGPR and C\r
+ * 2. Call IntCtrl_Entry(void *curr_stack)\r
+ * 2.1 Check for exception\r
+ * 2.2 If softint, clear it.\r
+ * 2.3 If PROC_ISR1, then just call the function\r
+ * 2.4 If PROC_ISR2 -> it's a PCB, let the OS handle it.\r
+ */\r
+\r
+#define _ASSEMBLER_\r
+#include "asm_ppc.h"\r
+#include "asm_offset.h"\r
+#include "asm_book_e.h"\r
+.extern os_intc_pcb_tbl\r
+.extern os_intc_types_tbl\r
+.extern os_sys\r
+\r
+\r
+/*\r
+ * Small assembler school\r
+ * Compare imm(32-bit)\r
+ * > cmpwi rA,100\r
+ * Extract bits and right adjust\r
+ * > extrwi rA,rS,n,b ( n-number of bits, b- startbit )\r
+ *\r
+ * Note!\r
+ * The offset's (d or D)for SPE instructins are rediculously low.\r
+ * Normally you have 16-bits offset, but when using spe load and store\r
+ * you can use only 8-bit.\r
+*/\r
+\r
+#define LOCK() wrteei 0\r
+#define UNLOCK() wrteei 1\r
+\r
+\r
+.extern os_proc_start_extended\r
+\r
+//-------------------------------------------------------------------\r
+\r
+ .global os_exception_IVOR8\r
+ .balign 16\r
+os_exception_IVOR8:\r
+ stwu sp,-(EXC_SIZE+VGPR_SIZE)(sp)\r
+ stw r3,EXC_R3_OFF(r1)\r
+ stw r4,EXC_R4_OFF(r1)\r
+ SAVE_EXC_FRAME(3,1,0,SPR_SRR0,SPR_SRR1)\r
+ SAVE_VGPR(1,EXC_SIZE);\r
+ li r3,328\r
+ stw r3,EXC_VECTOR_OFF(r1)\r
+\r
+ rfi\r
+\r
+dummy_int:\r
+ b dummy_int\r
+\r
+/*--------------------------------------------------------------------\r
+ * void os_swap_context(pcb_t *old, pcb_t *new )\r
+ *\r
+ * Saves a small context on current stack, pops a new one from new context\r
+ *\r
+ * r3 - pcb for old process\r
+ * r4 - pcb for new process\r
+ *\r
+ *--------------------------------------------------------------------*/\r
+\r
+// TODO: this assumes that both are in user mode?.. can this happen under trusted functions?\r
+// When I get here we're ALWAYS in kernel mode\r
+\r
+.global os_arch_swap_context_to\r
+.global os_arch_swap_context\r
+.section .text\r
+os_arch_swap_context:\r
+ // allocate space for context+nvgpr\r
+ // (no need for proper stack-frame here)\r
+ stwu r1,-(C_SIZE+NVGPR_SIZE)(r1)\r
+ // save lr and cr */\r
+ mflr r0\r
+ stw r0,C_LR_OFF(sp)\r
+ mfcr r0\r
+ stw r0,C_CR_OFF(sp)\r
+ // Save small-context pattern\r
+ li r0,SC_PATTERN\r
+ stw r0,C_CONTEXT_OFF(sp)\r
+ // Save registers preserved by function call\r
+ SAVE_NVGPR(sp,(C_SIZE-14*GPR_SIZE))\r
+// Save stack ptr...\r
+ stw sp,PCB_STACK_CURR_P(r3)\r
+\r
+// Stack frame here\r
+// --------- bottom( high address )\r
+// SC_xxx\r
+// C_xxx\r
+// --------- <- stack.curr\r
+//\r
+// --------- top( low address )\r
+\r
+\r
+// TODO: If we change application we must change mmu setup\r
+os_arch_swap_context_to:\r
+// Get stack for new task\r
+ lwz sp,PCB_STACK_CURR_P(r4)\r
+\r
+// Set new current process\r
+ LOAD_ADDR_32(3,os_sys)\r
+ stw r4,SYS_CURR_PCB_P(r3)\r
+\r
+// Restore C context\r
+ lwz r0,C_CR_OFF(sp)\r
+ mtcr r0\r
+ lwz r0,C_LR_OFF (sp)\r
+ mtlr r0\r
+\r
+// Get the context type\r
+ lwz r0,C_CONTEXT_OFF(sp)\r
+ cmpli 0,r0,SC_PATTERN\r
+ beq+ os_sc_restore\r
+ cmpli 0,r0,LC_PATTERN\r
+ beq+ os_lc_restore\r
+ b os_bad_bad\r
+\r
+\r
+// SC_xxx\r
+// C_xxxx <- We point here\r
+\r
+os_sc_restore:\r
+ RESTORE_NVGPR(sp,(C_SIZE-14*GPR_SIZE))\r
+ addi sp,sp,(C_SIZE+NVGPR_SIZE)\r
+ // TODO: The blr will not do the trick if swapping to a user land task.\r
+ blr\r
+\r
+os_lc_restore:\r
+ addi r1,r1,C_SIZE\r
+ RESTORE_NVGPR(1,0)\r
+ addi r1,r1,-C_SIZE\r
+ RESTORE_VGPR(1,C_SIZE)\r
+\r
+ RESTORE_WORK_AND_MORE\r
+ rfi\r
+\r
+// When something really bad happens we end up here for the moment\r
+os_bad_bad:\r
+ b os_bad_bad\r
+\r
+\r
+\r
+\r
+// ------------------------------------------------------------------\r
+\r
+/*\r
+ * Trap interface !!!! See article http://www.linuxjournal.com/article/6516\r
+ * http://www.osweekly.com/index.php?option=com_content&task=view&id=2229\r
+ */\r
+\r
+/* The T32 instruction sim can't handle trap's so we have to make something\r
+ * - write SRR0, SRR1, MSR\r
+ * - jump to there routines\r
+ */\r
+\r
+// ------------------------------------------------------------------\r
+\r
+\r
+// System call, use this for trusted function ???\r
+// TODO: The example in autosar is not neccesary.. sc here here instead??\r
+//\r
+// NOTE!!!!!\r
+// Since the sc is a sync call, it should be enough to save NV regs(14->)\r
+// If I don't use the NV regs here I shouldn't need to save them\r
+// TODO: Inform compiler in SC_CALL() that I clobber volatile regs( r0, r3->\r
+// (since the compiler does not know it's a function call)\r
+// TODO: Could probably do this shorter....only NV regs that I use need saving\r
+// ( only cr2->cr4 according to e500 ABI )\r
+\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*
+ * int_ctrl.c
+ *
+ * Created on: Jul 13, 2009
+ * Author: mahi
+ */
+
+#include "typedefs.h"
+#include "asm_book_e.h"
+#include "irq.h"
+#include "mpc55xx.h"
+#if !defined(USE_KERNEL)
+#include "Mcu.h"
+#endif
+#include <assert.h>
+#include "Ramlog.h"
+//#include <stdio.h>
+
+#if defined(USE_KERNEL)
+#include "pcb.h"
+#include "sys.h"
+#include "internal.h"
+#include "task_i.h"
+#include "hooks.h"
+#include "swap.h"
+
+#if 0
+#define INTC_SSCIR0_CLR7 7
+#define MLB_SERVICE_REQUEST 293
+#define CRITICAL_INPUT_EXCEPTION 320
+#define DEBUG_EXCEPTION 335
+#define NUMBER_OF_INTERRUPTS_AND_EXCEPTIONS 336
+#endif
+
+#include "Trace.h"
+#endif
+
+static void dump_exception_regs( uint32_t *regs );
+
+typedef void (*f_t)( uint32_t *);
+typedef void (*func_t)();
+//extern vfunc_t intc_vector_tbl[];
+extern void exception_tbl(void);
+
+
+
+#if defined(USE_KERNEL)
+extern void * intc_vector_tbl[NUMBER_OF_INTERRUPTS_AND_EXCEPTIONS];
+extern uint8 intc_type_tbl[NUMBER_OF_INTERRUPTS_AND_EXCEPTIONS];
+#else
+extern func_t intc_vector_tbl[];
+#endif
+
+// write 0 to pop INTC stack
+void IntCtrl_Init( void ) {
+ // Check alignment for the exception table
+ assert(((uint32)exception_tbl & 0xfff)==0);
+ set_spr(SPR_IVPR,(uint32)exception_tbl);
+
+ ramlog_str("Test\n");
+ ramlog_hex(0x10);
+ ramlog_dec(20);
+
+ // TODO: The 5516 simulator still thinks it's a 5554 so setup the rest
+#if (defined(CFG_SIMULATOR) && defined(CFG_MPC5516)) || defined(CFG_MPC5567) || defined(CFG_MPC5554)
+ set_spr(SPR_IVOR0,((uint32_t)&exception_tbl+0x0) );
+ set_spr(SPR_IVOR1,((uint32_t)&exception_tbl+0x10) );
+ set_spr(SPR_IVOR2,((uint32_t)&exception_tbl+0x20) );
+ set_spr(SPR_IVOR3,((uint32_t)&exception_tbl+0x30) );
+ set_spr(SPR_IVOR4,((uint32_t)&exception_tbl+0x40) );
+ set_spr(SPR_IVOR5,((uint32_t)&exception_tbl+0x50) );
+ set_spr(SPR_IVOR6,((uint32_t)&exception_tbl+0x60) );
+ set_spr(SPR_IVOR7,((uint32_t)&exception_tbl+0x70) );
+ set_spr(SPR_IVOR8,((uint32_t)&exception_tbl+0x80) );
+ set_spr(SPR_IVOR9,((uint32_t)&exception_tbl+0x90) );
+ set_spr(SPR_IVOR10,((uint32_t)&exception_tbl+0xa0) );
+ set_spr(SPR_IVOR11,((uint32_t)&exception_tbl+0xb0) );
+ set_spr(SPR_IVOR12,((uint32_t)&exception_tbl+0xc0) );
+ set_spr(SPR_IVOR13,((uint32_t)&exception_tbl+0xd0) );
+ set_spr(SPR_IVOR14,((uint32_t)&exception_tbl+0xe0) );
+#if defined(CFG_SPE)
+ // SPE exceptions...map to dummy
+ set_spr(SPR_IVOR32,((uint32_t)&exception_tbl+0xf0) );
+ set_spr(SPR_IVOR33,((uint32_t)&exception_tbl+0xf0) );
+ set_spr(SPR_IVOR34,((uint32_t)&exception_tbl+0xf0) );
+#endif
+#endif
+
+ //
+ // Setup INTC
+ //
+ // according to manual
+ //
+ // 1. configure VTES_PRC0,VTES_PRC1,HVEN_PRC0 and HVEN_PRC1 in INTC_MCR
+ // 2. configure VTBA_PRCx in INTC_IACKR_PRCx
+ // 3. raise the PRIx fields and set the PRC_SELx fields to the desired processor in INTC_PSRx_x
+ // 4. set the enable bits or clear the mask bits for the peripheral interrupt requests
+ // 5. lower PRI in INTC_CPR_PRCx to zero
+ // 6. enable processor(s) recognition of interrupts
+
+ // Z1 init
+
+ #if defined(CFG_MPC5516)
+ INTC.MCR.B.HVEN_PRC0 = 0; // Soft vector mode
+ INTC.MCR.B.VTES_PRC0 = 0; // 4 byte offset between entries
+ #elif defined(CFG_MPC5554) || defined(CFG_MPC5567)
+ INTC.MCR.B.HVEN = 0; // Soft vector mode
+ INTC.MCR.B.VTES = 0; // 4 byte offset between entries
+ #endif
+
+
+ // Check alignment requirements for the INTC table
+ assert( (((uint32_t)&intc_vector_tbl[0]) & 0x7ff) == 0 );
+ #if defined(CFG_MPC5516)
+ INTC.IACKR_PRC0.R = (uint32_t) & intc_vector_tbl[0]; // Set INTC ISR vector table
+ #elif defined(CFG_MPC5554) || defined(CFG_MPC5567)
+ INTC.IACKR.R = (uint32_t) & intc_vector_tbl[0]; // Set INTC ISR vector table
+ #endif
+ // Pop the FIFO queue
+ for (int i = 0; i < 15; i++)
+ {
+ #if defined(CFG_MPC5516)
+ INTC.EOIR_PRC0.R = 0;
+ #elif defined(CFG_MPC5554) || defined(CFG_MPC5567)
+ INTC.EOIR.R = 0;
+ #endif
+ }
+
+ // Accept interrupts
+ #if defined(CFG_MPC5516)
+ INTC.CPR_PRC0.B.PRI = 0;
+ #elif defined(CFG_MPC5554) || defined(CFG_MPC5567)
+ INTC.CPR.B.PRI = 0;
+ #endif
+
+}
+
+
+void IntCtrl_EOI( void ) {
+#if defined(CFG_MPC5516)
+ struct INTC_tag *intc = &INTC;
+ intc->EOIR_PRC0.R = 0;
+#elif defined(CFG_MPC5554)||defined(CFG_MPC5567)
+ volatile struct INTC_tag *intc = &INTC;
+ intc->EOIR.R = 0;
+#endif
+}
+
+
+/**
+ *
+ * @param stack_p Ptr to the current stack.
+ *
+ * The stack holds C, NVGPR, VGPR and the EXC frame.
+ *
+ */
+void *IntCtrl_Entry( void *stack_p )
+{
+ uint32_t vector;
+ uint32_t *stack = (uint32_t *)stack_p;
+ uint32_t exc_vector = (EXC_OFF_FROM_BOTTOM+EXC_VECTOR_OFF) / sizeof(uint32_t);
+
+ // Check for exception
+ if( stack[exc_vector]>=CRITICAL_INPUT_EXCEPTION )
+ {
+ vector = stack[exc_vector];
+ }
+ else
+ {
+#if defined(CFG_MPC5516)
+ struct INTC_tag *intc = &INTC;
+ vector = (intc->IACKR_PRC0.B.INTVEC_PRC0);
+#elif defined(CFG_MPC5554)||defined(CFG_MPC5567)
+ volatile struct INTC_tag *intc = &INTC;
+ vector = (intc->IACKR.B.INTVEC);
+#endif
+ // save the vector for later
+ stack[exc_vector] = vector;
+
+ // Check for software interrupt
+ if((uint32_t)vector<=INTC_SSCIR0_CLR7)
+ {
+ // Clear soft int
+ intc->SSCIR[vector].B.CLR = 1;
+ asm("mbar 0");
+ }
+ }
+
+#if defined(USE_KERNEL)
+
+ if( intc_type_tbl[vector] == PROC_ISR1 ) {
+ // It's a function, just call it.
+ ((func_t)intc_vector_tbl[vector])();
+ return stack;
+ } else {
+ // It's a PCB
+ // Let the kernel handle the rest,
+ return Os_Isr(stack, (void *)intc_vector_tbl[vector]);
+ }
+
+
+#else
+ //read address
+ t = (func_t)intc_vector_tbl[vector];
+
+ if( t == ((void *)0) )
+ {
+ while(1);
+ }
+
+ // Enable nestling interrupts
+ Irq_Enable();
+ t();
+ Irq_Disable();
+
+ if( vector < INTC_NUMBER_OF_INTERRUPTS )
+ {
+ // write 0 to pop INTC stack
+ intc->EOIR_PRC0.R = 0;
+ }
+ return NULL;
+
+#endif
+}
+
+
+
+#if defined(USE_KERNEL)
+/**
+ * Attach an ISR type 1 to the interrupt controller.
+ *
+ * @param entry
+ * @param int_ctrl
+ * @param vector
+ * @param prio
+ */
+void IntCtrl_AttachIsr1( void (*entry)(void), void *int_ctrl, uint32_t vector,uint8_t prio) {
+ intc_vector_tbl[vector] = (void *)entry;
+ intc_type_tbl[vector] = PROC_ISR1;
+
+ if (vector < INTC_NUMBER_OF_INTERRUPTS) {
+#if defined(CFG_MPC5516)
+ uint8_t cpu = 0; /* 0- cpu Z1, 1-CPU Z0(slave) */
+ INTC.PSR[vector].B.PRC_SEL = cpu;
+#endif
+ INTC.PSR[vector].B.PRI = prio;
+
+ } else if ((vector >= CRITICAL_INPUT_EXCEPTION) && (vector
+ <= DEBUG_EXCEPTION)) {
+ } else {
+ /* Invalid vector! */
+ assert(0);
+ }
+
+}
+
+/**
+ * Attach a ISR type 2 to the interrupt controller.
+ *
+ * @param tid
+ * @param int_ctrl
+ * @param vector
+ */
+void IntCtrl_AttachIsr2(TaskType tid,void *int_ctrl,uint32_t vector ) {
+ pcb_t *pcb;
+
+ pcb = os_find_task(tid);
+ intc_vector_tbl[vector] = (void *)pcb;
+ intc_type_tbl[vector] = PROC_ISR2;
+
+ if (vector < INTC_NUMBER_OF_INTERRUPTS) {
+#if defined(CFG_MPC5516)
+ uint8_t cpu = 0; /* 0- cpu Z1, 1-CPU Z0(slave) */
+ INTC.PSR[vector].B.PRC_SEL = cpu;
+#endif
+ INTC.PSR[vector].B.PRI = pcb->prio;
+
+ } else if ((vector >= CRITICAL_INPUT_EXCEPTION) && (vector
+ <= DEBUG_EXCEPTION)) {
+ } else {
+ /* Invalid vector! */
+ assert(0);
+ }
+}
+
+#endif /* defined(USE_KERNEL) */
+
+#if !defined(USE_KERNEL)
+/**
+ * Installs a vector in intc vector table. It also sets the priority in the INTC
+ * internal registers.
+ *
+ * This does NOT use the kernel
+ *
+ * @param func The function to install
+ * @param vector INTC vector to install it to
+ * @param priority INTC priority. 0 - Low prio. 15- Highest( NMI )
+ * @param cpu
+ */
+
+void IntCtrl_InstallVector(void(*func)(), IrqType vector,
+ uint8_t priority, Cpu_t cpu)
+{
+ VALIDATE( ( 1 == Mcu_Global.initRun ), MCU_INTCVECTORINSTALL_SERVICE_ID, MCU_E_UNINIT );
+ DEBUG(DEBUG_LOW,"Installing INTC vector:%d,prio:%d,cpu,%d\n",vector,priority,cpu);
+ intc_vector_tbl[vector] = func;
+
+ if (vector <= MLB_SERVICE_REQUEST)
+ {
+ INTC.PSR[vector].B.PRC_SEL = cpu;
+ INTC.PSR[vector].B.PRI = priority;
+
+ intc_vector_tbl[vector] = func;
+ } else if ((vector >= CRITICAL_INPUT_EXCEPTION)
+ && (vector <= DEBUG_EXCEPTION))
+ {
+ intc_vector_tbl[vector] = func;
+ } else
+ {
+ /* Invalid vector! */
+ assert(0);
+ }
+}
+#endif
+
+
+
+/**
+ * Generates a soft interrupt
+ * @param vector
+ */
+void IntCtrl_GenerateSoftInt( IrqType vector ) {
+ if( vector > INTC_SSCIR0_CLR7 ) {
+ assert(0);
+ }
+
+ INTC.SSCIR[vector].B.SET = 1;
+}
+
+/**
+ * Get the current priority from the interrupt controller.
+ * @param cpu
+ * @return
+ */
+uint8_t IntCtrl_GetCurrentPriority( Cpu_t cpu) {
+
+ uint8_t prio;
+
+#if defined(CFG_MPC5516)
+ if( cpu == CPU_Z1 ) {
+ prio = INTC.CPR_PRC0.B.PRI;
+ } else if ( cpu == CPU_Z0 ) {
+ prio = INTC.CPR_PRC1.B.PRI;
+ }
+#elif defined(CFG_MPC5554)||defined(CFG_MPC5567)
+ prio = INTC.CPR.B.PRI;
+#endif
+
+ return prio;
+}
+
+
+
+void dummy (void);
+
+// Critical Input Interrupt
+void IVOR0Exception (uint32_t *regs)
+{
+// srr0 = get_spr(SPR_SRR0);
+// srr1 = get_spr(SPR_SRR0);
+// ExceptionSave(srr0,srr1,esr,mcsr,dear;)
+ // CSRR0, CSSR1
+ // Nothing more
+ dump_exception_regs(regs);
+ while (1);
+}
+
+// Machine check
+void IVOR1Exception (uint32_t *regs)
+{
+ // CSRR0, CSSR1
+ // MCSR - Source of machine check
+ dump_exception_regs(regs);
+ while (1);
+}
+// Data Storage Interrupt
+void IVOR2Exception (uint32_t *regs)
+{
+ // SRR0, SRR1
+ // ESR - lots of stuff
+ dump_exception_regs(regs);
+ while (1);
+}
+
+// Instruction Storage Interrupt
+void IVOR3Exception (uint32_t *regs)
+{
+ // SRR0, SRR1
+ // ESR - lots of stuff
+ dump_exception_regs(regs);
+ while (1);
+}
+
+// Alignment Interrupt
+void IVOR5Exception (uint32_t *regs)
+{
+ // SRR0, SRR1
+ // ESR - lots of stuff
+ // DEAR - Address of load store that caused the exception
+ dump_exception_regs(regs);
+ while (1);
+}
+
+// Program Interrupt
+void IVOR6Exception (uint32_t *regs)
+{
+ // SRR0, SRR1
+ // ESR - lots of stuff
+ dump_exception_regs(regs);
+ while (1);
+}
+
+// Floating point unavailable
+void IVOR7Exception (uint32_t *regs)
+{
+ // SRR0, SRR1
+ dump_exception_regs(regs);
+ while (1);
+}
+
+// System call
+void IVOR8Exception (uint32_t *regs)
+{
+ // SRR0, SRR1
+ // ESR
+ dump_exception_regs(regs);
+ while (1);
+}
+
+// Aux processor Unavailable
+void IVOR9Exception (uint32_t *regs)
+{
+ // Does not happen on e200
+ dump_exception_regs(regs);
+ while (1);
+}
+#if 0
+// Decrementer
+void IVOR10Exception (uint32_t *regs)
+{
+ // SRR0, SRR1
+ while (1);
+}
+#endif
+
+// FIT
+void IVOR11Exception (uint32_t *regs)
+{
+ // SRR0, SRR1
+ dump_exception_regs(regs);
+ while (1);
+}
+
+// Watchdog Timer
+void IVOR12Exception (uint32_t *regs)
+{
+ // SRR0, SRR1
+ dump_exception_regs(regs);
+ while (1);
+}
+
+// Data TLB Error Interrupt
+void IVOR13Exception (uint32_t *regs)
+{
+
+ // SRR0, SRR1
+ // ESR - lots
+ // DEAR -
+ while (1);
+}
+
+// Instruction TLB Error Interupt
+void IVOR14Exception (uint32_t *regs)
+{
+ // SRR0, SRR1
+ // ESR - MIF set, All others cleared
+ dump_exception_regs(regs);
+ while (1);
+}
+
+void IVOR15Exception (uint32_t *regs)
+{
+ // Debug
+ dump_exception_regs(regs);
+ while (1);
+}
+
+#if defined(CFG_CONSOLE_T32) || defined(CFG_CONSOLE_WINIDEA)
+
+typedef struct {
+ uint32_t sp;
+ uint32_t bc; // backchain
+ uint32_t pad;
+ uint32_t srr0;
+ uint32_t srr1;
+ uint32_t lr;
+ uint32_t ctr;
+ uint32_t xer;
+ uint32_t cr;
+ uint32_t esr;
+ uint32_t mcsr;
+ uint32_t dear;
+ uint32_t vector;
+ uint32_t r3;
+ uint32_t r4;
+} exc_stack_t;
+
+
+
+static void dump_exception_regs( uint32_t *regs ) {
+ exc_stack_t *r = (exc_stack_t *)regs;
+
+ dbg_printf("sp %08x srr0 %08x srr1 %08x\n",r->sp,r->srr0,r->srr1);
+ dbg_printf("lr %08x ctr %08x xer %08x\n",r->lr,r->ctr,r->xer);
+ dbg_printf("cr %08x esr %08x mcsr %08x\n",r->cr,r->esr,r->mcsr);
+ dbg_printf("dear %08x vec %08x r3 %08x\n",r->dear,r->vector,r->r3);
+ dbg_printf("r4 %08x\n",r->r4);
+}
+
+#else
+static void dump_exception_regs( uint32_t *regs ) {
+}
+#endif
+
+#if !defined(USE_KERNEL)
+func_t intc_vector_tbl[NUMBER_OF_INTERRUPTS_AND_EXCEPTIONS] __attribute__ ((aligned (0x800))) = {
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 00 - 04 */
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 05 - 09 */
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 10 - 14 */
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 15 - 19 */
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 20 - 24 */
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 25 - 29 */
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 30 - 34 */
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 35 - 39 */
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 40 - 44 */
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 45 - 49 */
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 50 - 54 */
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 55 - 59 */
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 60 - 64 */
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 55 - 69 */
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 70 - 74 */
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 75 - 79 */
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 80 - 84 */
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 85 - 89 */
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 90 - 94 */
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 95 - 99 */
+
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 100 - 104 */
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 105 - 109 */
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 110 - 114 */
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 115 - 119 */
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 120 - 124 */
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 125 - 129 */
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 130 - 134 */
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 135 - 139 */
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 140 - 144 */
+ dummy, dummy, dummy, dummy, dummy /* PIT1 */, /* ISRs 145 - 149 */
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 150 - 154 */
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 155 - 159 */
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 160 - 164 */
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 155 - 169 */
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 170 - 174 */
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 175 - 179 */
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 180 - 184 */
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 185 - 189 */
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 190 - 194 */
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 195 - 199 */
+
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 200 - 204 */
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 205 - 209 */
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 210 - 214 */
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 215 - 219 */
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 220 - 224 */
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 225 - 229 */
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 230 - 234 */
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 235 - 239 */
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 240 - 244 */
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 245 - 249 */
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 250 - 254 */
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 255 - 259 */
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 260 - 264 */
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 255 - 269 */
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 270 - 274 */
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 275 - 279 */
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 280 - 284 */
+ dummy, dummy, dummy, dummy, dummy, /* ISRs 285 - 289 */
+ dummy, dummy, dummy, dummy, /* ISRs 290 - 293 */
+
+ /* Some reserved vectors between INC interrupts and exceptions. */
+ dummy, /* INTC_NUMBER_OF_INTERRUPTS */
+
+ dummy, dummy, dummy, dummy, dummy,
+ dummy, dummy, dummy, dummy, dummy,
+ dummy, dummy, dummy, dummy, dummy,
+ dummy, dummy, dummy, dummy, dummy,
+ dummy, dummy, dummy, dummy, dummy,
+
+ IVOR0Exception, /* CRITICAL_INPUT_EXCEPTION, */
+ IVOR1Exception, /* MACHINE_CHECK_EXCEPTION */
+ IVOR2Exception, /* DATA_STORAGE_EXCEPTION */
+ IVOR3Exception, /* INSTRUCTION_STORAGE_EXCEPTION */
+ dummy, /* EXTERNAL_INTERRUPT */
+ /* This is the place where the "normal" interrupts will hit the CPU... */
+ IVOR5Exception, /* ALIGNMENT_EXCEPTION */
+ IVOR6Exception, /* PROGRAM_EXCEPTION */
+ IVOR7Exception, /* FLOATING_POINT_EXCEPTION */
+ IVOR8Exception, /* SYSTEM_CALL_EXCEPTION */
+ dummy, /* AUX_EXCEPTION Not implemented in MPC5516. */
+ dummy, /* DECREMENTER_EXCEPTION */
+ IVOR11Exception, /* FIXED_INTERVAL_TIMER_EXCEPTION */
+ IVOR12Exception, /* WATCHDOG_TIMER_EXCEPTION */
+ IVOR13Exception, /* DATA_TLB_EXCEPTION */
+ IVOR14Exception, /* INSTRUCTION_TLB_EXCEPTION */
+ IVOR15Exception, /* DEBUG_EXCEPTION */
+};
+
+void dummy (void) {
+ while (1){
+ /* TODO: Rename and check for what spurious interrupt have happend */
+ };
+ }
+
+#endif
+
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*
+ * irq.h
+ *
+ * Defines some additional types used for mpc55xx
+ *
+ * Created on: Jul 13, 2009
+ * Author: mahi
+ */
+
+#ifndef IRQ_H
+#define IRQ_H
+
+
+typedef enum
+{
+ /* Software interrupts. */
+ INTC_SSCIR0_CLR0, // 0
+ INTC_SSCIR0_CLR1, // 1
+ INTC_SSCIR0_CLR2, // 2
+ INTC_SSCIR0_CLR3, // 3
+ INTC_SSCIR0_CLR4, // 4
+ INTC_SSCIR0_CLR5, // 5
+ INTC_SSCIR0_CLR6, // 6
+ INTC_SSCIR0_CLR7, // 7
+ MCM_MSWTIR_SWTIC, // 8
+ MCM_ESR_COMB, // 9
+ /* eDMA */
+ EDMA_ERRL_ERR31_0, // 10
+ EDMA_INTL_INT0, // 11
+ EDMA_INTL_INT1,
+ EDMA_INTL_INT2,
+ EDMA_INTL_INT3,
+ EDMA_INTL_INT4,
+ EDMA_INTL_INT5,
+ EDMA_INTL_INT6,
+ EDMA_INTL_INT7,
+ EDMA_INTL_INT8,
+ EDMA_INTL_INT9,
+ EDMA_INTL_INT10,
+ EDMA_INTL_INT11,
+ EDMA_INTL_INT12,
+ EDMA_INTL_INT13,
+ EDMA_INTL_INT14,
+ EDMA_INTL_INT15, // 26
+#if defined(CFG_MPC5554)||defined(CFG_MPC5567)
+ EDMA_INTL_INT16,
+ EDMA_INTL_INT17,
+ EDMA_INTL_INT18,
+ EDMA_INTL_INT19, // 30
+ EDMA_INTL_INT20,
+ EDMA_INTL_INT21,
+ EDMA_INTL_INT22,
+ EDMA_INTL_INT23,
+ EDMA_INTL_INT24,
+ EDMA_INTL_INT25,
+ EDMA_INTL_INT26,
+ EDMA_INTL_INT27,
+ EDMA_INTL_INT28,
+ EDMA_INTL_INT29,
+ EDMA_INTL_INT30,
+ EDMA_INTL_INT31, // 42
+#else
+ RESERVED0,
+ RESERVED1,
+ RESERVED2,
+ RESERVED3, // 30
+ RESERVED4,
+ RESERVED5,
+ RESERVED6,
+ RESERVED7,
+ RESERVED8,
+ RESERVED9,
+ RESERVED10,
+ RESERVED11,
+ RESERVED12,
+ RESERVED13,
+ RESERVED14,
+ RESERVED15, // 42
+#endif
+
+#if defined(CFG_MPC5516)
+ /* Semahpore's */
+ SEMAPHORE_INT0, // 43
+ SEMAPHORE_INT1,
+ RESERVED16,
+ CRP_INTERRUPT,
+ LVI_INTERRUPT,
+ IIC_A_IBSR_IBIF,
+ RESERVED17,
+#endif
+ PLL_SYNSR_LOCF, // 54-43, 16-50
+ PLL_SYNSR_LOLF, // 54-44, 16-51
+ SIU_OSR_OVER,
+ /* External interrupts */
+ SIU_EISR_EIF0, // 53
+ SIU_EISR_EIF1,
+ SIU_EISR_EIF2,
+ SIU_EISR_EIF3,
+ SIU_EISR_EIF15_4, // 54-50, 57
+
+ /* eMIOS */
+ EMISOS200_FLAG_F0, // 58
+ EMISOS200_FLAG_F1,
+ EMISOS200_FLAG_F2,
+ EMISOS200_FLAG_F3,
+ EMISOS200_FLAG_F4,
+ EMISOS200_FLAG_F5,
+ EMISOS200_FLAG_F6,
+ EMISOS200_FLAG_F7,
+ EMISOS200_FLAG_F8,
+ EMISOS200_FLAG_F9,
+ EMISOS200_FLAG_F10,
+ EMISOS200_FLAG_F11,
+ EMISOS200_FLAG_F12,
+ EMISOS200_FLAG_F13,
+ EMISOS200_FLAG_F14,
+ EMISOS200_FLAG_F15, // 73
+#if defined(CFG_MPC5516)
+ EMISOS200_FLAG_F16,
+ EMISOS200_FLAG_F17,
+ EMISOS200_FLAG_F18,
+ EMISOS200_FLAG_F19,
+ EMISOS200_FLAG_F20,
+ EMISOS200_FLAG_F21,
+ EMISOS200_FLAG_F22,
+ EMISOS200_FLAG_F23, // 16-81
+#elif defined(CFG_MPC5554)||defined(CFG_MPC5567)
+ ETPU_GLOBAL, // 54-67
+ ETPU_A_CIS_0,
+ ETPU_A_CIS_1,
+ ETPU_A_CIS_2, // 54-70
+ ETPU_A_CIS_3,
+ ETPU_A_CIS_4,
+ ETPU_A_CIS_5,
+ ETPU_A_CIS_6,
+ ETPU_A_CIS_7,
+ ETPU_A_CIS_8,
+ ETPU_A_CIS_9,
+ ETPU_A_CIS_10,
+ ETPU_A_CIS_11,
+ ETPU_A_CIS_12, // 54-80
+ ETPU_A_CIS_13,
+ ETPU_A_CIS_14,
+ ETPU_A_CIS_15,
+ ETPU_A_CIS_16,
+ ETPU_A_CIS_17,
+ ETPU_A_CIS_18,
+ ETPU_A_CIS_19,
+ ETPU_A_CIS_20,
+ ETPU_A_CIS_21,
+ ETPU_A_CIS_22, // 54-90
+ ETPU_A_CIS_23,
+ ETPU_A_CIS_24,
+ ETPU_A_CIS_25,
+ ETPU_A_CIS_26,
+ ETPU_A_CIS_27,
+ ETPU_A_CIS_28,
+ ETPU_A_CIS_29,
+ ETPU_A_CIS_30,
+ ETPU_A_CIS_31, // 99
+#endif
+
+ /* eQADC */
+ EQADC_FISR_OVER, // 54-100, 16-82
+ EQADC_FISR0_NCF0,
+ EQADC_FISR0_PF0,
+ EQADC_FISR0_EOQF0,
+ EQADC_FISR0_CFFF0,
+ EQADC_FISR0_RFDF0,
+ EQADC_FISR1_NCF1,
+ EQADC_FISR1_PF1,
+ EQADC_FISR1_EOQF1,
+ EQADC_FISR1_CFFF1,
+ EQADC_FISR1_RFDF1, // 110, 92
+ EQADC_FISR2_NCF2,
+ EQADC_FISR2_PF2,
+ EQADC_FISR2_EOQF2,
+ EQADC_FISR2_CFFF2,
+ EQADC_FISR2_RFDF2,
+ EQADC_FISR3_NCF3,
+ EQADC_FISR3_PF3,
+ EQADC_FISR3_EOQF3,
+ EQADC_FISR3_CFFF3,
+ EQADC_FISR3_RFDF3, // 120, 102
+ EQADC_FISR4_NCF4,
+ EQADC_FISR4_PF4,
+ EQADC_FISR4_EOQF4,
+ EQADC_FISR4_CFFF4,
+ EQADC_FISR4_RFDF4,
+ EQADC_FISR5_NCF5,
+ EQADC_FISR5_PF5,
+ EQADC_FISR5_EOQF5,
+ EQADC_FISR5_CFFF5,
+ EQADC_FISR5_RFDF5, // 130, 112
+
+#if defined(CFG_MPC5516)
+ /* SCI */
+ SCI_A_COMB, // 16-113
+ SCI_B_COMB,
+ SCI_C_COMB,
+ SCI_D_COMB,
+ /* DSPI A,B */
+ DSPI_A_ISR_OVER,
+ DSPI_A_ISR_EOQF,
+ DSPI_A_ISR_TFFF,
+ DSPI_A_ISR_TCF,
+ DSPI_A_ISR_RFDF,
+ DSPI_B_ISR_OVER, // 16-122
+ DSPI_B_ISR_EOQF,
+ DSPI_B_ISR_TFFF,
+ DSPI_B_ISR_TCF,
+ DSPI_B_ISR_RFDF,
+#elif defined(CFG_MPC5554)||defined(CFG_MPC5567)
+ DSPI_B_COMB, // 54-131
+ DSPI_B_ISR_EOQF,
+ DSPI_B_ISR_TFFF,
+ DSPI_B_ISR_TCF,
+ DSPI_B_ISR_RFDF, // 54-135
+ DSPI_C_COMB,
+ DSPI_C_ISR_EOQF,
+ DSPI_C_ISR_TFFF,
+ DSPI_C_ISR_TCF,
+ DSPI_C_ISR_RFDF, // 54-140
+ DSPI_D_COMB,
+ DSPI_D_ISR_EOQF,
+ DSPI_D_ISR_TFFF,
+ DSPI_D_ISR_TCF,
+ DSPI_D_ISR_RFDF, // 54-145
+
+ ESCI_A_COMB0,
+ RESERVED0,
+ RESERVED1,
+ ESCI_A_COMB1,
+ RESERVED2,
+ RESERVED3, // 54-151
+#endif
+
+ /* FlexCAN A */
+
+ FLEXCAN_A_ESR_BOFF_INT, // 54-152, 16-127
+ FLEXCAN_A_ESR_ERR_INT,
+ RESERVED18,
+ FLEXCAN_A_IFLAG1_BUF0I,
+ FLEXCAN_A_IFLAG1_BUF1I,
+ FLEXCAN_A_IFLAG1_BUF2I,
+ FLEXCAN_A_IFLAG1_BUF3I,
+ FLEXCAN_A_IFLAG1_BUF4I,
+ FLEXCAN_A_IFLAG1_BUF5I,
+ FLEXCAN_A_IFLAG1_BUF6I,
+ FLEXCAN_A_IFLAG1_BUF7I,
+ FLEXCAN_A_IFLAG1_BUF8I,
+ FLEXCAN_A_IFLAG1_BUF9I,
+ FLEXCAN_A_IFLAG1_BUF10I,
+ FLEXCAN_A_IFLAG1_BUF11I,
+ FLEXCAN_A_IFLAG1_BUF12I,
+ FLEXCAN_A_IFLAG1_BUF13I,
+ FLEXCAN_A_IFLAG1_BUF14I,
+ FLEXCAN_A_IFLAG1_BUF15I,
+ FLEXCAN_A_IFLAG1_BUF31_16I,
+ FLEXCAN_A_IFLAG1_BUF63_32I,
+
+#if defined(CFG_MPC5516)
+ /* Periodic interrupt timer */
+ PIT_PITFLG_RTIF,
+ PIT_PITFLG_PIT1,
+ PIT_PITFLG_PIT2,
+ PIT_PITFLG_PIT3,
+ PIT_PITFLG_PIT4,
+ PIT_PITFLG_PIT5,
+ PIT_PITFLG_PIT6,
+ PIT_PITFLG_PIT7,
+ PIT_PITFLG_PIT8,
+
+ /* FlexCAN B */
+ FLEXCAN_B_ESR_BOFF_INT,
+ FLEXCAN_B_ESR_ERR_INT,
+ RESERVED19,
+ FLEXCAN_B_IFLAG1_BUF0I,
+ FLEXCAN_B_IFLAG1_BUF1I,
+ FLEXCAN_B_IFLAG1_BUF2I,
+ FLEXCAN_B_IFLAG1_BUF3I,
+ FLEXCAN_B_IFLAG1_BUF4I,
+ FLEXCAN_B_IFLAG1_BUF5I,
+ FLEXCAN_B_IFLAG1_BUF6I,
+ FLEXCAN_B_IFLAG1_BUF7I,
+ FLEXCAN_B_IFLAG1_BUF8I,
+ FLEXCAN_B_IFLAG1_BUF9I,
+ FLEXCAN_B_IFLAG1_BUF10I,
+ FLEXCAN_B_IFLAG1_BUF11I,
+ FLEXCAN_B_IFLAG1_BUF12I,
+ FLEXCAN_B_IFLAG1_BUF13I,
+ FLEXCAN_B_IFLAG1_BUF14I,
+ FLEXCAN_B_IFLAG1_BUF15I,
+ FLEXCAN_B_IFLAG1_BUF31_16I,
+ FLEXCAN_B_IFLAG1_BUF63_32I,
+ /* FlexCAN C */
+ FLEXCAN_C_ESR_BOFF_INT,
+ FLEXCAN_C_ESR_ERR_INT,
+ RESERVED20,
+ FLEXCAN_C_IFLAG1_BUF0I,
+ FLEXCAN_C_IFLAG1_BUF1I,
+ FLEXCAN_C_IFLAG1_BUF2I,
+ FLEXCAN_C_IFLAG1_BUF3I,
+ FLEXCAN_C_IFLAG1_BUF4I,
+ FLEXCAN_C_IFLAG1_BUF5I,
+ FLEXCAN_C_IFLAG1_BUF6I,
+ FLEXCAN_C_IFLAG1_BUF7I,
+ FLEXCAN_C_IFLAG1_BUF8I,
+ FLEXCAN_C_IFLAG1_BUF9I,
+ FLEXCAN_C_IFLAG1_BUF10I,
+ FLEXCAN_C_IFLAG1_BUF11I,
+ FLEXCAN_C_IFLAG1_BUF12I,
+ FLEXCAN_C_IFLAG1_BUF13I,
+ FLEXCAN_C_IFLAG1_BUF14I,
+ FLEXCAN_C_IFLAG1_BUF15I,
+ FLEXCAN_C_IFLAG1_BUF31_16I,
+ FLEXCAN_C_IFLAG1_BUF63_32I,
+ /* FlexCAN D */
+ FLEXCAN_D_ESR_BOFF_INT,
+ FLEXCAN_D_ESR_ERR_INT,
+ RESERVED21,
+ FLEXCAN_D_IFLAG1_BUF0I,
+ FLEXCAN_D_IFLAG1_BUF1I,
+ FLEXCAN_D_IFLAG1_BUF2I,
+ FLEXCAN_D_IFLAG1_BUF3I,
+ FLEXCAN_D_IFLAG1_BUF4I,
+ FLEXCAN_D_IFLAG1_BUF5I,
+ FLEXCAN_D_IFLAG1_BUF6I,
+ FLEXCAN_D_IFLAG1_BUF7I,
+ FLEXCAN_D_IFLAG1_BUF8I,
+ FLEXCAN_D_IFLAG1_BUF9I,
+ FLEXCAN_D_IFLAG1_BUF10I,
+ FLEXCAN_D_IFLAG1_BUF11I,
+ FLEXCAN_D_IFLAG1_BUF12I,
+ FLEXCAN_D_IFLAG1_BUF13I,
+ FLEXCAN_D_IFLAG1_BUF14I,
+ FLEXCAN_D_IFLAG1_BUF15I,
+ FLEXCAN_D_IFLAG1_BUF31_16I,
+ FLEXCAN_D_IFLAG1_BUF63_32I,
+ /* FlexCAN E */
+ FLEXCAN_E_ESR_BOFF_INT,
+ FLEXCAN_E_ESR_ERR_INT,
+ RESERVED22,
+ FLEXCAN_E_IFLAG1_BUF0I,
+ FLEXCAN_E_IFLAG1_BUF1I,
+ FLEXCAN_E_IFLAG1_BUF2I,
+ FLEXCAN_E_IFLAG1_BUF3I,
+ FLEXCAN_E_IFLAG1_BUF4I,
+ FLEXCAN_E_IFLAG1_BUF5I,
+ FLEXCAN_E_IFLAG1_BUF6I,
+ FLEXCAN_E_IFLAG1_BUF7I,
+ FLEXCAN_E_IFLAG1_BUF8I,
+ FLEXCAN_E_IFLAG1_BUF9I,
+ FLEXCAN_E_IFLAG1_BUF10I,
+ FLEXCAN_E_IFLAG1_BUF11I,
+ FLEXCAN_E_IFLAG1_BUF12I,
+ FLEXCAN_E_IFLAG1_BUF13I,
+ FLEXCAN_E_IFLAG1_BUF14I,
+ FLEXCAN_E_IFLAG1_BUF15I,
+ FLEXCAN_E_IFLAG1_BUF31_16I,
+ FLEXCAN_E_IFLAG1_BUF63_32I,
+ /* FlexCAN F */
+ FLEXCAN_F_ESR_BOFF_INT,
+ FLEXCAN_F_ESR_ERR_INT,
+ RESERVED23,
+ FLEXCAN_F_IFLAG1_BUF0I,
+ FLEXCAN_F_IFLAG1_BUF1I,
+ FLEXCAN_F_IFLAG1_BUF2I,
+ FLEXCAN_F_IFLAG1_BUF3I,
+ FLEXCAN_F_IFLAG1_BUF4I,
+ FLEXCAN_F_IFLAG1_BUF5I,
+ FLEXCAN_F_IFLAG1_BUF6I,
+ FLEXCAN_F_IFLAG1_BUF7I,
+ FLEXCAN_F_IFLAG1_BUF8I,
+ FLEXCAN_F_IFLAG1_BUF9I,
+ FLEXCAN_F_IFLAG1_BUF10I,
+ FLEXCAN_F_IFLAG1_BUF11I,
+ FLEXCAN_F_IFLAG1_BUF12I,
+ FLEXCAN_F_IFLAG1_BUF13I,
+ FLEXCAN_F_IFLAG1_BUF14I,
+ FLEXCAN_F_IFLAG1_BUF15I,
+ FLEXCAN_F_IFLAG1_BUF31_16I,
+ FLEXCAN_F_IFLAG1_BUF63_32I,
+ RESERVED24,
+ RESERVED25,
+ RESERVED26,
+ RESERVED27,
+ RESERVED28,
+ RESERVED29,
+ RESERVED30,
+ RESERVED31,
+ /* SCI */
+ SCI_E_COMB,
+ SCI_F_COMB,
+ SCI_G_COMB,
+ SCI_H_COMB,
+ /* DSPI */
+ DSPI_C_ISR_OVER,
+ DSPI_C_ISR_EOQF,
+ DSPI_C_ISR_TFFF,
+ DSPI_C_ISR_TCF,
+ DSPI_C_ISR_RFDF,
+ DSPI_D_ISR_OVER,
+ DSPI_D_ISR_EOQF,
+ DSPI_D_ISR_TFFF,
+ DSPI_D_ISR_TCF,
+ DSPI_D_ISR_RFDF,
+ /* Flexray */
+ FLEXRAY_GLOB,
+ FLEXRAY_PRIF,
+ FLEXRAY_CHIF,
+ FLEXRAY_WUP_IF,
+ FLEXRAY_FBNE_F,
+ FLEXRAY_FANE_F,
+ FLEXRAY_RBIF,
+ FLEXRAY_TBIF,
+ RESERVED32,
+ MLB_SERVICE_REQUEST,
+ INTC_NUMBER_OF_INTERRUPTS,
+ /* End of INTC interrupts. The vectors below are used to handle exceptions. */
+ RESERVED_SPACE_BEFORE_EXCEPTIONS1,
+ RESERVED_SPACE_BEFORE_EXCEPTIONS2,
+ RESERVED_SPACE_BEFORE_EXCEPTIONS3,
+ RESERVED_SPACE_BEFORE_EXCEPTIONS4,
+ RESERVED_SPACE_BEFORE_EXCEPTIONS5,
+ RESERVED_SPACE_BEFORE_EXCEPTIONS6,
+ RESERVED_SPACE_BEFORE_EXCEPTIONS7,
+ RESERVED_SPACE_BEFORE_EXCEPTIONS8,
+ RESERVED_SPACE_BEFORE_EXCEPTIONS9,
+ RESERVED_SPACE_BEFORE_EXCEPTIONS10,
+ RESERVED_SPACE_BEFORE_EXCEPTIONS11,
+ RESERVED_SPACE_BEFORE_EXCEPTIONS12,
+ RESERVED_SPACE_BEFORE_EXCEPTIONS13,
+ RESERVED_SPACE_BEFORE_EXCEPTIONS14,
+ RESERVED_SPACE_BEFORE_EXCEPTIONS15,
+ RESERVED_SPACE_BEFORE_EXCEPTIONS16,
+ RESERVED_SPACE_BEFORE_EXCEPTIONS17,
+ RESERVED_SPACE_BEFORE_EXCEPTIONS18,
+ RESERVED_SPACE_BEFORE_EXCEPTIONS19,
+ RESERVED_SPACE_BEFORE_EXCEPTIONS20,
+ RESERVED_SPACE_BEFORE_EXCEPTIONS21,
+ RESERVED_SPACE_BEFORE_EXCEPTIONS22,
+ RESERVED_SPACE_BEFORE_EXCEPTIONS23,
+ RESERVED_SPACE_BEFORE_EXCEPTIONS24,
+ RESERVED_SPACE_BEFORE_EXCEPTIONS25,
+#endif
+
+#if defined(CFG_MPC5554)||defined(CFG_MPC5567)
+ /* FlexCAN C */
+ FLEXCAN_C_ESR_BOFF_INT = 173,
+ FLEXCAN_C_ESR_ERR_INT,
+ RESERVED20,
+ FLEXCAN_C_IFLAG1_BUF0I,
+ FLEXCAN_C_IFLAG1_BUF1I,
+ FLEXCAN_C_IFLAG1_BUF2I,
+ FLEXCAN_C_IFLAG1_BUF3I,
+ FLEXCAN_C_IFLAG1_BUF4I,
+ FLEXCAN_C_IFLAG1_BUF5I,
+ FLEXCAN_C_IFLAG1_BUF6I,
+ FLEXCAN_C_IFLAG1_BUF7I,
+ FLEXCAN_C_IFLAG1_BUF8I,
+ FLEXCAN_C_IFLAG1_BUF9I,
+ FLEXCAN_C_IFLAG1_BUF10I,
+ FLEXCAN_C_IFLAG1_BUF11I,
+ FLEXCAN_C_IFLAG1_BUF12I,
+ FLEXCAN_C_IFLAG1_BUF13I,
+ FLEXCAN_C_IFLAG1_BUF14I,
+ FLEXCAN_C_IFLAG1_BUF15I,
+ FLEXCAN_C_IFLAG1_BUF31_16I,
+ FLEXCAN_C_IFLAG1_BUF63_32I,
+
+ // ....
+
+ // 275
+ DSPI_A_COMB = 275, // 54-131
+ DSPI_A_ISR_EOQF,
+ DSPI_A_ISR_TFFF,
+ DSPI_A_ISR_TCF,
+ DSPI_A_ISR_RFDF, // 54-135
+
+ /* FlexCAN B */
+ FLEXCAN_B_ESR_BOFF_INT = 280,
+ FLEXCAN_B_ESR_ERR_INT,
+ RESERVED21,
+ FLEXCAN_B_IFLAG1_BUF0I,
+ FLEXCAN_B_IFLAG1_BUF1I,
+ FLEXCAN_B_IFLAG1_BUF2I,
+ FLEXCAN_B_IFLAG1_BUF3I,
+ FLEXCAN_B_IFLAG1_BUF4I,
+ FLEXCAN_B_IFLAG1_BUF5I,
+ FLEXCAN_B_IFLAG1_BUF6I,
+ FLEXCAN_B_IFLAG1_BUF7I,
+ FLEXCAN_B_IFLAG1_BUF8I,
+ FLEXCAN_B_IFLAG1_BUF9I,
+ FLEXCAN_B_IFLAG1_BUF10I,
+ FLEXCAN_B_IFLAG1_BUF11I,
+ FLEXCAN_B_IFLAG1_BUF12I,
+ FLEXCAN_B_IFLAG1_BUF13I,
+ FLEXCAN_B_IFLAG1_BUF14I,
+ FLEXCAN_B_IFLAG1_BUF15I,
+ FLEXCAN_B_IFLAG1_BUF31_16I,
+ FLEXCAN_B_IFLAG1_BUF63_32I,
+
+ /* FlexCAN D */
+ FLEXCAN_D_ESR_BOFF_INT = 308,
+ FLEXCAN_D_ESR_ERR_INT,
+ RESERVED22,
+ FLEXCAN_D_IFLAG1_BUF0I,
+ FLEXCAN_D_IFLAG1_BUF1I,
+ FLEXCAN_D_IFLAG1_BUF2I,
+ FLEXCAN_D_IFLAG1_BUF3I,
+ FLEXCAN_D_IFLAG1_BUF4I,
+ FLEXCAN_D_IFLAG1_BUF5I,
+ FLEXCAN_D_IFLAG1_BUF6I,
+ FLEXCAN_D_IFLAG1_BUF7I,
+ FLEXCAN_D_IFLAG1_BUF8I,
+ FLEXCAN_D_IFLAG1_BUF9I,
+ FLEXCAN_D_IFLAG1_BUF10I,
+ FLEXCAN_D_IFLAG1_BUF11I,
+ FLEXCAN_D_IFLAG1_BUF12I,
+ FLEXCAN_D_IFLAG1_BUF13I,
+ FLEXCAN_D_IFLAG1_BUF14I,
+ FLEXCAN_D_IFLAG1_BUF15I,
+ FLEXCAN_D_IFLAG1_BUF31_16I,
+ FLEXCAN_D_IFLAG1_BUF63_32I,
+
+ /* FlexCAN E */
+ FLEXCAN_E_ESR_BOFF_INT = 329,
+ FLEXCAN_E_ESR_ERR_INT,
+ RESERVED23,
+ FLEXCAN_E_IFLAG1_BUF0I,
+ FLEXCAN_E_IFLAG1_BUF1I,
+ FLEXCAN_E_IFLAG1_BUF2I,
+ FLEXCAN_E_IFLAG1_BUF3I,
+ FLEXCAN_E_IFLAG1_BUF4I,
+ FLEXCAN_E_IFLAG1_BUF5I,
+ FLEXCAN_E_IFLAG1_BUF6I,
+ FLEXCAN_E_IFLAG1_BUF7I,
+ FLEXCAN_E_IFLAG1_BUF8I,
+ FLEXCAN_E_IFLAG1_BUF9I,
+ FLEXCAN_E_IFLAG1_BUF10I,
+ FLEXCAN_E_IFLAG1_BUF11I,
+ FLEXCAN_E_IFLAG1_BUF12I,
+ FLEXCAN_E_IFLAG1_BUF13I,
+ FLEXCAN_E_IFLAG1_BUF14I,
+ FLEXCAN_E_IFLAG1_BUF15I,
+ FLEXCAN_E_IFLAG1_BUF31_16I,
+ FLEXCAN_E_IFLAG1_BUF63_32I,
+
+ INTC_NUMBER_OF_INTERRUPTS,
+
+ DUMMY_DUMMY = 319,
+
+#endif /* defined(CFG_MPC5554)||defined(CFG_MPC5567) */
+
+ CRITICAL_INPUT_EXCEPTION,
+ MACHINE_CHECK_EXCEPTION,
+ DATA_STORAGE_EXCEPTION,
+ INSTRUCTION_STORAGE_EXCEPTION,
+ EXTERNAL_INTERRUPT, /* This is the place where the "normal" interrupts will hit the CPU... */
+ ALIGNMENT_EXCEPTION,
+ PROGRAM_EXCEPTION,
+ FLOATING_POINT_EXCEPTION,
+ SYSTEM_CALL_EXCEPTION,
+ AUX_EXCEPTION,
+ DECREMENTER_EXCEPTION,
+ FIXED_INTERVAL_TIMER_EXCEPTION,
+ WATCHDOG_TIMER_EXCEPTION,
+ DATA_TLB_EXCEPTION,
+ INSTRUCTION_TLB_EXCEPTION,
+ DEBUG_EXCEPTION,
+ NUMBER_OF_INTERRUPTS_AND_EXCEPTIONS,
+}IrqType;
+
+typedef enum {
+ PERIPHERAL_CLOCK_FLEXCAN_A,
+ PERIPHERAL_CLOCK_FLEXCAN_B,
+ PERIPHERAL_CLOCK_FLEXCAN_C,
+ PERIPHERAL_CLOCK_FLEXCAN_D,
+ PERIPHERAL_CLOCK_FLEXCAN_E,
+ PERIPHERAL_CLOCK_FLEXCAN_F,
+ PERIPHERAL_CLOCK_PIT,
+ PERIPHERAL_CLOCK_DSPI_A,
+ PERIPHERAL_CLOCK_DSPI_B,
+ PERIPHERAL_CLOCK_DSPI_C,
+ PERIPHERAL_CLOCK_DSPI_D,
+ PERIPHERAL_CLOCK_EMIOS,
+ PERIPHERAL_CLOCK_ESCI_A,
+ PERIPHERAL_CLOCK_ESCI_B,
+ PERIPHERAL_CLOCK_ESCI_C,
+ PERIPHERAL_CLOCK_ESCI_D,
+ PERIPHERAL_CLOCK_ESCI_E,
+ PERIPHERAL_CLOCK_ESCI_F,
+ PERIPHERAL_CLOCK_ESCI_G,
+ PERIPHERAL_CLOCK_ESCI_H,
+ PERIPHERAL_CLOCK_IIC_A,
+ PERIPHERAL_CLOCK_MLB,
+} McuE_PeriperalClock_t;
+
+
+#if defined(CFG_MPC5516)
+typedef enum {
+ CPU_Z1=0,
+ CPU_Z0,
+} Cpu_t;
+#else
+typedef uint8_t Cpu_t;
+#endif
+
+
+#endif /* IRQ_H_ */
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef CACHE_H_\r
+#define CACHE_H_\r
+\r
+#endif /*CACHE_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef MM_H_\r
+#define MM_H_\r
+\r
+/* [address: XXXXXX/auto]\r
+ * \r
+ * application: xx\r
+ * allocation: [auto/manual]\r
+ * - allocates text,data,bsss\r
+ * [segment: text]\r
+ * size: rolldown with sizes... auto??\r
+ *\r
+ * application: xx\r
+ * segment: special\r
+ * address: [auto/manual]\r
+ * permissions: \r
+ * size: \r
+ * \r
+ * CPU dependent\r
+ * -------------------------------\r
+ * ENUM [\r
+ * PU,\r
+ * MMU,\r
+ * ] MM_TYPE\r
+ *\r
+ * ENUM [\r
+ * PSIZE_PU_????\r
+ * \r
+ * ] MM_PU_PSIZE;\r
+ * \r
+ * ENUM [\r
+ * PSIZE_1K,\r
+ * PSIZE_4K,\r
+ * PSIZE_64K,\r
+ * PSIZE_1M, \r
+ * ] MM_MMU_PSIZE; \r
+ * \r
+ * ENUM [\r
+ * PERM_S_R,\r
+ * PERM_S_RW,\r
+ * ....\r
+ * ] MM_PERMISSIONS\r
+ * \r
+ * NOT CPU dependent\r
+ * -------------------------------\r
+ * \r
+ * For each application.\r
+ * \r
+ * ENUM [\r
+ * AUTO {\r
+ * }\r
+ * MANUAL {\r
+ * ADDRESS,\r
+ * PERMISSION,\r
+ * SIZE, \r
+ * }\r
+ * ] ALLOCATION;\r
+ */\r
+\r
+#define BIT(x) (1<<(x))\r
+#define PPC_BITS_32(x,offset) ((x)<<(31-(offset)))\r
+\r
+#define MM_PSIZE_4K PPC_BITS_32(1,20)\r
+#define MM_PSIZE_16K PPC_BITS_32(2,20)\r
+#define MM_PSIZE_64K PPC_BITS_32(3,20)\r
+#define MM_PSIZE_256K PPC_BITS_32(4,20)\r
+#define MM_PSIZE_1M PPC_BITS_32(5,20)\r
+#define MM_PSIZE_4M PPC_BITS_32(6,20)\r
+#define MM_PSIZE_16M PPC_BITS_32(7,20)\r
+#define MM_PSIZE_64M PPC_BITS_32(8,20)\r
+#define MM_PSIZE_256M PPC_BITS_32(9,20)\r
+\r
+\r
+/* Memory and cache attribs \r
+ * W - Write through, I-cache inhibit, \r
+ * M -Memory coherent, G-Guarded,\r
+ * E - Endian(big=0) \r
+ */\r
+#define MM_W BIT(0) \r
+#define MM_I BIT(1)\r
+#define MM_M BIT(2)\r
+#define MM_G BIT(3)\r
+#define MM_E BIT(4)\r
+\r
+/* memory size */\r
+#define MM_SIZE_8 BIT(16)\r
+#define MM_SIZE_16 BIT(17)\r
+#define MM_SIZE_32 BIT(18)\r
+\r
+/* permissions */\r
+#define MM_SX BIT(24)\r
+#define MM_SR BIT(25)\r
+#define MM_SW BIT(26)\r
+#define MM_UX BIT(27)\r
+#define MM_UR BIT(28)\r
+#define MM_UW BIT(29)\r
+\r
+#define MM_PERM_STEXT (MM_SR|MM_X)\r
+#define MM_PERM_SDATA (MM_SR|MM_SW)\r
+\r
+\r
+#endif /*MM_H_*/\r
--- /dev/null
+\r
+# prefered version\r
+CC_VERSION=4.1.2\r
+\r
+# No smalldata\r
+ppc_common-y += -msdata=none\r
+\r
+gcc_version := $(word 3,$(shell ${CROSS_COMPILE}gcc --version))\r
+gcc_split = $(subst ., ,$(gcc_version))\r
+\r
+# If version 4.3 or above then use -te500v1\r
+ifeq ($(word 1,$(gcc_split)),4)\r
+ifneq ($(filter $(word 2,$(gcc_split)),3 4 5 6 7 8 9),)\r
+ppc_common-$(CFG_SPE) += -te500v1 -mhard-float # -mfloat-gprs=single -mspe=yes -mhard-float\r
+endif\r
+endif\r
+ifeq ($(ppc_common-y),)\r
+ppc_common-$(CFG_SPE) += -mfloat-gprs=single -mspe=yes -mhard-float -mcpu=8540 -mno-eabi\r
+endif\r
+#\r
+ppc_common-y += -mmultiple\r
+ppc_common-$(CFG_MPC5516) += -msoft-float -mcpu=8540 -mno-eabi\r
+ppc_common-y += -mstrict-align\r
+ppc_common-y += -gdwarf-2\r
+ppc_common-y += -D_PPC\r
+\r
+cflags-$(CFG_MPC55XX) += -B$(prefix)/libexec/gcc:/opt\r
+#cflags-$(CFG_MPC55XX) += -mcpu=8540 \r
+#cflags-$(CFG_SPE) += -mabi=spe\r
+cflags-$(CFG_MPC55XX) += -mno-eabi\r
+\r
+cflags-$(CFG_MPC55XX) += $(ppc_common-y)\r
+\r
+lib-y += -lgcc -lc \r
+#LDFLAGS += -te500v1\r
+\r
+asflags-$(CFG_BOOKE) += -me500\r
+asflags-$(CFG_SPE) += -mspe\r
+asflags-y += -mregnames\r
+ \r
+ASFLAGS += $(asflags-y)\r
+\r
+\r
--- /dev/null
+\r
+/* For more info on sections check the E500 freescale doc: E500ABIUG.pdf\r
+ *\r
+ *\r
+ */\r
+OUTPUT_FORMAT("elf32-powerpc", "elf32-powerpc", "elf32-powerpc")\r
+OUTPUT_ARCH(powerpc)\r
+ENTRY(_start)\r
+\r
+\r
+MEMORY\r
+{\r
+ rcw(R) : ORIGIN = 0x00000000, LENGTH = 0x8\r
+ flash(R) : ORIGIN = 0x00000008, LENGTH = 0x100000\r
+ /* 5516S, 48K\r
+ * 5517S,5516G,5516E, 64K RAM\r
+ * 5517G,E , 80K RAM\r
+ */\r
+ ram(RW) : ORIGIN = 0x40000000, LENGTH = 0x100000\r
+}\r
+\r
+SECTIONS\r
+{\r
+ .rcw : { *(.rcw) }> rcw\r
+\r
+ .text :\r
+ {\r
+ *(.text .text.* .init .fini* .eini* .gnu.linkonce* .gnu.warning)\r
+ } > flash\r
+\r
+ .fls_rom : {\r
+ __FLS_ERASE_ROM__ = .;\r
+ *(.fls_erase);\r
+ __FLS_WRITE_ROM__ = .;\r
+ *(.fls_write);\r
+ __FLS_END_ROM__ = .;\r
+ } > flash\r
+\r
+/* mpc5554, align 64K. mpc5516, 4k */\r
+ .exception_tbl ALIGN(0x10000) :\r
+ {\r
+ *(.isrvectbl)\r
+ } > flash\r
+\r
+ /* Read-only data section. */\r
+ .rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) } > flash\r
+\r
+ /* initialized read-only small data section. */\r
+ .sdata2 : {\r
+ _SDA2_BASE_ = .; /* r2 */\r
+ *(.sdata2 .sdata2.* .gnu.linkonce.s2.*);\r
+ *(PPC.EMB.sdata2 .PPC.EMB.sbss2)\r
+ } > flash\r
+\r
+\r
+ /* uninitialized read-only small data section. */\r
+ .sbss2 : {\r
+ *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*);\r
+ __TEXT_END = .;\r
+ . = . + ALIGN(8);\r
+ __DATA_ROM = .;\r
+ } > flash\r
+\r
+ .data : AT(ALIGN(LOADADDR(.sbss2)+SIZEOF(.sbss2),4)) {\r
+ __DATA_RAM = .; *(.data .data.* .gnu.linkonce.d.* .gnu.linkonce.r.* .eh_frame)\r
+ } > ram\r
+\r
+ .sdata : AT(ALIGN(LOADADDR(.data)+SIZEOF(.data),4)) {\r
+ __SDATA_START__ = .;\r
+ _SDA_BASE_ = .; /* r13 */\r
+ *(.sdata .sdata.* .gnu.linkonce.s.*)\r
+ *(PPC.EMB.sdata2 .PPC.EMB.sbss2)\r
+ . = . + ALIGN(8);\r
+ __DATA_END = .;\r
+ } > ram\r
+\r
+ .sbss :\r
+ {\r
+ __SBSS_START__ = .;\r
+ *(.sbss .sbss.* .scommon .gnu.linkonce.sb.* .t32_outport);\r
+ __SBSS_END__ = .;\r
+ } > ram\r
+\r
+ .got2 ALIGN(0x10): {. = . + ALIGN(16);*(.got2); . = . + ALIGN(8); } > ram\r
+ .fixup : { . = . + ALIGN(16);*(.fixup); . = . + ALIGN(8); } > ram\r
+ .t32_outport ALIGN(0x10): { *(.t32_outport); } > ram\r
+ .got : AT(ALIGN(LOADADDR(.sdata)+SIZEOF(.sdata),4)) { *(.got.plt) *(.got) } > ram\r
+ .bss : { *(.bss .bss.* COMMON .gnu.linkonce.b.*);__BSS_END = .; } > ram\r
+ .init_stack ALIGN(16) (NOLOAD) : { __SP_END = .;. = . + 3000; __SP_INIT = .; } > ram\r
+ /* Fls RAM section */\r
+ .fls_ram ALIGN(16) (NOLOAD) : {\r
+ __FLS_ERASE_RAM__ = .;\r
+ . = . + SIZEOF(.fls_rom);\r
+ } > ram\r
+\r
+ .ctors :\r
+ {\r
+ KEEP (*(SORT(.ctors.*)))\r
+ }\r
+\r
+ .uninit ALIGN(0x10): { *(.winidea_port .ramlog) ; } > ram\r
+\r
+ __FLS_SIZE__ = SIZEOF(.fls_rom);\r
+ __FLS_WRITE_RAM__ = __FLS_ERASE_RAM__ + (__FLS_WRITE_ROM__ - __FLS_ERASE_ROM__);\r
+\r
+ /* Stabs debugging sections. */\r
+ .stab 0 : { *(.stab) }\r
+ .stabstr 0 : { *(.stabstr) }\r
+ .stab.excl 0 : { *(.stab.excl) }\r
+ .stab.exclstr 0 : { *(.stab.exclstr) }\r
+ .stab.index 0 : { *(.stab.index) }\r
+ .stab.indexstr 0 : { *(.stab.indexstr) }\r
+ .comment 0 : { *(.comment) }\r
+ /* DWARF debug sections.\r
+ Symbols in the DWARF debugging sections are relative to the beginning\r
+ of the section so we begin them at 0. */\r
+ /* DWARF 1 */\r
+ .debug 0 : { *(.debug) }\r
+ .line 0 : { *(.line) }\r
+ /* GNU DWARF 1 extensions */\r
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }\r
+ .debug_sfnames 0 : { *(.debug_sfnames) }\r
+ /* DWARF 1.1 and DWARF 2 */\r
+ .debug_aranges 0 : { *(.debug_aranges) }\r
+ .debug_pubnames 0 : { *(.debug_pubnames) }\r
+ /* DWARF 2 */\r
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }\r
+ .debug_abbrev 0 : { *(.debug_abbrev) }\r
+ .debug_line 0 : { *(.debug_line) }\r
+ .debug_frame 0 : { *(.debug_frame) }\r
+ .debug_str 0 : { *(.debug_str) }\r
+ .debug_loc 0 : { *(.debug_loc) }\r
+ .debug_macinfo 0 : { *(.debug_macinfo) }\r
+ /* SGI/MIPS DWARF 2 extensions */\r
+ .debug_weaknames 0 : { *(.debug_weaknames) }\r
+ .debug_funcnames 0 : { *(.debug_funcnames) }\r
+ .debug_typenames 0 : { *(.debug_typenames) }\r
+ .debug_varnames 0 : { *(.debug_varnames) }\r
+}\r
+\r
+__TEXT_START = ADDR(.text);\r
+__RAM_START = ADDR(.sdata);\r
+\r
+__DATA_RAM = ADDR(.data);\r
+/*__DATA_END = ADDR(.sdata)+SIZEOF(.sdata);*/\r
+/*__BSS_START = ADDR(.sbss);*/\r
+__BSS_START = ADDR(.sbss);\r
+\r
+/* _SDA_BASE_ and _SDA2_BASE_ is defined in e500 ABI\r
+ * Some of the symbols below is used by eabi() that does interesting.\r
+ * Can't get rid of it even with no-eabi option\r
+ */\r
+\r
+/* __SBSS_END__ = ADDR(.sbss) + SIZEOF(.sbss); */\r
+ __SDATA2_START__ = ADDR(.sdata2);\r
+ __SBSS2_END__ = ADDR(.sbss2) + SIZEOF(.sbss2);\r
+__GOT_START__ = ADDR(.got);\r
+__GOT_END__ = ADDR(.got) + SIZEOF(.got);\r
+__GOT2_START__ = ADDR(.got2);\r
+__GOT2_END__ = ADDR(.got2) + SIZEOF(.got2);\r
+__FIXUP_START__ = ADDR(.fixup);\r
+__FIXUP_END__ = ADDR(.fixup) + SIZEOF(.fixup);\r
+\r
+__EXCEPT_START__ = 0x0;\r
+__EXCEPT_END__ = 0x0;\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+BDIR=system/kernel,system/kernel/testsystem
+CROSS_COMPILE=/opt/arm-elf/bin/arm-elf-
--- /dev/null
+export BOARDDIR=mpc5554sim
+export MCU=MPC5554
+export ARCH=mpc55xx
+export ARCH_FAM=ppc
--- /dev/null
+\r
+obj-$(CFG_PPC) += crt0.o\r
+vpath-$(CFG_ARM_CM3) += $(ARCH_PATH-y)kernel \r
+obj-$(CFG_ARM_CM3) += startup_stm32f10x_hd.o\r
+obj-$(CFG_ARM_CM3) += system_stm32f10x.o\r
+obj-$(CFG_ARM_CM3) += core_cm3.o\r
+\r
+#Ecu\r
+#obj-y += EcuM_$(BOARDDIR).o\r
+obj-y += EcuM.o\r
+obj-y += EcuM_Cfg.o\r
+obj-y += EcuM_Callout_template.o\r
+inc-y += $(ROOTDIR)/system/EcuM\r
+vpath-y += $(ROOTDIR)/system/EcuM\r
+\r
+# Gpt\r
+obj-$(USE_GPT) += Gpt.o\r
+obj-$(USE_GPT) += Gpt_Cfg.o\r
+\r
+# Dma\r
+obj-$(USE_DMA) += Dma.o\r
+obj-$(USE_DMA) += Dma_Cfg.o\r
+inc-$(USE_DMA) += $(ROOTDIR)/$(ARCH_PATH-y)/drivers\r
+\r
+# Mcu\r
+obj-$(USE_MCU) += Mcu.o\r
+obj-$(USE_MCU) += Mcu_Cfg.o\r
+obj-$(CFG_MPC55XX)-$(USE_MCU) += Mcu_Exceptions.o\r
+#obj-$(USE_MCU) += Mcu_IntcVectors.o\r
+\r
+# Flash\r
+obj-$(USE_FLS) += Fls.o\r
+obj-$(USE_FLS) += Fls_Cfg.o\r
+obj-$(USE_FLS) += Fls_H7F.o\r
+\r
+# Bring in the freescale driver source \r
+inc-$(CFG_MPC55XX) += $(ROOTDIR)/$(ARCH_PATH-y)/delivery/mpc5500_h7f/include\r
+\r
+# Can\r
+obj-$(USE_CAN) += Can.o\r
+obj-$(USE_CAN) += Can_Lcfg.o\r
+obj-$(USE_CANIF) += CanIf.o\r
+obj-$(USE_CANIF) += CanIf_Cfg.o\r
+\r
+obj-$(USE_DIO) += Dio.o\r
+obj-$(USE_DIO) += Dio_Lcfg.o\r
+\r
+obj-$(USE_PORT) += Port.o\r
+obj-$(USE_PORT) += Port_Cfg.o\r
+\r
+obj-$(USE_ADC) += Adc.o\r
+obj-$(USE_ADC) += Adc_Cfg.o\r
+\r
+\r
+# Spi\r
+obj-$(USE_SPI) += Spi.o\r
+obj-$(USE_SPI) += Spi_Lcfg.o\r
+\r
+#Eep\r
+obj-$(USE_EEP) += Eep.o\r
+obj-$(USE_EEP) += Eep_Lcfg.o\r
+obj-$(USE_EEP) += Eeprom_Lcfg.o\r
+\r
+#Fls ext\r
+obj-$(USE_FLS_SST25XX) += Fls_SST25xx.o\r
+obj-$(USE_FLS_SST25XX) += Fls_SST25xx_Cfg.o\r
+vpath-y += $(ROOTDIR)/peripherals\r
+\r
+#Wdg\r
+obj-$(USE_WDG) += Wdg.o\r
+\r
+#WdgM\r
+obj-$(USE_WDGM) += WdgM.o\r
+obj-$(USE_WDGM) += WdgM_Cfg.o\r
+\r
+#Pwm\r
+obj-$(USE_PWM) += Pwm.o\r
+obj-$(USE_PWM) += Pwm_Cfg.o\r
+\r
+# Misc\r
+obj-y += Det.o\r
+\r
+# Lin\r
+obj-$(USE_LIN) += Lin_PBcfg.o\r
+obj-$(USE_LIN) += Lin_Lcfg.o\r
+obj-$(USE_LIN) += LinIf_Lcfg.o\r
+obj-$(USE_LIN) += LinIf_PBcfg.o\r
+obj-$(USE_LIN) += LinSM_Lcfg.o\r
+obj-$(USE_LIN) += LinSM_PBcfg.o\r
+obj-$(USE_LIN) += LinSM_Cfg.o\r
+obj-$(USE_LIN) += Lin.o\r
+obj-$(USE_LIN) += LinIf.o\r
+obj-$(USE_LIN) += LinSM.o\r
+vpath-y += $(ROOTDIR)/drivers/Lin/\r
+vpath-y += $(ROOTDIR)/communication/Lin\r
+inc-y += $(ROOTDIR)/communication/ComM\r
+\r
+# ComM\r
+obj-$(USE_COMM) += ComM.o\r
+inc-$(USE_COMM) += $(ROOTDIR)/communication/ComM\r
+vpath-$(USE_COMM) += $(ROOTDIR)/communication/ComM\r
+vpath-y += $(ROOTDIR)/communication/ComM\r
+inc-$(USE_COMM) += $(ROOTDIR)/communication/ComM\r
+\r
+\r
+# Com\r
+obj-$(USE_COM) += Com_PbCfg.o\r
+obj-$(USE_COM) += Com_Com.o\r
+obj-$(USE_COM) += Com_Sched.o\r
+obj-$(USE_COM) += Com.o\r
+obj-$(USE_COM) += Com_RunTest.o\r
+obj-$(USE_COM) += Com_misc.o\r
+#obj-$(USE_COM) += Com_TestData.o\r
+inc-$(USE_PDUR) += $(ROOTDIR)/communication/Com\r
+inc-$(USE_COM) += $(ROOTDIR)/communication/Com\r
+vpath-$(USE_COM) += $(ROOTDIR)/communication/Com\r
+\r
+# PduR\r
+obj-$(USE_PDUR) += PduR_Com.o\r
+obj-$(USE_PDUR) += PduR_If.o\r
+obj-$(USE_PDUR) += PduR_LinIf.o\r
+obj-$(USE_PDUR) += PduR_PbCfg.o\r
+obj-$(USE_PDUR) += PduR_CanIf.o\r
+obj-$(USE_PDUR) += PduR.o\r
+inc-$(USE_PDUR) += $(ROOTDIR)/communication/PduR\r
+inc-$(USE_COM) += $(ROOTDIR)/communication/PduR\r
+vpath-$(USE_PDUR) += $(ROOTDIR)/communication/PduR\r
+\r
+#tests\r
+#obj-y += RunTests.o\r
+#obj-$(USE_CAN) += can_test.o\r
+#obj-$(USE_DIO) += dio_test.o\r
+#obj-$(USE_PORT) += port_test.o\r
+#obj-$(USE_CANIF) += canif_test.o\r
+#obj-$(USE_FLS) += fls_test.o\r
+#obj-y += mahi_test.o\r
+#obj-$(USE_GPT) += gpt_test.o\r
+#obj-$(USE_SPI) += spi_test.o\r
+#obj-$(USE_EEP) += eep_test.o\r
+#obj-y += det_test.o\r
+#obj-$(USE_MCU) += mcu_test.o\r
+#obj-$(USE_FLS_SST25XX) += xfls_test.o\r
+#obj-y += lin_test.o\r
+#obj-$(USE_PDUR) += pdur_test.o\r
+#obj-$(USE_COM) += com_test.o\r
+\r
+#inc-$(USE_TESTS) += $(ROOTDIR)/embunit/embUnit\r
+#inc-$(USE_TESTS) += $(ROOTDIR)/embunit/textui\r
+#inc-$(USE_TESTS) += $(ROOTDIR)/embunit\r
+\r
+#libitem-$(USE_TESTS) += $(ROOTDIR)/embunit/embUnit/obj_$(ARCH)/libembunit.a\r
+#libitem-$(USE_TESTS) += $(ROOTDIR)/embunit/textui/obj_$(ARCH)/libtextui.a\r
+\r
+\r
+\r
+# Common\r
+obj-y += xtoa.o\r
+obj-y += ramlog.o\r
+obj-y += printf.o\r
+VPATH += $(ROOTDIR)/common\r
+\r
+obj-y += newlib_port.o\r
+obj-y += $(obj-y-y)\r
+\r
+#def-y += CC_KERNEL\r
+\r
+vpath-y += $(ROOTDIR)/$(ARCH_PATH-y)/kernel\r
+vpath-y += $(ROOTDIR)/$(ARCH_PATH-y)/drivers\r
+vpath-y += $(ROOTDIR)/boards/$(BOARDDIR)\r
+vpath-y += $(ROOTDIR)/arch/$(ARCH_FAM)\r
+vpath-y += $(ROOTDIR)/boards/$(BOARDDIR)/config\r
+vpath-y += $(ROOTDIR)/diagnostic/Dem\r
+vpath-y += $(ROOTDIR)/diagnostic/Det\r
+\r
+\r
+VPATH += $(vpath-y)\r
+\r
+#$(error $(VPATH))\r
+\r
+# libs needed by us\r
+#build-lib-y += $(ROOTDIR)/libs/libboard_$(BOARDDIR).a\r
+\r
+# include files need by us\r
+inc-y += $(ROOTDIR)/include\r
+inc-y += $(ROOTDIR)/kernel/test\r
+inc-y += $(ROOTDIR)/kernel/include\r
+inc-y += $(ROOTDIR)/$(ARCH_PATH-y)/kernel\r
+inc-y += $(ROOTDIR)/$(ARCH_PATH-y)/drivers\r
+inc-y += $(ROOTDIR)/boards/$(BOARDDIR)/config\r
+inc-y += $(ROOTDIR)/drivers/Dem\r
+inc-y += $(ROOTDIR)/drivers/test\r
+\r
+\r
+#\r
+# And last the generic board\r
+#\r
+inc-y += $(ROOTDIR)/boards/generic\r
+\r
--- /dev/null
+
+# ARCH defines
+ARCH=arm_cm3
+ARCH_FAM=arm
+ARCH_MCU=arm_cm3
+
+# CFG (y/n) macros
+CFG=ARM ARM_CM3 BRD_ET_STM32_STAMP
+
+
+# What buildable modules does this board have,
+# default or private
+MOD_AVAIL=KERNEL MCU T32_TERM
+
+# Needed by us
+MOD_USE=KERNEL MCU
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+#ifndef MCU_CFG_C_\r
+#define MCU_CFG_C_\r
+\r
+#include "Mcu_Cfg.h"\r
+\r
+Mcu_RamSectorSettingConfigType Mcu_RamSectorSettingConfigData[] = {\r
+ {\r
+ // This parameter shall represent the Data pre-setting to be initialized\r
+ .McuRamDefaultValue = 0,\r
+\r
+ // This parameter shall represent the MCU RAM section base address\r
+ .McuRamSectionBaseAddress = 0,\r
+\r
+ // This parameter shall represent the MCU RAM Section size\r
+ .McuRamSectionSize = 0xFF,\r
+ }\r
+};\r
+\r
+Mcu_ClockSettingConfigType Mcu_ClockSettingConfigData[] =\r
+{\r
+ {\r
+ .McuClockReferencePoint = 8000000UL,\r
+ .PllEprediv = 1,\r
+ .PllEmfd = 104,\r
+ .PllErfd = 5,\r
+ },\r
+ {\r
+ .McuClockReferencePoint = 16000000UL,\r
+ .PllEprediv = 3,\r
+ .PllEmfd = 83,\r
+ .PllErfd = 5,\r
+ }\r
+};\r
+\r
+\r
+ const Mcu_ConfigType McuConfigData[] = {\r
+ {\r
+ // Enables/Disables clock failure notification. In case this feature is not supported\r
+ // by HW the setting should be disabled.\r
+ .McuClockSrcFailureNotification = 0,\r
+\r
+ // This parameter shall represent the number of Modes available for the\r
+ // MCU. calculationFormula = Number of configured McuModeSettingConf\r
+ .McuNumberOfMcuModes = 1, /* NOT USED */\r
+\r
+ // This parameter shall represent the number of RAM sectors available for\r
+ // the MCU. calculationFormula = Number of configured McuRamSectorSet-\r
+ // tingConf\r
+ .McuRamSectors = 1,\r
+\r
+ // This parameter shall represent the number of clock setting available for\r
+ // the MCU.\r
+ .McuClockSettings = MCU_NBR_OF_CLOCKS,\r
+\r
+ // Default clock frequency used\r
+ .McuDefaultClockSettings = MCU_CLOCKTYPE_EXT_REF_80MHZ,\r
+\r
+ // This parameter relates to the MCU specific reset configuration. This ap-\r
+ // plies to the function Mcu_PerformReset, which performs a microcontroller\r
+ // reset using the hardware feature of the microcontroller.\r
+ .McuResetSetting = 0, /* NOT USED */\r
+\r
+ // This container contains the configuration (parameters) for the\r
+ // Clock settings of the MCU. Please see MCU031 for more in-\r
+ // formation on the MCU clock settings.\r
+ .McuClockSettingConfig = &Mcu_ClockSettingConfigData[0],\r
+\r
+ // This container contains the configuration (parameters) for the\r
+ // Mode setting of the MCU. Please see MCU035 for more infor-\r
+ // mation on the MCU mode settings.\r
+ .McuModeSettingConfig = 0,\r
+\r
+ // This container contains the configuration (parameters) for the\r
+ // RAM Sector setting. Please see MCU030 for more information\r
+ // on RAM sec-tor settings.\r
+ .McuRamSectorSettingConfig = &Mcu_RamSectorSettingConfigData[0],\r
+ },\r
+};\r
+\r
+#endif /*MCU_CFG_C_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef MCU_CFG_H_\r
+#define MCU_CFG_H_\r
+\r
+#define MCU_DEV_ERROR_DETECT STD_ON\r
+// Preprocessor switch to enable / disable the use of the function\r
+// Mcu_PerformReset()\r
+#define MCU_PERFORM_RESET_API STD_ON\r
+\r
+#define MCU_VERSION_INFO_API STD_ON\r
+\r
+#include "Std_Types.h"\r
+\r
+/* FMPLL modes( atleast in 5553/5554 ) */\r
+\r
+typedef enum {\r
+ MCU_FMPLL_BYPASS = 0,\r
+ MCU_FMPLL_EXTERNAL_REF,\r
+ MCU_FMPLL_EXTERNAL_REF_NO_FM,\r
+ MCU_FMPLL_DUAL_CONTROLLER_MODE,\r
+} Mcu_FMPLLmode_t;\r
+\r
+typedef enum {\r
+ MCU_CLOCKTYPE_EXT_REF_80MHZ = 0,\r
+ MCU_CLOCKTYPE_EXT_REF_66MHZ,\r
+ MCU_NBR_OF_CLOCKS,\r
+ //MCU_CLOCKTYPE_EXTERNAL_REF,\r
+ //MCU_CLOCKTYPE_EXTERNAL_REF_NO_FM,\r
+ //MCU_CLOCKTYPE_DUAL_CONTROLLER_MODE,\r
+} Mcu_ClockType;\r
+\r
+typedef struct {\r
+ // This container defines a reference point in the Mcu Clock tree\r
+ // It defines the frequency which then can be used by other modules\r
+ // as an input value. Lower multiplicity is 1, as even in the\r
+ // simplest case (only one frequency is used), there is one\r
+ // frequency to be defined.\r
+ uint32 McuClockReferencePoint;\r
+\r
+ // Phase locked loop configuration parameters for MPC551x.\r
+ uint8 PllEprediv;\r
+ uint8 PllEmfd;\r
+ uint8 PllErfd;\r
+} Mcu_ClockSettingConfigType;\r
+\r
+typedef struct {\r
+ // The parameter represents the MCU Mode settings\r
+ uint32 McuMode;\r
+} Mcu_ModeSettingConfigType;\r
+\r
+typedef struct {\r
+ // This parameter shall represent the Data pre-setting to be initialized\r
+ uint32 McuRamDefaultValue;\r
+\r
+ // This parameter shall represent the MCU RAM section base address\r
+ uint32 McuRamSectionBaseAddress;\r
+\r
+ // This parameter shall represent the MCU RAM Section size\r
+ uint32 McuRamSectionSize;\r
+\r
+} Mcu_RamSectorSettingConfigType;\r
+\r
+\r
+// This container defines a reference point in the Mcu Clock tree. It defines\r
+// the frequency which then can be used by other modules as an input value.\r
+// Lower multiplicity is 1, as even in the simplest case (only one frequency is\r
+// used), there is one frequency to be defined.\r
+typedef struct {\r
+\r
+ // This is the frequency for the specific instance of the McuClockReference-\r
+ // Point container. It shall be givn in Hz.\r
+ uint32 McuClockReferencePointFrequency;\r
+\r
+} Mcu_ClockReferencePointType;\r
+\r
+typedef struct {\r
+ // Enables/Disables clock failure notification. In case this feature is not supported\r
+ // by HW the setting should be disabled.\r
+ uint8 McuClockSrcFailureNotification;\r
+\r
+ // This parameter shall represent the number of Modes available for the\r
+ // MCU. calculationFormula = Number of configured McuModeSettingConf\r
+ uint8 McuNumberOfMcuModes;\r
+\r
+ // This parameter shall represent the number of RAM sectors available for\r
+ // the MCU. calculationFormula = Number of configured McuRamSectorSet-\r
+ // tingConf\r
+ uint8 McuRamSectors;\r
+\r
+ // This parameter shall represent the number of clock setting available for\r
+ // the MCU.\r
+ uint8 McuClockSettings;\r
+\r
+ // This parameter defines the default clock settings that should be used\r
+ // It is an index into the McuClockSettingsConfig\r
+ Mcu_ClockType McuDefaultClockSettings;\r
+\r
+ // This parameter relates to the MCU specific reset configuration. This ap-\r
+ // plies to the function Mcu_PerformReset, which performs a microcontroller\r
+ // reset using the hardware feature of the microcontroller.\r
+ uint32 McuResetSetting;\r
+\r
+ // This container contains the configuration (parameters) for the\r
+ // Clock settings of the MCU. Please see MCU031 for more in-\r
+ // formation on the MCU clock settings.\r
+ Mcu_ClockSettingConfigType * McuClockSettingConfig;\r
+\r
+ // This container contains the configuration (parameters) for the\r
+ // Mode setting of the MCU. Please see MCU035 for more information\r
+ // on the MCU mode settings.\r
+ Mcu_ModeSettingConfigType *McuModeSettingConfig;\r
+\r
+ // This container contains the configuration (parameters) for the\r
+ // RAM Sector setting. Please see MCU030 for more information\r
+ // on RAM sec-tor settings.\r
+ Mcu_RamSectorSettingConfigType *McuRamSectorSettingConfig;\r
+\r
+} Mcu_ConfigType;\r
+\r
+extern const Mcu_ConfigType McuConfigData[];\r
+\r
+#define MCU_DEFAULT_CONFIG McuConfigData[0]\r
+\r
+#endif /*MCU_CFG_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*\r
+ * Development Error Tracer driver\r
+ *\r
+ * Specification: Autosar v2.0.1, Final\r
+ *\r
+ */\r
+#ifndef _DET_CFG_H_\r
+#define _DET_CFG_H_\r
+\r
+#define DET_ENABLE_CALLBACKS STD_ON // Enable to use callback on errors\r
+#define DET_USE_RAMLOG STD_ON // Enable to log DET errors to ramlog\r
+#define DET_WRAP_RAMLOG STD_ON // The ramlog wraps around when reaching the end\r
+#define DET_USE_STDERR STD_OFF // Enable to get DET errors on stderr\r
+\r
+#define DET_DEINIT_API STD_ON // Enable/Disable the Det_DeInit function\r
+\r
+#define DET_RAMLOG_SIZE (32) // Number of entries in ramlog\r
+#define DET_NUMBER_OF_CALLBACKS (5) // Number of callbacks\r
+\r
+#endif /*_DET_CFG_H_*/\r
--- /dev/null
+\r
+\r
+Test board. \r
+=======================================================\r
+\r
+The regression test board comes in different variants.\r
+\r
+\r
+This file supports:\r
+- EVB5516\r
+ \r
--- /dev/null
+
+# ARCH defines
+ARCH=mpc55xx
+ARCH_FAM=ppc
+ARCH_MCU=mpc5516
+
+# CFG (y/n) macros
+CFG=PPC BOOKE E200Z1 MPC55XX MPC5516 BRD_MPC5516IT
+
+# What buildable modules does this board have,
+# default or private
+MOD_AVAIL+=KERNEL MCU GPT LIN CAN CANIF PORT DIO WDG WDGM T32_TERM PWM WINIDEA_TERM COM ADC DMA
+
+# Needed by us
+MOD_USE=KERNEL MCU
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include "Adc.h"\r
+#include "Dma.h"\r
+#include "mpc5516.h"\r
+\r
+const struct tcd_t AdcGroupDMACommandConfig [ADC_NBR_OF_GROUPS];\r
+const struct tcd_t AdcGroupDMAResultConfig [ADC_NBR_OF_GROUPS];\r
+\r
+Adc_GroupStatus AdcGroupStatus[ADC_NBR_OF_GROUPS];\r
+\r
+/* Configuration goes here. */\r
+void Adc_Group0Notification (void)\r
+{\r
+}\r
+\r
+void Adc_Group1Notification (void)\r
+{\r
+}\r
+\r
+const Adc_HWConfigurationType AdcHWUnitConfiguration =\r
+{\r
+ .hwUnitId = 0,\r
+ .adcPrescale = ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_8,\r
+ .clockSource = ADC_SYSTEM_CLOCK,\r
+};\r
+\r
+const Adc_ChannelConfigurationType AdcChannelConfiguration [ADC_NBR_OF_CHANNELS] =\r
+{\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_DISABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+};\r
+\r
+const Adc_ChannelType Adc_Group0ChannelList[ADC_NBR_OF_GROUP0_CHANNELS] =\r
+{\r
+ ADC_CH1, ADC_CH2, ADC_CH3, ADC_CH4, ADC_CH5, ADC_CH6, ADC_CH7\r
+};\r
+\r
+const Adc_ChannelType Adc_Group1ChannelList[ADC_NBR_OF_GROUP1_CHANNELS] =\r
+{\r
+ ADC_CH0, ADC_CH2, ADC_CH3, ADC_CH4\r
+};\r
+\r
+const Adc_ChannelType Adc_Group2ChannelList[ADC_NBR_OF_GROUP2_CHANNELS] =\r
+{\r
+ ADC_CH0, ADC_CH1, ADC_CH2\r
+};\r
+\r
+const Adc_ChannelType Adc_Group3ChannelList[ADC_NBR_OF_GROUP3_CHANNELS] =\r
+{\r
+ ADC_CH0, ADC_CH1, ADC_CH2\r
+};\r
+\r
+/* Ram buffers for command and result queues. These are located here in the\r
+ configuration to be able to reconfigure system without recompiling the\r
+ drivers. */\r
+Adc_ValueGroupType Adc_Group0Buffer [sizeof(Adc_Group0ChannelList)/sizeof(Adc_Group0ChannelList[0])];\r
+Adc_CommandType Adc_Group0Commands [sizeof(Adc_Group0ChannelList)/sizeof(Adc_Group0ChannelList[0])];\r
+\r
+Adc_ValueGroupType Adc_Group1Buffer [sizeof(Adc_Group1ChannelList)/sizeof(Adc_Group1ChannelList[0])];\r
+Adc_CommandType Adc_Group1Commands [sizeof(Adc_Group1ChannelList)/sizeof(Adc_Group1ChannelList[0])];\r
+\r
+Adc_ValueGroupType Adc_Group2Buffer [sizeof(Adc_Group2ChannelList)/sizeof(Adc_Group2ChannelList[0])];\r
+Adc_CommandType Adc_Group2Commands [sizeof(Adc_Group2ChannelList)/sizeof(Adc_Group2ChannelList[0])];\r
+\r
+Adc_ValueGroupType Adc_Group3Buffer [sizeof(Adc_Group3ChannelList)/sizeof(Adc_Group3ChannelList[0])];\r
+Adc_CommandType Adc_Group3Commands [sizeof(Adc_Group3ChannelList)/sizeof(Adc_Group3ChannelList[0])];\r
+\r
+\r
+const Adc_GroupDefType AdcGroupConfiguration [] =\r
+{\r
+ { .accessMode = ADC_ACCESS_MODE_SINGLE, .conversionMode = ADC_CONV_MODE_ONESHOT,\r
+ .triggerSrc = ADC_TRIGG_SRC_SW, .hwTriggerSignal = ADC_NO_HW_TRIG,\r
+ .hwTriggerTimer = ADC_NO_TIMER,\r
+ .groupCallback = Adc_Group0Notification,\r
+ .streamBufferMode = ADC_NO_STREAMING, .streamNumSamples = 0,\r
+ .channelList = Adc_Group0ChannelList,\r
+ .resultBuffer = Adc_Group0Buffer,\r
+ .commandBuffer = Adc_Group0Commands,\r
+ .numberOfChannels = sizeof(Adc_Group0Commands)/sizeof(Adc_Group0Commands[0]),\r
+ .status = &AdcGroupStatus[ADC_GROUP0],\r
+ .dmaCommandChannel = DMA_ADC_GROUP0_COMMAND_CHANNEL,\r
+ .dmaResultChannel = DMA_ADC_GROUP0_RESULT_CHANNEL,\r
+ .groupDMACommands = &AdcGroupDMACommandConfig[ADC_GROUP0],\r
+ .groupDMAResults = &AdcGroupDMAResultConfig[ADC_GROUP0]},\r
+\r
+ { .accessMode = ADC_ACCESS_MODE_SINGLE, .conversionMode = ADC_CONV_MODE_CONTINOUS,\r
+ .triggerSrc = ADC_TRIGG_SRC_SW, .hwTriggerSignal = ADC_NO_HW_TRIG,\r
+ .hwTriggerTimer = ADC_NO_TIMER,\r
+ .groupCallback = Adc_Group1Notification,\r
+ .streamBufferMode = ADC_NO_STREAMING, .streamNumSamples = 0,\r
+ .channelList = Adc_Group1ChannelList,\r
+ .resultBuffer = Adc_Group1Buffer,\r
+ .commandBuffer = Adc_Group1Commands,\r
+ .numberOfChannels = sizeof(Adc_Group1Commands)/sizeof(Adc_Group1Commands[0]),\r
+ .status = &AdcGroupStatus[ADC_GROUP1],\r
+ .dmaCommandChannel = DMA_ADC_GROUP1_COMMAND_CHANNEL,\r
+ .dmaResultChannel = DMA_ADC_GROUP1_RESULT_CHANNEL,\r
+ .groupDMACommands = &AdcGroupDMACommandConfig[ADC_GROUP1],\r
+ .groupDMAResults = &AdcGroupDMAResultConfig[ADC_GROUP1]}\r
+};\r
+\r
+\r
+/******************************************************************/\r
+/* */\r
+/* End of user configuration area. DO NOT modify the code below!! */\r
+/* */\r
+/******************************************************************/\r
+const Adc_ConfigType AdcConfig [] =\r
+{\r
+ {\r
+ .hwConfigPtr = &AdcHWUnitConfiguration,\r
+ .channelConfigPtr = AdcChannelConfiguration,\r
+ .nbrOfChannels = sizeof(AdcChannelConfiguration)/sizeof(AdcChannelConfiguration[0]),\r
+ .groupConfigPtr = AdcGroupConfiguration,\r
+ .nbrOfGroups = sizeof(AdcGroupConfiguration)/sizeof(AdcGroupConfiguration[0])}\r
+};\r
+\r
+/* DMA configuration. */\r
+const struct tcd_t AdcGroupDMACommandConfig [ADC_NBR_OF_GROUPS] =\r
+{\r
+ {\r
+ .SADDR = (uint32_t)Adc_Group0Commands,\r
+ .SMOD = 0,\r
+ .SSIZE = DMA_TRANSFER_SIZE_32BITS,\r
+ .DMOD = 0,\r
+ .DSIZE = DMA_TRANSFER_SIZE_32BITS,\r
+ .SOFF = sizeof(Adc_CommandType),\r
+ .NBYTES = sizeof(Adc_CommandType),\r
+ .SLAST = -sizeof(Adc_Group0Commands),\r
+ .DADDR = (vint32_t)&EQADC.CFPR[ADC_GROUP0].R,\r
+ .CITERE_LINK = 0,\r
+ .CITER = sizeof(Adc_Group0Commands)/sizeof(Adc_Group0Commands[0]),\r
+ .DOFF = 0,\r
+ .DLAST_SGA = 0,\r
+ .BITERE_LINK = 0,\r
+ .BITER = sizeof(Adc_Group0Commands)/sizeof(Adc_Group0Commands[0]),\r
+ .BWC = 0,\r
+ .MAJORLINKCH = 0,\r
+ .DONE = 0,\r
+ .ACTIVE = 0,\r
+ .MAJORE_LINK = 0,\r
+ .E_SG = 0,\r
+ .D_REQ = 0,\r
+ .INT_HALF = 0,\r
+ .INT_MAJ = 0,\r
+ .START = 0\r
+ },\r
+ {\r
+ .SADDR = (uint32_t)Adc_Group1Commands,\r
+ .SMOD = 0,\r
+ .SSIZE = DMA_TRANSFER_SIZE_32BITS,\r
+ .DMOD = 0,\r
+ .DSIZE = DMA_TRANSFER_SIZE_32BITS,\r
+ .SOFF = sizeof(Adc_CommandType),\r
+ .NBYTES = sizeof(Adc_CommandType),\r
+ .SLAST = -sizeof(Adc_Group1Commands),\r
+ .DADDR = (vint32_t)&EQADC.CFPR[ADC_GROUP1].R,\r
+ .CITERE_LINK = 0,\r
+ .CITER = sizeof(Adc_Group1Commands)/sizeof(Adc_Group1Commands[0]),\r
+ .DOFF = 0,\r
+ .DLAST_SGA = 0,\r
+ .BITERE_LINK = 0,\r
+ .BITER = sizeof(Adc_Group1Commands)/sizeof(Adc_Group1Commands[0]),\r
+ .BWC = 0,\r
+ .MAJORLINKCH = 0,\r
+ .DONE = 0,\r
+ .ACTIVE = 0,\r
+ .MAJORE_LINK = 0,\r
+ .E_SG = 0,\r
+ .D_REQ = 0,\r
+ .INT_HALF = 0,\r
+ .INT_MAJ = 0,\r
+ .START = 0\r
+ }\r
+};\r
+\r
+const struct tcd_t AdcGroupDMAResultConfig [ADC_NBR_OF_GROUPS]=\r
+{\r
+ {\r
+ .SADDR = (vint32_t)&EQADC.RFPR[ADC_GROUP0].R + 2,\r
+ .SMOD = 0,\r
+ .SSIZE = DMA_TRANSFER_SIZE_16BITS,\r
+ .DMOD = 0,\r
+ .DSIZE = DMA_TRANSFER_SIZE_16BITS,\r
+ .SOFF = 0,\r
+ .NBYTES = sizeof(Adc_ValueGroupType),\r
+ .SLAST = 0,\r
+ .DADDR = (uint32_t)Adc_Group0Buffer,\r
+ .CITERE_LINK = 0,\r
+ .CITER = sizeof(Adc_Group0Buffer)/sizeof(Adc_Group0Buffer[0]),\r
+ .DOFF = sizeof(Adc_ValueGroupType),\r
+ .DLAST_SGA = -sizeof(Adc_Group0Buffer),\r
+ .BITERE_LINK = 0,\r
+ .BITER = sizeof(Adc_Group0Buffer)/sizeof(Adc_Group0Buffer[0]),\r
+ .BWC = 0,\r
+ .MAJORLINKCH = 0,\r
+ .DONE = 0,\r
+ .ACTIVE = 0,\r
+ .MAJORE_LINK = 0,\r
+ .E_SG = 0,\r
+ .D_REQ = 0,\r
+ .INT_HALF = 0,\r
+ .INT_MAJ = 0,\r
+ .START = 0\r
+ },\r
+ {\r
+ .SADDR = (vint32_t)&EQADC.RFPR[ADC_GROUP1].R + 2,\r
+ .SMOD = 0,\r
+ .SSIZE = DMA_TRANSFER_SIZE_16BITS,\r
+ .DMOD = 0,\r
+ .DSIZE = DMA_TRANSFER_SIZE_16BITS,\r
+ .SOFF = 0,\r
+ .NBYTES = sizeof(Adc_ValueGroupType),\r
+ .SLAST = 0,\r
+ .DADDR = (uint32_t)Adc_Group1Buffer,\r
+ .CITERE_LINK = 0,\r
+ .CITER = sizeof(Adc_Group1Buffer)/sizeof(Adc_Group1Buffer[0]),\r
+ .DOFF = sizeof(Adc_ValueGroupType),\r
+ .DLAST_SGA = -sizeof(Adc_Group1Buffer),\r
+ .BITERE_LINK = 0,\r
+ .BITER = sizeof(Adc_Group1Buffer)/sizeof(Adc_Group1Buffer[0]),\r
+ .BWC = 0,\r
+ .MAJORLINKCH = 0,\r
+ .DONE = 0,\r
+ .ACTIVE = 0,\r
+ .MAJORE_LINK = 0,\r
+ .E_SG = 0,\r
+ .D_REQ = 0,\r
+ .INT_HALF = 0,\r
+ .INT_MAJ = 0,\r
+ .START = 0\r
+}\r
+};\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef ADC_CFG_H_\r
+#define ADC_CFG_H_\r
+\r
+#define ADC_PRIORITY_HW 0\r
+#define ADC_PRIORITY_HW_SW 1\r
+#define ADC_PRIORITY_NONE 2\r
+\r
+#define ADC_DEINIT_API STD_ON\r
+#define ADC_DEV_ERROR_DETECT STD_ON\r
+#define ADC_ENABLE_QUEUING STD_ON\r
+#define ADC_ENABLE_START_STOP_GROUP_API STD_ON\r
+#define ADC_GRP_NOTIF_CAPABILITY STD_ON\r
+#define ADC_HW_TRIGGER_API STD_OFF /* Not implemented. */\r
+#define ADC_PRIORITY_IMPLEMENTATION ADC_PRIORITY_HW\r
+#define ADC_READ_GROUP_API STD_ON\r
+#define ADC_VERSION_API STD_ON /* Not implemented. */\r
+\r
+/* Group definitions. */\r
+\r
+\r
+typedef enum\r
+{\r
+ ADC_GROUP0,\r
+ ADC_GROUP1,\r
+ ADC_GROUP2,\r
+ ADC_GROUP3,\r
+ ADC_NBR_OF_GROUPS\r
+}Adc_GroupType;\r
+\r
+typedef enum\r
+{\r
+ ADC_CH0,\r
+ ADC_CH1,\r
+ ADC_CH2,\r
+ ADC_CH3,\r
+ ADC_CH4,\r
+ ADC_CH5,\r
+ ADC_CH6,\r
+ ADC_CH7,\r
+ ADC_CH8,\r
+ ADC_CH9,\r
+ ADC_CH10,\r
+ ADC_CH11,\r
+ ADC_CH12,\r
+ ADC_CH13,\r
+ ADC_CH14,\r
+ ADC_CH15,\r
+ ADC_CH16,\r
+ ADC_CH17,\r
+ ADC_CH18,\r
+ ADC_CH19,\r
+ ADC_CH20,\r
+ ADC_NBR_OF_CHANNELS,\r
+}Adc_ChannelType;\r
+\r
+typedef enum\r
+{\r
+ ADC_TEST_BOARD_AIN1,\r
+ ADC_TEST_BOARD_AIN2,\r
+ ADC_TEST_BOARD_AIN3,\r
+ ADC_TEST_BOARD_AIN4,\r
+ ADC_TEST_BOARD_AIN5,\r
+ ADC_TEST_BOARD_AIN6,\r
+ ADC_TEST_BOARD_AIN7,\r
+ ADC_NBR_OF_GROUP0_CHANNELS,\r
+}Adc_Group0SignalType;\r
+\r
+typedef enum\r
+{\r
+ ADC_GROUP1_CH1,\r
+ ADC_GROUP1_CH2,\r
+ ADC_GROUP1_CH3,\r
+ ADC_GROUP1_CH4,\r
+ ADC_NBR_OF_GROUP1_CHANNELS,\r
+}Adc_Group1SignalType;\r
+\r
+typedef enum\r
+{\r
+ ADC_GROUP2_CH0,\r
+ ADC_GROUP2_CH1,\r
+ ADC_GROUP2_CH2,\r
+ ADC_NBR_OF_GROUP2_CHANNELS,\r
+}Adc_Group2Signals;\r
+\r
+typedef enum\r
+{\r
+ ADC_GROUP3_CH0,\r
+ ADC_GROUP3_CH1,\r
+ ADC_GROUP3_CH2,\r
+ ADC_NBR_OF_GROUP3_CHANNELS,\r
+}Adc_Group3Signals;\r
+\r
+extern const struct tcd_t AdcGroupDMACommandConfig [ADC_NBR_OF_GROUPS];\r
+extern const struct tcd_t AdcGroupDMAResultConfig [ADC_NBR_OF_GROUPS];\r
+\r
+#endif /*ADC_CFG_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include "CanIf.h"\r
+#include <stdlib.h>\r
+\r
+// Imported structs from Can_Lcfg.c\r
+extern const Can_ControllerConfigType CanControllerConfigData[];\r
+extern const Can_ConfigSetType CanConfigSetData;\r
+\r
+\r
+// Container that gets slamed into CanIf_InitController()\r
+// Inits ALL controllers\r
+// Multiplicity 1..*\r
+const CanIf_ControllerConfigType CanIfControllerConfig[] =\r
+{\r
+ { // This is the ConfigurationIndex in CanIf_InitController()\r
+ .WakeupSupport = CANIF_WAKEUP_SUPPORT_NO_WAKEUP,\r
+ .CanIfControllerIdRef = CAN_CTRL_A,\r
+ .CanIfDriverNameRef = "FLEXCAN", // Not used\r
+ .CanIfInitControllerRef = &CanControllerConfigData[0],\r
+ },\r
+ {\r
+ .WakeupSupport = CANIF_WAKEUP_SUPPORT_NO_WAKEUP,\r
+ .CanIfControllerIdRef = CAN_CTRL_C,\r
+ .CanIfDriverNameRef = "FLEXCAN", // Not used\r
+ .CanIfInitControllerRef = &CanControllerConfigData[1],\r
+ }\r
+};\r
+\r
+// Function callbacks for higher layers\r
+const CanIf_DispatchConfigType CanIfDispatchConfig =\r
+{\r
+ .CanIfBusOffNotification = NULL,\r
+ .CanIfWakeUpNotification = NULL, // Not used\r
+ .CanIfWakeupValidNotification = NULL, // Not used\r
+ .CanIfErrorNotificaton = NULL,\r
+};\r
+\r
+//-------------------------------------------------------------------\r
+const CanIf_HthConfigType CanIfHthConfigData[] =\r
+{\r
+ {\r
+ .CanIfHthType = CAN_ECORE_HANDLE_TYPE_BASIC,\r
+ .CanIfCanControllerIdRef = CAN_CTRL_A,\r
+ .CanIfHthIdSymRef = CAN_HTH_A_1, // Ref to the HTH\r
+ .CanIfEcoreEOL = 0,\r
+ },\r
+ {\r
+ .CanIfHthType = CAN_ECORE_HANDLE_TYPE_BASIC,\r
+ .CanIfCanControllerIdRef = CAN_CTRL_C,\r
+ .CanIfHthIdSymRef = CAN_HTH_C_1, // Ref to the HTH\r
+ .CanIfEcoreEOL = 1,\r
+ },\r
+};\r
+\r
+//-------------------------------------------------------------------\r
+const CanIf_HrhConfigType CanIfHrhConfigData[] =\r
+{\r
+ {\r
+ .CanIfHrhType = CAN_ECORE_HANDLE_TYPE_BASIC,\r
+ .CanIfSoftwareFilterHrh = TRUE, // Disable software filtering\r
+ .CanIfCanControllerHrhIdRef = CAN_CTRL_A,\r
+ .CanIfHrhIdSymRef = CAN_HRH_A_1, // Ref to the HRH\r
+ .CanIfEcoreEOL = 0,\r
+ },\r
+ {\r
+ .CanIfHrhType = CAN_ECORE_HANDLE_TYPE_BASIC,\r
+ .CanIfSoftwareFilterHrh = TRUE, // Disable software filtering\r
+ .CanIfCanControllerHrhIdRef = CAN_CTRL_C,\r
+ .CanIfHrhIdSymRef = CAN_HRH_C_1, // Ref to the HRH\r
+ .CanIfEcoreEOL = 1,\r
+ },\r
+};\r
+//-------------------------------------------------------------------\r
+\r
+/*\r
+ * TX PDUs\r
+ */\r
+const CanIf_TxPduConfigType CanIfTxPduConfigData[] =\r
+{\r
+ {\r
+ .CanIfTxPduId = PDU_MSG_HARDWARE_TEST_ENGINE_STATUS, //PDU_MSG_TX789,\r
+ .CanIfCanTxPduIdCanId = 0x0000000,\r
+ .CanIfCanTxPduIdDlc = 8,\r
+ .CanIfCanTxPduType = CANIF_PDU_TYPE_STATIC,\r
+#if ( CANIF_READTXPDU_NOTIFY_STATUS_API == STD_ON )\r
+ .CanIfReadTxPduNotifyStatus = FALSE,\r
+#endif\r
+ .CanIfTxPduIdCanIdType = CANIF_CAN_ID_TYPE_29,\r
+ .CanIfUserTxConfirmation = PduR_CanIfTxConfirmation, //NULL,\r
+ .CanIfCanTxPduHthRef = &CanIfHthConfigData[0], // Send on controller A,\r
+ .PduIdRef = NULL,\r
+ },\r
+ {\r
+ .CanIfTxPduId = PDU_MSG_TX987,\r
+ .CanIfCanTxPduIdCanId = 0x0000100,\r
+ .CanIfCanTxPduIdDlc = 8,\r
+ .CanIfCanTxPduType = CANIF_PDU_TYPE_DYNAMIC,\r
+#if ( CANIF_READTXPDU_NOTIFY_STATUS_API == STD_ON )\r
+ .CanIfReadTxPduNotifyStatus = FALSE,\r
+#endif\r
+ .CanIfTxPduIdCanIdType = CANIF_CAN_ID_TYPE_29,\r
+ .CanIfUserTxConfirmation = NULL,\r
+ .CanIfCanTxPduHthRef = &CanIfHthConfigData[1], // Send on controller C,\r
+ .PduIdRef = NULL,\r
+ },\r
+ //Added by mattias\r
+ {\r
+ .CanIfTxPduId = 2, //PDU_MSG_TX789,\r
+ .CanIfCanTxPduIdCanId = 0x0000200,\r
+ .CanIfCanTxPduIdDlc = 8,\r
+ .CanIfCanTxPduType = CANIF_PDU_TYPE_STATIC,\r
+ #if ( CANIF_READTXPDU_NOTIFY_STATUS_API == STD_ON )\r
+ .CanIfReadTxPduNotifyStatus = FALSE,\r
+ #endif\r
+ .CanIfTxPduIdCanIdType = CANIF_CAN_ID_TYPE_29,\r
+ .CanIfUserTxConfirmation = PduR_CanIfTxConfirmation, // NULL\r
+ .CanIfCanTxPduHthRef = &CanIfHthConfigData[0], // Send on controller A,\r
+ .PduIdRef = NULL,\r
+ },\r
+};\r
+//-------------------------------------------------------------------\r
+\r
+/*\r
+ * RX PDUs\r
+ */\r
+const CanIf_RxPduConfigType CanIfRxPduConfigData[] =\r
+{\r
+ {\r
+ .CanIfCanRxPduId = PDU_MSG_HARDWARE_TEST_ENGINE_CONTROL, //PDU_MSG_RX234,\r
+ .CanIfCanRxPduCanId = 1, // CAN ID\r
+ .CanIfCanRxPduDlc = 8, //DLC\r
+#if ( CANIF_CANPDUID_READDATA_API == STD_ON )\r
+ .CanIfReadRxPduData = FALSE, // no buffering\r
+#endif\r
+#if ( CANIF_READRXPDU_NOTIF_STATUS_API == STD_ON )\r
+ .CanIfReadRxPduNotifyStatus = FALSE, // No indication\r
+#endif\r
+ .CanIfRxPduIdCanIdType = CANIF_CAN_ID_TYPE_29,\r
+ .CanIfRxUserType = CANIF_USER_TYPE_CAN_PDUR, // CANIF_USER_TYPE_CAN_SPECIAL, // Changed by Mattias to test PDU router and Com layer.\r
+ .CanIfUserRxIndication = NULL, // No indication\r
+ .CanIfCanRxPduHrhRef = &CanIfHrhConfigData[0], // Received on controller A\r
+ .PduIdRef = NULL, // Could be used by upper layers\r
+ .CanIfSoftwareFilterType = CANIF_SOFTFILTER_TYPE_MASK, // Not enabled in HRH\r
+ .CanIfCanRxPduCanIdMask = 0xFFF,\r
+ },\r
+ {\r
+ .CanIfCanRxPduId = PDU_MSG_HARDWARE_TEST_ROUTED_MSG, //PDU_MSG_RX123,\r
+ .CanIfCanRxPduCanId = 0x02, // CAN ID\r
+ .CanIfCanRxPduDlc = 8, //DLC\r
+#if ( CANIF_CANPDUID_READDATA_API == STD_ON )\r
+ .CanIfReadRxPduData = FALSE, // no buffering\r
+#endif\r
+#if ( CANIF_READRXPDU_NOTIF_STATUS_API == STD_ON )\r
+ .CanIfReadRxPduNotifyStatus = FALSE, // No indication\r
+#endif\r
+ .CanIfRxPduIdCanIdType = CANIF_CAN_ID_TYPE_29, //\r
+ .CanIfRxUserType = CANIF_USER_TYPE_CAN_PDUR, // CANIF_USER_TYPE_CAN_SPECIAL,\r
+ .CanIfUserRxIndication = NULL, // No indication\r
+ .CanIfCanRxPduHrhRef = &CanIfHrhConfigData[0], //&CanIfHrhConfigData[1], // Received on controller C\r
+ .PduIdRef = NULL, //\r
+ .CanIfSoftwareFilterType = CANIF_SOFTFILTER_TYPE_MASK, // Not enabled in HRH\r
+ .CanIfCanRxPduCanIdMask = 0xFFF,\r
+ },\r
+\r
+};\r
+\r
+//-------------------------------------------------------------------\r
+const CanIf_InitHohConfigType CanIfHohConfigData[] =\r
+{\r
+ {\r
+ .CanConfigSet = &CanConfigSetData,\r
+ .CanIfHrhConfig = CanIfHrhConfigData,\r
+ .CanIfHthConfig = CanIfHthConfigData,\r
+ .CanIfEcoreEOL = 1,\r
+ },\r
+};\r
+\r
+// This container contains the init parameters of the CAN\r
+// Multiplicity 1..*\r
+const CanIf_InitConfigType CanIfInitConfig =\r
+{\r
+ .CanIfConfigSet = 0, // Not used\r
+ .CanIfNumberOfCanRxPduIds = sizeof(CanIfRxPduConfigData)/sizeof(CanIf_RxPduConfigType),\r
+ .CanIfNumberOfCanTXPduIds = sizeof(CanIfTxPduConfigData)/sizeof(CanIf_TxPduConfigType),\r
+ .CanIfNumberOfDynamicCanTXPduIds = 0, // Not used\r
+\r
+ // Containers\r
+ .CanIfHohConfigPtr = CanIfHohConfigData,\r
+ .CanIfRxPduConfigPtr = CanIfRxPduConfigData,\r
+ .CanIfTxPduConfigPtr = CanIfTxPduConfigData,\r
+};\r
+\r
+// This container includes all necessary configuration sub-containers\r
+// according the CAN Interface configuration structure.\r
+CanIf_ConfigType CanIf_Config =\r
+{\r
+ .ControllerConfig = CanIfControllerConfig,\r
+ .DispatchConfig = &CanIfDispatchConfig,\r
+ .InitConfig = &CanIfInitConfig,\r
+ .TransceiverConfig = NULL, // Not used\r
+};\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef CANIF_CFG_H_\r
+#define CANIF_CFG_H_\r
+\r
+#include "Can.h"\r
+\r
+typedef enum {\r
+ CANIF_SOFTFILTER_TYPE_BINARY = 0, // Not supported\r
+ CANIF_SOFTFILTER_TYPE_INDEX, // Not supported\r
+ CANIF_SOFTFILTER_TYPE_LINEAR, // Not supported\r
+ CANIF_SOFTFILTER_TYPE_TABLE, // Not supported\r
+ CANIF_SOFTFILTER_TYPE_MASK, // CanIfCanRxPduCanIdMask in RxPduConfig is used for filtering\r
+} CanIf_SoftwareFilterTypeType;\r
+\r
+typedef enum {\r
+ CANIF_USER_TYPE_CAN_NM,\r
+ CANIF_USER_TYPE_CAN_TP,\r
+ CANIF_USER_TYPE_CAN_PDUR,\r
+ CANIF_USER_TYPE_CAN_SPECIAL,\r
+} CanIf_UserTypeType;\r
+\r
+\r
+\r
+typedef void (*CanIf_FuncTypeCanSpecial)(PduIdType, const uint8 *, uint8, Can_IdType);\r
+\r
+typedef enum {\r
+ CANIF_PDU_TYPE_STATIC = 0,\r
+ CANIF_PDU_TYPE_DYNAMIC // Not supported\r
+} CanIf_PduTypeType;\r
+\r
+typedef enum {\r
+ CANIF_CAN_ID_TYPE_29 = 0,\r
+ CANIF_CAN_ID_TYPE_11\r
+} CanIf_CanIdTypeType;\r
+\r
+/*\r
+ * Public container\r
+ */\r
+#define CANIF_VERSION_INFO_API STD_ON\r
+#define CANIF_DEV_ERROR_DETECT STD_ON\r
+#define CANIF_DLC_CHECK STD_ON\r
+#define CANIF_MULITPLE_DRIVER_SUPPORT STD_OFF // Not supported\r
+#define CANIF_READRXPDU_DATA_API STD_OFF // Not supported\r
+#define CANIF_READRXPDU_NOTIFY_STATUS_API STD_OFF // Not supported\r
+#define CANIF_READTXPDU_NOTIFY_STATUS_API STD_OFF // Not supported\r
+#define CANIF_SETDYNAMICTXID_API STD_OFF // Not supported\r
+#define CANIF_WAKEUP_EVENT_API STD_OFF // Not supported\r
+#define CANIF_TRANSCEIVER_API STD_OFF // Not supported\r
+#define CANIF_TRANSMIT_CANCELLATION STD_OFF // Not supported\r
+\r
+//-------------------------------------------------------------------\r
+\r
+typedef struct {\r
+ void (*CancelTxConfirmation)( void *); // (const Can_PduType *);\r
+ void (*RxIndication)(void *); //(const Can_PduType *);\r
+ void (*ControllerBusOff)(uint8);\r
+ void (*ControllerWakeup)(uint8);\r
+ void (*EcoreError)(uint8,uint32);\r
+} CanIf_CallbackType;\r
+\r
+\r
+\r
+//-------------------------------------------------------------------\r
+/*\r
+ * CanIfHrhRangeConfig container\r
+ */\r
+\r
+typedef struct {\r
+ // Lower CAN Identifier of a receive CAN L-PDU for identifier range\r
+ // definition, in which all CAN Ids shall pass the software filtering. Range: 11\r
+ // Bit for Standard CAN Identifier 29 Bit for Extended CAN Identifer\r
+ uint32 CanIfRxPduLowerCanId;\r
+\r
+ // Upper CAN Identifier of a receive CAN L-PDU for identifier range\r
+ // definition, in which all CAN Ids shall pass the software filtering. Range: 11\r
+ // Bit for Standard CAN Identifier 29 Bit for Extended CAN Identifer\r
+ uint32 CanIfRxPduUpperCanId;\r
+} CanIf_HrhRangeConfigType;\r
+\r
+\r
+\r
+//-------------------------------------------------------------------\r
+/*\r
+ * CanIfInitHrhConfig container\r
+ */\r
+typedef struct {\r
+ // Defines the HRH type i.e, whether its a BasicCan or FullCan. If BasicCan is\r
+ // configured, software filtering is enabled.\r
+ Can_EcoreHohType CanIfHrhType;\r
+\r
+ // Selects the hardware receive objects by using the HRH range/list from\r
+ // CAN Driver configuration to define, for which HRH a software filtering has\r
+ // to be performed at during receive processing. True: Software filtering is\r
+ // enabled False: Software filtering is disabled\r
+ boolean CanIfSoftwareFilterHrh;\r
+\r
+ // Reference to controller Id to which the HRH belongs to. A controller can\r
+ // contain one or more HRHs.\r
+ uint8 CanIfCanControllerHrhIdRef;\r
+\r
+ // The parameter refers to a particular HRH object in the CAN Driver Module\r
+ // configuration. The HRH id is unique in a given CAN Driver. The HRH Ids\r
+ // are defined in the CAN Driver Module and hence it is derived from CAN\r
+ // Driver Configuration.\r
+ Can_EcoreHRHType CanIfHrhIdSymRef ;\r
+\r
+ // Defines the parameters required for configuraing multiple\r
+ // CANID ranges for a given same HRH.\r
+ const CanIf_HrhRangeConfigType *CanIfHrhRangeConfig;\r
+\r
+ // End Of List. Set to TRUE is this is the last object in the list.\r
+ boolean CanIfEcoreEOL;\r
+} CanIf_HrhConfigType;\r
+\r
+//-------------------------------------------------------------------\r
+/*\r
+ * CanIfInitHthConfig container\r
+ */\r
+\r
+typedef struct {\r
+ // Defines the HTH type i.e, whether its a BasicCan or FullCan.\r
+ Can_EcoreHohType CanIfHthType;\r
+\r
+ // Reference to controller Id to which the HTH belongs to. A controller\r
+ // can contain one or more HTHs\r
+ uint8 CanIfCanControllerIdRef;\r
+\r
+ // The parameter refers to a particular HTH object in the CAN Driver Module\r
+ // configuration. The HTH id is unique in a given CAN Driver. The HTH Ids\r
+ // are defined in the CAN Driver Module and hence it is derived from CAN\r
+ // Driver Configuration.\r
+ Can_EcoreHTHType CanIfHthIdSymRef ;\r
+\r
+ // End Of List. Set to TRUE is this is the last object in the list.\r
+ boolean CanIfEcoreEOL;\r
+} CanIf_HthConfigType;\r
+\r
+//-------------------------------------------------------------------\r
+/*\r
+ * CanIfInitHohConfig container\r
+ */\r
+typedef struct {\r
+ // Selects the CAN interface specific configuration setup. This type of external\r
+ // data structure shall contain the post build initialization data for the\r
+ // CAN interface for all underlying CAN Drivers.\r
+ const Can_ConfigSetType *CanConfigSet;\r
+\r
+ // This container contains contiguration parameters for each hardware receive object.\r
+ const CanIf_HrhConfigType *CanIfHrhConfig;\r
+\r
+ // This container contains parameters releated to each HTH\r
+ const CanIf_HthConfigType *CanIfHthConfig;\r
+\r
+ // End Of List. Set to TRUE is this is the last object in the list.\r
+ boolean CanIfEcoreEOL;\r
+} CanIf_InitHohConfigType;\r
+\r
+//-------------------------------------------------------------------\r
+/*\r
+ * CanIfTxPduConfig container\r
+ */\r
+\r
+// This container contains the configuration (parameters) of each transmit\r
+// CAN L-PDU. The SHORT-NAME of "CanIfTxPduConfig" container\r
+// represents the symolic name of Transmit L-PDU.\r
+typedef struct {\r
+ // ECU wide unique, symbolic handle for transmit CAN L-PDU. The\r
+ // CanIfCanTxPduId is configurable at pre-compile and post-built time.\r
+ // Range: 0..max. number of CantTxPduIds PduIdType CanTxPduId;\r
+ PduIdType CanIfTxPduId;\r
+\r
+ // CAN Identifier of transmit CAN L-PDUs used by the CAN Driver for CAN L-\r
+ // PDU transmission. Range: 11 Bit For Standard CAN Identifier ... 29 Bit For\r
+ // Extended CAN identifier\r
+ uint32 CanIfCanTxPduIdCanId;\r
+\r
+ // Data length code (in bytes) of transmit CAN L-PDUs used by the CAN\r
+ // Driver for CAN L-PDU transmission. The data area size of a CAN L-Pdu\r
+ // can have a range from 0 to 8 bytes.\r
+ uint8 CanIfCanTxPduIdDlc;\r
+\r
+ // Defines the type of each transmit CAN L-PDU.\r
+ // DYNAMIC CAN ID is defined at runtime.\r
+ // STATIC CAN ID is defined at compile-time.\r
+ CanIf_PduTypeType CanIfCanTxPduType;\r
+\r
+#if ( CANIF_READTXPDU_NOTIFY_STATUS_API == STD_ON )\r
+ // Enables and disables transmit confirmation for each transmit CAN L-PDU\r
+ // for reading its notification status. True: Enabled False: Disabled\r
+ boolean CanIfReadTxPduNotifyStatus;\r
+#endif\r
+\r
+ // CAN Identifier of transmit CAN L-PDUs used by the CAN Driver for CAN L-\r
+ // PDU transmission.\r
+ // EXTENDED_CAN The CANID is of type Extended (29 bits)\r
+ // STANDARD_CAN The CANID is of type Standard (11 bits)\r
+ CanIf_CanIdTypeType CanIfTxPduIdCanIdType;\r
+\r
+ // Name of target confirmation services to target upper layers (PduR, CanNm\r
+ // and CanTp. If parameter is not configured then no call-out function is\r
+ // provided by the upper layer for this Tx L-PDU.\r
+ void (*CanIfUserTxConfirmation)(PduIdType); /* CANIF 109 */\r
+\r
+ // Handle, that defines the hardware object or the pool of hardware objects\r
+ // configured for transmission. The parameter refers HTH Id, to which the L-\r
+ // PDU belongs to.\r
+ const CanIf_HthConfigType *CanIfCanTxPduHthRef;\r
+\r
+ // Reference to the "global" Pdu structure to allow harmonization of handle\r
+ // IDs in the COM-Stack. ..\r
+ void *PduIdRef;\r
+} CanIf_TxPduConfigType;\r
+\r
+//-------------------------------------------------------------------\r
+/*\r
+ * CanIfRxPduConfig container\r
+ */\r
+\r
+\r
+// This container contains the configuration (parameters) of each receive\r
+// CAN L-PDU. The SHORT-NAME of "CanIfRxPduConfig" container itself\r
+// represents the symolic name of Receive L-PDU.\r
+\r
+typedef struct {\r
+ // ECU wide unique, symbolic handle for receive CAN L-PDU. The\r
+ // CanRxPduId is configurable at pre-compile and post-built time. It shall fulfill\r
+ // ANSI/AUTOSAR definitions for constant defines. Range: 0..max. number\r
+ // of defined CanRxPduIds\r
+ PduIdType CanIfCanRxPduId;\r
+\r
+ // CAN Identifier of Receive CAN L-PDUs used by the CAN Interface. Exa:\r
+ // Software Filtering. Range: 11 Bit For Standard CAN Identifier ... 29 Bit For\r
+ // Extended CAN identifier\r
+ uint32 CanIfCanRxPduCanId;\r
+\r
+ // Data Length code of received CAN L-PDUs used by the CAN Interface.\r
+ // Exa: DLC check. The data area size of a CAN L-PDU can have a range\r
+ // from 0 to 8 bytes. uint8 CanIfCanRxPduDlc;\r
+ uint8 CanIfCanRxPduDlc;\r
+\r
+#if ( CANIF_CANPDUID_READDATA_API == STD_ON )\r
+ // Enables and disables the Rx buffering for reading of received L-PDU data.\r
+ // True: Enabled False: Disabled\r
+ boolean CanIfReadRxPduData;\r
+#endif\r
+\r
+#if ( CANIF_READRXPDU_NOTIF_STATUS_API == STD_ON )\r
+ // CanIfReadRxPduNotifyStatus {CANIF_READRXPDU_NOTIFY_STATUS}\r
+ // Enables and disables receive indication for each receive CAN L-PDU for\r
+ // reading its' notification status. True: Enabled False: Disabled\r
+ boolean CanIfReadRxPduNotifyStatus;\r
+#endif\r
+\r
+ // CAN Identifier of receive CAN L-PDUs used by the CAN Driver for CAN L-\r
+ // PDU transmission.\r
+ // EXTENDED_CAN The CANID is of type Extended (29 bits)\r
+ // STANDARD_CAN The CANID is of type Standard (11 bits)\r
+ CanIf_CanIdTypeType CanIfRxPduIdCanIdType;\r
+\r
+ // This parameter defines the type of the receive indication call-outs called to\r
+ // the corresponding upper layer the used TargetRxPduId belongs to.\r
+ CanIf_UserTypeType CanIfRxUserType;\r
+\r
+ // Name of target indication services to target upper layers (PduRouter,\r
+ // CanNm, CanTp and ComplexDeviceDrivers). If parameter is 0 no call-out\r
+ // function is configured.\r
+ void *CanIfUserRxIndication;\r
+\r
+ // The HRH to which Rx L-PDU belongs to, is referred through this\r
+ // parameter.\r
+ const CanIf_HrhConfigType *CanIfCanRxPduHrhRef;\r
+\r
+ // Reference to the "global" Pdu structure to allow harmonization of handle\r
+ // IDs in the COM-Stack.\r
+ void *PduIdRef;\r
+\r
+ // Defines the type of software filtering that should be used\r
+ // for this receive object.\r
+ CanIf_SoftwareFilterTypeType CanIfSoftwareFilterType;\r
+\r
+ // Acceptance filters, 1 - care, 0 - don't care.\r
+ // Is enabled by the CanIfSoftwareFilterMask in CanIf_HrhConfigType\r
+ // Ecore exension\r
+ uint32 CanIfCanRxPduCanIdMask;\r
+\r
+} CanIf_RxPduConfigType;\r
+\r
+//-------------------------------------------------------------------\r
+\r
+/*\r
+ * CanIfControllerConfig container\r
+ */\r
+\r
+typedef enum {\r
+ CANIF_WAKEUP_SUPPORT_CONTROLLER,\r
+ CANIF_WAKEUP_SUPPORT_NO_WAKEUP,\r
+ CANIF_WAKEUP_SUPPORT_TRANSCEIVER,\r
+} CanIf_WakeupSupportType;\r
+\r
+\r
+// This is the type supplied to CanIf_InitController()\r
+typedef struct {\r
+ CanIf_WakeupSupportType WakeupSupport; // Not used\r
+\r
+ CanControllerIdType CanIfControllerIdRef;\r
+\r
+ const char CanIfDriverNameRef[8]; // Not used\r
+\r
+ const Can_ControllerConfigType *CanIfInitControllerRef;\r
+} CanIf_ControllerConfigType;\r
+\r
+//-------------------------------------------------------------------\r
+/*\r
+ * CanIfTransceiverDrvConfig container\r
+ */\r
+\r
+typedef struct {\r
+ boolean TrcvWakeupNotification;\r
+ uint8 TrcvIdRef;\r
+} CanIf_TransceiverDrvConfigType;\r
+\r
+\r
+typedef struct {\r
+ uint32 todo;\r
+} CanIf_TransceiverConfigType;\r
+\r
+// Callout functions with respect to the upper layers. This callout functions\r
+// defined in this container are common to all configured underlying CAN\r
+// Drivers / CAN Transceiver Drivers.\r
+typedef struct {\r
+ // Name of target BusOff notification services to target upper layers\r
+ // (PduRouter, CanNm, CanTp and ComplexDeviceDrivers).\r
+ // Multiplicity: 1\r
+ void (*CanIfBusOffNotification)(uint8 Controller);\r
+\r
+ // Name of target wakeup notification services to target upper layers\r
+ // e.g Ecu_StateManager. If parameter is 0\r
+ // no call-out function is configured.\r
+ // Multiplicity: 0..1\r
+ void (*CanIfWakeUpNotification)();\r
+\r
+ // Name of target wakeup validation notification services to target upper\r
+ // layers (ECU State Manager). If parameter is 0 no call-out function is\r
+ // configured.\r
+ // Multiplicity: 0..1\r
+ void (*CanIfWakeupValidNotification)();\r
+\r
+ // Ecore ext.\r
+ void (*CanIfErrorNotificaton)(uint8,Can_EcoreErrorType);\r
+\r
+} CanIf_DispatchConfigType;\r
+\r
+// This container contains the references to the configuration setup of each\r
+// underlying CAN driver.\r
+\r
+typedef struct {\r
+ // Selects the CAN Interface specific configuration setup. This type of the\r
+ // external data structure shall contain the post build initialization data for the\r
+ // CAN Interface for all underlying CAN Dirvers. constant to CanIf_ConfigType\r
+ uint32 CanIfConfigSet;\r
+\r
+ uint32 CanIfNumberOfCanRxPduIds;\r
+ uint32 CanIfNumberOfCanTXPduIds;\r
+ uint32 CanIfNumberOfDynamicCanTXPduIds;\r
+\r
+ //\r
+ // Containers\r
+ //\r
+\r
+ // This container contains the reference to the configuration\r
+ // setup of each underlying CAN driver.\r
+ // Multiplicity: 0..*\r
+ const CanIf_InitHohConfigType *CanIfHohConfigPtr;\r
+\r
+ // This container contains the configuration (parameters) of each\r
+ // receive CAN L-PDU. The SHORT-NAME of\r
+ // "CanIfRxPduConfig" container itself represents the symolic\r
+ // name of Receive L-PDU.\r
+ // Multiplicity: 0..*\r
+ const CanIf_RxPduConfigType *CanIfRxPduConfigPtr;\r
+\r
+ // This container contains the configuration (parameters) of each\r
+ // transmit CAN L-PDU. The SHORT-NAME of\r
+ // "CanIfTxPduConfig" container represents the symolic name of\r
+ // Transmit L-PDU.\r
+ // Multiplicity: 0..*\r
+ const CanIf_TxPduConfigType *CanIfTxPduConfigPtr;\r
+\r
+} CanIf_InitConfigType;\r
+\r
+\r
+typedef struct {\r
+ // This container contains the configuration (parameters) of all\r
+ // addressed CAN controllers by each underlying CAN driver.\r
+ // Multiplicity: 1..*\r
+ const CanIf_ControllerConfigType *ControllerConfig;\r
+\r
+ // Callout functions with respect to the upper layers. This callout\r
+ // functions defined in this container are common to all\r
+ // configured underlying CAN Drivers / CAN Transceiver Drivers\r
+ const CanIf_DispatchConfigType *DispatchConfig;\r
+\r
+ // This container contains the init parameters of the CAN\r
+ // Interface.\r
+ // Multiplicity: 1..*\r
+ const CanIf_InitConfigType *InitConfig;\r
+\r
+ // This container contains the configuration (parameters) of all\r
+ // addressed CAN transceivers by each underlying CAN\r
+ // Transceiver Driver.\r
+ // Multiplicity: 1..*\r
+ const CanIf_TransceiverConfigType *TransceiverConfig;\r
+} CanIf_ConfigType;\r
+\r
+\r
+extern CanIf_ConfigType CanIf_Config;\r
+\r
+#endif\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef CAN_CFG_H_\r
+#define CAN_CFG_H_\r
+\r
+// Number of controller configs\r
+#define CAN_ECORE_CTRL_CONFIG_CNT 2\r
+\r
+#define CAN_DEV_ERROR_DETECT STD_ON\r
+#define CAN_VERSION_INFO_API STD_ON\r
+#define CAN_MULTIPLEXED_TRANSMISSION STD_ON // Makes no differens in the code\r
+#define CAN_WAKEUP_SUPPORT STD_OFF // Not supported\r
+#define CAN_HW_TRANSMIT_CANCELLATION STD_OFF // Not supported\r
+\r
+// loop cnt.. very strange timeout\r
+#define CAN_TIMEOUT_DURATION 100\r
+\r
+#define INTERRUPT 0\r
+#define POLLING 1\r
+\r
+// Can controller\r
+#define CAN_BUSOFF_PROCESSING INTERRUPT // INTERRUPT/POLLING\r
+#define CAN_CONTROLLER_ACTIVATION OFF\r
+#define CAN_CONTROLLER_BAUD_RATE 125000\r
+#define CAN_DRIVER_CONTROLLER_ID 0\r
+#define CAN_CONTROLLER_PROP_SEG 4\r
+#define CAN_CONTROLLER_PHASE1_SEG 4\r
+#define CAN_CONTROLLER_PHASE2_SEG 4\r
+#define CAN_CONTROLLER_TIME_QUANTA 4\r
+#define CAN_RX_PROCESSING INTERRUPT\r
+#define CAN_TX_PROCESSING INTERRUPT\r
+#define CAN_WAKEUP_PROCESSING INTERRUPT\r
+\r
+typedef enum {\r
+ CAN_CTRL_A = 0,\r
+ CAN_CTRL_B,\r
+ CAN_CTRL_C,\r
+ CAN_CTRL_D,\r
+ CAN_CTRL_E,\r
+ CAN_CTRL_F,\r
+ CAN_CONTROLLER_CNT \r
+}CanControllerIdType;\r
+\r
+typedef enum {\r
+ CAN_ID_TYPE_EXTENDED,\r
+ CAN_ID_TYPE_MIXED,\r
+ CAN_ID_TYPE_STANDARD,\r
+} Can_IdTypeType;\r
+\r
+typedef enum {\r
+ CAN_OBJECT_TYPE_RECEIVE,\r
+ CAN_OBJECT_TYPE_TRANSMIT,\r
+} Can_ObjectTypeType;\r
+\r
+typedef enum {\r
+ CAN_ECORE_HANDLE_TYPE_BASIC,\r
+ CAN_ECORE_HANDLE_TYPE_FULL\r
+} Can_EcoreHohType;\r
+\r
+// HTH definitions\r
+// Due to effiency: Start with index 0 and don't use any holes in the enumeration\r
+typedef enum {\r
+ CAN_HTH_A_1 = 0,\r
+ CAN_HTH_C_1,\r
+ NUM_OF_HTHS\r
+} Can_EcoreHTHType;\r
+\r
+// HRH definitions\r
+// Due to effiency: Start with index 0 and don't use any holes in the enumeration\r
+typedef enum {\r
+ CAN_HRH_A_1 = 0,\r
+ CAN_HRH_C_1,\r
+ NUM_OF_HRHS\r
+} Can_EcoreHRHType;\r
+\r
+// Non-standard type\r
+typedef struct {\r
+ void (*CancelTxConfirmation)( const Can_PduType *);\r
+ void (*RxIndication)( uint8 ,Can_IdType ,uint8 , const uint8 * );\r
+ void (*ControllerBusOff)(uint8);\r
+ void (*TxConfirmation)(PduIdType);\r
+ void (*ControllerWakeup)(uint8);\r
+ void (*EcoreError)(uint8,Can_EcoreErrorType);\r
+} Can_CallbackType;\r
+\r
+/*\r
+ * CanGeneral Container\r
+ */\r
+\r
+// This container contains the parameters related each CAN Driver Unit.\r
+typedef struct {\r
+ // Specifies the InstanceId of this module instance. If only one instance is\r
+ // present it shall have the Id 0\r
+ int CanIndex;\r
+\r
+#if 0 // This is only used by the config tool\r
+ // This parameter describes the period for cyclic call to\r
+ // Can_MainFunction_Busoff. Unit is seconds.\r
+ float CanMainFunctionBusoffPeriod;\r
+ // This parameter describes the period for cyclic call to\r
+ // Can_MainFunction_Read. Unit is seconds.\r
+ float CanMainFunctionReadPeriod;\r
+ // This parameter describes the period for cyclic call to\r
+ // Can_MainFunction_Wakeup. Unit is seconds.\r
+ float CanMainFunctionWakeupPeriod;\r
+ // This parameter describes the period for cyclic call to\r
+ // Can_MainFunction_Write. Unit is seconds.\r
+ float CanMainFunctionWritePeriod;\r
+#endif\r
+\r
+\r
+#if ( CAN_TIMEOUT_DURATION == STD_ON )\r
+ // Specifies the maximum number of loops for blocking function until a\r
+ // timeout is raised in short term wait loops.\r
+ uint32 CanTimeoutDurationFactor;\r
+#endif\r
+\r
+} Can_GeneralType;\r
+\r
+\r
+/*\r
+ * CanFilterMask container\r
+ */\r
+typedef uint32 Can_FilterMaskType;\r
+\r
+/*\r
+ * CanHardwareObject container\r
+ */\r
+\r
+//This container contains the configuration (parameters) of CAN Hardware\r
+//Objects.\r
+typedef struct Can_HardwareObjectStruct {\r
+ // Specifies the type (Full-CAN or Basic-CAN) of a hardware object.\r
+ Can_EcoreHohType CanHandleType;\r
+\r
+ // Specifies whether the IdValue is of type - standard identifier - extended\r
+ // identifier - mixed mode ImplementationType: Can_IdType\r
+ Can_IdTypeType CanIdType;\r
+\r
+ // Specifies (together with the filter mask) the identifiers range that passes\r
+ // the hardware filter.\r
+ uint32 CanIdValue;\r
+\r
+ // Holds the handle ID of HRH or HTH. The value of this parameter is unique\r
+ // in a given CAN Driver, and it should start with 0 and continue without any\r
+ // gaps. The HRH and HTH Ids are defined under two different name-spaces.\r
+ // Example: HRH0-0, HRH1-1, HTH0-2, HTH1-3\r
+ uint32 CanObjectId;\r
+\r
+ // Specifies if the HardwareObject is used as Transmit or as Receive object\r
+ Can_ObjectTypeType CanObjectType;\r
+\r
+ // Reference to the filter mask that is used for hardware filtering togerther\r
+ // with the CAN_ID_VALUE\r
+ Can_FilterMaskType *CanFilterMaskRef;\r
+\r
+ // A "1" in this mask tells the driver that that HW Message Box should be\r
+ // occupied by this Hoh. A "1" in bit 31(ppc) occupies Mb 0 in HW.\r
+ uint32 CanEcoreMbMask;\r
+\r
+ // End Of List. Set to TRUE is this is the last object in the list.\r
+ boolean CanEcoreEOL;\r
+\r
+} Can_HardwareObjectType;\r
+\r
+\r
+/*\r
+ * CanController container\r
+ */\r
+typedef enum {\r
+ CAN_ECORE_PROCESS_TYPE_INTERRUPT,\r
+ CAN_ECORE_PROCESS_TYPE_POLLING,\r
+} Can_EcoreProcessType;\r
+\r
+typedef struct {\r
+\r
+ // Enables / disables API Can_MainFunction_BusOff() for handling busoff\r
+ // events in polling mode.\r
+ // INTERRUPT or POLLING\r
+ Can_EcoreProcessType CanBusOffProcessing;\r
+\r
+ // Defines if a CAN controller is used in the configuration.\r
+ boolean CanControllerActivation;\r
+\r
+ // Specifies the buadrate of the controller in kbps.\r
+ uint32 CanControllerBaudRate;\r
+\r
+ // This parameter provides the controller ID which is unique in a given CAN\r
+ // Driver. The value for this parameter starts with 0 and continue without any\r
+ // gaps.\r
+ CanControllerIdType CanControllerId;\r
+\r
+ // Specifies propagation delay in time quantas.\r
+ uint32 CanControllerPropSeg;\r
+\r
+ // Specifies phase segment 1 in time quantas.\r
+ uint32 CanControllerSeg1;\r
+\r
+ // Specifies phase segment 2 in time quantas.\r
+ uint32 CanControllerSeg2;\r
+\r
+ // Specifies the time quanta for the controller. The calculation of the resulting\r
+ // prescaler value depending on module clocking and time quanta shall be\r
+ // done offline Hardware specific.\r
+ uint32 CanControllerTimeQuanta;\r
+\r
+ // Enables / disables API Can_MainFunction_Read() for handling PDU\r
+ // reception events in polling mode.\r
+ Can_EcoreProcessType CanRxProcessing;\r
+\r
+ // Enables / disables API Can_MainFunction_Write() for handling PDU\r
+ // transmission events in polling mode.\r
+ Can_EcoreProcessType CanTxProcessing;\r
+\r
+ // Enables / disables API Can_MainFunction_Wakeup() for handling wakeup\r
+ // events in polling mode.\r
+ Can_EcoreProcessType CanWakeupProcessing;\r
+\r
+ // Reference to the CPU clock configuration, which is set in the MCU driver\r
+ // configuration\r
+ uint32 CanCpuClockRef;\r
+\r
+ // This parameter contains a reference to the Wakeup Source for this\r
+ // controller as defined in the ECU State Manager. Implementation Type:\r
+ // reference to EcuM_WakeupSourceType\r
+ uint32 CanWakeupSourceRef;\r
+\r
+ //\r
+ // Ecore stuff\r
+ //\r
+\r
+ // List of Hoh id's that belong to this controller\r
+ const Can_HardwareObjectType *CanEcoreHoh;\r
+\r
+ boolean CanEcoreLoopback;\r
+\r
+ // Set this to use the fifo\r
+ boolean CanEcoreFifo;\r
+\r
+} Can_ControllerConfigType;\r
+\r
+\r
+\r
+/*\r
+ * CanConfigSet container\r
+ */\r
+typedef struct {\r
+ const Can_ControllerConfigType *CanController;\r
+ \r
+ // Callbacks( Extension )\r
+ const Can_CallbackType *CanCallbacks;\r
+} Can_ConfigSetType;\r
+\r
+\r
+typedef struct {\r
+ // This is the multiple configuration set container for CAN Driver\r
+ // Multiplicity 1..*\r
+ const Can_ConfigSetType *CanConfigSet;\r
+ // This container contains the parameters related each CAN\r
+ // Driver Unit.\r
+ // Multiplicity 1..*\r
+ const Can_GeneralType *CanGeneral;\r
+\r
+\r
+} Can_ConfigType;\r
+\r
+\r
+extern const Can_ConfigType CanConfigData;\r
+extern const Can_ControllerConfigType CanControllerConfigData[];\r
+extern const Can_ConfigSetType Can_ConfigSet;\r
+\r
+\r
+#endif /*CAN_CFG_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include <stdlib.h>\r
+#include "Can.h"\r
+#include "CanIf_Cbk.h"\r
+\r
+/* CONFIGURATION TEMPLATE\r
+ * ------------------------------------------------------------------\r
+ *\r
+ * The following template configures:\r
+ * - 2 CAN controllers, CAN_CTRL_A and CAN_CNTR_C\r
+ * - Callbacks are configured to call standard CanIf callbacks\r
+ *\r
+ * CAN_CTRL_A\r
+ * - 125K baudrate\r
+ * - Extended 11-bit ID's\r
+ * - Rx/Tx are interrupt based\r
+ * - Both Rx(MB 16->24) and Tx(MB 24->31) Hoh's are of type BASIC\r
+ *\r
+ * CAN_CTRL_C\r
+ * - 125K baudrate\r
+ * - Standard 29-bit ID's\r
+ * - Rx/Tx are interrupt based\r
+ * - Both Rx(MB 16->24) and Tx(MB 24->31) Hoh's are of type BASIC\r
+ * *\r
+ */\r
+\r
+// Accept everything = 0\r
+Can_FilterMaskType Can_FilterMaskConfigData = 0;\r
+\r
+// HOH:s for CAN_CTRL_A\r
+const Can_HardwareObjectType CanHardwareObjectConfig_CTRL_A[] =\r
+{\r
+ {\r
+ .CanHandleType = CAN_ECORE_HANDLE_TYPE_BASIC,\r
+ .CanIdType = CAN_ID_TYPE_EXTENDED,\r
+ .CanObjectType = CAN_OBJECT_TYPE_RECEIVE,\r
+ .CanObjectId = CAN_HRH_A_1,\r
+ .CanFilterMaskRef = &Can_FilterMaskConfigData,\r
+ // Ecore\r
+ .CanEcoreMbMask = 0x00ff0000,\r
+ .CanEcoreEOL = 0,\r
+ },\r
+ {\r
+ .CanHandleType = CAN_ECORE_HANDLE_TYPE_BASIC,\r
+ .CanIdType = CAN_ID_TYPE_EXTENDED,\r
+ .CanObjectType = CAN_OBJECT_TYPE_TRANSMIT,\r
+ .CanObjectId = CAN_HTH_A_1,\r
+ .CanFilterMaskRef = &Can_FilterMaskConfigData,\r
+ // Ecore\r
+ .CanEcoreMbMask = 0xff000000,\r
+ .CanEcoreEOL = 1,\r
+ },\r
+};\r
+\r
+// HOH:s for CAN_CTRL_C\r
+const Can_HardwareObjectType CanHardwareObjectConfig_CTRL_C[] =\r
+{\r
+ {\r
+ .CanHandleType = CAN_ECORE_HANDLE_TYPE_BASIC,\r
+ .CanIdType = CAN_ID_TYPE_STANDARD,\r
+ .CanObjectType = CAN_OBJECT_TYPE_RECEIVE,\r
+ .CanObjectId = CAN_HRH_C_1,\r
+ .CanFilterMaskRef = &Can_FilterMaskConfigData,\r
+ // Ecore\r
+ .CanEcoreMbMask = 0x00ff0000,\r
+ .CanEcoreEOL = 0,\r
+ },\r
+ {\r
+ .CanHandleType = CAN_ECORE_HANDLE_TYPE_BASIC,\r
+ .CanIdType = CAN_ID_TYPE_STANDARD,\r
+ .CanObjectType = CAN_OBJECT_TYPE_TRANSMIT,\r
+ .CanObjectId = CAN_HTH_C_1,\r
+ .CanFilterMaskRef = &Can_FilterMaskConfigData,\r
+ // Ecore\r
+ .CanEcoreMbMask = 0xff000000,\r
+ .CanEcoreEOL = 1,\r
+ },\r
+};\r
+\r
+/* CAN controller data for ALL controllers that are to be configured\r
+ * See Autosar release 3.0 specification for more info\r
+ */\r
+const Can_ControllerConfigType CanControllerConfigData[] =\r
+{\r
+ {\r
+ .CanControllerActivation = TRUE,\r
+ .CanControllerBaudRate = 125,\r
+ .CanControllerId = CAN_CTRL_A,\r
+ .CanControllerPropSeg = 4,\r
+ .CanControllerSeg1 = 4,\r
+ .CanControllerSeg2 = 4,\r
+ .CanBusOffProcessing = CAN_ECORE_PROCESS_TYPE_INTERRUPT,\r
+ .CanRxProcessing = CAN_ECORE_PROCESS_TYPE_INTERRUPT,\r
+ .CanTxProcessing = CAN_ECORE_PROCESS_TYPE_INTERRUPT,\r
+ .CanWakeupProcessing = CAN_ECORE_PROCESS_TYPE_INTERRUPT,\r
+ .CanCpuClockRef = PERIPHERAL_CLOCK_FLEXCAN_A,\r
+ // Ecore\r
+ .CanEcoreHoh = &CanHardwareObjectConfig_CTRL_A[0],\r
+ .CanEcoreLoopback = 0,\r
+ .CanEcoreFifo = 0,\r
+\r
+ },{\r
+ .CanControllerActivation = TRUE,\r
+ .CanControllerBaudRate = 125,\r
+ .CanControllerId = CAN_CTRL_C,\r
+ .CanControllerPropSeg = 4,\r
+ .CanControllerSeg1 = 4,\r
+ .CanControllerSeg2 = 4,\r
+ .CanBusOffProcessing = CAN_ECORE_PROCESS_TYPE_INTERRUPT,\r
+ .CanRxProcessing = CAN_ECORE_PROCESS_TYPE_INTERRUPT,\r
+ .CanTxProcessing = CAN_ECORE_PROCESS_TYPE_INTERRUPT,\r
+ .CanWakeupProcessing = CAN_ECORE_PROCESS_TYPE_INTERRUPT,\r
+ .CanCpuClockRef = PERIPHERAL_CLOCK_FLEXCAN_C,\r
+ // Ecore\r
+ .CanEcoreHoh = &CanHardwareObjectConfig_CTRL_C[0],\r
+ .CanEcoreLoopback = 1,\r
+ .CanEcoreFifo = 0,\r
+ }\r
+};\r
+\r
+/* Callbacks for the can drivers\r
+ * See Autosar release 3.0 specification for more info\r
+ */\r
+const Can_CallbackType CanCallbackConfigData = {\r
+ NULL, //CanIf_CancelTxConfirmation,\r
+ CanIf_RxIndication,\r
+ CanIf_ControllerBusOff,\r
+ CanIf_TxConfirmation,\r
+ NULL, //CanIf_ControllerWakeup,\r
+ CanIf_EcoreError,\r
+};\r
+\r
+/* Configset configuration information\r
+ * See Autosar release 3.0 specification for more info\r
+ */\r
+const Can_ConfigSetType CanConfigSetData =\r
+{\r
+ .CanController = CanControllerConfigData,\r
+ .CanCallbacks = &CanCallbackConfigData,\r
+};\r
+\r
+/* Top config struct passed to Can_Init() */\r
+const Can_ConfigType CanConfigData = {\r
+ .CanConfigSet = &CanConfigSetData,\r
+};\r
+\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*\r
+ * ComGlobals.h\r
+ *\r
+ * Created on: 2009-jan-11\r
+ * Author: Mattias\r
+ */\r
+\r
+#ifndef COMGLOBALS_H_\r
+#define COMGLOBALS_H_\r
+\r
+\r
+// PDU definitions\r
+enum {\r
+ // Used for PCAN.\r
+ PCAN_RX_FRAME_1 = 0,\r
+ PCAN_RX_FRAME_2 = 2,\r
+ PCAN_TX_FRAME_1 = 3,\r
+ PCAN_TX_FRAME_2 = 4,\r
+\r
+ // Used for hardware test.\r
+ PDU_MSG_HARDWARE_TEST_ENGINE_STATUS = 0,\r
+ PDU_MSG_HARDWARE_TEST_ENGINE_CONTROL = 1,\r
+ PDU_MSG_HARDWARE_TEST_ROUTED_MSG = 2,\r
+\r
+ // Used for testing CanIf\r
+ PDU_MSG_RX234 = 8,\r
+ PDU_MSG_RX123 = 10,\r
+ PDU_MSG_TX789 = 9,\r
+ PDU_MSG_TX987 = 11\r
+\r
+};\r
+\r
+\r
+#endif /* COMGLOBALS_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef COM_CFG_H_\r
+#define COM_CFG_H_\r
+\r
+#define COM_MODULE_ID 20\r
+#define COM_INSTANCE_ID 1\r
+\r
+#define COM_DEV_ERROR_DETECT\r
+\r
+\r
+#define COM_MAX_NR_IPDU 30\r
+#define COM_MAX_NR_SIGNAL 30\r
+#define COM_MAX_NR_GROUPSIGNAL 30\r
+\r
+#define COM_MAX_NR_SIGNALS_PER_IPDU 10\r
+#define COM_MAX_NR_SIGNALGROUPS_PER_IPDU 10\r
+#define COM_MAX_NR_SIGNALS_PER_SIGNAL_GROUP 10\r
+\r
+\r
+#define COM_E_INVALID_FILTER_CONFIGURATION 101\r
+#define COM_E_INITIALIZATION_FAILED 102\r
+#define COM_E_INVALID_SIGNAL_CONFIGURATION 103\r
+#define COM_INVALID_PDU_ID 104\r
+#define COM_ERROR_SIGNAL_IS_SIGNALGROUP 105\r
+\r
+#define COM_E_TOO_MANY_IPDU 106\r
+#define COM_E_TOO_MANY_SIGNAL 107\r
+#define COM_E_TOO_MANY_GROUPSIGNAL 108\r
+\r
+#define CPU_ENDIANESS BIG_ENDIAN\r
+\r
+/*\r
+ * ComGeneral pre-compile time configuration parameters.
+ */\r
+#define ComConfigurationTimeBase\r
+#define ComConfigurationUseDet\r
+#define ComVersionInfoApi\r
+\r
+\r
+\r
+\r
+\r
+#endif /*COM_CFG_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include "Com_PbCfg.h"\r
+#include "Com_RunTest.h"\r
+\r
+#include "stdlib.h"\r
+\r
+\r
+/*\r
+ * PCAN Configuration
+ */\r
+ComSignal_type PCAN_ComSignal[] = {\r
+ // Signals for PCAN_RX_FRAME_1\r
+ {\r
+ .ComBitPosition = 0,\r
+ .ComBitSize = 8,\r
+ //.ComDataInvalidAction (NOT IMPLEMENTED)\r
+ .ComErrorNotification = NULL,\r
+ .ComFirstTimeoutFactor = 0,\r
+ .ComHandleId = 0,\r
+ //.ComInvalidNotification (NOT IMPLEMENTED)\r
+ .ComNotification = NULL,\r
+ //.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
+ //.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
+ .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalInitValue = 0x0,\r
+ .ComSignalLength = 0,\r
+ .ComSignalType = UINT8,\r
+ .ComTimeoutFactor = 0,\r
+ .ComTimeoutNotification = NULL,\r
+ .ComTransferProperty = TRIGGERED,\r
+ .ComUpdateBitPosition = 0,\r
+ .ComSignalEcoreUseUpdateBit = 0,\r
+ .ComFilter = {\r
+ .ComFilterAlgorithm = ALWAYS,\r
+ .ComFilterMask = 0,\r
+ .ComFilterMax = 0,\r
+ .ComFilterMin = 0,\r
+ .ComFilterOffset = 0,\r
+ .ComFilterPeriodFactor = 0,\r
+ .ComFilterX = 0\r
+ }\r
+ },\r
+ {\r
+ .ComBitPosition = 8,\r
+ .ComBitSize = 8,\r
+ //.ComDataInvalidAction (NOT IMPLEMENTED)\r
+ .ComErrorNotification = NULL,\r
+ .ComFirstTimeoutFactor = 0,\r
+ .ComHandleId = 1,\r
+ //.ComInvalidNotification (NOT IMPLEMENTED)\r
+ .ComNotification = NULL,\r
+ //.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
+ //.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
+ .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalInitValue = 0x00,\r
+ .ComSignalLength = 0,\r
+ .ComSignalType = UINT8,\r
+ .ComTimeoutFactor = 0,\r
+ .ComTimeoutNotification = NULL,\r
+ .ComTransferProperty = TRIGGERED,\r
+ .ComUpdateBitPosition = 0,\r
+ .ComSignalEcoreUseUpdateBit = 0,\r
+ .ComFilter = {\r
+ .ComFilterAlgorithm = ALWAYS,\r
+ .ComFilterMask = 0,\r
+ .ComFilterMax = 0,\r
+ .ComFilterMin = 0,\r
+ .ComFilterOffset = 0,\r
+ .ComFilterPeriodFactor = 0,\r
+ .ComFilterX = 0\r
+ }\r
+ },\r
+ {\r
+ .ComBitPosition = 16,\r
+ .ComBitSize = 1,\r
+ //.ComDataInvalidAction (NOT IMPLEMENTED)\r
+ .ComErrorNotification = NULL,\r
+ .ComFirstTimeoutFactor = 0,\r
+ .ComHandleId = 2,\r
+ //.ComInvalidNotification (NOT IMPLEMENTED)\r
+ .ComNotification = NULL,\r
+ //.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
+ //.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
+ .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalInitValue = 0x00,\r
+ .ComSignalLength = 0,\r
+ .ComSignalType = UINT8,\r
+ .ComTimeoutFactor = 0,\r
+ .ComTimeoutNotification = NULL,\r
+ .ComTransferProperty = TRIGGERED,\r
+ .ComUpdateBitPosition = 0,\r
+ .ComSignalEcoreUseUpdateBit = 0,\r
+ .ComFilter = {\r
+ .ComFilterAlgorithm = ALWAYS,\r
+ .ComFilterMask = 0,\r
+ .ComFilterMax = 0,\r
+ .ComFilterMin = 0,\r
+ .ComFilterOffset = 0,\r
+ .ComFilterPeriodFactor = 0,\r
+ .ComFilterX = 0\r
+ }\r
+ },\r
+ {\r
+ .ComBitPosition = 17,\r
+ .ComBitSize = 2,\r
+ //.ComDataInvalidAction (NOT IMPLEMENTED)\r
+ .ComErrorNotification = NULL,\r
+ .ComFirstTimeoutFactor = 0,\r
+ .ComHandleId = 3,\r
+ //.ComInvalidNotification (NOT IMPLEMENTED)\r
+ .ComNotification = NULL,\r
+ //.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
+ //.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
+ .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalInitValue = 0x00,\r
+ .ComSignalLength = 0,\r
+ .ComSignalType = UINT8,\r
+ .ComTimeoutFactor = 0,\r
+ .ComTimeoutNotification = NULL,\r
+ .ComTransferProperty = TRIGGERED,\r
+ .ComUpdateBitPosition = 0,\r
+ .ComSignalEcoreUseUpdateBit = 0,\r
+ .ComFilter = {\r
+ .ComFilterAlgorithm = ALWAYS,\r
+ .ComFilterMask = 0,\r
+ .ComFilterMax = 0,\r
+ .ComFilterMin = 0,\r
+ .ComFilterOffset = 0,\r
+ .ComFilterPeriodFactor = 0,\r
+ .ComFilterX = 0\r
+ }\r
+ },\r
+\r
+\r
+\r
+ // Signals for PCAN_RX_FRAME_2\r
+ {\r
+ .ComBitPosition = 0,\r
+ .ComBitSize = 8,\r
+ //.ComDataInvalidAction (NOT IMPLEMENTED)\r
+ .ComErrorNotification = NULL,\r
+ .ComFirstTimeoutFactor = 0,\r
+ .ComHandleId = 4,\r
+ //.ComInvalidNotification (NOT IMPLEMENTED)\r
+ .ComNotification = NULL,\r
+ //.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
+ //.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
+ .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalInitValue = 0x0,\r
+ .ComSignalLength = 0,\r
+ .ComSignalType = UINT8,\r
+ .ComTimeoutFactor = 0,\r
+ .ComTimeoutNotification = NULL,\r
+ .ComTransferProperty = TRIGGERED,\r
+ .ComUpdateBitPosition = 0,\r
+ .ComSignalEcoreUseUpdateBit = 0,\r
+ .ComFilter = {\r
+ .ComFilterAlgorithm = ALWAYS,\r
+ .ComFilterMask = 0,\r
+ .ComFilterMax = 0,\r
+ .ComFilterMin = 0,\r
+ .ComFilterOffset = 0,\r
+ .ComFilterPeriodFactor = 0,\r
+ .ComFilterX = 0\r
+ }\r
+ },\r
+ {\r
+ .ComBitPosition = 8,\r
+ .ComBitSize = 8,\r
+ //.ComDataInvalidAction (NOT IMPLEMENTED)\r
+ .ComErrorNotification = NULL,\r
+ .ComFirstTimeoutFactor = 0,\r
+ .ComHandleId = 5,\r
+ //.ComInvalidNotification (NOT IMPLEMENTED)\r
+ .ComNotification = NULL,\r
+ //.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
+ //.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
+ .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalInitValue = 0x00,\r
+ .ComSignalLength = 0,\r
+ .ComSignalType = UINT8,\r
+ .ComTimeoutFactor = 0,\r
+ .ComTimeoutNotification = NULL,\r
+ .ComTransferProperty = TRIGGERED,\r
+ .ComUpdateBitPosition = 0,\r
+ .ComSignalEcoreUseUpdateBit = 0,\r
+ .ComFilter = {\r
+ .ComFilterAlgorithm = ALWAYS,\r
+ .ComFilterMask = 0,\r
+ .ComFilterMax = 0,\r
+ .ComFilterMin = 0,\r
+ .ComFilterOffset = 0,\r
+ .ComFilterPeriodFactor = 0,\r
+ .ComFilterX = 0\r
+ }\r
+ },\r
+ {\r
+ .ComBitPosition = 16,\r
+ .ComBitSize = 1,\r
+ //.ComDataInvalidAction (NOT IMPLEMENTED)\r
+ .ComErrorNotification = NULL,\r
+ .ComFirstTimeoutFactor = 0,\r
+ .ComHandleId = 6,\r
+ //.ComInvalidNotification (NOT IMPLEMENTED)\r
+ .ComNotification = NULL,\r
+ //.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
+ //.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
+ .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalInitValue = 0x00,\r
+ .ComSignalLength = 0,\r
+ .ComSignalType = UINT8,\r
+ .ComTimeoutFactor = 0,\r
+ .ComTimeoutNotification = NULL,\r
+ .ComTransferProperty = TRIGGERED,\r
+ .ComUpdateBitPosition = 0,\r
+ .ComSignalEcoreUseUpdateBit = 0,\r
+ .ComFilter = {\r
+ .ComFilterAlgorithm = ALWAYS,\r
+ .ComFilterMask = 0,\r
+ .ComFilterMax = 0,\r
+ .ComFilterMin = 0,\r
+ .ComFilterOffset = 0,\r
+ .ComFilterPeriodFactor = 0,\r
+ .ComFilterX = 0\r
+ }\r
+ },\r
+ {\r
+ .ComBitPosition = 17,\r
+ .ComBitSize = 2,\r
+ //.ComDataInvalidAction (NOT IMPLEMENTED)\r
+ .ComErrorNotification = NULL,\r
+ .ComFirstTimeoutFactor = 0,\r
+ .ComHandleId = 7,\r
+ //.ComInvalidNotification (NOT IMPLEMENTED)\r
+ .ComNotification = NULL,\r
+ //.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
+ //.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
+ .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalInitValue = 0x00,\r
+ .ComSignalLength = 0,\r
+ .ComSignalType = UINT8,\r
+ .ComTimeoutFactor = 0,\r
+ .ComTimeoutNotification = NULL,\r
+ .ComTransferProperty = TRIGGERED,\r
+ .ComUpdateBitPosition = 0,\r
+ .ComSignalEcoreUseUpdateBit = 0,\r
+ .ComFilter = {\r
+ .ComFilterAlgorithm = ALWAYS,\r
+ .ComFilterMask = 0,\r
+ .ComFilterMax = 0,\r
+ .ComFilterMin = 0,\r
+ .ComFilterOffset = 0,\r
+ .ComFilterPeriodFactor = 0,\r
+ .ComFilterX = 0\r
+ }\r
+ },\r
+\r
+ // Signals for PCAN_TX_FRAME_1\r
+ {\r
+ .ComBitPosition = 0,\r
+ .ComBitSize = 8,\r
+ //.ComDataInvalidAction (NOT IMPLEMENTED)\r
+ .ComErrorNotification = NULL,\r
+ .ComFirstTimeoutFactor = 0,\r
+ .ComHandleId = 8,\r
+ //.ComInvalidNotification (NOT IMPLEMENTED)\r
+ .ComNotification = NULL,\r
+ //.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
+ //.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
+ .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalInitValue = 0x0,\r
+ .ComSignalLength = 0,\r
+ .ComSignalType = UINT8,\r
+ .ComTimeoutFactor = 0,\r
+ .ComTimeoutNotification = NULL,\r
+ .ComTransferProperty = TRIGGERED,\r
+ .ComUpdateBitPosition = 0,\r
+ .ComSignalEcoreUseUpdateBit = 0,\r
+ .ComFilter = {\r
+ .ComFilterAlgorithm = ALWAYS,\r
+ .ComFilterMask = 0,\r
+ .ComFilterMax = 0,\r
+ .ComFilterMin = 0,\r
+ .ComFilterOffset = 0,\r
+ .ComFilterPeriodFactor = 0,\r
+ .ComFilterX = 0\r
+ }\r
+ },\r
+ {\r
+ .ComBitPosition = 8,\r
+ .ComBitSize = 8,\r
+ //.ComDataInvalidAction (NOT IMPLEMENTED)\r
+ .ComErrorNotification = NULL,\r
+ .ComFirstTimeoutFactor = 0,\r
+ .ComHandleId = 9,\r
+ //.ComInvalidNotification (NOT IMPLEMENTED)\r
+ .ComNotification = NULL,\r
+ //.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
+ //.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
+ .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalInitValue = 0x00,\r
+ .ComSignalLength = 0,\r
+ .ComSignalType = UINT8,\r
+ .ComTimeoutFactor = 0,\r
+ .ComTimeoutNotification = NULL,\r
+ .ComTransferProperty = TRIGGERED,\r
+ .ComUpdateBitPosition = 0,\r
+ .ComSignalEcoreUseUpdateBit = 0,\r
+ .ComFilter = {\r
+ .ComFilterAlgorithm = ALWAYS,\r
+ .ComFilterMask = 0,\r
+ .ComFilterMax = 0,\r
+ .ComFilterMin = 0,\r
+ .ComFilterOffset = 0,\r
+ .ComFilterPeriodFactor = 0,\r
+ .ComFilterX = 0\r
+ }\r
+ },\r
+ {\r
+ .ComBitPosition = 16,\r
+ .ComBitSize = 1,\r
+ //.ComDataInvalidAction (NOT IMPLEMENTED)\r
+ .ComErrorNotification = NULL,\r
+ .ComFirstTimeoutFactor = 0,\r
+ .ComHandleId = 10,\r
+ //.ComInvalidNotification (NOT IMPLEMENTED)\r
+ .ComNotification = NULL,\r
+ //.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
+ //.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
+ .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalInitValue = 0x00,\r
+ .ComSignalLength = 0,\r
+ .ComSignalType = UINT8,\r
+ .ComTimeoutFactor = 0,\r
+ .ComTimeoutNotification = NULL,\r
+ .ComTransferProperty = TRIGGERED,\r
+ .ComUpdateBitPosition = 0,\r
+ .ComSignalEcoreUseUpdateBit = 0,\r
+ .ComFilter = {\r
+ .ComFilterAlgorithm = ALWAYS,\r
+ .ComFilterMask = 0,\r
+ .ComFilterMax = 0,\r
+ .ComFilterMin = 0,\r
+ .ComFilterOffset = 0,\r
+ .ComFilterPeriodFactor = 0,\r
+ .ComFilterX = 0\r
+ }\r
+ },\r
+ {\r
+ .ComBitPosition = 17,\r
+ .ComBitSize = 2,\r
+ //.ComDataInvalidAction (NOT IMPLEMENTED)\r
+ .ComErrorNotification = NULL,\r
+ .ComFirstTimeoutFactor = 0,\r
+ .ComHandleId = 11,\r
+ //.ComInvalidNotification (NOT IMPLEMENTED)\r
+ .ComNotification = NULL,\r
+ //.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
+ //.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
+ .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalInitValue = 0x00,\r
+ .ComSignalLength = 0,\r
+ .ComSignalType = UINT8,\r
+ .ComTimeoutFactor = 0,\r
+ .ComTimeoutNotification = NULL,\r
+ .ComTransferProperty = TRIGGERED,\r
+ .ComUpdateBitPosition = 0,\r
+ .ComSignalEcoreUseUpdateBit = 0,\r
+ .ComFilter = {\r
+ .ComFilterAlgorithm = ALWAYS,\r
+ .ComFilterMask = 0,\r
+ .ComFilterMax = 0,\r
+ .ComFilterMin = 0,\r
+ .ComFilterOffset = 0,\r
+ .ComFilterPeriodFactor = 0,\r
+ .ComFilterX = 0\r
+ }\r
+ },\r
+\r
+ // Signals for PCAN_TX_FRAME_2\r
+ {\r
+ .ComBitPosition = 0,\r
+ .ComBitSize = 8,\r
+ //.ComDataInvalidAction (NOT IMPLEMENTED)\r
+ .ComErrorNotification = NULL,\r
+ .ComFirstTimeoutFactor = 0,\r
+ .ComHandleId = 12,\r
+ //.ComInvalidNotification (NOT IMPLEMENTED)\r
+ .ComNotification = NULL,\r
+ //.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
+ //.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
+ .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalInitValue = 0x0,\r
+ .ComSignalLength = 0,\r
+ .ComSignalType = UINT8,\r
+ .ComTimeoutFactor = 0,\r
+ .ComTimeoutNotification = NULL,\r
+ .ComTransferProperty = TRIGGERED,\r
+ .ComUpdateBitPosition = 0,\r
+ .ComSignalEcoreUseUpdateBit = 0,\r
+ .ComFilter = {\r
+ .ComFilterAlgorithm = ALWAYS,\r
+ .ComFilterMask = 0,\r
+ .ComFilterMax = 0,\r
+ .ComFilterMin = 0,\r
+ .ComFilterOffset = 0,\r
+ .ComFilterPeriodFactor = 0,\r
+ .ComFilterX = 0\r
+ }\r
+ },\r
+ {\r
+ .ComBitPosition = 8,\r
+ .ComBitSize = 8,\r
+ //.ComDataInvalidAction (NOT IMPLEMENTED)\r
+ .ComErrorNotification = NULL,\r
+ .ComFirstTimeoutFactor = 0,\r
+ .ComHandleId = 13,\r
+ //.ComInvalidNotification (NOT IMPLEMENTED)\r
+ .ComNotification = NULL,\r
+ //.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
+ //.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
+ .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalInitValue = 0x00,\r
+ .ComSignalLength = 0,\r
+ .ComSignalType = UINT8,\r
+ .ComTimeoutFactor = 0,\r
+ .ComTimeoutNotification = NULL,\r
+ .ComTransferProperty = TRIGGERED,\r
+ .ComUpdateBitPosition = 0,\r
+ .ComSignalEcoreUseUpdateBit = 0,\r
+ .ComFilter = {\r
+ .ComFilterAlgorithm = ALWAYS,\r
+ .ComFilterMask = 0,\r
+ .ComFilterMax = 0,\r
+ .ComFilterMin = 0,\r
+ .ComFilterOffset = 0,\r
+ .ComFilterPeriodFactor = 0,\r
+ .ComFilterX = 0\r
+ }\r
+ },\r
+ {\r
+ .ComBitPosition = 16,\r
+ .ComBitSize = 1,\r
+ //.ComDataInvalidAction (NOT IMPLEMENTED)\r
+ .ComErrorNotification = NULL,\r
+ .ComFirstTimeoutFactor = 0,\r
+ .ComHandleId = 14,\r
+ //.ComInvalidNotification (NOT IMPLEMENTED)\r
+ .ComNotification = NULL,\r
+ //.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
+ //.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
+ .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalInitValue = 0x00,\r
+ .ComSignalLength = 0,\r
+ .ComSignalType = UINT8,\r
+ .ComTimeoutFactor = 0,\r
+ .ComTimeoutNotification = NULL,\r
+ .ComTransferProperty = TRIGGERED,\r
+ .ComUpdateBitPosition = 0,\r
+ .ComSignalEcoreUseUpdateBit = 0,\r
+ .ComFilter = {\r
+ .ComFilterAlgorithm = ALWAYS,\r
+ .ComFilterMask = 0,\r
+ .ComFilterMax = 0,\r
+ .ComFilterMin = 0,\r
+ .ComFilterOffset = 0,\r
+ .ComFilterPeriodFactor = 0,\r
+ .ComFilterX = 0\r
+ }\r
+ },\r
+ {\r
+ .ComBitPosition = 17,\r
+ .ComBitSize = 2,\r
+ //.ComDataInvalidAction (NOT IMPLEMENTED)\r
+ .ComErrorNotification = NULL,\r
+ .ComFirstTimeoutFactor = 0,\r
+ .ComHandleId = 15,\r
+ //.ComInvalidNotification (NOT IMPLEMENTED)\r
+ .ComNotification = NULL,\r
+ //.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
+ //.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
+ .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalInitValue = 0x00,\r
+ .ComSignalLength = 0,\r
+ .ComSignalType = UINT8,\r
+ .ComTimeoutFactor = 0,\r
+ .ComTimeoutNotification = NULL,\r
+ .ComTransferProperty = TRIGGERED,\r
+ .ComUpdateBitPosition = 0,\r
+ .ComSignalEcoreUseUpdateBit = 0,\r
+ .ComFilter = {\r
+ .ComFilterAlgorithm = ALWAYS,\r
+ .ComFilterMask = 0,\r
+ .ComFilterMax = 0,\r
+ .ComFilterMin = 0,\r
+ .ComFilterOffset = 0,\r
+ .ComFilterPeriodFactor = 0,\r
+ .ComFilterX = 0\r
+ }\r
+ },\r
+ {\r
+ .ComEcoreEOL = 1\r
+ }\r
+};\r
+\r
+// Definitions of IPDU groups.\r
+ComIPduGroup_type PCAN_ComIPduGroup[] = {\r
+ {\r
+ .ComIPduGroupHandleId = 0\r
+ },\r
+ {\r
+ .ComEcoreEOL = 1\r
+ }\r
+};\r
+\r
+ComIPdu_type PCAN_ComIPdu[] = {\r
+ // This CAN-message is used to update properties of the engine.\r
+ {\r
+ .ComIPduCallout = NULL,\r
+ .ComIPduRxHandleId = PCAN_RX_FRAME_1,\r
+ .ComIPduSignalProcessing = IMMEDIATE,\r
+ .ComIPduSize = 8,\r
+ .ComIPduDirection = RECEIVE,\r
+ .ComIPduGroupRef = &PCAN_ComIPduGroup[0],\r
+ //.ComIPduSignalGroupRef (NOT IMPLEMENTED)\r
+ //./PduIdRef (NOT IMPLEMENTED)\r
+ .ComTxIPdu = {NULL},\r
+ .ComIPduSignalRef = {\r
+ &PCAN_ComSignal[0],\r
+ &PCAN_ComSignal[1],\r
+ &PCAN_ComSignal[2],\r
+ &PCAN_ComSignal[3],\r
+ NULL,\r
+ },\r
+ },\r
+ // This CAN-message is used to update properties of the engine.\r
+ {\r
+ .ComIPduCallout = NULL,\r
+ .ComIPduRxHandleId = PCAN_RX_FRAME_2,\r
+ .ComIPduSignalProcessing = IMMEDIATE,\r
+ .ComIPduSize = 8,\r
+ .ComIPduDirection = RECEIVE,\r
+ .ComIPduGroupRef = &PCAN_ComIPduGroup[0],\r
+ //.ComIPduSignalGroupRef (NOT IMPLEMENTED)\r
+ //./PduIdRef (NOT IMPLEMENTED)\r
+ .ComTxIPdu = {NULL},\r
+ .ComIPduSignalRef = {\r
+ &PCAN_ComSignal[4],\r
+ &PCAN_ComSignal[5],\r
+ &PCAN_ComSignal[6],\r
+ &PCAN_ComSignal[7],\r
+ NULL,\r
+ },\r
+ },\r
+ {\r
+ .ComIPduCallout = NULL,\r
+ .ComIPduRxHandleId = PCAN_TX_FRAME_1,\r
+ .ComIPduSignalProcessing = IMMEDIATE,\r
+ .ComIPduSize = 8,\r
+ .ComIPduDirection = SEND,\r
+ .ComIPduGroupRef = &PCAN_ComIPduGroup[0],\r
+ //.ComIPduSignalGroupRef (NOT IMPLEMENTED)\r
+ //./PduIdRef (NOT IMPLEMENTED)\r
+ .ComTxIPdu = {\r
+ .ComTxIPduMinimumDelayFactor = 0,\r
+ .ComTxIPduUnusedAreasDefault = 0x00,\r
+ .ComTxModeTrue = {\r
+ .ComTxModeMode = DIRECT,\r
+ .ComTxModeNumberOfRepetitions = 0,\r
+ .ComTxModeRepetitionPeriodFactor = 0,\r
+ .ComTxModeTimeOffsetFactor = 0,\r
+ .ComTxModeTimePeriodFactor = 0,\r
+ },\r
+ //.ComTxModeFalse (NOT IMPLEMENTED)\r
+ },\r
+ .ComIPduSignalRef = {\r
+ &PCAN_ComSignal[8],\r
+ &PCAN_ComSignal[9],\r
+ &PCAN_ComSignal[10],\r
+ &PCAN_ComSignal[11],\r
+ NULL,\r
+ },\r
+ },\r
+ {\r
+ .ComIPduCallout = NULL,\r
+ .ComIPduRxHandleId = PCAN_TX_FRAME_2,\r
+ .ComIPduSignalProcessing = IMMEDIATE,\r
+ .ComIPduSize = 8,\r
+ .ComIPduDirection = SEND,\r
+ .ComIPduGroupRef = &PCAN_ComIPduGroup[0],\r
+ //.ComIPduSignalGroupRef (NOT IMPLEMENTED)\r
+ //./PduIdRef (NOT IMPLEMENTED)\r
+ .ComTxIPdu = {\r
+ .ComTxIPduMinimumDelayFactor = 0,\r
+ .ComTxIPduUnusedAreasDefault = 0x00,\r
+ .ComTxModeTrue = {\r
+ .ComTxModeMode = DIRECT,\r
+ .ComTxModeNumberOfRepetitions = 0,\r
+ .ComTxModeRepetitionPeriodFactor = 0,\r
+ .ComTxModeTimeOffsetFactor = 0,\r
+ .ComTxModeTimePeriodFactor = 0,\r
+ },\r
+ //.ComTxModeFalse (NOT IMPLEMENTED)\r
+ },\r
+ .ComIPduSignalRef = {\r
+ &PCAN_ComSignal[12],\r
+ &PCAN_ComSignal[13],\r
+ &PCAN_ComSignal[14],\r
+ &PCAN_ComSignal[15],\r
+ NULL,\r
+ },\r
+ },\r
+\r
+ {\r
+ .ComEcoreEOL = 1\r
+ }\r
+};\r
+\r
+Com_ConfigType PCAN_ComConfig = {\r
+ .ComConfigurationId = 2,\r
+ .ComIPdu = PCAN_ComIPdu,\r
+ .ComIPduGroup = PCAN_ComIPduGroup,\r
+ .ComSignal = PCAN_ComSignal,\r
+};\r
+\r
+\r
+\r
+\r
+\r
+\r
+/*\r
+ * Target test configuration
+ */\r
+ComGroupSignal_type HardwareTest_ComGroupSignal[] = {\r
+ {\r
+ .ComBitPosition = 32,\r
+ .ComBitSize = 8,\r
+ .ComHandleId = 0,\r
+ .ComSignalType = UINT8,\r
+ },\r
+ {\r
+ .ComBitPosition = 40,\r
+ .ComBitSize = 2,\r
+ .ComHandleId = 1,\r
+ .ComSignalType = UINT8,\r
+ }\r
+};\r
+\r
+ComSignal_type HardwareTest_ComSignal[] = {\r
+ {\r
+ .ComBitPosition = 0,\r
+ .ComBitSize = 16,\r
+ //.ComDataInvalidAction (NOT IMPLEMENTED)\r
+ .ComErrorNotification = NULL,\r
+ .ComFirstTimeoutFactor = 0,\r
+ .ComHandleId = 0,\r
+ //.ComInvalidNotification (NOT IMPLEMENTED)\r
+ .ComNotification = NULL,\r
+ //.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
+ //.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
+ .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalInitValue = 0xFF,\r
+ .ComSignalLength = 0,\r
+ .ComSignalType = UINT16,\r
+ .ComTimeoutFactor = 0,\r
+ .ComTimeoutNotification = NULL,\r
+ .ComTransferProperty = TRIGGERED,\r
+ .ComUpdateBitPosition = 16,\r
+ .ComSignalEcoreUseUpdateBit = 1,\r
+ .ComFilter = {\r
+ .ComFilterAlgorithm = ALWAYS,\r
+ .ComFilterMask = 0,\r
+ .ComFilterMax = 0,\r
+ .ComFilterMin = 0,\r
+ .ComFilterOffset = 0,\r
+ .ComFilterPeriodFactor = 0,\r
+ .ComFilterX = 0\r
+ }\r
+ },\r
+ {\r
+ .ComBitPosition = 0,\r
+ .ComBitSize = 16,\r
+ //.ComDataInvalidAction (NOT IMPLEMENTED)\r
+ .ComErrorNotification = NULL,\r
+ .ComFirstTimeoutFactor = 0,\r
+ .ComHandleId = 1,\r
+ //.ComInvalidNotification (NOT IMPLEMENTED)\r
+ .ComNotification = RTE_EngineChangeSpeed,\r
+ //.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
+ //.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
+ .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalInitValue = 0x00,\r
+ .ComSignalLength = 0,\r
+ .ComSignalType = UINT16,\r
+ .ComTimeoutFactor = 0,\r
+ .ComTimeoutNotification = NULL,\r
+ .ComTransferProperty = TRIGGERED,\r
+ .ComUpdateBitPosition = 16,\r
+ .ComSignalEcoreUseUpdateBit = 1,\r
+ .ComFilter = {\r
+ .ComFilterAlgorithm = ALWAYS,\r
+ .ComFilterMask = 0,\r
+ .ComFilterMax = 0,\r
+ .ComFilterMin = 0,\r
+ .ComFilterOffset = 0,\r
+ .ComFilterPeriodFactor = 0,\r
+ .ComFilterX = 0\r
+ }\r
+ },\r
+\r
+ // This is a signal group\r
+ {\r
+ //.ComBitPosition = 0,\r
+ //.ComBitSize = 16,\r
+ //.ComDataInvalidAction (NOT IMPLEMENTED)\r
+ //.ComErrorNotification = NULL,\r
+ //.ComFirstTimeoutFactor = 0,\r
+ .ComHandleId = 2,\r
+ //.ComInvalidNotification (NOT IMPLEMENTED)\r
+ .ComNotification = RTE_SIL2MESSAGE,\r
+ //.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
+ //.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
+ //.ComSignalEndianess = BIG_ENDIAN,\r
+ //.ComSignalInitValue = 0xFF,\r
+ //.ComSignalLength = 0,\r
+ //.ComSignalType = UINT16,\r
+ //.ComTimeoutFactor = 0,\r
+ //.ComTimeoutNotification = NULL,\r
+ //.ComTransferProperty = TRIGGERED,\r
+ .ComUpdateBitPosition = 42,\r
+ .ComSignalEcoreUseUpdateBit = 1,\r
+ .ComEcoreIsSignalGroup = 1,\r
+ .ComGroupSignal = {\r
+ &HardwareTest_ComGroupSignal[0],\r
+ &HardwareTest_ComGroupSignal[1],\r
+ },\r
+ /*.ComFilter = {\r
+ .ComFilterAlgorithm = ALWAYS,\r
+ .ComFilterMask = 0,\r
+ .ComFilterMax = 0,\r
+ .ComFilterMin = 0,\r
+ .ComFilterOffset = 0,\r
+ .ComFilterPeriodFactor = 0,\r
+ .ComFilterX = 0\r
+ }*/\r
+ },\r
+ {\r
+ .ComEcoreEOL = 1\r
+ }\r
+};\r
+\r
+// Definitions of IPDU groups.\r
+ComIPduGroup_type HardwareTest_ComIPduGroup[] = {\r
+ {\r
+ .ComIPduGroupHandleId = 0\r
+ },\r
+ {\r
+ .ComIPduGroupHandleId = 1\r
+ },\r
+ {\r
+ .ComIPduGroupHandleId = 2\r
+ },\r
+ {\r
+ .ComEcoreEOL = 1\r
+ }\r
+};\r
+\r
+ComIPdu_type HardwareTest_ComIPdu[] = {\r
+ {\r
+ .ComIPduCallout = NULL,\r
+ .ComIPduRxHandleId = PDU_MSG_HARDWARE_TEST_ENGINE_STATUS,\r
+ .ComIPduSignalProcessing = IMMEDIATE,\r
+ .ComIPduSize = 8,\r
+ .ComIPduDirection = SEND,\r
+ .ComIPduGroupRef = &HardwareTest_ComIPduGroup[0],\r
+ //.ComIPduSignalGroupRef (NOT IMPLEMENTED)\r
+ //./PduIdRef (NOT IMPLEMENTED)\r
+ .ComTxIPdu = {\r
+ .ComTxIPduMinimumDelayFactor = 500,\r
+ .ComTxIPduUnusedAreasDefault = 0x00,\r
+ .ComTxModeTrue = {\r
+ .ComTxModeMode = MIXED,\r
+ .ComTxModeNumberOfRepetitions = 0,\r
+ .ComTxModeRepetitionPeriodFactor = 0,\r
+ .ComTxModeTimeOffsetFactor = 400,\r
+ .ComTxModeTimePeriodFactor = 1000,\r
+ },\r
+ //.ComTxModeFalse (NOT IMPLEMENTED)\r
+ },\r
+ .ComIPduSignalRef = {\r
+ &HardwareTest_ComSignal[0],\r
+ NULL,\r
+ },\r
+ },\r
+\r
+ // This CAN-message is used to update properties of the engine.\r
+ {\r
+ .ComIPduCallout = NULL,\r
+ .ComIPduRxHandleId = PDU_MSG_HARDWARE_TEST_ENGINE_CONTROL,\r
+ .ComIPduSignalProcessing = IMMEDIATE,\r
+ .ComIPduSize = 8,\r
+ .ComIPduDirection = RECEIVE,\r
+ .ComIPduGroupRef = &HardwareTest_ComIPduGroup[0],\r
+ //.ComIPduSignalGroupRef (NOT IMPLEMENTED)\r
+ //./PduIdRef (NOT IMPLEMENTED)\r
+ .ComTxIPdu = {NULL},\r
+ .ComIPduSignalRef = {\r
+ &HardwareTest_ComSignal[1],\r
+ &HardwareTest_ComSignal[2],\r
+ NULL,\r
+ },\r
+ },\r
+\r
+\r
+ // This is a gateway mode message on the PDU router level.\r
+ {\r
+ .ComIPduCallout = NULL,\r
+ .ComIPduRxHandleId = PDU_MSG_HARDWARE_TEST_ROUTED_MSG,\r
+ .ComIPduSize = 0,\r
+ .ComIPduDirection = RECEIVE,\r
+ .ComIPduGroupRef = &HardwareTest_ComIPduGroup[0],\r
+ //.ComIPduSignalGroupRef (NOT IMPLEMENTED)\r
+ //./PduIdRef (NOT IMPLEMENTED)\r
+ .ComTxIPdu = {NULL},\r
+ .ComIPduSignalRef = {\r
+ NULL\r
+ },\r
+ },\r
+ {\r
+ .ComEcoreEOL = 1\r
+ }\r
+};\r
+\r
+Com_ConfigType HardwareTest_ComConfig = {\r
+ .ComConfigurationId = 2,\r
+ .ComIPdu = HardwareTest_ComIPdu,\r
+ .ComIPduGroup = HardwareTest_ComIPduGroup,\r
+ .ComSignal = HardwareTest_ComSignal,\r
+ .ComGroupSignal = HardwareTest_ComGroupSignal\r
+};\r
+\r
+\r
+\r
+// TEST CONFIGURATION\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef _COM_PBCFG_H\r
+#define _COM_PBCFG_H\r
+\r
+#include "Com_Types.h"\r
+\r
+extern Com_ConfigType PCAN_ComConfig;\r
+extern Com_ConfigType HardwareTest_ComConfig;\r
+\r
+#endif /*_COM_PBCFG_H*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*\r
+ * Development Error Tracer driver\r
+ *\r
+ * Specification: Autosar v2.0.1, Final\r
+ *\r
+ */\r
+#ifndef _DET_CFG_H_\r
+#define _DET_CFG_H_\r
+\r
+#define DET_ENABLE_CALLBACKS STD_ON // Enable to use callback on errors\r
+#define DET_USE_RAMLOG STD_ON // Enable to log DET errors to ramlog\r
+#define DET_WRAP_RAMLOG STD_ON // The ramlog wraps around when reaching the end\r
+#define DET_USE_STDERR STD_ON // Enable to get DET errors on stderr\r
+\r
+#define DET_DEINIT_API STD_ON // Enable/Disable the Det_DeInit function\r
+\r
+#define DET_RAMLOG_SIZE (32) // Number of entries in ramlog\r
+#define DET_NUMBER_OF_CALLBACKS (5) // Number of callbacks\r
+\r
+#endif /*_DET_CFG_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef DIO_CFG_H_\r
+#define DIO_CFG_H_\r
+\r
+#define DIO_VERSION_INFO_API STD_ON\r
+#define DIO_DEV_ERROR_DETECT STD_ON\r
+#define DIO_END_OF_LIST -1\r
+\r
+// MPC5516 physical\r
+typedef enum\r
+{\r
+ DIO_PORT_A = 0,\r
+ DIO_PORT_B,\r
+ DIO_PORT_C,\r
+ DIO_PORT_D,\r
+ DIO_PORT_E,\r
+ DIO_PORT_F,\r
+ DIO_PORT_G,\r
+ DIO_PORT_H,\r
+ DIO_PORT_J,\r
+ DIO_PORT_K\r
+} Dio_PortTypesType;\r
+\r
+// Pin Name GPIO(PCR)Num\r
+#define DIO_CHANNEL_A0 0\r
+#define DIO_CHANNEL_A1 1\r
+#define DIO_CHANNEL_A2 2\r
+#define DIO_CHANNEL_A3 3\r
+#define DIO_CHANNEL_A4 4\r
+#define DIO_CHANNEL_A5 5\r
+#define DIO_CHANNEL_A6 6\r
+#define DIO_CHANNEL_A7 7\r
+#define DIO_CHANNEL_A8 8\r
+#define DIO_CHANNEL_A9 9\r
+#define DIO_CHANNEL_A10 10\r
+#define DIO_CHANNEL_A11 11\r
+#define DIO_CHANNEL_A12 12\r
+#define DIO_CHANNEL_A13 13\r
+#define DIO_CHANNEL_A14 14\r
+#define DIO_CHANNEL_A15 15\r
+\r
+#define DIO_CHANNEL_B0 16\r
+#define DIO_CHANNEL_B1 17\r
+#define DIO_CHANNEL_B2 18\r
+#define DIO_CHANNEL_B3 19\r
+#define DIO_CHANNEL_B4 20\r
+#define DIO_CHANNEL_B5 21\r
+#define DIO_CHANNEL_B6 22\r
+#define DIO_CHANNEL_B7 23\r
+#define DIO_CHANNEL_B8 24\r
+#define DIO_CHANNEL_B9 25\r
+#define DIO_CHANNEL_B10 26\r
+#define DIO_CHANNEL_B11 27\r
+#define DIO_CHANNEL_B12 28\r
+#define DIO_CHANNEL_B13 29\r
+#define DIO_CHANNEL_B14 30\r
+#define DIO_CHANNEL_B15 31\r
+\r
+#define DIO_CHANNEL_C0 32\r
+#define DIO_CHANNEL_C1 33\r
+#define DIO_CHANNEL_C2 34\r
+#define DIO_CHANNEL_C3 35\r
+#define DIO_CHANNEL_C4 36\r
+#define DIO_CHANNEL_C5 37\r
+#define DIO_CHANNEL_C6 38\r
+#define DIO_CHANNEL_C7 39\r
+#define DIO_CHANNEL_C8 40\r
+#define DIO_CHANNEL_C9 41\r
+#define DIO_CHANNEL_C10 42\r
+#define DIO_CHANNEL_C11 43\r
+#define DIO_CHANNEL_C12 44\r
+#define DIO_CHANNEL_C13 45\r
+#define DIO_CHANNEL_C14 46\r
+#define DIO_CHANNEL_C15 47\r
+\r
+#define DIO_CHANNEL_D0 48\r
+#define DIO_CHANNEL_D1 49\r
+#define DIO_CHANNEL_D2 50\r
+#define DIO_CHANNEL_D3 51\r
+#define DIO_CHANNEL_D4 52\r
+#define DIO_CHANNEL_D5 53\r
+#define DIO_CHANNEL_D6 54\r
+#define DIO_CHANNEL_D7 55\r
+#define DIO_CHANNEL_D8 56\r
+#define DIO_CHANNEL_D9 57\r
+#define DIO_CHANNEL_D10 58\r
+#define DIO_CHANNEL_D11 59\r
+#define DIO_CHANNEL_D12 60\r
+#define DIO_CHANNEL_D13 61\r
+#define DIO_CHANNEL_D14 62\r
+#define DIO_CHANNEL_D15 63\r
+\r
+#define DIO_CHANNEL_E0 64\r
+#define DIO_CHANNEL_E1 65\r
+#define DIO_CHANNEL_E2 66\r
+#define DIO_CHANNEL_E3 67\r
+#define DIO_CHANNEL_E4 68\r
+#define DIO_CHANNEL_E5 69\r
+#define DIO_CHANNEL_E6 70\r
+#define DIO_CHANNEL_E7 71\r
+#define DIO_CHANNEL_E8 72\r
+#define DIO_CHANNEL_E9 73\r
+#define DIO_CHANNEL_E10 74\r
+#define DIO_CHANNEL_E11 75\r
+#define DIO_CHANNEL_E12 76\r
+#define DIO_CHANNEL_E13 77\r
+#define DIO_CHANNEL_E14 78\r
+#define DIO_CHANNEL_E15 79\r
+\r
+#define DIO_CHANNEL_F0 80\r
+#define DIO_CHANNEL_F1 81\r
+#define DIO_CHANNEL_F2 82\r
+#define DIO_CHANNEL_F3 83\r
+#define DIO_CHANNEL_F4 84\r
+#define DIO_CHANNEL_F5 85\r
+#define DIO_CHANNEL_F6 86\r
+#define DIO_CHANNEL_F7 87\r
+#define DIO_CHANNEL_F8 88\r
+#define DIO_CHANNEL_F9 89\r
+#define DIO_CHANNEL_F10 90\r
+#define DIO_CHANNEL_F11 91\r
+#define DIO_CHANNEL_F12 92\r
+#define DIO_CHANNEL_F13 93\r
+#define DIO_CHANNEL_F14 94\r
+#define DIO_CHANNEL_F15 95\r
+\r
+#define DIO_CHANNEL_G0 96\r
+#define DIO_CHANNEL_G1 97\r
+#define DIO_CHANNEL_G2 98\r
+#define DIO_CHANNEL_G3 99\r
+#define DIO_CHANNEL_G4 100\r
+#define DIO_CHANNEL_G5 101\r
+#define DIO_CHANNEL_G6 102\r
+#define DIO_CHANNEL_G7 103\r
+#define DIO_CHANNEL_G8 104\r
+#define DIO_CHANNEL_G9 105\r
+#define DIO_CHANNEL_G10 106\r
+#define DIO_CHANNEL_G11 107\r
+#define DIO_CHANNEL_G12 108\r
+#define DIO_CHANNEL_G13 109\r
+#define DIO_CHANNEL_G14 110\r
+#define DIO_CHANNEL_G15 111\r
+\r
+#define DIO_CHANNEL_H0 112\r
+#define DIO_CHANNEL_H1 113\r
+#define DIO_CHANNEL_H2 114\r
+#define DIO_CHANNEL_H3 115\r
+#define DIO_CHANNEL_H4 116\r
+#define DIO_CHANNEL_H5 117\r
+#define DIO_CHANNEL_H6 118\r
+#define DIO_CHANNEL_H7 119\r
+#define DIO_CHANNEL_H8 120\r
+#define DIO_CHANNEL_H9 121\r
+#define DIO_CHANNEL_H10 122\r
+#define DIO_CHANNEL_H11 123\r
+#define DIO_CHANNEL_H12 124\r
+#define DIO_CHANNEL_H13 125\r
+#define DIO_CHANNEL_H14 126\r
+#define DIO_CHANNEL_H15 127\r
+\r
+#define DIO_CHANNEL_J0 128\r
+#define DIO_CHANNEL_J1 129\r
+#define DIO_CHANNEL_J2 130\r
+#define DIO_CHANNEL_J3 131\r
+#define DIO_CHANNEL_J4 132\r
+#define DIO_CHANNEL_J5 133\r
+#define DIO_CHANNEL_J6 134\r
+#define DIO_CHANNEL_J7 135\r
+#define DIO_CHANNEL_J8 136\r
+#define DIO_CHANNEL_J9 137\r
+#define DIO_CHANNEL_J10 138\r
+#define DIO_CHANNEL_J11 139\r
+#define DIO_CHANNEL_J12 140\r
+#define DIO_CHANNEL_J13 141\r
+#define DIO_CHANNEL_J14 142\r
+#define DIO_CHANNEL_J15 143\r
+\r
+#define DIO_CHANNEL_K0 144\r
+#define DIO_CHANNEL_K1 145\r
+\r
+// Channels \r
+extern const Dio_ChannelType DioChannelConfigData[];\r
+#define CHANNEL_PTR (&DioChannelConfigData)\r
+\r
+// Port\r
+extern const Dio_PortType DioPortConfigData[];\r
+#define PORT_PTR (&DioPortConfigData)\r
+\r
+// Channel group\r
+extern const Dio_ChannelGroupType DioConfigData[];\r
+#define CHANNEL_GRP_PTR (&DioConfigData)\r
+\r
+// Mapping of logical ports to physical \r
+#ifdef CFG_BRD_MPC5516IT\r
+\r
+// Channels \r
+#define LEDS_LED4 (DIO_CHANNEL_D4)\r
+#define LEDS_LED5 (DIO_CHANNEL_D5)\r
+\r
+// Port\r
+#define LED_PORT (DIO_PORT_D)\r
+\r
+// Channel group\r
+#define LED_GRP_PTR (&DioConfigData[0])\r
+\r
+#else\r
+//\r
+// Channels\r
+// \r
+#define CONTROL_BUS_EN \r
+#define CONTROL_BUS_STB\r
+#define CONTROL_BUS_ERR\r
+#define CONTROL_BUS_S_PLUS_ST\r
+#define CONTROL_BUS_S_MINUS_ST\r
+#define CONTROL_BUS_S_PLUS_IN\r
+\r
+#define MULTILINK_SO_IN\r
+#define MULTILINK_SO_ST\r
+\r
+#define DATALINK_CANERR\r
+#define DATALINK_CANEN\r
+#define DATALINK_CANSTB\r
+\r
+#define RF_PWM\r
+#define RF_C1\r
+#define RF_C2\r
+\r
+#define IO_SOUND_EN\r
+#define IO_SOUND\r
+\r
+//\r
+// Channel groups\r
+//\r
+#define CONTROL_BUS (DioConfigData)\r
+#define MULTILINK_BUS (DioConfigData)\r
+#define RF (DioConfigData)\r
+#define IO (DioConfigData)\r
+\r
+//\r
+// Port mapping\r
+//\r
+\r
+// Hmm, We have no need for any.. we group with channel group instead \r
+#endif\r
+\r
+#endif /*DIO_CFG_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include "Dio.h"\r
+#include "Dio_Cfg.h"\r
+\r
+const Dio_ChannelType DioChannelConfigData[] =\r
+{ LEDS_LED4, LEDS_LED5, DIO_END_OF_LIST, };\r
+\r
+const Dio_PortType DioPortConfigData[] =\r
+{ LED_PORT, DIO_END_OF_LIST };\r
+\r
+const Dio_ChannelGroupType DioConfigData[] =\r
+{\r
+ { .port = LED_PORT, .offset = 4, .mask = 0x30, },\r
+ { .port = DIO_END_OF_LIST, .offset = DIO_END_OF_LIST, .mask = DIO_END_OF_LIST, },\r
+};\r
+\r
+\r
+\r
+uint32 Dio_GetPortConfigSize(void)\r
+{\r
+ return sizeof(DioConfigData);\r
+}\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include "Dma.h"\r
+\r
+const Dma_MuxConfigType DmaMuxConfig [DMA_NUMBER_OF_CHANNELS] =\r
+{\r
+ {\r
+ .DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_EQADC_FISR0_RFDF0\r
+ },\r
+ {\r
+ .DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_EQADC_FISR0_CFFF0\r
+ },\r
+ {\r
+ .DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_EQADC_FISR1_RFDF0\r
+ },\r
+ {\r
+ .DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_EQADC_FISR1_CFFF0\r
+ },\r
+ {\r
+ .DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_DSPI_A_SR_TFFF\r
+ },\r
+ {\r
+ .DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_DSPI_A_SR_RFRD\r
+ },\r
+ {\r
+ .DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_DSPI_B_SR_TFFF\r
+ },\r
+ {\r
+ .DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_DSPI_B_SR_RFRD\r
+ }\r
+};\r
+\r
+const Dma_ChannelConfigType DmaChannelConfig [DMA_NUMBER_OF_CHANNELS] =\r
+{\r
+ {\r
+ .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP0_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1\r
+ },\r
+ {\r
+ .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP0_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1\r
+ },\r
+ {\r
+ .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP1_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1\r
+ },\r
+ {\r
+ .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP1_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1\r
+ },\r
+ {\r
+ .DMA_CHANNEL_PRIORITY = DMA_DSPI_A_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1\r
+ },\r
+ {\r
+ .DMA_CHANNEL_PRIORITY = DMA_DSPI_A_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1\r
+ },\r
+ {\r
+ .DMA_CHANNEL_PRIORITY = DMA_DSPI_B_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1\r
+ },\r
+ {\r
+ .DMA_CHANNEL_PRIORITY = DMA_DSPI_B_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1\r
+ }\r
+};\r
+\r
+\r
+const Dma_ConfigType DmaConfig []=\r
+{\r
+ {DmaMuxConfig, DmaChannelConfig, DMA_FIXED_PRIORITY_ARBITRATION}\r
+};\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef DMA_CFG_H_\r
+#define DMA_CFG_H_\r
+\r
+typedef enum\r
+{\r
+ DMA_ADC_GROUP0_RESULT_CHANNEL,\r
+ DMA_ADC_GROUP0_COMMAND_CHANNEL,\r
+ DMA_ADC_GROUP1_RESULT_CHANNEL,\r
+ DMA_ADC_GROUP1_COMMAND_CHANNEL,\r
+ DMA_DSPI_A_COMMAND_CHANNEL,\r
+ DMA_DSPI_A_RESULT_CHANNEL,\r
+ DMA_DSPI_B_COMMAND_CHANNEL,\r
+ DMA_DSPI_B_RESULT_CHANNEL,\r
+ /*DMA_CHANNEL8,\r
+ DMA_CHANNEL9,\r
+ DMA_CHANNEL10,\r
+ DMA_CHANNEL11,\r
+ DMA_CHANNEL12,\r
+ DMA_CHANNEL13,\r
+ DMA_CHANNEL14,\r
+ DMA_CHANNEL15,*/\r
+ DMA_NUMBER_OF_CHANNELS\r
+} Dma_ChannelType;\r
+\r
+\r
+\r
+#endif /* DMA_CFG_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef ECUM_CFG_H_\r
+#define ECUM_CFG_H_\r
+\r
+#define ECUM_VERSION_INFO_API STD_ON\r
+#define ECUM_INCLUDE_NVRAM_MGR STD_OFF\r
+#define ECUM_DEV_ERROR_DETECT STD_ON\r
+\r
+#include "EcuM_Generated_Types.h"\r
+\r
+#endif /*ECUM_CFG_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef EEP_CFG_H_
+#define EEP_CFG_H_
+
+#include "Spi.h"
+
+/* EepGeneral */
+
+// Switches to activate or deactivate interrupt controlled job processing. true:
+// Interrupt controlled job processing enabled. false: Interrupt controlled job
+// processing disabled.
+#define EEP_USE_INTERRUPTS STD_OFF
+
+// Pre-processor switch to enable and disable development error detection.
+// true: Development error detection enabled. false: Development error
+// detection disabled.
+#define EEP_DEV_ERROR_DETECT STD_ON
+
+// Pre-processor switch to enable / disable the API to read out the modules
+// version information. true: Version info API enabled. false: Version info API
+// disabled.
+#define EEP_VERSION_INFO_API STD_ON
+
+// ndex of the driver, used by EA.
+#define EEP_DRIVER_INDEX 1
+
+// Switches to activate or deactivate write cycle reduction (EEPROM value is
+// read and compared before being overwritten). true: Write cycle reduction
+// enabled. false: Write cycle reduction disabled.
+#define EEP_WRITE_CYCLE_REDUCTION STD_OFF
+
+// Container for runtime configuration parameters of the EEPROM driver.
+// Implementation Type: Eep_ConfigType.
+
+/* EepPublishedInformation
+ *
+ * TODO
+ *
+ * 3.0 additions?
+ */
+
+// Total size of EEPROM in bytes. Implementation Type: Eep_LengthType.
+#define EEP_TOTAL_SIZE TBD
+
+// Size of smallest erasable EEPROM data unit in bytes.
+#define EEP_ERASE_UNIT_SIZE TBD
+
+// EepMinimumLengthType {EEP_MINIMUM_LENGTH_TYPE}
+// Minimum expected size of Eep_LengthType.
+#define EEP_MINIMUM_LENGTH_TYPE TBD
+
+// Minimum expected size of Eep_AddressType.
+#define EEP_MINIMUM_ADDRESS_TYPE TBD
+
+// Size of smallest writable EEPROM data unit in bytes.
+#define EEP_WRITE_UNIT_SIZE TBD
+
+// Value of an erased EEPROM cell.
+#define EEP_ERASE_VALUE 0
+
+// Number of erase cycles specified for the EEP device (usually given in the
+// device data sheet).
+#define EEP_SPECIFIED_ERASE_CYCLES TBD
+
+// Size of smallest readable EEPROM data unit in bytes.
+#define EEP_READ_UNIT_SIZE TBD
+
+// Time for writing one EEPROM data unit.
+#define EEP_WRITE_TIME TBD
+
+// Time for erasing one EEPROM data unit
+#define EEP_ERASE_TIME TBD
+
+// Specified maximum number of write cycles under worst case conditions of
+// specific EEPROM hardware (e.g. +90°C)
+#define EEP_ALLOWED_WRITE_CYCLES x
+
+
+typedef struct {
+
+ /* EEP094 */
+
+ Spi_SequenceType EepCmdSequence;
+ Spi_SequenceType EepCmd2Sequence;
+ Spi_SequenceType EepReadSequence;
+ Spi_SequenceType EepWriteSequence;
+
+ Spi_ChannelType EepAddrChannel;
+ Spi_ChannelType EepCmdChannel;
+ Spi_ChannelType EepDataChannel;
+ Spi_ChannelType EepWrenChannel;
+
+ // number of bytes read within one job processing cycle in normal mode.
+ Eep_LengthType EepNormalReadBlockSize;
+
+ // call cycle of the job processing function during write/erase operations. Unit: [s]
+ float EepJobCallCycle;
+
+ // This parameter is the used size of EEPROM device in bytes.
+ Eep_LengthType EepSize;
+
+ // This parameter is a reference to a callback function for positive job result
+ void (*Eep_JobEndNotification)();
+
+ // This parameter is the default EEPROM device mode after initialization.
+ MemIf_ModeType EepDefaultMode;
+
+ // This parameter is the number of bytes read within one job processing cycle in fast mode
+ Eep_LengthType EepFastReadBlockSize;
+
+ // Number of bytes written within one job processing cycle in normal mode.
+ Eep_LengthType EepNormalWriteBlockSize;
+
+ // This parameter is a reference to a callback function for negative job result
+ void (*Eep_JobErrorNotification)();
+
+ // This parameter is the number of bytes written within one job processing cycle in fast mode
+ Eep_LengthType EepFastWriteBlockSize;
+
+ // This parameter is the EEPROM device base address.
+ Eep_AddressType EepBaseAddress;
+} Eep_ConfigType;
+
+// This container is present for external EEPROM drivers only. Internal
+// EEPROM drivers do not use the parameter listed in this container, hence
+// its multiplicity is 0 for internal drivers.
+typedef struct {
+ // Reference to SPI sequence (required for external EEPROM drivers).
+ // TODO: hmmm....
+ uint32 SpiReference;
+} Eep_ExternalDriverType;
+
+extern const Eep_ConfigType EepConfigData[];
+
+#define EEP_DEFAULT_CONFIG EepConfigData[0]
+
+#endif /*EEP_CFG_H_*/
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+
+#include "Eep.h"
+#include "Spi.h"
+#include "Spi_Cfg.h"
+
+//#define USE_TRACE 1
+//#define USE_DEBUG 1
+#undef DEBUG_LVL
+#define DEBUG_LVL DEBUG_LOW
+#include "Trace.h"
+
+static void _JobEndNotify(){
+ DEBUG(DEBUG_LOW,"EEP JOB END NOTIFICATION\n");
+}
+static void _JobErrorNotify(){
+ DEBUG(DEBUG_LOW,"EEP JOB ERROR NOTIFICATION\n");
+}
+
+const Eep_ConfigType EepConfigData[] = {
+ {
+
+ // READ and WRITE sequences and ID's defined in Spi_Cfg.h
+ .EepCmdSequence = SPI_SEQ_EEP_CMD,
+ .EepCmd2Sequence = SPI_SEQ_EEP_CMD2,
+ .EepReadSequence = SPI_SEQ_EEP_READ,
+ .EepWriteSequence = SPI_SEQ_EEP_WRITE,
+
+ // Channels used
+ .EepCmdChannel = SPI_CH_EEP_CMD,
+ .EepAddrChannel = SPI_CH_EEP_ADDR,
+ .EepWrenChannel = SPI_CH_EEP_WREN,
+ .EepDataChannel = SPI_CH_EEP_DATA,
+
+#if 0
+ .EepCmdJob = SPI_EEP_CMD_JOB,
+ .EepDataJob = SPI_EEP_DATA_JOB,
+
+ // Channels used
+ .EepCmdChannel = SPI_EEP_CMD_CH,
+ .EepAdrChannel = SPI_EEP_ADR_CH,
+ .EepDataChannel = SPI_EEP_DATA_CH,
+
+ // READ and WRITE sequences and ID's defined in Spi_Cfg.h
+ .EepReadSequence = SPI_EEP_SEQ_READ,
+ .EepWriteSequence = SPI_EEP_SEQ_WRITE,
+
+ // number of bytes read within one job processing cycle in normal mode.
+ .EepInitConfiguration = 1,
+#endif
+
+ // call cycle of the job processing function during write/erase operations. Unit: [s]
+ .EepJobCallCycle = 0.2,
+
+ // This parameter is the used size of EEPROM device in bytes.
+ .EepSize = 0x8000,
+
+ // This parameter is a reference to a callback function for positive job result
+ .Eep_JobEndNotification = &_JobEndNotify,
+
+ // This parameter is the default EEPROM device mode after initialization.
+ .EepDefaultMode = MEMIF_MODE_FAST,
+
+ // This parameter is the number of bytes read within one job processing cycle in fast mode
+ .EepFastReadBlockSize = 64,
+
+ .EepNormalReadBlockSize = 4,
+
+ // Number of bytes written within one job processing cycle in normal mode.
+ .EepNormalWriteBlockSize = 1,
+
+ // This parameter is a reference to a callback function for negative job result
+ .Eep_JobErrorNotification = &_JobErrorNotify,
+
+ // This parameter is the number of bytes written within one job processing cycle in fast mode
+ .EepFastWriteBlockSize = 64,
+
+ // This parameter is the EEPROM device base address.
+ .EepBaseAddress = 0
+ }
+};
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+
+#include "Eep.h"
+#include "Spi.h"
+#include "Spi_Cfg.h"
+
+//#define USE_TRACE 1
+//#define USE_DEBUG 1
+#undef DEBUG_LVL
+#define DEBUG_LVL DEBUG_LOW
+#include "Trace.h"
+
+static void _JobEndNotify(){
+ DEBUG(DEBUG_LOW,"E2 JOB END NOTIFICATION\n");
+}
+static void _JobErrorNotify(){
+ DEBUG(DEBUG_LOW,"E2 JOB ERROR NOTIFICATION\n");
+}
+
+const Eep_ConfigType EepromConfigData[] = {
+ {
+ // READ and WRITE sequences and ID's defined in Spi_Cfg.h
+ .EepCmdSequence = SPI_SEQ_E2_CMD,
+ .EepCmd2Sequence = SPI_SEQ_E2_CMD2,
+ .EepReadSequence = SPI_SEQ_E2_READ,
+ .EepWriteSequence = SPI_SEQ_E2_WRITE,
+
+ // Channels used
+ .EepCmdChannel = SPI_CH_E2_CMD,
+ .EepAddrChannel = SPI_CH_E2_ADDR,
+ .EepWrenChannel = SPI_CH_E2_WREN,
+ .EepDataChannel = SPI_CH_E2_DATA,
+
+
+#if 0
+ // number of bytes read within one job processing cycle in normal mode.
+ .EepInitConfiguration = 1,
+#endif
+
+ // call cycle of the job processing function during write/erase operations. Unit: [s]
+ .EepJobCallCycle = 0.2,
+
+ // This parameter is the used size of EEPROM device in bytes.
+ .EepSize = 0x8000,
+
+ // This parameter is a reference to a callback function for positive job result
+ .Eep_JobEndNotification = &_JobEndNotify,
+
+ // This parameter is the default EEPROM device mode after initialization.
+ .EepDefaultMode = MEMIF_MODE_FAST,
+
+ // This parameter is the number of bytes read within one job processing cycle in fast mode
+ .EepFastReadBlockSize = 64,
+
+ .EepNormalReadBlockSize = 4,
+
+ // Number of bytes written within one job processing cycle in normal mode.
+ .EepNormalWriteBlockSize = 1,
+
+ // This parameter is a reference to a callback function for negative job result
+ .Eep_JobErrorNotification = &_JobErrorNotify,
+
+ // This parameter is the number of bytes written within one job processing cycle in fast mode
+ .EepFastWriteBlockSize = 64,
+
+ // This parameter is the EEPROM device base address.
+ .EepBaseAddress = 0
+ }
+};
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include "Fls.h"\r
+#include <stdlib.h>\r
+\r
+\r
+#define KB *1024\r
+\r
+\r
+const Fls_SectorType fls_evbSectorList[] = {\r
+ { // L0->L7\r
+ .FlsSectorStartaddress = (Fls_AddressType)0x00000000, // Start address of this sector\r
+ .FlsPageSize = (Fls_LengthType)8, // Read page size of 128 bits (4 words), (8 bytes)\r
+ .FlsSectorSize = (Fls_LengthType)(16 KB), // 16Kbyte\r
+ // Number of continuous sectors with the above characteristics.\r
+ .FlsNumberOfSectors = (uint32)8,// L0->L7 , 8 sectors\r
+ },\r
+ { // L8,L9\r
+ .FlsSectorStartaddress = (Fls_AddressType)0x00020000,\r
+ .FlsPageSize = (Fls_LengthType)8, // Read page size of 128 bits (4 words), (8 bytes)\r
+ .FlsSectorSize = (Fls_LengthType)(64 KB), // 64Kbyte\r
+ .FlsNumberOfSectors = (uint32)2,// L8,L9 , 2 sectors\r
+ },\r
+ { // M0->H7\r
+ .FlsSectorStartaddress = (Fls_AddressType)0x00040000,\r
+ .FlsPageSize = (Fls_LengthType)8, // Read page size of 128 bits (4 words), (8 bytes)\r
+ .FlsSectorSize = (Fls_LengthType)(128 KB), // 128Kbyte\r
+ .FlsNumberOfSectors = (uint32)6,// M0->H7\r
+ }\r
+};\r
+\r
+/*\r
+ * Block to partition map\r
+ */\r
+uint8 Fls_BlockToPartitionMap[] = { 1,1,1,1,2,2,2,2,3,3,4,4,5,5,6,6,7,7,8,8 };\r
+\r
+const Fls_ConfigType FlsConfigSet[]=\r
+{\r
+ {\r
+#if ( FLS_AC_LOAD_ON_JOB_START == STD_ON)\r
+ .FlsAcWrite = __FLS_ERASE_RAM__,\r
+ .FlsAcErase = __FLS_WRITE_RAM__,\r
+#else\r
+ .FlsAcWrite = NULL,\r
+ .FlsAcErase = NULL,\r
+#endif\r
+ .FlsJobEndNotification = NULL,\r
+ .FlsJobErrorNotification = NULL,\r
+\r
+ .FlsSectorList = &fls_evbSectorList[0],\r
+ .FlsSectorListSize = sizeof(fls_evbSectorList)/sizeof(Fls_SectorType),\r
+ .FlsBlockToPartitionMap = Fls_BlockToPartitionMap,\r
+ }\r
+};\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef FLS_CFG_H_
+#define FLS_CFG_H_
+
+#include "MemIf_Types.h"
+
+
+/* Indicate that we are building Post Build, NOT Pre-Compile */
+#define FLS_VARIANT_PB STD_ON
+
+/*
+ * Fls General container
+ */
+// The flash driver shall load the flash access code to RAM whenever an
+// erase or write job is started and unload (overwrite) it after that job has
+// been finished or canceled. true: Flash access code loaded on job start /
+// unloaded on job end or error. false: Flash access code not loaded to /
+// unloaded from RAM at all.
+#define FLS_AC_LOAD_ON_JOB_START STD_OFF
+
+// The flash memory start address (see also FLS118).
+// FLS169: This parameter defines the lower boundary for read / write /
+// erase and compare jobs.
+#define FLS_BASE_ADDRESS 0x00000000
+
+// Compile switch to enable and disable the Fls_Cancel function. true: API
+// supported / function provided. false: API not supported / function not pro-
+// vided
+#define FLS_CANCEL_API STD_OFF
+
+// Compile switch to enable and disable the Fls_Compare function. true: API
+// supported / function provided. false: API not supported / function not pro-
+// vided
+#define FLS_COMPARE_API STD_ON
+
+// Pre-processor switch for enabling the development error detection and
+// reporting (see FLS077).
+
+#define FLS_DEV_ERROR_DETECT STD_ON
+
+// Index of the driver, used by FEE.
+#define FLS_DRIVER_INDEX 100
+
+// Compile switch to enable and disable the Fls_GetJobResult function. true:
+// API supported / function provided. false: API not supported / function not
+// provided
+#define FLS_GET_JOB_RESULT_API STD_ON
+
+// Compile switch to enable and disable the Fls_GetStatus function. true: API
+// supported / function provided. false: API not supported / function not pro-
+// vided
+#define FLS_GET_STATUS_API STD_ON
+
+// Compile switch to enable and disable the Fls_SetMode function. true: API
+// supported / function provided. false: API not supported / function not pro-
+// vided
+#define FLS_SET_MODE_API STD_OFF
+
+// The total amount of flash memory in bytes (see also FLS118).
+// FLS170: This parameter in conjunction with FLS_BASE_ADDRESS
+// defines the upper boundary for read / write / erase and compare jobs
+#define FLS_TOTAL_SIZE 0x180000 // from addr 0x0000_0000 to 0x0018_0000
+#define FLS_READ_PAGE_SIZE 0x8 // Read page size of 128 bits (4 words) (8 bytes)
+
+
+// Job processing triggered by hardware interrupt. true: Job processing trig-
+// gered by interrupt (hardware controlled). false: Job processing not trig-
+// gered by interrupt (software controlled)
+
+// NOT supported by Freescale hardware
+#define FLS_USE_INTERRUPTS STD_OFF
+
+#define FLS_VERSION_INFO_API STD_ON
+
+
+#if ( FLS_AC_LOAD_ON_JOB_START == STD_ON )
+/* Sections that are provided by linker */
+extern void __FLS_ERASE_RAM__(void);
+extern void __FLS_WRITE_RAM__(void);
+extern void __FLS_ERASE_ROM__(void);
+extern void __FLS_WRITE_ROM__(void);
+extern char __FLS_SIZE__;
+#endif
+
+// Configuration description of a flashable sector
+typedef struct {
+ // Number of continuous sectors with the above characteristics.
+ Fls_LengthType FlsNumberOfSectors;
+
+ // Size of one page of this sector. Implementation Type: Fls_LengthType.
+ Fls_LengthType FlsPageSize;
+
+ // Size of this sector. Implementation Type: Fls_LengthTyp
+ Fls_LengthType FlsSectorSize;
+
+ // Start address of this sector
+ Fls_AddressType FlsSectorStartaddress;
+
+} Fls_SectorType;
+
+
+// Container for runtime configuration parameters of the flash driver. Imple-
+// mentation Type: Fls_ConfigType.
+typedef struct {
+ // Address offset in RAM to which the erase flash access code shall be
+ // loaded. Used as function pointer to access the erase flash access code.
+ void (*FlsAcErase)();
+
+ // Address offset in RAM to which the write flash access code shall be
+ // loaded. Used as function pointer to access the write flash access code.
+ void (*FlsAcWrite)();
+//#if 0
+// // Cycle time of calls of the flash driver's main function.
+// float FlsCallCycle;
+//#endif
+ // Mapped to the job end notification routine provided by some upper layer
+ // module, typically the Fee module.
+ void (*FlsJobEndNotification)();
+
+ // Mapped to the job error notification routine provided by some upper layer
+ // module, typically the Fee module.
+ void (*FlsJobErrorNotification)();
+
+ // The maximum number of bytes to read or compare in one cycle of the
+ // flash driver's job processing function in fast mode.
+ uint32 FlsMaxReadFastMode;
+
+ // The maximum number of bytes to read or compare in one cycle of the
+ // flash driver's job processing function in normal mode.
+ uint32 FlsMaxReadNormalMode;
+
+ // The maximum number of bytes to write in one cycle of the flash driver's job
+ // processing function in fast mode.
+ uint32 FlsMaxWriteFastMode;
+
+ // The maximum number of bytes to write in one cycle of the flash driver's job
+ // processing function in normal mode.
+ uint32 FlsMaxWriteNormalMode;
+
+ // Erase/write protection settings. Only relevant if supported by hardware.
+ uint32 FlsProtection;
+
+ // List of flash:able sectors and pages
+ const Fls_SectorType *FlsSectorList;
+
+ // Size of List of the FlsSectorList
+ const uint32 FlsSectorListSize;
+
+ uint8 *FlsBlockToPartitionMap;
+
+
+} Fls_ConfigType;
+
+
+extern const Fls_ConfigType FlsConfigSet[];
+
+#if 0
+/* N/A since PPC have PIC */
+#define FLS_AC_LOCATION_ERASE
+#define FLS_AC_LOCATION_WRITE
+/* N/A since we have internal flash */
+#define FLS_EXPECTED_HW_ID
+#endif
+
+#define FLS_AC_SIZE_ERASE (__FLS_WRITE_ROM__ - __FLS_ERASE_ROM__)
+#define FLS_AC_SIZE_WRITE (__FLS_END_ROM__ - __FLS_ERASE_ROM__)
+#define FLS_ERASED_VALUE 0xff
+
+#define FLS_SPECIFIED_ERASE_CYCLES 0 /* TODO */
+#define FLS_WRITE_TIME 0 /* TODO */
+
+
+#endif /*FLS_CFG_H_*/
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include "Fls.h"\r
+#include <stdlib.h>\r
+\r
+\r
+#define KB *1024\r
+\r
+\r
+const Fls_SectorType fls_SST25xx_SectorList[] = {\r
+ { // L0->L7\r
+ .FlsSectorStartaddress = (Fls_AddressType)0x00000000, // Start address of this sector\r
+ .FlsPageSize = (Fls_LengthType)1, // Read page size of 128 bits (4 words), (8 bytes)\r
+ .FlsSectorSize = (Fls_LengthType)(4 KB), // 16Kbyte\r
+ // Number of continuous sectors with the above characteristics.\r
+ .FlsNumberOfSectors = (uint32)512,// L0->L7 , 8 sectors\r
+ },\r
+};\r
+\r
+// Partitions start at 1\r
+// uint8 Fls_BlockToPartitionMap[] = { 1,1,1,1,2,2,2,2,3,3,4,4,5,5,6,6,7,7,8,8 };\r
+\r
+const Fls_ConfigType FlsSST25xxConfigSet[]=\r
+{\r
+ {\r
+#if 0\r
+#if ( FLS_AC_LOAD_ON_JOB_START == STD_ON)\r
+ .FlsAcWrite = __FLS_ERASE_RAM__,\r
+ .FlsAcErase = __FLS_WRITE_RAM__,\r
+#else\r
+ .FlsAcWrite = NULL,\r
+ .FlsAcErase = NULL,\r
+#endif\r
+#endif\r
+ .FlsMaxReadFastMode = 64,\r
+ .FlsMaxReadNormalMode = 1,\r
+ .FlsMaxWriteFastMode = 1,\r
+ .FlsMaxWriteNormalMode = 1,\r
+\r
+ .FlsJobEndNotification = NULL,\r
+ .FlsJobErrorNotification = NULL,\r
+\r
+ .FlsSectorList = &fls_SST25xx_SectorList[0],\r
+ .FlsSectorListSize = sizeof(fls_SST25xx_SectorList)/sizeof(Fls_SectorType),\r
+#if 0\r
+ .FlsBlockToPartitionMap = Fls_BlockToPartitionMap,\r
+#endif\r
+ }\r
+};\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+#ifndef FLS_SST25XX_CFG_H_\r
+#define FLS_SST25XX_CFG_H_\r
+\r
+// Take in the original types\r
+\r
+\r
+#include "Fls_Cfg.h"\r
+\r
+\r
+extern const Fls_ConfigType FlsSST25xxConfigSet[];\r
+/*\r
+ * Fls General container\r
+ */\r
+\r
+// The flash driver shall load the flash access code to RAM whenever an\r
+// erase or write job is started and unload (overwrite) it after that job has\r
+// been finished or canceled. true: Flash access code loaded on job start /\r
+// unloaded on job end or error. false: Flash access code not loaded to /\r
+// unloaded from RAM at all.\r
+#define FLS_SST25XX_AC_LOAD_ON_JOB_START STD_OFF\r
+\r
+// The flash memory start address (see also FLS118).\r
+// FLS169: This parameter defines the lower boundary for read / write /\r
+// erase and compare jobs.\r
+#define FLS_SST25XX_BASE_ADDRESS 0x00000000\r
+\r
+// Compile switch to enable and disable the Fls_Cancel function. true: API\r
+// supported / function provided. false: API not supported / function not pro-\r
+// vided\r
+#define FLS_SST25XX_CANCEL_API STD_OFF\r
+\r
+// Compile switch to enable and disable the Fls_Compare function. true: API\r
+// supported / function provided. false: API not supported / function not pro-\r
+// vided\r
+#define FLS_SST25XX_COMPARE_API STD_ON\r
+\r
+// Pre-processor switch for enabling the development error detection and\r
+// reporting (see FLS077).\r
+\r
+#define FLS_SST25XX_DEV_ERROR_DETECT STD_ON\r
+\r
+// Index of the driver, used by FEE.\r
+#define FLS_SST25XX_DRIVER_INDEX 100\r
+\r
+// Compile switch to enable and disable the Fls_GetJobResult function. true:\r
+// API supported / function provided. false: API not supported / function not\r
+// provided\r
+#define FLS_SST25XX_GET_JOB_RESULT_API STD_OFF\r
+\r
+// Compile switch to enable and disable the Fls_GetStatus function. true: API\r
+// supported / function provided. false: API not supported / function not pro-\r
+// vided\r
+#define FLS_SST25XX_GET_STATUS_API STD_ON\r
+\r
+// Compile switch to enable and disable the Fls_SetMode function. true: API\r
+// supported / function provided. false: API not supported / function not pro-\r
+// vided\r
+#define FLS_SST25XX_SET_MODE_API STD_ON\r
+\r
+// The total amount of flash memory in bytes (see also FLS118).\r
+// FLS170: This parameter in conjunction with FLS_SST25XX_BASE_ADDRESS\r
+// defines the upper boundary for read / write / erase and compare jobs\r
+#define FLS_SST25XX_TOTAL_SIZE 0x200000 // 16Mbit->2Mb, 0x0000_0000 to 0x0020_0000\r
+#if 0\r
+#define FLS_SST25XX_READ_PAGE_SIZE 0x8 // Read page size of 128 bits (4 words) (8 bytes)\r
+#endif\r
+\r
+// Job processing triggered by hardware interrupt.\r
+// true: Job processing triggered by interrupt (hardware controlled).\r
+// false: Job processing not triggered by interrupt (software controlled)\r
+\r
+// NOT supported by Freescale hardware\r
+#define FLS_SST25XX_USE_INTERRUPTS STD_OFF\r
+\r
+#define FLS_SST25XX_VERSION_INFO_API STD_ON\r
+\r
+\r
+#endif /* FLS_SST25XX_CFG_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+#include "Gpt.h"\r
+#include "Gpt_Cfg.h"\r
+#include <stdlib.h>\r
+\r
+#if defined(USE_KERNEL)\r
+extern void OsTick( void );\r
+#endif\r
+\r
+const Gpt_ConfigType GptConfigData[] =\r
+{\r
+ {\r
+ .GptChannelId = GPT_CHANNEL_PIT_0,\r
+ .GptChannelMode = GPT_MODE_CONTINUOUS,\r
+ .GptChannelClkSrc = 0,\r
+ .GptNotification = NULL,\r
+ .GptChannelPrescale = 0,\r
+ .GptEnableWakeup = TRUE,\r
+ },{\r
+ .GptChannelId = GPT_CHANNEL_PIT_1,\r
+ .GptChannelMode = GPT_MODE_CONTINUOUS,\r
+ .GptChannelClkSrc = 0,\r
+ .GptNotification = NULL,\r
+ .GptChannelPrescale = 0,\r
+ .GptEnableWakeup = FALSE,\r
+ },{\r
+ .GptChannelId = GPT_CHANNEL_PIT_2,\r
+ .GptChannelMode = GPT_MODE_ONESHOT,\r
+ .GptChannelClkSrc = 0,\r
+ .GptNotification = NULL,\r
+ .GptChannelPrescale = 0,\r
+ .GptEnableWakeup = FALSE,\r
+ },{\r
+ .GptChannelId = GPT_CHANNEL_PIT_3,\r
+ .GptChannelMode = GPT_MODE_CONTINUOUS,\r
+ .GptChannelClkSrc = 0,\r
+ .GptNotification = NULL,\r
+ .GptChannelPrescale = 0,\r
+ .GptEnableWakeup = FALSE,\r
+ },{\r
+ .GptChannelId = GPT_CHANNEL_PIT_4,\r
+ .GptChannelMode = GPT_MODE_ONESHOT,\r
+ .GptChannelClkSrc = 0,\r
+ .GptNotification = NULL,\r
+ .GptChannelPrescale = 0,\r
+ .GptEnableWakeup = FALSE,\r
+ },{\r
+ .GptChannelId = GPT_CHANNEL_PIT_5,\r
+ .GptChannelMode = GPT_MODE_CONTINUOUS,\r
+ .GptChannelClkSrc = 0,\r
+ .GptNotification = NULL,\r
+ .GptChannelPrescale = 0,\r
+ .GptEnableWakeup = FALSE,\r
+ },{\r
+ .GptChannelId = GPT_CHANNEL_PIT_6,\r
+ .GptChannelMode = GPT_MODE_ONESHOT,\r
+ .GptChannelClkSrc = 0,\r
+ .GptNotification = NULL,\r
+ .GptChannelPrescale = 0,\r
+ .GptEnableWakeup = FALSE,\r
+ },{\r
+ .GptChannelId = GPT_CHANNEL_PIT_7,\r
+ .GptChannelMode = GPT_MODE_CONTINUOUS,\r
+ .GptChannelClkSrc = 0,\r
+ .GptNotification = NULL,\r
+ .GptChannelPrescale = 0,\r
+ .GptEnableWakeup = FALSE,\r
+ },{\r
+ .GptChannelId = GPT_CHANNEL_PIT_8,\r
+ .GptChannelMode = GPT_MODE_ONESHOT,\r
+ .GptChannelClkSrc = 0,\r
+ .GptNotification = NULL,\r
+ .GptChannelPrescale = 0,\r
+ .GptEnableWakeup = FALSE,\r
+ },{\r
+ .GptChannelId = GPT_CHANNEL_DEC,\r
+ .GptChannelMode = GPT_MODE_CONTINUOUS,\r
+ .GptChannelClkSrc = 0,\r
+#if defined(USE_KERNEL)\r
+ .GptNotification = OsTick,\r
+#else\r
+ .GptNotification = NULL,\r
+#endif\r
+ .GptEnableWakeup = FALSE,\r
+ .GptChannelPrescale = 0,\r
+ },{\r
+ // Last channel in list\r
+ .GptChannelId = GPT_CHANNEL_ILL,\r
+ }\r
+};\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef GPT_CFG_H_\r
+#define GPT_CFG_H_\r
+#include "Std_Types.h"\r
+\r
+\r
+// Pre-compile only\r
+#define GPT_VARIANT_PC STD_OFF\r
+// Mix of pre-compile and post-build\r
+#define GPT_VARIANT_PB STD_ON\r
+\r
+//#define DEC_TEST\r
+//#define GPT_TEST\r
+\r
+/* Std PIT channels */\r
+#define GPT_CHANNEL_RTI 0\r
+#define GPT_CHANNEL_PIT_0 GPT_CHANNEL_RTI\r
+#define GPT_CHANNEL_PIT_1 1\r
+#define GPT_CHANNEL_PIT_2 2\r
+#define GPT_CHANNEL_PIT_3 3\r
+#define GPT_CHANNEL_PIT_4 4\r
+#define GPT_CHANNEL_PIT_5 5\r
+#define GPT_CHANNEL_PIT_6 6\r
+#define GPT_CHANNEL_PIT_7 7\r
+#define GPT_CHANNEL_PIT_8 8\r
+\r
+#define GPT_PIT_CNT (GPT_CHANNEL_PIT_8 + 1)\r
+\r
+/* Mcu channels */\r
+#define GPT_CHANNEL_DEC 9\r
+\r
+#define GPT_CHANNEL_CNT (GPT_CHANNEL_DEC+1)\r
+\r
+// Illegal channel\r
+#define GPT_CHANNEL_ILL 31\r
+\r
+\r
+#define GPT_DEV_ERROR_DETECT STD_ON\r
+// Enables/Disables wakeup source reporting\r
+#define GPT_REPORT_WAKEUP_SOURCE STD_OFF\r
+\r
+#define GPT_DEINIT_API STD_ON\r
+#define GPT_ENABLE_DISABLE_NOTIFICATION_API STD_ON\r
+#define GPT_TIME_REMAINING_API STD_ON\r
+#define GPT_TIME_ELAPSED_API STD_ON\r
+#define GPT_VERSION_INFO_API STD_ON\r
+// TODO: EcuM things missing to get this API working properly\r
+#define GPT_WAKEUP_FUNCTIONALITY_API STD_OFF\r
+\r
+\r
+// This container contains the channel-wide configuration (parameters) of the\r
+// GPT Driver\r
+typedef struct {\r
+ // GPT187: The GPT module specific clock input for the timer unit can\r
+ // statically be configured and allows to select different clock sources\r
+ // (external clock, internal GPT specific clock) per channel\r
+ uint32 GptChannelClkSrc;\r
+\r
+ // Channel Id of the GPT channel. This value will be assigned to the symbolic\r
+ // name derived of the GptChannelConfiguration container short name.\r
+ Gpt_ChannelType GptChannelId;\r
+\r
+ // Specifies the behaviour of the timerchannel after the timeout has expired\r
+ Gpt_ChannelMode GptChannelMode;\r
+\r
+ // Function pointer to callback function\r
+ void (*GptNotification)();\r
+\r
+ // GPT module specific prescaler factor per channel\r
+ uint32 GptChannelPrescale;\r
+\r
+ // GPT188: Enables wakeup capability of CPU for a channel when timeout\r
+ // period expires. This might be different to enabling the notification\r
+ // depending on hardware capabilities\r
+ boolean GptEnableWakeup;\r
+} Gpt_ConfigType;\r
+\r
+extern const Gpt_ConfigType GptConfigData[];\r
+\r
+#endif /*GPT_CFG_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef LINIF_CFG_H_\r
+#define LINIF_CFG_H_\r
+\r
+#include "Std_Types.h"\r
+#include "Lin_Cfg.h"\r
+\r
+// PDU definitions\r
+enum {\r
+ PDU_MSG_LIN_TX_1 = 0, // Changed by Mattias original value 101\r
+ PDU_MSG_LIN_RX_1,\r
+ PDU_MSG_LIN_RX_2,\r
+};\r
+\r
+/* Switches the Development Error Detection and Notification\r
+ON or OFF. */\r
+#define LINIF_DEV_ERROR_DETECT STD_ON\r
+\r
+/* States if multiple drivers are included in the LIN Interface or not. The\r
+ * reason for this parameter is to reduce the size of LIN Interface if multiple\r
+ * drivers are not used. */\r
+#define LINIF_MULTIPLE_DRIVER_SUPPORT STD_OFF\r
+\r
+/* States if the node configuration commands Assign NAD and Conditional\r
+ * Change NAD are supported. */\r
+#define LINIF_OPTIONAL_REQUEST_SUPPORTED STD_OFF\r
+\r
+/* States if the TP is included in the LIN Interface or not. The reason for this\r
+ * parameter is to reduce the size of LIN Interface if the TP is not used. */\r
+#define LINIF_TP_SUPPORTED STD_OFF\r
+\r
+/* Switches the LinIf_GetVersionInfo function ON or OFF. */\r
+#define LINIF_VERSION_INFO_API STD_ON\r
+\r
+typedef struct {\r
+ /* Switches the Development Error Detection and Notification\r
+ ON or OFF. */\r
+ boolean LinIfDevErrorDetect;\r
+ /* States if multiple drivers are included in the LIN Interface or not. The\r
+ * reason for this parameter is to reduce the size of LIN Interface if multiple\r
+ * drivers are not used. */\r
+ boolean LinIfMultipleDriversSupported;\r
+ /* States if the node configuration commands Assign NAD and Conditional\r
+ * Change NAD are supported. */\r
+ boolean LinIfNcOptionalRequestSupported;\r
+ /* States if the TP is included in the LIN Interface or not. The reason for this\r
+ * parameter is to reduce the size of LIN Interface if the TP is not used. */\r
+ boolean LinIfTpSupported;\r
+ /* Switches the LinIf_GetVersionInfo function ON or OFF. */\r
+ boolean LinIfVersionInfoApi;\r
+}LinIf_GeneralType;\r
+\r
+typedef enum {\r
+ CLASSIC,\r
+ ENHANCED,\r
+}LinIf_ChecksumType;\r
+\r
+typedef enum {\r
+ ASSIGN,\r
+ ASSIGN_NAD,\r
+ CONDITIONAL,\r
+ EVENT_TRIGGERED,\r
+ FREE,\r
+ MRF,\r
+ SPORADIC,\r
+ SRF,\r
+ UNASSIGN,\r
+ UNCONDITIONAL,\r
+}LinIf_FrameTypeType;\r
+\r
+typedef enum\r
+{\r
+ LinIfInternalPdu,\r
+ LinIfRxPdu,\r
+ LinIfSlaveToSlavePdu,\r
+ LinIfTxPdu,\r
+}LinIf_PduDirectionType;\r
+\r
+typedef struct {\r
+ LinIf_ChecksumType LinIfChecksumType;\r
+ char* LinIfFrameName;\r
+ uint8 LinIfFramePriority;\r
+ LinIf_FrameTypeType LinIfFrameType;\r
+ uint8 LinIfLength;\r
+ uint8 LinIfPid;\r
+ uint8 LinIfTxTargetPduId;\r
+ uint8 *LinIfFixedFrameSdu;\r
+ LinIf_PduDirectionType LinIfPduDirection;\r
+ //LinIf_SubstitutionFramesType *LinIfSubstitutionFrames;\r
+} LinIf_FrameType;\r
+\r
+typedef struct {\r
+ uint32 LinIfJitter;\r
+}LinIf_MasterType;\r
+\r
+typedef struct {\r
+ uint32 LinIfConfiguredNad;\r
+ uint32 LinIfFunctionId;\r
+ char* LinIfProtocolVersion;\r
+ uint32 LinIfResponseErrorBitPos;\r
+ uint32 LinIfSupplierId;\r
+ uint32 LinIfVariant;\r
+ uint32 LinIfResponseErrorEventRef;\r
+ uint16 LinIfResponseErrorFrameRef;\r
+}LinIf_SlaveType;\r
+\r
+typedef enum {\r
+ CONTINUE_AT_IT_POINT,\r
+ START_FROM_BEGINNING,\r
+}LinIf_ResumePositionType;\r
+\r
+typedef enum {\r
+ RUN_CONTINUOUS,\r
+ RUN_ONCE,\r
+}LinIfRunModeType;\r
+\r
+typedef struct {\r
+ uint16 LinIfDelay;\r
+ uint16 LinIfEntryIndex;\r
+ uint16 LinIfCollisionResolvingRef;\r
+ uint16 LinIfFrameRef;\r
+}LinIfEntryType;\r
+\r
+typedef struct {\r
+ LinIf_ResumePositionType LinIfResumePosition;\r
+ LinIfRunModeType LinIfRunMode;\r
+ uint8 LinIfSchedulePriority;\r
+ uint16 LinIfScheduleTableIndex;\r
+ char* LinIfScheduleTableName;\r
+ const LinIfEntryType *LinIfEntry;\r
+ uint16 LinIfNofEntries;\r
+}LinIf_ScheduleTableType;\r
+\r
+typedef uint8 LinIf_WakeUpSourceType;\r
+\r
+typedef char* LinIf_NodeComposition;\r
+\r
+typedef struct {\r
+ /* Internal ID for the channel on LIN Interface level. This parameter shall map\r
+ * the NetworkHandleType to the physical LIN channel.\r
+ * Implementation Type: NetworkHandleType */\r
+ uint8 LinIfChannelId;\r
+ /* Number of schedule requests the schedule table manager can handle for\r
+ * this channel. */\r
+ uint8 LinIfScheduleRequestQueueLength;\r
+ /* Reference to the used channel in Lin. Replaces LINIF_CHANNEL_INDEX */\r
+ const Lin_ChannelConfigType *LinIfChannelRef;\r
+\r
+ /* Generic container for all types of LIN frames. */\r
+ const LinIf_FrameType *LinIfFrame;\r
+ /* Each Master can only be connected to one physical channel.\r
+ * This could be compared to the Node parameter in a LDF file. */\r
+ LinIf_MasterType LinIfMaster;\r
+ /* Describes a schedule table. Each LinIfChannel may have several schedule tables.\r
+ * Each schedule table can only be connected to one channel. */\r
+ const LinIf_ScheduleTableType *LinIfScheduleTable;\r
+ /* The Node attributes of the Slaves are provided with these parameter. */\r
+ const LinIf_SlaveType *LinIfSlave;\r
+ /* This container contains the configuration (parameters) needed\r
+ to configure a wakeup capable channel */\r
+ const LinIf_WakeUpSourceType *LinIfWakeUpSource;\r
+} LinIf_ChannelType;\r
+\r
+typedef struct {\r
+ uint16 LinIfTimeBase;\r
+ const LinIf_ChannelType *LinIfChannel;\r
+}LinIf_GlobalConfigType;\r
+\r
+typedef struct {\r
+ const LinIf_GeneralType *LinIfGeneral;\r
+ const LinIf_GlobalConfigType *LinIfGlobalConfig;\r
+} LinIf_Type;\r
+\r
+extern const LinIfEntryType LinIfEntryCfg1[];\r
+extern const LinIf_ScheduleTableType LinIfScheduleTableCfg[];\r
+extern const LinIf_ChannelType LinIfChannelCfg[];\r
+extern const LinIf_GlobalConfigType LinIfGlobalConfig;\r
+\r
+// TODO not in Lin if spec\r
+extern const LinIf_FrameType LinIfFrameCfg[];\r
+\r
+#define LINIF_CONTROLLER_CNT 1\r
+#define LINIF_SCH_CNT 2\r
+\r
+#endif /*LINIF_CFG_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include "LinIf_Cfg.h"\r
+#include "Lin_Cfg.h"\r
+\r
+extern const Lin_ChannelConfigType LinChannelConfigData[];\r
+\r
+// Frames config\r
+const LinIf_FrameType LinIfFrameCfg[] = {\r
+ {\r
+ .LinIfChecksumType = ENHANCED,\r
+ .LinIfFramePriority = 0,//not used\r
+ .LinIfFrameType = UNCONDITIONAL,\r
+ .LinIfLength = 2,\r
+ .LinIfPid = 0xC1,\r
+ .LinIfTxTargetPduId = PDU_MSG_LIN_TX_1,\r
+ .LinIfFixedFrameSdu = 0,\r
+ .LinIfPduDirection = LinIfTxPdu,\r
+ },\r
+ {\r
+ .LinIfChecksumType = ENHANCED,\r
+ .LinIfFramePriority = 0,//not used\r
+ .LinIfFrameType = UNCONDITIONAL,\r
+ .LinIfLength = 3,\r
+ .LinIfPid = 0x42,\r
+ .LinIfTxTargetPduId = PDU_MSG_LIN_RX_1,\r
+ .LinIfFixedFrameSdu = 0,\r
+ .LinIfPduDirection = LinIfRxPdu,\r
+ },\r
+ {\r
+ .LinIfChecksumType = ENHANCED,\r
+ .LinIfFramePriority = 0,//not used\r
+ .LinIfFrameType = UNCONDITIONAL,\r
+ .LinIfLength = 6,\r
+ .LinIfPid = 0x03,\r
+ .LinIfTxTargetPduId = PDU_MSG_LIN_RX_2,\r
+ .LinIfFixedFrameSdu = 0,\r
+ .LinIfPduDirection = LinIfRxPdu,\r
+ },\r
+};\r
+\r
+// Schedule entry config.\r
+// Multiplicity 1..*\r
+const LinIfEntryType LinIfEntryCfg1[] = {\r
+ {\r
+ .LinIfDelay = 8,\r
+ .LinIfEntryIndex = 0,\r
+ .LinIfCollisionResolvingRef = 0,\r
+ .LinIfFrameRef = 0,\r
+ },\r
+ {\r
+ .LinIfDelay = 8,\r
+ .LinIfEntryIndex = 1,\r
+ .LinIfCollisionResolvingRef = 0,\r
+ .LinIfFrameRef = 1,\r
+ },\r
+ {\r
+ .LinIfDelay = 8,\r
+ .LinIfEntryIndex = 2,\r
+ .LinIfCollisionResolvingRef = 0,\r
+ .LinIfFrameRef = 2,\r
+ },\r
+ {\r
+ .LinIfDelay = 8,\r
+ .LinIfEntryIndex = 3,\r
+ .LinIfCollisionResolvingRef = 0,\r
+ .LinIfFrameRef = 1,\r
+ },\r
+};\r
+\r
+// Schedule table config.\r
+// Multiplicity 1..*\r
+const LinIf_ScheduleTableType LinIfScheduleTableCfg[] =\r
+{\r
+ {\r
+ .LinIfResumePosition = START_FROM_BEGINNING,\r
+ .LinIfRunMode = RUN_CONTINUOUS,\r
+ .LinIfSchedulePriority = 1,\r
+ .LinIfScheduleTableIndex = 0,\r
+ .LinIfScheduleTableName = "NULL_SCHEDULE", //Not used\r
+ .LinIfEntry = 0, // Null schedule\r
+ .LinIfNofEntries = 0,\r
+ },\r
+ {\r
+ .LinIfResumePosition = START_FROM_BEGINNING,\r
+ .LinIfRunMode = RUN_CONTINUOUS,\r
+ .LinIfSchedulePriority = 1,\r
+ .LinIfScheduleTableIndex = 1,\r
+ .LinIfScheduleTableName = "NORMAL", //Not used\r
+ .LinIfEntry = &LinIfEntryCfg1[0],\r
+ .LinIfNofEntries = 4,\r
+ },\r
+};\r
+\r
+// Channel config.\r
+// Multiplicity 1..*\r
+const LinIf_ChannelType LinIfChannelCfg[] =\r
+{\r
+ {\r
+ .LinIfChannelId = LIN_CTRL_B, // Should map against driver\r
+ .LinIfScheduleRequestQueueLength = 1,\r
+ .LinIfChannelRef = &LinChannelConfigData[0],\r
+ .LinIfFrame = 0, // TODO ???????\r
+ .LinIfMaster.LinIfJitter = 1,\r
+ .LinIfScheduleTable = &LinIfScheduleTableCfg[0],\r
+ .LinIfSlave = 0, // Master only\r
+ .LinIfWakeUpSource = 0, // Not needed\r
+ },\r
+};\r
+\r
+// Global config.\r
+const LinIf_GlobalConfigType LinIfGlobalConfig =\r
+{\r
+ .LinIfTimeBase = 8,\r
+ .LinIfChannel = &LinIfChannelCfg[0],\r
+};\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef LINSM_CFG_H_\r
+#define LINSM_CFG_H_\r
+\r
+#include "Std_Types.h"\r
+#include "LinIf_Cfg.h"\r
+\r
+// Own timeout configs in ticks\r
+#define LINSM_SCHEDULE_REQUEST_TIMEOUT 1\r
+#define LINSM_GOTO_SLEEP_TIMEOUT 2\r
+#define LINSM_WAKEUP_TIMEOUT 1\r
+\r
+/* Switches the Development Error Detection and Notification\r
+ON or OFF. */\r
+#define LINSM_DEV_ERROR_DETECT STD_ON\r
+\r
+/* Switches the LINSM_GetVersionInfo function ON or OFF. */\r
+#define LINSM_VERSION_INFO_API STD_ON\r
+\r
+typedef struct {\r
+ uint32 LinSMRxPduGroupRef;//ComIPduGroup\r
+ uint32 LinSMTxPduGroupRef;\r
+ const LinIf_ScheduleTableType *LinSMScheduleIndexRef;\r
+}LinSM_ScheduleType;\r
+\r
+typedef struct {\r
+ float LinSMConfirmationTimeout;\r
+ boolean LinSMSleepSupport;\r
+ uint16 LinSMChannelIndex;\r
+ const LinSM_ScheduleType *LinSMSchedule;\r
+}LinSM_ChannelType;\r
+\r
+extern const LinSM_ChannelType LinSMChannelType[];\r
+\r
+#endif /*LINSM_CFG_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include "LinSM_Cfg.h"\r
+#include "LinIf_Cfg.h"\r
+#include "Lin_Cfg.h"\r
+\r
+const LinSM_ScheduleType LinSMScheduleType =\r
+{\r
+ .LinSMRxPduGroupRef = 0, // TODO ref till COM\r
+ .LinSMTxPduGroupRef = 0, // TODO ref till COM\r
+ .LinSMScheduleIndexRef = &LinIfScheduleTableCfg[0],\r
+};\r
+\r
+const LinSM_ChannelType LinSMChannelType[] =\r
+{\r
+ {\r
+ .LinSMConfirmationTimeout = 20.0,\r
+ .LinSMSleepSupport = TRUE,\r
+ .LinSMChannelIndex = LIN_CTRL_B,\r
+ .LinSMSchedule = &LinSMScheduleType,\r
+ },\r
+};\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef LIN_CFG_H_\r
+#define LIN_CFG_H_\r
+\r
+#include "Std_Types.h"\r
+\r
+/* Switches the Development Error Detection and Notification\r
+ON or OFF. */\r
+#define LIN_DEV_ERROR_DETECT STD_ON\r
+\r
+/* Specifies the InstanceId of this module instance. If only one\r
+instance is present it shall have the Id 0. */\r
+#define LIN_INDEX 0\r
+\r
+/* Specifies the maximum number of loops for blocking function\r
+ * until a timeout is raised in short term wait loops */\r
+#define LIN_TIMEOUT_DURATION 10\r
+\r
+/* Switches the Lin_GetVersionInfo function ON or OFF. */\r
+#define LIN_VERSION_INFO_API STD_ON\r
+\r
+typedef enum {\r
+ LIN_CTRL_A = 0,\r
+ LIN_CTRL_B,\r
+ LIN_CTRL_C,\r
+ LIN_CTRL_D,\r
+ LIN_CTRL_E,\r
+ LIN_CTRL_F,\r
+ LIN_CTRL_G,\r
+ LIN_CTRL_H,\r
+ LIN_CONTROLLER_CNT\r
+}LinControllerIdType;\r
+\r
+typedef struct {\r
+ /* Switches the Development Error Detection and Notification\r
+ ON or OFF. */\r
+ boolean LinDevErrorDetect;\r
+ /* Specifies the InstanceId of this module instance. If only one\r
+ instance is present it shall have the Id 0. */\r
+ uint8 LinIndex;\r
+ /* Specifies the maximum number of loops for blocking function\r
+ * until a timeout is raised in short term wait loops */\r
+ uint16 LinTimeoutDuration;\r
+ /* Switches the Lin_GetVersionInfo function ON or OFF. */\r
+ boolean LinVersionInfoApi;\r
+}Lin_GeneralType;\r
+\r
+typedef struct {\r
+ /* Specifies the baud rate of the LIN channel */\r
+ uint16 LinChannelBaudRate;\r
+ /* Identifies the LIN channel.*/\r
+ uint8 LinChannelId;\r
+ /* Specifies if the LIN hardware channel supports wake up functionality */\r
+ boolean LinChannelWakeUpSupport;\r
+ /* This parameter contains a reference to the Wakeup Source\r
+ * for this controller as defined in the ECU State Manager.\r
+ * Implementation Type: reference to EcuM_WakeupSourceType */\r
+ uint32 LinChannelEcuMWakeUpSource;\r
+ /* Reference to the LIN clock source configuration, which is set\r
+ * in the MCU driver configuration.*/\r
+ uint32 LinClockRef;\r
+} Lin_ChannelConfigType;\r
+\r
+\r
+#endif /*LIN_CFG_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include "Mcu_Cfg.h"\r
+#include "Lin_Cfg.h"\r
+\r
+const Lin_ChannelConfigType LinChannelConfigData[] = {\r
+ {\r
+ .LinChannelBaudRate = 19200,\r
+ .LinChannelId = LIN_CTRL_B,\r
+ .LinChannelWakeUpSupport = TRUE,\r
+ .LinChannelEcuMWakeUpSource = 0, //not used\r
+ .LinClockRef = PERIPHERAL_CLOCK_ESCI_B,\r
+ },\r
+};\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include "Lin_Cfg.h"\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef MCU_CFG_C_\r
+#define MCU_CFG_C_\r
+\r
+#include "Mcu_Cfg.h"\r
+\r
+Mcu_RamSectorSettingConfigType Mcu_RamSectorSettingConfigData[] = {\r
+ {\r
+ // This parameter shall represent the Data pre-setting to be initialized\r
+ .McuRamDefaultValue = 0,\r
+\r
+ // This parameter shall represent the MCU RAM section base address\r
+ .McuRamSectionBaseAddress = 0,\r
+\r
+ // This parameter shall represent the MCU RAM Section size\r
+ .McuRamSectionSize = 0xFF,\r
+ }\r
+};\r
+\r
+Mcu_ClockSettingConfigType Mcu_ClockSettingConfigData[] =\r
+{\r
+ {\r
+ .McuClockReferencePoint = 8000000UL,\r
+ .PllEprediv = 1,\r
+ .PllEmfd = 104,\r
+ .PllErfd = 5,\r
+ },\r
+ {\r
+ .McuClockReferencePoint = 16000000UL,\r
+ .PllEprediv = 3,\r
+ .PllEmfd = 83,\r
+ .PllErfd = 5,\r
+ }\r
+};\r
+\r
+\r
+ const Mcu_ConfigType McuConfigData[] = {\r
+ {\r
+ // Enables/Disables clock failure notification. In case this feature is not supported\r
+ // by HW the setting should be disabled.\r
+ .McuClockSrcFailureNotification = 0,\r
+\r
+ // This parameter shall represent the number of Modes available for the\r
+ // MCU. calculationFormula = Number of configured McuModeSettingConf\r
+ .McuNumberOfMcuModes = 1, /* NOT USED */\r
+\r
+ // This parameter shall represent the number of RAM sectors available for\r
+ // the MCU. calculationFormula = Number of configured McuRamSectorSet-\r
+ // tingConf\r
+ .McuRamSectors = 1,\r
+\r
+ // This parameter shall represent the number of clock setting available for\r
+ // the MCU.\r
+ .McuClockSettings = MCU_NBR_OF_CLOCKS,\r
+\r
+ // Default clock frequency used\r
+ .McuDefaultClockSettings = MCU_CLOCKTYPE_EXT_REF_80MHZ,\r
+\r
+ // This parameter relates to the MCU specific reset configuration. This ap-\r
+ // plies to the function Mcu_PerformReset, which performs a microcontroller\r
+ // reset using the hardware feature of the microcontroller.\r
+ .McuResetSetting = 0, /* NOT USED */\r
+\r
+ // This container contains the configuration (parameters) for the\r
+ // Clock settings of the MCU. Please see MCU031 for more in-\r
+ // formation on the MCU clock settings.\r
+ .McuClockSettingConfig = &Mcu_ClockSettingConfigData[0],\r
+\r
+ // This container contains the configuration (parameters) for the\r
+ // Mode setting of the MCU. Please see MCU035 for more infor-\r
+ // mation on the MCU mode settings.\r
+ .McuModeSettingConfig = 0,\r
+\r
+ // This container contains the configuration (parameters) for the\r
+ // RAM Sector setting. Please see MCU030 for more information\r
+ // on RAM sec-tor settings.\r
+ .McuRamSectorSettingConfig = &Mcu_RamSectorSettingConfigData[0],\r
+ },\r
+};\r
+\r
+#endif /*MCU_CFG_C_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef MCU_CFG_H_\r
+#define MCU_CFG_H_\r
+\r
+#include "mpc55xx.h"\r
+\r
+#define MCU_DEV_ERROR_DETECT STD_ON\r
+// Preprocessor switch to enable / disable the use of the function\r
+// Mcu_PerformReset()\r
+#define MCU_PERFORM_RESET_API STD_ON\r
+\r
+#define MCU_VERSION_INFO_API STD_ON\r
+\r
+#include "Std_Types.h"\r
+\r
+/* FMPLL modes( atleast in 5553/5554 ) */\r
+\r
+typedef enum {\r
+ MCU_FMPLL_BYPASS = 0,\r
+ MCU_FMPLL_EXTERNAL_REF,\r
+ MCU_FMPLL_EXTERNAL_REF_NO_FM,\r
+ MCU_FMPLL_DUAL_CONTROLLER_MODE,\r
+} Mcu_FMPLLmode_t;\r
+\r
+typedef enum {\r
+ MCU_CLOCKTYPE_EXT_REF_80MHZ = 0,\r
+ MCU_CLOCKTYPE_EXT_REF_66MHZ,\r
+ MCU_NBR_OF_CLOCKS,\r
+ //MCU_CLOCKTYPE_EXTERNAL_REF,\r
+ //MCU_CLOCKTYPE_EXTERNAL_REF_NO_FM,\r
+ //MCU_CLOCKTYPE_DUAL_CONTROLLER_MODE,\r
+} Mcu_ClockType;\r
+\r
+\r
+typedef struct {\r
+ // This container defines a reference point in the Mcu Clock tree\r
+ // It defines the frequency which then can be used by other modules\r
+ // as an input value. Lower multiplicity is 1, as even in the\r
+ // simplest case (only one frequency is used), there is one\r
+ // frequency to be defined.\r
+ uint32 McuClockReferencePoint;\r
+\r
+ // Phase locked loop configuration parameters for MPC551x.\r
+ uint8 PllEprediv;\r
+ uint8 PllEmfd;\r
+ uint8 PllErfd;\r
+} Mcu_ClockSettingConfigType;\r
+\r
+typedef struct {\r
+ // The parameter represents the MCU Mode settings\r
+ uint32 McuMode;\r
+} Mcu_ModeSettingConfigType;\r
+\r
+typedef struct {\r
+ // This parameter shall represent the Data pre-setting to be initialized\r
+ uint32 McuRamDefaultValue;\r
+\r
+ // This parameter shall represent the MCU RAM section base address\r
+ uint32 McuRamSectionBaseAddress;\r
+\r
+ // This parameter shall represent the MCU RAM Section size\r
+ uint32 McuRamSectionSize;\r
+\r
+} Mcu_RamSectorSettingConfigType;\r
+\r
+\r
+// This container defines a reference point in the Mcu Clock tree. It defines\r
+// the frequency which then can be used by other modules as an input value.\r
+// Lower multiplicity is 1, as even in the simplest case (only one frequency is\r
+// used), there is one frequency to be defined.\r
+typedef struct {\r
+\r
+ // This is the frequency for the specific instance of the McuClockReference-\r
+ // Point container. It shall be givn in Hz.\r
+ uint32 McuClockReferencePointFrequency;\r
+\r
+} Mcu_ClockReferencePointType;\r
+\r
+typedef struct {\r
+ // Enables/Disables clock failure notification. In case this feature is not supported\r
+ // by HW the setting should be disabled.\r
+ uint8 McuClockSrcFailureNotification;\r
+\r
+ // This parameter shall represent the number of Modes available for the\r
+ // MCU. calculationFormula = Number of configured McuModeSettingConf\r
+ uint8 McuNumberOfMcuModes;\r
+\r
+ // This parameter shall represent the number of RAM sectors available for\r
+ // the MCU. calculationFormula = Number of configured McuRamSectorSet-\r
+ // tingConf\r
+ uint8 McuRamSectors;\r
+\r
+ // This parameter shall represent the number of clock setting available for\r
+ // the MCU.\r
+ uint8 McuClockSettings;\r
+\r
+ // This parameter defines the default clock settings that should be used\r
+ // It is an index into the McuClockSettingsConfig\r
+ Mcu_ClockType McuDefaultClockSettings;\r
+\r
+ // This parameter relates to the MCU specific reset configuration. This ap-\r
+ // plies to the function Mcu_PerformReset, which performs a microcontroller\r
+ // reset using the hardware feature of the microcontroller.\r
+ uint32 McuResetSetting;\r
+\r
+ // This container contains the configuration (parameters) for the\r
+ // Clock settings of the MCU. Please see MCU031 for more in-\r
+ // formation on the MCU clock settings.\r
+ Mcu_ClockSettingConfigType * McuClockSettingConfig;\r
+\r
+ // This container contains the configuration (parameters) for the\r
+ // Mode setting of the MCU. Please see MCU035 for more information\r
+ // on the MCU mode settings.\r
+ Mcu_ModeSettingConfigType *McuModeSettingConfig;\r
+\r
+ // This container contains the configuration (parameters) for the\r
+ // RAM Sector setting. Please see MCU030 for more information\r
+ // on RAM sec-tor settings.\r
+ Mcu_RamSectorSettingConfigType *McuRamSectorSettingConfig;\r
+\r
+} Mcu_ConfigType;\r
+\r
+extern const Mcu_ConfigType McuConfigData[];\r
+\r
+#define MCU_DEFAULT_CONFIG McuConfigData[0]\r
+\r
+#endif /*MCU_CFG_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef MEMIF_CFG_H_
+#define MEMIF_CFG_H_
+
+// TODO. include FEE and EA modules
+
+
+
+#endif /*MEMIF_CFG_H_*/
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#define PDUR_ZERO_COST_OPERATION\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+#include "Port_Cfg.h"\r
+\r
+// All: PA,OBE,IBE,ODE,HYS,SRC,WPE,WPS\r
+// Input: PA,OBE,IBE,HYS,WPE,WPS\r
+// Output: PA,OBE,IBE,ODE,SRC,(WPE,WPS)\r
+\r
+#define PCR_PWM PCR_BOOTCFG\r
+#define PCR_ADC (0)\r
+#define PCR_IO_INPUT PCR_BOOTCFG\r
+#define PCR_IO_OUTPUT OBE_ENABLE\r
+#define PCR_CAN (0)\r
+#define PCR_SPI PCR_BOOTCFG\r
+#define PCR_I2C PCR_BOOTCFG\r
+\r
+\r
+const uint16_t PortPadConfigData[] =\r
+{\r
+ // pad 0-15\r
+ PCR_ADC|PA_FUNC1, /* PA0, AN0 */\r
+ PCR_RESET, /* PA1 */\r
+ PCR_RESET, /* PA2 */\r
+ PCR_RESET, /* PA3 */\r
+ PCR_RESET, /* PA4 */\r
+ PCR_RESET, /* PA5 */\r
+ PCR_RESET, /* PA6, */\r
+ PCR_RESET, /* PA7(input only) */\r
+ PCR_RESET, /* PA8(input only) */\r
+ PCR_RESET, /* PA9(input only) */\r
+ PCR_RESET, /* PA10(input only) */\r
+ PCR_RESET, /* PA11(input only) */\r
+ PCR_RESET, /* PA12(input only) */\r
+ PCR_RESET, /* PA13(input only) */\r
+ PCR_RESET, /* PA14(input only) */\r
+ PCR_RESET, /* PA15(input only) */\r
+\r
+ // pad 16-31\r
+ PCR_RESET, /* PB0 */\r
+ PCR_RESET, /* PB1 */\r
+ PCR_RESET, /* PB2 */\r
+ PCR_RESET, /* PB3 */\r
+ PCR_RESET, /* PB4 */\r
+ PCR_RESET, /* PB5 */\r
+ PCR_RESET, /* PB6 */\r
+ PCR_RESET, /* PB7 */\r
+ PCR_RESET, /* PB8 */\r
+ PCR_RESET, /* PB9 */\r
+ PCR_RESET, /* PB10 */\r
+ PCR_RESET, /* PB11 */\r
+ PCR_RESET, /* PB12 */\r
+ PCR_RESET, /* PB13 */\r
+ PCR_RESET, /* PB14 */\r
+ PCR_RESET, /* PB15 */\r
+\r
+ // pad 32-47\r
+ PCR_RESET, /* PC0/emios0 */\r
+ PCR_RESET, // PC1\r
+ PCR_RESET, // PC2\r
+ PCR_RESET, /* PC3 */\r
+ PCR_RESET, /* PC4 */\r
+ PCR_RESET, /* PC5 */\r
+ PCR_RESET, /* PC6 */\r
+ PCR_RESET, /* PC7 */\r
+ PCR_RESET, /* PC8 */\r
+ PCR_RESET, /* PC9 */\r
+ PCR_RESET, /* PC10 */\r
+ PCR_RESET, /* PC11 */\r
+ PCR_RESET, /* PC12 */\r
+ PCR_RESET, /* PC13 */\r
+ PCR_RESET, /* PC14 */\r
+ PCR_RESET, /* PC15 */\r
+\r
+ // pad 48-63\r
+ (PCR_CAN|PA_FUNC1), /* PD0, CAN_A, Tx */\r
+ (PCR_CAN|PA_FUNC1), /* PD1, CAN_A, Rx */\r
+ PCR_BOOTCFG, /* PD2 */\r
+ PCR_RESET, /* PD3 */\r
+ PCR_IO_OUTPUT, /* PD4, LED */\r
+ PCR_IO_OUTPUT, /* PD5, LED */\r
+ PCR_RESET, /* PD6 , SCI_RS232??*/\r
+ PCR_RESET, /* PD7 , SCI_RS232??*/\r
+ (PA_FUNC1 | OBE_ENABLE | SLEW_RATE_MAX), /* PD8 LIN TX */\r
+ (PA_FUNC1 | IBE_ENABLE), /* PD9 LIN RX */\r
+ PCR_RESET, /* PD10 */\r
+ PCR_RESET, /* PD11 */\r
+ (PA_FUNC1 | OBE_ENABLE | SLEW_RATE_MAX), /* PD12 SPIB_CS0 */\r
+ (PA_FUNC1 | OBE_ENABLE | SLEW_RATE_MAX), /* PD13 SPIB_CLK*/\r
+ (PA_FUNC1 | OBE_ENABLE | SLEW_RATE_MAX), /* PD14 SPIB_SO*/\r
+ (PA_FUNC1 | IBE_ENABLE), /* PD15 SPIB_SI*/\r
+\r
+ // pad 64-79\r
+ (PA_FUNC1 | OBE_ENABLE | SLEW_RATE_MAX), /* PE0 SPIA_CS1 */\r
+ (PA_FUNC1 | OBE_ENABLE | SLEW_RATE_MAX), /* PE1 SPIA_CS2*/\r
+ PCR_RESET, /* PE2 */\r
+ (PA_FUNC1 | OBE_ENABLE | SLEW_RATE_MAX), /* PE3 SPIA_CLK*/\r
+ (PA_FUNC1 | OBE_ENABLE | SLEW_RATE_MAX), /* PE4 SPIA_SO*/\r
+ (PA_FUNC1 | IBE_ENABLE), /* PE5 SPIA_SI*/\r
+ PCR_RESET, /* PE6 */\r
+ PCR_RESET, /* PE7 */\r
+ PCR_RESET, /* PE8 */\r
+ PCR_RESET, /* PE9 */\r
+ PCR_RESET, /* PE10 */\r
+ PCR_RESET, /* PE11 */\r
+ PCR_RESET, /* PE12 */\r
+ PCR_RESET, /* PE13 */\r
+ PCR_RESET, /* PE14 */\r
+ PCR_RESET, /* PE15 */\r
+\r
+ // pad 80-95\r
+ PCR_RESET, /* PF0 */\r
+ PCR_RESET, /* PF1 */\r
+ PCR_RESET, /* PF2 */\r
+ PCR_RESET, /* PF3 */\r
+ PCR_RESET, /* PF4 */\r
+ PCR_RESET, /* PF5 */\r
+ PCR_RESET, /* PF6 */\r
+ PCR_RESET, /* PF7 */\r
+ PCR_RESET, /* PF8 */\r
+ PCR_RESET, /* PF9 */\r
+ PCR_RESET, /* PF10 */\r
+ PCR_RESET, /* PF11 */\r
+ PA_FUNC2|OBE_ENABLE|PULL_UP, /* PF12 SCI_D Transmit, J1708 Tx*/\r
+ PA_FUNC2|IBE_ENABLE|PULL_UP, /* PF13 SCI_D Receive, J1708 Rx*/\r
+ PCR_RESET, /* PF14 */\r
+ PCR_RESET, /* PF15 */\r
+\r
+ // pad 96-111\r
+ PCR_RESET, /* PG0 */\r
+ PA_FUNC2|IBE_ENABLE|PULL_UP, /* PG1 eMIOS[17], J1708 Edgedetect*/\r
+ PCR_RESET, /* PG2 */\r
+ PCR_RESET, /* PG3 */\r
+ PCR_RESET, /* PG4 */\r
+ PCR_RESET, /* PG5 */\r
+ PCR_RESET, /* PG6 */\r
+ PCR_RESET, /* PG7 */\r
+ PCR_RESET, /* PG8 */\r
+ PCR_RESET, /* PG9 */\r
+ PCR_RESET, /* PG10 */\r
+ PCR_RESET, /* PG11 */\r
+ PCR_RESET, /* PG12 */\r
+ PCR_RESET, /* PG13 */\r
+ PCR_RESET, /* PG14 */\r
+ PCR_RESET, /* PG15 */\r
+\r
+ // pad 112-127\r
+ PCR_RESET, /* PH0 */\r
+ PCR_RESET, /* PH1 */\r
+ PCR_RESET, /* PH2 */\r
+ PCR_RESET, /* PH3 */\r
+ PCR_RESET, /* PH4 */\r
+ PCR_RESET, /* PH5 */\r
+ PCR_RESET, /* PH6 */\r
+ PCR_RESET, /* PH7 */\r
+ PCR_RESET, /* PH8 */\r
+ PCR_RESET, /* PH9 */\r
+ PCR_RESET, /* PH10 */\r
+ PCR_RESET, /* PH11 */\r
+ PCR_RESET, /* PH12 */\r
+ PCR_RESET, /* PH13 */\r
+ PCR_RESET, /* PH14 */\r
+ PCR_RESET, /* PH15 */\r
+\r
+ // pad 128-143\r
+ PCR_RESET, /* PJ0 */\r
+ PCR_RESET, /* PJ1 */\r
+ PCR_RESET, /* PJ2 */\r
+ PCR_RESET, /* PJ3 */\r
+ PCR_RESET, /* PJ4 */\r
+ PCR_RESET, /* PJ5 */\r
+ PCR_RESET, /* PJ6 */\r
+ PCR_RESET, /* PJ7 */\r
+ PCR_RESET, /* PJ8 */\r
+ PCR_RESET, /* PJ9 */\r
+ PCR_RESET, /* PJ10 */\r
+ PCR_RESET, /* PJ11 */\r
+ PCR_RESET, /* PJ12 */\r
+ PCR_RESET, /* PJ13 */\r
+ PCR_RESET, /* PJ14 */\r
+ PCR_RESET, /* PJ15 */\r
+\r
+ // pad 144-145\r
+ PCR_RESET, /* PK0 (input only) */\r
+ PCR_RESET, /* PK1 (input only)*/\r
+};\r
+\r
+\r
+#define GPDO_RESET 0\r
+\r
+const uint8_t PortOutConfigData[] =\r
+{\r
+ // pad 16-31\r
+ GPDO_RESET, /* PB0 */\r
+ GPDO_RESET, /* PB1 */\r
+ GPDO_RESET, /* PB2 */\r
+ GPDO_RESET, /* PB3 */\r
+ GPDO_RESET, /* PB4 */\r
+ GPDO_RESET, /* PB5 */\r
+ GPDO_RESET, /* PB6 */\r
+ GPDO_RESET, /* PB7 */\r
+ GPDO_RESET, /* PB8 */\r
+ GPDO_RESET, /* PB9 */\r
+ GPDO_RESET, /* PB10 */\r
+ GPDO_RESET, /* PB11 */\r
+ GPDO_RESET, /* PB12 */\r
+ GPDO_RESET, /* PB13 */\r
+ GPDO_RESET, /* PB14 */\r
+ GPDO_RESET, /* PB15 */\r
+\r
+ // pad 32-47\r
+ GPDO_RESET, /* PC0 */\r
+ GPDO_RESET, /* PC1 */\r
+ GPDO_RESET, /* PC2 */\r
+ GPDO_RESET, /* PC3 */\r
+ GPDO_RESET, /* PC4 */\r
+ GPDO_RESET, /* PC5 */\r
+ GPDO_RESET, /* PC6 */\r
+ GPDO_RESET, /* PC7 */\r
+ GPDO_RESET, /* PC8 */\r
+ GPDO_RESET, /* PC9 */\r
+ GPDO_RESET, /* PC10 */\r
+ GPDO_RESET, /* PC11 */\r
+ GPDO_RESET, /* PC12 */\r
+ GPDO_RESET, /* PC13 */\r
+ GPDO_RESET, /* PC14 */\r
+ GPDO_RESET, /* PC15 */\r
+\r
+ // pad 48-63\r
+ GPDO_RESET, /* PD0 */\r
+ GPDO_RESET, /* PD1 */\r
+ GPDO_RESET, /* PD2 */\r
+ GPDO_RESET, /* PD3 */\r
+ GPDO_RESET, /* PD4 */\r
+ GPDO_RESET, /* PD5 */\r
+ GPDO_RESET, /* PD6 */\r
+ GPDO_RESET, /* PD7 */\r
+ GPDO_RESET, /* PD8 */\r
+ GPDO_RESET, /* PD9 */\r
+ GPDO_RESET, /* PD10 */\r
+ GPDO_RESET, /* PD11 */\r
+ GPDO_RESET, /* PD12 */\r
+ GPDO_RESET, /* PD13 */\r
+ GPDO_RESET, /* PD14 */\r
+ GPDO_RESET, /* PD15 */\r
+\r
+ // pad 64-79\r
+ GPDO_RESET, /* PE0 */\r
+ GPDO_RESET, /* PE1 */\r
+ GPDO_RESET, /* PE2 */\r
+ GPDO_RESET, /* PE3 */\r
+ GPDO_RESET, /* PE4 */\r
+ GPDO_RESET, /* PE5 */\r
+ GPDO_RESET, /* PE6 */\r
+ GPDO_RESET, /* PE7 */\r
+ GPDO_RESET, /* PE8 */\r
+ GPDO_RESET, /* PE9 */\r
+ GPDO_RESET, /* PE10 */\r
+ GPDO_RESET, /* PE11 */\r
+ GPDO_RESET, /* PE12 */\r
+ GPDO_RESET, /* PE13 */\r
+ GPDO_RESET, /* PE14 */\r
+ GPDO_RESET, /* PE15 */\r
+\r
+ // pad 80-95\r
+ GPDO_RESET, /* PF0 */\r
+ GPDO_RESET, /* PF1 */\r
+ GPDO_RESET, /* PF2 */\r
+ GPDO_RESET, /* PF3 */\r
+ GPDO_RESET, /* PF4 */\r
+ GPDO_RESET, /* PF5 */\r
+ GPDO_RESET, /* PF6 */\r
+ GPDO_RESET, /* PF7 */\r
+ GPDO_RESET, /* PF8 */\r
+ GPDO_RESET, /* PF9 */\r
+ GPDO_RESET, /* PF10 */\r
+ GPDO_RESET, /* PF11 */\r
+ GPDO_RESET, /* PF12 */\r
+ GPDO_RESET, /* PF13 */\r
+ GPDO_RESET, /* PF14 */\r
+ GPDO_RESET, /* PF15 */\r
+\r
+ // pad 96-111\r
+ GPDO_RESET, /* PG0 */\r
+ GPDO_RESET, /* PG1 */\r
+ GPDO_RESET, /* PG2 */\r
+ GPDO_RESET, /* PG3 */\r
+ GPDO_RESET, /* PG4 */\r
+ GPDO_RESET, /* PG5 */\r
+ GPDO_RESET, /* PG6 */\r
+ GPDO_RESET, /* PG7 */\r
+ GPDO_RESET, /* PG8 */\r
+ GPDO_RESET, /* PG9 */\r
+ GPDO_RESET, /* PG10 */\r
+ GPDO_RESET, /* PG11 */\r
+ GPDO_RESET, /* PG12 */\r
+ GPDO_RESET, /* PG13 */\r
+ GPDO_RESET, /* PG14 */\r
+ GPDO_RESET, /* PG15 */\r
+\r
+ // pad 112-127\r
+ GPDO_RESET, /* PH0 */\r
+ GPDO_RESET, /* PH1 */\r
+ GPDO_RESET, /* PH2 */\r
+ GPDO_RESET, /* PH3 */\r
+ GPDO_RESET, /* PH4 */\r
+ GPDO_RESET, /* PH5 */\r
+ GPDO_RESET, /* PH6 */\r
+ GPDO_RESET, /* PH7 */\r
+ GPDO_RESET, /* PH8 */\r
+ GPDO_RESET, /* PH9 */\r
+ GPDO_RESET, /* PH10 */\r
+ GPDO_RESET, /* PH11 */\r
+ GPDO_RESET, /* PH12 */\r
+ GPDO_RESET, /* PH13 */\r
+ GPDO_RESET, /* PH14 */\r
+ GPDO_RESET, /* PH15 */\r
+\r
+ // pad 128-143\r
+ GPDO_RESET, /* PJ0 */\r
+ GPDO_RESET, /* PJ1 */\r
+ GPDO_RESET, /* PJ2 */\r
+ GPDO_RESET, /* PJ3 */\r
+ GPDO_RESET, /* PJ4 */\r
+ GPDO_RESET, /* PJ5 */\r
+ GPDO_RESET, /* PJ6 */\r
+ GPDO_RESET, /* PJ7 */\r
+ GPDO_RESET, /* PJ8 */\r
+ GPDO_RESET, /* PJ9 */\r
+ GPDO_RESET, /* PJ10 */\r
+ GPDO_RESET, /* PJ11 */\r
+ GPDO_RESET, /* PJ12 */\r
+ GPDO_RESET, /* PJ13 */\r
+ GPDO_RESET, /* PJ14 */\r
+ GPDO_RESET, /* PJ15 */\r
+};\r
+\r
+//#define GPDI_RESET 0\r
+//const uint8_t PortInConfigData[] =\r
+//{\r
+// // pad 0-15\r
+// GPDI_RESET, /* PA0(input only) */\r
+// GPDI_RESET, /* PA1(input only) */\r
+// GPDI_RESET, /* PA2(input only) */\r
+// GPDI_RESET, /* PA3(input only) */\r
+// GPDI_RESET, /* PA4(input only) */\r
+// GPDI_RESET, /* PA5(input only) */\r
+// GPDI_RESET, /* PA6(input only) */\r
+// GPDI_RESET, /* PA7(input only) */\r
+// GPDI_RESET, /* PA8(input only) */\r
+// GPDI_RESET, /* PA9(input only) */\r
+// GPDI_RESET, /* PA10(input only) */\r
+// GPDI_RESET, /* PA11(input only) */\r
+// GPDI_RESET, /* PA12(input only) */\r
+// GPDI_RESET, /* PA13(input only) */\r
+// GPDI_RESET, /* PA14(input only) */\r
+// GPDI_RESET, /* PA15(input only) */\r
+//\r
+// // pad 16-31\r
+// GPDI_RESET, /* PB0 */\r
+// GPDI_RESET, /* PB1 */\r
+// GPDI_RESET, /* PB2 */\r
+// GPDI_RESET, /* PB3 */\r
+// GPDI_RESET, /* PB4 */\r
+// GPDI_RESET, /* PB5 */\r
+// GPDI_RESET, /* PB6 */\r
+// GPDI_RESET, /* PB7 */\r
+// GPDI_RESET, /* PB8 */\r
+// GPDI_RESET, /* PB9 */\r
+// GPDI_RESET, /* PB10 */\r
+// GPDI_RESET, /* PB11 */\r
+// GPDI_RESET, /* PB12 */\r
+// GPDI_RESET, /* PB13 */\r
+// GPDI_RESET, /* PB14 */\r
+// GPDI_RESET, /* PB15 */\r
+//\r
+// // pad 32-47\r
+// GPDI_RESET, /* PC0 */\r
+// GPDI_RESET, /* PC1 */\r
+// GPDI_RESET, /* PC2 */\r
+// GPDI_RESET, /* PC3 */\r
+// GPDI_RESET, /* PC4 */\r
+// GPDI_RESET, /* PC5 */\r
+// GPDI_RESET, /* PC6 */\r
+// GPDI_RESET, /* PC7 */\r
+// GPDI_RESET, /* PC8 */\r
+// GPDI_RESET, /* PC9 */\r
+// GPDI_RESET, /* PC10 */\r
+// GPDI_RESET, /* PC11 */\r
+// GPDI_RESET, /* PC12 */\r
+// GPDI_RESET, /* PC13 */\r
+// GPDI_RESET, /* PC14 */\r
+// GPDI_RESET, /* PC15 */\r
+//\r
+// // pad 48-63\r
+// GPDI_RESET, /* PD0 */\r
+// GPDI_RESET, /* PD1 */\r
+// GPDI_RESET, /* PD2 */\r
+// GPDI_RESET, /* PD3 */\r
+// GPDI_RESET, /* PD4 */\r
+// GPDI_RESET, /* PD5 */\r
+// GPDI_RESET, /* PD6 */\r
+// GPDI_RESET, /* PD7 */\r
+// GPDI_RESET, /* PD8 */\r
+// GPDI_RESET, /* PD9 */\r
+// GPDI_RESET, /* PD10 */\r
+// GPDI_RESET, /* PD11 */\r
+// GPDI_RESET, /* PD12 */\r
+// GPDI_RESET, /* PD13 */\r
+// GPDI_RESET, /* PD14 */\r
+// GPDI_RESET, /* PD15 */\r
+//\r
+// // pad 64-79\r
+// GPDI_RESET, /* PE0 */\r
+// GPDI_RESET, /* PE1 */\r
+// GPDI_RESET, /* PE2 */\r
+// GPDI_RESET, /* PE3 */\r
+// GPDI_RESET, /* PE4 */\r
+// GPDI_RESET, /* PE5 */\r
+// GPDI_RESET, /* PE6 */\r
+// GPDI_RESET, /* PE7 */\r
+// GPDI_RESET, /* PE8 */\r
+// GPDI_RESET, /* PE9 */\r
+// GPDI_RESET, /* PE10 */\r
+// GPDI_RESET, /* PE11 */\r
+// GPDI_RESET, /* PE12 */\r
+// GPDI_RESET, /* PE13 */\r
+// GPDI_RESET, /* PE14 */\r
+// GPDI_RESET, /* PE15 */\r
+//\r
+// // pad 80-95\r
+// GPDI_RESET, /* PF0 */\r
+// GPDI_RESET, /* PF1 */\r
+// GPDI_RESET, /* PF2 */\r
+// GPDI_RESET, /* PF3 */\r
+// GPDI_RESET, /* PF4 */\r
+// GPDI_RESET, /* PF5 */\r
+// GPDI_RESET, /* PF6 */\r
+// GPDI_RESET, /* PF7 */\r
+// GPDI_RESET, /* PF8 */\r
+// GPDI_RESET, /* PF9 */\r
+// GPDI_RESET, /* PF10 */\r
+// GPDI_RESET, /* PF11 */\r
+// GPDI_RESET, /* PF12 */\r
+// GPDI_RESET, /* PF13 */\r
+// GPDI_RESET, /* PF14 */\r
+// GPDI_RESET, /* PF15 */\r
+//\r
+// // pad 96-111\r
+// GPDI_RESET, /* PG0 */\r
+// GPDI_RESET, /* PG1 */\r
+// GPDI_RESET, /* PG2 */\r
+// GPDI_RESET, /* PG3 */\r
+// GPDI_RESET, /* PG4 */\r
+// GPDI_RESET, /* PG5 */\r
+// GPDI_RESET, /* PG6 */\r
+// GPDI_RESET, /* PG7 */\r
+// GPDI_RESET, /* PG8 */\r
+// GPDI_RESET, /* PG9 */\r
+// GPDI_RESET, /* PG10 */\r
+// GPDI_RESET, /* PG11 */\r
+// GPDI_RESET, /* PG12 */\r
+// GPDI_RESET, /* PG13 */\r
+// GPDI_RESET, /* PG14 */\r
+// GPDI_RESET, /* PG15 */\r
+//\r
+// // pad 112-127\r
+// GPDI_RESET, /* PH0 */\r
+// GPDI_RESET, /* PH1 */\r
+// GPDI_RESET, /* PH2 */\r
+// GPDI_RESET, /* PH3 */\r
+// GPDI_RESET, /* PH4 */\r
+// GPDI_RESET, /* PH5 */\r
+// GPDI_RESET, /* PH6 */\r
+// GPDI_RESET, /* PH7 */\r
+// GPDI_RESET, /* PH8 */\r
+// GPDI_RESET, /* PH9 */\r
+// GPDI_RESET, /* PH10 */\r
+// GPDI_RESET, /* PH11 */\r
+// GPDI_RESET, /* PH12 */\r
+// GPDI_RESET, /* PH13 */\r
+// GPDI_RESET, /* PH14 */\r
+// GPDI_RESET, /* PH15 */\r
+//\r
+// // pad 128-143\r
+// GPDI_RESET, /* PJ0 */\r
+// GPDI_RESET, /* PJ1 */\r
+// GPDI_RESET, /* PJ2 */\r
+// GPDI_RESET, /* PJ3 */\r
+// GPDI_RESET, /* PJ4 */\r
+// GPDI_RESET, /* PJ5 */\r
+// GPDI_RESET, /* PJ6 */\r
+// GPDI_RESET, /* PJ7 */\r
+// GPDI_RESET, /* PJ8 */\r
+// GPDI_RESET, /* PJ9 */\r
+// GPDI_RESET, /* PJ10 */\r
+// GPDI_RESET, /* PJ11 */\r
+// GPDI_RESET, /* PJ12 */\r
+// GPDI_RESET, /* PJ13 */\r
+// GPDI_RESET, /* PJ14 */\r
+// GPDI_RESET, /* PJ15 */\r
+//\r
+// // pad 144-145\r
+// GPDI_RESET, /* PK0 (input only) */\r
+// GPDI_RESET, /* PK1 (input only) */\r
+//};\r
+\r
+const Port_ConfigType PortConfigData =\r
+{\r
+ .padCnt = sizeof(PortPadConfigData),\r
+ .padConfig = PortPadConfigData,\r
+ .outCnt = sizeof(PortOutConfigData),\r
+ .outConfig = PortOutConfigData,\r
+// .inCnt = sizeof(PortInConfigData),\r
+// .inConfig = PortInConfigData,\r
+};\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef PORT_CFG_H_\r
+#define PORT_CFG_H_\r
+\r
+#include "Std_Types.h"\r
+\r
+#define PORT_VERSION_INFO_API STD_ON\r
+#define PORT_DEV_ERROR_DETECT STD_ON\r
+#define PORT_PIN_DIRECTION_CHANGES_ALLOWED STD_ON\r
+\r
+typedef enum\r
+{\r
+ PA0,\r
+ PA1,\r
+ PA2,\r
+ PA3,\r
+ PA4,\r
+ PA5,\r
+ PA6,\r
+ PA7,\r
+ PA8,\r
+ PA9,\r
+ PA10,\r
+ PA11,\r
+ PA12,\r
+ PA13,\r
+ PA14,\r
+ PA15,\r
+ PB0,\r
+ PB1,\r
+ PB2,\r
+ PB3,\r
+ PB4,\r
+ PB5,\r
+ PB6,\r
+ PB7,\r
+ PB8,\r
+ PB9,\r
+ PB10,\r
+ PB11,\r
+ PB12,\r
+ PB13,\r
+ PB14,\r
+ PB15,\r
+ PC0,\r
+ PC1,\r
+ PC2,\r
+ PC3,\r
+ PC4,\r
+ PC5,\r
+ PC6,\r
+ PC7,\r
+ PC8,\r
+ PC9,\r
+ PC10,\r
+ PC11,\r
+ PC12,\r
+ PC13,\r
+ PC14,\r
+ PC15,\r
+ PD0,\r
+ PD1,\r
+ PD2,\r
+ PD3,\r
+ PD4,\r
+ PD5,\r
+ PD6,\r
+ PD7,\r
+ PD8,\r
+ PD9,\r
+ PD10,\r
+ PD11,\r
+ PD12,\r
+ PD13,\r
+ PD14,\r
+ PD15,\r
+ PE0,\r
+ PE1,\r
+ PE2,\r
+ PE3,\r
+ PE4,\r
+ PE5,\r
+ PE6,\r
+ PE7,\r
+ PE8,\r
+ PE9,\r
+ PE10,\r
+ PE11,\r
+ PE12,\r
+ PE13,\r
+ PE14,\r
+ PE15,\r
+ PF0,\r
+ PF1,\r
+ PF2,\r
+ PF3,\r
+ PF4,\r
+ PF5,\r
+ PF6,\r
+ PF7,\r
+ PF8,\r
+ PF9,\r
+ PF10,\r
+ PF11,\r
+ PF12,\r
+ PF13,\r
+ PF14,\r
+ PF15,\r
+ PG0,\r
+ PG1,\r
+ PG2,\r
+ PG3,\r
+ PG4,\r
+ PG5,\r
+ PG6,\r
+ PG7,\r
+ PG8,\r
+ PG9,\r
+ PG10,\r
+ PG11,\r
+ PG12,\r
+ PG13,\r
+ PG14,\r
+ PG15,\r
+ PH0,\r
+ PH1,\r
+ PH2,\r
+ PH3,\r
+ PH4,\r
+ PH5,\r
+ PH6,\r
+ PH7,\r
+ PH8,\r
+ PH9,\r
+ PH10,\r
+ PH11,\r
+ PH12,\r
+ PH13,\r
+ PH14,\r
+ PH15,\r
+ PJ0,\r
+ PJ1,\r
+ PJ2,\r
+ PJ3,\r
+ PJ4,\r
+ PJ5,\r
+ PJ6,\r
+ PJ7,\r
+ PJ8,\r
+ PJ9,\r
+ PJ10,\r
+ PJ11,\r
+ PJ12,\r
+ PJ13,\r
+ PJ14,\r
+ PJ15,\r
+ PK0,\r
+ PK1\r
+} Port_PinType;\r
+\r
+#define BIT0 (1<<15)\r
+#define BIT1 (1<<14)\r
+#define BIT2 (1<<13)\r
+#define BIT3 (1<<12)\r
+#define BIT4 (1<<11)\r
+#define BIT5 (1<<10)\r
+#define BIT6 (1<<9)\r
+#define BIT7 (1<<8)\r
+#define BIT8 (1<<7)\r
+#define BIT9 (1<<6)\r
+#define BIT10 (1<<5)\r
+#define BIT11 (1<<4)\r
+#define BIT12 (1<<3)\r
+#define BIT13 (1<<2)\r
+#define BIT14 (1<<1)\r
+#define BIT15 (1<<0)\r
+\r
+#define WPE_BIT BIT14\r
+#define WPS_BIT BIT15\r
+#define SRC0 BIT12\r
+#define SRC1 BIT13\r
+\r
+#define PULL_UP (WPE_BIT|WPS_BIT)\r
+#define PULL_DOWN (WPE_BIT)\r
+#define PULL_NONE 0\r
+#define SLEW_RATE_MIN 0\r
+#define SLEW_RATE_MED BIT13\r
+#define SLEW_RATE_MAX (BIT12|BIT13)\r
+#define HYS_ENABLE BIT11\r
+#define ODE_ENABLE BIT10\r
+#define IBE_ENABLE BIT7\r
+#define OBE_ENABLE BIT6\r
+#define PA_IO 0\r
+#define PA_FUNC1 (BIT5)\r
+#define PA_FUNC2 (BIT4)\r
+#define PA_FUNC3 (BIT4|BIT5)\r
+\r
+#define NORMAL_INPUT (BIT15)\r
+\r
+// Should be this out of reset\r
+#define PCR_RESET (0)\r
+#define PCR_BOOTCFG (IBE_ENABLE|PULL_DOWN)\r
+\r
+\r
+#define EVB_TEST_CONFIG (&PortConfigData)\r
+\r
+\r
+typedef struct\r
+{\r
+ uint16_t padCnt;\r
+ const uint16_t *padConfig;\r
+ uint16_t outCnt;\r
+ const uint8_t *outConfig;\r
+// uint16_t inCnt;\r
+// const uint8_t *inConfig;\r
+} Port_ConfigType;\r
+\r
+extern const Port_ConfigType PortConfigData;\r
+\r
+#endif /*PORT_CFG_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef SPI_CFG_H_
+#define SPI_CFG_H_
+
+#include "Dma_Cfg.h"
+#include "mpc55xx.h"
+#include "Mcu_Cfg.h"
+
+#define DSPI_CTRL_A 0
+#define DSPI_CTRL_B 1
+#define DSPI_CTRL_C 2
+#define DSPI_CTRL_D 3
+
+/*
+ * General configuration
+ */
+
+// Maximum amount of data that can be written/read in one go.
+#define SPI_EB_MAX_LENGTH 64
+
+// Switches the Spi_Cancel function ON or OFF.
+#define SPI_CANCEL_API STD_OFF
+
+// Selects the SPI Handler/Driver Channel Buffers usage allowed and delivered.
+// LEVEL 0 - Only Internal buffers
+// LEVEL 1 - Only external buffers
+// LEVEL 2 - Both internal/external buffers
+#define SPI_CHANNEL_BUFFERS_ALLOWED 1
+
+#define SPI_DEV_ERROR_DETECT STD_ON
+// Switches the Spi_GetHWUnitStatus function ON or OFF.
+#define SPI_HW_STATUS_API STD_ON
+// Switches the Interruptible Sequences handling functionality ON or OFF.
+#define SPI_INTERRUPTIBLE_SEQ_ALLOWED STD_OFF
+
+// LEVEL 0 - Simple sync
+// LEVEL 1 - Basic async
+// LEVEL 2 - Enhanced mode
+#define SPI_LEVEL_DELIVERED 2
+
+#define SPI_VERSION_INFO_API STD_ON
+
+#if 0
+#if SPI_LEVEL_DELIVERED>=1
+#define SPI_INTERRUPTIBLE_SEQ_ALLOWED STD_ON
+#endif
+#endif
+
+// M95256
+#define E2_WREN 0x6 // Write Enable 0000 0110
+#define E2_WRDI 0x4 // Write Disable 0000 0100
+#define E2_RDSR 0x5 // Read Status Register 0000 0101
+ // 1 - Read data
+#define E2_WRSR 0x1 // Write Status Register 0000 0001
+ // 1 - Write data
+#define E2_READ 0x3 // Read from Memory Array 0000 0011
+ // 1 - Write 16-bit address
+ // n - 8 -bit read data
+#define E2_WRITE 0x2 // WRITE Write to Memory Array 0000 0010
+ // 1 Write 16-bit address
+ // n - 8-bit reads
+
+
+#define FLASH_READ_25 0x03
+#define FLASH_READ_50 0x0B
+#define FLASH_RDSR 0x05
+#define FLASH_JEDEC_ID 0x9f
+#define FLASH_RDID 0x90
+#define FLASH_BYTE_WRITE 0x02
+#define FLASH_AI_WORD_WRITE 0xad
+#define FLASH_WREN 0x06
+#define FLASH_WRDI 0x04
+#define FLASH_WRSR 0x01
+#define FLASH_ERASE_4K 0x20
+
+
+
+typedef enum
+{
+ SPI_EB = 0, // External Buffer
+ SPI_IB // Internal Buffer
+} Spi_BufferType;
+
+typedef enum {
+ SPI_EXT_DEVICE_A_E2,
+ SPI_EXT_DEVICE_A_FLASH,
+ SPI_EXT_DEVICE_B_E2,
+} Spi_ExternalDeviceTypeType;
+
+typedef enum
+{
+ SPI_CH_E2_CMD = 0,
+ SPI_CH_E2_ADDR,
+ SPI_CH_E2_WREN,
+ SPI_CH_E2_DATA,
+
+ SPI_CH_EEP_CMD,
+ SPI_CH_EEP_ADDR,
+ SPI_CH_EEP_WREN,
+ SPI_CH_EEP_DATA,
+
+ SPI_CH_FLASH_CMD,
+ SPI_CH_FLASH_ADDR,
+ SPI_CH_FLASH_DATA,
+ SPI_CH_FLASH_WREN,
+ SPI_CH_FLASH_WRDI,
+ SPI_CH_FLASH_WRSR,
+
+ SPI_MAX_CHANNEL,
+} Spi_ChannelType;
+
+typedef enum
+{
+ SPI_JOB_E2_CMD = 0,
+ SPI_JOB_E2_CMD2,
+ SPI_JOB_E2_DATA,
+ SPI_JOB_E2_WREN,
+
+ SPI_JOB_EEP_CMD,
+ SPI_JOB_EEP_CMD2,
+ SPI_JOB_EEP_DATA,
+ SPI_JOB_EEP_WREN,
+
+ SPI_JOB_FLASH_CMD,
+ SPI_JOB_FLASH_CMD2,
+ SPI_JOB_FLASH_CMD_DATA,
+ SPI_JOB_FLASH_READ,
+ SPI_JOB_FLASH_WREN,
+ SPI_JOB_FLASH_WRDI,
+ SPI_JOB_FLASH_DATA,
+ SPI_JOB_FLASH_WRSR,
+ SPI_JOB_FLASH_ADDR,
+
+ SPI_MAX_JOB,
+} Spi_JobType;
+
+#define SPI_MAX_CHANNELS 8
+
+typedef enum
+{
+ SPI_SEQ_E2_CMD = 0,
+ SPI_SEQ_E2_CMD2,
+ SPI_SEQ_E2_READ,
+ SPI_SEQ_E2_WRITE,
+
+ SPI_SEQ_EEP_CMD,
+ SPI_SEQ_EEP_CMD2,
+ SPI_SEQ_EEP_READ,
+ SPI_SEQ_EEP_WRITE,
+
+ SPI_SEQ_FLASH_CMD,
+ SPI_SEQ_FLASH_CMD2,
+ SPI_SEQ_FLASH_CMD_DATA,
+ SPI_SEQ_FLASH_READ,
+ SPI_SEQ_FLASH_WRITE,
+ SPI_SEQ_FLASH_WRSR,
+ SPI_SEQ_FLASH_ERASE,
+
+ SPI_MAX_SEQUENCE,
+} Spi_SequenceType;
+
+typedef enum
+{
+ SPI_ECORE_TRANSFER_START_LSB,
+ SPI_ECORE_TRANSFER_START_MSB,
+} Spi_EcoreTransferStartType;
+
+
+typedef enum {
+ SPI_EDGE_LEADING,
+ SPI_EDGE_TRAILING
+} Spi_EdgeType;
+
+
+
+// All data needed to configure one SPI-channel
+typedef struct
+{
+ // Symbolic name
+ Spi_ChannelType SpiChannelId;
+ // Buffer usage with EB/IB channel
+ // TODO: The type is wrong...
+ unsigned SpiChannelType;
+
+ // This parameter is the width of a transmitted data unit.
+ uint32 SpiDataWidth;
+ // This parameter is the default value to transmit.
+ uint32 SpiDefaultData;
+
+ // This parameter contains the maximum size of data buffers in case of EB
+ // Channels and only.
+ Spi_NumberOfDataType SpiEbMaxLength;
+
+ // This parameter contains the maximum number of data buffers in case of IB
+ // Channels and only.
+ Spi_NumberOfDataType SpiIbNBuffers;
+
+ // This parameter defines the first starting bit for transmission.
+ Spi_EcoreTransferStartType SpiTransferStart;
+
+ //
+ _Bool SpiDmaNoIncreaseSrc;
+
+} Spi_ChannelConfigType;
+
+// All data needed to configure one SPI-Job, amongst others the connection
+// between the internal SPI unit and the special settings for an external de-
+// vice is done.
+typedef struct
+{
+
+ Spi_JobType SpiJobId;
+
+ // This parameter is the symbolic name to identify the HW SPI Hardware micro-
+ // controller peripheral allocated to this Job.
+ uint32 SpiHwUnit;
+
+ // This parameter is a reference to a notification function.
+ void (*SpiJobEndNotification)();
+
+ // Priority of the Job
+ // range 0..3
+ unsigned SpiJobPriority;
+
+ // A job references several channels.
+ uint32 ChannelAssignment[SPI_MAX_CHANNELS];
+
+ // Reference to the external device used by this job
+ Spi_ExternalDeviceTypeType DeviceAssignment;
+
+// unsigned SPI_NUMBER_OF_CHANNELS;
+// unsigned SPI_LIST_OF_CHANNELS[SPI_MAX_CHANNEL];
+} Spi_JobConfigType;
+
+// The communication settings of an external device. Closely linked to Spi-
+// Job.
+typedef struct
+{
+
+ // This parameter is the communication baudrate - This parameter allows
+ // using a range of values, from the point of view of configuration tools, from
+ // Hz up to MHz.
+ // Note! Float in config case, not here
+ uint32 SpiBaudrate;
+
+ // Symbolic name to identify the CS used for this job
+ uint32 SpiCsIdentifier;
+
+ // This parameter defines the active polarity of Chip Select.
+ // STD_HIGH or STD_LOW
+ uint8 SpiCsPolarity;
+
+ // This parameter defines the SPI data shift edge.
+ Spi_EdgeType SpiDataShiftEdge;
+
+ // This parameter enables or not the Chip Select handling functions.
+ uint8 SpiEnableCs;
+
+ // This parameter defines the SPI shift clock idle level.
+ uint8 SpiShiftClockIdleLevel;
+
+ // Timing between clock and chip select - This parameter allows to use a
+ // range of values from 0 up to 100 microSec. the real configuration-value
+ // used in software BSW-SPI is calculated out of this by the generator-tools
+ // Note! Float in config case, not here. Unit ns
+ uint32 SpiTimeClk2Cs;
+
+ // Timing between PCS and first edge of SCK. Unit ns.
+ uint32 SpiTimeCs2Clk;
+
+ // Ecore extension...
+ // The controller ID(0..3)
+ //uint32 SpiControllerId;
+
+} Spi_ExternalDeviceType;
+
+// All data needed to configure one SPI-sequence
+typedef struct
+{
+ // This parameter allows or not this Sequence to be suspended by another
+ // one.
+ unsigned SpiInterruptibleSequence;
+ // This parameter is a reference to a notification function.
+ void (*SpiSeqEndNotification)();
+ //
+ Spi_SequenceType SpiSequenceId;
+ // unsigned SPI_NUMBER_OF_JOBS;
+ // A sequence references several jobs, which are executed during a commu-
+ // nication sequence
+ uint32 JobAssignment[SPI_MAX_JOB];
+} Spi_SequenceConfigType;
+
+typedef struct
+{
+ /* Interrupt priority level for this SPI channel. */
+ uint8 IsrPriority;
+
+ /* This channel is to be activated for use. */
+ uint8 Activated;
+
+ /* Receive DMA channel. */
+ Dma_ChannelType RxDmaChannel;
+
+ /* Transmit DMA channel. */
+ Dma_ChannelType TxDmaChannel;
+
+ /* Peripheral clock source. */
+ McuE_PeriperalClock_t PeripheralClock;
+}Spi_HwConfigType;
+
+typedef struct
+{
+ // This parameter contains the number of Channels configured. It will be
+ // gathered by tools during the configuration stage.
+ uint8 SpiMaxChannel;
+
+ uint8 SpiMaxJob;
+
+ uint8 SpiMaxSequence;
+
+ // All data needed to configure one SPI-channel
+ const Spi_ChannelConfigType * SpiChannelConfig;
+
+ // The communication settings of an external device. Closely
+ // linked to SpiJob.
+ const Spi_ExternalDeviceType * SpiExternalDevice;
+
+ // All data needed to configure one SPI-Job, amongst others the
+ // connection between the internal SPI unit and the special set-
+ // tings for an external device is done.
+ const Spi_JobConfigType * SpiJobConfig;
+
+ // All data needed to configure one SPI-sequence
+ const Spi_SequenceConfigType * SpiSequenceConfig;
+
+ const Spi_HwConfigType *SpiHwConfig;
+} Spi_DriverType;
+
+typedef Spi_DriverType Spi_ConfigType;
+
+
+#if 0
+struct SpiDriverConfiguration_s
+{
+ Spi_ChannelType SPI_MAX_CHANNEL;
+ Spi_JobType SPI_MAX_JOB;
+ Spi_SequenceType SPI_MAX_SEQUENCE;
+};
+#endif
+
+// This is implementation specific but not all values may be valid
+// within the type.This type shall be chosen in order to have the
+// most efficient implementation on a specific microcontroller
+// platform.
+// In-short: Type of application data buffer elements
+// The 5516 TXDATA is 16-bit.. fits ?
+
+typedef uint8 Spi_DataType;
+//typedef uint16 Spi_DataType;
+
+// Specifies the identification (ID) for a SPI Hardware microcontroller peripheral (unit).
+// SPI140: This type is configurable (On / Off) at pre-compile time. The switch
+// SPI_HW_STATUS_API shall activate or deactivate the declaration of this
+// type.
+typedef uint32 Spi_HWUnitType;
+
+#if 0
+typedef struct
+{
+ Spi_SequenceConfigType SpiSequenceConfig;
+ Spi_JobConfigType SpiJobConfig;
+ Spi_ChannelConfigType SpiChannelConfig;
+ Spi_ExternalDeviceType SpiExternalDevice;
+}Spi_ConfigType;
+#endif
+
+extern const Spi_ConfigType SpiConfigData;
+
+
+uint32 Spi_GetJobCnt(void );
+uint32 Spi_GetChannelCnt(void );
+uint32 Spi_GetExternalDeviceCnt(void );
+
+
+
+#endif /*SPI_CFG_H_*/
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include "Spi.h"
+#include "Spi_Cfg.h"
+#include <stdlib.h>
+
+
+// SPI_A
+#define SPI_A_CS_E2 2
+#define SPI_A_CS_FLASH 1
+
+// SPI_B
+#define SPI_B_CS_E2 0
+
+
+#if 1
+extern void Spi_SeqEndNotification( void );
+extern void Spi_JobEndNotification( void );
+extern void Spi_Test_SeqEndNotification( Spi_SequenceType seq);
+extern void Spi_Test_JobEndNotification( Spi_JobType job);
+
+static void Spi_Test_SeqEndNotification_E2_CMD( void ) { Spi_Test_SeqEndNotification(SPI_SEQ_E2_CMD); }
+static void Spi_Test_SeqEndNotification_E2_CMD2( void ) { Spi_Test_SeqEndNotification(SPI_SEQ_E2_CMD2); }
+static void Spi_Test_SeqEndNotification_E2_READ( void ){ Spi_Test_SeqEndNotification(SPI_SEQ_E2_READ); }
+static void Spi_Test_SeqEndNotification_E2_WRITE( void ){ Spi_Test_SeqEndNotification(SPI_SEQ_E2_WRITE); }
+
+static void Spi_Test_JobEndNotification_E2_CMD( void ){ Spi_Test_JobEndNotification(SPI_JOB_E2_CMD); }
+static void Spi_Test_JobEndNotification_E2_CMD2( void ){ Spi_Test_JobEndNotification(SPI_JOB_E2_CMD2); }
+static void Spi_Test_JobEndNotification_E2_DATA( void ){ Spi_Test_JobEndNotification(SPI_JOB_E2_DATA); }
+static void Spi_Test_JobEndNotification_E2_WREN( void ){ Spi_Test_JobEndNotification(SPI_JOB_E2_WREN); }
+
+#define SPI_SEQ_END_NOTIFICATION NULL
+#define SPI_JOB_END_NOTIFICAITON NULL
+
+// Notifications
+// Seq
+#define SPI_SEQ_E2_CMD_END_NOTIFICATION Spi_Test_SeqEndNotification_E2_CMD
+#define SPI_SEQ_E2_CMD2_END_NOTIFICATION Spi_Test_SeqEndNotification_E2_CMD2
+#define SPI_SEQ_E2_READ_END_NOTIFICATION Spi_Test_SeqEndNotification_E2_READ
+#define SPI_SEQ_E2_WRITE_END_NOTIFICATION Spi_Test_SeqEndNotification_E2_WRITE
+// Jobs
+#define SPI_JOB_E2_CMD_END_NOTIFICATION Spi_Test_JobEndNotification_E2_CMD
+#define SPI_JOB_E2_CMD2_END_NOTIFICATION Spi_Test_JobEndNotification_E2_CMD2
+#define SPI_JOB_E2_DATA_END_NOTIFICATION Spi_Test_JobEndNotification_E2_DATA
+#define SPI_JOB_E2_WREN_END_NOTIFICATION Spi_Test_JobEndNotification_E2_WREN
+
+#else
+#define SPI_SEQ_END_NOTIFICATION NULL
+#define SPI_JOB_END_NOTIFICAITON NULL
+#endif
+
+
+/* SEQUENCES */
+const Spi_SequenceConfigType SpiSequenceConfigData[] =
+{
+ {
+ .SpiSequenceId = SPI_SEQ_E2_CMD, // The EEP read sequence
+ .SpiInterruptibleSequence = 0,
+ .SpiSeqEndNotification = SPI_SEQ_E2_CMD_END_NOTIFICATION,
+ .JobAssignment = { SPI_JOB_E2_CMD,(-1)},
+ },
+ {
+ .SpiSequenceId = SPI_SEQ_E2_CMD2, // The EEP read sequence
+ .SpiInterruptibleSequence = 0,
+ .SpiSeqEndNotification = SPI_SEQ_E2_CMD2_END_NOTIFICATION,
+ .JobAssignment = { SPI_JOB_E2_CMD2,(-1)},
+ },
+ {
+ .SpiSequenceId = SPI_SEQ_E2_READ, // The EEP read sequence
+ .SpiInterruptibleSequence = 0,
+ .SpiSeqEndNotification = SPI_SEQ_E2_READ_END_NOTIFICATION,
+ .JobAssignment = { SPI_JOB_E2_DATA,(-1)},
+ },
+ {
+ .SpiSequenceId = SPI_SEQ_E2_WRITE, // The EEP write sequence
+ .SpiInterruptibleSequence = 0,
+ .SpiSeqEndNotification = SPI_SEQ_E2_WRITE_END_NOTIFICATION,
+ .JobAssignment = { SPI_JOB_E2_DATA,(-1)},
+ },
+
+ // -----------------------------------
+ {
+ .SpiSequenceId = SPI_SEQ_EEP_CMD, // The EEP read sequence
+ .SpiInterruptibleSequence = 0,
+ .SpiSeqEndNotification = SPI_SEQ_END_NOTIFICATION,
+ .JobAssignment = { SPI_JOB_EEP_CMD,(-1)},
+ },
+ {
+ .SpiSequenceId = SPI_SEQ_EEP_CMD2, // The EEP read sequence
+ .SpiInterruptibleSequence = 0,
+ .SpiSeqEndNotification = SPI_SEQ_END_NOTIFICATION,
+ .JobAssignment = { SPI_JOB_EEP_CMD2,(-1)},
+ },
+ {
+ .SpiSequenceId = SPI_SEQ_EEP_READ, // The EEP read sequence
+ .SpiInterruptibleSequence = 0,
+ .SpiSeqEndNotification = SPI_SEQ_END_NOTIFICATION,
+ .JobAssignment = { SPI_JOB_EEP_DATA,(-1)},
+ },
+ {
+ .SpiSequenceId = SPI_SEQ_EEP_WRITE, // The EEP write sequence
+ .SpiInterruptibleSequence = 0,
+ .SpiSeqEndNotification = SPI_SEQ_END_NOTIFICATION,
+ .JobAssignment = { SPI_JOB_EEP_WREN,SPI_JOB_EEP_DATA,(-1)},
+ },
+
+ // -----------------------------------
+
+
+ {
+ .SpiSequenceId = SPI_SEQ_FLASH_CMD, // The EEP write sequence
+ .SpiInterruptibleSequence = 0,
+ .SpiSeqEndNotification = SPI_SEQ_END_NOTIFICATION,
+ .JobAssignment = { SPI_JOB_FLASH_CMD,(-1)},
+ },
+ {
+ .SpiSequenceId = SPI_SEQ_FLASH_CMD2, // The EEP read sequence
+ .SpiInterruptibleSequence = 0,
+ .SpiSeqEndNotification = SPI_SEQ_END_NOTIFICATION,
+ .JobAssignment = { SPI_JOB_FLASH_CMD2,(-1)},
+ },
+ {
+ .SpiSequenceId = SPI_SEQ_FLASH_CMD_DATA, // The EEP write sequence
+ .SpiInterruptibleSequence = 0,
+ .SpiSeqEndNotification = SPI_SEQ_END_NOTIFICATION,
+ .JobAssignment = { SPI_JOB_FLASH_CMD_DATA,(-1)},
+ },
+ {
+ .SpiSequenceId = SPI_SEQ_FLASH_READ, // The EEP write sequence
+ .SpiInterruptibleSequence = 0,
+ .SpiSeqEndNotification = SPI_SEQ_END_NOTIFICATION,
+ .JobAssignment = { SPI_JOB_FLASH_READ,(-1)},
+ },
+ {
+ .SpiSequenceId = SPI_SEQ_FLASH_WRITE, // The EEP write sequence
+ .SpiInterruptibleSequence = 0,
+ .SpiSeqEndNotification = SPI_SEQ_END_NOTIFICATION,
+ .JobAssignment = { SPI_JOB_FLASH_WREN,SPI_JOB_FLASH_DATA,SPI_JOB_FLASH_WRDI,(-1)},
+ },
+ {
+ .SpiSequenceId = SPI_SEQ_FLASH_WRSR, // The EEP write sequence
+ .SpiInterruptibleSequence = 0,
+ .SpiSeqEndNotification = SPI_SEQ_END_NOTIFICATION,
+ .JobAssignment = { SPI_JOB_FLASH_WREN,SPI_JOB_FLASH_WRSR,(-1)},
+ },
+ {
+ .SpiSequenceId = SPI_SEQ_FLASH_ERASE, // The EEP write sequence
+ .SpiInterruptibleSequence = 0,
+ .SpiSeqEndNotification = SPI_SEQ_END_NOTIFICATION,
+ .JobAssignment = { SPI_JOB_FLASH_WREN,SPI_JOB_FLASH_ADDR,SPI_JOB_FLASH_WRDI,(-1)},
+ },
+};
+
+/* JOBS */
+const Spi_JobConfigType SpiJobConfigData[] =
+{
+ {
+ .SpiJobId = SPI_JOB_E2_CMD, // The command job for EEP
+ .SpiHwUnit = DSPI_CTRL_A,
+ .SpiJobPriority = 3,
+ .SpiJobEndNotification = SPI_JOB_E2_CMD_END_NOTIFICATION,
+ .DeviceAssignment = SPI_EXT_DEVICE_A_E2,
+ .ChannelAssignment = { SPI_CH_E2_CMD ,(-1)},
+ },
+ {
+ .SpiJobId = SPI_JOB_E2_CMD2, // The command job for EEP
+ .SpiHwUnit = DSPI_CTRL_A,
+ .SpiJobPriority = 3,
+ .SpiJobEndNotification = SPI_JOB_E2_CMD2_END_NOTIFICATION,
+ .DeviceAssignment = SPI_EXT_DEVICE_A_E2,
+ .ChannelAssignment = { SPI_CH_E2_CMD ,SPI_CH_E2_DATA,(-1)},
+ },
+ {
+ .SpiJobId = SPI_JOB_E2_DATA, // The data job for EEP
+ .SpiHwUnit = DSPI_CTRL_A,
+ .SpiJobPriority = 2,
+ .SpiJobEndNotification = SPI_JOB_E2_DATA_END_NOTIFICATION,
+ .DeviceAssignment = SPI_EXT_DEVICE_A_E2,
+ .ChannelAssignment = { SPI_CH_E2_CMD, SPI_CH_E2_ADDR ,SPI_CH_E2_DATA,(-1)},
+ },
+ {
+ .SpiJobId = SPI_JOB_E2_WREN, // The data job for EEP
+ .SpiHwUnit = DSPI_CTRL_A,
+ .SpiJobPriority = 2,
+ .SpiJobEndNotification = SPI_JOB_E2_WREN_END_NOTIFICATION,
+ .DeviceAssignment = SPI_EXT_DEVICE_A_E2,
+ .ChannelAssignment = { SPI_CH_E2_WREN,(-1)},
+ },
+
+ // -----------------------------------
+
+ {
+ .SpiJobId = SPI_JOB_EEP_CMD, // The command job for EEP
+ .SpiHwUnit = DSPI_CTRL_B,
+ .SpiJobPriority = 3,
+ .SpiJobEndNotification = SPI_JOB_END_NOTIFICAITON,
+ .DeviceAssignment = SPI_EXT_DEVICE_B_E2,
+ .ChannelAssignment = { SPI_CH_EEP_CMD ,(-1)},
+ },
+ {
+ .SpiJobId = SPI_JOB_EEP_CMD2, // The command job for EEP
+ .SpiHwUnit = DSPI_CTRL_B,
+ .SpiJobPriority = 3,
+ .SpiJobEndNotification = SPI_JOB_END_NOTIFICAITON,
+ .DeviceAssignment = SPI_EXT_DEVICE_B_E2,
+ .ChannelAssignment = { SPI_CH_EEP_CMD ,SPI_CH_EEP_DATA,(-1)},
+ },
+ {
+ .SpiJobId = SPI_JOB_EEP_DATA, // The data job for EEP
+ .SpiHwUnit = DSPI_CTRL_B,
+ .SpiJobPriority = 2,
+ .SpiJobEndNotification = SPI_JOB_END_NOTIFICAITON,
+ .DeviceAssignment = SPI_EXT_DEVICE_B_E2,
+ .ChannelAssignment = { SPI_CH_EEP_CMD, SPI_CH_EEP_ADDR ,SPI_CH_EEP_DATA,(-1)},
+ },
+ {
+ .SpiJobId = SPI_JOB_EEP_WREN, // The data job for EEP
+ .SpiHwUnit = DSPI_CTRL_B,
+ .SpiJobPriority = 2,
+ .SpiJobEndNotification = SPI_JOB_END_NOTIFICAITON,
+ .DeviceAssignment = SPI_EXT_DEVICE_B_E2,
+ .ChannelAssignment = { SPI_CH_EEP_WREN,(-1)},
+ },
+
+
+ // -----------------------------------
+ // 8
+ {
+ .SpiJobId = SPI_JOB_FLASH_CMD, // The command job for EEP
+ .SpiHwUnit = DSPI_CTRL_A,
+ .SpiJobPriority = 3,
+ .SpiJobEndNotification = SPI_JOB_END_NOTIFICAITON,
+ .DeviceAssignment = SPI_EXT_DEVICE_A_FLASH,
+ .ChannelAssignment = { SPI_CH_FLASH_CMD ,(-1)},
+ },
+ {
+ .SpiJobId = SPI_JOB_FLASH_CMD2, // The command job for EEP
+ .SpiHwUnit = DSPI_CTRL_A,
+ .SpiJobPriority = 3,
+ .SpiJobEndNotification = SPI_JOB_END_NOTIFICAITON,
+ .DeviceAssignment = SPI_EXT_DEVICE_A_FLASH,
+ .ChannelAssignment = { SPI_CH_FLASH_CMD ,SPI_CH_FLASH_DATA, (-1)},
+ },
+ {
+ .SpiJobId = SPI_JOB_FLASH_CMD_DATA, // The data job for EEP
+ .SpiHwUnit = DSPI_CTRL_A,
+ .SpiJobPriority = 2,
+ .SpiJobEndNotification = SPI_JOB_END_NOTIFICAITON,
+ .DeviceAssignment = SPI_EXT_DEVICE_A_FLASH,
+ .ChannelAssignment = { SPI_CH_FLASH_CMD, SPI_CH_FLASH_DATA,(-1)},
+ },
+ {
+ .SpiJobId = SPI_JOB_FLASH_READ, // The data job for EEP
+ .SpiHwUnit = DSPI_CTRL_A,
+ .SpiJobPriority = 2,
+ .SpiJobEndNotification = SPI_JOB_END_NOTIFICAITON,
+ .DeviceAssignment = SPI_EXT_DEVICE_A_FLASH,
+ .ChannelAssignment = { SPI_CH_FLASH_CMD, SPI_CH_FLASH_ADDR, SPI_CH_FLASH_DATA,(-1)},
+ },
+ {
+ .SpiJobId = SPI_JOB_FLASH_WREN,
+ .SpiHwUnit = DSPI_CTRL_A,
+ .SpiJobPriority = 2,
+ .SpiJobEndNotification = SPI_JOB_END_NOTIFICAITON,
+ .DeviceAssignment = SPI_EXT_DEVICE_A_FLASH,
+ .ChannelAssignment = { SPI_CH_FLASH_WREN,(-1)},
+ },
+ {
+ .SpiJobId = SPI_JOB_FLASH_WRDI,
+ .SpiHwUnit = DSPI_CTRL_A,
+ .SpiJobPriority = 2,
+ .SpiJobEndNotification = SPI_JOB_END_NOTIFICAITON,
+ .DeviceAssignment = SPI_EXT_DEVICE_A_FLASH,
+ .ChannelAssignment = { SPI_CH_FLASH_WRDI,(-1)},
+ },
+ {
+ .SpiJobId = SPI_JOB_FLASH_DATA,
+ .SpiHwUnit = DSPI_CTRL_A,
+ .SpiJobPriority = 2,
+ .SpiJobEndNotification = 0,
+ .DeviceAssignment = SPI_EXT_DEVICE_A_FLASH,
+ .ChannelAssignment = { SPI_CH_FLASH_CMD, SPI_CH_FLASH_ADDR ,SPI_CH_FLASH_DATA,(-1)},
+ },
+ {
+ .SpiJobId = SPI_JOB_FLASH_WRSR,
+ .SpiHwUnit = DSPI_CTRL_A,
+ .SpiJobPriority = 2,
+ .SpiJobEndNotification = 0,
+ .DeviceAssignment = SPI_EXT_DEVICE_A_FLASH,
+ .ChannelAssignment = { SPI_CH_FLASH_WRSR, SPI_CH_FLASH_DATA ,(-1)},
+ },
+ {
+ .SpiJobId = SPI_JOB_FLASH_ADDR,
+ .SpiHwUnit = DSPI_CTRL_A,
+ .SpiJobPriority = 2,
+ .SpiJobEndNotification = 0,
+ .DeviceAssignment = SPI_EXT_DEVICE_A_FLASH,
+ .ChannelAssignment = { SPI_CH_FLASH_CMD, SPI_CH_FLASH_ADDR,(-1)},
+ },
+};
+
+uint32 Spi_GetJobCnt(void ) { return sizeof(SpiJobConfigData)/sizeof(SpiJobConfigData[0]); }
+
+
+/* CHANNELS */
+const Spi_ChannelConfigType SpiChannelConfigData[] =
+{
+ {
+ .SpiChannelId = SPI_CH_E2_CMD,
+ .SpiChannelType = SPI_EB,
+ .SpiDataWidth = 8,
+ .SpiIbNBuffers = 0,
+ .SpiEbMaxLength = SPI_EB_MAX_LENGTH,
+ .SpiDefaultData = 0x00,
+ .SpiDmaNoIncreaseSrc = 0,
+ },
+ {
+ .SpiChannelId = SPI_CH_E2_ADDR,
+ .SpiChannelType = SPI_EB,
+ .SpiDataWidth = 16,
+ .SpiIbNBuffers = 0,
+ .SpiEbMaxLength = SPI_EB_MAX_LENGTH,
+ .SpiDefaultData = 0x0000,
+ .SpiDmaNoIncreaseSrc = 0,
+ },
+ {
+ .SpiChannelId = SPI_CH_E2_WREN,
+ .SpiChannelType = SPI_EB,
+ .SpiDataWidth = 8,
+ .SpiIbNBuffers = 0,
+ .SpiEbMaxLength = SPI_EB_MAX_LENGTH,
+ .SpiDefaultData = 0x00,
+ .SpiDmaNoIncreaseSrc = 0,
+ },
+
+ {
+ .SpiChannelId = SPI_CH_E2_DATA,
+ .SpiChannelType = SPI_EB,
+ .SpiDataWidth = 8,
+ .SpiIbNBuffers = 0,
+ .SpiEbMaxLength = SPI_EB_MAX_LENGTH,
+ .SpiDefaultData = 0x00,
+ .SpiDmaNoIncreaseSrc = 0,
+ },
+
+ // -----------------------------------
+
+ {
+ .SpiChannelId = SPI_CH_EEP_CMD,
+ .SpiChannelType = SPI_EB,
+ .SpiDataWidth = 8,
+ .SpiIbNBuffers = 0,
+ .SpiEbMaxLength = SPI_EB_MAX_LENGTH,
+ .SpiDefaultData = 0x00,
+ .SpiDmaNoIncreaseSrc = 0,
+ },
+ {
+ .SpiChannelId = SPI_CH_EEP_ADDR,
+ .SpiChannelType = SPI_EB,
+ .SpiDataWidth = 16,
+ .SpiIbNBuffers = 0,
+ .SpiEbMaxLength = SPI_EB_MAX_LENGTH,
+ .SpiDefaultData = 0x0000,
+ .SpiDmaNoIncreaseSrc = 0,
+ },
+ {
+ .SpiChannelId = SPI_CH_EEP_WREN,
+ .SpiChannelType = SPI_EB,
+ .SpiDataWidth = 8,
+ .SpiIbNBuffers = 0,
+ .SpiEbMaxLength = 1,
+ .SpiDefaultData = E2_WREN,
+ .SpiDmaNoIncreaseSrc = 0,
+ },
+
+ {
+ .SpiChannelId = SPI_CH_EEP_DATA,
+ .SpiChannelType = SPI_EB,
+ .SpiDataWidth = 8,
+ .SpiIbNBuffers = 0,
+ .SpiEbMaxLength = SPI_EB_MAX_LENGTH,
+ .SpiDefaultData = 0x00,
+ .SpiDmaNoIncreaseSrc = 0,
+ },
+
+ // -----------------------------------
+
+ {
+ .SpiChannelId = SPI_CH_FLASH_CMD,
+ .SpiChannelType = SPI_EB,
+ .SpiDataWidth = 8,
+ .SpiIbNBuffers = 0,
+ .SpiEbMaxLength = SPI_EB_MAX_LENGTH,
+ .SpiDefaultData = 0x00,
+ .SpiDmaNoIncreaseSrc = 0,
+ },
+ {
+ .SpiChannelId = SPI_CH_FLASH_ADDR,
+ .SpiChannelType = SPI_EB,
+ .SpiDataWidth = 8,
+ .SpiIbNBuffers = 0,
+ .SpiEbMaxLength = SPI_EB_MAX_LENGTH,
+ .SpiDefaultData = 0x0000,
+ .SpiDmaNoIncreaseSrc = 0,
+ },
+ {
+ .SpiChannelId = SPI_CH_FLASH_DATA,
+ .SpiChannelType = SPI_EB,
+ .SpiDataWidth = 8,
+ .SpiIbNBuffers = 0,
+ .SpiEbMaxLength = SPI_EB_MAX_LENGTH,
+ .SpiDefaultData = 0x00,
+ .SpiDmaNoIncreaseSrc = 0,
+ },
+ {
+ .SpiChannelId = SPI_CH_FLASH_WREN,
+ .SpiChannelType = SPI_EB,
+ .SpiDataWidth = 8,
+ .SpiIbNBuffers = 0,
+ .SpiEbMaxLength = 1,
+ .SpiDefaultData = FLASH_WREN,
+ .SpiDmaNoIncreaseSrc = 0,
+ },
+ {
+ .SpiChannelId = SPI_CH_FLASH_WRDI,
+ .SpiChannelType = SPI_EB,
+ .SpiDataWidth = 8,
+ .SpiIbNBuffers = 0,
+ .SpiEbMaxLength = 1,
+ .SpiDefaultData = FLASH_WRDI,
+ .SpiDmaNoIncreaseSrc = 0,
+ },
+ {
+ .SpiChannelId = SPI_CH_FLASH_WRSR,
+ .SpiChannelType = SPI_EB,
+ .SpiDataWidth = 8,
+ .SpiIbNBuffers = 0,
+ .SpiEbMaxLength = 1,
+ .SpiDefaultData = FLASH_WRSR,
+ .SpiDmaNoIncreaseSrc = 0,
+ },
+
+ {
+ .SpiChannelId = (-1),
+ }
+};
+
+uint32 Spi_GetChanneCnt(void ) { return sizeof(SpiChannelConfigData)/sizeof(SpiChannelConfigData[0]); }
+
+const Spi_ExternalDeviceType SpiExternalConfigData[] =
+{
+ // SPI_EXT_DEVICE_A_E2
+
+ // E2
+ {
+ .SpiBaudrate = 1000000UL,
+ .SpiCsIdentifier = SPI_A_CS_E2,
+ .SpiCsPolarity = STD_LOW,
+ .SpiDataShiftEdge = SPI_EDGE_LEADING,
+ .SpiEnableCs = 1,
+ .SpiShiftClockIdleLevel = STD_LOW,
+ .SpiTimeClk2Cs = 606, // ns
+ .SpiTimeCs2Clk = 606, // ns
+ },
+ // SPI_EXT_DEVICE_A_FLASH
+ {
+ .SpiBaudrate = 1000000UL,
+ .SpiCsIdentifier = SPI_A_CS_FLASH,
+ .SpiCsPolarity = STD_LOW,
+ .SpiDataShiftEdge = SPI_EDGE_LEADING,
+ .SpiEnableCs = 1,
+ .SpiShiftClockIdleLevel = STD_LOW,
+ .SpiTimeClk2Cs = 606, // ns
+ .SpiTimeCs2Clk = 606, // ns
+ },
+
+ //
+ // SPI_BUS_B
+ //
+
+ // SPI_EXT_DEVICE_B_E2
+ {
+ .SpiBaudrate = 1000000UL,
+ .SpiCsIdentifier = SPI_B_CS_E2,
+ .SpiCsPolarity = STD_LOW,
+ .SpiDataShiftEdge = SPI_EDGE_LEADING,
+ .SpiEnableCs = 1,
+ .SpiShiftClockIdleLevel = STD_LOW,
+ .SpiTimeClk2Cs = 0,
+ .SpiTimeCs2Clk = 0,
+ },
+};
+
+uint32 Spi_GetExternalDeviceCnt(void ) { return sizeof(SpiExternalConfigData)/sizeof(SpiExternalConfigData[0]); }
+
+const Spi_HwConfigType SpiHwConfig[] =
+{
+ {
+ .IsrPriority = 1,
+ .Activated = TRUE,
+ .RxDmaChannel = DMA_DSPI_A_RESULT_CHANNEL,
+ .TxDmaChannel = DMA_DSPI_A_COMMAND_CHANNEL,
+ .PeripheralClock = PERIPHERAL_CLOCK_DSPI_A,
+ },
+ {
+ .IsrPriority = 1,
+ .Activated = TRUE,
+ .RxDmaChannel = DMA_DSPI_B_RESULT_CHANNEL,
+ .TxDmaChannel = DMA_DSPI_B_COMMAND_CHANNEL,
+ .PeripheralClock = PERIPHERAL_CLOCK_DSPI_B,
+ },
+ {
+ .IsrPriority = 1,
+ .Activated = FALSE,
+ .RxDmaChannel = 0,
+ .TxDmaChannel = 0,
+ .PeripheralClock = 0,
+ },
+ {
+ .IsrPriority = 1,
+ .Activated = TRUE,
+ .RxDmaChannel = 0,
+ .TxDmaChannel = 0,
+ .PeripheralClock = 0,
+ },
+};
+
+const Spi_DriverType SpiConfigData =
+{
+ .SpiMaxChannel = SPI_MAX_CHANNEL,
+ .SpiMaxJob = SPI_MAX_JOB,
+ .SpiMaxSequence = SPI_MAX_SEQUENCE,
+ .SpiChannelConfig = &SpiChannelConfigData[0],
+ .SpiSequenceConfig = &SpiSequenceConfigData[0],
+ .SpiJobConfig = &SpiJobConfigData[0],
+ .SpiExternalDevice = &SpiExternalConfigData[0],
+ .SpiHwConfig = &SpiHwConfig[0],
+};
+
--- /dev/null
+
+# ARCH defines
+ARCH=mpc55xx
+ARCH_FAM=ppc
+ARCH_MCU=mpc5516
+
+# CFG (y/n) macros
+CFG=PPC BOOKE E200Z1 MPC55XX MPC5516 BRD_MPC551XSIM SIMULATOR
+
+# What buildable modules does this board have,
+# default or private
+MOD_AVAIL=KERNEL MCU GPT LIN CAN WDG WDGM T32_TERM WINIDEA_TERM
+
+# Needed by us
+MOD_USE=KERNEL MCU
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef CANIF_CFG_H_\r
+#define CANIF_CFG_H_\r
+\r
+#include "Can.h"\r
+\r
+typedef enum {\r
+ CANIF_SOFTFILTER_TYPE_BINARY = 0, // Not supported\r
+ CANIF_SOFTFILTER_TYPE_INDEX, // Not supported\r
+ CANIF_SOFTFILTER_TYPE_LINEAR, // Not supported\r
+ CANIF_SOFTFILTER_TYPE_TABLE, // Not supported\r
+ CANIF_SOFTFILTER_TYPE_MASK, // CanIfCanRxPduCanIdMask in RxPduConfig is used for filtering\r
+} CanIf_SoftwareFilterTypeType;\r
+\r
+typedef enum {\r
+ CANIF_USER_TYPE_CAN_NM,\r
+ CANIF_USER_TYPE_CAN_TP,\r
+ CANIF_USER_TYPE_CAN_PDUR,\r
+ CANIF_USER_TYPE_CAN_SPECIAL,\r
+} CanIf_UserTypeType;\r
+\r
+\r
+\r
+typedef void (*CanIf_FuncTypeCanSpecial)(PduIdType, const uint8 *, uint8, Can_IdType);\r
+\r
+typedef enum {\r
+ CANIF_PDU_TYPE_STATIC = 0,\r
+ CANIF_PDU_TYPE_DYNAMIC // Not supported\r
+} CanIf_PduTypeType;\r
+\r
+typedef enum {\r
+ CANIF_CAN_ID_TYPE_29 = 0,\r
+ CANIF_CAN_ID_TYPE_11\r
+} CanIf_CanIdTypeType;\r
+\r
+/*\r
+ * Public container\r
+ */\r
+#define CANIF_VERSION_INFO_API STD_ON\r
+#define CANIF_DEV_ERROR_DETECT STD_ON\r
+#define CANIF_DLC_CHECK STD_ON\r
+#define CANIF_MULITPLE_DRIVER_SUPPORT STD_OFF // Not supported\r
+#define CANIF_READRXPDU_DATA_API STD_OFF // Not supported\r
+#define CANIF_READRXPDU_NOTIFY_STATUS_API STD_OFF // Not supported\r
+#define CANIF_READTXPDU_NOTIFY_STATUS_API STD_OFF // Not supported\r
+#define CANIF_SETDYNAMICTXID_API STD_OFF // Not supported\r
+#define CANIF_WAKEUP_EVENT_API STD_OFF // Not supported\r
+#define CANIF_TRANSCEIVER_API STD_OFF // Not supported\r
+#define CANIF_TRANSMIT_CANCELLATION STD_OFF // Not supported\r
+\r
+//-------------------------------------------------------------------\r
+\r
+typedef struct {\r
+ void (*CancelTxConfirmation)( void *); // (const Can_PduType *);\r
+ void (*RxIndication)(void *); //(const Can_PduType *);\r
+ void (*ControllerBusOff)(uint8);\r
+ void (*ControllerWakeup)(uint8);\r
+ void (*EcoreError)(uint8,uint32);\r
+} CanIf_CallbackType;\r
+\r
+\r
+\r
+//-------------------------------------------------------------------\r
+/*\r
+ * CanIfHrhRangeConfig container\r
+ */\r
+\r
+typedef struct {\r
+ // Lower CAN Identifier of a receive CAN L-PDU for identifier range\r
+ // definition, in which all CAN Ids shall pass the software filtering. Range: 11\r
+ // Bit for Standard CAN Identifier 29 Bit for Extended CAN Identifer\r
+ uint32 CanIfRxPduLowerCanId;\r
+\r
+ // Upper CAN Identifier of a receive CAN L-PDU for identifier range\r
+ // definition, in which all CAN Ids shall pass the software filtering. Range: 11\r
+ // Bit for Standard CAN Identifier 29 Bit for Extended CAN Identifer\r
+ uint32 CanIfRxPduUpperCanId;\r
+} CanIf_HrhRangeConfigType;\r
+\r
+\r
+\r
+//-------------------------------------------------------------------\r
+/*\r
+ * CanIfInitHrhConfig container\r
+ */\r
+typedef struct {\r
+ // Defines the HRH type i.e, whether its a BasicCan or FullCan. If BasicCan is\r
+ // configured, software filtering is enabled.\r
+ Can_EcoreHohType CanIfHrhType;\r
+\r
+ // Selects the hardware receive objects by using the HRH range/list from\r
+ // CAN Driver configuration to define, for which HRH a software filtering has\r
+ // to be performed at during receive processing. True: Software filtering is\r
+ // enabled False: Software filtering is disabled\r
+ boolean CanIfSoftwareFilterHrh;\r
+\r
+ // Reference to controller Id to which the HRH belongs to. A controller can\r
+ // contain one or more HRHs.\r
+ uint8 CanIfCanControllerHrhIdRef;\r
+\r
+ // The parameter refers to a particular HRH object in the CAN Driver Module\r
+ // configuration. The HRH id is unique in a given CAN Driver. The HRH Ids\r
+ // are defined in the CAN Driver Module and hence it is derived from CAN\r
+ // Driver Configuration.\r
+ Can_EcoreHRHType CanIfHrhIdSymRef ;\r
+\r
+ // Defines the parameters required for configuraing multiple\r
+ // CANID ranges for a given same HRH.\r
+ const CanIf_HrhRangeConfigType *CanIfHrhRangeConfig;\r
+\r
+ // End Of List. Set to TRUE is this is the last object in the list.\r
+ boolean CanIfEcoreEOL;\r
+} CanIf_HrhConfigType;\r
+\r
+//-------------------------------------------------------------------\r
+/*\r
+ * CanIfInitHthConfig container\r
+ */\r
+\r
+typedef struct {\r
+ // Defines the HTH type i.e, whether its a BasicCan or FullCan.\r
+ Can_EcoreHohType CanIfHthType;\r
+\r
+ // Reference to controller Id to which the HTH belongs to. A controller\r
+ // can contain one or more HTHs\r
+ uint8 CanIfCanControllerIdRef;\r
+\r
+ // The parameter refers to a particular HTH object in the CAN Driver Module\r
+ // configuration. The HTH id is unique in a given CAN Driver. The HTH Ids\r
+ // are defined in the CAN Driver Module and hence it is derived from CAN\r
+ // Driver Configuration.\r
+ Can_EcoreHTHType CanIfHthIdSymRef ;\r
+\r
+ // End Of List. Set to TRUE is this is the last object in the list.\r
+ boolean CanIfEcoreEOL;\r
+} CanIf_HthConfigType;\r
+\r
+//-------------------------------------------------------------------\r
+/*\r
+ * CanIfInitHohConfig container\r
+ */\r
+typedef struct {\r
+ // Selects the CAN interface specific configuration setup. This type of external\r
+ // data structure shall contain the post build initialization data for the\r
+ // CAN interface for all underlying CAN Drivers.\r
+ const Can_ConfigSetType *CanConfigSet;\r
+\r
+ // This container contains contiguration parameters for each hardware receive object.\r
+ const CanIf_HrhConfigType *CanIfHrhConfig;\r
+\r
+ // This container contains parameters releated to each HTH\r
+ const CanIf_HthConfigType *CanIfHthConfig;\r
+\r
+ // End Of List. Set to TRUE is this is the last object in the list.\r
+ boolean CanIfEcoreEOL;\r
+} CanIf_InitHohConfigType;\r
+\r
+//-------------------------------------------------------------------\r
+/*\r
+ * CanIfTxPduConfig container\r
+ */\r
+\r
+// This container contains the configuration (parameters) of each transmit\r
+// CAN L-PDU. The SHORT-NAME of "CanIfTxPduConfig" container\r
+// represents the symolic name of Transmit L-PDU.\r
+typedef struct {\r
+ // ECU wide unique, symbolic handle for transmit CAN L-PDU. The\r
+ // CanIfCanTxPduId is configurable at pre-compile and post-built time.\r
+ // Range: 0..max. number of CantTxPduIds PduIdType CanTxPduId;\r
+ PduIdType CanIfTxPduId;\r
+\r
+ // CAN Identifier of transmit CAN L-PDUs used by the CAN Driver for CAN L-\r
+ // PDU transmission. Range: 11 Bit For Standard CAN Identifier ... 29 Bit For\r
+ // Extended CAN identifier\r
+ uint32 CanIfCanTxPduIdCanId;\r
+\r
+ // Data length code (in bytes) of transmit CAN L-PDUs used by the CAN\r
+ // Driver for CAN L-PDU transmission. The data area size of a CAN L-Pdu\r
+ // can have a range from 0 to 8 bytes.\r
+ uint8 CanIfCanTxPduIdDlc;\r
+\r
+ // Defines the type of each transmit CAN L-PDU.\r
+ // DYNAMIC CAN ID is defined at runtime.\r
+ // STATIC CAN ID is defined at compile-time.\r
+ CanIf_PduTypeType CanIfCanTxPduType;\r
+\r
+#if ( CANIF_READTXPDU_NOTIFY_STATUS_API == STD_ON )\r
+ // Enables and disables transmit confirmation for each transmit CAN L-PDU\r
+ // for reading its notification status. True: Enabled False: Disabled\r
+ boolean CanIfReadTxPduNotifyStatus;\r
+#endif\r
+\r
+ // CAN Identifier of transmit CAN L-PDUs used by the CAN Driver for CAN L-\r
+ // PDU transmission.\r
+ // EXTENDED_CAN The CANID is of type Extended (29 bits)\r
+ // STANDARD_CAN The CANID is of type Standard (11 bits)\r
+ CanIf_CanIdTypeType CanIfTxPduIdCanIdType;\r
+\r
+ // Name of target confirmation services to target upper layers (PduR, CanNm\r
+ // and CanTp. If parameter is not configured then no call-out function is\r
+ // provided by the upper layer for this Tx L-PDU.\r
+ void (*CanIfUserTxConfirmation)(PduIdType); /* CANIF 109 */\r
+\r
+ // Handle, that defines the hardware object or the pool of hardware objects\r
+ // configured for transmission. The parameter refers HTH Id, to which the L-\r
+ // PDU belongs to.\r
+ const CanIf_HthConfigType *CanIfCanTxPduHthRef;\r
+\r
+ // Reference to the "global" Pdu structure to allow harmonization of handle\r
+ // IDs in the COM-Stack. ..\r
+ void *PduIdRef;\r
+} CanIf_TxPduConfigType;\r
+\r
+//-------------------------------------------------------------------\r
+/*\r
+ * CanIfRxPduConfig container\r
+ */\r
+\r
+\r
+// This container contains the configuration (parameters) of each receive\r
+// CAN L-PDU. The SHORT-NAME of "CanIfRxPduConfig" container itself\r
+// represents the symolic name of Receive L-PDU.\r
+\r
+typedef struct {\r
+ // ECU wide unique, symbolic handle for receive CAN L-PDU. The\r
+ // CanRxPduId is configurable at pre-compile and post-built time. It shall fulfill\r
+ // ANSI/AUTOSAR definitions for constant defines. Range: 0..max. number\r
+ // of defined CanRxPduIds\r
+ PduIdType CanIfCanRxPduId;\r
+\r
+ // CAN Identifier of Receive CAN L-PDUs used by the CAN Interface. Exa:\r
+ // Software Filtering. Range: 11 Bit For Standard CAN Identifier ... 29 Bit For\r
+ // Extended CAN identifier\r
+ uint32 CanIfCanRxPduCanId;\r
+\r
+ // Data Length code of received CAN L-PDUs used by the CAN Interface.\r
+ // Exa: DLC check. The data area size of a CAN L-PDU can have a range\r
+ // from 0 to 8 bytes. uint8 CanIfCanRxPduDlc;\r
+ uint8 CanIfCanRxPduDlc;\r
+\r
+#if ( CANIF_CANPDUID_READDATA_API == STD_ON )\r
+ // Enables and disables the Rx buffering for reading of received L-PDU data.\r
+ // True: Enabled False: Disabled\r
+ boolean CanIfReadRxPduData;\r
+#endif\r
+\r
+#if ( CANIF_READRXPDU_NOTIF_STATUS_API == STD_ON )\r
+ // CanIfReadRxPduNotifyStatus {CANIF_READRXPDU_NOTIFY_STATUS}\r
+ // Enables and disables receive indication for each receive CAN L-PDU for\r
+ // reading its' notification status. True: Enabled False: Disabled\r
+ boolean CanIfReadRxPduNotifyStatus;\r
+#endif\r
+\r
+ // CAN Identifier of receive CAN L-PDUs used by the CAN Driver for CAN L-\r
+ // PDU transmission.\r
+ // EXTENDED_CAN The CANID is of type Extended (29 bits)\r
+ // STANDARD_CAN The CANID is of type Standard (11 bits)\r
+ CanIf_CanIdTypeType CanIfRxPduIdCanIdType;\r
+\r
+ // This parameter defines the type of the receive indication call-outs called to\r
+ // the corresponding upper layer the used TargetRxPduId belongs to.\r
+ CanIf_UserTypeType CanIfRxUserType;\r
+\r
+ // Name of target indication services to target upper layers (PduRouter,\r
+ // CanNm, CanTp and ComplexDeviceDrivers). If parameter is 0 no call-out\r
+ // function is configured.\r
+ void *CanIfUserRxIndication;\r
+\r
+ // The HRH to which Rx L-PDU belongs to, is referred through this\r
+ // parameter.\r
+ const CanIf_HrhConfigType *CanIfCanRxPduHrhRef;\r
+\r
+ // Reference to the "global" Pdu structure to allow harmonization of handle\r
+ // IDs in the COM-Stack.\r
+ void *PduIdRef;\r
+\r
+ // Defines the type of software filtering that should be used\r
+ // for this receive object.\r
+ CanIf_SoftwareFilterTypeType CanIfSoftwareFilterType;\r
+\r
+ // Acceptance filters, 1 - care, 0 - don't care.\r
+ // Is enabled by the CanIfSoftwareFilterMask in CanIf_HrhConfigType\r
+ // Ecore exension\r
+ uint32 CanIfCanRxPduCanIdMask;\r
+\r
+} CanIf_RxPduConfigType;\r
+\r
+//-------------------------------------------------------------------\r
+\r
+/*\r
+ * CanIfControllerConfig container\r
+ */\r
+\r
+typedef enum {\r
+ CANIF_WAKEUP_SUPPORT_CONTROLLER,\r
+ CANIF_WAKEUP_SUPPORT_NO_WAKEUP,\r
+ CANIF_WAKEUP_SUPPORT_TRANSCEIVER,\r
+} CanIf_WakeupSupportType;\r
+\r
+\r
+// This is the type supplied to CanIf_InitController()\r
+typedef struct {\r
+ CanIf_WakeupSupportType WakeupSupport; // Not used\r
+\r
+ CanControllerIdType CanIfControllerIdRef;\r
+\r
+ const char CanIfDriverNameRef[8]; // Not used\r
+\r
+ const Can_ControllerConfigType *CanIfInitControllerRef;\r
+} CanIf_ControllerConfigType;\r
+\r
+//-------------------------------------------------------------------\r
+/*\r
+ * CanIfTransceiverDrvConfig container\r
+ */\r
+\r
+typedef struct {\r
+ boolean TrcvWakeupNotification;\r
+ uint8 TrcvIdRef;\r
+} CanIf_TransceiverDrvConfigType;\r
+\r
+\r
+typedef struct {\r
+ uint32 todo;\r
+} CanIf_TransceiverConfigType;\r
+\r
+// Callout functions with respect to the upper layers. This callout functions\r
+// defined in this container are common to all configured underlying CAN\r
+// Drivers / CAN Transceiver Drivers.\r
+typedef struct {\r
+ // Name of target BusOff notification services to target upper layers\r
+ // (PduRouter, CanNm, CanTp and ComplexDeviceDrivers).\r
+ // Multiplicity: 1\r
+ void (*CanIfBusOffNotification)(uint8 Controller);\r
+\r
+ // Name of target wakeup notification services to target upper layers\r
+ // e.g Ecu_StateManager. If parameter is 0\r
+ // no call-out function is configured.\r
+ // Multiplicity: 0..1\r
+ void (*CanIfWakeUpNotification)();\r
+\r
+ // Name of target wakeup validation notification services to target upper\r
+ // layers (ECU State Manager). If parameter is 0 no call-out function is\r
+ // configured.\r
+ // Multiplicity: 0..1\r
+ void (*CanIfWakeupValidNotification)();\r
+\r
+ // Ecore ext.\r
+ void (*CanIfErrorNotificaton)(uint8,Can_EcoreErrorType);\r
+\r
+} CanIf_DispatchConfigType;\r
+\r
+// This container contains the references to the configuration setup of each\r
+// underlying CAN driver.\r
+\r
+typedef struct {\r
+ // Selects the CAN Interface specific configuration setup. This type of the\r
+ // external data structure shall contain the post build initialization data for the\r
+ // CAN Interface for all underlying CAN Dirvers. constant to CanIf_ConfigType\r
+ uint32 CanIfConfigSet;\r
+\r
+ uint32 CanIfNumberOfCanRxPduIds;\r
+ uint32 CanIfNumberOfCanTXPduIds;\r
+ uint32 CanIfNumberOfDynamicCanTXPduIds;\r
+\r
+ //\r
+ // Containers\r
+ //\r
+\r
+ // This container contains the reference to the configuration\r
+ // setup of each underlying CAN driver.\r
+ // Multiplicity: 0..*\r
+ const CanIf_InitHohConfigType *CanIfHohConfigPtr;\r
+\r
+ // This container contains the configuration (parameters) of each\r
+ // receive CAN L-PDU. The SHORT-NAME of\r
+ // "CanIfRxPduConfig" container itself represents the symolic\r
+ // name of Receive L-PDU.\r
+ // Multiplicity: 0..*\r
+ const CanIf_RxPduConfigType *CanIfRxPduConfigPtr;\r
+\r
+ // This container contains the configuration (parameters) of each\r
+ // transmit CAN L-PDU. The SHORT-NAME of\r
+ // "CanIfTxPduConfig" container represents the symolic name of\r
+ // Transmit L-PDU.\r
+ // Multiplicity: 0..*\r
+ const CanIf_TxPduConfigType *CanIfTxPduConfigPtr;\r
+\r
+} CanIf_InitConfigType;\r
+\r
+\r
+typedef struct {\r
+ // This container contains the configuration (parameters) of all\r
+ // addressed CAN controllers by each underlying CAN driver.\r
+ // Multiplicity: 1..*\r
+ const CanIf_ControllerConfigType *ControllerConfig;\r
+\r
+ // Callout functions with respect to the upper layers. This callout\r
+ // functions defined in this container are common to all\r
+ // configured underlying CAN Drivers / CAN Transceiver Drivers\r
+ const CanIf_DispatchConfigType *DispatchConfig;\r
+\r
+ // This container contains the init parameters of the CAN\r
+ // Interface.\r
+ // Multiplicity: 1..*\r
+ const CanIf_InitConfigType *InitConfig;\r
+\r
+ // This container contains the configuration (parameters) of all\r
+ // addressed CAN transceivers by each underlying CAN\r
+ // Transceiver Driver.\r
+ // Multiplicity: 1..*\r
+ const CanIf_TransceiverConfigType *TransceiverConfig;\r
+} CanIf_ConfigType;\r
+\r
+\r
+extern CanIf_ConfigType CanIf_Config;\r
+\r
+#endif\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef CAN_CFG_H_\r
+#define CAN_CFG_H_\r
+\r
+// Number of controller configs\r
+#define CAN_ECORE_CTRL_CONFIG_CNT 2\r
+\r
+#define CAN_DEV_ERROR_DETECT STD_ON\r
+#define CAN_VERSION_INFO_API STD_ON\r
+#define CAN_MULTIPLEXED_TRANSMISSION STD_ON // Makes no differens in the code\r
+#define CAN_WAKEUP_SUPPORT STD_OFF // Not supported\r
+#define CAN_HW_TRANSMIT_CANCELLATION STD_OFF // Not supported\r
+\r
+// loop cnt.. very strange timeout\r
+#define CAN_TIMEOUT_DURATION 100\r
+\r
+#define INTERRUPT 0\r
+#define POLLING 1\r
+\r
+// Can controller\r
+#define CAN_BUSOFF_PROCESSING INTERRUPT // INTERRUPT/POLLING\r
+#define CAN_CONTROLLER_ACTIVATION OFF\r
+#define CAN_CONTROLLER_BAUD_RATE 125000\r
+#define CAN_DRIVER_CONTROLLER_ID 0\r
+#define CAN_CONTROLLER_PROP_SEG 4\r
+#define CAN_CONTROLLER_PHASE1_SEG 4\r
+#define CAN_CONTROLLER_PHASE2_SEG 4\r
+#define CAN_CONTROLLER_TIME_QUANTA 4\r
+#define CAN_RX_PROCESSING INTERRUPT\r
+#define CAN_TX_PROCESSING INTERRUPT\r
+#define CAN_WAKEUP_PROCESSING INTERRUPT\r
+\r
+typedef enum {\r
+ CAN_CTRL_A = 0,\r
+ CAN_CTRL_B,\r
+ CAN_CTRL_C,\r
+ CAN_CTRL_D,\r
+ CAN_CTRL_E,\r
+ CAN_CTRL_F,\r
+ CAN_CONTROLLER_CNT \r
+}CanControllerIdType;\r
+\r
+typedef enum {\r
+ CAN_ID_TYPE_EXTENDED,\r
+ CAN_ID_TYPE_MIXED,\r
+ CAN_ID_TYPE_STANDARD,\r
+} Can_IdTypeType;\r
+\r
+typedef enum {\r
+ CAN_OBJECT_TYPE_RECEIVE,\r
+ CAN_OBJECT_TYPE_TRANSMIT,\r
+} Can_ObjectTypeType;\r
+\r
+typedef enum {\r
+ CAN_ECORE_HANDLE_TYPE_BASIC,\r
+ CAN_ECORE_HANDLE_TYPE_FULL\r
+} Can_EcoreHohType;\r
+\r
+// HTH definitions\r
+// Due to effiency: Start with index 0 and don't use any holes in the enumeration\r
+typedef enum {\r
+ CAN_HTH_A_1 = 0,\r
+ CAN_HTH_C_1,\r
+ NUM_OF_HTHS\r
+} Can_EcoreHTHType;\r
+\r
+// HRH definitions\r
+// Due to effiency: Start with index 0 and don't use any holes in the enumeration\r
+typedef enum {\r
+ CAN_HRH_A_1 = 0,\r
+ CAN_HRH_C_1,\r
+ NUM_OF_HRHS\r
+} Can_EcoreHRHType;\r
+\r
+// Non-standard type\r
+typedef struct {\r
+ void (*CancelTxConfirmation)( const Can_PduType *);\r
+ void (*RxIndication)( uint8 ,Can_IdType ,uint8 , const uint8 * );\r
+ void (*ControllerBusOff)(uint8);\r
+ void (*TxConfirmation)(PduIdType);\r
+ void (*ControllerWakeup)(uint8);\r
+ void (*EcoreError)(uint8,Can_EcoreErrorType);\r
+} Can_CallbackType;\r
+\r
+/*\r
+ * CanGeneral Container\r
+ */\r
+\r
+// This container contains the parameters related each CAN Driver Unit.\r
+typedef struct {\r
+ // Specifies the InstanceId of this module instance. If only one instance is\r
+ // present it shall have the Id 0\r
+ int CanIndex;\r
+\r
+#if 0 // This is only used by the config tool\r
+ // This parameter describes the period for cyclic call to\r
+ // Can_MainFunction_Busoff. Unit is seconds.\r
+ float CanMainFunctionBusoffPeriod;\r
+ // This parameter describes the period for cyclic call to\r
+ // Can_MainFunction_Read. Unit is seconds.\r
+ float CanMainFunctionReadPeriod;\r
+ // This parameter describes the period for cyclic call to\r
+ // Can_MainFunction_Wakeup. Unit is seconds.\r
+ float CanMainFunctionWakeupPeriod;\r
+ // This parameter describes the period for cyclic call to\r
+ // Can_MainFunction_Write. Unit is seconds.\r
+ float CanMainFunctionWritePeriod;\r
+#endif\r
+\r
+\r
+#if ( CAN_TIMEOUT_DURATION == STD_ON )\r
+ // Specifies the maximum number of loops for blocking function until a\r
+ // timeout is raised in short term wait loops.\r
+ uint32 CanTimeoutDurationFactor;\r
+#endif\r
+\r
+} Can_GeneralType;\r
+\r
+\r
+/*\r
+ * CanFilterMask container\r
+ */\r
+typedef uint32 Can_FilterMaskType;\r
+\r
+/*\r
+ * CanHardwareObject container\r
+ */\r
+\r
+//This container contains the configuration (parameters) of CAN Hardware\r
+//Objects.\r
+typedef struct Can_HardwareObjectStruct {\r
+ // Specifies the type (Full-CAN or Basic-CAN) of a hardware object.\r
+ Can_EcoreHohType CanHandleType;\r
+\r
+ // Specifies whether the IdValue is of type - standard identifier - extended\r
+ // identifier - mixed mode ImplementationType: Can_IdType\r
+ Can_IdTypeType CanIdType;\r
+\r
+ // Specifies (together with the filter mask) the identifiers range that passes\r
+ // the hardware filter.\r
+ uint32 CanIdValue;\r
+\r
+ // Holds the handle ID of HRH or HTH. The value of this parameter is unique\r
+ // in a given CAN Driver, and it should start with 0 and continue without any\r
+ // gaps. The HRH and HTH Ids are defined under two different name-spaces.\r
+ // Example: HRH0-0, HRH1-1, HTH0-2, HTH1-3\r
+ uint32 CanObjectId;\r
+\r
+ // Specifies if the HardwareObject is used as Transmit or as Receive object\r
+ Can_ObjectTypeType CanObjectType;\r
+\r
+ // Reference to the filter mask that is used for hardware filtering togerther\r
+ // with the CAN_ID_VALUE\r
+ Can_FilterMaskType *CanFilterMaskRef;\r
+\r
+ // A "1" in this mask tells the driver that that HW Message Box should be\r
+ // occupied by this Hoh. A "1" in bit 31(ppc) occupies Mb 0 in HW.\r
+ uint32 CanEcoreMbMask;\r
+\r
+ // End Of List. Set to TRUE is this is the last object in the list.\r
+ boolean CanEcoreEOL;\r
+\r
+} Can_HardwareObjectType;\r
+\r
+\r
+/*\r
+ * CanController container\r
+ */\r
+typedef enum {\r
+ CAN_ECORE_PROCESS_TYPE_INTERRUPT,\r
+ CAN_ECORE_PROCESS_TYPE_POLLING,\r
+} Can_EcoreProcessType;\r
+\r
+typedef struct {\r
+\r
+ // Enables / disables API Can_MainFunction_BusOff() for handling busoff\r
+ // events in polling mode.\r
+ // INTERRUPT or POLLING\r
+ Can_EcoreProcessType CanBusOffProcessing;\r
+\r
+ // Defines if a CAN controller is used in the configuration.\r
+ boolean CanControllerActivation;\r
+\r
+ // Specifies the buadrate of the controller in kbps.\r
+ uint32 CanControllerBaudRate;\r
+\r
+ // This parameter provides the controller ID which is unique in a given CAN\r
+ // Driver. The value for this parameter starts with 0 and continue without any\r
+ // gaps.\r
+ CanControllerIdType CanControllerId;\r
+\r
+ // Specifies propagation delay in time quantas.\r
+ uint32 CanControllerPropSeg;\r
+\r
+ // Specifies phase segment 1 in time quantas.\r
+ uint32 CanControllerSeg1;\r
+\r
+ // Specifies phase segment 2 in time quantas.\r
+ uint32 CanControllerSeg2;\r
+\r
+ // Specifies the time quanta for the controller. The calculation of the resulting\r
+ // prescaler value depending on module clocking and time quanta shall be\r
+ // done offline Hardware specific.\r
+ uint32 CanControllerTimeQuanta;\r
+\r
+ // Enables / disables API Can_MainFunction_Read() for handling PDU\r
+ // reception events in polling mode.\r
+ Can_EcoreProcessType CanRxProcessing;\r
+\r
+ // Enables / disables API Can_MainFunction_Write() for handling PDU\r
+ // transmission events in polling mode.\r
+ Can_EcoreProcessType CanTxProcessing;\r
+\r
+ // Enables / disables API Can_MainFunction_Wakeup() for handling wakeup\r
+ // events in polling mode.\r
+ Can_EcoreProcessType CanWakeupProcessing;\r
+\r
+ // Reference to the CPU clock configuration, which is set in the MCU driver\r
+ // configuration\r
+ uint32 CanCpuClockRef;\r
+\r
+ // This parameter contains a reference to the Wakeup Source for this\r
+ // controller as defined in the ECU State Manager. Implementation Type:\r
+ // reference to EcuM_WakeupSourceType\r
+ uint32 CanWakeupSourceRef;\r
+\r
+ //\r
+ // Ecore stuff\r
+ //\r
+\r
+ // List of Hoh id's that belong to this controller\r
+ const Can_HardwareObjectType *CanEcoreHoh;\r
+\r
+ boolean CanEcoreLoopback;\r
+\r
+ // Set this to use the fifo\r
+ boolean CanEcoreFifo;\r
+\r
+} Can_ControllerConfigType;\r
+\r
+\r
+\r
+/*\r
+ * CanConfigSet container\r
+ */\r
+typedef struct {\r
+ const Can_ControllerConfigType *CanController;\r
+ \r
+ // Callbacks( Extension )\r
+ const Can_CallbackType *CanCallbacks;\r
+} Can_ConfigSetType;\r
+\r
+\r
+typedef struct {\r
+ // This is the multiple configuration set container for CAN Driver\r
+ // Multiplicity 1..*\r
+ const Can_ConfigSetType *CanConfigSet;\r
+ // This container contains the parameters related each CAN\r
+ // Driver Unit.\r
+ // Multiplicity 1..*\r
+ const Can_GeneralType *CanGeneral;\r
+\r
+\r
+} Can_ConfigType;\r
+\r
+\r
+extern const Can_ConfigType CanConfigData;\r
+extern const Can_ControllerConfigType CanControllerConfigData[];\r
+extern const Can_ConfigSetType Can_ConfigSet;\r
+\r
+\r
+#endif /*CAN_CFG_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include <stdlib.h>\r
+#include "Can.h"\r
+#include "CanIf_Cbk.h"\r
+\r
+/* CONFIGURATION TEMPLATE\r
+ * ------------------------------------------------------------------\r
+ *\r
+ * The following template configures:\r
+ * - 2 CAN controllers, CAN_CTRL_A and CAN_CNTR_C\r
+ * - Callbacks are configured to call standard CanIf callbacks\r
+ *\r
+ * CAN_CTRL_A\r
+ * - 125K baudrate\r
+ * - Extended 11-bit ID's\r
+ * - Rx/Tx are interrupt based\r
+ * - Both Rx(MB 16->24) and Tx(MB 24->31) Hoh's are of type BASIC\r
+ *\r
+ * CAN_CTRL_C\r
+ * - 125K baudrate\r
+ * - Standard 29-bit ID's\r
+ * - Rx/Tx are interrupt based\r
+ * - Both Rx(MB 16->24) and Tx(MB 24->31) Hoh's are of type BASIC\r
+ * *\r
+ */\r
+\r
+// Accept everything = 0\r
+Can_FilterMaskType Can_FilterMaskConfigData = 0;\r
+\r
+// HOH:s for CAN_CTRL_A\r
+const Can_HardwareObjectType CanHardwareObjectConfig_CTRL_A[] =\r
+{\r
+ {\r
+ .CanHandleType = CAN_ECORE_HANDLE_TYPE_BASIC,\r
+ .CanIdType = CAN_ID_TYPE_EXTENDED,\r
+ .CanObjectType = CAN_OBJECT_TYPE_RECEIVE,\r
+ .CanObjectId = CAN_HRH_A_1,\r
+ .CanFilterMaskRef = &Can_FilterMaskConfigData,\r
+ // Ecore\r
+ .CanEcoreMbMask = 0x00ff0000,\r
+ .CanEcoreEOL = 0,\r
+ },\r
+ {\r
+ .CanHandleType = CAN_ECORE_HANDLE_TYPE_BASIC,\r
+ .CanIdType = CAN_ID_TYPE_EXTENDED,\r
+ .CanObjectType = CAN_OBJECT_TYPE_TRANSMIT,\r
+ .CanObjectId = CAN_HTH_A_1,\r
+ .CanFilterMaskRef = &Can_FilterMaskConfigData,\r
+ // Ecore\r
+ .CanEcoreMbMask = 0xff000000,\r
+ .CanEcoreEOL = 1,\r
+ },\r
+};\r
+\r
+// HOH:s for CAN_CTRL_C\r
+const Can_HardwareObjectType CanHardwareObjectConfig_CTRL_C[] =\r
+{\r
+ {\r
+ .CanHandleType = CAN_ECORE_HANDLE_TYPE_BASIC,\r
+ .CanIdType = CAN_ID_TYPE_STANDARD,\r
+ .CanObjectType = CAN_OBJECT_TYPE_RECEIVE,\r
+ .CanObjectId = CAN_HRH_C_1,\r
+ .CanFilterMaskRef = &Can_FilterMaskConfigData,\r
+ // Ecore\r
+ .CanEcoreMbMask = 0x00ff0000,\r
+ .CanEcoreEOL = 0,\r
+ },\r
+ {\r
+ .CanHandleType = CAN_ECORE_HANDLE_TYPE_BASIC,\r
+ .CanIdType = CAN_ID_TYPE_STANDARD,\r
+ .CanObjectType = CAN_OBJECT_TYPE_TRANSMIT,\r
+ .CanObjectId = CAN_HTH_C_1,\r
+ .CanFilterMaskRef = &Can_FilterMaskConfigData,\r
+ // Ecore\r
+ .CanEcoreMbMask = 0xff000000,\r
+ .CanEcoreEOL = 1,\r
+ },\r
+};\r
+\r
+/* CAN controller data for ALL controllers that are to be configured\r
+ * See Autosar release 3.0 specification for more info\r
+ */\r
+const Can_ControllerConfigType CanControllerConfigData[] =\r
+{\r
+ {\r
+ .CanControllerActivation = TRUE,\r
+ .CanControllerBaudRate = 125,\r
+ .CanControllerId = CAN_CTRL_A,\r
+ .CanControllerPropSeg = 4,\r
+ .CanControllerSeg1 = 4,\r
+ .CanControllerSeg2 = 4,\r
+ .CanBusOffProcessing = CAN_ECORE_PROCESS_TYPE_INTERRUPT,\r
+ .CanRxProcessing = CAN_ECORE_PROCESS_TYPE_INTERRUPT,\r
+ .CanTxProcessing = CAN_ECORE_PROCESS_TYPE_INTERRUPT,\r
+ .CanWakeupProcessing = CAN_ECORE_PROCESS_TYPE_INTERRUPT,\r
+ .CanCpuClockRef = PERIPHERAL_CLOCK_FLEXCAN_A,\r
+ // Ecore\r
+ .CanEcoreHoh = &CanHardwareObjectConfig_CTRL_A[0],\r
+ .CanEcoreLoopback = 0,\r
+ .CanEcoreFifo = 0,\r
+\r
+ },{\r
+ .CanControllerActivation = TRUE,\r
+ .CanControllerBaudRate = 125,\r
+ .CanControllerId = CAN_CTRL_C,\r
+ .CanControllerPropSeg = 4,\r
+ .CanControllerSeg1 = 4,\r
+ .CanControllerSeg2 = 4,\r
+ .CanBusOffProcessing = CAN_ECORE_PROCESS_TYPE_INTERRUPT,\r
+ .CanRxProcessing = CAN_ECORE_PROCESS_TYPE_INTERRUPT,\r
+ .CanTxProcessing = CAN_ECORE_PROCESS_TYPE_INTERRUPT,\r
+ .CanWakeupProcessing = CAN_ECORE_PROCESS_TYPE_INTERRUPT,\r
+ .CanCpuClockRef = PERIPHERAL_CLOCK_FLEXCAN_C,\r
+ // Ecore\r
+ .CanEcoreHoh = &CanHardwareObjectConfig_CTRL_C[0],\r
+ .CanEcoreLoopback = 1,\r
+ .CanEcoreFifo = 0,\r
+ }\r
+};\r
+\r
+/* Callbacks for the can drivers\r
+ * See Autosar release 3.0 specification for more info\r
+ */\r
+const Can_CallbackType CanCallbackConfigData = {\r
+ NULL, //CanIf_CancelTxConfirmation,\r
+ CanIf_RxIndication,\r
+ CanIf_ControllerBusOff,\r
+ CanIf_TxConfirmation,\r
+ NULL, //CanIf_ControllerWakeup,\r
+ CanIf_EcoreError,\r
+};\r
+\r
+/* Configset configuration information\r
+ * See Autosar release 3.0 specification for more info\r
+ */\r
+const Can_ConfigSetType CanConfigSetData =\r
+{\r
+ .CanController = CanControllerConfigData,\r
+ .CanCallbacks = &CanCallbackConfigData,\r
+};\r
+\r
+/* Top config struct passed to Can_Init() */\r
+const Can_ConfigType CanConfigData = {\r
+ .CanConfigSet = &CanConfigSetData,\r
+};\r
+\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef COM_CFG_H_\r
+#define COM_CFG_H_\r
+\r
+#define COM_MODULE_ID 20\r
+#define COM_INSTANCE_ID 1\r
+\r
+#define COM_DEV_ERROR_DETECT\r
+\r
+#define COM_MAX_NR_IPDU 30\r
+#define COM_MAX_NR_SIGNAL 30\r
+#define COM_MAX_NR_GROUPSIGNAL 30\r
+\r
+#define COM_MAX_NR_SIGNALS_PER_IPDU 10\r
+#define COM_MAX_NR_SIGNALGROUPS_PER_IPDU 10\r
+#define COM_MAX_NR_SIGNALS_PER_SIGNAL_GROUP 10\r
+\r
+\r
+#define COM_E_INVALID_FILTER_CONFIGURATION 101\r
+#define COM_E_INITIALIZATION_FAILED 102\r
+#define COM_E_INVALID_SIGNAL_CONFIGURATION 103\r
+#define COM_INVALID_PDU_ID 104\r
+#define COM_ERROR_SIGNAL_IS_SIGNALGROUP 105\r
+\r
+#define COM_E_TOO_MANY_IPDU 106\r
+#define COM_E_TOO_MANY_SIGNAL 107\r
+#define COM_E_TOO_MANY_GROUPSIGNAL 108\r
+\r
+#define CPU_ENDIANESS BIG_ENDIAN\r
+\r
+/*\r
+ * ComGeneral pre-compile time configuration parameters.
+ */\r
+#define ComConfigurationTimeBase\r
+#define ComConfigurationUseDet\r
+#define ComVersionInfoApi\r
+\r
+\r
+\r
+\r
+\r
+#endif /*COM_CFG_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*\r
+ * Development Error Tracer driver\r
+ *\r
+ * Specification: Autosar v2.0.1, Final\r
+ *\r
+ */\r
+#ifndef _DET_CFG_H_\r
+#define _DET_CFG_H_\r
+\r
+#define DET_ENABLE_CALLBACKS STD_ON // Enable to use callback on errors\r
+#define DET_USE_RAMLOG STD_ON // Enable to log DET errors to ramlog\r
+#define DET_WRAP_RAMLOG STD_ON // The ramlog wraps around when reaching the end\r
+#define DET_USE_STDERR STD_OFF // Enable to get DET errors on stderr\r
+\r
+#define DET_DEINIT_API STD_ON // Enable/Disable the Det_DeInit function\r
+\r
+#define DET_RAMLOG_SIZE (32) // Number of entries in ramlog\r
+#define DET_NUMBER_OF_CALLBACKS (5) // Number of callbacks\r
+\r
+#endif /*_DET_CFG_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+/* Link time config */\r
+\r
+#include "Std_Types.h"\r
+#include "Os.h"\r
+#include "Mcu.h"\r
+#include "Gpt.h"\r
+#include <assert.h>\r
+#include "Cpu.h"\r
+\r
+//#include "ComM.h"\r
+//#include "WdgM.h"\r
+\r
+//#include "Dem.h"\r
+//#include "Det.h"\r
+//#include "NvM.h"\r
+//#include "rte.h"\r
+\r
+extern void os_exception_IVPR();\r
+extern void os_exception_IVOR10();\r
+// The OS startup hook\r
+\r
+#if 0\r
+void StartupHook( void ) {\r
+\r
+ // There a several things we need to connect here\r
+ // * counter id for the system counter is 0\r
+ // * that need to be attached to Gpt\r
+ // --> We need to tell the OS that what Gpt channel it's\r
+ // counter is connected to.\r
+\r
+ // TODO: We need counter information here..\r
+ // How do I get that information from the OS???\r
+\r
+ //? GetCounterAlarmBase()\r
+\r
+// Gpt_StartTimer(GPT_CHANNEL_DEC, 100 );\r
+// Gpt_EnableNotification(GPT_CHANNEL_DEC);\r
+// Gpt_SetMode(0);\r
+}\r
+#endif\r
+\r
+extern void os_system_timer( void );\r
+\r
+void EcuM_Init( void );\r
+int main( void ) {\r
+\r
+ EcuM_Init();\r
+ return 0;\r
+}\r
+\r
+void EcuM_Init( void ) {\r
+ /* Call all mandatory interfaces, see 8.7.1 */\r
+\r
+ /* I'm giving up on the MCU configuration. From what I\r
+ * can tell from the documentation the Mcu_Init()\r
+ */\r
+\r
+#if 0\r
+ ComM_ConfigType comMConfig;\r
+ WdgM_ConfigType wdgmConfig;\r
+#endif\r
+\r
+// Startup I\r
+ {\r
+ const Mcu_ConfigType mcuConfig;\r
+ Mcu_Init(&mcuConfig);\r
+ }\r
+// Mcu_GetResetReason();\r
+#if 0\r
+ Det_Init();\r
+ Dem_PreInit();\r
+ EcuM_AL_DriverInitOne();\r
+#endif\r
+\r
+\r
+ {\r
+ // If we assume the OS will require SYSTEM_COUNTER to function.\r
+ // We should either get the values from SYSTEM_COUNTER\r
+\r
+ Gpt_ConfigType GptConfigData[] =\r
+ { {\r
+ .GptChannelId = GPT_CHANNEL_DEC,\r
+ .GptChannelMode = GPT_MODE_CONTINUOUS,\r
+ .GptChannelClkSrc = 0,\r
+ .GptNotification = os_system_timer,\r
+ }\r
+ };\r
+ Gpt_Init(&GptConfigData[0]);\r
+\r
+ // The timer is actually started in StartupHook()\r
+ }\r
+\r
+\r
+// EcuM_SelectShutdownTarget(target,mode);\r
+ StartOS(0);\r
+// Startup II\r
+ //EcuM_AL_DriverInitTwo();\r
+\r
+#if 0\r
+ ComM_Init(&comMConfig);\r
+ WdgM_Init(&wdgmConfig);\r
+ NvM_Init();\r
+ NvM_ReadAll();\r
+ NvM_WriteAll();\r
+ NvM_CancelWriteAll();\r
+\r
+ Dem_PreInit();\r
+ Dem_Init();\r
+ {\r
+ Dem_EventIdType id = 0;\r
+ Dem_EventStatusType status = 0;\r
+ Dem_ReportErrorStatus(id,status);\r
+ }\r
+ Rte_Start();\r
+ Rte_Stop();\r
+#endif\r
+\r
+ ShutdownOS(E_OK);\r
+ EnableAllInterrupts();\r
+ DisableAllInterrupts();\r
+\r
+// Det_ReportError(1,2,3,4);\r
+}\r
+\r
+void EcuM_Shutdown( void ) {\r
+\r
+}\r
+\r
+void EcuM_GetVersionInfo( Std_VersionInfoType *versioninfo ) {\r
+\r
+}\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+#include "Gpt.h"\r
+#include "Gpt_Cfg.h"\r
+#include <stdlib.h>\r
+\r
+#if defined(USE_KERNEL)\r
+extern void OsTick( void );\r
+#endif\r
+\r
+const Gpt_ConfigType GptConfigData[] =\r
+{\r
+#if defined(USE_KERNEL)\r
+ {\r
+ .GptChannelId = GPT_CHANNEL_DEC,\r
+ .GptChannelMode = GPT_MODE_CONTINUOUS,\r
+ .GptChannelClkSrc = 0,\r
+ .GptNotification = OsTick,\r
+ .GptEnableWakeup = FALSE,\r
+ .GptChannelPrescale = 0,\r
+ },\r
+#endif\r
+ {\r
+ // Last channel in list\r
+ .GptChannelId = GPT_CHANNEL_ILL,\r
+ }\r
+};\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef GPT_CFG_H_\r
+#define GPT_CFG_H_\r
+#include "Std_Types.h"\r
+\r
+\r
+// Pre-compile only\r
+#define GPT_VARIANT_PC STD_OFF\r
+// Mix of pre-compile and post-build\r
+#define GPT_VARIANT_PB STD_ON\r
+\r
+//#define DEC_TEST\r
+//#define GPT_TEST\r
+\r
+/* Std PIT channels */\r
+#define GPT_CHANNEL_RTI 0\r
+#define GPT_CHANNEL_PIT_0 GPT_CHANNEL_RTI\r
+#define GPT_CHANNEL_PIT_1 1\r
+#define GPT_CHANNEL_PIT_2 2\r
+#define GPT_CHANNEL_PIT_3 3\r
+#define GPT_CHANNEL_PIT_4 4\r
+#define GPT_CHANNEL_PIT_5 5\r
+#define GPT_CHANNEL_PIT_6 6\r
+#define GPT_CHANNEL_PIT_7 7\r
+#define GPT_CHANNEL_PIT_8 8\r
+\r
+#define GPT_PIT_CNT (GPT_CHANNEL_PIT_8 + 1)\r
+\r
+/* Mcu channels */\r
+#define GPT_CHANNEL_DEC 9\r
+\r
+#define GPT_CHANNEL_CNT (GPT_CHANNEL_DEC+1)\r
+\r
+// Illegal channel\r
+#define GPT_CHANNEL_ILL 31\r
+\r
+\r
+#define GPT_DEV_ERROR_DETECT STD_ON\r
+// Enables/Disables wakeup source reporting\r
+#define GPT_REPORT_WAKEUP_SOURCE STD_OFF\r
+\r
+#define GPT_DEINIT_API STD_ON\r
+#define GPT_ENABLE_DISABLE_NOTIFICATION_API STD_ON\r
+#define GPT_TIME_REMAINING_API STD_ON\r
+#define GPT_TIME_ELAPSED_API STD_ON\r
+#define GPT_VERSION_INFO_API STD_ON\r
+// TODO: EcuM things missing to get this API working properly\r
+#define GPT_WAKEUP_FUNCTIONALITY_API STD_OFF\r
+\r
+\r
+// This container contains the channel-wide configuration (parameters) of the\r
+// GPT Driver\r
+typedef struct {\r
+ // GPT187: The GPT module specific clock input for the timer unit can\r
+ // statically be configured and allows to select different clock sources\r
+ // (external clock, internal GPT specific clock) per channel\r
+ uint32 GptChannelClkSrc;\r
+\r
+ // Channel Id of the GPT channel. This value will be assigned to the symbolic\r
+ // name derived of the GptChannelConfiguration container short name.\r
+ Gpt_ChannelType GptChannelId;\r
+\r
+ // Specifies the behaviour of the timerchannel after the timeout has expired\r
+ Gpt_ChannelMode GptChannelMode;\r
+\r
+ // Function pointer to callback function\r
+ void (*GptNotification)();\r
+\r
+ // GPT module specific prescaler factor per channel\r
+ uint32 GptChannelPrescale;\r
+\r
+ // GPT188: Enables wakeup capability of CPU for a channel when timeout\r
+ // period expires. This might be different to enabling the notification\r
+ // depending on hardware capabilities\r
+ boolean GptEnableWakeup;\r
+} Gpt_ConfigType;\r
+\r
+extern const Gpt_ConfigType GptConfigData[];\r
+\r
+#endif /*GPT_CFG_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef MCU_CFG_C_\r
+#define MCU_CFG_C_\r
+\r
+#include "Mcu_Cfg.h"\r
+\r
+Mcu_RamSectorSettingConfigType Mcu_RamSectorSettingConfigData[] = {\r
+ {\r
+ // This parameter shall represent the Data pre-setting to be initialized\r
+ .McuRamDefaultValue = 0,\r
+\r
+ // This parameter shall represent the MCU RAM section base address\r
+ .McuRamSectionBaseAddress = 0,\r
+\r
+ // This parameter shall represent the MCU RAM Section size\r
+ .McuRamSectionSize = 0xFF,\r
+ }\r
+};\r
+\r
+Mcu_ClockSettingConfigType Mcu_ClockSettingConfigData[] =\r
+{\r
+ {\r
+ .McuClockReferencePoint = 8000000UL,\r
+ .PllEprediv = 1,\r
+ .PllEmfd = 104,\r
+ .PllErfd = 5,\r
+ },\r
+ {\r
+ .McuClockReferencePoint = 16000000UL,\r
+ .PllEprediv = 3,\r
+ .PllEmfd = 83,\r
+ .PllErfd = 5,\r
+ }\r
+};\r
+\r
+\r
+ const Mcu_ConfigType McuConfigData[] = {\r
+ {\r
+ // Enables/Disables clock failure notification. In case this feature is not supported\r
+ // by HW the setting should be disabled.\r
+ .McuClockSrcFailureNotification = 0,\r
+\r
+ // This parameter shall represent the number of Modes available for the\r
+ // MCU. calculationFormula = Number of configured McuModeSettingConf\r
+ .McuNumberOfMcuModes = 1, /* NOT USED */\r
+\r
+ // This parameter shall represent the number of RAM sectors available for\r
+ // the MCU. calculationFormula = Number of configured McuRamSectorSet-\r
+ // tingConf\r
+ .McuRamSectors = 1,\r
+\r
+ // This parameter shall represent the number of clock setting available for\r
+ // the MCU.\r
+ .McuClockSettings = MCU_NBR_OF_CLOCKS,\r
+\r
+ // This parameter relates to the MCU specific reset configuration. This ap-\r
+ // plies to the function Mcu_PerformReset, which performs a microcontroller\r
+ // reset using the hardware feature of the microcontroller.\r
+ .McuResetSetting = 0, /* NOT USED */\r
+\r
+ // This container contains the configuration (parameters) for the\r
+ // Clock settings of the MCU. Please see MCU031 for more in-\r
+ // formation on the MCU clock settings.\r
+ .McuClockSettingConfig = &Mcu_ClockSettingConfigData[0],\r
+\r
+ // This container contains the configuration (parameters) for the\r
+ // Mode setting of the MCU. Please see MCU035 for more infor-\r
+ // mation on the MCU mode settings.\r
+ .McuModeSettingConfig = 0,\r
+\r
+ // This container contains the configuration (parameters) for the\r
+ // RAM Sector setting. Please see MCU030 for more information\r
+ // on RAM sec-tor settings.\r
+ .McuRamSectorSettingConfig = &Mcu_RamSectorSettingConfigData[0],\r
+ },\r
+};\r
+\r
+#endif /*MCU_CFG_C_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef MCU_CFG_H_\r
+#define MCU_CFG_H_\r
+\r
+#include "mpc55xx.h"\r
+\r
+#define MCU_DEV_ERROR_DETECT STD_ON\r
+// Preprocessor switch to enable / disable the use of the function\r
+// Mcu_PerformReset()\r
+#define MCU_PERFORM_RESET_API STD_ON\r
+\r
+#define MCU_VERSION_INFO_API STD_ON\r
+\r
+#include "Std_Types.h"\r
+\r
+/* FMPLL modes( atleast in 5553/5554 ) */\r
+\r
+typedef enum {\r
+ MCU_FMPLL_BYPASS = 0,\r
+ MCU_FMPLL_EXTERNAL_REF,\r
+ MCU_FMPLL_EXTERNAL_REF_NO_FM,\r
+ MCU_FMPLL_DUAL_CONTROLLER_MODE,\r
+} Mcu_FMPLLmode_t;\r
+\r
+typedef enum {\r
+ MCU_CLOCKTYPE_EXT_REF_80MHZ = 0,\r
+ MCU_CLOCKTYPE_EXT_REF_66MHZ,\r
+ MCU_NBR_OF_CLOCKS,\r
+ //MCU_CLOCKTYPE_EXTERNAL_REF,\r
+ //MCU_CLOCKTYPE_EXTERNAL_REF_NO_FM,\r
+ //MCU_CLOCKTYPE_DUAL_CONTROLLER_MODE,\r
+} Mcu_ClockType;\r
+\r
+typedef struct {\r
+ // This container defines a reference point in the Mcu Clock tree\r
+ // It defines the frequency which then can be used by other modules\r
+ // as an input value. Lower multiplicity is 1, as even in the\r
+ // simplest case (only one frequency is used), there is one\r
+ // frequency to be defined.\r
+ uint32 McuClockReferencePoint;\r
+\r
+ // Phase locked loop configuration parameters for MPC551x.\r
+ uint8 PllEprediv;\r
+ uint8 PllEmfd;\r
+ uint8 PllErfd;\r
+} Mcu_ClockSettingConfigType;\r
+\r
+typedef struct {\r
+ // The parameter represents the MCU Mode settings\r
+ uint32 McuMode;\r
+} Mcu_ModeSettingConfigType;\r
+\r
+typedef struct {\r
+ // This parameter shall represent the Data pre-setting to be initialized\r
+ uint32 McuRamDefaultValue;\r
+\r
+ // This parameter shall represent the MCU RAM section base address\r
+ uint32 McuRamSectionBaseAddress;\r
+\r
+ // This parameter shall represent the MCU RAM Section size\r
+ uint32 McuRamSectionSize;\r
+\r
+} Mcu_RamSectorSettingConfigType;\r
+\r
+\r
+// This container defines a reference point in the Mcu Clock tree. It defines\r
+// the frequency which then can be used by other modules as an input value.\r
+// Lower multiplicity is 1, as even in the simplest case (only one frequency is\r
+// used), there is one frequency to be defined.\r
+typedef struct {\r
+\r
+ // This is the frequency for the specific instance of the McuClockReference-\r
+ // Point container. It shall be givn in Hz.\r
+ uint32 McuClockReferencePointFrequency;\r
+\r
+} Mcu_ClockReferencePointType;\r
+\r
+typedef struct {\r
+ // Enables/Disables clock failure notification. In case this feature is not supported\r
+ // by HW the setting should be disabled.\r
+ uint8 McuClockSrcFailureNotification;\r
+\r
+ // This parameter shall represent the number of Modes available for the\r
+ // MCU. calculationFormula = Number of configured McuModeSettingConf\r
+ uint8 McuNumberOfMcuModes;\r
+\r
+ // This parameter shall represent the number of RAM sectors available for\r
+ // the MCU. calculationFormula = Number of configured McuRamSectorSet-\r
+ // tingConf\r
+ uint8 McuRamSectors;\r
+\r
+ // This parameter shall represent the number of clock setting available for\r
+ // the MCU.\r
+ uint8 McuClockSettings;\r
+\r
+ // This parameter defines the default clock settings that should be used\r
+ // It is an index into the McuClockSettingsConfig\r
+ Mcu_ClockType McuDefaultClockSettings;\r
+\r
+ // This parameter relates to the MCU specific reset configuration. This ap-\r
+ // plies to the function Mcu_PerformReset, which performs a microcontroller\r
+ // reset using the hardware feature of the microcontroller.\r
+ uint32 McuResetSetting;\r
+\r
+ // This container contains the configuration (parameters) for the\r
+ // Clock settings of the MCU. Please see MCU031 for more in-\r
+ // formation on the MCU clock settings.\r
+ Mcu_ClockSettingConfigType * McuClockSettingConfig;\r
+\r
+ // This container contains the configuration (parameters) for the\r
+ // Mode setting of the MCU. Please see MCU035 for more information\r
+ // on the MCU mode settings.\r
+ Mcu_ModeSettingConfigType *McuModeSettingConfig;\r
+\r
+ // This container contains the configuration (parameters) for the\r
+ // RAM Sector setting. Please see MCU030 for more information\r
+ // on RAM sec-tor settings.\r
+ Mcu_RamSectorSettingConfigType *McuRamSectorSettingConfig;\r
+\r
+} Mcu_ConfigType;\r
+\r
+extern const Mcu_ConfigType McuConfigData[];\r
+\r
+#define MCU_DEFAULT_CONFIG McuConfigData[0]\r
+\r
+#endif /*MCU_CFG_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef MEMIF_CFG_H_
+#define MEMIF_CFG_H_
+
+// TODO. include FEE and EA modules
+
+
+
+#endif /*MEMIF_CFG_H_*/
--- /dev/null
+
+# ARCH defines
+ARCH=mpc55xx
+ARCH_FAM=ppc
+ARCH_MCU=mpc5554
+
+# CFG (y/n) macros
+CFG=PPC BOOKE SPE E200Z6 MPC55XX MPC5554 BRD_MPC5554SIM SIMULATOR
+
+# What buildable modules does this board have,
+# default or private
+MOD_AVAIL+=KERNEL MCU GPT LIN CAN COM WDG WDGM T32_TERM WINIDEA_TERM
+
+# Needed by kernel
+MOD_USE+=KERNEL MCU
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*\r
+ * Development Error Tracer driver\r
+ *\r
+ * Specification: Autosar v2.0.1, Final\r
+ *\r
+ */\r
+#ifndef _DET_CFG_H_\r
+#define _DET_CFG_H_\r
+\r
+#define DET_ENABLE_CALLBACKS STD_ON // Enable to use callback on errors\r
+#define DET_USE_RAMLOG STD_ON // Enable to log DET errors to ramlog\r
+#define DET_WRAP_RAMLOG STD_ON // The ramlog wraps around when reaching the end\r
+#define DET_USE_STDERR STD_OFF // Enable to get DET errors on stderr\r
+\r
+#define DET_DEINIT_API STD_ON // Enable/Disable the Det_DeInit function\r
+\r
+#define DET_RAMLOG_SIZE (32) // Number of entries in ramlog\r
+#define DET_NUMBER_OF_CALLBACKS (5) // Number of callbacks\r
+\r
+#endif /*_DET_CFG_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef MCU_CFG_C_\r
+#define MCU_CFG_C_\r
+\r
+#include "Mcu_Cfg.h"\r
+\r
+Mcu_RamSectorSettingConfigType Mcu_RamSectorSettingConfigData[] = {\r
+ {\r
+ // This parameter shall represent the Data pre-setting to be initialized\r
+ .McuRamDefaultValue = 0,\r
+\r
+ // This parameter shall represent the MCU RAM section base address\r
+ .McuRamSectionBaseAddress = 0,\r
+\r
+ // This parameter shall represent the MCU RAM Section size\r
+ .McuRamSectionSize = 0xFF,\r
+ }\r
+};\r
+\r
+Mcu_ClockSettingConfigType Mcu_ClockSettingConfigData[] =\r
+{\r
+ {\r
+ .McuClockReferencePoint = 8000000UL,\r
+ .PllEprediv = 1,\r
+ .PllEmfd = 104,\r
+ .PllErfd = 5,\r
+ },\r
+ {\r
+ .McuClockReferencePoint = 16000000UL,\r
+ .PllEprediv = 3,\r
+ .PllEmfd = 83,\r
+ .PllErfd = 5,\r
+ }\r
+};\r
+\r
+\r
+ const Mcu_ConfigType McuConfigData[] = {\r
+ {\r
+ // Enables/Disables clock failure notification. In case this feature is not supported\r
+ // by HW the setting should be disabled.\r
+ .McuClockSrcFailureNotification = 0,\r
+\r
+ // This parameter shall represent the number of Modes available for the\r
+ // MCU. calculationFormula = Number of configured McuModeSettingConf\r
+ .McuNumberOfMcuModes = 1, /* NOT USED */\r
+\r
+ // This parameter shall represent the number of RAM sectors available for\r
+ // the MCU. calculationFormula = Number of configured McuRamSectorSet-\r
+ // tingConf\r
+ .McuRamSectors = 1,\r
+\r
+ // This parameter shall represent the number of clock setting available for\r
+ // the MCU.\r
+ .McuClockSettings = MCU_NBR_OF_CLOCKS,\r
+\r
+ // This parameter relates to the MCU specific reset configuration. This ap-\r
+ // plies to the function Mcu_PerformReset, which performs a microcontroller\r
+ // reset using the hardware feature of the microcontroller.\r
+ .McuResetSetting = 0, /* NOT USED */\r
+\r
+ // This container contains the configuration (parameters) for the\r
+ // Clock settings of the MCU. Please see MCU031 for more in-\r
+ // formation on the MCU clock settings.\r
+ .McuClockSettingConfig = &Mcu_ClockSettingConfigData[0],\r
+\r
+ // This container contains the configuration (parameters) for the\r
+ // Mode setting of the MCU. Please see MCU035 for more infor-\r
+ // mation on the MCU mode settings.\r
+ .McuModeSettingConfig = 0,\r
+\r
+ // This container contains the configuration (parameters) for the\r
+ // RAM Sector setting. Please see MCU030 for more information\r
+ // on RAM sec-tor settings.\r
+ .McuRamSectorSettingConfig = &Mcu_RamSectorSettingConfigData[0],\r
+ },\r
+};\r
+\r
+#endif /*MCU_CFG_C_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef MCU_CFG_H_\r
+#define MCU_CFG_H_\r
+\r
+#include "mpc55xx.h"\r
+\r
+#define MCU_DEV_ERROR_DETECT STD_ON\r
+// Preprocessor switch to enable / disable the use of the function\r
+// Mcu_PerformReset()\r
+#define MCU_PERFORM_RESET_API STD_ON\r
+\r
+#define MCU_VERSION_INFO_API STD_ON\r
+\r
+#include "Std_Types.h"\r
+\r
+/* FMPLL modes( atleast in 5553/5554 ) */\r
+\r
+typedef enum {\r
+ MCU_FMPLL_BYPASS = 0,\r
+ MCU_FMPLL_EXTERNAL_REF,\r
+ MCU_FMPLL_EXTERNAL_REF_NO_FM,\r
+ MCU_FMPLL_DUAL_CONTROLLER_MODE,\r
+} Mcu_FMPLLmode_t;\r
+\r
+typedef enum {\r
+ MCU_CLOCKTYPE_EXT_REF_80MHZ = 0,\r
+ MCU_CLOCKTYPE_EXT_REF_66MHZ,\r
+ MCU_NBR_OF_CLOCKS,\r
+ //MCU_CLOCKTYPE_EXTERNAL_REF,\r
+ //MCU_CLOCKTYPE_EXTERNAL_REF_NO_FM,\r
+ //MCU_CLOCKTYPE_DUAL_CONTROLLER_MODE,\r
+} Mcu_ClockType;\r
+\r
+typedef struct {\r
+ // This container defines a reference point in the Mcu Clock tree\r
+ // It defines the frequency which then can be used by other modules\r
+ // as an input value. Lower multiplicity is 1, as even in the\r
+ // simplest case (only one frequency is used), there is one\r
+ // frequency to be defined.\r
+ uint32 McuClockReferencePoint;\r
+\r
+ // Phase locked loop configuration parameters for MPC551x.\r
+ uint8 PllEprediv;\r
+ uint8 PllEmfd;\r
+ uint8 PllErfd;\r
+} Mcu_ClockSettingConfigType;\r
+\r
+typedef struct {\r
+ // The parameter represents the MCU Mode settings\r
+ uint32 McuMode;\r
+} Mcu_ModeSettingConfigType;\r
+\r
+typedef struct {\r
+ // This parameter shall represent the Data pre-setting to be initialized\r
+ uint32 McuRamDefaultValue;\r
+\r
+ // This parameter shall represent the MCU RAM section base address\r
+ uint32 McuRamSectionBaseAddress;\r
+\r
+ // This parameter shall represent the MCU RAM Section size\r
+ uint32 McuRamSectionSize;\r
+\r
+} Mcu_RamSectorSettingConfigType;\r
+\r
+\r
+// This container defines a reference point in the Mcu Clock tree. It defines\r
+// the frequency which then can be used by other modules as an input value.\r
+// Lower multiplicity is 1, as even in the simplest case (only one frequency is\r
+// used), there is one frequency to be defined.\r
+typedef struct {\r
+\r
+ // This is the frequency for the specific instance of the McuClockReference-\r
+ // Point container. It shall be givn in Hz.\r
+ uint32 McuClockReferencePointFrequency;\r
+\r
+} Mcu_ClockReferencePointType;\r
+\r
+typedef struct {\r
+ // Enables/Disables clock failure notification. In case this feature is not supported\r
+ // by HW the setting should be disabled.\r
+ uint8 McuClockSrcFailureNotification;\r
+\r
+ // This parameter shall represent the number of Modes available for the\r
+ // MCU. calculationFormula = Number of configured McuModeSettingConf\r
+ uint8 McuNumberOfMcuModes;\r
+\r
+ // This parameter shall represent the number of RAM sectors available for\r
+ // the MCU. calculationFormula = Number of configured McuRamSectorSet-\r
+ // tingConf\r
+ uint8 McuRamSectors;\r
+\r
+ // This parameter shall represent the number of clock setting available for\r
+ // the MCU.\r
+ uint8 McuClockSettings;\r
+\r
+ // This parameter defines the default clock settings that should be used\r
+ // It is an index into the McuClockSettingsConfig\r
+ Mcu_ClockType McuDefaultClockSettings;\r
+\r
+ // This parameter relates to the MCU specific reset configuration. This ap-\r
+ // plies to the function Mcu_PerformReset, which performs a microcontroller\r
+ // reset using the hardware feature of the microcontroller.\r
+ uint32 McuResetSetting;\r
+\r
+ // This container contains the configuration (parameters) for the\r
+ // Clock settings of the MCU. Please see MCU031 for more in-\r
+ // formation on the MCU clock settings.\r
+ Mcu_ClockSettingConfigType * McuClockSettingConfig;\r
+\r
+ // This container contains the configuration (parameters) for the\r
+ // Mode setting of the MCU. Please see MCU035 for more information\r
+ // on the MCU mode settings.\r
+ Mcu_ModeSettingConfigType *McuModeSettingConfig;\r
+\r
+ // This container contains the configuration (parameters) for the\r
+ // RAM Sector setting. Please see MCU030 for more information\r
+ // on RAM sec-tor settings.\r
+ Mcu_RamSectorSettingConfigType *McuRamSectorSettingConfig;\r
+\r
+} Mcu_ConfigType;\r
+\r
+extern const Mcu_ConfigType McuConfigData[];\r
+\r
+#define MCU_DEFAULT_CONFIG McuConfigData[0]\r
+\r
+#endif /*MCU_CFG_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef MEMIF_CFG_H_
+#define MEMIF_CFG_H_
+
+// TODO. include FEE and EA modules
+
+
+
+#endif /*MEMIF_CFG_H_*/
--- /dev/null
+
+# ARCH defines
+ARCH=mpc55xx
+ARCH_FAM=ppc
+ARCH_MCU=mpc5567
+
+# CFG (y/n) macros
+CFG=PPC BOOKE E200Z6 MPC55XX MPC5567 BRD_MPC5567QRTECH SPE
+
+# What buildable modules does this board have,
+# default or private
+MOD_AVAIL=KERNEL MCU WDG WDGM PORT DIO WDG WDGM T32_TERM WINIDEA_TERM PWM CAN CANIF COM ADC DMA
+
+# Needed by us
+MOD_USE=KERNEL MCU
+
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*\r
+ * config.h\r
+ *\r
+ * Created on: 2009-jul-08\r
+ * Author: mahi\r
+ */\r
+\r
+#ifndef CONFIG_H_\r
+#define CONFIG_H_\r
+\r
+/* For makefile's only (used to get the directory search paths right) */\r
+#define ARCH mpc55xx\r
+#define ARCH_FAM ppc\r
+#define ARCH_MCU mpc5567\r
+/*\r
+ * CPU and board\r
+ */\r
+#define CFG_PPC 1\r
+#define CFG_BOOKE 1\r
+#define CFG_E200Z6 1\r
+#define CFG_MPC55XX 1\r
+#define CFG_MPC5567 1\r
+\r
+#define USE_KERNEL 1\r
+#define USE_MCU 1\r
+\r
+\r
+/*\r
+ * Misc\r
+ */\r
+//#define USE_T32_TERM 1\r
+//#define CFG_CONSOLE_T32 1\r
+#define USE_WINIDEA_TERM 1\r
+#define CFG_CONSOLE_WINIDEA 1\r
+\r
+#define USE_PROTECTIONHOOK 1\r
+#define USE_STARTUPHOOK 1\r
+#define USE_SHUTDOWNHOOK 1\r
+#define USE_ERRORHOOK 1\r
+#define USE_PRETASKHOOK 1\r
+#define USE_POSTTASKHOOK 1\r
+\r
+#endif /* CONFIG_H_ */\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include "Adc.h"\r
+#include "Dma.h"\r
+#include "mpc5516.h"\r
+\r
+const struct tcd_t AdcGroupDMACommandConfig [ADC_NBR_OF_GROUPS];\r
+const struct tcd_t AdcGroupDMAResultConfig [ADC_NBR_OF_GROUPS];\r
+\r
+Adc_GroupStatus AdcGroupStatus[ADC_NBR_OF_GROUPS];\r
+\r
+/* Configuration goes here. */\r
+void Adc_Group0Notification (void)\r
+{\r
+}\r
+\r
+void Adc_Group1Notification (void)\r
+{\r
+}\r
+\r
+const Adc_HWConfigurationType AdcHWUnitConfiguration =\r
+{\r
+ .hwUnitId = 0,\r
+ .adcPrescale = ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_8,\r
+ .clockSource = ADC_SYSTEM_CLOCK,\r
+};\r
+\r
+const Adc_ChannelConfigurationType AdcChannelConfiguration [ADC_NBR_OF_CHANNELS] =\r
+{\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_DISABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+};\r
+\r
+const Adc_ChannelType Adc_Group0ChannelList[ADC_NBR_OF_GROUP0_CHANNELS] =\r
+{\r
+ ADC_CH1, ADC_CH2, ADC_CH3, ADC_CH4, ADC_CH5, ADC_CH6, ADC_CH7\r
+};\r
+\r
+const Adc_ChannelType Adc_Group1ChannelList[ADC_NBR_OF_GROUP1_CHANNELS] =\r
+{\r
+ ADC_CH0, ADC_CH2, ADC_CH3, ADC_CH4\r
+};\r
+\r
+const Adc_ChannelType Adc_Group2ChannelList[ADC_NBR_OF_GROUP2_CHANNELS] =\r
+{\r
+ ADC_CH0, ADC_CH1, ADC_CH2\r
+};\r
+\r
+const Adc_ChannelType Adc_Group3ChannelList[ADC_NBR_OF_GROUP3_CHANNELS] =\r
+{\r
+ ADC_CH0, ADC_CH1, ADC_CH2\r
+};\r
+\r
+/* Ram buffers for command and result queues. These are located here in the\r
+ configuration to be able to reconfigure system without recompiling the\r
+ drivers. */\r
+Adc_ValueGroupType Adc_Group0Buffer [sizeof(Adc_Group0ChannelList)/sizeof(Adc_Group0ChannelList[0])];\r
+Adc_CommandType Adc_Group0Commands [sizeof(Adc_Group0ChannelList)/sizeof(Adc_Group0ChannelList[0])];\r
+\r
+Adc_ValueGroupType Adc_Group1Buffer [sizeof(Adc_Group1ChannelList)/sizeof(Adc_Group1ChannelList[0])];\r
+Adc_CommandType Adc_Group1Commands [sizeof(Adc_Group1ChannelList)/sizeof(Adc_Group1ChannelList[0])];\r
+\r
+Adc_ValueGroupType Adc_Group2Buffer [sizeof(Adc_Group2ChannelList)/sizeof(Adc_Group2ChannelList[0])];\r
+Adc_CommandType Adc_Group2Commands [sizeof(Adc_Group2ChannelList)/sizeof(Adc_Group2ChannelList[0])];\r
+\r
+Adc_ValueGroupType Adc_Group3Buffer [sizeof(Adc_Group3ChannelList)/sizeof(Adc_Group3ChannelList[0])];\r
+Adc_CommandType Adc_Group3Commands [sizeof(Adc_Group3ChannelList)/sizeof(Adc_Group3ChannelList[0])];\r
+\r
+\r
+const Adc_GroupDefType AdcGroupConfiguration [] =\r
+{\r
+ { .accessMode = ADC_ACCESS_MODE_SINGLE, .conversionMode = ADC_CONV_MODE_ONESHOT,\r
+ .triggerSrc = ADC_TRIGG_SRC_SW, .hwTriggerSignal = ADC_NO_HW_TRIG,\r
+ .hwTriggerTimer = ADC_NO_TIMER,\r
+ .groupCallback = Adc_Group0Notification,\r
+ .streamBufferMode = ADC_NO_STREAMING, .streamNumSamples = 0,\r
+ .channelList = Adc_Group0ChannelList,\r
+ .resultBuffer = Adc_Group0Buffer,\r
+ .commandBuffer = Adc_Group0Commands,\r
+ .numberOfChannels = sizeof(Adc_Group0Commands)/sizeof(Adc_Group0Commands[0]),\r
+ .status = &AdcGroupStatus[ADC_GROUP0],\r
+ .dmaCommandChannel = DMA_ADC_GROUP0_COMMAND_CHANNEL,\r
+ .dmaResultChannel = DMA_ADC_GROUP0_RESULT_CHANNEL,\r
+ .groupDMACommands = &AdcGroupDMACommandConfig[ADC_GROUP0],\r
+ .groupDMAResults = &AdcGroupDMAResultConfig[ADC_GROUP0]},\r
+\r
+ { .accessMode = ADC_ACCESS_MODE_SINGLE, .conversionMode = ADC_CONV_MODE_CONTINOUS,\r
+ .triggerSrc = ADC_TRIGG_SRC_SW, .hwTriggerSignal = ADC_NO_HW_TRIG,\r
+ .hwTriggerTimer = ADC_NO_TIMER,\r
+ .groupCallback = Adc_Group1Notification,\r
+ .streamBufferMode = ADC_NO_STREAMING, .streamNumSamples = 0,\r
+ .channelList = Adc_Group1ChannelList,\r
+ .resultBuffer = Adc_Group1Buffer,\r
+ .commandBuffer = Adc_Group1Commands,\r
+ .numberOfChannels = sizeof(Adc_Group1Commands)/sizeof(Adc_Group1Commands[0]),\r
+ .status = &AdcGroupStatus[ADC_GROUP1],\r
+ .dmaCommandChannel = DMA_ADC_GROUP1_COMMAND_CHANNEL,\r
+ .dmaResultChannel = DMA_ADC_GROUP1_RESULT_CHANNEL,\r
+ .groupDMACommands = &AdcGroupDMACommandConfig[ADC_GROUP1],\r
+ .groupDMAResults = &AdcGroupDMAResultConfig[ADC_GROUP1]}\r
+};\r
+\r
+\r
+/******************************************************************/\r
+/* */\r
+/* End of user configuration area. DO NOT modify the code below!! */\r
+/* */\r
+/******************************************************************/\r
+const Adc_ConfigType AdcConfig [] =\r
+{\r
+ {\r
+ .hwConfigPtr = &AdcHWUnitConfiguration,\r
+ .channelConfigPtr = AdcChannelConfiguration,\r
+ .nbrOfChannels = sizeof(AdcChannelConfiguration)/sizeof(AdcChannelConfiguration[0]),\r
+ .groupConfigPtr = AdcGroupConfiguration,\r
+ .nbrOfGroups = sizeof(AdcGroupConfiguration)/sizeof(AdcGroupConfiguration[0])}\r
+};\r
+\r
+/* DMA configuration. */\r
+const struct tcd_t AdcGroupDMACommandConfig [ADC_NBR_OF_GROUPS] =\r
+{\r
+ {\r
+ .SADDR = (uint32_t)Adc_Group0Commands,\r
+ .SMOD = 0,\r
+ .SSIZE = DMA_TRANSFER_SIZE_32BITS,\r
+ .DMOD = 0,\r
+ .DSIZE = DMA_TRANSFER_SIZE_32BITS,\r
+ .SOFF = sizeof(Adc_CommandType),\r
+ .NBYTES = sizeof(Adc_CommandType),\r
+ .SLAST = -sizeof(Adc_Group0Commands),\r
+ .DADDR = (vint32_t)&EQADC.CFPR[ADC_GROUP0].R,\r
+ .CITERE_LINK = 0,\r
+ .CITER = sizeof(Adc_Group0Commands)/sizeof(Adc_Group0Commands[0]),\r
+ .DOFF = 0,\r
+ .DLAST_SGA = 0,\r
+ .BITERE_LINK = 0,\r
+ .BITER = sizeof(Adc_Group0Commands)/sizeof(Adc_Group0Commands[0]),\r
+ .BWC = 0,\r
+ .MAJORLINKCH = 0,\r
+ .DONE = 0,\r
+ .ACTIVE = 0,\r
+ .MAJORE_LINK = 0,\r
+ .E_SG = 0,\r
+ .D_REQ = 0,\r
+ .INT_HALF = 0,\r
+ .INT_MAJ = 0,\r
+ .START = 0\r
+ },\r
+ {\r
+ .SADDR = (uint32_t)Adc_Group1Commands,\r
+ .SMOD = 0,\r
+ .SSIZE = DMA_TRANSFER_SIZE_32BITS,\r
+ .DMOD = 0,\r
+ .DSIZE = DMA_TRANSFER_SIZE_32BITS,\r
+ .SOFF = sizeof(Adc_CommandType),\r
+ .NBYTES = sizeof(Adc_CommandType),\r
+ .SLAST = -sizeof(Adc_Group1Commands),\r
+ .DADDR = (vint32_t)&EQADC.CFPR[ADC_GROUP1].R,\r
+ .CITERE_LINK = 0,\r
+ .CITER = sizeof(Adc_Group1Commands)/sizeof(Adc_Group1Commands[0]),\r
+ .DOFF = 0,\r
+ .DLAST_SGA = 0,\r
+ .BITERE_LINK = 0,\r
+ .BITER = sizeof(Adc_Group1Commands)/sizeof(Adc_Group1Commands[0]),\r
+ .BWC = 0,\r
+ .MAJORLINKCH = 0,\r
+ .DONE = 0,\r
+ .ACTIVE = 0,\r
+ .MAJORE_LINK = 0,\r
+ .E_SG = 0,\r
+ .D_REQ = 0,\r
+ .INT_HALF = 0,\r
+ .INT_MAJ = 0,\r
+ .START = 0\r
+ }\r
+};\r
+\r
+const struct tcd_t AdcGroupDMAResultConfig [ADC_NBR_OF_GROUPS]=\r
+{\r
+ {\r
+ .SADDR = (vint32_t)&EQADC.RFPR[ADC_GROUP0].R + 2,\r
+ .SMOD = 0,\r
+ .SSIZE = DMA_TRANSFER_SIZE_16BITS,\r
+ .DMOD = 0,\r
+ .DSIZE = DMA_TRANSFER_SIZE_16BITS,\r
+ .SOFF = 0,\r
+ .NBYTES = sizeof(Adc_ValueGroupType),\r
+ .SLAST = 0,\r
+ .DADDR = (uint32_t)Adc_Group0Buffer,\r
+ .CITERE_LINK = 0,\r
+ .CITER = sizeof(Adc_Group0Buffer)/sizeof(Adc_Group0Buffer[0]),\r
+ .DOFF = sizeof(Adc_ValueGroupType),\r
+ .DLAST_SGA = -sizeof(Adc_Group0Buffer),\r
+ .BITERE_LINK = 0,\r
+ .BITER = sizeof(Adc_Group0Buffer)/sizeof(Adc_Group0Buffer[0]),\r
+ .BWC = 0,\r
+ .MAJORLINKCH = 0,\r
+ .DONE = 0,\r
+ .ACTIVE = 0,\r
+ .MAJORE_LINK = 0,\r
+ .E_SG = 0,\r
+ .D_REQ = 0,\r
+ .INT_HALF = 0,\r
+ .INT_MAJ = 0,\r
+ .START = 0\r
+ },\r
+ {\r
+ .SADDR = (vint32_t)&EQADC.RFPR[ADC_GROUP1].R + 2,\r
+ .SMOD = 0,\r
+ .SSIZE = DMA_TRANSFER_SIZE_16BITS,\r
+ .DMOD = 0,\r
+ .DSIZE = DMA_TRANSFER_SIZE_16BITS,\r
+ .SOFF = 0,\r
+ .NBYTES = sizeof(Adc_ValueGroupType),\r
+ .SLAST = 0,\r
+ .DADDR = (uint32_t)Adc_Group1Buffer,\r
+ .CITERE_LINK = 0,\r
+ .CITER = sizeof(Adc_Group1Buffer)/sizeof(Adc_Group1Buffer[0]),\r
+ .DOFF = sizeof(Adc_ValueGroupType),\r
+ .DLAST_SGA = -sizeof(Adc_Group1Buffer),\r
+ .BITERE_LINK = 0,\r
+ .BITER = sizeof(Adc_Group1Buffer)/sizeof(Adc_Group1Buffer[0]),\r
+ .BWC = 0,\r
+ .MAJORLINKCH = 0,\r
+ .DONE = 0,\r
+ .ACTIVE = 0,\r
+ .MAJORE_LINK = 0,\r
+ .E_SG = 0,\r
+ .D_REQ = 0,\r
+ .INT_HALF = 0,\r
+ .INT_MAJ = 0,\r
+ .START = 0\r
+}\r
+};\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef ADC_CFG_H_\r
+#define ADC_CFG_H_\r
+\r
+#define ADC_PRIORITY_HW 0\r
+#define ADC_PRIORITY_HW_SW 1\r
+#define ADC_PRIORITY_NONE 2\r
+\r
+#define ADC_DEINIT_API STD_ON\r
+#define ADC_DEV_ERROR_DETECT STD_ON\r
+#define ADC_ENABLE_QUEUING STD_ON\r
+#define ADC_ENABLE_START_STOP_GROUP_API STD_ON\r
+#define ADC_GRP_NOTIF_CAPABILITY STD_ON\r
+#define ADC_HW_TRIGGER_API STD_OFF /* Not implemented. */\r
+#define ADC_PRIORITY_IMPLEMENTATION ADC_PRIORITY_HW\r
+#define ADC_READ_GROUP_API STD_ON\r
+#define ADC_VERSION_API STD_ON /* Not implemented. */\r
+\r
+/* Group definitions. */\r
+\r
+\r
+typedef enum\r
+{\r
+ ADC_GROUP0,\r
+ ADC_GROUP1,\r
+ ADC_GROUP2,\r
+ ADC_GROUP3,\r
+ ADC_NBR_OF_GROUPS\r
+}Adc_GroupType;\r
+\r
+typedef enum\r
+{\r
+ ADC_CH0,\r
+ ADC_CH1,\r
+ ADC_CH2,\r
+ ADC_CH3,\r
+ ADC_CH4,\r
+ ADC_CH5,\r
+ ADC_CH6,\r
+ ADC_CH7,\r
+ ADC_CH8,\r
+ ADC_CH9,\r
+ ADC_CH10,\r
+ ADC_CH11,\r
+ ADC_CH12,\r
+ ADC_CH13,\r
+ ADC_CH14,\r
+ ADC_CH15,\r
+ ADC_CH16,\r
+ ADC_CH17,\r
+ ADC_CH18,\r
+ ADC_CH19,\r
+ ADC_CH20,\r
+ ADC_NBR_OF_CHANNELS,\r
+}Adc_ChannelType;\r
+\r
+typedef enum\r
+{\r
+ ADC_TEST_BOARD_AIN1,\r
+ ADC_TEST_BOARD_AIN2,\r
+ ADC_TEST_BOARD_AIN3,\r
+ ADC_TEST_BOARD_AIN4,\r
+ ADC_TEST_BOARD_AIN5,\r
+ ADC_TEST_BOARD_AIN6,\r
+ ADC_TEST_BOARD_AIN7,\r
+ ADC_NBR_OF_GROUP0_CHANNELS,\r
+}Adc_Group0SignalType;\r
+\r
+typedef enum\r
+{\r
+ ADC_GROUP1_CH1,\r
+ ADC_GROUP1_CH2,\r
+ ADC_GROUP1_CH3,\r
+ ADC_GROUP1_CH4,\r
+ ADC_NBR_OF_GROUP1_CHANNELS,\r
+}Adc_Group1SignalType;\r
+\r
+typedef enum\r
+{\r
+ ADC_GROUP2_CH0,\r
+ ADC_GROUP2_CH1,\r
+ ADC_GROUP2_CH2,\r
+ ADC_NBR_OF_GROUP2_CHANNELS,\r
+}Adc_Group2Signals;\r
+\r
+typedef enum\r
+{\r
+ ADC_GROUP3_CH0,\r
+ ADC_GROUP3_CH1,\r
+ ADC_GROUP3_CH2,\r
+ ADC_NBR_OF_GROUP3_CHANNELS,\r
+}Adc_Group3Signals;\r
+\r
+extern const struct tcd_t AdcGroupDMACommandConfig [ADC_NBR_OF_GROUPS];\r
+extern const struct tcd_t AdcGroupDMAResultConfig [ADC_NBR_OF_GROUPS];\r
+\r
+#endif /*ADC_CFG_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include "CanIf.h"\r
+#include <stdlib.h>\r
+\r
+// Imported structs from Can_Lcfg.c\r
+extern const Can_ControllerConfigType CanControllerConfigData[];\r
+extern const Can_ConfigSetType CanConfigSetData;\r
+\r
+\r
+// Container that gets slamed into CanIf_InitController()\r
+// Inits ALL controllers\r
+// Multiplicity 1..*\r
+const CanIf_ControllerConfigType CanIfControllerConfig[] =\r
+{\r
+ { // This is the ConfigurationIndex in CanIf_InitController()\r
+ .WakeupSupport = CANIF_WAKEUP_SUPPORT_NO_WAKEUP,\r
+ .CanIfControllerIdRef = CAN_CTRL_A,\r
+ .CanIfDriverNameRef = "FLEXCAN", // Not used\r
+ .CanIfInitControllerRef = &CanControllerConfigData[0],\r
+ },\r
+ {\r
+ .WakeupSupport = CANIF_WAKEUP_SUPPORT_NO_WAKEUP,\r
+ .CanIfControllerIdRef = CAN_CTRL_C,\r
+ .CanIfDriverNameRef = "FLEXCAN", // Not used\r
+ .CanIfInitControllerRef = &CanControllerConfigData[1],\r
+ }\r
+};\r
+\r
+// Function callbacks for higher layers\r
+const CanIf_DispatchConfigType CanIfDispatchConfig =\r
+{\r
+ .CanIfBusOffNotification = NULL,\r
+ .CanIfWakeUpNotification = NULL, // Not used\r
+ .CanIfWakeupValidNotification = NULL, // Not used\r
+ .CanIfErrorNotificaton = NULL,\r
+};\r
+\r
+//-------------------------------------------------------------------\r
+const CanIf_HthConfigType CanIfHthConfigData[] =\r
+{\r
+ {\r
+ .CanIfHthType = CAN_ECORE_HANDLE_TYPE_BASIC,\r
+ .CanIfCanControllerIdRef = CAN_CTRL_A,\r
+ .CanIfHthIdSymRef = CAN_HTH_A_1, // Ref to the HTH\r
+ .CanIfEcoreEOL = 0,\r
+ },\r
+ {\r
+ .CanIfHthType = CAN_ECORE_HANDLE_TYPE_BASIC,\r
+ .CanIfCanControllerIdRef = CAN_CTRL_C,\r
+ .CanIfHthIdSymRef = CAN_HTH_C_1, // Ref to the HTH\r
+ .CanIfEcoreEOL = 1,\r
+ },\r
+};\r
+\r
+//-------------------------------------------------------------------\r
+const CanIf_HrhConfigType CanIfHrhConfigData[] =\r
+{\r
+ {\r
+ .CanIfHrhType = CAN_ECORE_HANDLE_TYPE_BASIC,\r
+ .CanIfSoftwareFilterHrh = TRUE, // Disable software filtering\r
+ .CanIfCanControllerHrhIdRef = CAN_CTRL_A,\r
+ .CanIfHrhIdSymRef = CAN_HRH_A_1, // Ref to the HRH\r
+ .CanIfEcoreEOL = 0,\r
+ },\r
+ {\r
+ .CanIfHrhType = CAN_ECORE_HANDLE_TYPE_BASIC,\r
+ .CanIfSoftwareFilterHrh = TRUE, // Disable software filtering\r
+ .CanIfCanControllerHrhIdRef = CAN_CTRL_C,\r
+ .CanIfHrhIdSymRef = CAN_HRH_C_1, // Ref to the HRH\r
+ .CanIfEcoreEOL = 1,\r
+ },\r
+};\r
+//-------------------------------------------------------------------\r
+\r
+/*\r
+ * TX PDUs\r
+ */\r
+const CanIf_TxPduConfigType CanIfTxPduConfigData[] =\r
+{\r
+ {\r
+ .CanIfTxPduId = PDU_MSG_HARDWARE_TEST_ENGINE_STATUS, //PDU_MSG_TX789,\r
+ .CanIfCanTxPduIdCanId = 0x0000000,\r
+ .CanIfCanTxPduIdDlc = 8,\r
+ .CanIfCanTxPduType = CANIF_PDU_TYPE_STATIC,\r
+#if ( CANIF_READTXPDU_NOTIFY_STATUS_API == STD_ON )\r
+ .CanIfReadTxPduNotifyStatus = FALSE,\r
+#endif\r
+ .CanIfTxPduIdCanIdType = CANIF_CAN_ID_TYPE_29,\r
+ .CanIfUserTxConfirmation = PduR_CanIfTxConfirmation, //NULL,\r
+ .CanIfCanTxPduHthRef = &CanIfHthConfigData[0], // Send on controller A,\r
+ .PduIdRef = NULL,\r
+ },\r
+ {\r
+ .CanIfTxPduId = PDU_MSG_TX987,\r
+ .CanIfCanTxPduIdCanId = 0x0000100,\r
+ .CanIfCanTxPduIdDlc = 8,\r
+ .CanIfCanTxPduType = CANIF_PDU_TYPE_DYNAMIC,\r
+#if ( CANIF_READTXPDU_NOTIFY_STATUS_API == STD_ON )\r
+ .CanIfReadTxPduNotifyStatus = FALSE,\r
+#endif\r
+ .CanIfTxPduIdCanIdType = CANIF_CAN_ID_TYPE_29,\r
+ .CanIfUserTxConfirmation = NULL,\r
+ .CanIfCanTxPduHthRef = &CanIfHthConfigData[1], // Send on controller C,\r
+ .PduIdRef = NULL,\r
+ },\r
+ //Added by mattias\r
+ {\r
+ .CanIfTxPduId = 2, //PDU_MSG_TX789,\r
+ .CanIfCanTxPduIdCanId = 0x0000200,\r
+ .CanIfCanTxPduIdDlc = 8,\r
+ .CanIfCanTxPduType = CANIF_PDU_TYPE_STATIC,\r
+ #if ( CANIF_READTXPDU_NOTIFY_STATUS_API == STD_ON )\r
+ .CanIfReadTxPduNotifyStatus = FALSE,\r
+ #endif\r
+ .CanIfTxPduIdCanIdType = CANIF_CAN_ID_TYPE_29,\r
+ .CanIfUserTxConfirmation = PduR_CanIfTxConfirmation, // NULL\r
+ .CanIfCanTxPduHthRef = &CanIfHthConfigData[0], // Send on controller A,\r
+ .PduIdRef = NULL,\r
+ },\r
+};\r
+//-------------------------------------------------------------------\r
+\r
+/*\r
+ * RX PDUs\r
+ */\r
+const CanIf_RxPduConfigType CanIfRxPduConfigData[] =\r
+{\r
+ {\r
+ .CanIfCanRxPduId = PDU_MSG_HARDWARE_TEST_ENGINE_CONTROL, //PDU_MSG_RX234,\r
+ .CanIfCanRxPduCanId = 1, // CAN ID\r
+ .CanIfCanRxPduDlc = 8, //DLC\r
+#if ( CANIF_CANPDUID_READDATA_API == STD_ON )\r
+ .CanIfReadRxPduData = FALSE, // no buffering\r
+#endif\r
+#if ( CANIF_READRXPDU_NOTIF_STATUS_API == STD_ON )\r
+ .CanIfReadRxPduNotifyStatus = FALSE, // No indication\r
+#endif\r
+ .CanIfRxPduIdCanIdType = CANIF_CAN_ID_TYPE_29,\r
+ .CanIfRxUserType = CANIF_USER_TYPE_CAN_PDUR, // CANIF_USER_TYPE_CAN_SPECIAL, // Changed by Mattias to test PDU router and Com layer.\r
+ .CanIfUserRxIndication = NULL, // No indication\r
+ .CanIfCanRxPduHrhRef = &CanIfHrhConfigData[0], // Received on controller A\r
+ .PduIdRef = NULL, // Could be used by upper layers\r
+ .CanIfSoftwareFilterType = CANIF_SOFTFILTER_TYPE_MASK, // Not enabled in HRH\r
+ .CanIfCanRxPduCanIdMask = 0xFFF,\r
+ },\r
+ {\r
+ .CanIfCanRxPduId = PDU_MSG_HARDWARE_TEST_ROUTED_MSG, //PDU_MSG_RX123,\r
+ .CanIfCanRxPduCanId = 0x02, // CAN ID\r
+ .CanIfCanRxPduDlc = 8, //DLC\r
+#if ( CANIF_CANPDUID_READDATA_API == STD_ON )\r
+ .CanIfReadRxPduData = FALSE, // no buffering\r
+#endif\r
+#if ( CANIF_READRXPDU_NOTIF_STATUS_API == STD_ON )\r
+ .CanIfReadRxPduNotifyStatus = FALSE, // No indication\r
+#endif\r
+ .CanIfRxPduIdCanIdType = CANIF_CAN_ID_TYPE_29, //\r
+ .CanIfRxUserType = CANIF_USER_TYPE_CAN_PDUR, // CANIF_USER_TYPE_CAN_SPECIAL,\r
+ .CanIfUserRxIndication = NULL, // No indication\r
+ .CanIfCanRxPduHrhRef = &CanIfHrhConfigData[0], //&CanIfHrhConfigData[1], // Received on controller C\r
+ .PduIdRef = NULL, //\r
+ .CanIfSoftwareFilterType = CANIF_SOFTFILTER_TYPE_MASK, // Not enabled in HRH\r
+ .CanIfCanRxPduCanIdMask = 0xFFF,\r
+ },\r
+\r
+};\r
+\r
+//-------------------------------------------------------------------\r
+const CanIf_InitHohConfigType CanIfHohConfigData[] =\r
+{\r
+ {\r
+ .CanConfigSet = &CanConfigSetData,\r
+ .CanIfHrhConfig = CanIfHrhConfigData,\r
+ .CanIfHthConfig = CanIfHthConfigData,\r
+ .CanIfEcoreEOL = 1,\r
+ },\r
+};\r
+\r
+// This container contains the init parameters of the CAN\r
+// Multiplicity 1..*\r
+const CanIf_InitConfigType CanIfInitConfig =\r
+{\r
+ .CanIfConfigSet = 0, // Not used\r
+ .CanIfNumberOfCanRxPduIds = sizeof(CanIfRxPduConfigData)/sizeof(CanIf_RxPduConfigType),\r
+ .CanIfNumberOfCanTXPduIds = sizeof(CanIfTxPduConfigData)/sizeof(CanIf_TxPduConfigType),\r
+ .CanIfNumberOfDynamicCanTXPduIds = 0, // Not used\r
+\r
+ // Containers\r
+ .CanIfHohConfigPtr = CanIfHohConfigData,\r
+ .CanIfRxPduConfigPtr = CanIfRxPduConfigData,\r
+ .CanIfTxPduConfigPtr = CanIfTxPduConfigData,\r
+};\r
+\r
+// This container includes all necessary configuration sub-containers\r
+// according the CAN Interface configuration structure.\r
+CanIf_ConfigType CanIf_Config =\r
+{\r
+ .ControllerConfig = CanIfControllerConfig,\r
+ .DispatchConfig = &CanIfDispatchConfig,\r
+ .InitConfig = &CanIfInitConfig,\r
+ .TransceiverConfig = NULL, // Not used\r
+};\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef CANIF_CFG_H_\r
+#define CANIF_CFG_H_\r
+\r
+#include "Can.h"\r
+\r
+typedef enum {\r
+ CANIF_SOFTFILTER_TYPE_BINARY = 0, // Not supported\r
+ CANIF_SOFTFILTER_TYPE_INDEX, // Not supported\r
+ CANIF_SOFTFILTER_TYPE_LINEAR, // Not supported\r
+ CANIF_SOFTFILTER_TYPE_TABLE, // Not supported\r
+ CANIF_SOFTFILTER_TYPE_MASK, // CanIfCanRxPduCanIdMask in RxPduConfig is used for filtering\r
+} CanIf_SoftwareFilterTypeType;\r
+\r
+typedef enum {\r
+ CANIF_USER_TYPE_CAN_NM,\r
+ CANIF_USER_TYPE_CAN_TP,\r
+ CANIF_USER_TYPE_CAN_PDUR,\r
+ CANIF_USER_TYPE_CAN_SPECIAL,\r
+} CanIf_UserTypeType;\r
+\r
+\r
+\r
+typedef void (*CanIf_FuncTypeCanSpecial)(PduIdType, const uint8 *, uint8, Can_IdType);\r
+\r
+typedef enum {\r
+ CANIF_PDU_TYPE_STATIC = 0,\r
+ CANIF_PDU_TYPE_DYNAMIC // Not supported\r
+} CanIf_PduTypeType;\r
+\r
+typedef enum {\r
+ CANIF_CAN_ID_TYPE_29 = 0,\r
+ CANIF_CAN_ID_TYPE_11\r
+} CanIf_CanIdTypeType;\r
+\r
+/*\r
+ * Public container\r
+ */\r
+#define CANIF_VERSION_INFO_API STD_ON\r
+#define CANIF_DEV_ERROR_DETECT STD_ON\r
+#define CANIF_DLC_CHECK STD_ON\r
+#define CANIF_MULITPLE_DRIVER_SUPPORT STD_OFF // Not supported\r
+#define CANIF_READRXPDU_DATA_API STD_OFF // Not supported\r
+#define CANIF_READRXPDU_NOTIFY_STATUS_API STD_OFF // Not supported\r
+#define CANIF_READTXPDU_NOTIFY_STATUS_API STD_OFF // Not supported\r
+#define CANIF_SETDYNAMICTXID_API STD_OFF // Not supported\r
+#define CANIF_WAKEUP_EVENT_API STD_OFF // Not supported\r
+#define CANIF_TRANSCEIVER_API STD_OFF // Not supported\r
+#define CANIF_TRANSMIT_CANCELLATION STD_OFF // Not supported\r
+\r
+//-------------------------------------------------------------------\r
+\r
+typedef struct {\r
+ void (*CancelTxConfirmation)( void *); // (const Can_PduType *);\r
+ void (*RxIndication)(void *); //(const Can_PduType *);\r
+ void (*ControllerBusOff)(uint8);\r
+ void (*ControllerWakeup)(uint8);\r
+ void (*EcoreError)(uint8,uint32);\r
+} CanIf_CallbackType;\r
+\r
+\r
+\r
+//-------------------------------------------------------------------\r
+/*\r
+ * CanIfHrhRangeConfig container\r
+ */\r
+\r
+typedef struct {\r
+ // Lower CAN Identifier of a receive CAN L-PDU for identifier range\r
+ // definition, in which all CAN Ids shall pass the software filtering. Range: 11\r
+ // Bit for Standard CAN Identifier 29 Bit for Extended CAN Identifer\r
+ uint32 CanIfRxPduLowerCanId;\r
+\r
+ // Upper CAN Identifier of a receive CAN L-PDU for identifier range\r
+ // definition, in which all CAN Ids shall pass the software filtering. Range: 11\r
+ // Bit for Standard CAN Identifier 29 Bit for Extended CAN Identifer\r
+ uint32 CanIfRxPduUpperCanId;\r
+} CanIf_HrhRangeConfigType;\r
+\r
+\r
+\r
+//-------------------------------------------------------------------\r
+/*\r
+ * CanIfInitHrhConfig container\r
+ */\r
+typedef struct {\r
+ // Defines the HRH type i.e, whether its a BasicCan or FullCan. If BasicCan is\r
+ // configured, software filtering is enabled.\r
+ Can_EcoreHohType CanIfHrhType;\r
+\r
+ // Selects the hardware receive objects by using the HRH range/list from\r
+ // CAN Driver configuration to define, for which HRH a software filtering has\r
+ // to be performed at during receive processing. True: Software filtering is\r
+ // enabled False: Software filtering is disabled\r
+ boolean CanIfSoftwareFilterHrh;\r
+\r
+ // Reference to controller Id to which the HRH belongs to. A controller can\r
+ // contain one or more HRHs.\r
+ uint8 CanIfCanControllerHrhIdRef;\r
+\r
+ // The parameter refers to a particular HRH object in the CAN Driver Module\r
+ // configuration. The HRH id is unique in a given CAN Driver. The HRH Ids\r
+ // are defined in the CAN Driver Module and hence it is derived from CAN\r
+ // Driver Configuration.\r
+ Can_EcoreHRHType CanIfHrhIdSymRef ;\r
+\r
+ // Defines the parameters required for configuraing multiple\r
+ // CANID ranges for a given same HRH.\r
+ const CanIf_HrhRangeConfigType *CanIfHrhRangeConfig;\r
+\r
+ // End Of List. Set to TRUE is this is the last object in the list.\r
+ boolean CanIfEcoreEOL;\r
+} CanIf_HrhConfigType;\r
+\r
+//-------------------------------------------------------------------\r
+/*\r
+ * CanIfInitHthConfig container\r
+ */\r
+\r
+typedef struct {\r
+ // Defines the HTH type i.e, whether its a BasicCan or FullCan.\r
+ Can_EcoreHohType CanIfHthType;\r
+\r
+ // Reference to controller Id to which the HTH belongs to. A controller\r
+ // can contain one or more HTHs\r
+ uint8 CanIfCanControllerIdRef;\r
+\r
+ // The parameter refers to a particular HTH object in the CAN Driver Module\r
+ // configuration. The HTH id is unique in a given CAN Driver. The HTH Ids\r
+ // are defined in the CAN Driver Module and hence it is derived from CAN\r
+ // Driver Configuration.\r
+ Can_EcoreHTHType CanIfHthIdSymRef ;\r
+\r
+ // End Of List. Set to TRUE is this is the last object in the list.\r
+ boolean CanIfEcoreEOL;\r
+} CanIf_HthConfigType;\r
+\r
+//-------------------------------------------------------------------\r
+/*\r
+ * CanIfInitHohConfig container\r
+ */\r
+typedef struct {\r
+ // Selects the CAN interface specific configuration setup. This type of external\r
+ // data structure shall contain the post build initialization data for the\r
+ // CAN interface for all underlying CAN Drivers.\r
+ const Can_ConfigSetType *CanConfigSet;\r
+\r
+ // This container contains contiguration parameters for each hardware receive object.\r
+ const CanIf_HrhConfigType *CanIfHrhConfig;\r
+\r
+ // This container contains parameters releated to each HTH\r
+ const CanIf_HthConfigType *CanIfHthConfig;\r
+\r
+ // End Of List. Set to TRUE is this is the last object in the list.\r
+ boolean CanIfEcoreEOL;\r
+} CanIf_InitHohConfigType;\r
+\r
+//-------------------------------------------------------------------\r
+/*\r
+ * CanIfTxPduConfig container\r
+ */\r
+\r
+// This container contains the configuration (parameters) of each transmit\r
+// CAN L-PDU. The SHORT-NAME of "CanIfTxPduConfig" container\r
+// represents the symolic name of Transmit L-PDU.\r
+typedef struct {\r
+ // ECU wide unique, symbolic handle for transmit CAN L-PDU. The\r
+ // CanIfCanTxPduId is configurable at pre-compile and post-built time.\r
+ // Range: 0..max. number of CantTxPduIds PduIdType CanTxPduId;\r
+ PduIdType CanIfTxPduId;\r
+\r
+ // CAN Identifier of transmit CAN L-PDUs used by the CAN Driver for CAN L-\r
+ // PDU transmission. Range: 11 Bit For Standard CAN Identifier ... 29 Bit For\r
+ // Extended CAN identifier\r
+ uint32 CanIfCanTxPduIdCanId;\r
+\r
+ // Data length code (in bytes) of transmit CAN L-PDUs used by the CAN\r
+ // Driver for CAN L-PDU transmission. The data area size of a CAN L-Pdu\r
+ // can have a range from 0 to 8 bytes.\r
+ uint8 CanIfCanTxPduIdDlc;\r
+\r
+ // Defines the type of each transmit CAN L-PDU.\r
+ // DYNAMIC CAN ID is defined at runtime.\r
+ // STATIC CAN ID is defined at compile-time.\r
+ CanIf_PduTypeType CanIfCanTxPduType;\r
+\r
+#if ( CANIF_READTXPDU_NOTIFY_STATUS_API == STD_ON )\r
+ // Enables and disables transmit confirmation for each transmit CAN L-PDU\r
+ // for reading its notification status. True: Enabled False: Disabled\r
+ boolean CanIfReadTxPduNotifyStatus;\r
+#endif\r
+\r
+ // CAN Identifier of transmit CAN L-PDUs used by the CAN Driver for CAN L-\r
+ // PDU transmission.\r
+ // EXTENDED_CAN The CANID is of type Extended (29 bits)\r
+ // STANDARD_CAN The CANID is of type Standard (11 bits)\r
+ CanIf_CanIdTypeType CanIfTxPduIdCanIdType;\r
+\r
+ // Name of target confirmation services to target upper layers (PduR, CanNm\r
+ // and CanTp. If parameter is not configured then no call-out function is\r
+ // provided by the upper layer for this Tx L-PDU.\r
+ void (*CanIfUserTxConfirmation)(PduIdType); /* CANIF 109 */\r
+\r
+ // Handle, that defines the hardware object or the pool of hardware objects\r
+ // configured for transmission. The parameter refers HTH Id, to which the L-\r
+ // PDU belongs to.\r
+ const CanIf_HthConfigType *CanIfCanTxPduHthRef;\r
+\r
+ // Reference to the "global" Pdu structure to allow harmonization of handle\r
+ // IDs in the COM-Stack. ..\r
+ void *PduIdRef;\r
+} CanIf_TxPduConfigType;\r
+\r
+//-------------------------------------------------------------------\r
+/*\r
+ * CanIfRxPduConfig container\r
+ */\r
+\r
+\r
+// This container contains the configuration (parameters) of each receive\r
+// CAN L-PDU. The SHORT-NAME of "CanIfRxPduConfig" container itself\r
+// represents the symolic name of Receive L-PDU.\r
+\r
+typedef struct {\r
+ // ECU wide unique, symbolic handle for receive CAN L-PDU. The\r
+ // CanRxPduId is configurable at pre-compile and post-built time. It shall fulfill\r
+ // ANSI/AUTOSAR definitions for constant defines. Range: 0..max. number\r
+ // of defined CanRxPduIds\r
+ PduIdType CanIfCanRxPduId;\r
+\r
+ // CAN Identifier of Receive CAN L-PDUs used by the CAN Interface. Exa:\r
+ // Software Filtering. Range: 11 Bit For Standard CAN Identifier ... 29 Bit For\r
+ // Extended CAN identifier\r
+ uint32 CanIfCanRxPduCanId;\r
+\r
+ // Data Length code of received CAN L-PDUs used by the CAN Interface.\r
+ // Exa: DLC check. The data area size of a CAN L-PDU can have a range\r
+ // from 0 to 8 bytes. uint8 CanIfCanRxPduDlc;\r
+ uint8 CanIfCanRxPduDlc;\r
+\r
+#if ( CANIF_CANPDUID_READDATA_API == STD_ON )\r
+ // Enables and disables the Rx buffering for reading of received L-PDU data.\r
+ // True: Enabled False: Disabled\r
+ boolean CanIfReadRxPduData;\r
+#endif\r
+\r
+#if ( CANIF_READRXPDU_NOTIF_STATUS_API == STD_ON )\r
+ // CanIfReadRxPduNotifyStatus {CANIF_READRXPDU_NOTIFY_STATUS}\r
+ // Enables and disables receive indication for each receive CAN L-PDU for\r
+ // reading its' notification status. True: Enabled False: Disabled\r
+ boolean CanIfReadRxPduNotifyStatus;\r
+#endif\r
+\r
+ // CAN Identifier of receive CAN L-PDUs used by the CAN Driver for CAN L-\r
+ // PDU transmission.\r
+ // EXTENDED_CAN The CANID is of type Extended (29 bits)\r
+ // STANDARD_CAN The CANID is of type Standard (11 bits)\r
+ CanIf_CanIdTypeType CanIfRxPduIdCanIdType;\r
+\r
+ // This parameter defines the type of the receive indication call-outs called to\r
+ // the corresponding upper layer the used TargetRxPduId belongs to.\r
+ CanIf_UserTypeType CanIfRxUserType;\r
+\r
+ // Name of target indication services to target upper layers (PduRouter,\r
+ // CanNm, CanTp and ComplexDeviceDrivers). If parameter is 0 no call-out\r
+ // function is configured.\r
+ void *CanIfUserRxIndication;\r
+\r
+ // The HRH to which Rx L-PDU belongs to, is referred through this\r
+ // parameter.\r
+ const CanIf_HrhConfigType *CanIfCanRxPduHrhRef;\r
+\r
+ // Reference to the "global" Pdu structure to allow harmonization of handle\r
+ // IDs in the COM-Stack.\r
+ void *PduIdRef;\r
+\r
+ // Defines the type of software filtering that should be used\r
+ // for this receive object.\r
+ CanIf_SoftwareFilterTypeType CanIfSoftwareFilterType;\r
+\r
+ // Acceptance filters, 1 - care, 0 - don't care.\r
+ // Is enabled by the CanIfSoftwareFilterMask in CanIf_HrhConfigType\r
+ // Ecore exension\r
+ uint32 CanIfCanRxPduCanIdMask;\r
+\r
+} CanIf_RxPduConfigType;\r
+\r
+//-------------------------------------------------------------------\r
+\r
+/*\r
+ * CanIfControllerConfig container\r
+ */\r
+\r
+typedef enum {\r
+ CANIF_WAKEUP_SUPPORT_CONTROLLER,\r
+ CANIF_WAKEUP_SUPPORT_NO_WAKEUP,\r
+ CANIF_WAKEUP_SUPPORT_TRANSCEIVER,\r
+} CanIf_WakeupSupportType;\r
+\r
+\r
+// This is the type supplied to CanIf_InitController()\r
+typedef struct {\r
+ CanIf_WakeupSupportType WakeupSupport; // Not used\r
+\r
+ CanControllerIdType CanIfControllerIdRef;\r
+\r
+ const char CanIfDriverNameRef[8]; // Not used\r
+\r
+ const Can_ControllerConfigType *CanIfInitControllerRef;\r
+} CanIf_ControllerConfigType;\r
+\r
+//-------------------------------------------------------------------\r
+/*\r
+ * CanIfTransceiverDrvConfig container\r
+ */\r
+\r
+typedef struct {\r
+ boolean TrcvWakeupNotification;\r
+ uint8 TrcvIdRef;\r
+} CanIf_TransceiverDrvConfigType;\r
+\r
+\r
+typedef struct {\r
+ uint32 todo;\r
+} CanIf_TransceiverConfigType;\r
+\r
+// Callout functions with respect to the upper layers. This callout functions\r
+// defined in this container are common to all configured underlying CAN\r
+// Drivers / CAN Transceiver Drivers.\r
+typedef struct {\r
+ // Name of target BusOff notification services to target upper layers\r
+ // (PduRouter, CanNm, CanTp and ComplexDeviceDrivers).\r
+ // Multiplicity: 1\r
+ void (*CanIfBusOffNotification)(uint8 Controller);\r
+\r
+ // Name of target wakeup notification services to target upper layers\r
+ // e.g Ecu_StateManager. If parameter is 0\r
+ // no call-out function is configured.\r
+ // Multiplicity: 0..1\r
+ void (*CanIfWakeUpNotification)();\r
+\r
+ // Name of target wakeup validation notification services to target upper\r
+ // layers (ECU State Manager). If parameter is 0 no call-out function is\r
+ // configured.\r
+ // Multiplicity: 0..1\r
+ void (*CanIfWakeupValidNotification)();\r
+\r
+ // Ecore ext.\r
+ void (*CanIfErrorNotificaton)(uint8,Can_EcoreErrorType);\r
+\r
+} CanIf_DispatchConfigType;\r
+\r
+// This container contains the references to the configuration setup of each\r
+// underlying CAN driver.\r
+\r
+typedef struct {\r
+ // Selects the CAN Interface specific configuration setup. This type of the\r
+ // external data structure shall contain the post build initialization data for the\r
+ // CAN Interface for all underlying CAN Dirvers. constant to CanIf_ConfigType\r
+ uint32 CanIfConfigSet;\r
+\r
+ uint32 CanIfNumberOfCanRxPduIds;\r
+ uint32 CanIfNumberOfCanTXPduIds;\r
+ uint32 CanIfNumberOfDynamicCanTXPduIds;\r
+\r
+ //\r
+ // Containers\r
+ //\r
+\r
+ // This container contains the reference to the configuration\r
+ // setup of each underlying CAN driver.\r
+ // Multiplicity: 0..*\r
+ const CanIf_InitHohConfigType *CanIfHohConfigPtr;\r
+\r
+ // This container contains the configuration (parameters) of each\r
+ // receive CAN L-PDU. The SHORT-NAME of\r
+ // "CanIfRxPduConfig" container itself represents the symolic\r
+ // name of Receive L-PDU.\r
+ // Multiplicity: 0..*\r
+ const CanIf_RxPduConfigType *CanIfRxPduConfigPtr;\r
+\r
+ // This container contains the configuration (parameters) of each\r
+ // transmit CAN L-PDU. The SHORT-NAME of\r
+ // "CanIfTxPduConfig" container represents the symolic name of\r
+ // Transmit L-PDU.\r
+ // Multiplicity: 0..*\r
+ const CanIf_TxPduConfigType *CanIfTxPduConfigPtr;\r
+\r
+} CanIf_InitConfigType;\r
+\r
+\r
+typedef struct {\r
+ // This container contains the configuration (parameters) of all\r
+ // addressed CAN controllers by each underlying CAN driver.\r
+ // Multiplicity: 1..*\r
+ const CanIf_ControllerConfigType *ControllerConfig;\r
+\r
+ // Callout functions with respect to the upper layers. This callout\r
+ // functions defined in this container are common to all\r
+ // configured underlying CAN Drivers / CAN Transceiver Drivers\r
+ const CanIf_DispatchConfigType *DispatchConfig;\r
+\r
+ // This container contains the init parameters of the CAN\r
+ // Interface.\r
+ // Multiplicity: 1..*\r
+ const CanIf_InitConfigType *InitConfig;\r
+\r
+ // This container contains the configuration (parameters) of all\r
+ // addressed CAN transceivers by each underlying CAN\r
+ // Transceiver Driver.\r
+ // Multiplicity: 1..*\r
+ const CanIf_TransceiverConfigType *TransceiverConfig;\r
+} CanIf_ConfigType;\r
+\r
+\r
+extern CanIf_ConfigType CanIf_Config;\r
+\r
+#endif\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef CAN_CFG_H_\r
+#define CAN_CFG_H_\r
+\r
+// Number of controller configs\r
+#define CAN_ECORE_CTRL_CONFIG_CNT 2\r
+\r
+#define CAN_DEV_ERROR_DETECT STD_ON\r
+#define CAN_VERSION_INFO_API STD_ON\r
+#define CAN_MULTIPLEXED_TRANSMISSION STD_ON // Makes no differens in the code\r
+#define CAN_WAKEUP_SUPPORT STD_OFF // Not supported\r
+#define CAN_HW_TRANSMIT_CANCELLATION STD_OFF // Not supported\r
+\r
+// loop cnt.. very strange timeout\r
+#define CAN_TIMEOUT_DURATION 100\r
+\r
+#define INTERRUPT 0\r
+#define POLLING 1\r
+\r
+// Can controller\r
+#define CAN_BUSOFF_PROCESSING INTERRUPT // INTERRUPT/POLLING\r
+#define CAN_CONTROLLER_ACTIVATION OFF\r
+#define CAN_CONTROLLER_BAUD_RATE 125000\r
+#define CAN_DRIVER_CONTROLLER_ID 0\r
+#define CAN_CONTROLLER_PROP_SEG 4\r
+#define CAN_CONTROLLER_PHASE1_SEG 4\r
+#define CAN_CONTROLLER_PHASE2_SEG 4\r
+#define CAN_CONTROLLER_TIME_QUANTA 4\r
+#define CAN_RX_PROCESSING INTERRUPT\r
+#define CAN_TX_PROCESSING INTERRUPT\r
+#define CAN_WAKEUP_PROCESSING INTERRUPT\r
+\r
+typedef enum {\r
+ CAN_CTRL_A = 0,\r
+ CAN_CTRL_B,\r
+ CAN_CTRL_C,\r
+ CAN_CTRL_D,\r
+ CAN_CTRL_E,\r
+ CAN_CONTROLLER_CNT \r
+}CanControllerIdType;\r
+\r
+typedef enum {\r
+ CAN_ID_TYPE_EXTENDED,\r
+ CAN_ID_TYPE_MIXED,\r
+ CAN_ID_TYPE_STANDARD,\r
+} Can_IdTypeType;\r
+\r
+typedef enum {\r
+ CAN_OBJECT_TYPE_RECEIVE,\r
+ CAN_OBJECT_TYPE_TRANSMIT,\r
+} Can_ObjectTypeType;\r
+\r
+typedef enum {\r
+ CAN_ECORE_HANDLE_TYPE_BASIC,\r
+ CAN_ECORE_HANDLE_TYPE_FULL\r
+} Can_EcoreHohType;\r
+\r
+// HTH definitions\r
+// Due to effiency: Start with index 0 and don't use any holes in the enumeration\r
+typedef enum {\r
+ CAN_HTH_A_1 = 0,\r
+ CAN_HTH_C_1,\r
+ NUM_OF_HTHS\r
+} Can_EcoreHTHType;\r
+\r
+// HRH definitions\r
+// Due to effiency: Start with index 0 and don't use any holes in the enumeration\r
+typedef enum {\r
+ CAN_HRH_A_1 = 0,\r
+ CAN_HRH_C_1,\r
+ NUM_OF_HRHS\r
+} Can_EcoreHRHType;\r
+\r
+// Non-standard type\r
+typedef struct {\r
+ void (*CancelTxConfirmation)( const Can_PduType *);\r
+ void (*RxIndication)( uint8 ,Can_IdType ,uint8 , const uint8 * );\r
+ void (*ControllerBusOff)(uint8);\r
+ void (*TxConfirmation)(PduIdType);\r
+ void (*ControllerWakeup)(uint8);\r
+ void (*EcoreError)(uint8,Can_EcoreErrorType);\r
+} Can_CallbackType;\r
+\r
+/*\r
+ * CanGeneral Container\r
+ */\r
+\r
+// This container contains the parameters related each CAN Driver Unit.\r
+typedef struct {\r
+ // Specifies the InstanceId of this module instance. If only one instance is\r
+ // present it shall have the Id 0\r
+ int CanIndex;\r
+\r
+#if 0 // This is only used by the config tool\r
+ // This parameter describes the period for cyclic call to\r
+ // Can_MainFunction_Busoff. Unit is seconds.\r
+ float CanMainFunctionBusoffPeriod;\r
+ // This parameter describes the period for cyclic call to\r
+ // Can_MainFunction_Read. Unit is seconds.\r
+ float CanMainFunctionReadPeriod;\r
+ // This parameter describes the period for cyclic call to\r
+ // Can_MainFunction_Wakeup. Unit is seconds.\r
+ float CanMainFunctionWakeupPeriod;\r
+ // This parameter describes the period for cyclic call to\r
+ // Can_MainFunction_Write. Unit is seconds.\r
+ float CanMainFunctionWritePeriod;\r
+#endif\r
+\r
+\r
+#if ( CAN_TIMEOUT_DURATION == STD_ON )\r
+ // Specifies the maximum number of loops for blocking function until a\r
+ // timeout is raised in short term wait loops.\r
+ uint32 CanTimeoutDurationFactor;\r
+#endif\r
+\r
+} Can_GeneralType;\r
+\r
+\r
+/*\r
+ * CanFilterMask container\r
+ */\r
+typedef uint32 Can_FilterMaskType;\r
+\r
+/*\r
+ * CanHardwareObject container\r
+ */\r
+\r
+//This container contains the configuration (parameters) of CAN Hardware\r
+//Objects.\r
+typedef struct Can_HardwareObjectStruct {\r
+ // Specifies the type (Full-CAN or Basic-CAN) of a hardware object.\r
+ Can_EcoreHohType CanHandleType;\r
+\r
+ // Specifies whether the IdValue is of type - standard identifier - extended\r
+ // identifier - mixed mode ImplementationType: Can_IdType\r
+ Can_IdTypeType CanIdType;\r
+\r
+ // Specifies (together with the filter mask) the identifiers range that passes\r
+ // the hardware filter.\r
+ uint32 CanIdValue;\r
+\r
+ // Holds the handle ID of HRH or HTH. The value of this parameter is unique\r
+ // in a given CAN Driver, and it should start with 0 and continue without any\r
+ // gaps. The HRH and HTH Ids are defined under two different name-spaces.\r
+ // Example: HRH0-0, HRH1-1, HTH0-2, HTH1-3\r
+ uint32 CanObjectId;\r
+\r
+ // Specifies if the HardwareObject is used as Transmit or as Receive object\r
+ Can_ObjectTypeType CanObjectType;\r
+\r
+ // Reference to the filter mask that is used for hardware filtering togerther\r
+ // with the CAN_ID_VALUE\r
+ Can_FilterMaskType *CanFilterMaskRef;\r
+\r
+ // A "1" in this mask tells the driver that that HW Message Box should be\r
+ // occupied by this Hoh. A "1" in bit 31(ppc) occupies Mb 0 in HW.\r
+ uint32 CanEcoreMbMask;\r
+\r
+ // End Of List. Set to TRUE is this is the last object in the list.\r
+ boolean CanEcoreEOL;\r
+\r
+} Can_HardwareObjectType;\r
+\r
+\r
+/*\r
+ * CanController container\r
+ */\r
+typedef enum {\r
+ CAN_ECORE_PROCESS_TYPE_INTERRUPT,\r
+ CAN_ECORE_PROCESS_TYPE_POLLING,\r
+} Can_EcoreProcessType;\r
+\r
+typedef struct {\r
+\r
+ // Enables / disables API Can_MainFunction_BusOff() for handling busoff\r
+ // events in polling mode.\r
+ // INTERRUPT or POLLING\r
+ Can_EcoreProcessType CanBusOffProcessing;\r
+\r
+ // Defines if a CAN controller is used in the configuration.\r
+ boolean CanControllerActivation;\r
+\r
+ // Specifies the buadrate of the controller in kbps.\r
+ uint32 CanControllerBaudRate;\r
+\r
+ // This parameter provides the controller ID which is unique in a given CAN\r
+ // Driver. The value for this parameter starts with 0 and continue without any\r
+ // gaps.\r
+ CanControllerIdType CanControllerId;\r
+\r
+ // Specifies propagation delay in time quantas.\r
+ uint32 CanControllerPropSeg;\r
+\r
+ // Specifies phase segment 1 in time quantas.\r
+ uint32 CanControllerSeg1;\r
+\r
+ // Specifies phase segment 2 in time quantas.\r
+ uint32 CanControllerSeg2;\r
+\r
+ // Specifies the time quanta for the controller. The calculation of the resulting\r
+ // prescaler value depending on module clocking and time quanta shall be\r
+ // done offline Hardware specific.\r
+ uint32 CanControllerTimeQuanta;\r
+\r
+ // Enables / disables API Can_MainFunction_Read() for handling PDU\r
+ // reception events in polling mode.\r
+ Can_EcoreProcessType CanRxProcessing;\r
+\r
+ // Enables / disables API Can_MainFunction_Write() for handling PDU\r
+ // transmission events in polling mode.\r
+ Can_EcoreProcessType CanTxProcessing;\r
+\r
+ // Enables / disables API Can_MainFunction_Wakeup() for handling wakeup\r
+ // events in polling mode.\r
+ Can_EcoreProcessType CanWakeupProcessing;\r
+\r
+ // Reference to the CPU clock configuration, which is set in the MCU driver\r
+ // configuration\r
+ uint32 CanCpuClockRef;\r
+\r
+ // This parameter contains a reference to the Wakeup Source for this\r
+ // controller as defined in the ECU State Manager. Implementation Type:\r
+ // reference to EcuM_WakeupSourceType\r
+ uint32 CanWakeupSourceRef;\r
+\r
+ //\r
+ // Ecore stuff\r
+ //\r
+\r
+ // List of Hoh id's that belong to this controller\r
+ const Can_HardwareObjectType *CanEcoreHoh;\r
+\r
+ boolean CanEcoreLoopback;\r
+\r
+ // Set this to use the fifo\r
+ boolean CanEcoreFifo;\r
+\r
+} Can_ControllerConfigType;\r
+\r
+\r
+\r
+/*\r
+ * CanConfigSet container\r
+ */\r
+typedef struct {\r
+ const Can_ControllerConfigType *CanController;\r
+ \r
+ // Callbacks( Extension )\r
+ const Can_CallbackType *CanCallbacks;\r
+} Can_ConfigSetType;\r
+\r
+\r
+typedef struct {\r
+ // This is the multiple configuration set container for CAN Driver\r
+ // Multiplicity 1..*\r
+ const Can_ConfigSetType *CanConfigSet;\r
+ // This container contains the parameters related each CAN\r
+ // Driver Unit.\r
+ // Multiplicity 1..*\r
+ const Can_GeneralType *CanGeneral;\r
+\r
+\r
+} Can_ConfigType;\r
+\r
+\r
+extern const Can_ConfigType CanConfigData;\r
+extern const Can_ControllerConfigType CanControllerConfigData[];\r
+extern const Can_ConfigSetType Can_ConfigSet;\r
+\r
+\r
+#endif /*CAN_CFG_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include <stdlib.h>\r
+#include "Can.h"\r
+#include "CanIf_Cbk.h"\r
+\r
+/* CONFIGURATION TEMPLATE\r
+ * ------------------------------------------------------------------\r
+ *\r
+ * The following template configures:\r
+ * - 2 CAN controllers, CAN_CTRL_A and CAN_CNTR_C\r
+ * - Callbacks are configured to call standard CanIf callbacks\r
+ *\r
+ * CAN_CTRL_A\r
+ * - 125K baudrate\r
+ * - Extended 11-bit ID's\r
+ * - Rx/Tx are interrupt based\r
+ * - Both Rx(MB 16->24) and Tx(MB 24->31) Hoh's are of type BASIC\r
+ *\r
+ * CAN_CTRL_C\r
+ * - 125K baudrate\r
+ * - Standard 29-bit ID's\r
+ * - Rx/Tx are interrupt based\r
+ * - Both Rx(MB 16->24) and Tx(MB 24->31) Hoh's are of type BASIC\r
+ * *\r
+ */\r
+\r
+// Accept everything = 0\r
+Can_FilterMaskType Can_FilterMaskConfigData = 0;\r
+\r
+// HOH:s for CAN_CTRL_A\r
+const Can_HardwareObjectType CanHardwareObjectConfig_CTRL_A[] =\r
+{\r
+ {\r
+ .CanHandleType = CAN_ECORE_HANDLE_TYPE_BASIC,\r
+ .CanIdType = CAN_ID_TYPE_EXTENDED,\r
+ .CanObjectType = CAN_OBJECT_TYPE_RECEIVE,\r
+ .CanObjectId = CAN_HRH_A_1,\r
+ .CanFilterMaskRef = &Can_FilterMaskConfigData,\r
+ // Ecore\r
+ .CanEcoreMbMask = 0x00ff0000,\r
+ .CanEcoreEOL = 0,\r
+ },\r
+ {\r
+ .CanHandleType = CAN_ECORE_HANDLE_TYPE_BASIC,\r
+ .CanIdType = CAN_ID_TYPE_EXTENDED,\r
+ .CanObjectType = CAN_OBJECT_TYPE_TRANSMIT,\r
+ .CanObjectId = CAN_HTH_A_1,\r
+ .CanFilterMaskRef = &Can_FilterMaskConfigData,\r
+ // Ecore\r
+ .CanEcoreMbMask = 0xff000000,\r
+ .CanEcoreEOL = 1,\r
+ },\r
+};\r
+\r
+// HOH:s for CAN_CTRL_C\r
+const Can_HardwareObjectType CanHardwareObjectConfig_CTRL_C[] =\r
+{\r
+ {\r
+ .CanHandleType = CAN_ECORE_HANDLE_TYPE_BASIC,\r
+ .CanIdType = CAN_ID_TYPE_STANDARD,\r
+ .CanObjectType = CAN_OBJECT_TYPE_RECEIVE,\r
+ .CanObjectId = CAN_HRH_C_1,\r
+ .CanFilterMaskRef = &Can_FilterMaskConfigData,\r
+ // Ecore\r
+ .CanEcoreMbMask = 0x00ff0000,\r
+ .CanEcoreEOL = 0,\r
+ },\r
+ {\r
+ .CanHandleType = CAN_ECORE_HANDLE_TYPE_BASIC,\r
+ .CanIdType = CAN_ID_TYPE_STANDARD,\r
+ .CanObjectType = CAN_OBJECT_TYPE_TRANSMIT,\r
+ .CanObjectId = CAN_HTH_C_1,\r
+ .CanFilterMaskRef = &Can_FilterMaskConfigData,\r
+ // Ecore\r
+ .CanEcoreMbMask = 0xff000000,\r
+ .CanEcoreEOL = 1,\r
+ },\r
+};\r
+\r
+/* CAN controller data for ALL controllers that are to be configured\r
+ * See Autosar release 3.0 specification for more info\r
+ */\r
+const Can_ControllerConfigType CanControllerConfigData[] =\r
+{\r
+ {\r
+ .CanControllerActivation = TRUE,\r
+ .CanControllerBaudRate = 125,\r
+ .CanControllerId = CAN_CTRL_A,\r
+ .CanControllerPropSeg = 4,\r
+ .CanControllerSeg1 = 4,\r
+ .CanControllerSeg2 = 4,\r
+ .CanBusOffProcessing = CAN_ECORE_PROCESS_TYPE_INTERRUPT,\r
+ .CanRxProcessing = CAN_ECORE_PROCESS_TYPE_INTERRUPT,\r
+ .CanTxProcessing = CAN_ECORE_PROCESS_TYPE_INTERRUPT,\r
+ .CanWakeupProcessing = CAN_ECORE_PROCESS_TYPE_INTERRUPT,\r
+ .CanCpuClockRef = PERIPHERAL_CLOCK_FLEXCAN_A,\r
+ // Ecore\r
+ .CanEcoreHoh = &CanHardwareObjectConfig_CTRL_A[0],\r
+ .CanEcoreLoopback = 0,\r
+ .CanEcoreFifo = 0,\r
+\r
+ },{\r
+ .CanControllerActivation = TRUE,\r
+ .CanControllerBaudRate = 125,\r
+ .CanControllerId = CAN_CTRL_C,\r
+ .CanControllerPropSeg = 4,\r
+ .CanControllerSeg1 = 4,\r
+ .CanControllerSeg2 = 4,\r
+ .CanBusOffProcessing = CAN_ECORE_PROCESS_TYPE_INTERRUPT,\r
+ .CanRxProcessing = CAN_ECORE_PROCESS_TYPE_INTERRUPT,\r
+ .CanTxProcessing = CAN_ECORE_PROCESS_TYPE_INTERRUPT,\r
+ .CanWakeupProcessing = CAN_ECORE_PROCESS_TYPE_INTERRUPT,\r
+ .CanCpuClockRef = PERIPHERAL_CLOCK_FLEXCAN_C,\r
+ // Ecore\r
+ .CanEcoreHoh = &CanHardwareObjectConfig_CTRL_C[0],\r
+ .CanEcoreLoopback = 1,\r
+ .CanEcoreFifo = 0,\r
+ }\r
+};\r
+\r
+/* Callbacks for the can drivers\r
+ * See Autosar release 3.0 specification for more info\r
+ */\r
+const Can_CallbackType CanCallbackConfigData = {\r
+ NULL, //CanIf_CancelTxConfirmation,\r
+ CanIf_RxIndication,\r
+ CanIf_ControllerBusOff,\r
+ CanIf_TxConfirmation,\r
+ NULL, //CanIf_ControllerWakeup,\r
+ CanIf_EcoreError,\r
+};\r
+\r
+/* Configset configuration information\r
+ * See Autosar release 3.0 specification for more info\r
+ */\r
+const Can_ConfigSetType CanConfigSetData =\r
+{\r
+ .CanController = CanControllerConfigData,\r
+ .CanCallbacks = &CanCallbackConfigData,\r
+};\r
+\r
+/* Top config struct passed to Can_Init() */\r
+const Can_ConfigType CanConfigData = {\r
+ .CanConfigSet = &CanConfigSetData,\r
+};\r
+\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*\r
+ * ComGlobals.h\r
+ *\r
+ * Created on: 2009-jan-11\r
+ * Author: Mattias\r
+ */\r
+\r
+#ifndef COMGLOBALS_H_\r
+#define COMGLOBALS_H_\r
+\r
+\r
+// PDU definitions\r
+enum {\r
+ // Used for PCAN.\r
+ PCAN_RX_FRAME_1 = 0,\r
+ PCAN_RX_FRAME_2 = 2,\r
+ PCAN_TX_FRAME_1 = 3,\r
+ PCAN_TX_FRAME_2 = 4,\r
+\r
+ // Used for hardware test.\r
+ PDU_MSG_HARDWARE_TEST_ENGINE_STATUS = 0,\r
+ PDU_MSG_HARDWARE_TEST_ENGINE_CONTROL = 1,\r
+ PDU_MSG_HARDWARE_TEST_ROUTED_MSG = 2,\r
+\r
+ // Used for testing CanIf\r
+ PDU_MSG_RX234 = 8,\r
+ PDU_MSG_RX123 = 10,\r
+ PDU_MSG_TX789 = 9,\r
+ PDU_MSG_TX987 = 11\r
+\r
+};\r
+\r
+\r
+#endif /* COMGLOBALS_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef COM_CFG_H_\r
+#define COM_CFG_H_\r
+\r
+#define COM_MODULE_ID 20\r
+#define COM_INSTANCE_ID 1\r
+\r
+#define COM_DEV_ERROR_DETECT\r
+\r
+\r
+#define COM_MAX_NR_IPDU 30\r
+#define COM_MAX_NR_SIGNAL 30\r
+#define COM_MAX_NR_GROUPSIGNAL 30\r
+\r
+#define COM_MAX_NR_SIGNALS_PER_IPDU 10\r
+#define COM_MAX_NR_SIGNALGROUPS_PER_IPDU 10\r
+#define COM_MAX_NR_SIGNALS_PER_SIGNAL_GROUP 10\r
+\r
+\r
+#define COM_E_INVALID_FILTER_CONFIGURATION 101\r
+#define COM_E_INITIALIZATION_FAILED 102\r
+#define COM_E_INVALID_SIGNAL_CONFIGURATION 103\r
+#define COM_INVALID_PDU_ID 104\r
+#define COM_ERROR_SIGNAL_IS_SIGNALGROUP 105\r
+\r
+#define COM_E_TOO_MANY_IPDU 106\r
+#define COM_E_TOO_MANY_SIGNAL 107\r
+#define COM_E_TOO_MANY_GROUPSIGNAL 108\r
+\r
+#define CPU_ENDIANESS BIG_ENDIAN\r
+\r
+/*\r
+ * ComGeneral pre-compile time configuration parameters.
+ */\r
+#define ComConfigurationTimeBase\r
+#define ComConfigurationUseDet\r
+#define ComVersionInfoApi\r
+\r
+\r
+\r
+\r
+\r
+#endif /*COM_CFG_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include "Com_PbCfg.h"\r
+#include "Com_RunTest.h"\r
+\r
+#include "stdlib.h"\r
+\r
+\r
+/*\r
+ * PCAN Configuration
+ */\r
+ComSignal_type PCAN_ComSignal[] = {\r
+ // Signals for PCAN_RX_FRAME_1\r
+ {\r
+ .ComBitPosition = 0,\r
+ .ComBitSize = 8,\r
+ //.ComDataInvalidAction (NOT IMPLEMENTED)\r
+ .ComErrorNotification = NULL,\r
+ .ComFirstTimeoutFactor = 0,\r
+ .ComHandleId = 0,\r
+ //.ComInvalidNotification (NOT IMPLEMENTED)\r
+ .ComNotification = NULL,\r
+ //.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
+ //.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
+ .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalInitValue = 0x0,\r
+ .ComSignalLength = 0,\r
+ .ComSignalType = UINT8,\r
+ .ComTimeoutFactor = 0,\r
+ .ComTimeoutNotification = NULL,\r
+ .ComTransferProperty = TRIGGERED,\r
+ .ComUpdateBitPosition = 0,\r
+ .ComSignalEcoreUseUpdateBit = 0,\r
+ .ComFilter = {\r
+ .ComFilterAlgorithm = ALWAYS,\r
+ .ComFilterMask = 0,\r
+ .ComFilterMax = 0,\r
+ .ComFilterMin = 0,\r
+ .ComFilterOffset = 0,\r
+ .ComFilterPeriodFactor = 0,\r
+ .ComFilterX = 0\r
+ }\r
+ },\r
+ {\r
+ .ComBitPosition = 8,\r
+ .ComBitSize = 8,\r
+ //.ComDataInvalidAction (NOT IMPLEMENTED)\r
+ .ComErrorNotification = NULL,\r
+ .ComFirstTimeoutFactor = 0,\r
+ .ComHandleId = 1,\r
+ //.ComInvalidNotification (NOT IMPLEMENTED)\r
+ .ComNotification = NULL,\r
+ //.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
+ //.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
+ .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalInitValue = 0x00,\r
+ .ComSignalLength = 0,\r
+ .ComSignalType = UINT8,\r
+ .ComTimeoutFactor = 0,\r
+ .ComTimeoutNotification = NULL,\r
+ .ComTransferProperty = TRIGGERED,\r
+ .ComUpdateBitPosition = 0,\r
+ .ComSignalEcoreUseUpdateBit = 0,\r
+ .ComFilter = {\r
+ .ComFilterAlgorithm = ALWAYS,\r
+ .ComFilterMask = 0,\r
+ .ComFilterMax = 0,\r
+ .ComFilterMin = 0,\r
+ .ComFilterOffset = 0,\r
+ .ComFilterPeriodFactor = 0,\r
+ .ComFilterX = 0\r
+ }\r
+ },\r
+ {\r
+ .ComBitPosition = 16,\r
+ .ComBitSize = 1,\r
+ //.ComDataInvalidAction (NOT IMPLEMENTED)\r
+ .ComErrorNotification = NULL,\r
+ .ComFirstTimeoutFactor = 0,\r
+ .ComHandleId = 2,\r
+ //.ComInvalidNotification (NOT IMPLEMENTED)\r
+ .ComNotification = NULL,\r
+ //.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
+ //.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
+ .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalInitValue = 0x00,\r
+ .ComSignalLength = 0,\r
+ .ComSignalType = UINT8,\r
+ .ComTimeoutFactor = 0,\r
+ .ComTimeoutNotification = NULL,\r
+ .ComTransferProperty = TRIGGERED,\r
+ .ComUpdateBitPosition = 0,\r
+ .ComSignalEcoreUseUpdateBit = 0,\r
+ .ComFilter = {\r
+ .ComFilterAlgorithm = ALWAYS,\r
+ .ComFilterMask = 0,\r
+ .ComFilterMax = 0,\r
+ .ComFilterMin = 0,\r
+ .ComFilterOffset = 0,\r
+ .ComFilterPeriodFactor = 0,\r
+ .ComFilterX = 0\r
+ }\r
+ },\r
+ {\r
+ .ComBitPosition = 17,\r
+ .ComBitSize = 2,\r
+ //.ComDataInvalidAction (NOT IMPLEMENTED)\r
+ .ComErrorNotification = NULL,\r
+ .ComFirstTimeoutFactor = 0,\r
+ .ComHandleId = 3,\r
+ //.ComInvalidNotification (NOT IMPLEMENTED)\r
+ .ComNotification = NULL,\r
+ //.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
+ //.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
+ .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalInitValue = 0x00,\r
+ .ComSignalLength = 0,\r
+ .ComSignalType = UINT8,\r
+ .ComTimeoutFactor = 0,\r
+ .ComTimeoutNotification = NULL,\r
+ .ComTransferProperty = TRIGGERED,\r
+ .ComUpdateBitPosition = 0,\r
+ .ComSignalEcoreUseUpdateBit = 0,\r
+ .ComFilter = {\r
+ .ComFilterAlgorithm = ALWAYS,\r
+ .ComFilterMask = 0,\r
+ .ComFilterMax = 0,\r
+ .ComFilterMin = 0,\r
+ .ComFilterOffset = 0,\r
+ .ComFilterPeriodFactor = 0,\r
+ .ComFilterX = 0\r
+ }\r
+ },\r
+\r
+\r
+\r
+ // Signals for PCAN_RX_FRAME_2\r
+ {\r
+ .ComBitPosition = 0,\r
+ .ComBitSize = 8,\r
+ //.ComDataInvalidAction (NOT IMPLEMENTED)\r
+ .ComErrorNotification = NULL,\r
+ .ComFirstTimeoutFactor = 0,\r
+ .ComHandleId = 4,\r
+ //.ComInvalidNotification (NOT IMPLEMENTED)\r
+ .ComNotification = NULL,\r
+ //.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
+ //.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
+ .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalInitValue = 0x0,\r
+ .ComSignalLength = 0,\r
+ .ComSignalType = UINT8,\r
+ .ComTimeoutFactor = 0,\r
+ .ComTimeoutNotification = NULL,\r
+ .ComTransferProperty = TRIGGERED,\r
+ .ComUpdateBitPosition = 0,\r
+ .ComSignalEcoreUseUpdateBit = 0,\r
+ .ComFilter = {\r
+ .ComFilterAlgorithm = ALWAYS,\r
+ .ComFilterMask = 0,\r
+ .ComFilterMax = 0,\r
+ .ComFilterMin = 0,\r
+ .ComFilterOffset = 0,\r
+ .ComFilterPeriodFactor = 0,\r
+ .ComFilterX = 0\r
+ }\r
+ },\r
+ {\r
+ .ComBitPosition = 8,\r
+ .ComBitSize = 8,\r
+ //.ComDataInvalidAction (NOT IMPLEMENTED)\r
+ .ComErrorNotification = NULL,\r
+ .ComFirstTimeoutFactor = 0,\r
+ .ComHandleId = 5,\r
+ //.ComInvalidNotification (NOT IMPLEMENTED)\r
+ .ComNotification = NULL,\r
+ //.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
+ //.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
+ .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalInitValue = 0x00,\r
+ .ComSignalLength = 0,\r
+ .ComSignalType = UINT8,\r
+ .ComTimeoutFactor = 0,\r
+ .ComTimeoutNotification = NULL,\r
+ .ComTransferProperty = TRIGGERED,\r
+ .ComUpdateBitPosition = 0,\r
+ .ComSignalEcoreUseUpdateBit = 0,\r
+ .ComFilter = {\r
+ .ComFilterAlgorithm = ALWAYS,\r
+ .ComFilterMask = 0,\r
+ .ComFilterMax = 0,\r
+ .ComFilterMin = 0,\r
+ .ComFilterOffset = 0,\r
+ .ComFilterPeriodFactor = 0,\r
+ .ComFilterX = 0\r
+ }\r
+ },\r
+ {\r
+ .ComBitPosition = 16,\r
+ .ComBitSize = 1,\r
+ //.ComDataInvalidAction (NOT IMPLEMENTED)\r
+ .ComErrorNotification = NULL,\r
+ .ComFirstTimeoutFactor = 0,\r
+ .ComHandleId = 6,\r
+ //.ComInvalidNotification (NOT IMPLEMENTED)\r
+ .ComNotification = NULL,\r
+ //.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
+ //.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
+ .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalInitValue = 0x00,\r
+ .ComSignalLength = 0,\r
+ .ComSignalType = UINT8,\r
+ .ComTimeoutFactor = 0,\r
+ .ComTimeoutNotification = NULL,\r
+ .ComTransferProperty = TRIGGERED,\r
+ .ComUpdateBitPosition = 0,\r
+ .ComSignalEcoreUseUpdateBit = 0,\r
+ .ComFilter = {\r
+ .ComFilterAlgorithm = ALWAYS,\r
+ .ComFilterMask = 0,\r
+ .ComFilterMax = 0,\r
+ .ComFilterMin = 0,\r
+ .ComFilterOffset = 0,\r
+ .ComFilterPeriodFactor = 0,\r
+ .ComFilterX = 0\r
+ }\r
+ },\r
+ {\r
+ .ComBitPosition = 17,\r
+ .ComBitSize = 2,\r
+ //.ComDataInvalidAction (NOT IMPLEMENTED)\r
+ .ComErrorNotification = NULL,\r
+ .ComFirstTimeoutFactor = 0,\r
+ .ComHandleId = 7,\r
+ //.ComInvalidNotification (NOT IMPLEMENTED)\r
+ .ComNotification = NULL,\r
+ //.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
+ //.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
+ .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalInitValue = 0x00,\r
+ .ComSignalLength = 0,\r
+ .ComSignalType = UINT8,\r
+ .ComTimeoutFactor = 0,\r
+ .ComTimeoutNotification = NULL,\r
+ .ComTransferProperty = TRIGGERED,\r
+ .ComUpdateBitPosition = 0,\r
+ .ComSignalEcoreUseUpdateBit = 0,\r
+ .ComFilter = {\r
+ .ComFilterAlgorithm = ALWAYS,\r
+ .ComFilterMask = 0,\r
+ .ComFilterMax = 0,\r
+ .ComFilterMin = 0,\r
+ .ComFilterOffset = 0,\r
+ .ComFilterPeriodFactor = 0,\r
+ .ComFilterX = 0\r
+ }\r
+ },\r
+\r
+ // Signals for PCAN_TX_FRAME_1\r
+ {\r
+ .ComBitPosition = 0,\r
+ .ComBitSize = 8,\r
+ //.ComDataInvalidAction (NOT IMPLEMENTED)\r
+ .ComErrorNotification = NULL,\r
+ .ComFirstTimeoutFactor = 0,\r
+ .ComHandleId = 8,\r
+ //.ComInvalidNotification (NOT IMPLEMENTED)\r
+ .ComNotification = NULL,\r
+ //.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
+ //.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
+ .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalInitValue = 0x0,\r
+ .ComSignalLength = 0,\r
+ .ComSignalType = UINT8,\r
+ .ComTimeoutFactor = 0,\r
+ .ComTimeoutNotification = NULL,\r
+ .ComTransferProperty = TRIGGERED,\r
+ .ComUpdateBitPosition = 0,\r
+ .ComSignalEcoreUseUpdateBit = 0,\r
+ .ComFilter = {\r
+ .ComFilterAlgorithm = ALWAYS,\r
+ .ComFilterMask = 0,\r
+ .ComFilterMax = 0,\r
+ .ComFilterMin = 0,\r
+ .ComFilterOffset = 0,\r
+ .ComFilterPeriodFactor = 0,\r
+ .ComFilterX = 0\r
+ }\r
+ },\r
+ {\r
+ .ComBitPosition = 8,\r
+ .ComBitSize = 8,\r
+ //.ComDataInvalidAction (NOT IMPLEMENTED)\r
+ .ComErrorNotification = NULL,\r
+ .ComFirstTimeoutFactor = 0,\r
+ .ComHandleId = 9,\r
+ //.ComInvalidNotification (NOT IMPLEMENTED)\r
+ .ComNotification = NULL,\r
+ //.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
+ //.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
+ .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalInitValue = 0x00,\r
+ .ComSignalLength = 0,\r
+ .ComSignalType = UINT8,\r
+ .ComTimeoutFactor = 0,\r
+ .ComTimeoutNotification = NULL,\r
+ .ComTransferProperty = TRIGGERED,\r
+ .ComUpdateBitPosition = 0,\r
+ .ComSignalEcoreUseUpdateBit = 0,\r
+ .ComFilter = {\r
+ .ComFilterAlgorithm = ALWAYS,\r
+ .ComFilterMask = 0,\r
+ .ComFilterMax = 0,\r
+ .ComFilterMin = 0,\r
+ .ComFilterOffset = 0,\r
+ .ComFilterPeriodFactor = 0,\r
+ .ComFilterX = 0\r
+ }\r
+ },\r
+ {\r
+ .ComBitPosition = 16,\r
+ .ComBitSize = 1,\r
+ //.ComDataInvalidAction (NOT IMPLEMENTED)\r
+ .ComErrorNotification = NULL,\r
+ .ComFirstTimeoutFactor = 0,\r
+ .ComHandleId = 10,\r
+ //.ComInvalidNotification (NOT IMPLEMENTED)\r
+ .ComNotification = NULL,\r
+ //.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
+ //.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
+ .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalInitValue = 0x00,\r
+ .ComSignalLength = 0,\r
+ .ComSignalType = UINT8,\r
+ .ComTimeoutFactor = 0,\r
+ .ComTimeoutNotification = NULL,\r
+ .ComTransferProperty = TRIGGERED,\r
+ .ComUpdateBitPosition = 0,\r
+ .ComSignalEcoreUseUpdateBit = 0,\r
+ .ComFilter = {\r
+ .ComFilterAlgorithm = ALWAYS,\r
+ .ComFilterMask = 0,\r
+ .ComFilterMax = 0,\r
+ .ComFilterMin = 0,\r
+ .ComFilterOffset = 0,\r
+ .ComFilterPeriodFactor = 0,\r
+ .ComFilterX = 0\r
+ }\r
+ },\r
+ {\r
+ .ComBitPosition = 17,\r
+ .ComBitSize = 2,\r
+ //.ComDataInvalidAction (NOT IMPLEMENTED)\r
+ .ComErrorNotification = NULL,\r
+ .ComFirstTimeoutFactor = 0,\r
+ .ComHandleId = 11,\r
+ //.ComInvalidNotification (NOT IMPLEMENTED)\r
+ .ComNotification = NULL,\r
+ //.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
+ //.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
+ .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalInitValue = 0x00,\r
+ .ComSignalLength = 0,\r
+ .ComSignalType = UINT8,\r
+ .ComTimeoutFactor = 0,\r
+ .ComTimeoutNotification = NULL,\r
+ .ComTransferProperty = TRIGGERED,\r
+ .ComUpdateBitPosition = 0,\r
+ .ComSignalEcoreUseUpdateBit = 0,\r
+ .ComFilter = {\r
+ .ComFilterAlgorithm = ALWAYS,\r
+ .ComFilterMask = 0,\r
+ .ComFilterMax = 0,\r
+ .ComFilterMin = 0,\r
+ .ComFilterOffset = 0,\r
+ .ComFilterPeriodFactor = 0,\r
+ .ComFilterX = 0\r
+ }\r
+ },\r
+\r
+ // Signals for PCAN_TX_FRAME_2\r
+ {\r
+ .ComBitPosition = 0,\r
+ .ComBitSize = 8,\r
+ //.ComDataInvalidAction (NOT IMPLEMENTED)\r
+ .ComErrorNotification = NULL,\r
+ .ComFirstTimeoutFactor = 0,\r
+ .ComHandleId = 12,\r
+ //.ComInvalidNotification (NOT IMPLEMENTED)\r
+ .ComNotification = NULL,\r
+ //.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
+ //.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
+ .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalInitValue = 0x0,\r
+ .ComSignalLength = 0,\r
+ .ComSignalType = UINT8,\r
+ .ComTimeoutFactor = 0,\r
+ .ComTimeoutNotification = NULL,\r
+ .ComTransferProperty = TRIGGERED,\r
+ .ComUpdateBitPosition = 0,\r
+ .ComSignalEcoreUseUpdateBit = 0,\r
+ .ComFilter = {\r
+ .ComFilterAlgorithm = ALWAYS,\r
+ .ComFilterMask = 0,\r
+ .ComFilterMax = 0,\r
+ .ComFilterMin = 0,\r
+ .ComFilterOffset = 0,\r
+ .ComFilterPeriodFactor = 0,\r
+ .ComFilterX = 0\r
+ }\r
+ },\r
+ {\r
+ .ComBitPosition = 8,\r
+ .ComBitSize = 8,\r
+ //.ComDataInvalidAction (NOT IMPLEMENTED)\r
+ .ComErrorNotification = NULL,\r
+ .ComFirstTimeoutFactor = 0,\r
+ .ComHandleId = 13,\r
+ //.ComInvalidNotification (NOT IMPLEMENTED)\r
+ .ComNotification = NULL,\r
+ //.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
+ //.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
+ .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalInitValue = 0x00,\r
+ .ComSignalLength = 0,\r
+ .ComSignalType = UINT8,\r
+ .ComTimeoutFactor = 0,\r
+ .ComTimeoutNotification = NULL,\r
+ .ComTransferProperty = TRIGGERED,\r
+ .ComUpdateBitPosition = 0,\r
+ .ComSignalEcoreUseUpdateBit = 0,\r
+ .ComFilter = {\r
+ .ComFilterAlgorithm = ALWAYS,\r
+ .ComFilterMask = 0,\r
+ .ComFilterMax = 0,\r
+ .ComFilterMin = 0,\r
+ .ComFilterOffset = 0,\r
+ .ComFilterPeriodFactor = 0,\r
+ .ComFilterX = 0\r
+ }\r
+ },\r
+ {\r
+ .ComBitPosition = 16,\r
+ .ComBitSize = 1,\r
+ //.ComDataInvalidAction (NOT IMPLEMENTED)\r
+ .ComErrorNotification = NULL,\r
+ .ComFirstTimeoutFactor = 0,\r
+ .ComHandleId = 14,\r
+ //.ComInvalidNotification (NOT IMPLEMENTED)\r
+ .ComNotification = NULL,\r
+ //.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
+ //.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
+ .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalInitValue = 0x00,\r
+ .ComSignalLength = 0,\r
+ .ComSignalType = UINT8,\r
+ .ComTimeoutFactor = 0,\r
+ .ComTimeoutNotification = NULL,\r
+ .ComTransferProperty = TRIGGERED,\r
+ .ComUpdateBitPosition = 0,\r
+ .ComSignalEcoreUseUpdateBit = 0,\r
+ .ComFilter = {\r
+ .ComFilterAlgorithm = ALWAYS,\r
+ .ComFilterMask = 0,\r
+ .ComFilterMax = 0,\r
+ .ComFilterMin = 0,\r
+ .ComFilterOffset = 0,\r
+ .ComFilterPeriodFactor = 0,\r
+ .ComFilterX = 0\r
+ }\r
+ },\r
+ {\r
+ .ComBitPosition = 17,\r
+ .ComBitSize = 2,\r
+ //.ComDataInvalidAction (NOT IMPLEMENTED)\r
+ .ComErrorNotification = NULL,\r
+ .ComFirstTimeoutFactor = 0,\r
+ .ComHandleId = 15,\r
+ //.ComInvalidNotification (NOT IMPLEMENTED)\r
+ .ComNotification = NULL,\r
+ //.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
+ //.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
+ .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalInitValue = 0x00,\r
+ .ComSignalLength = 0,\r
+ .ComSignalType = UINT8,\r
+ .ComTimeoutFactor = 0,\r
+ .ComTimeoutNotification = NULL,\r
+ .ComTransferProperty = TRIGGERED,\r
+ .ComUpdateBitPosition = 0,\r
+ .ComSignalEcoreUseUpdateBit = 0,\r
+ .ComFilter = {\r
+ .ComFilterAlgorithm = ALWAYS,\r
+ .ComFilterMask = 0,\r
+ .ComFilterMax = 0,\r
+ .ComFilterMin = 0,\r
+ .ComFilterOffset = 0,\r
+ .ComFilterPeriodFactor = 0,\r
+ .ComFilterX = 0\r
+ }\r
+ },\r
+ {\r
+ .ComEcoreEOL = 1\r
+ }\r
+};\r
+\r
+// Definitions of IPDU groups.\r
+ComIPduGroup_type PCAN_ComIPduGroup[] = {\r
+ {\r
+ .ComIPduGroupHandleId = 0\r
+ },\r
+ {\r
+ .ComEcoreEOL = 1\r
+ }\r
+};\r
+\r
+ComIPdu_type PCAN_ComIPdu[] = {\r
+ // This CAN-message is used to update properties of the engine.\r
+ {\r
+ .ComIPduCallout = NULL,\r
+ .ComIPduRxHandleId = PCAN_RX_FRAME_1,\r
+ .ComIPduSignalProcessing = IMMEDIATE,\r
+ .ComIPduSize = 8,\r
+ .ComIPduDirection = RECEIVE,\r
+ .ComIPduGroupRef = &PCAN_ComIPduGroup[0],\r
+ //.ComIPduSignalGroupRef (NOT IMPLEMENTED)\r
+ //./PduIdRef (NOT IMPLEMENTED)\r
+ .ComTxIPdu = {NULL},\r
+ .ComIPduSignalRef = {\r
+ &PCAN_ComSignal[0],\r
+ &PCAN_ComSignal[1],\r
+ &PCAN_ComSignal[2],\r
+ &PCAN_ComSignal[3],\r
+ NULL,\r
+ },\r
+ },\r
+ // This CAN-message is used to update properties of the engine.\r
+ {\r
+ .ComIPduCallout = NULL,\r
+ .ComIPduRxHandleId = PCAN_RX_FRAME_2,\r
+ .ComIPduSignalProcessing = IMMEDIATE,\r
+ .ComIPduSize = 8,\r
+ .ComIPduDirection = RECEIVE,\r
+ .ComIPduGroupRef = &PCAN_ComIPduGroup[0],\r
+ //.ComIPduSignalGroupRef (NOT IMPLEMENTED)\r
+ //./PduIdRef (NOT IMPLEMENTED)\r
+ .ComTxIPdu = {NULL},\r
+ .ComIPduSignalRef = {\r
+ &PCAN_ComSignal[4],\r
+ &PCAN_ComSignal[5],\r
+ &PCAN_ComSignal[6],\r
+ &PCAN_ComSignal[7],\r
+ NULL,\r
+ },\r
+ },\r
+ {\r
+ .ComIPduCallout = NULL,\r
+ .ComIPduRxHandleId = PCAN_TX_FRAME_1,\r
+ .ComIPduSignalProcessing = IMMEDIATE,\r
+ .ComIPduSize = 8,\r
+ .ComIPduDirection = SEND,\r
+ .ComIPduGroupRef = &PCAN_ComIPduGroup[0],\r
+ //.ComIPduSignalGroupRef (NOT IMPLEMENTED)\r
+ //./PduIdRef (NOT IMPLEMENTED)\r
+ .ComTxIPdu = {\r
+ .ComTxIPduMinimumDelayFactor = 0,\r
+ .ComTxIPduUnusedAreasDefault = 0x00,\r
+ .ComTxModeTrue = {\r
+ .ComTxModeMode = DIRECT,\r
+ .ComTxModeNumberOfRepetitions = 0,\r
+ .ComTxModeRepetitionPeriodFactor = 0,\r
+ .ComTxModeTimeOffsetFactor = 0,\r
+ .ComTxModeTimePeriodFactor = 0,\r
+ },\r
+ //.ComTxModeFalse (NOT IMPLEMENTED)\r
+ },\r
+ .ComIPduSignalRef = {\r
+ &PCAN_ComSignal[8],\r
+ &PCAN_ComSignal[9],\r
+ &PCAN_ComSignal[10],\r
+ &PCAN_ComSignal[11],\r
+ NULL,\r
+ },\r
+ },\r
+ {\r
+ .ComIPduCallout = NULL,\r
+ .ComIPduRxHandleId = PCAN_TX_FRAME_2,\r
+ .ComIPduSignalProcessing = IMMEDIATE,\r
+ .ComIPduSize = 8,\r
+ .ComIPduDirection = SEND,\r
+ .ComIPduGroupRef = &PCAN_ComIPduGroup[0],\r
+ //.ComIPduSignalGroupRef (NOT IMPLEMENTED)\r
+ //./PduIdRef (NOT IMPLEMENTED)\r
+ .ComTxIPdu = {\r
+ .ComTxIPduMinimumDelayFactor = 0,\r
+ .ComTxIPduUnusedAreasDefault = 0x00,\r
+ .ComTxModeTrue = {\r
+ .ComTxModeMode = DIRECT,\r
+ .ComTxModeNumberOfRepetitions = 0,\r
+ .ComTxModeRepetitionPeriodFactor = 0,\r
+ .ComTxModeTimeOffsetFactor = 0,\r
+ .ComTxModeTimePeriodFactor = 0,\r
+ },\r
+ //.ComTxModeFalse (NOT IMPLEMENTED)\r
+ },\r
+ .ComIPduSignalRef = {\r
+ &PCAN_ComSignal[12],\r
+ &PCAN_ComSignal[13],\r
+ &PCAN_ComSignal[14],\r
+ &PCAN_ComSignal[15],\r
+ NULL,\r
+ },\r
+ },\r
+\r
+ {\r
+ .ComEcoreEOL = 1\r
+ }\r
+};\r
+\r
+Com_ConfigType PCAN_ComConfig = {\r
+ .ComConfigurationId = 2,\r
+ .ComIPdu = PCAN_ComIPdu,\r
+ .ComIPduGroup = PCAN_ComIPduGroup,\r
+ .ComSignal = PCAN_ComSignal,\r
+};\r
+\r
+\r
+\r
+\r
+\r
+\r
+/*\r
+ * Target test configuration
+ */\r
+ComGroupSignal_type HardwareTest_ComGroupSignal[] = {\r
+ {\r
+ .ComBitPosition = 32,\r
+ .ComBitSize = 8,\r
+ .ComHandleId = 0,\r
+ .ComSignalType = UINT8,\r
+ },\r
+ {\r
+ .ComBitPosition = 40,\r
+ .ComBitSize = 2,\r
+ .ComHandleId = 1,\r
+ .ComSignalType = UINT8,\r
+ }\r
+};\r
+\r
+ComSignal_type HardwareTest_ComSignal[] = {\r
+ {\r
+ .ComBitPosition = 0,\r
+ .ComBitSize = 16,\r
+ //.ComDataInvalidAction (NOT IMPLEMENTED)\r
+ .ComErrorNotification = NULL,\r
+ .ComFirstTimeoutFactor = 0,\r
+ .ComHandleId = 0,\r
+ //.ComInvalidNotification (NOT IMPLEMENTED)\r
+ .ComNotification = NULL,\r
+ //.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
+ //.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
+ .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalInitValue = 0xFF,\r
+ .ComSignalLength = 0,\r
+ .ComSignalType = UINT16,\r
+ .ComTimeoutFactor = 0,\r
+ .ComTimeoutNotification = NULL,\r
+ .ComTransferProperty = TRIGGERED,\r
+ .ComUpdateBitPosition = 16,\r
+ .ComSignalEcoreUseUpdateBit = 1,\r
+ .ComFilter = {\r
+ .ComFilterAlgorithm = ALWAYS,\r
+ .ComFilterMask = 0,\r
+ .ComFilterMax = 0,\r
+ .ComFilterMin = 0,\r
+ .ComFilterOffset = 0,\r
+ .ComFilterPeriodFactor = 0,\r
+ .ComFilterX = 0\r
+ }\r
+ },\r
+ {\r
+ .ComBitPosition = 0,\r
+ .ComBitSize = 16,\r
+ //.ComDataInvalidAction (NOT IMPLEMENTED)\r
+ .ComErrorNotification = NULL,\r
+ .ComFirstTimeoutFactor = 0,\r
+ .ComHandleId = 1,\r
+ //.ComInvalidNotification (NOT IMPLEMENTED)\r
+ .ComNotification = RTE_EngineChangeSpeed,\r
+ //.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
+ //.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
+ .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalInitValue = 0x00,\r
+ .ComSignalLength = 0,\r
+ .ComSignalType = UINT16,\r
+ .ComTimeoutFactor = 0,\r
+ .ComTimeoutNotification = NULL,\r
+ .ComTransferProperty = TRIGGERED,\r
+ .ComUpdateBitPosition = 16,\r
+ .ComSignalEcoreUseUpdateBit = 1,\r
+ .ComFilter = {\r
+ .ComFilterAlgorithm = ALWAYS,\r
+ .ComFilterMask = 0,\r
+ .ComFilterMax = 0,\r
+ .ComFilterMin = 0,\r
+ .ComFilterOffset = 0,\r
+ .ComFilterPeriodFactor = 0,\r
+ .ComFilterX = 0\r
+ }\r
+ },\r
+\r
+ // This is a signal group\r
+ {\r
+ //.ComBitPosition = 0,\r
+ //.ComBitSize = 16,\r
+ //.ComDataInvalidAction (NOT IMPLEMENTED)\r
+ //.ComErrorNotification = NULL,\r
+ //.ComFirstTimeoutFactor = 0,\r
+ .ComHandleId = 2,\r
+ //.ComInvalidNotification (NOT IMPLEMENTED)\r
+ .ComNotification = RTE_SIL2MESSAGE,\r
+ //.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
+ //.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
+ //.ComSignalEndianess = BIG_ENDIAN,\r
+ //.ComSignalInitValue = 0xFF,\r
+ //.ComSignalLength = 0,\r
+ //.ComSignalType = UINT16,\r
+ //.ComTimeoutFactor = 0,\r
+ //.ComTimeoutNotification = NULL,\r
+ //.ComTransferProperty = TRIGGERED,\r
+ .ComUpdateBitPosition = 42,\r
+ .ComSignalEcoreUseUpdateBit = 1,\r
+ .ComEcoreIsSignalGroup = 1,\r
+ .ComGroupSignal = {\r
+ &HardwareTest_ComGroupSignal[0],\r
+ &HardwareTest_ComGroupSignal[1],\r
+ },\r
+ /*.ComFilter = {\r
+ .ComFilterAlgorithm = ALWAYS,\r
+ .ComFilterMask = 0,\r
+ .ComFilterMax = 0,\r
+ .ComFilterMin = 0,\r
+ .ComFilterOffset = 0,\r
+ .ComFilterPeriodFactor = 0,\r
+ .ComFilterX = 0\r
+ }*/\r
+ },\r
+ {\r
+ .ComEcoreEOL = 1\r
+ }\r
+};\r
+\r
+// Definitions of IPDU groups.\r
+ComIPduGroup_type HardwareTest_ComIPduGroup[] = {\r
+ {\r
+ .ComIPduGroupHandleId = 0\r
+ },\r
+ {\r
+ .ComIPduGroupHandleId = 1\r
+ },\r
+ {\r
+ .ComIPduGroupHandleId = 2\r
+ },\r
+ {\r
+ .ComEcoreEOL = 1\r
+ }\r
+};\r
+\r
+ComIPdu_type HardwareTest_ComIPdu[] = {\r
+ {\r
+ .ComIPduCallout = NULL,\r
+ .ComIPduRxHandleId = PDU_MSG_HARDWARE_TEST_ENGINE_STATUS,\r
+ .ComIPduSignalProcessing = IMMEDIATE,\r
+ .ComIPduSize = 8,\r
+ .ComIPduDirection = SEND,\r
+ .ComIPduGroupRef = &HardwareTest_ComIPduGroup[0],\r
+ //.ComIPduSignalGroupRef (NOT IMPLEMENTED)\r
+ //./PduIdRef (NOT IMPLEMENTED)\r
+ .ComTxIPdu = {\r
+ .ComTxIPduMinimumDelayFactor = 500,\r
+ .ComTxIPduUnusedAreasDefault = 0x00,\r
+ .ComTxModeTrue = {\r
+ .ComTxModeMode = MIXED,\r
+ .ComTxModeNumberOfRepetitions = 0,\r
+ .ComTxModeRepetitionPeriodFactor = 0,\r
+ .ComTxModeTimeOffsetFactor = 400,\r
+ .ComTxModeTimePeriodFactor = 1000,\r
+ },\r
+ //.ComTxModeFalse (NOT IMPLEMENTED)\r
+ },\r
+ .ComIPduSignalRef = {\r
+ &HardwareTest_ComSignal[0],\r
+ NULL,\r
+ },\r
+ },\r
+\r
+ // This CAN-message is used to update properties of the engine.\r
+ {\r
+ .ComIPduCallout = NULL,\r
+ .ComIPduRxHandleId = PDU_MSG_HARDWARE_TEST_ENGINE_CONTROL,\r
+ .ComIPduSignalProcessing = IMMEDIATE,\r
+ .ComIPduSize = 8,\r
+ .ComIPduDirection = RECEIVE,\r
+ .ComIPduGroupRef = &HardwareTest_ComIPduGroup[0],\r
+ //.ComIPduSignalGroupRef (NOT IMPLEMENTED)\r
+ //./PduIdRef (NOT IMPLEMENTED)\r
+ .ComTxIPdu = {NULL},\r
+ .ComIPduSignalRef = {\r
+ &HardwareTest_ComSignal[1],\r
+ &HardwareTest_ComSignal[2],\r
+ NULL,\r
+ },\r
+ },\r
+\r
+\r
+ // This is a gateway mode message on the PDU router level.\r
+ {\r
+ .ComIPduCallout = NULL,\r
+ .ComIPduRxHandleId = PDU_MSG_HARDWARE_TEST_ROUTED_MSG,\r
+ .ComIPduSize = 0,\r
+ .ComIPduDirection = RECEIVE,\r
+ .ComIPduGroupRef = &HardwareTest_ComIPduGroup[0],\r
+ //.ComIPduSignalGroupRef (NOT IMPLEMENTED)\r
+ //./PduIdRef (NOT IMPLEMENTED)\r
+ .ComTxIPdu = {NULL},\r
+ .ComIPduSignalRef = {\r
+ NULL\r
+ },\r
+ },\r
+ {\r
+ .ComEcoreEOL = 1\r
+ }\r
+};\r
+\r
+Com_ConfigType HardwareTest_ComConfig = {\r
+ .ComConfigurationId = 2,\r
+ .ComIPdu = HardwareTest_ComIPdu,\r
+ .ComIPduGroup = HardwareTest_ComIPduGroup,\r
+ .ComSignal = HardwareTest_ComSignal,\r
+ .ComGroupSignal = HardwareTest_ComGroupSignal\r
+};\r
+\r
+\r
+\r
+// TEST CONFIGURATION\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef _COM_PBCFG_H\r
+#define _COM_PBCFG_H\r
+\r
+#include "Com_Types.h"\r
+\r
+extern Com_ConfigType PCAN_ComConfig;\r
+extern Com_ConfigType HardwareTest_ComConfig;\r
+\r
+#endif /*_COM_PBCFG_H*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*\r
+ * Development Error Tracer driver\r
+ *\r
+ * Specification: Autosar v2.0.1, Final\r
+ *\r
+ */\r
+#ifndef _DET_CFG_H_\r
+#define _DET_CFG_H_\r
+\r
+#define DET_ENABLE_CALLBACKS STD_ON // Enable to use callback on errors\r
+#define DET_USE_RAMLOG STD_ON // Enable to log DET errors to ramlog\r
+#define DET_WRAP_RAMLOG STD_ON // The ramlog wraps around when reaching the end\r
+#define DET_USE_STDERR STD_ON // Enable to get DET errors on stderr\r
+\r
+#define DET_DEINIT_API STD_ON // Enable/Disable the Det_DeInit function\r
+\r
+#define DET_RAMLOG_SIZE (32) // Number of entries in ramlog\r
+#define DET_NUMBER_OF_CALLBACKS (5) // Number of callbacks\r
+\r
+#endif /*_DET_CFG_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef DIO_CFG_H_\r
+#define DIO_CFG_H_\r
+\r
+#define DIO_VERSION_INFO_API STD_ON\r
+#define DIO_DEV_ERROR_DETECT STD_ON\r
+#define DIO_END_OF_LIST -1\r
+\r
+// Channels\r
+extern const Dio_ChannelType DioChannelConfigData[];\r
+#define CHANNEL_PTR (&DioChannelConfigData)\r
+\r
+// Port\r
+extern const Dio_PortType DioPortConfigData[];\r
+#define PORT_PTR (&DioPortConfigData)\r
+\r
+// Channel group\r
+extern const Dio_ChannelGroupType DioConfigData[];\r
+#define CHANNEL_GRP_PTR (&DioConfigData)\r
+\r
+// Mapping of logical ports to physical\r
+\r
+// Channels\r
+#define LED_K2 (125)\r
+\r
+// Port\r
+// No ports available for MPC5567\r
+\r
+// Channel group\r
+#define LED_GRP_PTR (&DioConfigData[0])\r
+\r
+//\r
+// Channels\r
+//\r
+#define CONTROL_BUS_EN\r
+#define CONTROL_BUS_STB\r
+#define CONTROL_BUS_ERR\r
+#define CONTROL_BUS_S_PLUS_ST\r
+#define CONTROL_BUS_S_MINUS_ST\r
+#define CONTROL_BUS_S_PLUS_IN\r
+\r
+#define MULTILINK_SO_IN\r
+#define MULTILINK_SO_ST\r
+\r
+#define DATALINK_CANERR\r
+#define DATALINK_CANEN\r
+#define DATALINK_CANSTB\r
+\r
+#define RF_PWM\r
+#define RF_C1\r
+#define RF_C2\r
+\r
+#define IO_SOUND_EN\r
+#define IO_SOUND\r
+\r
+//\r
+// Channel groups\r
+//\r
+#define CONTROL_BUS (DioConfigData)\r
+#define MULTILINK_BUS (DioConfigData)\r
+#define RF (DioConfigData)\r
+#define IO (DioConfigData)\r
+\r
+//\r
+// Port mapping\r
+//\r
+\r
+// Hmm, We have no need for any.. we group with channel group instead\r
+\r
+#endif /*DIO_CFG_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include "Dio.h"\r
+#include "Dio_Cfg.h"\r
+\r
+const Dio_ChannelType DioChannelConfigData[] =\r
+{ LED_K2, DIO_END_OF_LIST, };\r
+\r
+// No ports available for 5567\r
+const Dio_PortType DioPortConfigData[] =\r
+{ DIO_END_OF_LIST };\r
+\r
+const Dio_ChannelGroupType DioConfigData[] =\r
+{\r
+ { .port = DIO_END_OF_LIST, .offset = DIO_END_OF_LIST, .mask = DIO_END_OF_LIST, },\r
+};\r
+\r
+uint32 Dio_GetPortConfigSize(void)\r
+{\r
+ return sizeof(DioConfigData);\r
+}\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include "Dma.h"\r
+\r
+\r
+const Dma_ChannelConfigType DmaChannelConfig [DMA_NUMBER_OF_CHANNELS] =\r
+{\r
+ { .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP0_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },\r
+ { .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP0_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },\r
+\r
+ { .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP1_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },\r
+ { .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP1_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },\r
+\r
+ { .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP2_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },\r
+ { .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP2_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },\r
+\r
+ { .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP3_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },\r
+ { .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP3_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },\r
+\r
+ { .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP4_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },\r
+ { .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP4_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },\r
+\r
+ { .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP5_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },\r
+ { .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP5_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },\r
+\r
+ { .DMA_CHANNEL_PRIORITY = DMA_SPI_B_TRANSMIT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },\r
+ { .DMA_CHANNEL_PRIORITY = DMA_SPI_B_RECEIVE_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },\r
+\r
+ { .DMA_CHANNEL_PRIORITY = DMA_SPI_C_TRANSMIT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },\r
+ { .DMA_CHANNEL_PRIORITY = DMA_SPI_C_RECEIVE_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },\r
+\r
+ { .DMA_CHANNEL_PRIORITY = DMA_SPI_D_TRANSMIT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },\r
+ { .DMA_CHANNEL_PRIORITY = DMA_SPI_D_RECEIVE_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },\r
+\r
+ { .DMA_CHANNEL_PRIORITY = DMA_SPI_COMBINED_TRANSMIT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },\r
+ { .DMA_CHANNEL_PRIORITY = DMA_SPI_COMBINED_RECEIVE_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },\r
+\r
+ { .DMA_CHANNEL_PRIORITY = DMA_EMIOS_0_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },\r
+ { .DMA_CHANNEL_PRIORITY = DMA_EMIOS_1_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },\r
+ { .DMA_CHANNEL_PRIORITY = DMA_EMIOS_2_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },\r
+ { .DMA_CHANNEL_PRIORITY = DMA_EMIOS_3_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },\r
+ { .DMA_CHANNEL_PRIORITY = DMA_EMIOS_4_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },\r
+ { .DMA_CHANNEL_PRIORITY = DMA_EMIOS_8_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },\r
+ { .DMA_CHANNEL_PRIORITY = DMA_EMIOS_9_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },\r
+\r
+ { .DMA_CHANNEL_PRIORITY = DMA_TPU_0_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },\r
+ { .DMA_CHANNEL_PRIORITY = DMA_TPU_1_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },\r
+ { .DMA_CHANNEL_PRIORITY = DMA_TPU_2_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },\r
+ { .DMA_CHANNEL_PRIORITY = DMA_TPU_14_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },\r
+ { .DMA_CHANNEL_PRIORITY = DMA_TPU_15_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },\r
+\r
+};\r
+\r
+\r
+const Dma_ConfigType DmaConfig []=\r
+{\r
+ {DmaChannelConfig, DMA_FIXED_PRIORITY_ARBITRATION}\r
+};\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef DMA_CFG_H_\r
+#define DMA_CFG_H_\r
+\r
+// See section 9.4.3 DMA Request Assignments in MPC5567 RM\r
+typedef enum\r
+{\r
+ DMA_ADC_GROUP0_COMMAND_CHANNEL,\r
+ DMA_ADC_GROUP0_RESULT_CHANNEL,\r
+\r
+ DMA_ADC_GROUP1_COMMAND_CHANNEL,\r
+ DMA_ADC_GROUP1_RESULT_CHANNEL,\r
+\r
+ DMA_ADC_GROUP2_COMMAND_CHANNEL,\r
+ DMA_ADC_GROUP2_RESULT_CHANNEL,\r
+\r
+ DMA_ADC_GROUP3_COMMAND_CHANNEL,\r
+ DMA_ADC_GROUP3_RESULT_CHANNEL,\r
+\r
+ DMA_ADC_GROUP4_COMMAND_CHANNEL,\r
+ DMA_ADC_GROUP4_RESULT_CHANNEL,\r
+\r
+ DMA_ADC_GROUP5_COMMAND_CHANNEL,\r
+ DMA_ADC_GROUP5_RESULT_CHANNEL,\r
+\r
+ DMA_SPI_B_TRANSMIT_CHANNEL,\r
+ DMA_SPI_B_RECEIVE_CHANNEL,\r
+\r
+ DMA_SPI_C_TRANSMIT_CHANNEL,\r
+ DMA_SPI_C_RECEIVE_CHANNEL,\r
+\r
+ DMA_SPI_D_TRANSMIT_CHANNEL,\r
+ DMA_SPI_D_RECEIVE_CHANNEL,\r
+\r
+ DMA_SPI_COMBINED_TRANSMIT_CHANNEL,\r
+ DMA_SPI_COMBINED_RECEIVE_CHANNEL,\r
+\r
+ DMA_EMIOS_0_CHANNEL,\r
+ DMA_EMIOS_1_CHANNEL,\r
+ DMA_EMIOS_2_CHANNEL,\r
+ DMA_EMIOS_3_CHANNEL,\r
+ DMA_EMIOS_4_CHANNEL,\r
+ DMA_EMIOS_8_CHANNEL,\r
+ DMA_EMIOS_9_CHANNEL,\r
+\r
+ DMA_TPU_0_CHANNEL,\r
+ DMA_TPU_1_CHANNEL,\r
+ DMA_TPU_2_CHANNEL,\r
+ DMA_TPU_14_CHANNEL,\r
+ DMA_TPU_15_CHANNEL,\r
+\r
+ DMA_NUMBER_OF_CHANNELS\r
+} Dma_ChannelType;\r
+\r
+\r
+\r
+#endif /* DMA_CFG_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef ECUM_CFG_H_\r
+#define ECUM_CFG_H_\r
+\r
+#define ECUM_VERSION_INFO_API STD_ON\r
+#define ECUM_INCLUDE_NVRAM_MGR STD_OFF\r
+#define ECUM_DEV_ERROR_DETECT STD_ON\r
+\r
+#include "EcuM_Generated_Types.h"\r
+\r
+#endif /*ECUM_CFG_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef EEP_CFG_H_
+#define EEP_CFG_H_
+
+#include "Spi.h"
+
+/* EepGeneral */
+
+// Switches to activate or deactivate interrupt controlled job processing. true:
+// Interrupt controlled job processing enabled. false: Interrupt controlled job
+// processing disabled.
+#define EEP_USE_INTERRUPTS STD_OFF
+
+// Pre-processor switch to enable and disable development error detection.
+// true: Development error detection enabled. false: Development error
+// detection disabled.
+#define EEP_DEV_ERROR_DETECT STD_ON
+
+// Pre-processor switch to enable / disable the API to read out the modules
+// version information. true: Version info API enabled. false: Version info API
+// disabled.
+#define EEP_VERSION_INFO_API STD_ON
+
+// ndex of the driver, used by EA.
+#define EEP_DRIVER_INDEX 1
+
+// Switches to activate or deactivate write cycle reduction (EEPROM value is
+// read and compared before being overwritten). true: Write cycle reduction
+// enabled. false: Write cycle reduction disabled.
+#define EEP_WRITE_CYCLE_REDUCTION STD_OFF
+
+// Container for runtime configuration parameters of the EEPROM driver.
+// Implementation Type: Eep_ConfigType.
+
+/* EepPublishedInformation
+ *
+ * TODO
+ *
+ * 3.0 additions?
+ */
+
+// Total size of EEPROM in bytes. Implementation Type: Eep_LengthType.
+#define EEP_TOTAL_SIZE TBD
+
+// Size of smallest erasable EEPROM data unit in bytes.
+#define EEP_ERASE_UNIT_SIZE TBD
+
+// EepMinimumLengthType {EEP_MINIMUM_LENGTH_TYPE}
+// Minimum expected size of Eep_LengthType.
+#define EEP_MINIMUM_LENGTH_TYPE TBD
+
+// Minimum expected size of Eep_AddressType.
+#define EEP_MINIMUM_ADDRESS_TYPE TBD
+
+// Size of smallest writable EEPROM data unit in bytes.
+#define EEP_WRITE_UNIT_SIZE TBD
+
+// Value of an erased EEPROM cell.
+#define EEP_ERASE_VALUE 0
+
+// Number of erase cycles specified for the EEP device (usually given in the
+// device data sheet).
+#define EEP_SPECIFIED_ERASE_CYCLES TBD
+
+// Size of smallest readable EEPROM data unit in bytes.
+#define EEP_READ_UNIT_SIZE TBD
+
+// Time for writing one EEPROM data unit.
+#define EEP_WRITE_TIME TBD
+
+// Time for erasing one EEPROM data unit
+#define EEP_ERASE_TIME TBD
+
+// Specified maximum number of write cycles under worst case conditions of
+// specific EEPROM hardware (e.g. +90°C)
+#define EEP_ALLOWED_WRITE_CYCLES x
+
+
+typedef struct {
+
+ /* EEP094 */
+
+ Spi_SequenceType EepCmdSequence;
+ Spi_SequenceType EepCmd2Sequence;
+ Spi_SequenceType EepReadSequence;
+ Spi_SequenceType EepWriteSequence;
+
+ Spi_ChannelType EepAddrChannel;
+ Spi_ChannelType EepCmdChannel;
+ Spi_ChannelType EepDataChannel;
+ Spi_ChannelType EepWrenChannel;
+
+ // number of bytes read within one job processing cycle in normal mode.
+ Eep_LengthType EepNormalReadBlockSize;
+
+ // call cycle of the job processing function during write/erase operations. Unit: [s]
+ float EepJobCallCycle;
+
+ // This parameter is the used size of EEPROM device in bytes.
+ Eep_LengthType EepSize;
+
+ // This parameter is a reference to a callback function for positive job result
+ void (*Eep_JobEndNotification)();
+
+ // This parameter is the default EEPROM device mode after initialization.
+ MemIf_ModeType EepDefaultMode;
+
+ // This parameter is the number of bytes read within one job processing cycle in fast mode
+ Eep_LengthType EepFastReadBlockSize;
+
+ // Number of bytes written within one job processing cycle in normal mode.
+ Eep_LengthType EepNormalWriteBlockSize;
+
+ // This parameter is a reference to a callback function for negative job result
+ void (*Eep_JobErrorNotification)();
+
+ // This parameter is the number of bytes written within one job processing cycle in fast mode
+ Eep_LengthType EepFastWriteBlockSize;
+
+ // This parameter is the EEPROM device base address.
+ Eep_AddressType EepBaseAddress;
+} Eep_ConfigType;
+
+// This container is present for external EEPROM drivers only. Internal
+// EEPROM drivers do not use the parameter listed in this container, hence
+// its multiplicity is 0 for internal drivers.
+typedef struct {
+ // Reference to SPI sequence (required for external EEPROM drivers).
+ // TODO: hmmm....
+ uint32 SpiReference;
+} Eep_ExternalDriverType;
+
+extern const Eep_ConfigType EepConfigData[];
+
+#define EEP_DEFAULT_CONFIG EepConfigData[0]
+
+#endif /*EEP_CFG_H_*/
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+
+#include "Eep.h"
+#include "Spi.h"
+#include "Spi_Cfg.h"
+
+//#define USE_TRACE 1
+//#define USE_DEBUG 1
+#undef DEBUG_LVL
+#define DEBUG_LVL DEBUG_LOW
+#include "Trace.h"
+
+static void _JobEndNotify(){
+ DEBUG(DEBUG_LOW,"EEP JOB END NOTIFICATION\n");
+}
+static void _JobErrorNotify(){
+ DEBUG(DEBUG_LOW,"EEP JOB ERROR NOTIFICATION\n");
+}
+
+const Eep_ConfigType EepConfigData[] = {
+ {
+
+ // READ and WRITE sequences and ID's defined in Spi_Cfg.h
+ .EepCmdSequence = SPI_SEQ_EEP_CMD,
+ .EepCmd2Sequence = SPI_SEQ_EEP_CMD2,
+ .EepReadSequence = SPI_SEQ_EEP_READ,
+ .EepWriteSequence = SPI_SEQ_EEP_WRITE,
+
+ // Channels used
+ .EepCmdChannel = SPI_CH_EEP_CMD,
+ .EepAddrChannel = SPI_CH_EEP_ADDR,
+ .EepWrenChannel = SPI_CH_EEP_WREN,
+ .EepDataChannel = SPI_CH_EEP_DATA,
+
+#if 0
+ .EepCmdJob = SPI_EEP_CMD_JOB,
+ .EepDataJob = SPI_EEP_DATA_JOB,
+
+ // Channels used
+ .EepCmdChannel = SPI_EEP_CMD_CH,
+ .EepAdrChannel = SPI_EEP_ADR_CH,
+ .EepDataChannel = SPI_EEP_DATA_CH,
+
+ // READ and WRITE sequences and ID's defined in Spi_Cfg.h
+ .EepReadSequence = SPI_EEP_SEQ_READ,
+ .EepWriteSequence = SPI_EEP_SEQ_WRITE,
+
+ // number of bytes read within one job processing cycle in normal mode.
+ .EepInitConfiguration = 1,
+#endif
+
+ // call cycle of the job processing function during write/erase operations. Unit: [s]
+ .EepJobCallCycle = 0.2,
+
+ // This parameter is the used size of EEPROM device in bytes.
+ .EepSize = 0x8000,
+
+ // This parameter is a reference to a callback function for positive job result
+ .Eep_JobEndNotification = &_JobEndNotify,
+
+ // This parameter is the default EEPROM device mode after initialization.
+ .EepDefaultMode = MEMIF_MODE_FAST,
+
+ // This parameter is the number of bytes read within one job processing cycle in fast mode
+ .EepFastReadBlockSize = 64,
+
+ .EepNormalReadBlockSize = 4,
+
+ // Number of bytes written within one job processing cycle in normal mode.
+ .EepNormalWriteBlockSize = 1,
+
+ // This parameter is a reference to a callback function for negative job result
+ .Eep_JobErrorNotification = &_JobErrorNotify,
+
+ // This parameter is the number of bytes written within one job processing cycle in fast mode
+ .EepFastWriteBlockSize = 64,
+
+ // This parameter is the EEPROM device base address.
+ .EepBaseAddress = 0
+ }
+};
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+
+#include "Eep.h"
+#include "Spi.h"
+#include "Spi_Cfg.h"
+
+//#define USE_TRACE 1
+//#define USE_DEBUG 1
+#undef DEBUG_LVL
+#define DEBUG_LVL DEBUG_LOW
+#include "Trace.h"
+
+static void _JobEndNotify(){
+ DEBUG(DEBUG_LOW,"E2 JOB END NOTIFICATION\n");
+}
+static void _JobErrorNotify(){
+ DEBUG(DEBUG_LOW,"E2 JOB ERROR NOTIFICATION\n");
+}
+
+const Eep_ConfigType EepromConfigData[] = {
+ {
+ // READ and WRITE sequences and ID's defined in Spi_Cfg.h
+ .EepCmdSequence = SPI_SEQ_E2_CMD,
+ .EepCmd2Sequence = SPI_SEQ_E2_CMD2,
+ .EepReadSequence = SPI_SEQ_E2_READ,
+ .EepWriteSequence = SPI_SEQ_E2_WRITE,
+
+ // Channels used
+ .EepCmdChannel = SPI_CH_E2_CMD,
+ .EepAddrChannel = SPI_CH_E2_ADDR,
+ .EepWrenChannel = SPI_CH_E2_WREN,
+ .EepDataChannel = SPI_CH_E2_DATA,
+
+
+#if 0
+ // number of bytes read within one job processing cycle in normal mode.
+ .EepInitConfiguration = 1,
+#endif
+
+ // call cycle of the job processing function during write/erase operations. Unit: [s]
+ .EepJobCallCycle = 0.2,
+
+ // This parameter is the used size of EEPROM device in bytes.
+ .EepSize = 0x8000,
+
+ // This parameter is a reference to a callback function for positive job result
+ .Eep_JobEndNotification = &_JobEndNotify,
+
+ // This parameter is the default EEPROM device mode after initialization.
+ .EepDefaultMode = MEMIF_MODE_FAST,
+
+ // This parameter is the number of bytes read within one job processing cycle in fast mode
+ .EepFastReadBlockSize = 64,
+
+ .EepNormalReadBlockSize = 4,
+
+ // Number of bytes written within one job processing cycle in normal mode.
+ .EepNormalWriteBlockSize = 1,
+
+ // This parameter is a reference to a callback function for negative job result
+ .Eep_JobErrorNotification = &_JobErrorNotify,
+
+ // This parameter is the number of bytes written within one job processing cycle in fast mode
+ .EepFastWriteBlockSize = 64,
+
+ // This parameter is the EEPROM device base address.
+ .EepBaseAddress = 0
+ }
+};
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include "Fls.h"\r
+#include <stdlib.h>\r
+\r
+\r
+#define KB *1024\r
+\r
+\r
+const Fls_SectorType fls_evbSectorList[] = {\r
+ { // L0->L7\r
+ .FlsSectorStartaddress = (Fls_AddressType)0x00000000, // Start address of this sector\r
+ .FlsPageSize = (Fls_LengthType)8, // Read page size of 128 bits (4 words), (8 bytes)\r
+ .FlsSectorSize = (Fls_LengthType)(16 KB), // 16Kbyte\r
+ // Number of continuous sectors with the above characteristics.\r
+ .FlsNumberOfSectors = (uint32)8,// L0->L7 , 8 sectors\r
+ },\r
+ { // L8,L9\r
+ .FlsSectorStartaddress = (Fls_AddressType)0x00020000,\r
+ .FlsPageSize = (Fls_LengthType)8, // Read page size of 128 bits (4 words), (8 bytes)\r
+ .FlsSectorSize = (Fls_LengthType)(64 KB), // 64Kbyte\r
+ .FlsNumberOfSectors = (uint32)2,// L8,L9 , 2 sectors\r
+ },\r
+ { // M0->H7\r
+ .FlsSectorStartaddress = (Fls_AddressType)0x00040000,\r
+ .FlsPageSize = (Fls_LengthType)8, // Read page size of 128 bits (4 words), (8 bytes)\r
+ .FlsSectorSize = (Fls_LengthType)(128 KB), // 128Kbyte\r
+ .FlsNumberOfSectors = (uint32)6,// M0->H7\r
+ }\r
+};\r
+\r
+/*\r
+ * Block to partition map\r
+ */\r
+uint8 Fls_BlockToPartitionMap[] = { 1,1,1,1,2,2,2,2,3,3,4,4,5,5,6,6,7,7,8,8 };\r
+\r
+const Fls_ConfigType FlsConfigSet[]=\r
+{\r
+ {\r
+#if ( FLS_AC_LOAD_ON_JOB_START == STD_ON)\r
+ .FlsAcWrite = __FLS_ERASE_RAM__,\r
+ .FlsAcErase = __FLS_WRITE_RAM__,\r
+#else\r
+ .FlsAcWrite = NULL,\r
+ .FlsAcErase = NULL,\r
+#endif\r
+ .FlsJobEndNotification = NULL,\r
+ .FlsJobErrorNotification = NULL,\r
+\r
+ .FlsSectorList = &fls_evbSectorList[0],\r
+ .FlsSectorListSize = sizeof(fls_evbSectorList)/sizeof(Fls_SectorType),\r
+ .FlsBlockToPartitionMap = Fls_BlockToPartitionMap,\r
+ }\r
+};\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef FLS_CFG_H_
+#define FLS_CFG_H_
+
+#include "MemIf_Types.h"
+
+
+/* Indicate that we are building Post Build, NOT Pre-Compile */
+#define FLS_VARIANT_PB STD_ON
+
+/*
+ * Fls General container
+ */
+// The flash driver shall load the flash access code to RAM whenever an
+// erase or write job is started and unload (overwrite) it after that job has
+// been finished or canceled. true: Flash access code loaded on job start /
+// unloaded on job end or error. false: Flash access code not loaded to /
+// unloaded from RAM at all.
+#define FLS_AC_LOAD_ON_JOB_START STD_OFF
+
+// The flash memory start address (see also FLS118).
+// FLS169: This parameter defines the lower boundary for read / write /
+// erase and compare jobs.
+#define FLS_BASE_ADDRESS 0x00000000
+
+// Compile switch to enable and disable the Fls_Cancel function. true: API
+// supported / function provided. false: API not supported / function not pro-
+// vided
+#define FLS_CANCEL_API STD_OFF
+
+// Compile switch to enable and disable the Fls_Compare function. true: API
+// supported / function provided. false: API not supported / function not pro-
+// vided
+#define FLS_COMPARE_API STD_ON
+
+// Pre-processor switch for enabling the development error detection and
+// reporting (see FLS077).
+
+#define FLS_DEV_ERROR_DETECT STD_ON
+
+// Index of the driver, used by FEE.
+#define FLS_DRIVER_INDEX 100
+
+// Compile switch to enable and disable the Fls_GetJobResult function. true:
+// API supported / function provided. false: API not supported / function not
+// provided
+#define FLS_GET_JOB_RESULT_API STD_ON
+
+// Compile switch to enable and disable the Fls_GetStatus function. true: API
+// supported / function provided. false: API not supported / function not pro-
+// vided
+#define FLS_GET_STATUS_API STD_ON
+
+// Compile switch to enable and disable the Fls_SetMode function. true: API
+// supported / function provided. false: API not supported / function not pro-
+// vided
+#define FLS_SET_MODE_API STD_OFF
+
+// The total amount of flash memory in bytes (see also FLS118).
+// FLS170: This parameter in conjunction with FLS_BASE_ADDRESS
+// defines the upper boundary for read / write / erase and compare jobs
+#define FLS_TOTAL_SIZE 0x180000 // from addr 0x0000_0000 to 0x0018_0000
+#define FLS_READ_PAGE_SIZE 0x8 // Read page size of 128 bits (4 words) (8 bytes)
+
+
+// Job processing triggered by hardware interrupt. true: Job processing trig-
+// gered by interrupt (hardware controlled). false: Job processing not trig-
+// gered by interrupt (software controlled)
+
+// NOT supported by Freescale hardware
+#define FLS_USE_INTERRUPTS STD_OFF
+
+#define FLS_VERSION_INFO_API STD_ON
+
+
+#if ( FLS_AC_LOAD_ON_JOB_START == STD_ON )
+/* Sections that are provided by linker */
+extern void __FLS_ERASE_RAM__(void);
+extern void __FLS_WRITE_RAM__(void);
+extern void __FLS_ERASE_ROM__(void);
+extern void __FLS_WRITE_ROM__(void);
+extern char __FLS_SIZE__;
+#endif
+
+// Configuration description of a flashable sector
+typedef struct {
+ // Number of continuous sectors with the above characteristics.
+ Fls_LengthType FlsNumberOfSectors;
+
+ // Size of one page of this sector. Implementation Type: Fls_LengthType.
+ Fls_LengthType FlsPageSize;
+
+ // Size of this sector. Implementation Type: Fls_LengthTyp
+ Fls_LengthType FlsSectorSize;
+
+ // Start address of this sector
+ Fls_AddressType FlsSectorStartaddress;
+
+} Fls_SectorType;
+
+
+// Container for runtime configuration parameters of the flash driver. Imple-
+// mentation Type: Fls_ConfigType.
+typedef struct {
+ // Address offset in RAM to which the erase flash access code shall be
+ // loaded. Used as function pointer to access the erase flash access code.
+ void (*FlsAcErase)();
+
+ // Address offset in RAM to which the write flash access code shall be
+ // loaded. Used as function pointer to access the write flash access code.
+ void (*FlsAcWrite)();
+//#if 0
+// // Cycle time of calls of the flash driver's main function.
+// float FlsCallCycle;
+//#endif
+ // Mapped to the job end notification routine provided by some upper layer
+ // module, typically the Fee module.
+ void (*FlsJobEndNotification)();
+
+ // Mapped to the job error notification routine provided by some upper layer
+ // module, typically the Fee module.
+ void (*FlsJobErrorNotification)();
+
+ // The maximum number of bytes to read or compare in one cycle of the
+ // flash driver's job processing function in fast mode.
+ uint32 FlsMaxReadFastMode;
+
+ // The maximum number of bytes to read or compare in one cycle of the
+ // flash driver's job processing function in normal mode.
+ uint32 FlsMaxReadNormalMode;
+
+ // The maximum number of bytes to write in one cycle of the flash driver's job
+ // processing function in fast mode.
+ uint32 FlsMaxWriteFastMode;
+
+ // The maximum number of bytes to write in one cycle of the flash driver's job
+ // processing function in normal mode.
+ uint32 FlsMaxWriteNormalMode;
+
+ // Erase/write protection settings. Only relevant if supported by hardware.
+ uint32 FlsProtection;
+
+ // List of flash:able sectors and pages
+ const Fls_SectorType *FlsSectorList;
+
+ // Size of List of the FlsSectorList
+ const uint32 FlsSectorListSize;
+
+ uint8 *FlsBlockToPartitionMap;
+
+
+} Fls_ConfigType;
+
+
+extern const Fls_ConfigType FlsConfigSet[];
+
+#if 0
+/* N/A since PPC have PIC */
+#define FLS_AC_LOCATION_ERASE
+#define FLS_AC_LOCATION_WRITE
+/* N/A since we have internal flash */
+#define FLS_EXPECTED_HW_ID
+#endif
+
+#define FLS_AC_SIZE_ERASE (__FLS_WRITE_ROM__ - __FLS_ERASE_ROM__)
+#define FLS_AC_SIZE_WRITE (__FLS_END_ROM__ - __FLS_ERASE_ROM__)
+#define FLS_ERASED_VALUE 0xff
+
+#define FLS_SPECIFIED_ERASE_CYCLES 0 /* TODO */
+#define FLS_WRITE_TIME 0 /* TODO */
+
+
+#endif /*FLS_CFG_H_*/
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include "Fls.h"\r
+#include <stdlib.h>\r
+\r
+\r
+#define KB *1024\r
+\r
+\r
+const Fls_SectorType fls_SST25xx_SectorList[] = {\r
+ { // L0->L7\r
+ .FlsSectorStartaddress = (Fls_AddressType)0x00000000, // Start address of this sector\r
+ .FlsPageSize = (Fls_LengthType)1, // Read page size of 128 bits (4 words), (8 bytes)\r
+ .FlsSectorSize = (Fls_LengthType)(4 KB), // 16Kbyte\r
+ // Number of continuous sectors with the above characteristics.\r
+ .FlsNumberOfSectors = (uint32)512,// L0->L7 , 8 sectors\r
+ },\r
+};\r
+\r
+// Partitions start at 1\r
+// uint8 Fls_BlockToPartitionMap[] = { 1,1,1,1,2,2,2,2,3,3,4,4,5,5,6,6,7,7,8,8 };\r
+\r
+const Fls_ConfigType FlsSST25xxConfigSet[]=\r
+{\r
+ {\r
+#if 0\r
+#if ( FLS_AC_LOAD_ON_JOB_START == STD_ON)\r
+ .FlsAcWrite = __FLS_ERASE_RAM__,\r
+ .FlsAcErase = __FLS_WRITE_RAM__,\r
+#else\r
+ .FlsAcWrite = NULL,\r
+ .FlsAcErase = NULL,\r
+#endif\r
+#endif\r
+ .FlsMaxReadFastMode = 64,\r
+ .FlsMaxReadNormalMode = 1,\r
+ .FlsMaxWriteFastMode = 1,\r
+ .FlsMaxWriteNormalMode = 1,\r
+\r
+ .FlsJobEndNotification = NULL,\r
+ .FlsJobErrorNotification = NULL,\r
+\r
+ .FlsSectorList = &fls_SST25xx_SectorList[0],\r
+ .FlsSectorListSize = sizeof(fls_SST25xx_SectorList)/sizeof(Fls_SectorType),\r
+#if 0\r
+ .FlsBlockToPartitionMap = Fls_BlockToPartitionMap,\r
+#endif\r
+ }\r
+};\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+#ifndef FLS_SST25XX_CFG_H_\r
+#define FLS_SST25XX_CFG_H_\r
+\r
+// Take in the original types\r
+\r
+\r
+#include "Fls_Cfg.h"\r
+\r
+\r
+extern const Fls_ConfigType FlsSST25xxConfigSet[];\r
+/*\r
+ * Fls General container\r
+ */\r
+\r
+// The flash driver shall load the flash access code to RAM whenever an\r
+// erase or write job is started and unload (overwrite) it after that job has\r
+// been finished or canceled. true: Flash access code loaded on job start /\r
+// unloaded on job end or error. false: Flash access code not loaded to /\r
+// unloaded from RAM at all.\r
+#define FLS_SST25XX_AC_LOAD_ON_JOB_START STD_OFF\r
+\r
+// The flash memory start address (see also FLS118).\r
+// FLS169: This parameter defines the lower boundary for read / write /\r
+// erase and compare jobs.\r
+#define FLS_SST25XX_BASE_ADDRESS 0x00000000\r
+\r
+// Compile switch to enable and disable the Fls_Cancel function. true: API\r
+// supported / function provided. false: API not supported / function not pro-\r
+// vided\r
+#define FLS_SST25XX_CANCEL_API STD_OFF\r
+\r
+// Compile switch to enable and disable the Fls_Compare function. true: API\r
+// supported / function provided. false: API not supported / function not pro-\r
+// vided\r
+#define FLS_SST25XX_COMPARE_API STD_ON\r
+\r
+// Pre-processor switch for enabling the development error detection and\r
+// reporting (see FLS077).\r
+\r
+#define FLS_SST25XX_DEV_ERROR_DETECT STD_ON\r
+\r
+// Index of the driver, used by FEE.\r
+#define FLS_SST25XX_DRIVER_INDEX 100\r
+\r
+// Compile switch to enable and disable the Fls_GetJobResult function. true:\r
+// API supported / function provided. false: API not supported / function not\r
+// provided\r
+#define FLS_SST25XX_GET_JOB_RESULT_API STD_OFF\r
+\r
+// Compile switch to enable and disable the Fls_GetStatus function. true: API\r
+// supported / function provided. false: API not supported / function not pro-\r
+// vided\r
+#define FLS_SST25XX_GET_STATUS_API STD_ON\r
+\r
+// Compile switch to enable and disable the Fls_SetMode function. true: API\r
+// supported / function provided. false: API not supported / function not pro-\r
+// vided\r
+#define FLS_SST25XX_SET_MODE_API STD_ON\r
+\r
+// The total amount of flash memory in bytes (see also FLS118).\r
+// FLS170: This parameter in conjunction with FLS_SST25XX_BASE_ADDRESS\r
+// defines the upper boundary for read / write / erase and compare jobs\r
+#define FLS_SST25XX_TOTAL_SIZE 0x200000 // 16Mbit->2Mb, 0x0000_0000 to 0x0020_0000\r
+#if 0\r
+#define FLS_SST25XX_READ_PAGE_SIZE 0x8 // Read page size of 128 bits (4 words) (8 bytes)\r
+#endif\r
+\r
+// Job processing triggered by hardware interrupt.\r
+// true: Job processing triggered by interrupt (hardware controlled).\r
+// false: Job processing not triggered by interrupt (software controlled)\r
+\r
+// NOT supported by Freescale hardware\r
+#define FLS_SST25XX_USE_INTERRUPTS STD_OFF\r
+\r
+#define FLS_SST25XX_VERSION_INFO_API STD_ON\r
+\r
+\r
+#endif /* FLS_SST25XX_CFG_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+#include "Gpt.h"\r
+#include "Gpt_Cfg.h"\r
+#include <stdlib.h>\r
+\r
+#if defined(USE_KERNEL)\r
+extern void OsTick( void );\r
+#endif\r
+\r
+const Gpt_ConfigType GptConfigData[] =\r
+{\r
+ {\r
+ .GptChannelId = GPT_CHANNEL_PIT_0,\r
+ .GptChannelMode = GPT_MODE_CONTINUOUS,\r
+ .GptChannelClkSrc = 0,\r
+ .GptNotification = NULL,\r
+ .GptChannelPrescale = 0,\r
+ .GptEnableWakeup = TRUE,\r
+ },{\r
+ .GptChannelId = GPT_CHANNEL_PIT_1,\r
+ .GptChannelMode = GPT_MODE_CONTINUOUS,\r
+ .GptChannelClkSrc = 0,\r
+ .GptNotification = NULL,\r
+ .GptChannelPrescale = 0,\r
+ .GptEnableWakeup = FALSE,\r
+ },{\r
+ .GptChannelId = GPT_CHANNEL_PIT_2,\r
+ .GptChannelMode = GPT_MODE_ONESHOT,\r
+ .GptChannelClkSrc = 0,\r
+ .GptNotification = NULL,\r
+ .GptChannelPrescale = 0,\r
+ .GptEnableWakeup = FALSE,\r
+ },{\r
+ .GptChannelId = GPT_CHANNEL_PIT_3,\r
+ .GptChannelMode = GPT_MODE_CONTINUOUS,\r
+ .GptChannelClkSrc = 0,\r
+ .GptNotification = NULL,\r
+ .GptChannelPrescale = 0,\r
+ .GptEnableWakeup = FALSE,\r
+ },{\r
+ .GptChannelId = GPT_CHANNEL_PIT_4,\r
+ .GptChannelMode = GPT_MODE_ONESHOT,\r
+ .GptChannelClkSrc = 0,\r
+ .GptNotification = NULL,\r
+ .GptChannelPrescale = 0,\r
+ .GptEnableWakeup = FALSE,\r
+ },{\r
+ .GptChannelId = GPT_CHANNEL_PIT_5,\r
+ .GptChannelMode = GPT_MODE_CONTINUOUS,\r
+ .GptChannelClkSrc = 0,\r
+ .GptNotification = NULL,\r
+ .GptChannelPrescale = 0,\r
+ .GptEnableWakeup = FALSE,\r
+ },{\r
+ .GptChannelId = GPT_CHANNEL_PIT_6,\r
+ .GptChannelMode = GPT_MODE_ONESHOT,\r
+ .GptChannelClkSrc = 0,\r
+ .GptNotification = NULL,\r
+ .GptChannelPrescale = 0,\r
+ .GptEnableWakeup = FALSE,\r
+ },{\r
+ .GptChannelId = GPT_CHANNEL_PIT_7,\r
+ .GptChannelMode = GPT_MODE_CONTINUOUS,\r
+ .GptChannelClkSrc = 0,\r
+ .GptNotification = NULL,\r
+ .GptChannelPrescale = 0,\r
+ .GptEnableWakeup = FALSE,\r
+ },{\r
+ .GptChannelId = GPT_CHANNEL_PIT_8,\r
+ .GptChannelMode = GPT_MODE_ONESHOT,\r
+ .GptChannelClkSrc = 0,\r
+ .GptNotification = NULL,\r
+ .GptChannelPrescale = 0,\r
+ .GptEnableWakeup = FALSE,\r
+ },{\r
+ .GptChannelId = GPT_CHANNEL_DEC,\r
+ .GptChannelMode = GPT_MODE_CONTINUOUS,\r
+ .GptChannelClkSrc = 0,\r
+#if defined(USE_KERNEL)\r
+ .GptNotification = OsTick,\r
+#else\r
+ .GptNotification = NULL,\r
+#endif\r
+ .GptEnableWakeup = FALSE,\r
+ .GptChannelPrescale = 0,\r
+ },{\r
+ // Last channel in list\r
+ .GptChannelId = GPT_CHANNEL_ILL,\r
+ }\r
+};\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef GPT_CFG_H_\r
+#define GPT_CFG_H_\r
+#include "Std_Types.h"\r
+\r
+\r
+// Pre-compile only\r
+#define GPT_VARIANT_PC STD_OFF\r
+// Mix of pre-compile and post-build\r
+#define GPT_VARIANT_PB STD_ON\r
+\r
+//#define DEC_TEST\r
+//#define GPT_TEST\r
+\r
+/* Std PIT channels */\r
+#define GPT_CHANNEL_RTI 0\r
+#define GPT_CHANNEL_PIT_0 GPT_CHANNEL_RTI\r
+#define GPT_CHANNEL_PIT_1 1\r
+#define GPT_CHANNEL_PIT_2 2\r
+#define GPT_CHANNEL_PIT_3 3\r
+#define GPT_CHANNEL_PIT_4 4\r
+#define GPT_CHANNEL_PIT_5 5\r
+#define GPT_CHANNEL_PIT_6 6\r
+#define GPT_CHANNEL_PIT_7 7\r
+#define GPT_CHANNEL_PIT_8 8\r
+\r
+#define GPT_PIT_CNT (GPT_CHANNEL_PIT_8 + 1)\r
+\r
+/* Mcu channels */\r
+#define GPT_CHANNEL_DEC 9\r
+\r
+#define GPT_CHANNEL_CNT (GPT_CHANNEL_DEC+1)\r
+\r
+// Illegal channel\r
+#define GPT_CHANNEL_ILL 31\r
+\r
+\r
+#define GPT_DEV_ERROR_DETECT STD_ON\r
+// Enables/Disables wakeup source reporting\r
+#define GPT_REPORT_WAKEUP_SOURCE STD_OFF\r
+\r
+#define GPT_DEINIT_API STD_ON\r
+#define GPT_ENABLE_DISABLE_NOTIFICATION_API STD_ON\r
+#define GPT_TIME_REMAINING_API STD_ON\r
+#define GPT_TIME_ELAPSED_API STD_ON\r
+#define GPT_VERSION_INFO_API STD_ON\r
+// TODO: EcuM things missing to get this API working properly\r
+#define GPT_WAKEUP_FUNCTIONALITY_API STD_OFF\r
+\r
+\r
+// This container contains the channel-wide configuration (parameters) of the\r
+// GPT Driver\r
+typedef struct {\r
+ // GPT187: The GPT module specific clock input for the timer unit can\r
+ // statically be configured and allows to select different clock sources\r
+ // (external clock, internal GPT specific clock) per channel\r
+ uint32 GptChannelClkSrc;\r
+\r
+ // Channel Id of the GPT channel. This value will be assigned to the symbolic\r
+ // name derived of the GptChannelConfiguration container short name.\r
+ Gpt_ChannelType GptChannelId;\r
+\r
+ // Specifies the behaviour of the timerchannel after the timeout has expired\r
+ Gpt_ChannelMode GptChannelMode;\r
+\r
+ // Function pointer to callback function\r
+ void (*GptNotification)();\r
+\r
+ // GPT module specific prescaler factor per channel\r
+ uint32 GptChannelPrescale;\r
+\r
+ // GPT188: Enables wakeup capability of CPU for a channel when timeout\r
+ // period expires. This might be different to enabling the notification\r
+ // depending on hardware capabilities\r
+ boolean GptEnableWakeup;\r
+} Gpt_ConfigType;\r
+\r
+extern const Gpt_ConfigType GptConfigData[];\r
+\r
+#endif /*GPT_CFG_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef LINIF_CFG_H_\r
+#define LINIF_CFG_H_\r
+\r
+#include "Std_Types.h"\r
+#include "Lin_Cfg.h"\r
+\r
+// PDU definitions\r
+enum {\r
+ PDU_MSG_LIN_TX_1 = 0, // Changed by Mattias original value 101\r
+ PDU_MSG_LIN_RX_1,\r
+ PDU_MSG_LIN_RX_2,\r
+};\r
+\r
+/* Switches the Development Error Detection and Notification\r
+ON or OFF. */\r
+#define LINIF_DEV_ERROR_DETECT STD_ON\r
+\r
+/* States if multiple drivers are included in the LIN Interface or not. The\r
+ * reason for this parameter is to reduce the size of LIN Interface if multiple\r
+ * drivers are not used. */\r
+#define LINIF_MULTIPLE_DRIVER_SUPPORT STD_OFF\r
+\r
+/* States if the node configuration commands Assign NAD and Conditional\r
+ * Change NAD are supported. */\r
+#define LINIF_OPTIONAL_REQUEST_SUPPORTED STD_OFF\r
+\r
+/* States if the TP is included in the LIN Interface or not. The reason for this\r
+ * parameter is to reduce the size of LIN Interface if the TP is not used. */\r
+#define LINIF_TP_SUPPORTED STD_OFF\r
+\r
+/* Switches the LinIf_GetVersionInfo function ON or OFF. */\r
+#define LINIF_VERSION_INFO_API STD_ON\r
+\r
+typedef struct {\r
+ /* Switches the Development Error Detection and Notification\r
+ ON or OFF. */\r
+ boolean LinIfDevErrorDetect;\r
+ /* States if multiple drivers are included in the LIN Interface or not. The\r
+ * reason for this parameter is to reduce the size of LIN Interface if multiple\r
+ * drivers are not used. */\r
+ boolean LinIfMultipleDriversSupported;\r
+ /* States if the node configuration commands Assign NAD and Conditional\r
+ * Change NAD are supported. */\r
+ boolean LinIfNcOptionalRequestSupported;\r
+ /* States if the TP is included in the LIN Interface or not. The reason for this\r
+ * parameter is to reduce the size of LIN Interface if the TP is not used. */\r
+ boolean LinIfTpSupported;\r
+ /* Switches the LinIf_GetVersionInfo function ON or OFF. */\r
+ boolean LinIfVersionInfoApi;\r
+}LinIf_GeneralType;\r
+\r
+typedef enum {\r
+ CLASSIC,\r
+ ENHANCED,\r
+}LinIf_ChecksumType;\r
+\r
+typedef enum {\r
+ ASSIGN,\r
+ ASSIGN_NAD,\r
+ CONDITIONAL,\r
+ EVENT_TRIGGERED,\r
+ FREE,\r
+ MRF,\r
+ SPORADIC,\r
+ SRF,\r
+ UNASSIGN,\r
+ UNCONDITIONAL,\r
+}LinIf_FrameTypeType;\r
+\r
+typedef enum\r
+{\r
+ LinIfInternalPdu,\r
+ LinIfRxPdu,\r
+ LinIfSlaveToSlavePdu,\r
+ LinIfTxPdu,\r
+}LinIf_PduDirectionType;\r
+\r
+typedef struct {\r
+ LinIf_ChecksumType LinIfChecksumType;\r
+ char* LinIfFrameName;\r
+ uint8 LinIfFramePriority;\r
+ LinIf_FrameTypeType LinIfFrameType;\r
+ uint8 LinIfLength;\r
+ uint8 LinIfPid;\r
+ uint8 LinIfTxTargetPduId;\r
+ uint8 *LinIfFixedFrameSdu;\r
+ LinIf_PduDirectionType LinIfPduDirection;\r
+ //LinIf_SubstitutionFramesType *LinIfSubstitutionFrames;\r
+} LinIf_FrameType;\r
+\r
+typedef struct {\r
+ uint32 LinIfJitter;\r
+}LinIf_MasterType;\r
+\r
+typedef struct {\r
+ uint32 LinIfConfiguredNad;\r
+ uint32 LinIfFunctionId;\r
+ char* LinIfProtocolVersion;\r
+ uint32 LinIfResponseErrorBitPos;\r
+ uint32 LinIfSupplierId;\r
+ uint32 LinIfVariant;\r
+ uint32 LinIfResponseErrorEventRef;\r
+ uint16 LinIfResponseErrorFrameRef;\r
+}LinIf_SlaveType;\r
+\r
+typedef enum {\r
+ CONTINUE_AT_IT_POINT,\r
+ START_FROM_BEGINNING,\r
+}LinIf_ResumePositionType;\r
+\r
+typedef enum {\r
+ RUN_CONTINUOUS,\r
+ RUN_ONCE,\r
+}LinIfRunModeType;\r
+\r
+typedef struct {\r
+ uint16 LinIfDelay;\r
+ uint16 LinIfEntryIndex;\r
+ uint16 LinIfCollisionResolvingRef;\r
+ uint16 LinIfFrameRef;\r
+}LinIfEntryType;\r
+\r
+typedef struct {\r
+ LinIf_ResumePositionType LinIfResumePosition;\r
+ LinIfRunModeType LinIfRunMode;\r
+ uint8 LinIfSchedulePriority;\r
+ uint16 LinIfScheduleTableIndex;\r
+ char* LinIfScheduleTableName;\r
+ const LinIfEntryType *LinIfEntry;\r
+ uint16 LinIfNofEntries;\r
+}LinIf_ScheduleTableType;\r
+\r
+typedef uint8 LinIf_WakeUpSourceType;\r
+\r
+typedef char* LinIf_NodeComposition;\r
+\r
+typedef struct {\r
+ /* Internal ID for the channel on LIN Interface level. This parameter shall map\r
+ * the NetworkHandleType to the physical LIN channel.\r
+ * Implementation Type: NetworkHandleType */\r
+ uint8 LinIfChannelId;\r
+ /* Number of schedule requests the schedule table manager can handle for\r
+ * this channel. */\r
+ uint8 LinIfScheduleRequestQueueLength;\r
+ /* Reference to the used channel in Lin. Replaces LINIF_CHANNEL_INDEX */\r
+ const Lin_ChannelConfigType *LinIfChannelRef;\r
+\r
+ /* Generic container for all types of LIN frames. */\r
+ const LinIf_FrameType *LinIfFrame;\r
+ /* Each Master can only be connected to one physical channel.\r
+ * This could be compared to the Node parameter in a LDF file. */\r
+ LinIf_MasterType LinIfMaster;\r
+ /* Describes a schedule table. Each LinIfChannel may have several schedule tables.\r
+ * Each schedule table can only be connected to one channel. */\r
+ const LinIf_ScheduleTableType *LinIfScheduleTable;\r
+ /* The Node attributes of the Slaves are provided with these parameter. */\r
+ const LinIf_SlaveType *LinIfSlave;\r
+ /* This container contains the configuration (parameters) needed\r
+ to configure a wakeup capable channel */\r
+ const LinIf_WakeUpSourceType *LinIfWakeUpSource;\r
+} LinIf_ChannelType;\r
+\r
+typedef struct {\r
+ uint16 LinIfTimeBase;\r
+ const LinIf_ChannelType *LinIfChannel;\r
+}LinIf_GlobalConfigType;\r
+\r
+typedef struct {\r
+ const LinIf_GeneralType *LinIfGeneral;\r
+ const LinIf_GlobalConfigType *LinIfGlobalConfig;\r
+} LinIf_Type;\r
+\r
+extern const LinIfEntryType LinIfEntryCfg1[];\r
+extern const LinIf_ScheduleTableType LinIfScheduleTableCfg[];\r
+extern const LinIf_ChannelType LinIfChannelCfg[];\r
+extern const LinIf_GlobalConfigType LinIfGlobalConfig;\r
+\r
+// TODO not in Lin if spec\r
+extern const LinIf_FrameType LinIfFrameCfg[];\r
+\r
+#define LINIF_CONTROLLER_CNT 1\r
+#define LINIF_SCH_CNT 2\r
+\r
+#endif /*LINIF_CFG_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include "LinIf_Cfg.h"\r
+#include "Lin_Cfg.h"\r
+\r
+extern const Lin_ChannelConfigType LinChannelConfigData[];\r
+\r
+// Frames config\r
+const LinIf_FrameType LinIfFrameCfg[] = {\r
+ {\r
+ .LinIfChecksumType = ENHANCED,\r
+ .LinIfFramePriority = 0,//not used\r
+ .LinIfFrameType = UNCONDITIONAL,\r
+ .LinIfLength = 2,\r
+ .LinIfPid = 0xC1,\r
+ .LinIfTxTargetPduId = PDU_MSG_LIN_TX_1,\r
+ .LinIfFixedFrameSdu = 0,\r
+ .LinIfPduDirection = LinIfTxPdu,\r
+ },\r
+ {\r
+ .LinIfChecksumType = ENHANCED,\r
+ .LinIfFramePriority = 0,//not used\r
+ .LinIfFrameType = UNCONDITIONAL,\r
+ .LinIfLength = 3,\r
+ .LinIfPid = 0x42,\r
+ .LinIfTxTargetPduId = PDU_MSG_LIN_RX_1,\r
+ .LinIfFixedFrameSdu = 0,\r
+ .LinIfPduDirection = LinIfRxPdu,\r
+ },\r
+ {\r
+ .LinIfChecksumType = ENHANCED,\r
+ .LinIfFramePriority = 0,//not used\r
+ .LinIfFrameType = UNCONDITIONAL,\r
+ .LinIfLength = 6,\r
+ .LinIfPid = 0x03,\r
+ .LinIfTxTargetPduId = PDU_MSG_LIN_RX_2,\r
+ .LinIfFixedFrameSdu = 0,\r
+ .LinIfPduDirection = LinIfRxPdu,\r
+ },\r
+};\r
+\r
+// Schedule entry config.\r
+// Multiplicity 1..*\r
+const LinIfEntryType LinIfEntryCfg1[] = {\r
+ {\r
+ .LinIfDelay = 8,\r
+ .LinIfEntryIndex = 0,\r
+ .LinIfCollisionResolvingRef = 0,\r
+ .LinIfFrameRef = 0,\r
+ },\r
+ {\r
+ .LinIfDelay = 8,\r
+ .LinIfEntryIndex = 1,\r
+ .LinIfCollisionResolvingRef = 0,\r
+ .LinIfFrameRef = 1,\r
+ },\r
+ {\r
+ .LinIfDelay = 8,\r
+ .LinIfEntryIndex = 2,\r
+ .LinIfCollisionResolvingRef = 0,\r
+ .LinIfFrameRef = 2,\r
+ },\r
+ {\r
+ .LinIfDelay = 8,\r
+ .LinIfEntryIndex = 3,\r
+ .LinIfCollisionResolvingRef = 0,\r
+ .LinIfFrameRef = 1,\r
+ },\r
+};\r
+\r
+// Schedule table config.\r
+// Multiplicity 1..*\r
+const LinIf_ScheduleTableType LinIfScheduleTableCfg[] =\r
+{\r
+ {\r
+ .LinIfResumePosition = START_FROM_BEGINNING,\r
+ .LinIfRunMode = RUN_CONTINUOUS,\r
+ .LinIfSchedulePriority = 1,\r
+ .LinIfScheduleTableIndex = 0,\r
+ .LinIfScheduleTableName = "NULL_SCHEDULE", //Not used\r
+ .LinIfEntry = 0, // Null schedule\r
+ .LinIfNofEntries = 0,\r
+ },\r
+ {\r
+ .LinIfResumePosition = START_FROM_BEGINNING,\r
+ .LinIfRunMode = RUN_CONTINUOUS,\r
+ .LinIfSchedulePriority = 1,\r
+ .LinIfScheduleTableIndex = 1,\r
+ .LinIfScheduleTableName = "NORMAL", //Not used\r
+ .LinIfEntry = &LinIfEntryCfg1[0],\r
+ .LinIfNofEntries = 4,\r
+ },\r
+};\r
+\r
+// Channel config.\r
+// Multiplicity 1..*\r
+const LinIf_ChannelType LinIfChannelCfg[] =\r
+{\r
+ {\r
+ .LinIfChannelId = LIN_CTRL_B, // Should map against driver\r
+ .LinIfScheduleRequestQueueLength = 1,\r
+ .LinIfChannelRef = &LinChannelConfigData[0],\r
+ .LinIfFrame = 0, // TODO ???????\r
+ .LinIfMaster.LinIfJitter = 1,\r
+ .LinIfScheduleTable = &LinIfScheduleTableCfg[0],\r
+ .LinIfSlave = 0, // Master only\r
+ .LinIfWakeUpSource = 0, // Not needed\r
+ },\r
+};\r
+\r
+// Global config.\r
+const LinIf_GlobalConfigType LinIfGlobalConfig =\r
+{\r
+ .LinIfTimeBase = 8,\r
+ .LinIfChannel = &LinIfChannelCfg[0],\r
+};\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef LINSM_CFG_H_\r
+#define LINSM_CFG_H_\r
+\r
+#include "Std_Types.h"\r
+#include "LinIf_Cfg.h"\r
+\r
+// Own timeout configs in ticks\r
+#define LINSM_SCHEDULE_REQUEST_TIMEOUT 1\r
+#define LINSM_GOTO_SLEEP_TIMEOUT 2\r
+#define LINSM_WAKEUP_TIMEOUT 1\r
+\r
+/* Switches the Development Error Detection and Notification\r
+ON or OFF. */\r
+#define LINSM_DEV_ERROR_DETECT STD_ON\r
+\r
+/* Switches the LINSM_GetVersionInfo function ON or OFF. */\r
+#define LINSM_VERSION_INFO_API STD_ON\r
+\r
+typedef struct {\r
+ uint32 LinSMRxPduGroupRef;//ComIPduGroup\r
+ uint32 LinSMTxPduGroupRef;\r
+ const LinIf_ScheduleTableType *LinSMScheduleIndexRef;\r
+}LinSM_ScheduleType;\r
+\r
+typedef struct {\r
+ float LinSMConfirmationTimeout;\r
+ boolean LinSMSleepSupport;\r
+ uint16 LinSMChannelIndex;\r
+ const LinSM_ScheduleType *LinSMSchedule;\r
+}LinSM_ChannelType;\r
+\r
+extern const LinSM_ChannelType LinSMChannelType[];\r
+\r
+#endif /*LINSM_CFG_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include "LinSM_Cfg.h"\r
+#include "LinIf_Cfg.h"\r
+#include "Lin_Cfg.h"\r
+\r
+const LinSM_ScheduleType LinSMScheduleType =\r
+{\r
+ .LinSMRxPduGroupRef = 0, // TODO ref till COM\r
+ .LinSMTxPduGroupRef = 0, // TODO ref till COM\r
+ .LinSMScheduleIndexRef = &LinIfScheduleTableCfg[0],\r
+};\r
+\r
+const LinSM_ChannelType LinSMChannelType[] =\r
+{\r
+ {\r
+ .LinSMConfirmationTimeout = 20.0,\r
+ .LinSMSleepSupport = TRUE,\r
+ .LinSMChannelIndex = LIN_CTRL_B,\r
+ .LinSMSchedule = &LinSMScheduleType,\r
+ },\r
+};\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef LIN_CFG_H_\r
+#define LIN_CFG_H_\r
+\r
+#include "Std_Types.h"\r
+\r
+/* Switches the Development Error Detection and Notification\r
+ON or OFF. */\r
+#define LIN_DEV_ERROR_DETECT STD_ON\r
+\r
+/* Specifies the InstanceId of this module instance. If only one\r
+instance is present it shall have the Id 0. */\r
+#define LIN_INDEX 0\r
+\r
+/* Specifies the maximum number of loops for blocking function\r
+ * until a timeout is raised in short term wait loops */\r
+#define LIN_TIMEOUT_DURATION 10\r
+\r
+/* Switches the Lin_GetVersionInfo function ON or OFF. */\r
+#define LIN_VERSION_INFO_API STD_ON\r
+\r
+typedef enum {\r
+ LIN_CTRL_A = 0,\r
+ LIN_CTRL_B,\r
+ LIN_CTRL_C,\r
+ LIN_CTRL_D,\r
+ LIN_CTRL_E,\r
+ LIN_CTRL_F,\r
+ LIN_CTRL_G,\r
+ LIN_CTRL_H,\r
+ LIN_CONTROLLER_CNT\r
+}LinControllerIdType;\r
+\r
+typedef struct {\r
+ /* Switches the Development Error Detection and Notification\r
+ ON or OFF. */\r
+ boolean LinDevErrorDetect;\r
+ /* Specifies the InstanceId of this module instance. If only one\r
+ instance is present it shall have the Id 0. */\r
+ uint8 LinIndex;\r
+ /* Specifies the maximum number of loops for blocking function\r
+ * until a timeout is raised in short term wait loops */\r
+ uint16 LinTimeoutDuration;\r
+ /* Switches the Lin_GetVersionInfo function ON or OFF. */\r
+ boolean LinVersionInfoApi;\r
+}Lin_GeneralType;\r
+\r
+typedef struct {\r
+ /* Specifies the baud rate of the LIN channel */\r
+ uint16 LinChannelBaudRate;\r
+ /* Identifies the LIN channel.*/\r
+ uint8 LinChannelId;\r
+ /* Specifies if the LIN hardware channel supports wake up functionality */\r
+ boolean LinChannelWakeUpSupport;\r
+ /* This parameter contains a reference to the Wakeup Source\r
+ * for this controller as defined in the ECU State Manager.\r
+ * Implementation Type: reference to EcuM_WakeupSourceType */\r
+ uint32 LinChannelEcuMWakeUpSource;\r
+ /* Reference to the LIN clock source configuration, which is set\r
+ * in the MCU driver configuration.*/\r
+ uint32 LinClockRef;\r
+} Lin_ChannelConfigType;\r
+\r
+\r
+#endif /*LIN_CFG_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include "Mcu_Cfg.h"\r
+#include "Lin_Cfg.h"\r
+\r
+const Lin_ChannelConfigType LinChannelConfigData[] = {\r
+ {\r
+ .LinChannelBaudRate = 19200,\r
+ .LinChannelId = LIN_CTRL_B,\r
+ .LinChannelWakeUpSupport = TRUE,\r
+ .LinChannelEcuMWakeUpSource = 0, //not used\r
+ .LinClockRef = PERIPHERAL_CLOCK_ESCI_B,\r
+ },\r
+};\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include "Lin_Cfg.h"\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef MCU_CFG_C_\r
+#define MCU_CFG_C_\r
+\r
+#include "Mcu_Cfg.h"\r
+\r
+Mcu_RamSectorSettingConfigType Mcu_RamSectorSettingConfigData[] = {\r
+ {\r
+ // This parameter shall represent the Data pre-setting to be initialized\r
+ .McuRamDefaultValue = 0,\r
+\r
+ // This parameter shall represent the MCU RAM section base address\r
+ .McuRamSectionBaseAddress = 0,\r
+\r
+ // This parameter shall represent the MCU RAM Section size\r
+ .McuRamSectionSize = 0xFF,\r
+ }\r
+};\r
+\r
+Mcu_ClockSettingConfigType Mcu_ClockSettingConfigData[] =\r
+{\r
+ {\r
+ .McuClockReferencePoint = 16000000UL,\r
+ .PllEprediv = 2,\r
+ .PllEmfd = 11,\r
+ .PllErfd = 0,\r
+ },\r
+};\r
+\r
+\r
+ const Mcu_ConfigType McuConfigData[] = {\r
+ {\r
+ // Enables/Disables clock failure notification. In case this feature is not supported\r
+ // by HW the setting should be disabled.\r
+ .McuClockSrcFailureNotification = 0,\r
+\r
+ // This parameter shall represent the number of Modes available for the\r
+ // MCU. calculationFormula = Number of configured McuModeSettingConf\r
+ .McuNumberOfMcuModes = 1, /* NOT USED */\r
+\r
+ // This parameter shall represent the number of RAM sectors available for\r
+ // the MCU. calculationFormula = Number of configured McuRamSectorSet-\r
+ // tingConf\r
+ .McuRamSectors = 1,\r
+\r
+ // This parameter shall represent the number of clock setting available for\r
+ // the MCU.\r
+ .McuClockSettings = MCU_NBR_OF_CLOCKS,\r
+\r
+ // Default clock frequency used\r
+ .McuDefaultClockSettings = MCU_CLOCKTYPE_EXT_REF_80MHZ,\r
+\r
+ // This parameter relates to the MCU specific reset configuration. This ap-\r
+ // plies to the function Mcu_PerformReset, which performs a microcontroller\r
+ // reset using the hardware feature of the microcontroller.\r
+ .McuResetSetting = 0, /* NOT USED */\r
+\r
+ // This container contains the configuration (parameters) for the\r
+ // Clock settings of the MCU. Please see MCU031 for more in-\r
+ // formation on the MCU clock settings.\r
+ .McuClockSettingConfig = &Mcu_ClockSettingConfigData[0],\r
+\r
+ // This container contains the configuration (parameters) for the\r
+ // Mode setting of the MCU. Please see MCU035 for more infor-\r
+ // mation on the MCU mode settings.\r
+ .McuModeSettingConfig = 0,\r
+\r
+ // This container contains the configuration (parameters) for the\r
+ // RAM Sector setting. Please see MCU030 for more information\r
+ // on RAM sec-tor settings.\r
+ .McuRamSectorSettingConfig = &Mcu_RamSectorSettingConfigData[0],\r
+ },\r
+};\r
+\r
+#endif /*MCU_CFG_C_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef MCU_CFG_H_\r
+#define MCU_CFG_H_\r
+\r
+#include "mpc55xx.h"\r
+\r
+#define MCU_DEV_ERROR_DETECT STD_ON\r
+// Preprocessor switch to enable / disable the use of the function\r
+// Mcu_PerformReset()\r
+#define MCU_PERFORM_RESET_API STD_ON\r
+\r
+#define MCU_VERSION_INFO_API STD_ON\r
+\r
+#include "Std_Types.h"\r
+#include "Mcu_Cfg.h"\r
+\r
+/* FMPLL modes( atleast in 5553/5554 ) */\r
+\r
+typedef enum {\r
+ MCU_FMPLL_BYPASS = 0,\r
+ MCU_FMPLL_EXTERNAL_REF,\r
+ MCU_FMPLL_EXTERNAL_REF_NO_FM,\r
+ MCU_FMPLL_DUAL_CONTROLLER_MODE,\r
+} Mcu_FMPLLmode_t;\r
+\r
+typedef enum {\r
+ MCU_CLOCKTYPE_EXT_REF_80MHZ = 0,\r
+ MCU_NBR_OF_CLOCKS,\r
+ //MCU_CLOCKTYPE_EXTERNAL_REF,\r
+ //MCU_CLOCKTYPE_EXTERNAL_REF_NO_FM,\r
+ //MCU_CLOCKTYPE_DUAL_CONTROLLER_MODE,\r
+} Mcu_ClockType;\r
+\r
+//\r
+//typedef enum {\r
+// CPU_Z1=0,\r
+// CPU_Z0,\r
+//} Cpu_t;\r
+//\r
+//typedef enum\r
+//{\r
+// /* Software interrupts. */\r
+// INTC_SSCIR0_CLR0,\r
+// INTC_SSCIR0_CLR1,\r
+// INTC_SSCIR0_CLR2,\r
+// INTC_SSCIR0_CLR3,\r
+// INTC_SSCIR0_CLR4,\r
+// INTC_SSCIR0_CLR5,\r
+// INTC_SSCIR0_CLR6,\r
+// INTC_SSCIR0_CLR7,\r
+// MCM_MSWTIR_SWTIC,\r
+// MCM_ESR_COMB,\r
+// /* eDMA */\r
+// EDMA_ERRL_ERR31_0,\r
+// EDMA_INTL_INT0,\r
+// EDMA_INTL_INT1,\r
+// EDMA_INTL_INT2,\r
+// EDMA_INTL_INT3,\r
+// EDMA_INTL_INT4,\r
+// EDMA_INTL_INT5,\r
+// EDMA_INTL_INT6,\r
+// EDMA_INTL_INT7,\r
+// EDMA_INTL_INT8,\r
+// EDMA_INTL_INT9,\r
+// EDMA_INTL_INT10,\r
+// EDMA_INTL_INT11,\r
+// EDMA_INTL_INT12,\r
+// EDMA_INTL_INT13,\r
+// EDMA_INTL_INT14,\r
+// EDMA_INTL_INT15,\r
+// RESERVED0,\r
+// RESERVED1,\r
+// RESERVED2,\r
+// RESERVED3,\r
+// RESERVED4,\r
+// RESERVED5,\r
+// RESERVED6,\r
+// RESERVED7,\r
+// RESERVED8,\r
+// RESERVED9,\r
+// RESERVED10,\r
+// RESERVED11,\r
+// RESERVED12,\r
+// RESERVED13,\r
+// RESERVED14,\r
+// RESERVED15,\r
+// /* Semahpore's */\r
+// SEMAPHORE_INT0,\r
+// SEMAPHORE_INT1,\r
+// RESERVED16,\r
+// CRP_INTERRUPT,\r
+// LVI_INTERRUPT,\r
+// IIC_A_IBSR_IBIF,\r
+// RESERVED17,\r
+// PLL_SYNSR_LOCF,\r
+// PLL_SYNSR_LOLF,\r
+// SIU_OSR_OVER,\r
+// /* External interrupts */\r
+// SIU_EISR_EIF0,\r
+// SIU_EISR_EIF1,\r
+// SIU_EISR_EIF2,\r
+// SIU_EISR_EIF3,\r
+// SIU_EISR_EIF15_4,\r
+// /* eMIOS */\r
+// EMISOS200_FLAG_F0,\r
+// EMISOS200_FLAG_F1,\r
+// EMISOS200_FLAG_F2,\r
+// EMISOS200_FLAG_F3,\r
+// EMISOS200_FLAG_F4,\r
+// EMISOS200_FLAG_F5,\r
+// EMISOS200_FLAG_F6,\r
+// EMISOS200_FLAG_F7,\r
+// EMISOS200_FLAG_F8,\r
+// EMISOS200_FLAG_F9,\r
+// EMISOS200_FLAG_F10,\r
+// EMISOS200_FLAG_F11,\r
+// EMISOS200_FLAG_F12,\r
+// EMISOS200_FLAG_F13,\r
+// EMISOS200_FLAG_F14,\r
+// EMISOS200_FLAG_F15,\r
+// EMISOS200_FLAG_F16,\r
+// EMISOS200_FLAG_F17,\r
+// EMISOS200_FLAG_F18,\r
+// EMISOS200_FLAG_F19,\r
+// EMISOS200_FLAG_F20,\r
+// EMISOS200_FLAG_F21,\r
+// EMISOS200_FLAG_F22,\r
+// EMISOS200_FLAG_F23,\r
+// /* eQADC */\r
+// EQADC_FISR_OVER,\r
+// EQADC_FISR0_NCF0,\r
+// EQADC_FISR0_PF0,\r
+// EQADC_FISR0_EOQF0,\r
+// EQADC_FISR0_CFFF0,\r
+// EQADC_FISR0_RFDF0,\r
+// EQADC_FISR1_NCF1,\r
+// EQADC_FISR1_PF1,\r
+// EQADC_FISR1_EOQF1,\r
+// EQADC_FISR1_CFFF1,\r
+// EQADC_FISR1_RFDF1,\r
+// EQADC_FISR2_NCF2,\r
+// EQADC_FISR2_PF2,\r
+// EQADC_FISR2_EOQF2,\r
+// EQADC_FISR2_CFFF2,\r
+// EQADC_FISR2_RFDF2,\r
+// EQADC_FISR3_NCF3,\r
+// EQADC_FISR3_PF3,\r
+// EQADC_FISR3_EOQF3,\r
+// EQADC_FISR3_CFFF3,\r
+// EQADC_FISR3_RFDF3,\r
+// EQADC_FISR4_NCF4,\r
+// EQADC_FISR4_PF4,\r
+// EQADC_FISR4_EOQF4,\r
+// EQADC_FISR4_CFFF4,\r
+// EQADC_FISR4_RFDF4,\r
+// EQADC_FISR5_NCF5,\r
+// EQADC_FISR5_PF5,\r
+// EQADC_FISR5_EOQF5,\r
+// EQADC_FISR5_CFFF5,\r
+// EQADC_FISR5_RFDF5,\r
+// /* SCI */\r
+// SCI_A_COMB,\r
+// SCI_B_COMB,\r
+// SCI_C_COMB,\r
+// SCI_D_COMB,\r
+// /* DSPI A,B */\r
+// DSPI_A_ISR_OVER,\r
+// DSPI_A_ISR_EOQF,\r
+// DSPI_A_ISR_TFFF,\r
+// DSPI_A_ISR_TCF,\r
+// DSPI_A_ISR_RFDF,\r
+// DSPI_B_ISR_OVER,\r
+// DSPI_B_ISR_EOQF,\r
+// DSPI_B_ISR_TFFF,\r
+// DSPI_B_ISR_TCF,\r
+// DSPI_B_ISR_RFDF,\r
+// /* FlexCAN A */\r
+// FLEXCAN_A_ESR_BOFF_INT,\r
+// FLEXCAN_A_ESR_ERR_INT,\r
+// RESERVED18,\r
+// FLEXCAN_A_IFLAG1_BUF0I,\r
+// FLEXCAN_A_IFLAG1_BUF1I,\r
+// FLEXCAN_A_IFLAG1_BUF2I,\r
+// FLEXCAN_A_IFLAG1_BUF3I,\r
+// FLEXCAN_A_IFLAG1_BUF4I,\r
+// FLEXCAN_A_IFLAG1_BUF5I,\r
+// FLEXCAN_A_IFLAG1_BUF6I,\r
+// FLEXCAN_A_IFLAG1_BUF7I,\r
+// FLEXCAN_A_IFLAG1_BUF8I,\r
+// FLEXCAN_A_IFLAG1_BUF9I,\r
+// FLEXCAN_A_IFLAG1_BUF10I,\r
+// FLEXCAN_A_IFLAG1_BUF11I,\r
+// FLEXCAN_A_IFLAG1_BUF12I,\r
+// FLEXCAN_A_IFLAG1_BUF13I,\r
+// FLEXCAN_A_IFLAG1_BUF14I,\r
+// FLEXCAN_A_IFLAG1_BUF15I,\r
+// FLEXCAN_A_IFLAG1_BUF31_16I,\r
+// FLEXCAN_A_IFLAG1_BUF63_32I,\r
+// /* Periodic interrupt timer */\r
+// PIT_PITFLG_RTIF,\r
+// PIT_PITFLG_PIT1,\r
+// PIT_PITFLG_PIT2,\r
+// PIT_PITFLG_PIT3,\r
+// PIT_PITFLG_PIT4,\r
+// PIT_PITFLG_PIT5,\r
+// PIT_PITFLG_PIT6,\r
+// PIT_PITFLG_PIT7,\r
+// PIT_PITFLG_PIT8,\r
+// /* FlexCAN B */\r
+// FLEXCAN_B_ESR_BOFF_INT,\r
+// FLEXCAN_B_ESR_ERR_INT,\r
+// RESERVED19,\r
+// FLEXCAN_B_IFLAG1_BUF0I,\r
+// FLEXCAN_B_IFLAG1_BUF1I,\r
+// FLEXCAN_B_IFLAG1_BUF2I,\r
+// FLEXCAN_B_IFLAG1_BUF3I,\r
+// FLEXCAN_B_IFLAG1_BUF4I,\r
+// FLEXCAN_B_IFLAG1_BUF5I,\r
+// FLEXCAN_B_IFLAG1_BUF6I,\r
+// FLEXCAN_B_IFLAG1_BUF7I,\r
+// FLEXCAN_B_IFLAG1_BUF8I,\r
+// FLEXCAN_B_IFLAG1_BUF9I,\r
+// FLEXCAN_B_IFLAG1_BUF10I,\r
+// FLEXCAN_B_IFLAG1_BUF11I,\r
+// FLEXCAN_B_IFLAG1_BUF12I,\r
+// FLEXCAN_B_IFLAG1_BUF13I,\r
+// FLEXCAN_B_IFLAG1_BUF14I,\r
+// FLEXCAN_B_IFLAG1_BUF15I,\r
+// FLEXCAN_B_IFLAG1_BUF31_16I,\r
+// FLEXCAN_B_IFLAG1_BUF63_32I,\r
+// /* FlexCAN C */\r
+// FLEXCAN_C_ESR_BOFF_INT,\r
+// FLEXCAN_C_ESR_ERR_INT,\r
+// RESERVED20,\r
+// FLEXCAN_C_IFLAG1_BUF0I,\r
+// FLEXCAN_C_IFLAG1_BUF1I,\r
+// FLEXCAN_C_IFLAG1_BUF2I,\r
+// FLEXCAN_C_IFLAG1_BUF3I,\r
+// FLEXCAN_C_IFLAG1_BUF4I,\r
+// FLEXCAN_C_IFLAG1_BUF5I,\r
+// FLEXCAN_C_IFLAG1_BUF6I,\r
+// FLEXCAN_C_IFLAG1_BUF7I,\r
+// FLEXCAN_C_IFLAG1_BUF8I,\r
+// FLEXCAN_C_IFLAG1_BUF9I,\r
+// FLEXCAN_C_IFLAG1_BUF10I,\r
+// FLEXCAN_C_IFLAG1_BUF11I,\r
+// FLEXCAN_C_IFLAG1_BUF12I,\r
+// FLEXCAN_C_IFLAG1_BUF13I,\r
+// FLEXCAN_C_IFLAG1_BUF14I,\r
+// FLEXCAN_C_IFLAG1_BUF15I,\r
+// FLEXCAN_C_IFLAG1_BUF31_16I,\r
+// FLEXCAN_C_IFLAG1_BUF63_32I,\r
+// /* FlexCAN D */\r
+// FLEXCAN_D_ESR_BOFF_INT,\r
+// FLEXCAN_D_ESR_ERR_INT,\r
+// RESERVED21,\r
+// FLEXCAN_D_IFLAG1_BUF0I,\r
+// FLEXCAN_D_IFLAG1_BUF1I,\r
+// FLEXCAN_D_IFLAG1_BUF2I,\r
+// FLEXCAN_D_IFLAG1_BUF3I,\r
+// FLEXCAN_D_IFLAG1_BUF4I,\r
+// FLEXCAN_D_IFLAG1_BUF5I,\r
+// FLEXCAN_D_IFLAG1_BUF6I,\r
+// FLEXCAN_D_IFLAG1_BUF7I,\r
+// FLEXCAN_D_IFLAG1_BUF8I,\r
+// FLEXCAN_D_IFLAG1_BUF9I,\r
+// FLEXCAN_D_IFLAG1_BUF10I,\r
+// FLEXCAN_D_IFLAG1_BUF11I,\r
+// FLEXCAN_D_IFLAG1_BUF12I,\r
+// FLEXCAN_D_IFLAG1_BUF13I,\r
+// FLEXCAN_D_IFLAG1_BUF14I,\r
+// FLEXCAN_D_IFLAG1_BUF15I,\r
+// FLEXCAN_D_IFLAG1_BUF31_16I,\r
+// FLEXCAN_D_IFLAG1_BUF63_32I,\r
+// /* FlexCAN E */\r
+// FLEXCAN_E_ESR_BOFF_INT,\r
+// FLEXCAN_E_ESR_ERR_INT,\r
+// RESERVED22,\r
+// FLEXCAN_E_IFLAG1_BUF0I,\r
+// FLEXCAN_E_IFLAG1_BUF1I,\r
+// FLEXCAN_E_IFLAG1_BUF2I,\r
+// FLEXCAN_E_IFLAG1_BUF3I,\r
+// FLEXCAN_E_IFLAG1_BUF4I,\r
+// FLEXCAN_E_IFLAG1_BUF5I,\r
+// FLEXCAN_E_IFLAG1_BUF6I,\r
+// FLEXCAN_E_IFLAG1_BUF7I,\r
+// FLEXCAN_E_IFLAG1_BUF8I,\r
+// FLEXCAN_E_IFLAG1_BUF9I,\r
+// FLEXCAN_E_IFLAG1_BUF10I,\r
+// FLEXCAN_E_IFLAG1_BUF11I,\r
+// FLEXCAN_E_IFLAG1_BUF12I,\r
+// FLEXCAN_E_IFLAG1_BUF13I,\r
+// FLEXCAN_E_IFLAG1_BUF14I,\r
+// FLEXCAN_E_IFLAG1_BUF15I,\r
+// FLEXCAN_E_IFLAG1_BUF31_16I,\r
+// FLEXCAN_E_IFLAG1_BUF63_32I,\r
+// /* FlexCAN F */\r
+// FLEXCAN_F_ESR_BOFF_INT,\r
+// FLEXCAN_F_ESR_ERR_INT,\r
+// RESERVED23,\r
+// FLEXCAN_F_IFLAG1_BUF0I,\r
+// FLEXCAN_F_IFLAG1_BUF1I,\r
+// FLEXCAN_F_IFLAG1_BUF2I,\r
+// FLEXCAN_F_IFLAG1_BUF3I,\r
+// FLEXCAN_F_IFLAG1_BUF4I,\r
+// FLEXCAN_F_IFLAG1_BUF5I,\r
+// FLEXCAN_F_IFLAG1_BUF6I,\r
+// FLEXCAN_F_IFLAG1_BUF7I,\r
+// FLEXCAN_F_IFLAG1_BUF8I,\r
+// FLEXCAN_F_IFLAG1_BUF9I,\r
+// FLEXCAN_F_IFLAG1_BUF10I,\r
+// FLEXCAN_F_IFLAG1_BUF11I,\r
+// FLEXCAN_F_IFLAG1_BUF12I,\r
+// FLEXCAN_F_IFLAG1_BUF13I,\r
+// FLEXCAN_F_IFLAG1_BUF14I,\r
+// FLEXCAN_F_IFLAG1_BUF15I,\r
+// FLEXCAN_F_IFLAG1_BUF31_16I,\r
+// FLEXCAN_F_IFLAG1_BUF63_32I,\r
+// RESERVED24,\r
+// RESERVED25,\r
+// RESERVED26,\r
+// RESERVED27,\r
+// RESERVED28,\r
+// RESERVED29,\r
+// RESERVED30,\r
+// RESERVED31,\r
+// /* SCI */\r
+// SCI_E_COMB,\r
+// SCI_F_COMB,\r
+// SCI_G_COMB,\r
+// SCI_H_COMB,\r
+// /* DSPI */\r
+// DSPI_C_ISR_OVER,\r
+// DSPI_C_ISR_EOQF,\r
+// DSPI_C_ISR_TFFF,\r
+// DSPI_C_ISR_TCF,\r
+// DSPI_C_ISR_RFDF,\r
+// DSPI_D_ISR_OVER,\r
+// DSPI_D_ISR_EOQF,\r
+// DSPI_D_ISR_TFFF,\r
+// DSPI_D_ISR_TCF,\r
+// DSPI_D_ISR_RFDF,\r
+// /* Flexray */\r
+// FLEXRAY_GLOB,\r
+// FLEXRAY_PRIF,\r
+// FLEXRAY_CHIF,\r
+// FLEXRAY_WUP_IF,\r
+// FLEXRAY_FBNE_F,\r
+// FLEXRAY_FANE_F,\r
+// FLEXRAY_RBIF,\r
+// FLEXRAY_TBIF,\r
+// RESERVED32,\r
+// MLB_SERVICE_REQUEST,\r
+// INTC_NUMBER_OF_INTERRUPTS,\r
+// /* End of INTC interrupts. The vectors below are used to handle exceptions. */\r
+// RESERVED_SPACE_BEFORE_EXCEPTIONS1,\r
+// RESERVED_SPACE_BEFORE_EXCEPTIONS2,\r
+// RESERVED_SPACE_BEFORE_EXCEPTIONS3,\r
+// RESERVED_SPACE_BEFORE_EXCEPTIONS4,\r
+// RESERVED_SPACE_BEFORE_EXCEPTIONS5,\r
+// RESERVED_SPACE_BEFORE_EXCEPTIONS6,\r
+// RESERVED_SPACE_BEFORE_EXCEPTIONS7,\r
+// RESERVED_SPACE_BEFORE_EXCEPTIONS8,\r
+// RESERVED_SPACE_BEFORE_EXCEPTIONS9,\r
+// RESERVED_SPACE_BEFORE_EXCEPTIONS10,\r
+// RESERVED_SPACE_BEFORE_EXCEPTIONS11,\r
+// RESERVED_SPACE_BEFORE_EXCEPTIONS12,\r
+// RESERVED_SPACE_BEFORE_EXCEPTIONS13,\r
+// RESERVED_SPACE_BEFORE_EXCEPTIONS14,\r
+// RESERVED_SPACE_BEFORE_EXCEPTIONS15,\r
+// RESERVED_SPACE_BEFORE_EXCEPTIONS16,\r
+// RESERVED_SPACE_BEFORE_EXCEPTIONS17,\r
+// RESERVED_SPACE_BEFORE_EXCEPTIONS18,\r
+// RESERVED_SPACE_BEFORE_EXCEPTIONS19,\r
+// RESERVED_SPACE_BEFORE_EXCEPTIONS20,\r
+// RESERVED_SPACE_BEFORE_EXCEPTIONS21,\r
+// RESERVED_SPACE_BEFORE_EXCEPTIONS22,\r
+// RESERVED_SPACE_BEFORE_EXCEPTIONS23,\r
+// RESERVED_SPACE_BEFORE_EXCEPTIONS24,\r
+// RESERVED_SPACE_BEFORE_EXCEPTIONS25,\r
+// CRITICAL_INPUT_EXCEPTION,\r
+// MACHINE_CHECK_EXCEPTION,\r
+// DATA_STORAGE_EXCEPTION,\r
+// INSTRUCTION_STORAGE_EXCEPTION,\r
+// EXTERNAL_INTERRUPT, /* This is the place where the "normal" interrupts will hit the CPU... */\r
+// ALIGNMENT_EXCEPTION,\r
+// PROGRAM_EXCEPTION,\r
+// FLOATING_POINT_EXCEPTION,\r
+// SYSTEM_CALL_EXCEPTION,\r
+// AUX_EXCEPTION,\r
+// DECREMENTER_EXCEPTION,\r
+// FIXED_INTERVAL_TIMER_EXCEPTION,\r
+// WATCHDOG_TIMER_EXCEPTION,\r
+// DATA_TLB_EXCEPTION,\r
+// INSTRUCTION_TLB_EXCEPTION,\r
+// DEBUG_EXCEPTION,\r
+// NUMBER_OF_INTERRUPTS_AND_EXCEPTIONS,\r
+//}IrqType;\r
+//\r
+//typedef enum {\r
+// PERIPHERAL_CLOCK_FLEXCAN_A,\r
+// PERIPHERAL_CLOCK_FLEXCAN_B,\r
+// PERIPHERAL_CLOCK_FLEXCAN_C,\r
+// PERIPHERAL_CLOCK_FLEXCAN_D,\r
+// PERIPHERAL_CLOCK_FLEXCAN_E,\r
+// PERIPHERAL_CLOCK_FLEXCAN_F,\r
+// PERIPHERAL_CLOCK_PIT,\r
+// PERIPHERAL_CLOCK_DSPI_A,\r
+// PERIPHERAL_CLOCK_DSPI_B,\r
+// PERIPHERAL_CLOCK_DSPI_C,\r
+// PERIPHERAL_CLOCK_DSPI_D,\r
+// PERIPHERAL_CLOCK_EMIOS,\r
+// PERIPHERAL_CLOCK_ESCI_A,\r
+// PERIPHERAL_CLOCK_ESCI_B,\r
+// PERIPHERAL_CLOCK_ESCI_C,\r
+// PERIPHERAL_CLOCK_ESCI_D,\r
+// PERIPHERAL_CLOCK_ESCI_E,\r
+// PERIPHERAL_CLOCK_ESCI_F,\r
+// PERIPHERAL_CLOCK_ESCI_G,\r
+// PERIPHERAL_CLOCK_ESCI_H,\r
+// PERIPHERAL_CLOCK_IIC_A,\r
+// PERIPHERAL_CLOCK_MLB,\r
+//} McuE_PeriperalClock_t;\r
+\r
+\r
+typedef struct {\r
+ // This container defines a reference point in the Mcu Clock tree\r
+ // It defines the frequency which then can be used by other modules\r
+ // as an input value. Lower multiplicity is 1, as even in the\r
+ // simplest case (only one frequency is used), there is one\r
+ // frequency to be defined.\r
+ uint32 McuClockReferencePoint;\r
+\r
+ // Phase locked loop configuration parameters for MPC551x.\r
+ uint8 PllEprediv;\r
+ uint8 PllEmfd;\r
+ uint8 PllErfd;\r
+} Mcu_ClockSettingConfigType;\r
+\r
+typedef struct {\r
+ // The parameter represents the MCU Mode settings\r
+ uint32 McuMode;\r
+} Mcu_ModeSettingConfigType;\r
+\r
+typedef struct {\r
+ // This parameter shall represent the Data pre-setting to be initialized\r
+ uint32 McuRamDefaultValue;\r
+\r
+ // This parameter shall represent the MCU RAM section base address\r
+ uint32 McuRamSectionBaseAddress;\r
+\r
+ // This parameter shall represent the MCU RAM Section size\r
+ uint32 McuRamSectionSize;\r
+\r
+} Mcu_RamSectorSettingConfigType;\r
+\r
+\r
+// This container defines a reference point in the Mcu Clock tree. It defines\r
+// the frequency which then can be used by other modules as an input value.\r
+// Lower multiplicity is 1, as even in the simplest case (only one frequency is\r
+// used), there is one frequency to be defined.\r
+typedef struct {\r
+\r
+ // This is the frequency for the specific instance of the McuClockReference-\r
+ // Point container. It shall be givn in Hz.\r
+ uint32 McuClockReferencePointFrequency;\r
+\r
+} Mcu_ClockReferencePointType;\r
+\r
+typedef struct {\r
+ // Enables/Disables clock failure notification. In case this feature is not supported\r
+ // by HW the setting should be disabled.\r
+ uint8 McuClockSrcFailureNotification;\r
+\r
+ // This parameter shall represent the number of Modes available for the\r
+ // MCU. calculationFormula = Number of configured McuModeSettingConf\r
+ uint8 McuNumberOfMcuModes;\r
+\r
+ // This parameter shall represent the number of RAM sectors available for\r
+ // the MCU. calculationFormula = Number of configured McuRamSectorSet-\r
+ // tingConf\r
+ uint8 McuRamSectors;\r
+\r
+ // This parameter shall represent the number of clock setting available for\r
+ // the MCU.\r
+ uint8 McuClockSettings;\r
+\r
+ // This parameter defines the default clock settings that should be used\r
+ // It is an index into the McuClockSettingsConfig\r
+ Mcu_ClockType McuDefaultClockSettings;\r
+\r
+ // This parameter relates to the MCU specific reset configuration. This ap-\r
+ // plies to the function Mcu_PerformReset, which performs a microcontroller\r
+ // reset using the hardware feature of the microcontroller.\r
+ uint32 McuResetSetting;\r
+\r
+ // This container contains the configuration (parameters) for the\r
+ // Clock settings of the MCU. Please see MCU031 for more in-\r
+ // formation on the MCU clock settings.\r
+ Mcu_ClockSettingConfigType * McuClockSettingConfig;\r
+\r
+ // This container contains the configuration (parameters) for the\r
+ // Mode setting of the MCU. Please see MCU035 for more information\r
+ // on the MCU mode settings.\r
+ Mcu_ModeSettingConfigType *McuModeSettingConfig;\r
+\r
+ // This container contains the configuration (parameters) for the\r
+ // RAM Sector setting. Please see MCU030 for more information\r
+ // on RAM sec-tor settings.\r
+ Mcu_RamSectorSettingConfigType *McuRamSectorSettingConfig;\r
+\r
+} Mcu_ConfigType;\r
+\r
+extern const Mcu_ConfigType McuConfigData[];\r
+\r
+#define MCU_DEFAULT_CONFIG McuConfigData[0]\r
+\r
+#endif /*MCU_CFG_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef MEMIF_CFG_H_
+#define MEMIF_CFG_H_
+
+// TODO. include FEE and EA modules
+
+
+
+#endif /*MEMIF_CFG_H_*/
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#define PDUR_ZERO_COST_OPERATION\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*\r
+ * Port_Cfg.c\r
+ *\r
+ * Created on: 2009-jul-08\r
+ * Author: rosa\r
+ */\r
+\r
+#include "Port_Cfg.h"\r
+\r
+\r
+const uint16_t PortPadConfigData[] = {\r
+ PCR_RESET, // SIU_PCR0\r
+ PCR_RESET, // SIU_PCR1\r
+ PCR_RESET, // SIU_PCR2\r
+ PCR_RESET, // SIU_PCR3\r
+ PCR_RESET, // SIU_PCR4\r
+ PCR_RESET, // SIU_PCR5\r
+ PCR_RESET, // SIU_PCR6\r
+ PCR_RESET, // SIU_PCR7\r
+ PCR_RESET, // SIU_PCR8\r
+ PCR_RESET, // SIU_PCR9\r
+ PCR_RESET, // SIU_PCR10\r
+ PCR_RESET, // SIU_PCR11\r
+ PCR_RESET, // SIU_PCR12\r
+ PCR_RESET, // SIU_PCR13\r
+ PCR_RESET, // SIU_PCR14\r
+ PCR_RESET, // SIU_PCR15\r
+ PCR_RESET, // SIU_PCR16\r
+ PCR_RESET, // SIU_PCR17\r
+ PCR_RESET, // SIU_PCR18\r
+ PCR_RESET, // SIU_PCR19\r
+ PCR_RESET, // SIU_PCR20\r
+ PCR_RESET, // SIU_PCR21\r
+ PCR_RESET, // SIU_PCR22\r
+ PCR_RESET, // SIU_PCR23\r
+ PCR_RESET, // SIU_PCR24\r
+ PCR_RESET, // SIU_PCR25\r
+ PCR_RESET, // SIU_PCR26\r
+ PCR_RESET, // SIU_PCR27\r
+ PCR_RESET, // SIU_PCR28\r
+ PCR_RESET, // SIU_PCR29\r
+ PCR_RESET, // SIU_PCR30\r
+ PCR_RESET, // SIU_PCR31\r
+ PCR_RESET, // SIU_PCR32\r
+ PCR_RESET, // SIU_PCR33\r
+ PCR_RESET, // SIU_PCR34\r
+ PCR_RESET, // SIU_PCR35\r
+ PCR_RESET, // SIU_PCR36\r
+ PCR_RESET, // SIU_PCR37\r
+ PCR_RESET, // SIU_PCR38\r
+ PCR_RESET, // SIU_PCR39\r
+ PCR_RESET, // SIU_PCR40\r
+ PCR_RESET, // SIU_PCR41\r
+ PCR_RESET, // SIU_PCR42\r
+ PCR_RESET, // SIU_PCR43\r
+ PCR_RESET, // SIU_PCR44\r
+ PCR_RESET, // SIU_PCR45\r
+ PCR_RESET, // SIU_PCR46\r
+ PCR_RESET, // SIU_PCR47\r
+ PCR_RESET, // SIU_PCR48\r
+ PCR_RESET, // SIU_PCR49\r
+ PCR_RESET, // SIU_PCR50\r
+ PCR_RESET, // SIU_PCR51\r
+ PCR_RESET, // SIU_PCR52\r
+ PCR_RESET, // SIU_PCR53\r
+ PCR_RESET, // SIU_PCR54\r
+ PCR_RESET, // SIU_PCR55\r
+ PCR_RESET, // SIU_PCR56\r
+ PCR_RESET, // SIU_PCR57\r
+ PCR_RESET, // SIU_PCR58\r
+ PCR_RESET, // SIU_PCR59\r
+ PCR_RESET, // SIU_PCR60\r
+ PCR_RESET, // SIU_PCR61\r
+ PCR_RESET, // SIU_PCR62\r
+ PCR_RESET, // SIU_PCR63\r
+ PCR_RESET, // SIU_PCR64\r
+ PCR_RESET, // SIU_PCR65\r
+ PCR_RESET, // SIU_PCR66\r
+ PCR_RESET, // SIU_PCR67\r
+ PCR_RESET, // SIU_PCR68\r
+ PCR_RESET, // SIU_PCR69\r
+ PCR_RESET, // SIU_PCR70\r
+ PCR_RESET, // SIU_PCR71\r
+ PCR_RESET, // SIU_PCR72\r
+ PCR_RESET, // SIU_PCR73\r
+ PCR_RESET, // SIU_PCR74\r
+ PCR_RESET, // SIU_PCR75\r
+ PCR_RESET, // SIU_PCR76\r
+ PCR_RESET, // SIU_PCR77\r
+ PCR_RESET, // SIU_PCR78\r
+ PCR_RESET, // SIU_PCR79\r
+ PCR_RESET, // SIU_PCR80\r
+ PCR_RESET, // SIU_PCR81\r
+ PCR_RESET, // SIU_PCR82\r
+ PCR_RESET, // SIU_PCR83\r
+ PCR_RESET, // SIU_PCR84\r
+ PCR_RESET, // SIU_PCR85\r
+ PCR_RESET, // SIU_PCR86\r
+ PCR_RESET, // SIU_PCR87\r
+ PCR_RESET, // SIU_PCR88\r
+ PCR_RESET, // SIU_PCR89\r
+ PCR_RESET, // SIU_PCR90\r
+ PCR_RESET, // SIU_PCR91\r
+ PCR_RESET, // SIU_PCR92\r
+ PCR_RESET, // SIU_PCR93\r
+ PCR_RESET, // SIU_PCR94\r
+ PCR_RESET, // SIU_PCR95\r
+ PCR_RESET, // SIU_PCR96\r
+ PCR_RESET, // SIU_PCR97\r
+ PCR_RESET, // SIU_PCR98\r
+ PCR_RESET, // SIU_PCR99\r
+ PCR_RESET, // SIU_PCR100\r
+ PCR_RESET, // SIU_PCR101\r
+ PCR_RESET, // SIU_PCR102\r
+ PCR_RESET, // SIU_PCR103\r
+ PCR_RESET, // SIU_PCR104\r
+ PCR_RESET, // SIU_PCR105\r
+ PCR_RESET, // SIU_PCR106\r
+ PCR_RESET, // SIU_PCR107\r
+ PCR_RESET, // SIU_PCR108\r
+ PCR_RESET, // SIU_PCR109\r
+ PCR_RESET, // SIU_PCR110\r
+ PCR_RESET, // SIU_PCR111\r
+ PCR_RESET, // SIU_PCR112\r
+ PCR_RESET, // SIU_PCR113\r
+ PCR_RESET, // SIU_PCR114\r
+ PCR_RESET, // SIU_PCR115\r
+ PCR_RESET, // SIU_PCR116\r
+ PCR_RESET, // SIU_PCR117\r
+ PCR_RESET, // SIU_PCR118\r
+ PCR_RESET, // SIU_PCR119\r
+ PCR_RESET, // SIU_PCR120\r
+ PCR_RESET, // SIU_PCR121\r
+ PCR_RESET, // SIU_PCR122\r
+ PCR_RESET, // SIU_PCR123\r
+ PCR_RESET, // SIU_PCR124\r
+ PCR_IO_OUTPUT, // SIU_PCR125 detta borde vara dioden som sitter på K2\r
+ PCR_RESET, // SIU_PCR126\r
+ PCR_RESET, // SIU_PCR127\r
+ PCR_RESET, // SIU_PCR128\r
+ PCR_RESET, // SIU_PCR129\r
+ PCR_RESET, // SIU_PCR130\r
+ PCR_RESET, // SIU_PCR131\r
+ PCR_RESET, // SIU_PCR132\r
+ PCR_RESET, // SIU_PCR133\r
+ PCR_RESET, // SIU_PCR134\r
+ PCR_RESET, // SIU_PCR135\r
+ PCR_RESET, // SIU_PCR136\r
+ PCR_RESET, // SIU_PCR137\r
+ PCR_RESET, // SIU_PCR138\r
+ PCR_RESET, // SIU_PCR139\r
+ PCR_RESET, // SIU_PCR140\r
+ PCR_RESET, // SIU_PCR141\r
+ PCR_RESET, // SIU_PCR142\r
+ PCR_RESET, // SIU_PCR143\r
+ PCR_RESET, // SIU_PCR144\r
+ PCR_RESET, // SIU_PCR145\r
+ PCR_RESET, // SIU_PCR146\r
+ PCR_RESET, // SIU_PCR147\r
+ PCR_RESET, // SIU_PCR148\r
+ PCR_RESET, // SIU_PCR149\r
+ PCR_RESET, // SIU_PCR150\r
+ PCR_RESET, // SIU_PCR151\r
+ PCR_RESET, // SIU_PCR152\r
+ PCR_RESET, // SIU_PCR153\r
+ PCR_RESET, // SIU_PCR154\r
+ PCR_RESET, // SIU_PCR155\r
+ PCR_RESET, // SIU_PCR156\r
+ PCR_RESET, // SIU_PCR157\r
+ PCR_RESET, // SIU_PCR158\r
+ PCR_RESET, // SIU_PCR159\r
+ PCR_RESET, // SIU_PCR160\r
+ PCR_RESET, // SIU_PCR161\r
+ PCR_RESET, // SIU_PCR162\r
+ PCR_RESET, // SIU_PCR163\r
+ PCR_RESET, // SIU_PCR164\r
+ PCR_RESET, // SIU_PCR165\r
+ PCR_RESET, // SIU_PCR166\r
+ PCR_RESET, // SIU_PCR167\r
+ PCR_RESET, // SIU_PCR168\r
+ PCR_RESET, // SIU_PCR169\r
+ PCR_RESET, // SIU_PCR170\r
+ PCR_RESET, // SIU_PCR171\r
+ PCR_RESET, // SIU_PCR172\r
+ PCR_RESET, // SIU_PCR173\r
+ PCR_RESET, // SIU_PCR174\r
+ PCR_RESET, // SIU_PCR175\r
+ PCR_RESET, // SIU_PCR176\r
+ PCR_RESET, // SIU_PCR177\r
+ PCR_RESET, // SIU_PCR178\r
+ PCR_RESET, // SIU_PCR179\r
+ PCR_RESET, // SIU_PCR180\r
+ PCR_RESET, // SIU_PCR181\r
+ PCR_RESET, // SIU_PCR182\r
+ PCR_RESET, // SIU_PCR183\r
+ PCR_RESET, // SIU_PCR184\r
+ PCR_RESET, // SIU_PCR185\r
+ PCR_RESET, // SIU_PCR186\r
+ PCR_RESET, // SIU_PCR187\r
+ PCR_RESET, // SIU_PCR188\r
+ PA_PRIMARY_FUNC|OBE_ENABLE, // SIU_PCR189; This one should be EMIOS channel 10\r
+ PCR_RESET, // SIU_PCR190\r
+ PA_PRIMARY_FUNC|OBE_ENABLE, // SIU_PCR191; EMIOS channel 12\r
+ PCR_RESET, // SIU_PCR192\r
+ PCR_RESET, // SIU_PCR193\r
+ PCR_RESET, // SIU_PCR194\r
+ PCR_RESET, // SIU_PCR195\r
+ PCR_RESET, // SIU_PCR196\r
+ PCR_RESET, // SIU_PCR197\r
+ PCR_RESET, // SIU_PCR198\r
+ PCR_RESET, // SIU_PCR199\r
+ PCR_RESET, // SIU_PCR200\r
+ PCR_RESET, // SIU_PCR201\r
+ PCR_RESET, // SIU_PCR202\r
+ PCR_RESET, // SIU_PCR203\r
+ PCR_RESET, // SIU_PCR204\r
+ PCR_RESET, // SIU_PCR205\r
+ PCR_RESET, // SIU_PCR206\r
+ PCR_RESET, // SIU_PCR207\r
+ PCR_RESET, // SIU_PCR208\r
+ PCR_RESET, // SIU_PCR209\r
+ PCR_RESET, // SIU_PCR210\r
+ PCR_RESET, // SIU_PCR211\r
+ PCR_RESET, // SIU_PCR212\r
+ PCR_RESET, // SIU_PCR213\r
+ PCR_RESET, // SIU_PCR214\r
+ PCR_RESET, // SIU_PCR215\r
+ PCR_RESET, // SIU_PCR216\r
+ PCR_RESET, // SIU_PCR217\r
+ PCR_RESET, // SIU_PCR218\r
+ PCR_RESET, // SIU_PCR219\r
+ PCR_RESET, // SIU_PCR220\r
+ PCR_RESET, // SIU_PCR221\r
+ PCR_RESET, // SIU_PCR222\r
+ PCR_RESET, // SIU_PCR223\r
+ PCR_RESET, // SIU_PCR224\r
+ PCR_RESET, // SIU_PCR225\r
+ PCR_RESET, // SIU_PCR226\r
+ PCR_RESET, // SIU_PCR227\r
+ PCR_RESET, // SIU_PCR228\r
+ PCR_RESET, // SIU_PCR229\r
+ PCR_RESET, // SIU_PCR230\r
+ };\r
+\r
+const uint8_t PortOutConfigData[] = {\r
+ GPDO_RESET, // SIU_GPDO0\r
+ GPDO_RESET, // SIU_GPDO1\r
+ GPDO_RESET, // SIU_GPDO2\r
+ GPDO_RESET, // SIU_GPDO3\r
+ GPDO_RESET, // SIU_GPDO4\r
+ GPDO_RESET, // SIU_GPDO5\r
+ GPDO_RESET, // SIU_GPDO6\r
+ GPDO_RESET, // SIU_GPDO7\r
+ GPDO_RESET, // SIU_GPDO8\r
+ GPDO_RESET, // SIU_GPDO9\r
+ GPDO_RESET, // SIU_GPDO10\r
+ GPDO_RESET, // SIU_GPDO11\r
+ GPDO_RESET, // SIU_GPDO12\r
+ GPDO_RESET, // SIU_GPDO13\r
+ GPDO_RESET, // SIU_GPDO14\r
+ GPDO_RESET, // SIU_GPDO15\r
+ GPDO_RESET, // SIU_GPDO16\r
+ GPDO_RESET, // SIU_GPDO17\r
+ GPDO_RESET, // SIU_GPDO18\r
+ GPDO_RESET, // SIU_GPDO19\r
+ GPDO_RESET, // SIU_GPDO20\r
+ GPDO_RESET, // SIU_GPDO21\r
+ GPDO_RESET, // SIU_GPDO22\r
+ GPDO_RESET, // SIU_GPDO23\r
+ GPDO_RESET, // SIU_GPDO24\r
+ GPDO_RESET, // SIU_GPDO25\r
+ GPDO_RESET, // SIU_GPDO26\r
+ GPDO_RESET, // SIU_GPDO27\r
+ GPDO_RESET, // SIU_GPDO28\r
+ GPDO_RESET, // SIU_GPDO29\r
+ GPDO_RESET, // SIU_GPDO30\r
+ GPDO_RESET, // SIU_GPDO31\r
+ GPDO_RESET, // SIU_GPDO32\r
+ GPDO_RESET, // SIU_GPDO33\r
+ GPDO_RESET, // SIU_GPDO34\r
+ GPDO_RESET, // SIU_GPDO35\r
+ GPDO_RESET, // SIU_GPDO36\r
+ GPDO_RESET, // SIU_GPDO37\r
+ GPDO_RESET, // SIU_GPDO38\r
+ GPDO_RESET, // SIU_GPDO39\r
+ GPDO_RESET, // SIU_GPDO40\r
+ GPDO_RESET, // SIU_GPDO41\r
+ GPDO_RESET, // SIU_GPDO42\r
+ GPDO_RESET, // SIU_GPDO43\r
+ GPDO_RESET, // SIU_GPDO44\r
+ GPDO_RESET, // SIU_GPDO45\r
+ GPDO_RESET, // SIU_GPDO46\r
+ GPDO_RESET, // SIU_GPDO47\r
+ GPDO_RESET, // SIU_GPDO48\r
+ GPDO_RESET, // SIU_GPDO49\r
+ GPDO_RESET, // SIU_GPDO50\r
+ GPDO_RESET, // SIU_GPDO51\r
+ GPDO_RESET, // SIU_GPDO52\r
+ GPDO_RESET, // SIU_GPDO53\r
+ GPDO_RESET, // SIU_GPDO54\r
+ GPDO_RESET, // SIU_GPDO55\r
+ GPDO_RESET, // SIU_GPDO56\r
+ GPDO_RESET, // SIU_GPDO57\r
+ GPDO_RESET, // SIU_GPDO58\r
+ GPDO_RESET, // SIU_GPDO59\r
+ GPDO_RESET, // SIU_GPDO60\r
+ GPDO_RESET, // SIU_GPDO61\r
+ GPDO_RESET, // SIU_GPDO62\r
+ GPDO_RESET, // SIU_GPDO63\r
+ GPDO_RESET, // SIU_GPDO64\r
+ GPDO_RESET, // SIU_GPDO65\r
+ GPDO_RESET, // SIU_GPDO66\r
+ GPDO_RESET, // SIU_GPDO67\r
+ GPDO_RESET, // SIU_GPDO68\r
+ GPDO_RESET, // SIU_GPDO69\r
+ GPDO_RESET, // SIU_GPDO70\r
+ GPDO_RESET, // SIU_GPDO71\r
+ GPDO_RESET, // SIU_GPDO72\r
+ GPDO_RESET, // SIU_GPDO73\r
+ GPDO_RESET, // SIU_GPDO74\r
+ GPDO_RESET, // SIU_GPDO75\r
+ GPDO_RESET, // SIU_GPDO76\r
+ GPDO_RESET, // SIU_GPDO77\r
+ GPDO_RESET, // SIU_GPDO78\r
+ GPDO_RESET, // SIU_GPDO79\r
+ GPDO_RESET, // SIU_GPDO80\r
+ GPDO_RESET, // SIU_GPDO81\r
+ GPDO_RESET, // SIU_GPDO82\r
+ GPDO_RESET, // SIU_GPDO83\r
+ GPDO_RESET, // SIU_GPDO84\r
+ GPDO_RESET, // SIU_GPDO85\r
+ GPDO_RESET, // SIU_GPDO86\r
+ GPDO_RESET, // SIU_GPDO87\r
+ GPDO_RESET, // SIU_GPDO88\r
+ GPDO_RESET, // SIU_GPDO89\r
+ GPDO_RESET, // SIU_GPDO90\r
+ GPDO_RESET, // SIU_GPDO91\r
+ GPDO_RESET, // SIU_GPDO92\r
+ GPDO_RESET, // SIU_GPDO93\r
+ GPDO_RESET, // SIU_GPDO94\r
+ GPDO_RESET, // SIU_GPDO95\r
+ GPDO_RESET, // SIU_GPDO96\r
+ GPDO_RESET, // SIU_GPDO97\r
+ GPDO_RESET, // SIU_GPDO98\r
+ GPDO_RESET, // SIU_GPDO99\r
+ GPDO_RESET, // SIU_GPDO100\r
+ GPDO_RESET, // SIU_GPDO101\r
+ GPDO_RESET, // SIU_GPDO102\r
+ GPDO_RESET, // SIU_GPDO103\r
+ GPDO_RESET, // SIU_GPDO104\r
+ GPDO_RESET, // SIU_GPDO105\r
+ GPDO_RESET, // SIU_GPDO106\r
+ GPDO_RESET, // SIU_GPDO107\r
+ GPDO_RESET, // SIU_GPDO108\r
+ GPDO_RESET, // SIU_GPDO109\r
+ GPDO_RESET, // SIU_GPDO110\r
+ GPDO_RESET, // SIU_GPDO111\r
+ GPDO_RESET, // SIU_GPDO112\r
+ GPDO_RESET, // SIU_GPDO113\r
+ GPDO_RESET, // SIU_GPDO114\r
+ GPDO_RESET, // SIU_GPDO115\r
+ GPDO_RESET, // SIU_GPDO116\r
+ GPDO_RESET, // SIU_GPDO117\r
+ GPDO_RESET, // SIU_GPDO118\r
+ GPDO_RESET, // SIU_GPDO119\r
+ GPDO_RESET, // SIU_GPDO120\r
+ GPDO_RESET, // SIU_GPDO121\r
+ GPDO_RESET, // SIU_GPDO122\r
+ GPDO_RESET, // SIU_GPDO123\r
+ GPDO_RESET, // SIU_GPDO124\r
+ GPDO_RESET, // SIU_GPDO125\r
+ GPDO_RESET, // SIU_GPDO126\r
+ GPDO_RESET, // SIU_GPDO127\r
+ GPDO_RESET, // SIU_GPDO128\r
+ GPDO_RESET, // SIU_GPDO129\r
+ GPDO_RESET, // SIU_GPDO130\r
+ GPDO_RESET, // SIU_GPDO131\r
+ GPDO_RESET, // SIU_GPDO132\r
+ GPDO_RESET, // SIU_GPDO133\r
+ GPDO_RESET, // SIU_GPDO134\r
+ GPDO_RESET, // SIU_GPDO135\r
+ GPDO_RESET, // SIU_GPDO136\r
+ GPDO_RESET, // SIU_GPDO137\r
+ GPDO_RESET, // SIU_GPDO138\r
+ GPDO_RESET, // SIU_GPDO139\r
+ GPDO_RESET, // SIU_GPDO140\r
+ GPDO_RESET, // SIU_GPDO141\r
+ GPDO_RESET, // SIU_GPDO142\r
+ GPDO_RESET, // SIU_GPDO143\r
+ GPDO_RESET, // SIU_GPDO144\r
+ GPDO_RESET, // SIU_GPDO145\r
+ GPDO_RESET, // SIU_GPDO146\r
+ GPDO_RESET, // SIU_GPDO147\r
+ GPDO_RESET, // SIU_GPDO148\r
+ GPDO_RESET, // SIU_GPDO149\r
+ GPDO_RESET, // SIU_GPDO150\r
+ GPDO_RESET, // SIU_GPDO151\r
+ GPDO_RESET, // SIU_GPDO152\r
+ GPDO_RESET, // SIU_GPDO153\r
+ GPDO_RESET, // SIU_GPDO154\r
+ GPDO_RESET, // SIU_GPDO155\r
+ GPDO_RESET, // SIU_GPDO156\r
+ GPDO_RESET, // SIU_GPDO157\r
+ GPDO_RESET, // SIU_GPDO158\r
+ GPDO_RESET, // SIU_GPDO159\r
+ GPDO_RESET, // SIU_GPDO160\r
+ GPDO_RESET, // SIU_GPDO161\r
+ GPDO_RESET, // SIU_GPDO162\r
+ GPDO_RESET, // SIU_GPDO163\r
+ GPDO_RESET, // SIU_GPDO164\r
+ GPDO_RESET, // SIU_GPDO165\r
+ GPDO_RESET, // SIU_GPDO166\r
+ GPDO_RESET, // SIU_GPDO167\r
+ GPDO_RESET, // SIU_GPDO168\r
+ GPDO_RESET, // SIU_GPDO169\r
+ GPDO_RESET, // SIU_GPDO170\r
+ GPDO_RESET, // SIU_GPDO171\r
+ GPDO_RESET, // SIU_GPDO172\r
+ GPDO_RESET, // SIU_GPDO173\r
+ GPDO_RESET, // SIU_GPDO174\r
+ GPDO_RESET, // SIU_GPDO175\r
+ GPDO_RESET, // SIU_GPDO176\r
+ GPDO_RESET, // SIU_GPDO177\r
+ GPDO_RESET, // SIU_GPDO178\r
+ GPDO_RESET, // SIU_GPDO179\r
+ GPDO_RESET, // SIU_GPDO180\r
+ GPDO_RESET, // SIU_GPDO181\r
+ GPDO_RESET, // SIU_GPDO182\r
+ GPDO_RESET, // SIU_GPDO183\r
+ GPDO_RESET, // SIU_GPDO184\r
+ GPDO_RESET, // SIU_GPDO185\r
+ GPDO_RESET, // SIU_GPDO186\r
+ GPDO_RESET, // SIU_GPDO187\r
+ GPDO_RESET, // SIU_GPDO188\r
+ GPDO_RESET, // SIU_GPDO189\r
+ GPDO_RESET, // SIU_GPDO190\r
+ GPDO_RESET, // SIU_GPDO191\r
+ GPDO_RESET, // SIU_GPDO192\r
+ GPDO_RESET, // SIU_GPDO193\r
+ GPDO_RESET, // SIU_GPDO194\r
+ GPDO_RESET, // SIU_GPDO195\r
+ GPDO_RESET, // SIU_GPDO196\r
+ GPDO_RESET, // SIU_GPDO197\r
+ GPDO_RESET, // SIU_GPDO198\r
+ GPDO_RESET, // SIU_GPDO199\r
+ GPDO_RESET, // SIU_GPDO200\r
+ GPDO_RESET, // SIU_GPDO201\r
+ GPDO_RESET, // SIU_GPDO202\r
+ GPDO_RESET, // SIU_GPDO203\r
+ GPDO_RESET, // SIU_GPDO204\r
+ GPDO_RESET, // SIU_GPDO205\r
+ GPDO_RESET, // SIU_GPDO206\r
+ GPDO_RESET, // SIU_GPDO207\r
+ GPDO_RESET, // SIU_GPDO208\r
+ GPDO_RESET, // SIU_GPDO209\r
+ GPDO_RESET, // SIU_GPDO210\r
+ GPDO_RESET, // SIU_GPDO211\r
+ GPDO_RESET, // SIU_GPDO212\r
+ GPDO_RESET, // SIU_GPDO213\r
+};\r
+\r
+const Port_ConfigType PortConfigData =\r
+{\r
+ .padCnt = sizeof(PortPadConfigData),\r
+ .padConfig = PortPadConfigData,\r
+ .outCnt = sizeof(PortOutConfigData),\r
+ .outConfig = PortOutConfigData,\r
+};\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef PORT_CFG_H_\r
+#define PORT_CFG_H_\r
+\r
+#include "Std_Types.h"\r
+\r
+#define PORT_VERSION_INFO_API STD_ON\r
+#define PORT_DEV_ERROR_DETECT STD_ON\r
+#define PORT_PIN_DIRECTION_CHANGES_ALLOWED STD_ON\r
+\r
+typedef uint16 Port_PinType;\r
+\r
+#define BIT0 (1<<15)\r
+#define BIT1 (1<<14)\r
+#define BIT2 (1<<13)\r
+#define BIT3 (1<<12)\r
+#define BIT4 (1<<11)\r
+#define BIT5 (1<<10)\r
+#define BIT6 (1<<9)\r
+#define BIT7 (1<<8)\r
+#define BIT8 (1<<7)\r
+#define BIT9 (1<<6)\r
+#define BIT10 (1<<5)\r
+#define BIT11 (1<<4)\r
+#define BIT12 (1<<3)\r
+#define BIT13 (1<<2)\r
+#define BIT14 (1<<1)\r
+#define BIT15 (1<<0)\r
+\r
+#define WPS_BIT BIT15\r
+#define WPE_BIT BIT14\r
+#define SRC1_BIT BIT13\r
+#define SRC0_BIT BIT12\r
+#define HYS_BIT BIT11\r
+#define ODE_BIT BIT10\r
+#define DSC1_BIT BIT9\r
+#define DSC0_BIT BIT8\r
+#define IBE_BIT BIT7\r
+#define OBE_BIT BIT6\r
+#define PA2_BIT BIT5\r
+#define PA1_BIT BIT4\r
+#define PA0_BIT BIT3\r
+\r
+#define PULL_UP (WPE_BIT|WPS_BIT)\r
+#define PULL_DOWN (WPE_BIT)\r
+#define PULL_NONE (0)\r
+#define SLEW_RATE_MIN (0)\r
+#define SLEW_RATE_MED (SRC1_BIT)\r
+#define SLEW_RATE_MAX (SRC1_BIT|SRC0_BIT)\r
+#define HYS_ENABLE (HYS_BIT)\r
+#define ODE_ENABLE (ODE_BIT)\r
+#define IBE_ENABLE (IBE_BIT)\r
+#define OBE_ENABLE (OBE_BIT)\r
+\r
+#define PA_IO (0)\r
+#define PA_PRIMARY_FUNC (PA2_BIT)\r
+#define PA_ALTERNATE_FUNC1 (PA1_BIT)\r
+#define PA_PRIMARY_FUNC1 (PA1_BIT|PA2_BIT)\r
+#define PA_ALTERNATE_FUNC2 (PA0_BIT)\r
+\r
+#define PCR_IO_INPUT (IBE_ENABLE|PULL_DOWN)\r
+#define PCR_IO_OUTPUT (OBE_ENABLE)\r
+\r
+// Should be this out of reset\r
+#define PCR_RESET (0)\r
+#define PCR_BOOTCFG (PCR_IO_INPUT)\r
+#define GPDO_RESET (0)\r
+\r
+typedef struct\r
+{\r
+ uint16_t padCnt;\r
+ const uint16_t *padConfig;\r
+ uint16_t outCnt;\r
+ const uint8_t *outConfig;\r
+} Port_ConfigType;\r
+\r
+extern const Port_ConfigType PortConfigData;\r
+\r
+#endif /*PORT_CFG_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*
+ * Pwm_Cfg.h
+ *
+ * Created on: 2009-jul-09
+ * Author: nian
+ */
+
+#ifndef PWM_CFG_H_
+#define PWM_CFG_H_
+
+/****************************************************************************
+ * Global configuration options and defines
+ */
+
+#define ON 1
+#define OFF 0
+
+/*
+ * PWM003: The detection of development errors is configurable (ON/OFF) at
+ * pre-compile time. The switch PwmDevErorDetect shall activate or disable
+ * the detection of all development errors
+ */
+#define PWM_DEV_EROR_DETECT ON
+#define PWM_GET_OUTPUT_STATE ON
+#define PWM_STATICALLY_CONFIGURED OFF
+#define PWM_NOTIFICATION_SUPPORTED ON
+#define PWM_SET_PERIOD_AND_DUTY ON
+#define PWM_DEINIT_API ON
+
+/*
+ * PWM132: Switch for enabling the update of duty cycle parameter at the end
+ * of the current period.
+ *
+ * Note: Currently only ON mode is supported.
+ */
+#define PWM_DUTYCYCLE_UPDATED_ENDPERIOD ON
+
+/****************************************************************************
+ * Not defined in AUTOSAR.
+ */
+#define PWM_ISR_PRIORITY 1
+#define PWM_PRESCALER 64
+/*
+ * Setting to ON freezes the current output state of a PWM channel when in
+ * debug mode.
+ */
+#define PWM_FREEZE_ENABLE ON
+
+/****************************************************************************
+ * Enumeration of channels
+ * Maps a symbolic name to a hardware channel
+ */
+typedef enum {
+#ifdef CFG_BRD_MPC5516IT
+ PWM_CHANNEL_1 = 13, /* Emios channel 13 and 12 map to the */
+ PWM_CHANNEL_2 = 12, /* LEDs LD4 and LD5 of MPC5516IT */
+
+#elif defined(CFG_BRD_MPC5567QRTECH)
+ PWM_CHANNEL_1 = 10, /* Emios channel 10 maps to PCR189 which
+ * is available on pin 54 of the
+ * ERNI 154822 connector
+ */
+ PWM_CHANNEL_2 = 12, /* Channel 12 goes to PCR191, also
+ * available on the ERNI 154822 connector
+ */
+#else
+#warning "Unknown board or CFG_BRD_* undefined"
+#endif
+ PWM_NUMBER_OF_CHANNELS = 2
+} Pwm_NamedChannelsType;
+
+#endif /* PWM_CFG_H_ */
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef SPI_CFG_H_
+#define SPI_CFG_H_
+
+#include "Dma_Cfg.h"
+#include "Mcu_Cfg.h"
+
+#define DSPI_CTRL_A 0
+#define DSPI_CTRL_B 1
+#define DSPI_CTRL_C 2
+#define DSPI_CTRL_D 3
+
+/*
+ * General configuration
+ */
+
+// Maximum amount of data that can be written/read in one go.
+#define SPI_EB_MAX_LENGTH 64
+
+// Switches the Spi_Cancel function ON or OFF.
+#define SPI_CANCEL_API STD_OFF
+
+// Selects the SPI Handler/Driver Channel Buffers usage allowed and delivered.
+// LEVEL 0 - Only Internal buffers
+// LEVEL 1 - Only external buffers
+// LEVEL 2 - Both internal/external buffers
+#define SPI_CHANNEL_BUFFERS_ALLOWED 1
+
+#define SPI_DEV_ERROR_DETECT STD_ON
+// Switches the Spi_GetHWUnitStatus function ON or OFF.
+#define SPI_HW_STATUS_API STD_ON
+// Switches the Interruptible Sequences handling functionality ON or OFF.
+#define SPI_INTERRUPTIBLE_SEQ_ALLOWED STD_OFF
+
+// LEVEL 0 - Simple sync
+// LEVEL 1 - Basic async
+// LEVEL 2 - Enhanced mode
+#define SPI_LEVEL_DELIVERED 2
+
+#define SPI_VERSION_INFO_API STD_ON
+
+#if 0
+#if SPI_LEVEL_DELIVERED>=1
+#define SPI_INTERRUPTIBLE_SEQ_ALLOWED STD_ON
+#endif
+#endif
+
+// M95256
+#define E2_WREN 0x6 // Write Enable 0000 0110
+#define E2_WRDI 0x4 // Write Disable 0000 0100
+#define E2_RDSR 0x5 // Read Status Register 0000 0101
+ // 1 - Read data
+#define E2_WRSR 0x1 // Write Status Register 0000 0001
+ // 1 - Write data
+#define E2_READ 0x3 // Read from Memory Array 0000 0011
+ // 1 - Write 16-bit address
+ // n - 8 -bit read data
+#define E2_WRITE 0x2 // WRITE Write to Memory Array 0000 0010
+ // 1 Write 16-bit address
+ // n - 8-bit reads
+
+
+#define FLASH_READ_25 0x03
+#define FLASH_READ_50 0x0B
+#define FLASH_RDSR 0x05
+#define FLASH_JEDEC_ID 0x9f
+#define FLASH_RDID 0x90
+#define FLASH_BYTE_WRITE 0x02
+#define FLASH_AI_WORD_WRITE 0xad
+#define FLASH_WREN 0x06
+#define FLASH_WRDI 0x04
+#define FLASH_WRSR 0x01
+#define FLASH_ERASE_4K 0x20
+
+
+
+typedef enum
+{
+ SPI_EB = 0, // External Buffer
+ SPI_IB // Internal Buffer
+} Spi_BufferType;
+
+typedef enum {
+ SPI_EXT_DEVICE_A_E2,
+ SPI_EXT_DEVICE_A_FLASH,
+ SPI_EXT_DEVICE_B_E2,
+} Spi_ExternalDeviceTypeType;
+
+typedef enum
+{
+ SPI_CH_E2_CMD = 0,
+ SPI_CH_E2_ADDR,
+ SPI_CH_E2_WREN,
+ SPI_CH_E2_DATA,
+
+ SPI_CH_EEP_CMD,
+ SPI_CH_EEP_ADDR,
+ SPI_CH_EEP_WREN,
+ SPI_CH_EEP_DATA,
+
+ SPI_CH_FLASH_CMD,
+ SPI_CH_FLASH_ADDR,
+ SPI_CH_FLASH_DATA,
+ SPI_CH_FLASH_WREN,
+ SPI_CH_FLASH_WRDI,
+ SPI_CH_FLASH_WRSR,
+
+ SPI_MAX_CHANNEL,
+} Spi_ChannelType;
+
+typedef enum
+{
+ SPI_JOB_E2_CMD = 0,
+ SPI_JOB_E2_CMD2,
+ SPI_JOB_E2_DATA,
+ SPI_JOB_E2_WREN,
+
+ SPI_JOB_EEP_CMD,
+ SPI_JOB_EEP_CMD2,
+ SPI_JOB_EEP_DATA,
+ SPI_JOB_EEP_WREN,
+
+ SPI_JOB_FLASH_CMD,
+ SPI_JOB_FLASH_CMD2,
+ SPI_JOB_FLASH_CMD_DATA,
+ SPI_JOB_FLASH_READ,
+ SPI_JOB_FLASH_WREN,
+ SPI_JOB_FLASH_WRDI,
+ SPI_JOB_FLASH_DATA,
+ SPI_JOB_FLASH_WRSR,
+ SPI_JOB_FLASH_ADDR,
+
+ SPI_MAX_JOB,
+} Spi_JobType;
+
+#define SPI_MAX_CHANNELS 8
+
+typedef enum
+{
+ SPI_SEQ_E2_CMD = 0,
+ SPI_SEQ_E2_CMD2,
+ SPI_SEQ_E2_READ,
+ SPI_SEQ_E2_WRITE,
+
+ SPI_SEQ_EEP_CMD,
+ SPI_SEQ_EEP_CMD2,
+ SPI_SEQ_EEP_READ,
+ SPI_SEQ_EEP_WRITE,
+
+ SPI_SEQ_FLASH_CMD,
+ SPI_SEQ_FLASH_CMD2,
+ SPI_SEQ_FLASH_CMD_DATA,
+ SPI_SEQ_FLASH_READ,
+ SPI_SEQ_FLASH_WRITE,
+ SPI_SEQ_FLASH_WRSR,
+ SPI_SEQ_FLASH_ERASE,
+
+ SPI_MAX_SEQUENCE,
+} Spi_SequenceType;
+
+typedef enum
+{
+ SPI_ECORE_TRANSFER_START_LSB,
+ SPI_ECORE_TRANSFER_START_MSB,
+} Spi_EcoreTransferStartType;
+
+
+typedef enum {
+ SPI_EDGE_LEADING,
+ SPI_EDGE_TRAILING
+} Spi_EdgeType;
+
+
+
+// All data needed to configure one SPI-channel
+typedef struct
+{
+ // Symbolic name
+ Spi_ChannelType SpiChannelId;
+ // Buffer usage with EB/IB channel
+ // TODO: The type is wrong...
+ unsigned SpiChannelType;
+
+ // This parameter is the width of a transmitted data unit.
+ uint32 SpiDataWidth;
+ // This parameter is the default value to transmit.
+ uint32 SpiDefaultData;
+
+ // This parameter contains the maximum size of data buffers in case of EB
+ // Channels and only.
+ Spi_NumberOfDataType SpiEbMaxLength;
+
+ // This parameter contains the maximum number of data buffers in case of IB
+ // Channels and only.
+ Spi_NumberOfDataType SpiIbNBuffers;
+
+ // This parameter defines the first starting bit for transmission.
+ Spi_EcoreTransferStartType SpiTransferStart;
+
+ //
+ _Bool SpiDmaNoIncreaseSrc;
+
+} Spi_ChannelConfigType;
+
+// All data needed to configure one SPI-Job, amongst others the connection
+// between the internal SPI unit and the special settings for an external de-
+// vice is done.
+typedef struct
+{
+
+ Spi_JobType SpiJobId;
+
+ // This parameter is the symbolic name to identify the HW SPI Hardware micro-
+ // controller peripheral allocated to this Job.
+ uint32 SpiHwUnit;
+
+ // This parameter is a reference to a notification function.
+ void (*SpiJobEndNotification)();
+
+ // Priority of the Job
+ // range 0..3
+ unsigned SpiJobPriority;
+
+ // A job references several channels.
+ uint32 ChannelAssignment[SPI_MAX_CHANNELS];
+
+ // Reference to the external device used by this job
+ Spi_ExternalDeviceTypeType DeviceAssignment;
+
+// unsigned SPI_NUMBER_OF_CHANNELS;
+// unsigned SPI_LIST_OF_CHANNELS[SPI_MAX_CHANNEL];
+} Spi_JobConfigType;
+
+// The communication settings of an external device. Closely linked to Spi-
+// Job.
+typedef struct
+{
+
+ // This parameter is the communication baudrate - This parameter allows
+ // using a range of values, from the point of view of configuration tools, from
+ // Hz up to MHz.
+ // Note! Float in config case, not here
+ uint32 SpiBaudrate;
+
+ // Symbolic name to identify the CS used for this job
+ uint32 SpiCsIdentifier;
+
+ // This parameter defines the active polarity of Chip Select.
+ // STD_HIGH or STD_LOW
+ uint8 SpiCsPolarity;
+
+ // This parameter defines the SPI data shift edge.
+ Spi_EdgeType SpiDataShiftEdge;
+
+ // This parameter enables or not the Chip Select handling functions.
+ uint8 SpiEnableCs;
+
+ // This parameter defines the SPI shift clock idle level.
+ uint8 SpiShiftClockIdleLevel;
+
+ // Timing between clock and chip select - This parameter allows to use a
+ // range of values from 0 up to 100 microSec. the real configuration-value
+ // used in software BSW-SPI is calculated out of this by the generator-tools
+ // Note! Float in config case, not here. Unit ns
+ uint32 SpiTimeClk2Cs;
+
+ // Timing between PCS and first edge of SCK. Unit ns.
+ uint32 SpiTimeCs2Clk;
+
+ // Ecore extension...
+ // The controller ID(0..3)
+ //uint32 SpiControllerId;
+
+} Spi_ExternalDeviceType;
+
+// All data needed to configure one SPI-sequence
+typedef struct
+{
+ // This parameter allows or not this Sequence to be suspended by another
+ // one.
+ unsigned SpiInterruptibleSequence;
+ // This parameter is a reference to a notification function.
+ void (*SpiSeqEndNotification)();
+ //
+ Spi_SequenceType SpiSequenceId;
+ // unsigned SPI_NUMBER_OF_JOBS;
+ // A sequence references several jobs, which are executed during a commu-
+ // nication sequence
+ uint32 JobAssignment[SPI_MAX_JOB];
+} Spi_SequenceConfigType;
+
+typedef struct
+{
+ /* Interrupt priority level for this SPI channel. */
+ uint8 IsrPriority;
+
+ /* This channel is to be activated for use. */
+ uint8 Activated;
+
+ /* Receive DMA channel. */
+ Dma_ChannelType RxDmaChannel;
+
+ /* Transmit DMA channel. */
+ Dma_ChannelType TxDmaChannel;
+
+ /* Peripheral clock source. */
+ McuE_PeriperalClock_t PeripheralClock;
+}Spi_HwConfigType;
+
+typedef struct
+{
+ // This parameter contains the number of Channels configured. It will be
+ // gathered by tools during the configuration stage.
+ uint8 SpiMaxChannel;
+
+ uint8 SpiMaxJob;
+
+ uint8 SpiMaxSequence;
+
+ // All data needed to configure one SPI-channel
+ const Spi_ChannelConfigType * SpiChannelConfig;
+
+ // The communication settings of an external device. Closely
+ // linked to SpiJob.
+ const Spi_ExternalDeviceType * SpiExternalDevice;
+
+ // All data needed to configure one SPI-Job, amongst others the
+ // connection between the internal SPI unit and the special set-
+ // tings for an external device is done.
+ const Spi_JobConfigType * SpiJobConfig;
+
+ // All data needed to configure one SPI-sequence
+ const Spi_SequenceConfigType * SpiSequenceConfig;
+
+ const Spi_HwConfigType *SpiHwConfig;
+} Spi_DriverType;
+
+typedef Spi_DriverType Spi_ConfigType;
+
+
+#if 0
+struct SpiDriverConfiguration_s
+{
+ Spi_ChannelType SPI_MAX_CHANNEL;
+ Spi_JobType SPI_MAX_JOB;
+ Spi_SequenceType SPI_MAX_SEQUENCE;
+};
+#endif
+
+// This is implementation specific but not all values may be valid
+// within the type.This type shall be chosen in order to have the
+// most efficient implementation on a specific microcontroller
+// platform.
+// In-short: Type of application data buffer elements
+// The 5516 TXDATA is 16-bit.. fits ?
+
+typedef uint8 Spi_DataType;
+//typedef uint16 Spi_DataType;
+
+// Specifies the identification (ID) for a SPI Hardware microcontroller peripheral (unit).
+// SPI140: This type is configurable (On / Off) at pre-compile time. The switch
+// SPI_HW_STATUS_API shall activate or deactivate the declaration of this
+// type.
+typedef uint32 Spi_HWUnitType;
+
+#if 0
+typedef struct
+{
+ Spi_SequenceConfigType SpiSequenceConfig;
+ Spi_JobConfigType SpiJobConfig;
+ Spi_ChannelConfigType SpiChannelConfig;
+ Spi_ExternalDeviceType SpiExternalDevice;
+}Spi_ConfigType;
+#endif
+
+extern const Spi_ConfigType SpiConfigData;
+
+
+uint32 Spi_GetJobCnt(void );
+uint32 Spi_GetChannelCnt(void );
+uint32 Spi_GetExternalDeviceCnt(void );
+
+
+
+#endif /*SPI_CFG_H_*/
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include "Spi.h"
+#include "Spi_Cfg.h"
+#include <stdlib.h>
+
+
+// SPI_A
+#define SPI_A_CS_E2 2
+#define SPI_A_CS_FLASH 1
+
+// SPI_B
+#define SPI_B_CS_E2 0
+
+
+#if 1
+extern void Spi_SeqEndNotification( void );
+extern void Spi_JobEndNotification( void );
+extern void Spi_Test_SeqEndNotification( Spi_SequenceType seq);
+extern void Spi_Test_JobEndNotification( Spi_JobType job);
+
+static void Spi_Test_SeqEndNotification_E2_CMD( void ) { Spi_Test_SeqEndNotification(SPI_SEQ_E2_CMD); }
+static void Spi_Test_SeqEndNotification_E2_CMD2( void ) { Spi_Test_SeqEndNotification(SPI_SEQ_E2_CMD2); }
+static void Spi_Test_SeqEndNotification_E2_READ( void ){ Spi_Test_SeqEndNotification(SPI_SEQ_E2_READ); }
+static void Spi_Test_SeqEndNotification_E2_WRITE( void ){ Spi_Test_SeqEndNotification(SPI_SEQ_E2_WRITE); }
+
+static void Spi_Test_JobEndNotification_E2_CMD( void ){ Spi_Test_JobEndNotification(SPI_JOB_E2_CMD); }
+static void Spi_Test_JobEndNotification_E2_CMD2( void ){ Spi_Test_JobEndNotification(SPI_JOB_E2_CMD2); }
+static void Spi_Test_JobEndNotification_E2_DATA( void ){ Spi_Test_JobEndNotification(SPI_JOB_E2_DATA); }
+static void Spi_Test_JobEndNotification_E2_WREN( void ){ Spi_Test_JobEndNotification(SPI_JOB_E2_WREN); }
+
+#define SPI_SEQ_END_NOTIFICATION NULL
+#define SPI_JOB_END_NOTIFICAITON NULL
+
+// Notifications
+// Seq
+#define SPI_SEQ_E2_CMD_END_NOTIFICATION Spi_Test_SeqEndNotification_E2_CMD
+#define SPI_SEQ_E2_CMD2_END_NOTIFICATION Spi_Test_SeqEndNotification_E2_CMD2
+#define SPI_SEQ_E2_READ_END_NOTIFICATION Spi_Test_SeqEndNotification_E2_READ
+#define SPI_SEQ_E2_WRITE_END_NOTIFICATION Spi_Test_SeqEndNotification_E2_WRITE
+// Jobs
+#define SPI_JOB_E2_CMD_END_NOTIFICATION Spi_Test_JobEndNotification_E2_CMD
+#define SPI_JOB_E2_CMD2_END_NOTIFICATION Spi_Test_JobEndNotification_E2_CMD2
+#define SPI_JOB_E2_DATA_END_NOTIFICATION Spi_Test_JobEndNotification_E2_DATA
+#define SPI_JOB_E2_WREN_END_NOTIFICATION Spi_Test_JobEndNotification_E2_WREN
+
+#else
+#define SPI_SEQ_END_NOTIFICATION NULL
+#define SPI_JOB_END_NOTIFICAITON NULL
+#endif
+
+
+/* SEQUENCES */
+const Spi_SequenceConfigType SpiSequenceConfigData[] =
+{
+ {
+ .SpiSequenceId = SPI_SEQ_E2_CMD, // The EEP read sequence
+ .SpiInterruptibleSequence = 0,
+ .SpiSeqEndNotification = SPI_SEQ_E2_CMD_END_NOTIFICATION,
+ .JobAssignment = { SPI_JOB_E2_CMD,(-1)},
+ },
+ {
+ .SpiSequenceId = SPI_SEQ_E2_CMD2, // The EEP read sequence
+ .SpiInterruptibleSequence = 0,
+ .SpiSeqEndNotification = SPI_SEQ_E2_CMD2_END_NOTIFICATION,
+ .JobAssignment = { SPI_JOB_E2_CMD2,(-1)},
+ },
+ {
+ .SpiSequenceId = SPI_SEQ_E2_READ, // The EEP read sequence
+ .SpiInterruptibleSequence = 0,
+ .SpiSeqEndNotification = SPI_SEQ_E2_READ_END_NOTIFICATION,
+ .JobAssignment = { SPI_JOB_E2_DATA,(-1)},
+ },
+ {
+ .SpiSequenceId = SPI_SEQ_E2_WRITE, // The EEP write sequence
+ .SpiInterruptibleSequence = 0,
+ .SpiSeqEndNotification = SPI_SEQ_E2_WRITE_END_NOTIFICATION,
+ .JobAssignment = { SPI_JOB_E2_DATA,(-1)},
+ },
+
+ // -----------------------------------
+ {
+ .SpiSequenceId = SPI_SEQ_EEP_CMD, // The EEP read sequence
+ .SpiInterruptibleSequence = 0,
+ .SpiSeqEndNotification = SPI_SEQ_END_NOTIFICATION,
+ .JobAssignment = { SPI_JOB_EEP_CMD,(-1)},
+ },
+ {
+ .SpiSequenceId = SPI_SEQ_EEP_CMD2, // The EEP read sequence
+ .SpiInterruptibleSequence = 0,
+ .SpiSeqEndNotification = SPI_SEQ_END_NOTIFICATION,
+ .JobAssignment = { SPI_JOB_EEP_CMD2,(-1)},
+ },
+ {
+ .SpiSequenceId = SPI_SEQ_EEP_READ, // The EEP read sequence
+ .SpiInterruptibleSequence = 0,
+ .SpiSeqEndNotification = SPI_SEQ_END_NOTIFICATION,
+ .JobAssignment = { SPI_JOB_EEP_DATA,(-1)},
+ },
+ {
+ .SpiSequenceId = SPI_SEQ_EEP_WRITE, // The EEP write sequence
+ .SpiInterruptibleSequence = 0,
+ .SpiSeqEndNotification = SPI_SEQ_END_NOTIFICATION,
+ .JobAssignment = { SPI_JOB_EEP_WREN,SPI_JOB_EEP_DATA,(-1)},
+ },
+
+ // -----------------------------------
+
+
+ {
+ .SpiSequenceId = SPI_SEQ_FLASH_CMD, // The EEP write sequence
+ .SpiInterruptibleSequence = 0,
+ .SpiSeqEndNotification = SPI_SEQ_END_NOTIFICATION,
+ .JobAssignment = { SPI_JOB_FLASH_CMD,(-1)},
+ },
+ {
+ .SpiSequenceId = SPI_SEQ_FLASH_CMD2, // The EEP read sequence
+ .SpiInterruptibleSequence = 0,
+ .SpiSeqEndNotification = SPI_SEQ_END_NOTIFICATION,
+ .JobAssignment = { SPI_JOB_FLASH_CMD2,(-1)},
+ },
+ {
+ .SpiSequenceId = SPI_SEQ_FLASH_CMD_DATA, // The EEP write sequence
+ .SpiInterruptibleSequence = 0,
+ .SpiSeqEndNotification = SPI_SEQ_END_NOTIFICATION,
+ .JobAssignment = { SPI_JOB_FLASH_CMD_DATA,(-1)},
+ },
+ {
+ .SpiSequenceId = SPI_SEQ_FLASH_READ, // The EEP write sequence
+ .SpiInterruptibleSequence = 0,
+ .SpiSeqEndNotification = SPI_SEQ_END_NOTIFICATION,
+ .JobAssignment = { SPI_JOB_FLASH_READ,(-1)},
+ },
+ {
+ .SpiSequenceId = SPI_SEQ_FLASH_WRITE, // The EEP write sequence
+ .SpiInterruptibleSequence = 0,
+ .SpiSeqEndNotification = SPI_SEQ_END_NOTIFICATION,
+ .JobAssignment = { SPI_JOB_FLASH_WREN,SPI_JOB_FLASH_DATA,SPI_JOB_FLASH_WRDI,(-1)},
+ },
+ {
+ .SpiSequenceId = SPI_SEQ_FLASH_WRSR, // The EEP write sequence
+ .SpiInterruptibleSequence = 0,
+ .SpiSeqEndNotification = SPI_SEQ_END_NOTIFICATION,
+ .JobAssignment = { SPI_JOB_FLASH_WREN,SPI_JOB_FLASH_WRSR,(-1)},
+ },
+ {
+ .SpiSequenceId = SPI_SEQ_FLASH_ERASE, // The EEP write sequence
+ .SpiInterruptibleSequence = 0,
+ .SpiSeqEndNotification = SPI_SEQ_END_NOTIFICATION,
+ .JobAssignment = { SPI_JOB_FLASH_WREN,SPI_JOB_FLASH_ADDR,SPI_JOB_FLASH_WRDI,(-1)},
+ },
+};
+
+/* JOBS */
+const Spi_JobConfigType SpiJobConfigData[] =
+{
+ {
+ .SpiJobId = SPI_JOB_E2_CMD, // The command job for EEP
+ .SpiHwUnit = DSPI_CTRL_A,
+ .SpiJobPriority = 3,
+ .SpiJobEndNotification = SPI_JOB_E2_CMD_END_NOTIFICATION,
+ .DeviceAssignment = SPI_EXT_DEVICE_A_E2,
+ .ChannelAssignment = { SPI_CH_E2_CMD ,(-1)},
+ },
+ {
+ .SpiJobId = SPI_JOB_E2_CMD2, // The command job for EEP
+ .SpiHwUnit = DSPI_CTRL_A,
+ .SpiJobPriority = 3,
+ .SpiJobEndNotification = SPI_JOB_E2_CMD2_END_NOTIFICATION,
+ .DeviceAssignment = SPI_EXT_DEVICE_A_E2,
+ .ChannelAssignment = { SPI_CH_E2_CMD ,SPI_CH_E2_DATA,(-1)},
+ },
+ {
+ .SpiJobId = SPI_JOB_E2_DATA, // The data job for EEP
+ .SpiHwUnit = DSPI_CTRL_A,
+ .SpiJobPriority = 2,
+ .SpiJobEndNotification = SPI_JOB_E2_DATA_END_NOTIFICATION,
+ .DeviceAssignment = SPI_EXT_DEVICE_A_E2,
+ .ChannelAssignment = { SPI_CH_E2_CMD, SPI_CH_E2_ADDR ,SPI_CH_E2_DATA,(-1)},
+ },
+ {
+ .SpiJobId = SPI_JOB_E2_WREN, // The data job for EEP
+ .SpiHwUnit = DSPI_CTRL_A,
+ .SpiJobPriority = 2,
+ .SpiJobEndNotification = SPI_JOB_E2_WREN_END_NOTIFICATION,
+ .DeviceAssignment = SPI_EXT_DEVICE_A_E2,
+ .ChannelAssignment = { SPI_CH_E2_WREN,(-1)},
+ },
+
+ // -----------------------------------
+
+ {
+ .SpiJobId = SPI_JOB_EEP_CMD, // The command job for EEP
+ .SpiHwUnit = DSPI_CTRL_B,
+ .SpiJobPriority = 3,
+ .SpiJobEndNotification = SPI_JOB_END_NOTIFICAITON,
+ .DeviceAssignment = SPI_EXT_DEVICE_B_E2,
+ .ChannelAssignment = { SPI_CH_EEP_CMD ,(-1)},
+ },
+ {
+ .SpiJobId = SPI_JOB_EEP_CMD2, // The command job for EEP
+ .SpiHwUnit = DSPI_CTRL_B,
+ .SpiJobPriority = 3,
+ .SpiJobEndNotification = SPI_JOB_END_NOTIFICAITON,
+ .DeviceAssignment = SPI_EXT_DEVICE_B_E2,
+ .ChannelAssignment = { SPI_CH_EEP_CMD ,SPI_CH_EEP_DATA,(-1)},
+ },
+ {
+ .SpiJobId = SPI_JOB_EEP_DATA, // The data job for EEP
+ .SpiHwUnit = DSPI_CTRL_B,
+ .SpiJobPriority = 2,
+ .SpiJobEndNotification = SPI_JOB_END_NOTIFICAITON,
+ .DeviceAssignment = SPI_EXT_DEVICE_B_E2,
+ .ChannelAssignment = { SPI_CH_EEP_CMD, SPI_CH_EEP_ADDR ,SPI_CH_EEP_DATA,(-1)},
+ },
+ {
+ .SpiJobId = SPI_JOB_EEP_WREN, // The data job for EEP
+ .SpiHwUnit = DSPI_CTRL_B,
+ .SpiJobPriority = 2,
+ .SpiJobEndNotification = SPI_JOB_END_NOTIFICAITON,
+ .DeviceAssignment = SPI_EXT_DEVICE_B_E2,
+ .ChannelAssignment = { SPI_CH_EEP_WREN,(-1)},
+ },
+
+
+ // -----------------------------------
+ // 8
+ {
+ .SpiJobId = SPI_JOB_FLASH_CMD, // The command job for EEP
+ .SpiHwUnit = DSPI_CTRL_A,
+ .SpiJobPriority = 3,
+ .SpiJobEndNotification = SPI_JOB_END_NOTIFICAITON,
+ .DeviceAssignment = SPI_EXT_DEVICE_A_FLASH,
+ .ChannelAssignment = { SPI_CH_FLASH_CMD ,(-1)},
+ },
+ {
+ .SpiJobId = SPI_JOB_FLASH_CMD2, // The command job for EEP
+ .SpiHwUnit = DSPI_CTRL_A,
+ .SpiJobPriority = 3,
+ .SpiJobEndNotification = SPI_JOB_END_NOTIFICAITON,
+ .DeviceAssignment = SPI_EXT_DEVICE_A_FLASH,
+ .ChannelAssignment = { SPI_CH_FLASH_CMD ,SPI_CH_FLASH_DATA, (-1)},
+ },
+ {
+ .SpiJobId = SPI_JOB_FLASH_CMD_DATA, // The data job for EEP
+ .SpiHwUnit = DSPI_CTRL_A,
+ .SpiJobPriority = 2,
+ .SpiJobEndNotification = SPI_JOB_END_NOTIFICAITON,
+ .DeviceAssignment = SPI_EXT_DEVICE_A_FLASH,
+ .ChannelAssignment = { SPI_CH_FLASH_CMD, SPI_CH_FLASH_DATA,(-1)},
+ },
+ {
+ .SpiJobId = SPI_JOB_FLASH_READ, // The data job for EEP
+ .SpiHwUnit = DSPI_CTRL_A,
+ .SpiJobPriority = 2,
+ .SpiJobEndNotification = SPI_JOB_END_NOTIFICAITON,
+ .DeviceAssignment = SPI_EXT_DEVICE_A_FLASH,
+ .ChannelAssignment = { SPI_CH_FLASH_CMD, SPI_CH_FLASH_ADDR, SPI_CH_FLASH_DATA,(-1)},
+ },
+ {
+ .SpiJobId = SPI_JOB_FLASH_WREN,
+ .SpiHwUnit = DSPI_CTRL_A,
+ .SpiJobPriority = 2,
+ .SpiJobEndNotification = SPI_JOB_END_NOTIFICAITON,
+ .DeviceAssignment = SPI_EXT_DEVICE_A_FLASH,
+ .ChannelAssignment = { SPI_CH_FLASH_WREN,(-1)},
+ },
+ {
+ .SpiJobId = SPI_JOB_FLASH_WRDI,
+ .SpiHwUnit = DSPI_CTRL_A,
+ .SpiJobPriority = 2,
+ .SpiJobEndNotification = SPI_JOB_END_NOTIFICAITON,
+ .DeviceAssignment = SPI_EXT_DEVICE_A_FLASH,
+ .ChannelAssignment = { SPI_CH_FLASH_WRDI,(-1)},
+ },
+ {
+ .SpiJobId = SPI_JOB_FLASH_DATA,
+ .SpiHwUnit = DSPI_CTRL_A,
+ .SpiJobPriority = 2,
+ .SpiJobEndNotification = 0,
+ .DeviceAssignment = SPI_EXT_DEVICE_A_FLASH,
+ .ChannelAssignment = { SPI_CH_FLASH_CMD, SPI_CH_FLASH_ADDR ,SPI_CH_FLASH_DATA,(-1)},
+ },
+ {
+ .SpiJobId = SPI_JOB_FLASH_WRSR,
+ .SpiHwUnit = DSPI_CTRL_A,
+ .SpiJobPriority = 2,
+ .SpiJobEndNotification = 0,
+ .DeviceAssignment = SPI_EXT_DEVICE_A_FLASH,
+ .ChannelAssignment = { SPI_CH_FLASH_WRSR, SPI_CH_FLASH_DATA ,(-1)},
+ },
+ {
+ .SpiJobId = SPI_JOB_FLASH_ADDR,
+ .SpiHwUnit = DSPI_CTRL_A,
+ .SpiJobPriority = 2,
+ .SpiJobEndNotification = 0,
+ .DeviceAssignment = SPI_EXT_DEVICE_A_FLASH,
+ .ChannelAssignment = { SPI_CH_FLASH_CMD, SPI_CH_FLASH_ADDR,(-1)},
+ },
+};
+
+uint32 Spi_GetJobCnt(void ) { return sizeof(SpiJobConfigData)/sizeof(SpiJobConfigData[0]); }
+
+
+/* CHANNELS */
+const Spi_ChannelConfigType SpiChannelConfigData[] =
+{
+ {
+ .SpiChannelId = SPI_CH_E2_CMD,
+ .SpiChannelType = SPI_EB,
+ .SpiDataWidth = 8,
+ .SpiIbNBuffers = 0,
+ .SpiEbMaxLength = SPI_EB_MAX_LENGTH,
+ .SpiDefaultData = 0x00,
+ .SpiDmaNoIncreaseSrc = 0,
+ },
+ {
+ .SpiChannelId = SPI_CH_E2_ADDR,
+ .SpiChannelType = SPI_EB,
+ .SpiDataWidth = 16,
+ .SpiIbNBuffers = 0,
+ .SpiEbMaxLength = SPI_EB_MAX_LENGTH,
+ .SpiDefaultData = 0x0000,
+ .SpiDmaNoIncreaseSrc = 0,
+ },
+ {
+ .SpiChannelId = SPI_CH_E2_WREN,
+ .SpiChannelType = SPI_EB,
+ .SpiDataWidth = 8,
+ .SpiIbNBuffers = 0,
+ .SpiEbMaxLength = SPI_EB_MAX_LENGTH,
+ .SpiDefaultData = 0x00,
+ .SpiDmaNoIncreaseSrc = 0,
+ },
+
+ {
+ .SpiChannelId = SPI_CH_E2_DATA,
+ .SpiChannelType = SPI_EB,
+ .SpiDataWidth = 8,
+ .SpiIbNBuffers = 0,
+ .SpiEbMaxLength = SPI_EB_MAX_LENGTH,
+ .SpiDefaultData = 0x00,
+ .SpiDmaNoIncreaseSrc = 0,
+ },
+
+ // -----------------------------------
+
+ {
+ .SpiChannelId = SPI_CH_EEP_CMD,
+ .SpiChannelType = SPI_EB,
+ .SpiDataWidth = 8,
+ .SpiIbNBuffers = 0,
+ .SpiEbMaxLength = SPI_EB_MAX_LENGTH,
+ .SpiDefaultData = 0x00,
+ .SpiDmaNoIncreaseSrc = 0,
+ },
+ {
+ .SpiChannelId = SPI_CH_EEP_ADDR,
+ .SpiChannelType = SPI_EB,
+ .SpiDataWidth = 16,
+ .SpiIbNBuffers = 0,
+ .SpiEbMaxLength = SPI_EB_MAX_LENGTH,
+ .SpiDefaultData = 0x0000,
+ .SpiDmaNoIncreaseSrc = 0,
+ },
+ {
+ .SpiChannelId = SPI_CH_EEP_WREN,
+ .SpiChannelType = SPI_EB,
+ .SpiDataWidth = 8,
+ .SpiIbNBuffers = 0,
+ .SpiEbMaxLength = 1,
+ .SpiDefaultData = E2_WREN,
+ .SpiDmaNoIncreaseSrc = 0,
+ },
+
+ {
+ .SpiChannelId = SPI_CH_EEP_DATA,
+ .SpiChannelType = SPI_EB,
+ .SpiDataWidth = 8,
+ .SpiIbNBuffers = 0,
+ .SpiEbMaxLength = SPI_EB_MAX_LENGTH,
+ .SpiDefaultData = 0x00,
+ .SpiDmaNoIncreaseSrc = 0,
+ },
+
+ // -----------------------------------
+
+ {
+ .SpiChannelId = SPI_CH_FLASH_CMD,
+ .SpiChannelType = SPI_EB,
+ .SpiDataWidth = 8,
+ .SpiIbNBuffers = 0,
+ .SpiEbMaxLength = SPI_EB_MAX_LENGTH,
+ .SpiDefaultData = 0x00,
+ .SpiDmaNoIncreaseSrc = 0,
+ },
+ {
+ .SpiChannelId = SPI_CH_FLASH_ADDR,
+ .SpiChannelType = SPI_EB,
+ .SpiDataWidth = 8,
+ .SpiIbNBuffers = 0,
+ .SpiEbMaxLength = SPI_EB_MAX_LENGTH,
+ .SpiDefaultData = 0x0000,
+ .SpiDmaNoIncreaseSrc = 0,
+ },
+ {
+ .SpiChannelId = SPI_CH_FLASH_DATA,
+ .SpiChannelType = SPI_EB,
+ .SpiDataWidth = 8,
+ .SpiIbNBuffers = 0,
+ .SpiEbMaxLength = SPI_EB_MAX_LENGTH,
+ .SpiDefaultData = 0x00,
+ .SpiDmaNoIncreaseSrc = 0,
+ },
+ {
+ .SpiChannelId = SPI_CH_FLASH_WREN,
+ .SpiChannelType = SPI_EB,
+ .SpiDataWidth = 8,
+ .SpiIbNBuffers = 0,
+ .SpiEbMaxLength = 1,
+ .SpiDefaultData = FLASH_WREN,
+ .SpiDmaNoIncreaseSrc = 0,
+ },
+ {
+ .SpiChannelId = SPI_CH_FLASH_WRDI,
+ .SpiChannelType = SPI_EB,
+ .SpiDataWidth = 8,
+ .SpiIbNBuffers = 0,
+ .SpiEbMaxLength = 1,
+ .SpiDefaultData = FLASH_WRDI,
+ .SpiDmaNoIncreaseSrc = 0,
+ },
+ {
+ .SpiChannelId = SPI_CH_FLASH_WRSR,
+ .SpiChannelType = SPI_EB,
+ .SpiDataWidth = 8,
+ .SpiIbNBuffers = 0,
+ .SpiEbMaxLength = 1,
+ .SpiDefaultData = FLASH_WRSR,
+ .SpiDmaNoIncreaseSrc = 0,
+ },
+
+ {
+ .SpiChannelId = (-1),
+ }
+};
+
+uint32 Spi_GetChanneCnt(void ) { return sizeof(SpiChannelConfigData)/sizeof(SpiChannelConfigData[0]); }
+
+const Spi_ExternalDeviceType SpiExternalConfigData[] =
+{
+ // SPI_EXT_DEVICE_A_E2
+
+ // E2
+ {
+ .SpiBaudrate = 1000000UL,
+ .SpiCsIdentifier = SPI_A_CS_E2,
+ .SpiCsPolarity = STD_LOW,
+ .SpiDataShiftEdge = SPI_EDGE_LEADING,
+ .SpiEnableCs = 1,
+ .SpiShiftClockIdleLevel = STD_LOW,
+ .SpiTimeClk2Cs = 606, // ns
+ .SpiTimeCs2Clk = 606, // ns
+ },
+ // SPI_EXT_DEVICE_A_FLASH
+ {
+ .SpiBaudrate = 1000000UL,
+ .SpiCsIdentifier = SPI_A_CS_FLASH,
+ .SpiCsPolarity = STD_LOW,
+ .SpiDataShiftEdge = SPI_EDGE_LEADING,
+ .SpiEnableCs = 1,
+ .SpiShiftClockIdleLevel = STD_LOW,
+ .SpiTimeClk2Cs = 606, // ns
+ .SpiTimeCs2Clk = 606, // ns
+ },
+
+ //
+ // SPI_BUS_B
+ //
+
+ // SPI_EXT_DEVICE_B_E2
+ {
+ .SpiBaudrate = 1000000UL,
+ .SpiCsIdentifier = SPI_B_CS_E2,
+ .SpiCsPolarity = STD_LOW,
+ .SpiDataShiftEdge = SPI_EDGE_LEADING,
+ .SpiEnableCs = 1,
+ .SpiShiftClockIdleLevel = STD_LOW,
+ .SpiTimeClk2Cs = 0,
+ .SpiTimeCs2Clk = 0,
+ },
+};
+
+uint32 Spi_GetExternalDeviceCnt(void ) { return sizeof(SpiExternalConfigData)/sizeof(SpiExternalConfigData[0]); }
+
+const Spi_HwConfigType SpiHwConfig[] =
+{
+ {
+ .IsrPriority = 1,
+ .Activated = TRUE,
+ .RxDmaChannel = DMA_DSPI_A_RESULT_CHANNEL,
+ .TxDmaChannel = DMA_DSPI_A_COMMAND_CHANNEL,
+ .PeripheralClock = PERIPHERAL_CLOCK_DSPI_A,
+ },
+ {
+ .IsrPriority = 1,
+ .Activated = TRUE,
+ .RxDmaChannel = DMA_DSPI_B_RESULT_CHANNEL,
+ .TxDmaChannel = DMA_DSPI_B_COMMAND_CHANNEL,
+ .PeripheralClock = PERIPHERAL_CLOCK_DSPI_B,
+ },
+ {
+ .IsrPriority = 1,
+ .Activated = FALSE,
+ .RxDmaChannel = 0,
+ .TxDmaChannel = 0,
+ .PeripheralClock = 0,
+ },
+ {
+ .IsrPriority = 1,
+ .Activated = TRUE,
+ .RxDmaChannel = 0,
+ .TxDmaChannel = 0,
+ .PeripheralClock = 0,
+ },
+};
+
+const Spi_DriverType SpiConfigData =
+{
+ .SpiMaxChannel = SPI_MAX_CHANNEL,
+ .SpiMaxJob = SPI_MAX_JOB,
+ .SpiMaxSequence = SPI_MAX_SEQUENCE,
+ .SpiChannelConfig = &SpiChannelConfigData[0],
+ .SpiSequenceConfig = &SpiSequenceConfigData[0],
+ .SpiJobConfig = &SpiJobConfigData[0],
+ .SpiExternalDevice = &SpiExternalConfigData[0],
+ .SpiHwConfig = &SpiHwConfig[0],
+};
+
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+\r
+#include <sys/stat.h>\r
+#include <sys/types.h>\r
+#include <errno.h>\r
+#include <stdlib.h>\r
+//#include "clibsupport_gcc.h"\r
+
+#if defined(CFG_ARM)
+#define open _open
+#define exit _exit
+#define fstat _fstat
+#define getpid _getpid
+#define kill _kill
+#define close _close
+#define isatty _isatty
+#define sbrk _sbrk
+#define read _read
+#define write _write
+#define lseek _lseek
+#endif
+\r
+// Operation on Winidea terminal buffer\r
+#define TWBUFF_SIZE 0x100\r
+#define TRBUFF_SIZE 0x100\r
+\r
+#define TBUFF_PTR 2\r
+\r
+#define TWBUFF_LEN (TWBUFF_SIZE+TBUFF_PTR)\r
+#define TRBUFF_LEN (TRBUFF_SIZE+TBUFF_PTR)\r
+#define TWBUFF_TPTR (g_TWBuffer[TWBUFF_SIZE+0])\r
+#define TWBUFF_CPTR (g_TWBuffer[TWBUFF_SIZE+1])\r
+#define TWBUFF_INC(n) ((n + 1)&(TWBUFF_SIZE-1))\r
+#define TWBUFF_FULL() (TWBUFF_TPTR==((TWBUFF_CPTR-1)&(TWBUFF_SIZE-1)))\r
+\r
+#ifdef USE_WINIDEA_TERM\r
+static volatile unsigned char g_TWBuffer[TWBUFF_LEN] __attribute__ ((aligned (0x100))); // Transmit to WinIDEA terminal\r
+static volatile unsigned char g_TRBuffer[TRBUFF_LEN] __attribute__ ((aligned (0x100)));\r
+static volatile char g_TConn __attribute__ ((section (".winidea_port")));\r
+#endif\r
+
+#define FILE_RAMLOG 3
+\r
+/*\r
+ * T32 stuff\r
+ */\r
+
+// This must be in un-cached space....\r
+static volatile char t32_outport __attribute__ ((section (".t32_outport")));\r
+\r
+\r
+int arc_putchar(int c) {\r
+ char cc = c;\r
+ write( 1,&cc,1);\r
+\r
+ return 0;\r
+}\r
+\r
+void t32_writebyte(char c)\r
+{
+ /* T32 can hang here for several reasons;
+ * - term.view e:address.offset(v.address(t32_outport)) e:0\r
+ */\r
+\r
+ while (t32_outport != 0 ) ; /* wait until port is free */\r
+ t32_outport = c; /* send character */\r
+}\r
+\r
+/*\r
+ * clib support\r
+ */\r
+\r
+/* Do nothing */\r
+int close( int fd ) {\r
+ (void)fd;\r
+ return (-1);\r
+}\r
+\r
+char *__env[1] = { 0 };\r
+char **environ = __env;\r
+\r
+\r
+#include <errno.h>\r
+#undef errno\r
+extern int errno;\r
+\r
+int execve(char *name, char **argv, char **env){\r
+ (void)name;\r
+ (void)argv;\r
+ (void)env;\r
+ errno=ENOMEM;\r
+ return -1;\r
+}\r
+\r
+int fork() {\r
+ errno=EAGAIN;\r
+ return -1;\r
+}\r
+\r
+#include <sys/stat.h>\r
+int fstat(int file, struct stat *st) {\r
+ (void)file;\r
+ st->st_mode = S_IFCHR;\r
+ return 0;\r
+}\r
+\r
+/* Returns 1 if connected to a terminal. T32 can be a terminal\r
+ */\r
+\r
+int isatty( int fd )\r
+{\r
+ (void)fd;\r
+ return 1;\r
+}\r
+\r
+/*\r
+int fstat( int fd, struct stat *buf )\r
+{\r
+ buf->st_mode = S_IFCHR;\r
+ buf->st_blksize = 0;\r
+\r
+ return (0);\r
+}\r
+*/\r
+\r
+/* reposition read/write file offset\r
+ * We can't seek, return error.*/\r
+off_t lseek( int fd, off_t offset,int whence)\r
+{\r
+ (void)fd;\r
+ (void)offset;\r
+ (void)whence;\r
+\r
+ errno = ESPIPE;\r
+ return ((off_t)-1);\r
+}\r
+\r
+int open(const char *name, int flags, int mode){\r
+ (void)name;\r
+ (void)flags;\r
+ (void)mode;\r
+\r
+ if( strcmp(name,"ramlog") == 0 ) {\r
+ return FILE_RAMLOG;\r
+ }\r
+\r
+ return -1;\r
+}\r
+\r
+int read( int fd, char *buf, int nbytes )\r
+{\r
+ (void)fd;\r
+ (void)buf;\r
+ (void)nbytes;\r
+#ifdef USE_WINIDEA_TERM\r
+ (void)g_TRBuffer[0];\r
+#endif\r
+\r
+ /* Only support write for now, return 0 read */\r
+ return 0;\r
+}\r
+\r
+\r
+int write( int fd, char *buf, int nbytes)\r
+{\r
+ //(void)fd; // Normally 0- ?, 1-stdout, 2-stderr,\r
+ // Added 3-ramlog,\r
+\r
+ if( fd < 3 ) {\r
+#ifdef USE_WINIDEA_TERM\r
+ if (g_TConn)\r
+ {\r
+ unsigned char nCnt,nLen;\r
+ for(nCnt=0; nCnt<nbytes; nCnt++)\r
+ {\r
+ while(TWBUFF_FULL());\r
+ nLen=TWBUFF_TPTR;\r
+ g_TWBuffer[nLen]=buf[nCnt];\r
+ nLen=TWBUFF_INC(nLen);\r
+ TWBUFF_TPTR=nLen;\r
+ }\r
+ }\r
+#endif\r
+\r
+#ifdef USE_T32_TERM\r
+ for (int i = 0; i < nbytes; i++) {\r
+ if (*(buf + i) == '\n') {\r
+ t32_writebyte ('\r');\r
+// t32_writebyte ('\n');\r
+ }\r
+ t32_writebyte (*(buf + i));\r
+ }\r
+#endif
+#ifdef USE_ARM_ITM_TERM
+ for (int i = 0; i < nbytes; i++) {
+ ITM_SendChar(*(buf + i));
+ }
+#endif
+
+ }\r
+ else\r
+ {
+ /* RAMLOG support */\r
+ if(fd == FILE_RAMLOG) {\r
+ for (int i = 0; i < nbytes; i++) {\r
+ ramlog_chr (*(buf + i));\r
+ }\r
+ }\r
+ }\r
+\r
+ return (nbytes);\r
+}\r
+\r
+/* If we use malloc and it runs out of memory it calls sbrk()\r
+ */\r
+#if 1\r
+\r
+extern char _end[];\r
+\r
+//static char *curbrk = _end;\r
+\r
+#define HEAPSIZE 16000\r
+unsigned char _heap[HEAPSIZE];\r
+\r
+caddr_t sbrk( int incr )\r
+{\r
+ static unsigned char *heap_end;\r
+ unsigned char *prev_heap_end;\r
+\r
+/* initialize */\r
+ if( heap_end == 0 )\r
+ heap_end = _heap;\r
+\r
+ prev_heap_end = heap_end;\r
+\r
+ if( heap_end + incr - _heap > HEAPSIZE ) {\r
+ /* heap overflow - announce on stderr */\r
+ write( 2, "Heap overflow!\n", 15 );\r
+ abort();\r
+ }\r
+\r
+ heap_end += incr;\r
+\r
+ return (caddr_t) prev_heap_end;\r
+}\r
+#else\r
+void *sbrk(int inc )\r
+{\r
+ /* We use our own malloc */\r
+ return (void *)(-1);\r
+}\r
+#endif\r
+\r
+int stat( const char *file, struct stat *st ) {\r
+//int stat(char *file, struct stat *st) {\r
+ (void)file;\r
+ st->st_mode = S_IFCHR;\r
+ return 0;\r
+}\r
+\r
+\r
+int getpid() {\r
+ return 1;\r
+}\r
+\r
+#include <errno.h>\r
+#undef errno\r
+extern int errno;\r
+int kill(int pid, int sig){\r
+ (void)pid;\r
+ (void)sig;\r
+ errno=EINVAL;\r
+ return(-1);\r
+}\r
+\r
+\r
+/* Should not really be here, but .. */\r
+\r
+void _fini( void )\r
+{\r
+\r
+}\r
+\r
+\r
+void __init( void )\r
+{\r
+\r
+}\r
+#if defined(CFG_ARM)\r
+void _exit( int status ) {\r
+ while(1);\r
+}\r
+#endif\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+
+//#include <stdio.h>
+#include <stdlib.h>
+#include <stdarg.h>
+
+#define BUF_SIZE 60
+
+#if 0
+//char *
+int dbg_printf(const char *fmt, ...) {
+ /* Guess we need no more than 100 bytes. */
+ int n;
+ va_list ap;
+ char p[BUF_SIZE];
+
+ /* Try to print in the allocated space. */
+ va_start(ap, fmt);
+ n = vsnprintf (p, BUF_SIZE, fmt, ap);
+ puts(p);
+ va_end(ap);
+ return 0;
+}
+
+#endif
+/*
+ Copyright 2001, 2002 Georges Menie (www.menie.org)
+ stdarg version contributed by Christian Ettinger
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU Lesser General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+*/
+
+
+/*
+ putchar is the only external dependency for this file,
+ if you have a working putchar, leave it commented out.
+ If not, uncomment the define below and
+ replace outbyte(c) by your own function call.
+
+#define putchar(c) outbyte(c)
+*/
+
+// newlib std function
+extern int putchar(int c);
+
+extern int arc_putchar(int c);
+
+static void printchar(char **str, int c)
+{
+ if (str) {
+ **str = c;
+ ++(*str);
+ }
+ else {
+ (void)arc_putchar(c);
+ }
+}
+
+#define PAD_RIGHT 1
+#define PAD_ZERO 2
+
+static int prints(char **out, const char *string, int width, int pad)
+{
+ register int pc = 0, padchar = ' ';
+
+ if (width > 0) {
+ register int len = 0;
+ register const char *ptr;
+ for (ptr = string; *ptr; ++ptr) ++len;
+ if (len >= width) width = 0;
+ else width -= len;
+ if (pad & PAD_ZERO) padchar = '0';
+ }
+ if (!(pad & PAD_RIGHT)) {
+ for ( ; width > 0; --width) {
+ printchar (out, padchar);
+ ++pc;
+ }
+ }
+ for ( ; *string ; ++string) {
+ printchar (out, *string);
+ ++pc;
+ }
+ for ( ; width > 0; --width) {
+ printchar (out, padchar);
+ ++pc;
+ }
+
+ return pc;
+}
+
+
+
+/* the following should be enough for 32 bit int */
+#define PRINT_BUF_LEN 12
+
+static int printi(char **out, int i, int b, int sg, int width, int pad, int letbase)
+{
+ char print_buf[PRINT_BUF_LEN];
+ register char *s;
+ register int t, neg = 0, pc = 0;
+ register unsigned int u = i;
+
+ if (i == 0) {
+ print_buf[0] = '0';
+ print_buf[1] = '\0';
+ return prints (out, print_buf, width, pad);
+ }
+
+ if (sg && b == 10 && i < 0) {
+ neg = 1;
+ u = -i;
+ }
+
+ s = print_buf + PRINT_BUF_LEN-1;
+ *s = '\0';
+
+ while (u) {
+ t = u % b;
+ if( t >= 10 )
+ t += letbase - '0' - 10;
+ *--s = t + '0';
+ u /= b;
+ }
+
+ if (neg) {
+ if( width && (pad & PAD_ZERO) ) {
+ printchar (out, '-');
+ ++pc;
+ --width;
+ }
+ else {
+ *--s = '-';
+ }
+ }
+
+ return pc + prints (out, s, width, pad);
+}
+
+static int print(char **out, const char *format, va_list args )
+{
+ int width, pad;
+ int pc = 0;
+ char scr[2];
+
+ for (; *format != 0; ++format) {
+ if (*format == '%') {
+ ++format;
+ width = pad = 0;
+ if (*format == '\0') break;
+ if (*format == '%') goto out;
+ if (*format == '-') {
+ ++format;
+ pad = PAD_RIGHT;
+ }
+ while (*format == '0') {
+ ++format;
+ pad |= PAD_ZERO;
+ }
+ for ( ; *format >= '0' && *format <= '9'; ++format) {
+ width *= 10;
+ width += *format - '0';
+ }
+ if( *format == 's' ) {
+ char *s = (char *)va_arg( args, int );
+ pc += prints (out, s?s:"(null)", width, pad);
+ continue;
+ }
+ if( *format == 'd' ) {
+ pc += printi (out, va_arg( args, int ), 10, 1, width, pad, 'a');
+ continue;
+ }
+ if( *format == 'x' ) {
+ pc += printi (out, va_arg( args, int ), 16, 0, width, pad, 'a');
+ continue;
+ }
+ if( *format == 'X' ) {
+ pc += printi (out, va_arg( args, int ), 16, 0, width, pad, 'A');
+ continue;
+ }
+ if( *format == 'u' ) {
+ pc += printi (out, va_arg( args, int ), 10, 0, width, pad, 'a');
+ continue;
+ }
+ if( *format == 'c' ) {
+ /* char are converted to int then pushed on the stack */
+ scr[0] = (char)va_arg( args, int );
+ scr[1] = '\0';
+ pc += prints (out, scr, width, pad);
+ continue;
+ }
+ }
+ else {
+ out:
+ printchar (out, *format);
+ ++pc;
+ }
+ }
+ if (out) **out = '\0';
+ va_end( args );
+ return pc;
+}
+
+int simple_printf(const char *format, ...)
+{
+ va_list args;
+
+ va_start( args, format );
+ return print( 0, format, args );
+}
+
+#if 0
+int arc_fprintf(FILE *fd, const char *format, ...);
+int arc_vfprintf(FILE *fp, const char *fmt, va_list list);
+#endif
+
+
+#if 0
+int simple_fprintf(FILE *fd, const char *format, ...)
+{
+ va_list args;
+
+ va_start( args, format );
+ return fprint( &fd, format, args );
+}
+#endif
+
+int simple_sprintf(char *out, const char *format, ...)
+{
+ va_list args;
+
+ va_start( args, format );
+ return print( &out, format, args );
+}
+
+#ifdef TEST_PRINTF
+int main(void)
+{
+ char *ptr = "Hello world!";
+ char *np = 0;
+ int i = 5;
+ unsigned int bs = sizeof(int)*8;
+ int mi;
+ char buf[80];
+
+ mi = (1 << (bs-1)) + 1;
+dbg_printf("%s\n", ptr);
+dbg_printf("printf test\n");
+dbg_printf("%s is null pointer\n", np);
+dbg_printf("%d = 5\n", i);
+dbg_printf("%d = - max int\n", mi);
+dbg_printf("char %c = 'a'\n", 'a');
+dbg_printf("hex %x = ff\n", 0xff);
+dbg_printf("hex %02x = 00\n", 0);
+dbg_printf("signed %d = unsigned %u = hex %x\n", -3, -3, -3);
+dbg_printf("%d %s(s)%", 0, "message");
+dbg_printf("\n");
+dbg_printf("%d %s(s) with %%\n", 0, "message");
+ sprintf(buf, "justif: \"%-10s\"\n", "left");dbg_printf("%s", buf);
+ sprintf(buf, "justif: \"%10s\"\n", "right");dbg_printf("%s", buf);
+ sprintf(buf, " 3: %04d zero padded\n", 3);dbg_printf("%s", buf);
+ sprintf(buf, " 3: %-4d left justif.\n", 3);dbg_printf("%s", buf);
+ sprintf(buf, " 3: %4d right justif.\n", 3);dbg_printf("%s", buf);
+ sprintf(buf, "-3: %04d zero padded\n", -3);dbg_printf("%s", buf);
+ sprintf(buf, "-3: %-4d left justif.\n", -3);dbg_printf("%s", buf);
+ sprintf(buf, "-3: %4d right justif.\n", -3);dbg_printf("%s", buf);
+
+ return 0;
+}
+
+/*
+ * if you compile this file with
+ * gcc -Wall $(YOUR_C_OPTIONS) -DTEST_PRINTF -cdbg_printf.c
+ * you will get a normal warning:
+ * dbg_printf.c:214: warning: spurious trailing `%' in format
+ * this line is testing an invalid % at the end of the format string.
+ *
+ * this should display (on 32bit int machine) :
+ *
+ * Hello world!
+ *dbg_printf test
+ * (null) is null pointer
+ * 5 = 5
+ * -2147483647 = - max int
+ * char a = 'a'
+ * hex ff = ff
+ * hex 00 = 00
+ * signed -3 = unsigned 4294967293 = hex fffffffd
+ * 0 message(s)
+ * 0 message(s) with %
+ * justif: "left "
+ * justif: " right"
+ * 3: 0003 zero padded
+ * 3: 3 left justif.
+ * 3: 3 right justif.
+ * -3: -003 zero padded
+ * -3: -3 left justif.
+ * -3: -3 right justif.
+ */
+
+#endif
+
+
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+#include <stdio.h>\r
+#include <stdarg.h>\r
+\r
+extern int simple_sprintf(char *, const char *format, ...);\r
+\r
+#define CONFIG_RAMLOG_SIZE 2000\r
+\r
+static unsigned char ramlog[CONFIG_RAMLOG_SIZE] __attribute__ ((section (".ramlog")));\r
+static unsigned ramlog_curr __attribute__ ((section (".ramlog")));\r
+static unsigned ramlog_session __attribute__ ((section (".ramlog")));\r
+\r
+static FILE *ramlogFile = 0;\r
+\r
+\r
+void ramlog_chr( char c ) {\r
+ ramlog[ramlog_curr++] = c;\r
+ if( ramlog_curr >= 2000 ) {\r
+ ramlog_curr = 0;\r
+ }\r
+}\r
+\r
+void ramlog_puts( char *str ) {\r
+\r
+ while(*str!=0) {\r
+ ramlog_chr(*str++);\r
+ }\r
+ ramlog_chr('\n');\r
+}\r
+\r
+void ramlog_printf( const char *format, ... ) {\r
+\r
+ // Fast and ugly ramlog support.\r
+ volatile int rv;\r
+ va_list args;\r
+ va_start(args,format);\r
+\r
+ rv = vfprintf(ramlogFile,format, args);\r
+ va_end(args);\r
+}\r
+\r
+void ramlog_init()\r
+{\r
+ char buf[32];\r
+ if( ramlog_curr>CONFIG_RAMLOG_SIZE)\r
+ {\r
+ ramlog_curr = 0;\r
+ ramlog_session = 0;\r
+ }\r
+\r
+ ramlogFile = fopen("ramlog","a");\r
+\r
+ ramlog_session++;\r
+\r
+ simple_sprintf(buf, "Session (%d)\n", ramlog_session);\r
+ ramlog_puts(buf);\r
+}\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*\r
+ * strace.c\r
+ *\r
+ * Created on: 2009-apr-19\r
+ * Author: mahi\r
+ *\r
+ * System trace...\r
+ * Idea to trace\r
+ *\r
+ *\r
+ * Inspiration:\r
+ * http://ltt.polymtl.ca/tracingwiki/index.php/TracingBook\r
+ * http://developer.apple.com/tools/performance/optimizingwithsystemtrace.html\r
+ * http://benno.id.au/docs/lttng_data_format.pml\r
+ */\r
+\r
+/*\r
+ * Channel\r
+ *\r
+ * ISR\r
+ * TASK\r
+ *
+ */\r
+\r
+typedef enum {\r
+ STRACE_CH_ISR = 1,\r
+ STRACE_CH_TASK = (1<<1),\r
+ STRACE_CH_KERNEL = (1<<2),\r
+} strace_ch_t;\r
+\r
+typedef enum {\r
+ STRACE_EV_ISR_START,\r
+ STRACE_EV_ISR_STOP,\r
+ STRACE_EV_TASK_START,\r
+ STRACE_EV_TASK_STOP,\r
+} strace_ev_t;\r
+\r
+\r
+struct strace_attr_s {\r
+ strace_ch_t\r
+ /* A timestamp in some unit */\r
+ uint32_t timestamp;\r
+};\r
+\r
+\r
+/**\r
+ *
+ * @param ch channel to record
+ */\r
+void strace( strace_ev_t event) {\r
+ switch( ch ) {\r
+ case STRACE_CH_ISR:\r
+ break;\r
+ case STRACE_CH_TASK:\r
+ break;\r
+ }\r
+}\r
+\r
+/**\r
+ * Channels to use.
+ */\r
+void strace_init( strace_ch_t ch ) {\r
+\r
+}\r
+\r
+void strace_print( void ) {\r
+\r
+}\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+#include <stdlib.h>\r
+/**\r
+ * Ansi C "itoa" based on Kernighan & Ritchie's "Ansi C"\r
+ * with slight modification to optimize for specific architecture:\r
+ */\r
+\r
+void strreverse(char* begin, char* end) {\r
+\r
+ char aux;\r
+\r
+ while (end > begin) {\r
+ aux = *end, *end-- = *begin, *begin++ = aux;\r
+ }\r
+}\r
+\r
+\r
+// int to string\r
+void xtoa(unsigned long val, char* str, int base,int negative) {\r
+ static char num[] = "0123456789abcdefghijklmnopqrstuvwxyz";\r
+ char* wstr = str;\r
+ int value = (int)val;\r
+\r
+ div_t res;\r
+\r
+ // Validate base\r
+ if (base < 2 || base > 35) {\r
+ *wstr = '\0';\r
+ return;\r
+ }\r
+\r
+ // Check sign\r
+ if ( negative ) {\r
+ value = -value;\r
+ }\r
+\r
+ do {\r
+ res = div(value, base);\r
+ *wstr++ = num[res.rem];\r
+ } while ((value = res.quot));\r
+\r
+ if (negative)\r
+ *wstr++ = '-';\r
+\r
+ *wstr = '\0';\r
+\r
+ // Reverse string\r
+ strreverse(str, wstr - 1);\r
+}\r
+\r
+\r
+// unsigned long to string\r
+void ultoa(unsigned long value, char* str, int base) {\r
+ xtoa(value,str,base,0);\r
+}\r
+\r
+// int to string\r
+void itoa(int value, char* str, int base) {\r
+ xtoa(value,str,base,(value<0));\r
+}\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include <stdlib.h>\r
+//#include <stdio.h>\r
+#include <string.h>\r
+#include "Com.h"\r
+#include "Com_Types.h"\r
+#include "Trace.h"\r
+\r
+#ifdef COM_DEV_ERROR_DETECT\r
+#include "Det.h"\r
+#endif\r
+\r
+const Com_ConfigType * ComConfig;\r
+\r
+ComEcoreIPdu_type ComEcoreIPdu[COM_MAX_NR_IPDU];\r
+ComEcoreSignal_type ComEcoreSignal[COM_MAX_NR_SIGNAL];\r
+ComEcoreGroupSignal_type ComEcoreGroupSignal[COM_MAX_NR_GROUPSIGNAL];\r
+\r
+ComEcoreConfig_type ComEcoreConfig = {\r
+ .ComIPdu = ComEcoreIPdu,\r
+ .ComSignal = ComEcoreSignal,\r
+ .ComGroupSignal = ComEcoreGroupSignal\r
+};\r
+\r
+\r
+void Com_Init(const Com_ConfigType *config ) {\r
+ DEBUG(DEBUG_LOW, "--Initialization of COM--\n");\r
+\r
+ ComConfig = config;\r
+\r
+ uint8 failure = 0;\r
+\r
+ uint32 earliestDeadline;\r
+ uint32 firstTimeout;\r
+\r
+ ComEcoreConfig.OutgoingPdu.SduDataPtr = malloc(8);\r
+\r
+ // Initialize each IPdu\r
+ //ComIPdu_type *IPdu;\r
+ //ComEcoreIPdu_type *EcoreIPdu;\r
+ const ComSignal_type *Signal;\r
+ const ComGroupSignal_type *GroupSignal;\r
+ for (int i = 0; !ComConfig->ComIPdu[i].ComEcoreEOL; i++) {\r
+ ComEcoreConfig.ComNIPdu++;\r
+\r
+ ComGetIPdu(i);\r
+ ComGetEcoreIPdu(i);\r
+\r
+ if (i >= COM_MAX_NR_IPDU) {\r
+ DET_REPORTERROR(COM_MODULE_ID, COM_INSTANCE_ID, 0x01, COM_E_TOO_MANY_IPDU);\r
+ failure = 1;\r
+ break;\r
+ }\r
+\r
+ // If this is a TX and cyclic IPdu, configure the first deadline.\r
+ if (IPdu->ComIPduDirection == SEND &&\r
+ (IPdu->ComTxIPdu.ComTxModeTrue.ComTxModeMode == PERIODIC || IPdu->ComTxIPdu.ComTxModeTrue.ComTxModeMode == MIXED)) {\r
+ //IPdu->ComEcoreTxIPduTimers.ComTxModeTimePeriodTimer = IPdu->ComTxIPdu.ComTxModeTrue.ComTxModeTimeOffsetFactor;\r
+ EcoreIPdu->ComEcoreTxIPduTimers.ComTxModeTimePeriodTimer = IPdu->ComTxIPdu.ComTxModeTrue.ComTxModeTimeOffsetFactor;\r
+ }\r
+\r
+\r
+ // Reset earliest deadline.\r
+ earliestDeadline = -1; // Gives the max value of uint32 due to overflow.\r
+ firstTimeout = -1;\r
+\r
+ // Reserve memory for all defined signals.\r
+ EcoreIPdu->ComIPduDataPtr = malloc(IPdu->ComIPduSize);\r
+ if (EcoreIPdu->ComIPduDataPtr == NULL) {\r
+ failure = 1;\r
+ }\r
+\r
+ // Initialize the memory with the default value.\r
+ if (IPdu->ComIPduDirection == SEND) {\r
+ memset(EcoreIPdu->ComIPduDataPtr, IPdu->ComTxIPdu.ComTxIPduUnusedAreasDefault, IPdu->ComIPduSize);\r
+ }\r
+\r
+ // For each signal in this PDU.\r
+ for (int j = 0; IPdu->ComIPduSignalRef[j] != NULL; j++) {\r
+ Signal = IPdu->ComIPduSignalRef[j];\r
+ ComGetEcoreSignal(Signal->ComHandleId);\r
+\r
+ // If this signal already has been configured this is most likely an error.\r
+ if (EcoreSignal->ComIPduDataPtr != NULL) {\r
+ DET_REPORTERROR(COM_MODULE_ID, COM_INSTANCE_ID, 0x01, COM_E_INVALID_SIGNAL_CONFIGURATION);\r
+ failure = 1;\r
+ }\r
+\r
+ // Configure signal deadline monitoring if used.\r
+ if (Signal->ComTimeoutFactor > 0) {\r
+\r
+ if (Signal->ComSignalEcoreUseUpdateBit) {\r
+ // This signal uses an update bit, and hence has its own deadline monitoring.\r
+ EcoreSignal->ComEcoreDeadlineCounter = Signal->ComFirstTimeoutFactor; // Configure the deadline counter\r
+ EcoreSignal->ComTimeoutFactor = Signal->ComTimeoutFactor;\r
+\r
+ } else {\r
+ // This signal does not use an update bit, and should therefore use per I-PDU deadline monitoring.\r
+ // Find the earliest deadline for this I-PDU and setup the deadline later.\r
+ if (earliestDeadline > Signal->ComTimeoutFactor) {\r
+ earliestDeadline = Signal->ComTimeoutFactor;\r
+ }\r
+ if (firstTimeout > Signal->ComFirstTimeoutFactor) {\r
+ firstTimeout = Signal->ComFirstTimeoutFactor;\r
+ }\r
+ }\r
+ }\r
+\r
+ // Increment helper counters\r
+ EcoreIPdu->NComIPduSignalRef = j + 1;\r
+\r
+ //IPdu->ComEcoreNIPduSignalGroupRef = j + 1;\r
+\r
+ EcoreSignal->ComIPduDataPtr = EcoreIPdu->ComIPduDataPtr;\r
+ EcoreSignal->ComIPduHandleId = i;\r
+\r
+ // Clear update bits\r
+ if (Signal->ComSignalEcoreUseUpdateBit) {\r
+ clearBit(EcoreIPdu->ComIPduDataPtr, Signal->ComUpdateBitPosition);\r
+ }\r
+\r
+ // If this signal is a signal group\r
+ if (Signal->ComEcoreIsSignalGroup) {\r
+ EcoreSignal->ComEcoreShadowBuffer = malloc(IPdu->ComIPduSize);\r
+\r
+ if (EcoreSignal->ComEcoreShadowBuffer == NULL) {\r
+ failure = 1;\r
+ }\r
+\r
+ // For each group signal of this signal group.\r
+ for(int h = 0; Signal->ComGroupSignal[h] != NULL; h++) {\r
+ GroupSignal = Signal->ComGroupSignal[h];\r
+ ComGetEcoreGroupSignal(GroupSignal->ComHandleId);\r
+ // Set pointer to shadow buffer\r
+ EcoreGroupSignal->ComEcoreShadowBuffer = EcoreSignal->ComEcoreShadowBuffer;\r
+ // Initialize group signal data.\r
+ Com_CopyData(EcoreIPdu->ComIPduDataPtr, &GroupSignal->ComSignalInitValue, GroupSignal->ComBitSize, GroupSignal->ComBitPosition, 0);\r
+ }\r
+\r
+ } else {\r
+ // Initialize signal data.\r
+ Com_CopyData(EcoreIPdu->ComIPduDataPtr, &Signal->ComSignalInitValue, Signal->ComBitSize, Signal->ComBitPosition, 0);\r
+ }\r
+\r
+ // Check filter configuration\r
+ if (IPdu->ComIPduDirection == RECEIVE) {\r
+\r
+ // This represents an invalid configuration of the UINT8_N datatype\r
+ if ((Signal->ComSignalType == UINT8_N\r
+ &&\r
+ (Signal->ComFilter.ComFilterAlgorithm == MASKED_NEW_EQUALS_X\r
+ || Signal->ComFilter.ComFilterAlgorithm == MASKED_NEW_DIFFERS_X\r
+ || Signal->ComFilter.ComFilterAlgorithm == MASKED_NEW_DIFFERS_MASKED_OLD\r
+ || Signal->ComFilter.ComFilterAlgorithm == NEW_IS_WITHIN\r
+ || Signal->ComFilter.ComFilterAlgorithm == NEW_IS_OUTSIDE\r
+ || Signal->ComFilter.ComFilterAlgorithm == ONE_EVERY_N))) {\r
+\r
+ DET_REPORTERROR(COM_MODULE_ID, COM_INSTANCE_ID, 0x01, COM_E_INVALID_FILTER_CONFIGURATION);\r
+ failure = 1;\r
+ }\r
+\r
+ // This represens an invalid configuration of the BOOLEAN datatype\r
+ if ((Signal->ComSignalType == BOOLEAN\r
+ &&\r
+ (Signal->ComFilter.ComFilterAlgorithm == NEW_IS_WITHIN\r
+ || Signal->ComFilter.ComFilterAlgorithm == NEW_IS_OUTSIDE))) {\r
+\r
+\r
+ DET_REPORTERROR(COM_MODULE_ID, COM_INSTANCE_ID, 0x01, COM_E_INVALID_FILTER_CONFIGURATION);\r
+ failure = 1;\r
+ }\r
+ // Initialize filter values. COM230\r
+ //signal.ComFilter.ComFilterNewValue = ComConfig->ComIPdu[i].ComTxIPdu.ComTxIPduUnusedAreasDefault;\r
+ //signal.ComFilter.ComFilterOldValue = ComConfig->ComIPdu[i].ComTxIPdu.ComTxIPduUnusedAreasDefault;\r
+ }\r
+ }\r
+\r
+ // Configure per I-PDU based deadline monitoring.\r
+ for (int j = 0; IPdu->ComIPduSignalRef[j] != NULL; j++) {\r
+ Signal = IPdu->ComIPduSignalRef[j];\r
+ ComGetEcoreSignal(Signal->ComHandleId);\r
+\r
+ if (Signal->ComTimeoutFactor > 0 && !Signal->ComSignalEcoreUseUpdateBit) {\r
+ EcoreSignal->ComTimeoutFactor = earliestDeadline;\r
+ EcoreSignal->ComEcoreDeadlineCounter = firstTimeout;\r
+ }\r
+ }\r
+ }\r
+\r
+\r
+ // An error occurred.\r
+ if (failure) {\r
+ // Free allocated memory\r
+ for (int i = 0; !ComConfig->ComIPdu[i].ComEcoreEOL; i++) {\r
+ // Release memory for all defined signals.\r
+ //free(ComConfig->ComIPdu[i].ComIPduDataPtr);\r
+ }\r
+ DEBUG(DEBUG_LOW, "--Initialization of COM failed--\n");\r
+ //DET_REPORTERROR(COM_MODULE_ID, COM_INSTANCE_ID, 0x01, COM_E_INVALID_FILTER_CONFIGURATION);\r
+ } else {\r
+ DEBUG(DEBUG_LOW, "--Initialization of COM completed--\n");\r
+ }\r
+}\r
+\r
+\r
+void Com_DeInit( void ) {\r
+\r
+}\r
+\r
+void Com_IpduGroupStart(Com_PduGroupIdType IpduGroupId,boolean Initialize) {\r
+ for (int i = 0; !ComConfig->ComIPdu[i].ComEcoreEOL; i++) {\r
+ if (ComConfig->ComIPdu[i].ComIPduGroupRef == IpduGroupId) {\r
+ ComEcoreConfig.ComIPdu[i].ComEcoreIpduStarted = 1;\r
+ }\r
+ }\r
+}\r
+\r
+void Com_IpduGroupStop(Com_PduGroupIdType IpduGroupId) {\r
+ for (int i = 0; !ComConfig->ComIPdu[i].ComEcoreEOL; i++) {\r
+ if (ComConfig->ComIPdu[i].ComIPduGroupRef == IpduGroupId) {\r
+ ComEcoreConfig.ComIPdu[i].ComEcoreIpduStarted = 0;\r
+ }\r
+ }\r
+}\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef COM_CBK_H_\r
+#define COM_CBK_H_\r
+\r
+#endif /*COM_CBK_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include <stdlib.h>\r
+#include <string.h>\r
+#include "Com_Com.h"\r
+#include "Trace.h"\r
+#include "CanIf.h"\r
+#include "PduR.h"\r
+#include "PduR_Com.h"\r
+#include "Byteorder.h"\r
+\r
+uint8 Com_SendSignal(Com_SignalIdType SignalId, const void *SignalDataPtr) {\r
+ COM_VALIDATE_SIGNAL(SignalId, 0x0a, E_NOT_OK);\r
+ // Store pointer to signal for easier coding.\r
+ ComGetSignal(SignalId);\r
+ ComGetEcoreSignal(SignalId);\r
+ ComGetIPdu(EcoreSignal->ComIPduHandleId);\r
+ ComGetEcoreIPdu(EcoreSignal->ComIPduHandleId);\r
+\r
+ //DEBUG(DEBUG_LOW, "Com_SendSignal: id %d, nBytes %d, BitPosition %d, intVal %d\n", SignalId, nBytes, signal->ComBitPosition, (uint32)*(uint8 *)SignalDataPtr);\r
+\r
+ void *dataPtr = (void *)SignalDataPtr;\r
+\r
+ if (Signal->ComSignalEndianess == BIG_ENDIAN) {\r
+ if (Signal->ComSignalType == UINT16) {\r
+ uint16 data;\r
+ memcpy(&data, SignalDataPtr, SignalTypeToSize(Signal->ComSignalType,Signal->ComSignalLength));\r
+ data = bswap16(data);\r
+ dataPtr = &data;\r
+\r
+ } else if (Signal->ComSignalType == UINT32) {\r
+ uint32 data;\r
+ memcpy(&data, SignalDataPtr, SignalTypeToSize(Signal->ComSignalType,Signal->ComSignalLength));\r
+ data = bswap32(data);\r
+ dataPtr = &data;\r
+\r
+ } else if (Signal->ComSignalType == SINT16) {\r
+ sint16 data;\r
+ memcpy(&data, SignalDataPtr, SignalTypeToSize(Signal->ComSignalType,Signal->ComSignalLength));\r
+ data = bswap16(data);\r
+ dataPtr = &data;\r
+\r
+ } else if (Signal->ComSignalType == SINT32) {\r
+ sint32 data;\r
+ memcpy(&data, SignalDataPtr, SignalTypeToSize(Signal->ComSignalType,Signal->ComSignalLength));\r
+ data = bswap32(data);\r
+ dataPtr = &data;\r
+ }\r
+\r
+ }\r
+\r
+ Com_CopyData(EcoreIPdu->ComIPduDataPtr, dataPtr, Signal->ComBitSize, Signal->ComBitPosition, 0);\r
+\r
+ // If the signal has an update bit. Set it!\r
+ if (Signal->ComSignalEcoreUseUpdateBit) {\r
+ setBit(EcoreIPdu->ComIPduDataPtr, Signal->ComUpdateBitPosition);\r
+ }\r
+\r
+ /*\r
+ * If signal has triggered transmit property, trigger a transmission!\r
+ */\r
+ if (Signal->ComTransferProperty == TRIGGERED) {\r
+ EcoreIPdu->ComEcoreTxIPduTimers.ComTxIPduNumberOfRepetitionsLeft = IPdu->ComTxIPdu.ComTxModeTrue.ComTxModeNumberOfRepetitions + 1;\r
+ }\r
+ return E_OK;\r
+}\r
+\r
+uint8 Com_ReceiveSignal(Com_SignalIdType SignalId, void* SignalDataPtr) {\r
+ ComGetSignal(SignalId);\r
+ COM_VALIDATE_SIGNAL(SignalId, 0x0b, E_NOT_OK);\r
+ DEBUG(DEBUG_LOW, "Com_ReceiveSignal: SignalId %d\n", SignalId);\r
+\r
+ Com_CopyFromSignal(&ComConfig->ComSignal[SignalId], SignalDataPtr);\r
+\r
+ if (Signal->ComSignalEndianess == BIG_ENDIAN) {\r
+ if (Signal->ComSignalType == UINT16) {\r
+ *(uint16*)SignalDataPtr = bswap16(*(uint16*)SignalDataPtr);\r
+ //memcpy(SignalDataPtr, dataPtr, SignalTypeToSize(Signal->ComSignalType,Signal->ComSignalLength));\r
+\r
+ } else if (Signal->ComSignalType == UINT32) {\r
+ *(uint32*)SignalDataPtr = bswap32(*(uint32*)SignalDataPtr);\r
+ //memcpy(SignalDataPtr, dataPtr, SignalTypeToSize(Signal->ComSignalType,Signal->ComSignalLength));\r
+\r
+ } else if (Signal->ComSignalType == SINT16) {\r
+ *(sint16*)SignalDataPtr = bswap16(*(sint16*)SignalDataPtr);\r
+ //memcpy(SignalDataPtr, dataPtr, SignalTypeToSize(Signal->ComSignalType,Signal->ComSignalLength));\r
+\r
+ } else if (Signal->ComSignalType == SINT32) {\r
+ *(sint32*)SignalDataPtr = bswap32(*(sint32*)SignalDataPtr);\r
+ //memcpy(SignalDataPtr, dataPtr, SignalTypeToSize(Signal->ComSignalType,Signal->ComSignalLength));\r
+ }\r
+ }\r
+\r
+\r
+\r
+ //uint16 val = *(uint16 *)SignalDataPtr;\r
+ //val = bswap16(val);\r
+ // Sign extend!\r
+ return E_OK;\r
+}\r
+\r
+Std_ReturnType Com_TriggerTransmit(PduIdType ComTxPduId, uint8 *SduPtr) {\r
+ PduIdCheck(ComTxPduId, 0x13, E_NOT_OK);\r
+ /*\r
+ * COM260: This function must not check the transmission mode of the I-PDU\r
+ * since it should be possible to use it regardless of the transmission mode.\r
+ */\r
+\r
+ /*\r
+ * COM395: This function must override the IPdu callouts used in Com_TriggerIPduTransmit();\r
+ */\r
+ ComGetIPdu(ComTxPduId);\r
+ ComGetEcoreIPdu(ComTxPduId);\r
+\r
+ memcpy(SduPtr, EcoreIPdu->ComIPduDataPtr, IPdu->ComIPduSize);\r
+ return E_OK;\r
+}\r
+\r
+\r
+void Com_TriggerIPduSend(PduIdType ComTxPduId) {\r
+ PduIdCheck(ComTxPduId, 0x17);\r
+\r
+ //DEBUG(DEBUG_MEDIUM, "Com_TriggerIPduSend sending IPdu %d... ", ComTxPduId);\r
+ ComGetIPdu(ComTxPduId);\r
+ ComGetEcoreIPdu(ComTxPduId);\r
+\r
+ // Is the IPdu ready for transmission?\r
+ if (EcoreIPdu->ComEcoreTxIPduTimers.ComTxIPduMinimumDelayTimer == 0) {\r
+ //DEBUG(DEBUG_MEDIUM, "success!\n", ComTxPduId);\r
+\r
+ /*\r
+ PduInfoType PduInfoPackage = {\r
+ .SduDataPtr = malloc(IPdu->ComIPduSize),\r
+ .SduLength = ComConfig->ComIPdu[ComTxPduId].ComIPduSize\r
+ };\r
+ memcpy((void *)PduInfoPackage.SduDataPtr, EcoreIPdu->ComIPduDataPtr, IPdu->ComIPduSize);\r
+ */\r
+\r
+ ComEcoreConfig.OutgoingPdu.SduLength = ComConfig->ComIPdu[ComTxPduId].ComIPduSize;\r
+ memcpy((void *)ComEcoreConfig.OutgoingPdu.SduDataPtr, EcoreIPdu->ComIPduDataPtr, IPdu->ComIPduSize);\r
+ // Check callout status\r
+ if (IPdu->ComIPduCallout != NULL) {\r
+ if (!IPdu->ComIPduCallout(ComTxPduId, EcoreIPdu->ComIPduDataPtr)) {\r
+ // TODO Report error to DET.\r
+ // Det_ReportError();\r
+ return;\r
+ }\r
+ }\r
+\r
+ // Send IPdu!\r
+ if (PduR_ComTransmit(ComTxPduId, &ComEcoreConfig.OutgoingPdu) == E_OK) {\r
+ // Clear all update bits for the contained signals\r
+ for (int i = 0; i < EcoreIPdu->NComIPduSignalRef; i++) {\r
+ if (IPdu->ComIPduSignalRef[i]->ComSignalEcoreUseUpdateBit) {\r
+ clearBit(EcoreIPdu->ComIPduDataPtr, IPdu->ComIPduSignalRef[i]->ComUpdateBitPosition);\r
+ }\r
+ }\r
+ }\r
+ // Free allocted memory.\r
+ // TODO: Is this the best way to solve this memory problem?\r
+ //free(PduInfoPackage.SduDataPtr);\r
+\r
+ // Reset miminum delay timer.\r
+ EcoreIPdu->ComEcoreTxIPduTimers.ComTxIPduMinimumDelayTimer = IPdu->ComTxIPdu.ComTxIPduMinimumDelayFactor;\r
+\r
+ } else {\r
+ //DEBUG(DEBUG_MEDIUM, "failed (MDT)!\n", ComTxPduId);\r
+ }\r
+}\r
+\r
+Std_ReturnType Com_RxIndication(PduIdType ComRxPduId, const uint8* SduPtr) {\r
+ PduIdCheck(ComRxPduId, 0x14, E_NOT_OK);\r
+\r
+ ComGetIPdu(ComRxPduId);\r
+ ComGetEcoreIPdu(ComRxPduId);\r
+\r
+ // If Ipdu is stopped\r
+ if (!EcoreIPdu->ComEcoreIpduStarted) {\r
+ return E_OK;\r
+ }\r
+\r
+ // Check callout status\r
+ if (IPdu->ComIPduCallout != NULL) {\r
+ if (!IPdu->ComIPduCallout(ComRxPduId, SduPtr)) {\r
+ // TODO Report error to DET.\r
+ // Det_ReportError();\r
+ return E_NOT_OK;\r
+ }\r
+ }\r
+\r
+ // Copy IPDU data\r
+ memcpy(EcoreIPdu->ComIPduDataPtr, SduPtr, IPdu->ComIPduSize);\r
+\r
+ // For each signal.\r
+ const ComSignal_type *signal;\r
+ for (int i = 0; IPdu->ComIPduSignalRef[i] != NULL; i++) {\r
+ signal = IPdu->ComIPduSignalRef[i];\r
+ ComGetEcoreSignal(signal->ComHandleId);\r
+\r
+ // If this signal uses an update bit, then it is only considered if this bit is set.\r
+ if (!signal->ComSignalEcoreUseUpdateBit ||\r
+ (signal->ComSignalEcoreUseUpdateBit && testBit(EcoreIPdu->ComIPduDataPtr, signal->ComUpdateBitPosition))) {\r
+\r
+ if (signal->ComTimeoutFactor > 0) { // If reception deadline monitoring is used.\r
+ // Reset the deadline monitoring timer.\r
+ EcoreSignal->ComEcoreDeadlineCounter = signal->ComTimeoutFactor;\r
+ }\r
+\r
+ /*\r
+ // Zero new filter value.\r
+ IPdu->ComIPduSignalRef[i]->ComFilter.ComFilterEcoreNewValue = 0;\r
+\r
+ //Fix this!!!\r
+ Com_CopyFromSignal(IPdu->ComIPduSignalRef[i], &IPdu->ComIPduSignalRef[i]->ComFilter.ComFilterEcoreNewValue);\r
+ */\r
+ // Perform filtering\r
+ //if (Com_Filter(IPdu->ComIPduSignalRef[i])) {\r
+\r
+ // Check the signal processing mode.\r
+ if (IPdu->ComIPduSignalProcessing == IMMEDIATE) {\r
+ // If signal processing mode is IMMEDIATE, notify the signal callback.\r
+ if (IPdu->ComIPduSignalRef[i]->ComNotification != NULL) {\r
+ IPdu->ComIPduSignalRef[i]->ComNotification();\r
+ }\r
+\r
+ } else {\r
+ // Signal processing mode is DEFERRED, mark the signal as updated.\r
+ EcoreSignal->ComSignalUpdated = 1;\r
+ }\r
+ //}\r
+ } else {\r
+ DEBUG(DEBUG_LOW, "Com_RxIndication: Ignored signal %d of I-PDU %d since its update bit was not set\n", signal->ComHandleId, IPdu->ComIPduRxHandleId);\r
+ }\r
+ }\r
+\r
+ return E_OK;\r
+}\r
+\r
+void Com_TxConfirmation(PduIdType ComTxPduId) {\r
+ PduIdCheck(ComTxPduId, 0x15);\r
+}\r
+\r
+\r
+Std_ReturnType Com_SendSignalGroup(Com_SignalGroupIdType SignalGroupId) {\r
+//#warning Com_SendSignalGroup should be performed atomically. Should we disable interrupts here?\r
+ ComGetSignal(SignalGroupId);\r
+ ComGetEcoreSignal(SignalGroupId);\r
+ ComGetEcoreIPdu(EcoreSignal->ComIPduHandleId);\r
+ ComGetIPdu(EcoreSignal->ComIPduHandleId);\r
+\r
+\r
+ // Copy shadow buffer to Ipdu data space\r
+ const ComGroupSignal_type *groupSignal;\r
+ for (int i = 0; Signal->ComGroupSignal[i] != NULL; i++) {\r
+ groupSignal = Signal->ComGroupSignal[i];\r
+ Com_CopyData(EcoreIPdu->ComIPduDataPtr, EcoreSignal->ComEcoreShadowBuffer, groupSignal->ComBitSize, groupSignal->ComBitPosition, groupSignal->ComBitPosition);\r
+ }\r
+\r
+ // If the signal has an update bit. Set it!\r
+ if (Signal->ComSignalEcoreUseUpdateBit) {\r
+ setBit(EcoreIPdu->ComIPduDataPtr, Signal->ComUpdateBitPosition);\r
+ }\r
+\r
+ /*\r
+ * If signal has triggered transmit property, trigger a transmission!\r
+ */\r
+ if (Signal->ComTransferProperty == TRIGGERED) {\r
+ EcoreIPdu->ComEcoreTxIPduTimers.ComTxIPduNumberOfRepetitionsLeft = IPdu->ComTxIPdu.ComTxModeTrue.ComTxModeNumberOfRepetitions + 1;\r
+ }\r
+\r
+ return E_OK;\r
+}\r
+\r
+\r
+Std_ReturnType Com_ReceiveSignalGroup(Com_SignalGroupIdType SignalGroupId) {\r
+//#warning Com_ReceiveSignalGroup should be performed atomically. Should we disable interrupts here?\r
+ ComGetSignal(SignalGroupId);\r
+ ComGetEcoreSignal(SignalGroupId);\r
+ ComGetEcoreIPdu(EcoreSignal->ComIPduHandleId);\r
+\r
+ // Copy Ipdu data buffer to shadow buffer.\r
+ const ComGroupSignal_type *groupSignal;\r
+ for (int i = 0; Signal->ComGroupSignal[i] != NULL; i++) {\r
+ groupSignal = Signal->ComGroupSignal[i];\r
+ Com_CopyData(EcoreSignal->ComEcoreShadowBuffer, EcoreIPdu->ComIPduDataPtr, groupSignal->ComBitSize, groupSignal->ComBitPosition, groupSignal->ComBitPosition);\r
+ }\r
+\r
+\r
+ return E_OK;\r
+}\r
+\r
+void Com_UpdateShadowSignal(Com_SignalIdType SignalId, const void *SignalDataPtr) {\r
+ ComGetGroupSignal(SignalId);\r
+ ComGetEcoreGroupSignal(SignalId);\r
+ Com_CopyData(EcoreGroupSignal->ComEcoreShadowBuffer, SignalDataPtr, GroupSignal->ComBitSize, GroupSignal->ComBitPosition, 0);\r
+}\r
+\r
+void Com_ReceiveShadowSignal(Com_SignalIdType SignalId, void *SignalDataPtr) {\r
+ ComGetGroupSignal(SignalId);\r
+ ComGetEcoreGroupSignal(SignalId);\r
+ Com_CopyData(SignalDataPtr, EcoreGroupSignal->ComEcoreShadowBuffer, GroupSignal->ComBitSize, 0, GroupSignal->ComBitPosition);\r
+}\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef COM_COM_H_\r
+#define COM_COM_H_\r
+\r
+#include "Com.h"\r
+#include "Com_misc.h"\r
+#include "PduR.h"\r
+\r
+uint8 Com_SendSignal(Com_SignalIdType SignalId, const void *SignalDataPtr);\r
+uint8 Com_ReceiveSignal(Com_SignalIdType SignalId, void* SignalDataPtr);\r
+\r
+Std_ReturnType Com_TriggerTransmit(PduIdType ComTxPduId, uint8 *SduPtr);\r
+\r
+void Com_TriggerIPduSend(PduIdType ComTxPduId);\r
+\r
+Std_ReturnType Com_RxIndication(PduIdType ComRxPduId, const uint8* PduInfoPtr);\r
+void Com_TxConfirmation(PduIdType ComTxPduId);\r
+\r
+\r
+/* Signal Groups */\r
+\r
+Std_ReturnType Com_SendSignalGroup(Com_SignalGroupIdType SignalGroupId);\r
+Std_ReturnType Com_ReceiveSignalGroup(Com_SignalGroupIdType SignalGroupId);\r
+\r
+void Com_UpdateShadowSignal(Com_SignalIdType SignalId, const void *SignalDataPtr);\r
+void Com_ReceiveShadowSignal(Com_SignalIdType SignalId, void *SignalDataPtr);\r
+\r
+\r
+#endif /* COM_COM_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+typedef struct {\r
+ uint32 ComFilterEcoreN;\r
+ uint32 ComFilterEcoreNewValue;\r
+ uint32 ComFilterEcoreOldValue;\r
+} ComEcoreFilter_type;\r
+\r
+typedef struct {\r
+\r
+ ComEcoreFilter_type ComFilter;\r
+\r
+ uint32 ComEcoreDeadlineCounter;\r
+ uint32 ComTimeoutFactor;\r
+ void *ComIPduDataPtr;\r
+\r
+ uint8 ComIPduHandleId;\r
+ uint8 ComSignalUpdated;\r
+ //uint8 ComEcoreEOL;\r
+ //uint8 ComEcoreIsSignalGroup;\r
+\r
+ /* For signal groups */\r
+ void *ComEcoreShadowBuffer;\r
+\r
+} ComEcoreSignal_type;\r
+\r
+\r
+typedef struct {\r
+ void *ComEcoreShadowBuffer;\r
+ //uint8 ComIPduHandleId;\r
+\r
+ uint8 ComSignalUpdated;\r
+ uint8 ComEcoreEOL;\r
+} ComEcoreGroupSignal_type;\r
+\r
+\r
+/*\r
+typedef struct {\r
+ void *ComEcoreShadowBuffer;\r
+ void *ComEcoreIPduDataPtr;\r
+ uint8 ComEcoreEOL;\r
+} ComEcoreSignalGroup_type;\r
+*/\r
+\r
+typedef struct {\r
+ uint8 ComTxIPduNumberOfRepetitionsLeft;\r
+ uint32 ComTxModeRepetitionPeriodTimer;\r
+ uint32 ComTxIPduMinimumDelayTimer;\r
+ uint32 ComTxModeTimePeriodTimer;\r
+} ComEcoreTxIPduTimer_type;\r
+\r
+typedef struct {\r
+\r
+ ComEcoreTxIPduTimer_type ComEcoreTxIPduTimers;\r
+ void *ComIPduDataPtr;\r
+\r
+ uint8 ComEcoreNIPduSignalGroupRef;\r
+\r
+ uint8 NComIPduSignalRef;\r
+\r
+ uint8 ComEcoreIpduStarted;\r
+\r
+} ComEcoreIPdu_type;\r
+\r
+typedef struct {\r
+ uint16 ComNIPdu;\r
+ ComEcoreIPdu_type *ComIPdu; // Only used in PduIdCheck()\r
+ //ComEcoreIPduGroup_type *ComIPduGroup;\r
+ ComEcoreSignal_type *ComSignal;\r
+ //ComEcoreSignalGroup_type *ComSignalGroup;\r
+ ComEcoreGroupSignal_type *ComGroupSignal;\r
+ PduInfoType OutgoingPdu;\r
+} ComEcoreConfig_type;\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include "Com_RunTest.h"\r
+#include "Com.h"\r
+#include "Trace.h"\r
+#include <stdlib.h>\r
+\r
+//#define DEBUG_LVL DEBUG_MEDIUM\r
+\r
+static uint8 RTE_ReceivedData[8] = {9,9,9,9,9,9,9,9};\r
+\r
+static void PrintReceivedData(int nBytes) {\r
+ DEBUG(DEBUG_HIGH, "Received data: ");\r
+ for (int i = 0; i < nBytes; i++) {\r
+ DEBUG(DEBUG_HIGH, "%d ", RTE_ReceivedData[i]);\r
+ }\r
+ DEBUG(DEBUG_HIGH,"\n");\r
+}\r
+\r
+void RTE_Notification(void) {\r
+ DEBUG(DEBUG_HIGH, "RTE received notification.");\r
+\r
+ Com_ReceiveSignal(11, (void *)RTE_ReceivedData);\r
+\r
+ PrintReceivedData(8);\r
+\r
+ DEBUG(DEBUG_HIGH, "Received data (signal %d): %d\n", 11, (sint8)RTE_ReceivedData[0]);\r
+}\r
+\r
+uint8 SIL2value;\r
+uint8 SIL2quality;\r
+void RTE_SIL2MESSAGE() {\r
+ Com_ReceiveSignalGroup(2);\r
+ Com_ReceiveShadowSignal(0, &SIL2value);\r
+ Com_ReceiveShadowSignal(1, &SIL2quality);\r
+\r
+ DEBUG(DEBUG_HIGH, "SIL2 message received! value: %d, quality: %d\n", SIL2value, SIL2quality);\r
+}\r
+\r
+static uint16 newSpeed;\r
+static uint16 setNewSpeed = 0;\r
+void RTE_EngineChangeSpeed() {\r
+ setNewSpeed = 1;\r
+}\r
+\r
+void RTE_EngineMain() {\r
+ if (setNewSpeed) {\r
+ Com_ReceiveSignal(1, (void *)&newSpeed);\r
+\r
+ dbg_printf("Setting engine speed to %d rpm\n", newSpeed);\r
+ /*\r
+ static uint16 sig;\r
+ sig = rand() % 10000;\r
+ */\r
+ Com_SendSignal(0, (void *)&newSpeed);\r
+ setNewSpeed = 0;\r
+ }\r
+}\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef COM_RUNTEST_H_\r
+#define COM_RUNTEST_H_\r
+\r
+void RTE_Notification(void);\r
+void RTE_EngineMain(void);\r
+void RTE_EngineChangeSpeed(void);\r
+void RTE_SIL2MESSAGE(void);\r
+\r
+#endif /* COM_RUNTEST_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include "Com_Sched.h"\r
+#include <string.h>\r
+#include "Trace.h"\r
+\r
+#define timerDec(timer) \\r
+ if (timer > 0) { \\r
+ timer = timer - 1; \\r
+ } \\r
+\r
+\r
+void Com_MainFunctionRx() {\r
+ //DEBUG(DEBUG_MEDIUM, "Com_MainFunctionRx() excecuting\n");\r
+ const ComSignal_type *signal;\r
+ for (int i = 0; !ComConfig->ComSignal[i].ComEcoreEOL; i++) {\r
+ signal = &ComConfig->ComSignal[i];\r
+ ComGetEcoreSignal(signal->ComHandleId);\r
+ ComGetEcoreIPdu(EcoreSignal->ComIPduHandleId);\r
+\r
+ // Monitor signal reception deadline\r
+ if (EcoreIPdu->ComEcoreIpduStarted && EcoreSignal->ComTimeoutFactor > 0) {\r
+\r
+ // Decrease deadline monitoring timer.\r
+ timerDec(EcoreSignal->ComEcoreDeadlineCounter);\r
+\r
+ // Check if a timeout has occurred.\r
+ if (EcoreSignal->ComEcoreDeadlineCounter == 0) {\r
+ if (signal->ComRxDataTimeoutAction == COM_TIMEOUT_DATA_ACTION_REPLACE) {\r
+ // Replace signal data.\r
+ uint32 signalInitData;\r
+ memset(&signalInitData, signal->ComSignalInitValue, sizeof(uint32));\r
+\r
+ Com_CopyData(EcoreIPdu->ComIPduDataPtr, &signalInitData, signal->ComBitSize, signal->ComBitPosition, 0);\r
+\r
+ }\r
+\r
+ // A timeout has occurred.\r
+ if (signal->ComTimeoutNotification != NULL) {\r
+ signal->ComTimeoutNotification();\r
+ }\r
+\r
+ // Restart timer\r
+ EcoreSignal->ComEcoreDeadlineCounter = EcoreSignal->ComTimeoutFactor;\r
+ }\r
+ }\r
+\r
+ if (EcoreSignal->ComSignalUpdated) {\r
+ ComConfig->ComSignal[i].ComNotification();\r
+ EcoreSignal->ComSignalUpdated = 0;\r
+ }\r
+ }\r
+}\r
+\r
+\r
+void Com_MainFunctionTx() {\r
+ //DEBUG(DEBUG_MEDIUM, "Com_MainFunctionTx() excecuting\n");\r
+ // Decrease timers.\r
+ const ComIPdu_type *IPdu;\r
+ for (int i = 0; !ComConfig->ComIPdu[i].ComEcoreEOL; i++) {\r
+ IPdu = &ComConfig->ComIPdu[i];\r
+ ComGetEcoreIPdu(i);\r
+\r
+ // Is this a IPdu that should be transmitted?\r
+ if (IPdu->ComIPduDirection == SEND && EcoreIPdu->ComEcoreIpduStarted) {\r
+ // Decrease minimum delay timer\r
+ timerDec(EcoreIPdu->ComEcoreTxIPduTimers.ComTxIPduMinimumDelayTimer);\r
+\r
+ // If IPDU has periodic or mixed transmission mode.\r
+ if (IPdu->ComTxIPdu.ComTxModeTrue.ComTxModeMode == PERIODIC\r
+ || IPdu->ComTxIPdu.ComTxModeTrue.ComTxModeMode == MIXED) {\r
+\r
+ timerDec(EcoreIPdu->ComEcoreTxIPduTimers.ComTxModeTimePeriodTimer);\r
+\r
+ // Is it time for a direct transmission?\r
+ if (IPdu->ComTxIPdu.ComTxModeTrue.ComTxModeMode == MIXED\r
+ && EcoreIPdu->ComEcoreTxIPduTimers.ComTxIPduNumberOfRepetitionsLeft > 0) {\r
+\r
+ timerDec(EcoreIPdu->ComEcoreTxIPduTimers.ComTxModeRepetitionPeriodTimer);\r
+\r
+ // Is it time for a transmission?\r
+ if (EcoreIPdu->ComEcoreTxIPduTimers.ComTxModeRepetitionPeriodTimer == 0\r
+ && EcoreIPdu->ComEcoreTxIPduTimers.ComTxIPduMinimumDelayTimer == 0) {\r
+\r
+ Com_TriggerIPduSend(IPdu->ComIPduRxHandleId);\r
+\r
+ // Reset periodic timer\r
+ EcoreIPdu->ComEcoreTxIPduTimers.ComTxModeRepetitionPeriodTimer = IPdu->ComTxIPdu.ComTxModeTrue.ComTxModeRepetitionPeriodFactor;\r
+\r
+ // Register this nth-transmission.\r
+ EcoreIPdu->ComEcoreTxIPduTimers.ComTxIPduNumberOfRepetitionsLeft--;\r
+ }\r
+ }\r
+\r
+ // Is it time for a cyclic transmission?\r
+ if (EcoreIPdu->ComEcoreTxIPduTimers.ComTxModeTimePeriodTimer == 0 && EcoreIPdu->ComEcoreTxIPduTimers.ComTxIPduMinimumDelayTimer == 0) {\r
+\r
+ Com_TriggerIPduSend(IPdu->ComIPduRxHandleId); // Send IPDU!\r
+\r
+ // Reset periodic timer.\r
+ EcoreIPdu->ComEcoreTxIPduTimers.ComTxModeTimePeriodTimer = IPdu->ComTxIPdu.ComTxModeTrue.ComTxModeTimePeriodFactor;\r
+ }\r
+\r
+ // If IPDU has direct transmission mode.\r
+ } else if (IPdu->ComTxIPdu.ComTxModeTrue.ComTxModeMode == DIRECT) {\r
+ // Do we need to transmit anything?\r
+ if (EcoreIPdu->ComEcoreTxIPduTimers.ComTxIPduNumberOfRepetitionsLeft > 0) {\r
+ timerDec(EcoreIPdu->ComEcoreTxIPduTimers.ComTxModeRepetitionPeriodTimer);\r
+\r
+ // Is it time for a transmission?\r
+ if (EcoreIPdu->ComEcoreTxIPduTimers.ComTxModeRepetitionPeriodTimer == 0 && EcoreIPdu->ComEcoreTxIPduTimers.ComTxIPduMinimumDelayTimer == 0) {\r
+ Com_TriggerIPduSend(IPdu->ComIPduRxHandleId);\r
+\r
+ // Reset periodic timer\r
+ EcoreIPdu->ComEcoreTxIPduTimers.ComTxModeRepetitionPeriodTimer = IPdu->ComTxIPdu.ComTxModeTrue.ComTxModeRepetitionPeriodFactor;\r
+\r
+ // Register this nth-transmission.\r
+ EcoreIPdu->ComEcoreTxIPduTimers.ComTxIPduNumberOfRepetitionsLeft--;\r
+ }\r
+ }\r
+\r
+ // The IDPU has NONE transmission mode.\r
+ } else {\r
+ // Don't send!\r
+ }\r
+ }\r
+ }\r
+\r
+ // Send scheduled packages.\r
+ // Cyclic\r
+ for (int i = 0; !ComConfig->ComIPdu[i].ComEcoreEOL; i++) {\r
+ if (ComConfig->ComIPdu[i].ComIPduDirection == SEND) {\r
+\r
+ }\r
+ }\r
+}\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef COM_SCHED_H_\r
+#define COM_SCHED_H_\r
+\r
+#include "Com.h"\r
+\r
+void Com_MainFunctionRx();\r
+void Com_MainFunctionTx();\r
+\r
+// Not supported in this version.\r
+//void Com_MainFunctionRouteSignals();\r
+\r
+#endif /* COM_SCHED_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+extern Com_ConfigType ComConfig_TEST;\r
+\r
+extern const PduR_PBConfigType PduRConfigData_TEST[];\r
+\r
+\r
+PduR_StdRTableType PduRConfigData_TEST = {\r
+ .TargetPduId = 0,\r
+ .NRoutingPaths = 6,\r
+ .RoutingTable = {\r
+ {\r
+ .FctPtrs = &PduR_StdLinFctPtrs,\r
+ .DestPduId = 0,\r
+ .SduLength = 2,\r
+ .DataProvision = PDUR_DIRECT,\r
+ .BufferDepth = 3,\r
+ },\r
+ {\r
+ .FctPtrs = &PduR_StdLinFctPtrs,\r
+ .DestPduId = 1,\r
+ .SduLength = 8,\r
+ .DataProvision = PDUR_NO_PROVISION,\r
+ },\r
+ {\r
+ .FctPtrs = &PduR_StdLinFctPtrs,\r
+ .DestPduId = 2,\r
+ .SduLength = 8,\r
+ .DataProvision = PDUR_TRIGGER_TRANSMIT,\r
+ .BufferDepth = 3,\r
+ },\r
+ {\r
+ .FctPtrs = &PduR_StdLinFctPtrs,\r
+ .DestPduId = 3,\r
+ .SduLength = 8,\r
+ .DataProvision = PDUR_DIRECT,\r
+ .PduR_GatewayMode = 1,\r
+ .BufferDepth = 4,\r
+ },\r
+\r
+ /* Gateway mode between lin interfaces but without buffers inbetween */\r
+ {\r
+ .FctPtrs = &PduR_StdLinFctPtrs,\r
+ .DestPduId = 4,\r
+ .SduLength = 8,\r
+ .DataProvision = PDUR_NO_PROVISION,\r
+ .PduR_GatewayMode = 1,\r
+ },\r
+\r
+ /* Gateway mode between lin interfaces using trigger transmit data provision */\r
+ {\r
+ .FctPtrs = &PduR_StdLinFctPtrs,\r
+ .DestPduId = 5,\r
+ .SduLength = 8,\r
+ .DataProvision = PDUR_TRIGGER_TRANSMIT,\r
+ .PduR_GatewayMode = 1,\r
+ .BufferDepth = 4,\r
+ },\r
+ }\r
+};\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef COM_TESTDATA_H_\r
+#define COM_TESTDATA_H_\r
+\r
+extern Com_ConfigType ComConfig_TEST;\r
+\r
+extern const PduR_PBConfigType PduRConfigData_TEST[];\r
+\r
+#endif /* COM_TESTDATA_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include <stdlib.h>\r
+#include <string.h>\r
+#include "Com_misc.h"\r
+\r
+\r
+void Com_CopyFromSignal(const ComSignal_type *signal, void *Destination) {\r
+ // Reset destination (for easier sign extension)\r
+ memset(Destination, 0, SignalTypeToSize(signal->ComSignalType, signal->ComSignalLength));\r
+\r
+ // Variables to store the source and destination bytes we are currently looking at.\r
+ uint8 sourceByte;\r
+ uint8 destByte;\r
+\r
+ // Pointer to a byte of the source and dest respectively.\r
+ ComGetEcoreSignal(signal->ComHandleId);\r
+ ComGetEcoreIPdu(EcoreSignal->ComIPduHandleId);\r
+ uint8 *source = (uint8 *)EcoreIPdu->ComIPduDataPtr;\r
+ uint8 *dest = (uint8 *)Destination;\r
+\r
+ uint8 signBit = 0;\r
+\r
+\r
+ if (signal->ComSignalEndianess != CPU_ENDIANESS && 0) {\r
+\r
+ uint8 numBytes = ((signal->ComBitPosition + signal->ComBitSize) / 8) + 1;\r
+ uint8 *sourceEndianConverted = malloc(numBytes) ; // NOT OK TO USE MALLOC! BUT IS THERE ANOTHER WAY?\r
+ //memcpy(sourceEndianConverted, source, numBytes);\r
+\r
+ // Reverse all bits in this temporary IPdu.\r
+ for(int i = 0; i < numBytes * 8; i++) {\r
+ sourceByte = i / 8; // Find out what byte this bit belongs to in the source.\r
+ destByte = i / 8; // Find the target byte.\r
+ if ( *(source + sourceByte) & (1 << (i % 8))) { // Is the bit set?\r
+ // Then set the target bit.\r
+ *(sourceEndianConverted + destByte) |= (1 << (7 - (i % 8)));\r
+ } else {\r
+ // Otherwise clear the target bit.\r
+ *(sourceEndianConverted + destByte) &= ~(1 << (7 - (i % 8)));\r
+ }\r
+ }\r
+\r
+ source = sourceEndianConverted;\r
+ }\r
+\r
+ signBit = Com_CopyData(dest, source, signal->ComBitSize, 0, signal->ComBitPosition);\r
+\r
+ // Sign extend!\r
+ // ############### THIS is NOT WORKING!\r
+ // Are there any unfilled bits in the destination?\r
+ if (signal->ComBitSize < SignalTypeToSize(signal->ComSignalType, signal->ComSignalLength) * 8) {\r
+ // These bits needs to be sign extended.\r
+ if ((signal->ComSignalType == SINT8\r
+ || signal->ComSignalType == SINT16\r
+ || signal->ComSignalType == SINT32)\r
+ && signBit) {\r
+\r
+ for (int i = signal->ComBitSize; i < SignalTypeToSize(signal->ComSignalType, signal->ComSignalLength) * 8; i++) {\r
+ destByte = i / 8;\r
+ *(dest + destByte) |= (1 << i % 8);\r
+ }\r
+ }\r
+ }\r
+\r
+ if (signal->ComSignalEndianess != CPU_ENDIANESS) {\r
+ free(source);\r
+ }\r
+}\r
+\r
+\r
+void Com_CopyToSignal(ComSignal_type *signal, const void *Source) {\r
+ ComGetEcoreSignal(signal->ComHandleId);\r
+ ComGetEcoreIPdu(EcoreSignal->ComIPduHandleId);\r
+ Com_CopyData(EcoreIPdu->ComIPduDataPtr, Source, signal->ComBitSize, signal->ComBitPosition, 0);\r
+}\r
+\r
+uint8 Com_CopyData(void *Destination, const void *Source, uint8 numBits, uint8 destOffset, uint8 sourceOffset) {\r
+\r
+ uint8 signBit;\r
+ // Variables to store the source and destination bytes we are currently looking at.\r
+ uint8 sourceByte;\r
+ uint8 destByte;\r
+\r
+ // Pointer to the first byte of the source and dest respectively.\r
+ uint8 *source = (uint8 *)Source;\r
+ uint8 *dest = (uint8 *)Destination;\r
+\r
+\r
+ // For every bit of the signal\r
+ for(int i = 0; i < numBits; i++) {\r
+ sourceByte = (i + sourceOffset) / 8; // Find out what byte this bit belongs to in the source.\r
+ destByte = (i + destOffset) / 8; // Find the target byte.\r
+ if ( testBit(source, (i + sourceOffset))) { // Is the bit set?\r
+ // Then set the target bit.\r
+ setBit(dest, (i + destOffset)); //*(dest + destByte) |= (1 << ((i + signal->ComBitPosition) % 8));\r
+ signBit = 1;\r
+ } else {\r
+ // Otherwise clear the target bit.\r
+ clearBit(dest, (i + destOffset)); //*(dest + destByte) &= ~(1 << ((i + signal->ComBitPosition) % 8));\r
+ signBit = 0;\r
+ }\r
+ }\r
+ return signBit;\r
+}\r
+\r
+\r
+uint8 Com_Filter(ComSignal_type *signal) {\r
+ ComGetEcoreSignal(signal->ComHandleId);\r
+ const ComFilter_type * filter = &signal->ComFilter;\r
+ uint8 success = 0;\r
+ if (filter->ComFilterAlgorithm == ALWAYS) {\r
+ success = 1;\r
+\r
+ } else if (filter->ComFilterAlgorithm == NEVER) {\r
+ success = 0;\r
+\r
+ } else if (filter->ComFilterAlgorithm == ONE_EVERY_N) {\r
+ // Treat the special cases that should not exists.\r
+ if (filter->ComFilterPeriodFactor < 2) {\r
+ // If PeriodFactor is 0 then every package is discarded.\r
+ // If PeriodFactor is 1 then every package is passed through.\r
+ success = filter->ComFilterPeriodFactor;\r
+\r
+ } else {\r
+ if (filter->ComFilterEcoreN == 0) {\r
+ success = 1;\r
+ } else {\r
+ success = 0;\r
+ }\r
+ EcoreSignal->ComFilter.ComFilterEcoreN++;\r
+ if (filter->ComFilterEcoreN >= filter->ComFilterPeriodFactor) {\r
+ EcoreSignal->ComFilter.ComFilterEcoreN = 0;\r
+ }\r
+ }\r
+\r
+ } else if (filter->ComFilterAlgorithm == NEW_IS_OUTSIDE) {\r
+ if ((filter->ComFilterMin > filter->ComFilterEcoreNewValue)\r
+ || (filter->ComFilterEcoreNewValue > filter->ComFilterMax)) {\r
+ success = 1;\r
+ } else {\r
+ success = 0;\r
+ }\r
+\r
+\r
+ } else if (filter->ComFilterAlgorithm == NEW_IS_WITHIN) {\r
+ if (filter->ComFilterMin <= filter->ComFilterEcoreNewValue\r
+ && filter->ComFilterEcoreNewValue <= filter->ComFilterMax) {\r
+ success = 1;\r
+ } else {\r
+ success = 0;\r
+ }\r
+\r
+\r
+ } else if (filter->ComFilterAlgorithm == MASKED_NEW_DIFFERS_MASKED_OLD) {\r
+ if ((filter->ComFilterEcoreNewValue & filter->ComFilterMask)\r
+ != (filter->ComFilterEcoreNewValue & filter->ComFilterMask)) {\r
+ success = 1;\r
+ } else {\r
+ success = 0;\r
+ }\r
+\r
+ } else if (filter->ComFilterAlgorithm == MASKED_NEW_DIFFERS_X) {\r
+ if ((filter->ComFilterEcoreNewValue & filter->ComFilterMask) != filter->ComFilterX) {\r
+ success = 1;\r
+ } else {\r
+ success = 0;\r
+ }\r
+\r
+ } else if (filter->ComFilterAlgorithm == MASKED_NEW_EQUALS_X) {\r
+ if ((filter->ComFilterEcoreNewValue & filter->ComFilterMask) == filter->ComFilterX) {\r
+ success = 1;\r
+ } else {\r
+ success = 0;\r
+ }\r
+ }\r
+\r
+ if (success) {\r
+ EcoreSignal->ComFilter.ComFilterEcoreOldValue = filter->ComFilterEcoreNewValue;\r
+ return 1;\r
+ } else return 0;\r
+}\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+#ifndef COM_MISC_H_\r
+#define COM_MISC_H_\r
+\r
+#include "Com.h"\r
+/*\r
+ * The following function are exported only for testing purposes.\r
+ */\r
+uint8 Com_Filter(ComSignal_type *signal);\r
+void Com_CopyFromSignal(const ComSignal_type *signal, void *Destination);\r
+void Com_CopyToSignal(ComSignal_type *signal, const void *Source);\r
+\r
+/*\r
+ * This function copies numBits bits of data from Source to Destination with the possibility to offset\r
+ * both the source and destination.\r
+ *\r
+ * Return value: the last bit it copies (sign bit).
+ */\r
+uint8 Com_CopyData(void *Destination, const void *Source, uint8 numBits, uint8 destOffset, uint8 sourceOffset);\r
+#endif /* COM_MISC_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+#include "ComM.h"\r
+#include "ComM_BusSm.h"\r
+\r
+void ComM_Init( ComM_ConfigType *config ) {\r
+\r
+ ( void )config;\r
+}\r
+\r
+void ComM_BusSM_ModeIndication(NetworkHandleType Channel,ComM_ModeType ComMode){\r
+\r
+}\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef COMM_H_\r
+#define COMM_H_\r
+\r
+typedef struct {\r
+ void *canIf;\r
+ void *canTp;\r
+ void *Frlf;\r
+ void *LinIf;\r
+ void *LinTp;\r
+ void *PduR;\r
+ void *IPDUM;\r
+ void *Nm;\r
+ void *Com;\r
+ void *Dcm; \r
+} ComM_ConfigType;\r
+\r
+void ComM_Init( ComM_ConfigType *);\r
+#endif /*COMM_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef COMM_BUSSM_H_\r
+#define COMM_BUSSM_H_\r
+\r
+#include "ComStack_Types.h"\r
+#include "ComM_Types.h"\r
+\r
+void ComM_BusSM_ModeIndication(NetworkHandleType Channel,ComM_ModeType ComMode);\r
+\r
+#endif /*COMM_BUSSM_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef COMM_CFG_H_\r
+#define COMM_CFG_H_\r
+\r
+#endif /*COMM_CFG_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef COMM_DCM_H_\r
+#define COMM_DCM_H_\r
+\r
+#endif /*COMM_DCM_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef COMM_ECUM_H_\r
+#define COMM_ECUM_H_\r
+\r
+#endif /*COMM_ECUM_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef COMM_NM_H_\r
+#define COMM_NM_H_\r
+\r
+#endif /*COMM_NM_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+#include "LinIf.h"\r
+#include "LinIf_Types.h"\r
+#include "LinIf_Cbk.h"\r
+#include "LinIf_Cfg.h"\r
+#include "Lin.h"\r
+#include "LinSM_Cbk.h"\r
+#include "PduR_LinIf.h"\r
+#include "Det.h"\r
+\r
+/* Development error macros. */\r
+#if ( LINIF_DEV_ERROR_DETECT == STD_ON )\r
+#define VALIDATE(_exp,_api,_err ) \\r
+ if( !(_exp) ) { \\r
+ Det_ReportError(MODULE_ID_LINIF,0,_api,_err); \\r
+ return; \\r
+ }\r
+\r
+#define VALIDATE_W_RV(_exp,_api,_err,_rv ) \\r
+ if( !(_exp) ) { \\r
+ Det_ReportError(MODULE_ID_LINIF,0,_api,_err); \\r
+ return (_rv); \\r
+ }\r
+#else\r
+#define VALIDATE(_exp,_api,_err )\r
+#define VALIDATE_W_RV(_exp,_api,_err,_rv )\r
+#endif\r
+\r
+typedef enum {\r
+ LINIF_UNINIT,\r
+ LINIF_INIT,\r
+ LINIF_CHANNEL_UNINIT,\r
+ LINIF_CHANNEL_OPERATIONAL,\r
+ LINIF_CHANNEL_SLEEP_TRANS,\r
+ LINIF_CHANNEL_SLEEP,\r
+}LinIf_StatusType;\r
+\r
+static LinIf_StatusType LinIfStatus = LINIF_UNINIT;\r
+static LinIf_StatusType LinIfChannelStatus[LINIF_CONTROLLER_CNT];\r
+\r
+static LinIf_ScheduleTableType *currentSchedule[LINIF_CONTROLLER_CNT];\r
+static uint16 currentIndex[LINIF_CONTROLLER_CNT];\r
+static uint16 currentDelayInTicks[LINIF_CONTROLLER_CNT];\r
+\r
+static boolean newScheduleRequest[LINIF_CONTROLLER_CNT];\r
+static LinIf_SchHandleType newSchedule[LINIF_CONTROLLER_CNT];\r
+\r
+void LinIf_Init( const void* ConfigPtr )\r
+{\r
+ uint8 i;\r
+\r
+ // Initalize driver\r
+ Lin_Init(0);\r
+\r
+ // Call Lin_InitChannel\r
+ for (i=0;i<LINIF_CONTROLLER_CNT;i++)\r
+ {\r
+ Lin_InitChannel(LinIfChannelCfg[i].LinIfChannelId, LinIfChannelCfg[i].LinIfChannelRef);\r
+ LinIfChannelStatus[i] = LINIF_CHANNEL_OPERATIONAL;\r
+ currentSchedule[i] = 0;\r
+ currentIndex[i] = 0;\r
+ currentDelayInTicks[i] = 0;\r
+ newScheduleRequest[i] = FALSE;\r
+ }\r
+ LinIfStatus = LINIF_INIT;\r
+}\r
+\r
+void LinIf_DeInit()\r
+{\r
+ uint8 i;\r
+\r
+ // Call Lin_InitChannel\r
+ for (i=0;i<LINIF_CONTROLLER_CNT;i++)\r
+ {\r
+ Lin_DeInitChannel(LinIfChannelCfg[i].LinIfChannelId);\r
+ }\r
+ // Uninitalize driver\r
+ Lin_DeInit();\r
+\r
+ LinIfStatus = LINIF_UNINIT;\r
+}\r
+\r
+Std_ReturnType LinIf_Transmit(PduIdType LinTxPduId,const PduInfoType* PduInfoPtr)\r
+{\r
+ // Sporadic frames not supported in this release\r
+ //printf("LinIf_Transmit received request. Id: %d, Data: %d\n", LinTxPduId, *(PduInfoPtr->SduDataPtr));\r
+ return E_OK;\r
+}\r
+\r
+\r
+Std_ReturnType LinIf_ScheduleRequest(NetworkHandleType Channel,LinIf_SchHandleType Schedule)\r
+{\r
+ VALIDATE_W_RV( (LinIfStatus != LINIF_UNINIT), LINIF_SCHEDULEREQUEST_SERVICE_ID, LINIF_E_UNINIT, E_NOT_OK);\r
+ VALIDATE_W_RV( (Channel < LINIF_CONTROLLER_CNT), LINIF_SCHEDULEREQUEST_SERVICE_ID, LINIF_E_NONEXISTENT_CHANNEL, E_NOT_OK);\r
+ VALIDATE_W_RV( (LinIfChannelStatus[Channel] != LINIF_CHANNEL_SLEEP && LinIfChannelStatus[Channel] != LINIF_CHANNEL_SLEEP_TRANS), LINIF_SCHEDULEREQUEST_SERVICE_ID, LINIF_E_SCHEDULE_REQUEST_ERROR, E_NOT_OK);\r
+\r
+ newScheduleRequest[Channel] = TRUE;\r
+ newSchedule[Channel] = Schedule;\r
+ return E_OK;\r
+}\r
+\r
+\r
+Std_ReturnType LinIf_GotoSleep(NetworkHandleType Channel)\r
+{\r
+ VALIDATE_W_RV( (LinIfStatus != LINIF_UNINIT), LINIF_GOTOSLEEP_SERVICE_ID, LINIF_E_UNINIT, E_NOT_OK);\r
+ VALIDATE_W_RV( (Channel < LINIF_CONTROLLER_CNT), LINIF_GOTOSLEEP_SERVICE_ID, LINIF_E_NONEXISTENT_CHANNEL, E_NOT_OK);\r
+\r
+ if (LinIfChannelStatus[Channel] == LINIF_CHANNEL_OPERATIONAL) {\r
+ LinIfChannelStatus[Channel] = LINIF_CHANNEL_SLEEP_TRANS;\r
+ }\r
+ return E_OK;\r
+}\r
+\r
+\r
+Std_ReturnType LinIf_WakeUp(NetworkHandleType Channel)\r
+{\r
+ VALIDATE_W_RV( (LinIfStatus != LINIF_UNINIT), LINIF_WAKEUP_SERVICE_ID, LINIF_E_UNINIT, E_NOT_OK);\r
+ VALIDATE_W_RV( (Channel < LINIF_CONTROLLER_CNT), LINIF_WAKEUP_SERVICE_ID, LINIF_E_NONEXISTENT_CHANNEL, E_NOT_OK);\r
+\r
+ if (LinIfChannelStatus[Channel] == LINIF_CHANNEL_SLEEP) {\r
+ Lin_WakeUp(LinIfChannelCfg[Channel].LinIfChannelId);\r
+ currentIndex[Channel] = 0;\r
+ currentDelayInTicks[Channel] = 0;\r
+ }\r
+ // LINIF432: The function LinIf_WakeUp shall do nothing and return E_OK when the\r
+ // referenced channel is not in the sleep state.\r
+ else{\r
+ LinIfChannelStatus[Channel] = LINIF_CHANNEL_OPERATIONAL;\r
+ LinSM_WakeUp_Confirmation(Channel, TRUE);\r
+ }\r
+ return E_OK;\r
+}\r
+\r
+void LinIf_MainFunction()\r
+{\r
+ uint8 chIndex;\r
+ uint8 buf[8];\r
+ uint8 *Lin_SduPtr;\r
+\r
+ if (LinIfStatus == LINIF_UNINIT) {\r
+ return;\r
+ }\r
+\r
+ for (chIndex = 0; chIndex < LINIF_CONTROLLER_CNT; chIndex++)\r
+ {\r
+ // Check if there are any pending sleep transitions\r
+ if (LinIfChannelStatus[chIndex] == LINIF_CHANNEL_SLEEP_TRANS) {\r
+ if (Lin_GetStatus(LinIfChannelCfg[chIndex].LinIfChannelId, &Lin_SduPtr) != LIN_CH_SLEEP){\r
+ Lin_GoToSleep(LinIfChannelCfg[chIndex].LinIfChannelId);\r
+ }\r
+ else\r
+ {\r
+ LinIfChannelStatus[chIndex] = LINIF_CHANNEL_SLEEP;\r
+ LinSM_GotoSleep_Confirmation(chIndex, TRUE);\r
+ }\r
+ // Set NULL schedule at sleep\r
+ currentIndex[chIndex] = 0;\r
+ currentDelayInTicks[chIndex] = 0;\r
+ currentSchedule[chIndex] = (LinIf_ScheduleTableType *)&LinIfScheduleTableCfg[0];\r
+ continue;\r
+ }\r
+\r
+ // Check if there are any wakeup transitions\r
+ if ((LinIfChannelStatus[chIndex] == LINIF_CHANNEL_SLEEP) &&\r
+ (Lin_GetStatus(LinIfChannelCfg[chIndex].LinIfChannelId, &Lin_SduPtr) != LIN_CH_SLEEP)) {\r
+ LinIfChannelStatus[chIndex] = LINIF_CHANNEL_OPERATIONAL;\r
+ LinSM_WakeUp_Confirmation(chIndex, TRUE);\r
+ }\r
+\r
+ // Normal scheduling\r
+ if(currentDelayInTicks[chIndex] > 0){\r
+ // Not time for sending yet\r
+ currentDelayInTicks[chIndex]--;\r
+ continue;\r
+ }\r
+\r
+\r
+ if(LinIfChannelStatus[chIndex] == LINIF_CHANNEL_OPERATIONAL) {\r
+ //Check if NULL schedule is present otherwise check status of last sent\r
+ if(!(currentSchedule[chIndex] == 0 || currentSchedule[chIndex]->LinIfEntry == 0)){\r
+ LinIfEntryType *ptrEntry = (LinIfEntryType *)¤tSchedule[chIndex]->LinIfEntry[currentIndex[chIndex]];\r
+ LinIf_FrameType *ptrFrame = (LinIf_FrameType *)&LinIfFrameCfg[ptrEntry->LinIfFrameRef];\r
+\r
+ // Handle received and sent frames\r
+ if(ptrFrame->LinIfPduDirection == LinIfRxPdu){\r
+ if(Lin_GetStatus(LinIfChannelCfg[chIndex].LinIfChannelId, &Lin_SduPtr) == LIN_RX_OK){\r
+ PduR_LinIfRxIndication(ptrFrame->LinIfTxTargetPduId,Lin_SduPtr);\r
+ }else{// RX_ERROR or BUSY\r
+ Det_ReportError(MODULE_ID_LINIF,0,LINIF_MAINFUNCTION_SERVICE_ID,LINIF_E_RESPONSE);\r
+ }\r
+ } else if(ptrFrame->LinIfPduDirection == LinIfTxPdu){\r
+ Lin_StatusType status = Lin_GetStatus(LinIfChannelCfg[chIndex].LinIfChannelId, &Lin_SduPtr);\r
+ if(status == LIN_TX_OK){\r
+ PduR_LinIfTxConfirmation(ptrFrame->LinIfTxTargetPduId);\r
+ }else{// TX_ERROR or BUSY\r
+ Det_ReportError(MODULE_ID_LINIF,0,LINIF_MAINFUNCTION_SERVICE_ID,LINIF_E_RESPONSE);\r
+ }\r
+ }\r
+ // Update index after getting status of last frame\r
+ currentIndex[chIndex] = (currentIndex[chIndex] + 1) % currentSchedule[chIndex]->LinIfNofEntries;\r
+\r
+ }\r
+\r
+ //Set new schedule if ordered\r
+ if(newScheduleRequest[chIndex] == TRUE){\r
+ currentSchedule[chIndex] = (LinIf_ScheduleTableType *)&LinIfScheduleTableCfg[newSchedule[chIndex]];\r
+ currentIndex[chIndex] = 0;\r
+ newScheduleRequest[chIndex]=FALSE;\r
+ LinSM_ScheduleRequest_Confirmation(chIndex);\r
+ }\r
+\r
+ // Handle new transmissions\r
+ if(!(currentSchedule[chIndex] == 0 || currentSchedule[chIndex]->LinIfEntry == 0)){\r
+ Lin_PduType PduInfo;\r
+ LinIfEntryType *ptrEntry = (LinIfEntryType *)¤tSchedule[chIndex]->LinIfEntry[currentIndex[chIndex]];\r
+ LinIf_FrameType *ptrFrame = (LinIf_FrameType *)&LinIfFrameCfg[ptrEntry->LinIfFrameRef];\r
+\r
+ // Only UNCONDITIONAL frames is supported in first version\r
+ if (ptrFrame->LinIfFrameType == UNCONDITIONAL){\r
+ // SendHeader\r
+ if(ptrFrame->LinIfChecksumType==ENHANCED){\r
+ PduInfo.Cs = LIN_ENHANCED_CS;\r
+ }else{\r
+ PduInfo.Cs = LIN_CLASSIC_CS;\r
+ }\r
+ PduInfo.Pid = ptrFrame->LinIfPid;\r
+ PduInfo.SduPtr = buf; // Data will be added in PduR_LinIfTriggerTransmit\r
+ PduInfo.DI = ptrFrame->LinIfLength;\r
+ if(ptrFrame->LinIfPduDirection == LinIfTxPdu){\r
+ PduInfo.Drc = LIN_MASTER_RESPONSE;\r
+ }else{\r
+ PduInfo.Drc = LIN_SLAVE_RESPONSE;\r
+ }\r
+\r
+\r
+ // Maybe send response also\r
+ if(ptrFrame->LinIfPduDirection == LinIfTxPdu){\r
+ //TX\r
+ PduR_LinIfTriggerTransmit(ptrFrame->LinIfTxTargetPduId,PduInfo.SduPtr);\r
+ Lin_SendHeader(LinIfChannelCfg[chIndex].LinIfChannelId, &PduInfo);\r
+ Lin_SendResponse(LinIfChannelCfg[chIndex].LinIfChannelId, &PduInfo);\r
+ }\r
+ else {\r
+ //RX\r
+ Lin_SendHeader(LinIfChannelCfg[chIndex].LinIfChannelId, &PduInfo);\r
+ }\r
+ }\r
+\r
+ // Set new delay\r
+ currentDelayInTicks[chIndex] = ptrEntry->LinIfDelay / LinIfGlobalConfig.LinIfTimeBase - 1;\r
+ }\r
+ }\r
+ }\r
+ LinSM_TimerTick();\r
+}\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include "Std_Types.h"\r
+#include "LinIf.h"\r
+#include "LinSM.h"\r
+#include "LinSM_Cfg.h"\r
+#include "Lin_Cfg.h"\r
+#include "LinSM_Cbk.h"\r
+#include "LinIf_Types.h"\r
+#include "Com.h"\r
+#include "ComM_Types.h"\r
+#include "ComStack_Types.h"\r
+#include "Com_Types.h"\r
+#include "ComM_BusSm.h"\r
+#include "Det.h"\r
+#include "Mcu.h"\r
+#include <stdlib.h>\r
+#include <string.h>\r
+\r
+/* Development error macros. */\r
+#if ( LINSM_DEV_ERROR_DETECT == STD_ON )\r
+#define VALIDATE(_exp,_api,_err ) \\r
+ if( !(_exp) ) { \\r
+ Det_ReportError(MODULE_ID_LINSM,0,_api,_err); \\r
+ return; \\r
+ }\r
+\r
+#define VALIDATE_W_RV(_exp,_api,_err,_rv ) \\r
+ if( !(_exp) ) { \\r
+ Det_ReportError(MODULE_ID_LINSM,0,_api,_err); \\r
+ return (_rv); \\r
+ }\r
+#else\r
+#define VALIDATE(_exp,_api,_err )\r
+#define VALIDATE_W_RV(_exp,_api,_err,_rv )\r
+#endif\r
+\r
+static uint8 ScheduleRequestTimer[LINIF_CONTROLLER_CNT];\r
+static uint8 GoToSleepTimer[LINIF_CONTROLLER_CNT];\r
+static uint8 WakeUpTimer[LINIF_CONTROLLER_CNT];\r
+\r
+static LinSM_StatusType LinSMStatus = LINSM_UNINIT;\r
+static LinSM_StatusType LinSMChannelStatus[LINIF_CONTROLLER_CNT];\r
+\r
+void LinSM_Init(const void* ConfigPtr)\r
+{\r
+ uint8 i;\r
+\r
+ for (i=0; i<LINIF_CONTROLLER_CNT; i++)\r
+ {\r
+ LinSMChannelStatus[i] = LINSM_NO_COM;\r
+ ScheduleRequestTimer[i] = 0;\r
+ GoToSleepTimer[i] = 0;\r
+ WakeUpTimer[i] = 0;\r
+ }\r
+\r
+ LinIf_Init(0);\r
+ LinSMStatus = LINSM_INIT;\r
+}\r
+\r
+void LinSM_DeInit()\r
+{\r
+ LinIf_DeInit();\r
+ LinSMStatus = LINSM_UNINIT;\r
+}\r
+\r
+Std_ReturnType LinSM_ScheduleRequest(NetworkHandleType channel,LinIf_SchHandleType schedule)\r
+{\r
+ VALIDATE_W_RV( (LinSMStatus != LINSM_UNINIT), LINSM_SCHEDULE_REQUEST_SERVICE_ID, LINSM_E_UNINIT, E_NOT_OK);\r
+ VALIDATE_W_RV( (channel < LINIF_CONTROLLER_CNT), LINSM_SCHEDULE_REQUEST_SERVICE_ID, LINSM_E_NOXEXISTENT_CHANNEL, E_NOT_OK);\r
+ VALIDATE_W_RV( (LinSMChannelStatus[channel] == LINSM_RUN_SCHEDULE), LINSM_SCHEDULE_REQUEST_SERVICE_ID, LINSM_E_NOT_IN_RUN_SCHEDULE, E_NOT_OK);\r
+ VALIDATE_W_RV( (schedule < LINIF_SCH_CNT), LINSM_SCHEDULE_REQUEST_SERVICE_ID, LINSM_E_PARAMETER, E_NOT_OK);\r
+\r
+ ScheduleRequestTimer[channel]=LINSM_SCHEDULE_REQUEST_TIMEOUT;\r
+ return LinIf_ScheduleRequest(channel, schedule);\r
+}\r
+\r
+Std_ReturnType LinSM_GetCurrentComMode(NetworkHandleType network,ComM_ModeType* mode)\r
+{\r
+ VALIDATE_W_RV( (LinSMStatus != LINSM_UNINIT), LINSM_GET_CURRENT_COM_MODE_SERVICE_ID, LINSM_E_UNINIT, E_NOT_OK);\r
+ VALIDATE_W_RV( (network < LINIF_CONTROLLER_CNT), LINSM_GET_CURRENT_COM_MODE_SERVICE_ID, LINSM_E_NOXEXISTENT_CHANNEL, E_NOT_OK);\r
+ VALIDATE_W_RV( (mode != NULL), LINSM_GET_CURRENT_COM_MODE_SERVICE_ID, LINSM_E_PARAMETER_POINTER, E_NOT_OK);\r
+\r
+ *mode= LinSMChannelStatus[network];\r
+ return E_OK;\r
+}\r
+\r
+Std_ReturnType LinSM_RequestComMode(NetworkHandleType network,ComM_ModeType mode)\r
+{\r
+ Std_ReturnType res = E_NOT_OK;\r
+ VALIDATE_W_RV( (LinSMStatus != LINSM_UNINIT), LINSM_REQUEST_COM_MODE_SERVICE_ID, LINSM_E_UNINIT, E_NOT_OK);\r
+ VALIDATE_W_RV( (network < LINIF_CONTROLLER_CNT), LINSM_REQUEST_COM_MODE_SERVICE_ID, LINSM_E_NOXEXISTENT_CHANNEL, E_NOT_OK);\r
+\r
+ switch(mode)\r
+ {\r
+ case COMM_NO_COMMUNICATION:\r
+ if (E_OK == LinIf_GotoSleep(network)){\r
+ LinSMChannelStatus[network] = LINSM_GOTO_SLEEP;\r
+ GoToSleepTimer[network]=LINSM_GOTO_SLEEP_TIMEOUT;\r
+ res = E_OK;\r
+ }\r
+ break;\r
+ case COMM_SILENT_COMMUNICATION:\r
+ // Standard say nothing about this case.\r
+ break;\r
+ case COMM_FULL_COMMUNICATION:\r
+ WakeUpTimer[network]=LINSM_WAKEUP_TIMEOUT; //should be done here since some implementations will confirm immediatly\r
+ if (E_OK == LinIf_WakeUp(network)){\r
+ res = E_OK;\r
+ }\r
+ else\r
+ {\r
+ WakeUpTimer[network]=0;\r
+ }\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+ return res;\r
+}\r
+\r
+void LinSM_ScheduleRequest_Confirmation(NetworkHandleType channel){\r
+ Com_PduGroupIdType IpduGroupId = 0;\r
+ VALIDATE( (LinSMStatus != LINSM_UNINIT), LINSM_SCHEDULE_REQUEST_CONF_SERVICE_ID, LINSM_E_UNINIT);\r
+ VALIDATE( (channel < LINIF_CONTROLLER_CNT), LINSM_SCHEDULE_REQUEST_CONF_SERVICE_ID, LINSM_E_NOXEXISTENT_CHANNEL);\r
+\r
+ if(ScheduleRequestTimer[channel]!=0){\r
+ Com_IpduGroupStop(IpduGroupId);\r
+ Com_IpduGroupStart(IpduGroupId,FALSE);\r
+ ScheduleRequestTimer[channel]=0;\r
+ }\r
+}\r
+\r
+void LinSM_WakeUp_Confirmation(NetworkHandleType channel,boolean success){\r
+ VALIDATE( (LinSMStatus != LINSM_UNINIT), LINSM_WAKEUP_CONF_SERVICE_ID, LINSM_E_UNINIT);\r
+ VALIDATE( (channel < LINIF_CONTROLLER_CNT), LINSM_WAKEUP_CONF_SERVICE_ID, LINSM_E_NOXEXISTENT_CHANNEL);\r
+\r
+ if(WakeUpTimer[channel]!=0){\r
+ WakeUpTimer[channel]=0;\r
+ ComM_BusSM_ModeIndication(channel,COMM_FULL_COMMUNICATION);\r
+ LinSMChannelStatus[channel] = LINSM_RUN_SCHEDULE;\r
+ }\r
+}\r
+\r
+void LinSM_GotoSleep_Confirmation(NetworkHandleType channel,boolean success){\r
+ VALIDATE( (LinSMStatus != LINSM_UNINIT), LINSM_GOTO_SLEEP_CONF_SERVICE_ID, LINSM_E_UNINIT);\r
+ VALIDATE( (channel < LINIF_CONTROLLER_CNT), LINSM_GOTO_SLEEP_CONF_SERVICE_ID, LINSM_E_NOXEXISTENT_CHANNEL);\r
+\r
+ if(GoToSleepTimer[channel]!=0){\r
+ GoToSleepTimer[channel]=0;\r
+ LinSMChannelStatus[channel] = LINSM_NO_COM;\r
+ ComM_BusSM_ModeIndication(channel,COMM_NO_COMMUNICATION);\r
+ }\r
+}\r
+\r
+void LinSM_TimerTick()\r
+{\r
+ uint8 channel;\r
+ for(channel=0;channel<LINIF_CONTROLLER_CNT;channel++){\r
+ // Check timers\r
+ if(ScheduleRequestTimer[channel] > 0){\r
+ ScheduleRequestTimer[channel]--;\r
+ if(ScheduleRequestTimer[channel]==0){\r
+ Det_ReportError(MODULE_ID_LINSM,0,LINSM_REQUEST_COM_MODE_SERVICE_ID,LINSM_E_CONFIRMATION_TIMEOUT);\r
+ LinSMChannelStatus[channel] = LINSM_NO_COM;\r
+ }\r
+ }\r
+ if(GoToSleepTimer[channel] > 0){\r
+ GoToSleepTimer[channel]--;\r
+ if(GoToSleepTimer[channel]==0){\r
+ Det_ReportError(MODULE_ID_LINSM,0,LINSM_REQUEST_COM_MODE_SERVICE_ID,LINSM_E_CONFIRMATION_TIMEOUT);\r
+ LinSMChannelStatus[channel] = LINSM_NO_COM;\r
+ }\r
+ }\r
+ if(WakeUpTimer[channel] > 0){\r
+ WakeUpTimer[channel]--;\r
+ if(WakeUpTimer[channel]==0){\r
+ Det_ReportError(MODULE_ID_LINSM,0,LINSM_REQUEST_COM_MODE_SERVICE_ID,LINSM_E_CONFIRMATION_TIMEOUT);\r
+ LinSMChannelStatus[channel] = LINSM_NO_COM;\r
+ }\r
+ }\r
+ }\r
+}\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+#include <stdlib.h>\r
+#include <string.h>\r
+\r
+\r
+#include "Det.h"\r
+#include "PduR.h"\r
+#include "PduR_Com.h"\r
+#include "PduR_CanIf.h"\r
+#include "PduR_LinIf.h"\r
+#include "PduR_Ipdum.h"\r
+#include "Mcu.h"\r
+#include "Trace.h"\r
+\r
+/*\r
+ * The state of the PDU router.
+ */\r
+PduR_StateType PduRState = PDUR_UNINIT;\r
+\r
+const PduR_PBConfigType * PduRConfig;\r
+\r
+\r
+/* ############### Zero Cost Operation Mode ############# */\r
+/* Only define the following functions if zero cost operation\r
+ * mode is not used! They are defined as macros in PduR.h otherwise. */\r
+#ifndef PDUR_ZERO_COST_OPERATION\r
+\r
+/*\r
+ * Initializes the PDU Router.
+ */\r
+void PduR_Init (const PduR_PBConfigType* ConfigPtr) {\r
+\r
+ //Enter(0);\r
+\r
+ // Make sure the PDU Router is uninitialized.\r
+ // Otherwise raise an error.\r
+ if (PduRState != PDUR_UNINIT) {\r
+ // Raise error and return.\r
+ DET_REPORTERROR(PDUR_MODULE_ID, PDUR_INSTANCE_ID, 0x00, PDUR_E_INVALID_REQUEST);\r
+ return;\r
+ }\r
+\r
+ if (ConfigPtr == NULL) {\r
+ DET_REPORTERROR(PDUR_MODULE_ID, PDUR_INSTANCE_ID, 0x00, PDUR_E_CONFIG_PTR_INVALID);\r
+ return;\r
+ } else {\r
+ PduRConfig = ConfigPtr;\r
+ }\r
+\r
+ // Start initialization!\r
+ DEBUG(DEBUG_LOW,"--Initialization of PDU router--\n");\r
+\r
+ uint8 failed = 0;\r
+\r
+ // TODO Initialize DestPduIds!!!!!\r
+\r
+ // TODO Initialize NRoutingPaths.\r
+\r
+ // Initialize buffers.\r
+ int bufferNr = 0;\r
+ int i = 0;\r
+ PduRRoutingPath_type *path;\r
+ for (i = 0; !PduRConfig->PduRRoutingTable->PduRRoutingPath[i].PduREcoreEOL && !failed; i++) {\r
+ PduRConfig->PduRRoutingTable->NRoutingPaths++;\r
+ path = &PduRConfig->PduRRoutingTable->PduRRoutingPath[i];\r
+\r
+ if (path->PduRDestPdu.DataProvision != PDUR_NO_PROVISION) {\r
+ // Allocate memory for new buffer.\r
+ PduRTxBuffer_type *buffer = path->PduRDestPdu.TxBufferRef;\r
+\r
+ if (bufferNr >= PDUR_MAX_TX_BUFFER_NUMBER) {\r
+ DEBUG(DEBUG_LOW,"PduR_Init: Initialization of buffer failed due to erroneous configuration.\nThe number of buffer exceeded the maximum number of allowed buffers.\n");\r
+ failed = 1;\r
+ break;\r
+ }\r
+ if ((buffer->Buffer = (uint8 *)malloc(buffer->Depth * sizeof(uint8) * path->SduLength)) == 0) {\r
+ DEBUG(DEBUG_LOW,"PduR_Init: Initialization of buffer failed. Buffer space could not be allocated for buffer number %d\n", bufferNr);\r
+ failed = 1;\r
+ break;\r
+ }\r
+\r
+ buffer->First = buffer->Buffer;\r
+ buffer->Last = buffer->Buffer;\r
+\r
+\r
+ // Initialize the new buffer.\r
+ buffer->BufferId = i; // Set buffer id.\r
+ buffer->BufferType = path->PduRDestPdu.DataProvision; // Set buffer data provision mode.\r
+ buffer->Length = path->SduLength; // Set buffer sdu length.\r
+\r
+ if (path->PduRDestPdu.DataProvision == PDUR_TRIGGER_TRANSMIT) {\r
+ //memcpy(buffer->First, path->PduRDefaultValue.PduRDefaultValueElement->DefaultValueElement,path->SduLength);\r
+ PduR_BufferQueue(buffer, path->PduRDefaultValue.PduRDefaultValueElement->DefaultValueElement);\r
+ }\r
+\r
+ // Save pointer to the new buffer.\r
+ //PduR_RTable_LoIf.RoutingTable[i].TxBufferRef = &PduRBuffers[bufferNr];\r
+\r
+ DEBUG(DEBUG_LOW,"Initialized buffer %d. Id: %d, Type: %d, Depth: %d\n", bufferNr, buffer->BufferId, buffer->BufferType, buffer->Depth);\r
+ bufferNr++;\r
+ }\r
+ }\r
+\r
+ if (failed) {\r
+ // TODO Report PDUR_E_INIT_FAILED to Dem.\r
+ PduRState = PDUR_REDUCED;\r
+ DEBUG(DEBUG_LOW,"--Initialization of PDU router failed--\n");\r
+\r
+\r
+ } else {\r
+ // The initialization succeeded!\r
+ PduRState = PDUR_ONLINE;\r
+ DEBUG(DEBUG_LOW,"--Initialization of PDU router completed --\n");\r
+\r
+ }\r
+}\r
+\r
+void PduR_BufferInc(PduRTxBuffer_type *Buffer, uint8 **ptr) {\r
+ (*ptr) = (*ptr) + Buffer->Length;\r
+\r
+ // TODO make more efficient without multiplication.\r
+ if (*ptr >= Buffer->Buffer + Buffer->Depth * Buffer->Length) {\r
+ *ptr = Buffer->Buffer;\r
+ }\r
+ //*val = (*val + 1) % Buffer->Depth;\r
+}\r
+\r
+void PduR_BufferQueue(PduRTxBuffer_type *Buffer, const uint8 * SduPtr) {\r
+ imask_t state = McuE_EnterCriticalSection();\r
+\r
+ if (PduR_BufferIsFull(Buffer)) { // Buffer is full\r
+ PduR_BufferFlush(Buffer);\r
+ DET_REPORTERROR(PDUR_MODULE_ID, PDUR_INSTANCE_ID, 0x00, PDUR_E_PDU_INSTANCE_LOST);\r
+\r
+\r
+ } else {\r
+ // Copy data to last place in buffer\r
+ memcpy(Buffer->Last, SduPtr, sizeof(uint8) * Buffer->Length);\r
+\r
+ PduR_BufferInc(Buffer, &Buffer->Last);\r
+ Buffer->NrItems++;\r
+ DEBUG(DEBUG_LOW,"\tBuffer %d: Queued data %d. Status: NrItems %d, First %d, Last %d\n", Buffer->BufferId, *SduPtr, Buffer->NrItems, *Buffer->First, *Buffer->Last);\r
+\r
+ }\r
+ McuE_ExitCriticalSection(state);\r
+}\r
+\r
+void PduR_BufferDeQueue(PduRTxBuffer_type *Buffer, uint8 *SduPtr) {\r
+ imask_t state = McuE_EnterCriticalSection();\r
+\r
+ if (Buffer->NrItems > 0) {\r
+ memcpy(SduPtr, Buffer->First, sizeof(uint8) * Buffer->Length);\r
+ PduR_BufferInc(Buffer, &Buffer->First);\r
+ Buffer->NrItems--;\r
+ DEBUG(DEBUG_LOW,"\tBuffer %d: DeQueueing data. Status: NrItems %d, First %d, Last %d\n", Buffer->BufferId, Buffer->NrItems, *Buffer->First, *Buffer->Last);\r
+ } else {\r
+ DEBUG(DEBUG_LOW,"\tBuffer %d: Buffer is empty, nothing to dequeue!\n", Buffer->BufferId);\r
+ }\r
+ McuE_ExitCriticalSection(state);\r
+}\r
+\r
+void PduR_BufferFlush(PduRTxBuffer_type *Buffer) {\r
+ DEBUG(DEBUG_LOW,"\tBuffer %d: Flushing!\n", Buffer->BufferId);\r
+ imask_t state = McuE_EnterCriticalSection();\r
+ Buffer->NrItems = 0;\r
+ Buffer->First = Buffer->Buffer;\r
+ Buffer->Last = Buffer->Buffer;\r
+ Buffer->TxConfP = 0;\r
+ McuE_ExitCriticalSection(state);\r
+}\r
+\r
+uint8 PduR_BufferIsFull(PduRTxBuffer_type *Buffer) {\r
+ imask_t state = McuE_EnterCriticalSection();\r
+ if (Buffer->NrItems < Buffer->Depth) {\r
+ return 0;\r
+ } else {\r
+ return 1;\r
+ }\r
+ McuE_ExitCriticalSection(state);\r
+}\r
+\r
+\r
+#ifdef PDUR_VERSION_INFO_API\r
+void PduR_GetVersionInfo (Std_VersionInfoType* versionInfo){\r
+ versionInfo->moduleID = (uint16)PDUR_MODULE_ID;\r
+ versionInfo->vendorID = (uint16)1;\r
+\r
+ // TODO Add vendor specific version numbers.\r
+}\r
+#endif\r
+\r
+uint32 PduR_GetConfigurationId () {\r
+ //DevCheck(0,1,0x18,E_NOT_OK);\r
+ return PduRConfig->PduRConfigurationId;\r
+}\r
+#endif // End of not Zero Cost Operation Mode\r
+\r
+Std_ReturnType PduR_CancelTransmitRequest(PduR_CancelReasonType PduCancelReason, PduIdType PduId) {\r
+ Enter(PduId,E_NOT_OK);\r
+ // TODO Implement!\r
+\r
+ Exit();\r
+ return E_NOT_OK;\r
+}\r
+\r
+void PduR_ChangeParameterRequest(PduR_ParameterValueType PduParameterValue, PduIdType PduId) {\r
+ Enter(0);\r
+ // TODO Implement!\r
+\r
+}\r
+\r
+\r
+// If we are using the simulator CANIF and LINIF are not available.\r
+// Therefore the functions needed by the functions pointer tables below needs to be stubbed.\r
+#if !defined(USE_CANIF)\r
+Std_ReturnType CanIf_Transmit(PduIdType CanTxPduId, const PduInfoType *PduInfoPtr) {\r
+ // Just a stub\r
+ return E_OK;\r
+}\r
+\r
+// If CAN are available we include these functions directly\r
+#else\r
+#include "CanIf.h"\r
+#endif\r
+\r
+\r
+#if !defined(USE_LINIF)\r
+Std_ReturnType LinIf_Transmit(PduIdType LinTxPduId,const PduInfoType* PduInfoPtr) {\r
+ // Just a stub\r
+ return E_OK;\r
+}\r
+\r
+// If LIN are available we include these functions directly\r
+#else\r
+#include "LinIf.h"\r
+#endif\r
+\r
+\r
+\r
+PduR_FctPtrType PduR_StdLinFctPtrs = {\r
+ .TargetIndicationFctPtr = Com_RxIndication,\r
+ .TargetTransmitFctPtr = LinIf_Transmit,\r
+ .TargetConfirmationFctPtr = Com_TxConfirmation,\r
+ .TargetTriggerTransmitFctPtr = Com_TriggerTransmit,\r
+};\r
+\r
+PduR_FctPtrType PduR_StdCanFctPtrs = {\r
+ .TargetIndicationFctPtr = Com_RxIndication,\r
+ .TargetTransmitFctPtr = CanIf_Transmit,\r
+ .TargetConfirmationFctPtr = Com_TxConfirmation,\r
+ .TargetTriggerTransmitFctPtr = Com_TriggerTransmit,\r
+};\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef _PDUR_H_\r
+#define _PDUR_H_\r
+\r
+#define PDUR_VENDOR_ID 1\r
+#define PDUR_AR_MAJOR_VERSION 2\r
+#define PDUR_AR_MINOR_VERSION 2\r
+#define PDUR_AR_PATCH_VERSION 2\r
+#define PDUR_SW_MAJOR_VERSION 3\r
+#define PDUR_SW_MINOR_VERSION 0\r
+#define PDUR_SW_PATCH_VERSION 2\r
+\r
+#include "PduR_Cfg.h"\r
+#include "PduR_Types.h"\r
+\r
+#ifndef PDUR_ZERO_COST_OPERATION\r
+#include "PduR_PbCfg.h"\r
+#endif\r
+\r
+#include "PduR_Com.h"\r
+#include "PduR_CanIf.h"\r
+#include "PduR_LinIf.h"\r
+\r
+/* Contain the current state of the PDU router. The router is uninitialized\r
+ * until PduR_Init has been run.\r
+ */\r
+PduR_StateType PduRState;\r
+\r
+extern const PduR_PBConfigType *PduRConfig;\r
+\r
+#ifdef PDUR_PRINT_DEBUG_STATEMENTS\r
+/* A simple debug macro to be used instead of printf(). This way all print\r
+ * statements are turned off if PDUR_PRINT_DEBUG_STATEMENTS is undefined.\r
+ */\r
+//#include <stdio.h>\r
+#define debug(...) simple_printf(__VA_ARGS__)\r
+\r
+#else\r
+#define debug(...)\r
+\r
+#endif\r
+\r
+#ifdef PDUR_REENTRANCY_CHECK\r
+/*\r
+ * The macros Enter and Exit performs the ReEntrancy check of the PDU router functions.\r
+ * Enter shall be called at the beginning of the function with the current PduId and the wanted\r
+ * return value (possibly nothing for void methods).\r
+ * Exit should be called at the end of the function where reentrancy is desirable.\r
+ */\r
+#define Enter(PduId,...) \\r
+ static uint8 entered;\\r
+ static PduIdType enteredId;\\r
+ if (entered && enteredId == PduId) { \\r
+ debug("Function already entered. EnteredId: %d, CurrentId: %d. Exiting.\n", enteredId, PduId); \\r
+ return __VA_ARGS__; \\r
+ } else { \\r
+ entered = 1; \\r
+ enteredId = PduId; \\r
+ } \\r
+\r
+\r
+#define Exit() \\r
+ entered = 0; \\r
+\r
+#else\r
+#define Enter(...)\r
+#define Exit()\r
+#endif\r
+\r
+#ifdef PDUR_DEV_ERROR_DETECT\r
+\r
+#undef DET_REPORTERROR\r
+#define DET_REPORTERROR(_x,_y,_z,_q) Det_ReportError(_x,_y,_z,_q)\r
+\r
+// Define macro for state, parameter and data pointer checks.\r
+// TODO Implement data range check if needed.\r
+#define DevCheck(PduId,PduPtr,ApiId,...) \\r
+ if (PduRState == PDUR_UNINIT || PduRState == PDUR_REDUCED) { \\r
+ DET_REPORTERROR(PDUR_MODULE_ID, PDUR_INSTANCE_ID, ApiId, PDUR_E_INVALID_REQUEST); \\r
+ DEBUG(DEBUG_LOW,"PDU Router not initialized. Routing request ignored.\n"); \\r
+ Exit(); \\r
+ return __VA_ARGS__; \\r
+ } \\r
+ if (PduPtr == 0 && PDUR_DEV_ERROR_DETECT) { \\r
+ DET_REPORTERROR(PDUR_MODULE_ID, PDUR_INSTANCE_ID, ApiId, PDUR_E_DATA_PTR_INVALID); \\r
+ Exit(); \\r
+ return __VA_ARGS__; \\r
+ } \\r
+ if ((PduId >= PduRConfig->PduRRoutingTable->NRoutingPaths) && PDUR_DEV_ERROR_DETECT) { \\r
+ DET_REPORTERROR(PDUR_MODULE_ID, PDUR_INSTANCE_ID, ApiId, PDUR_E_PDU_ID_INVALID); \\r
+ Exit(); \\r
+ return __VA_ARGS__; \\r
+ } \\r
+\r
+\r
+#else\r
+#undef DET_REPORTERROR\r
+#define DET_REPORTERROR(_x,_y,_z,_q)\r
+#define DevCheck(...)\r
+\r
+#endif\r
+\r
+Std_ReturnType PduR_CancelTransmitRequest(\r
+ PduR_CancelReasonType PduCancelReason, PduIdType PduId);\r
+void PduR_ChangeParameterRequest(PduR_ParameterValueType PduParameterValue,\r
+ PduIdType PduId);\r
+\r
+/* Zero Cost Operation function definitions\r
+ * These macros replaces the original functions if zero cost\r
+ * operation is desired. */\r
+#ifdef PDUR_ZERO_COST_OPERATION\r
+\r
+#define PduR_Init(...)\r
+#define PduR_GetVersionInfo(...)\r
+#define PduR_GetConfigurationId(...) 0\r
+\r
+#else // Not zero cost operation\r
+void PduR_Init(const PduR_PBConfigType* ConfigPtr);\r
+void PduR_GetVersionInfo(Std_VersionInfoType* versionInfo);\r
+uint32 PduR_GetConfigurationId();\r
+\r
+void PduR_BufferQueue(PduRTxBuffer_type *Buffer, const uint8 * SduPtr);\r
+void PduR_BufferDeQueue(PduRTxBuffer_type *Buffer, uint8 *SduPtr);\r
+void PduR_BufferFlush(PduRTxBuffer_type *Buffer);\r
+uint8 PduR_BufferIsFull(PduRTxBuffer_type *Buffer);\r
+\r
+/*\r
+ * Macros\r
+ */\r
+#define setTxConfP(R) R->PduRDestPdu.TxBufferRef->TxConfP = 1\r
+#define clearTxConfP(R) R->PduRDestPdu.TxBufferRef->TxConfP = 0\r
+\r
+#endif\r
+\r
+extern PduR_FctPtrType PduR_StdCanFctPtrs;\r
+extern PduR_FctPtrType PduR_StdLinFctPtrs;\r
+\r
+#endif /* _PDUR_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include "Det.h"\r
+#include "PduR_CanIf.h"\r
+#include "PduR_If.h"\r
+#include "Trace.h"\r
+\r
+#ifndef PDUR_ZERO_COST_OPERATION\r
+#ifdef PDUR_CANIF_SUPPORT\r
+\r
+\r
+void PduR_CanIfRxIndication(PduIdType CanRxPduId,const uint8* CanSduPtr) {\r
+ Enter(CanRxPduId);\r
+ DevCheck(CanRxPduId,CanSduPtr,0x0e);\r
+\r
+ DEBUG(DEBUG_LOW,"----------------------\n");\r
+ DEBUG(DEBUG_LOW,"PduR_CanIfRxIndication: received indication with id %d and data %d\n", CanRxPduId, *CanSduPtr);\r
+\r
+ PduR_LoIfRxIndication(CanRxPduId, CanSduPtr);\r
+\r
+ DEBUG(DEBUG_LOW,"----------------------\n");\r
+ Exit();\r
+}\r
+\r
+void PduR_CanIfTxConfirmation(PduIdType CanTxPduId) {\r
+ Enter(CanTxPduId);\r
+ DevCheck(CanTxPduId,1,0x0f);\r
+\r
+ DEBUG(DEBUG_LOW,"----------------------\n");\r
+ DEBUG(DEBUG_LOW,"PduR_CanIfTxConfirmation: received confirmation with id %d\n", CanTxPduId);\r
+\r
+ PduR_LoIfTxConfirmation(CanTxPduId);\r
+\r
+ DEBUG(DEBUG_LOW,"----------------------\n");\r
+ Exit();\r
+}\r
+\r
+#endif\r
+#endif\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef PDUR_CANIF_H_\r
+#define PDUR_CANIF_H_\r
+\r
+#include "PduR.h"\r
+\r
+#ifdef PDUR_CANIF_SUPPORT\r
+#ifndef PDUR_ZERO_COST_OPERATION\r
+\r
+void PduR_CanIfRxIndication (PduIdType CanRxPduId, const uint8 *CanSudPtr );\r
+void PduR_CanIfTxConfirmation(PduIdType CanTxPduId);\r
+\r
+\r
+#else // Zero cost operation active\r
+\r
+#define PduR_CanIfRxIndication Com_RxIndication\r
+#define PduR_CanIfTxConfirmation Com_TxConfirmation\r
+\r
+#endif\r
+#endif\r
+\r
+#endif /* PDUR_CANIF_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+#define PDUR_MODULE_ID 51\r
+#define PDUR_INSTANCE_ID 0\r
+\r
+#define MUST_BE_OFF 0\r
+\r
+/* Turns on/off debug print statements in the PDU router code. */\r
+//#define PDUR_PRINT_DEBUG_STATEMENTS\r
+\r
+/* Turns on/off reentrancy checks */\r
+#define PDUR_REENTRANCY_CHECK\r
+\r
+\r
+#define PDUR_DEV_ERROR_DETECT 1 // Should this be enables in DASA configuration?\r
+\r
+#define PDUR_VERSION_INFO_API\r
+\r
+#ifdef CFG_DASA\r
+#define PDUR_ZERO_COST_OPERATION\r
+#endif\r
+\r
+#ifdef PDUR_ZERO_COST_OPERATION\r
+ // CanIf, FrIf, LinIf\r
+ #define PDUR_SINGLE_IF CAN_IF\r
+ // CanTp, FrTp, LinTp\r
+ //#define PDUR_SINGLE_TP CanTp\r
+ #define PDUR_MULTICAST_TOIF_SUPPORT MUST_BE_OFF\r
+ #define PDUR_MULTICAST_FROMIF_SUPPORT MUST_BE_OFF\r
+ #define PDUR_MULTICAST_TOTP_SUPPORT MUST_BE_OFF\r
+ #define PDUR_MULTICAST_FROMTP_SUPPORT MUST_BE_OFF\r
+\r
+#else\r
+ #define PDUR_GATEWAY_OPERATION\r
+ #ifdef PDUR_GATEWAY_OPERATION\r
+ #define PDUR_MEMORY_SIZE\r
+ //#define PDUR_SB_TX_BUFFER_SUPPORT\r
+ #define PDUR_FIFO_TX_BUFFER_SUPPORT\r
+ #define PDUR_MAX_TX_BUFFER_NUMBER 10\r
+ #endif\r
+\r
+ //#define PDUR_IPDUM_SUPPORT\r
+\r
+ // NOTE: Support for minimum routing not implemented yet.\r
+ /*\r
+ #define PDUR_MINIMUM_ROUTING_UP_MODULE COM\r
+ #define PDUR_MINIMUM_ROUTING_LO_MODULE CAN_IF\r
+ #define PDUR_MINIMUM_ROUTING_UP_RXPDUID ((PduIdType)100)\r
+ #define PDUR_MINIMUM_ROUTING_LO_RXPDUID ((PduIdType)255)\r
+ #define PDUR_MINIMUM_ROUTING_UP_TXPDUID ((PduIdType)255)\r
+ #define PDUR_MINIMUM_ROUTING_LO_TXPDUID ((PduIdType)255)\r
+ */\r
+#endif\r
+\r
+// Interfaces\r
+#define PDUR_CANIF_SUPPORT\r
+//#define PDUR_CANTP_SUPPORT\r
+//#define PDUR_FRIF_SUPPORT\r
+//#define PDUR_FRTP_SUPPORT\r
+#define PDUR_LINIF_SUPPORT\r
+//#define PDUR_LINTP_SUPPORT\r
+#define PDUR_COM_SUPPORT\r
+#define PDUR_DCM_SUPPORT\r
+\r
+\r
+//#define PDUR_MAX_TX_BUFFER_NUMBER\r
+\r
+// ERROR TYPES\r
+#define PDUR_E_CONFIG_PTR_INVALID 0x06\r
+#define PDUR_E_INVALID_REQUEST 0x01\r
+#define PDUR_E_PDU_ID_INVALID 0x02\r
+#define PDUR_E_TP_TX_REQ_REJECTED 0x03\r
+#define PDUR_E_DATA_PTR_INVALID 0x05\r
+#define PDUR_E_PDU_INSTANCE_LOST 0x10\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include "Det.h"\r
+#include "PduR_Com.h"\r
+\r
+#ifndef PDUR_ZERO_COST_OPERATION\r
+#ifdef PDUR_COM_SUPPORT\r
+\r
+/**\r
+ * Called by the COM-layer in order to send a PDU through a protocol interface.
+ */\r
+Std_ReturnType PduR_ComTransmit(PduIdType ComTxPduId, const PduInfoType* PduInfoPtr) {\r
+ Enter(ComTxPduId, E_NOT_OK);\r
+ DevCheck(ComTxPduId,PduInfoPtr,0x15, E_NOT_OK);\r
+\r
+ //DEBUG(DEBUG_LOW,"PduR_ComTransmit: received transmit request with id %d and data %d\n", ComTxPduId, *PduInfoPtr->SduDataPtr);\r
+ PduRRoutingPath_type *route = &PduRConfig->PduRRoutingTable->PduRRoutingPath[ComTxPduId];\r
+ Std_ReturnType retVal = route->FctPtrs->TargetTransmitFctPtr(route->PduRDestPdu.DestPduId, PduInfoPtr);\r
+ Exit();\r
+ return retVal;\r
+}\r
+\r
+#endif\r
+#endif\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef PDUR_COM_H_\r
+#define PDUR_COM_H_\r
+\r
+#include "PduR.h"\r
+\r
+#ifdef PDUR_COM_SUPPORT\r
+#ifndef PDUR_ZERO_COST_OPERATION\r
+\r
+Std_ReturnType PduR_ComTransmit(PduIdType ComTxPduId, const PduInfoType* PduInfoPtr);\r
+\r
+#else\r
+\r
+#if PDUR_SINGLE_IF == CAN_IF\r
+\r
+#define PduR_ComTransmit CanIf_Transmit\r
+\r
+#elif PDUR_SINGLE_IF == LIN_IF\r
+\r
+#define PduR_ComTransmit LinIf_Transmit\r
+\r
+#endif\r
+\r
+#endif\r
+#endif\r
+\r
+#endif /* PDUR_COM_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include <string.h>\r
+#include "PduR_If.h"\r
+#include "Trace.h"\r
+\r
+#ifndef PDUR_ZERO_COST_OPERATION\r
+\r
+/**\r
+ * Helper function for the PduR_<LO>IfRxIndication functions. This helper performs the actions specified by PDUR255 and PDUR258.
+ * @param LinRxPduId - The id of the PDU to be routed.
+ * @param LinSduPtr - The payload of the PDU.
+ * @param LoIf_Transmit
+ */\r
+void PduR_LoIfRxIndication(PduIdType PduId, const uint8* SduPtr) {\r
+\r
+ // Perform routing lookup.\r
+ PduRRoutingPath_type *route = &PduRConfig->PduRRoutingTable->PduRRoutingPath[PduId];\r
+\r
+ if (route->PduR_GatewayMode == 0) {\r
+ // This is an ordinary request.\r
+ route->FctPtrs->TargetIndicationFctPtr(route->PduRDestPdu.DestPduId, SduPtr); // Send PDU to next receptor.\r
+\r
+\r
+ } else if (route->PduR_GatewayMode == 1 && route->PduRDestPdu.DataProvision == PDUR_NO_PROVISION) {\r
+ // This is a gateway request, but without any data provision (buffer usage).\r
+ PduInfoType PduInfo = {\r
+ .SduDataPtr = (uint8 *)SduPtr,\r
+ .SduLength = route->SduLength\r
+ };\r
+ route->FctPtrs->TargetTransmitFctPtr(route->PduRDestPdu.DestPduId, &PduInfo); // Send PDU to next receptor.\r
+\r
+\r
+ } else if (route->PduR_GatewayMode == 1 && route->PduRDestPdu.DataProvision == PDUR_TRIGGER_TRANSMIT) {\r
+ // Ths is a gateway request which uses trigger transmit data provision. PDUR255\r
+ DEBUG(DEBUG_LOW,"\tUsing gateway mode with trigger transmit provision\n");\r
+\r
+ if (route->PduRDestPdu.TxBufferRef->TxConfP) { // Transfer confirmation pending.\r
+ // Enqueue the new I-PDU. This will flush the buffer if it is full according to the buffer specification.\r
+ PduR_BufferQueue(route->PduRDestPdu.TxBufferRef, SduPtr);\r
+ // TODO report PDUR_E_INSTANCE_LOST to DEM if needed.\r
+ }\r
+\r
+ if (!route->PduRDestPdu.TxBufferRef->TxConfP) { // No transfer confirmation pending (anymore).\r
+ uint8 val[route->SduLength];\r
+ PduInfoType PduInfo = {\r
+ .SduDataPtr = val,\r
+ .SduLength = route->SduLength\r
+ };\r
+ PduR_BufferDeQueue(route->PduRDestPdu.TxBufferRef, val);\r
+ PduR_BufferQueue(route->PduRDestPdu.TxBufferRef, SduPtr);\r
+ if (route->FctPtrs->TargetTransmitFctPtr(route->PduRDestPdu.DestPduId, &PduInfo) == E_OK) {\r
+ setTxConfP(route);\r
+ }\r
+ }\r
+\r
+ } else if (route->PduR_GatewayMode == 1 && route->PduRDestPdu.DataProvision == PDUR_DIRECT) {\r
+ // This is a gateway request using a direct data provision fifo. PDUR258\r
+ DEBUG(DEBUG_LOW,"\tUsing gateway mode with direct provision\n");\r
+\r
+ if (route->PduRDestPdu.TxBufferRef->TxConfP) { // Transfer confirmation pending.\r
+ DEBUG(DEBUG_LOW,"\tTransfer confirmation pending.\n");\r
+ PduR_BufferQueue(route->PduRDestPdu.TxBufferRef, SduPtr);\r
+ // TODO report PDUR_E_INSTANCE_LOST to DEM if needed.\r
+\r
+ }\r
+\r
+ if (!route->PduRDestPdu.TxBufferRef->TxConfP) { // No transfer confirmation pending (anymore)\r
+ // TODO: Shall this function create a new I-PDU from LinSduPtr?\r
+\r
+ // Make new PduInfoPackage\r
+ DEBUG(DEBUG_LOW,"\tNo transfer confirmation pending. Forwarding packet.\n");\r
+ PduInfoType PduInfoPtr = {\r
+ .SduDataPtr = (uint8 *)SduPtr,\r
+ .SduLength = route->SduLength\r
+ };\r
+ if (route->FctPtrs->TargetTransmitFctPtr(route->PduRDestPdu.DestPduId, &PduInfoPtr) == E_OK) {\r
+ setTxConfP(route);\r
+\r
+\r
+ } else {\r
+ // TODO report PDUR_E_INSTANCE_LOST to DEM.\r
+ //Dem_ReportErrorStatus(PDUR_E_INSTANCE_LOST, 0);\r
+ DET_REPORTERROR(PDUR_MODULE_ID, PDUR_INSTANCE_ID, 0x00, PDUR_E_PDU_INSTANCE_LOST);\r
+ DEBUG(DEBUG_LOW,"\tTransmission failed. PDUR_E_INSTANCE_LOST\n");\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+// void PduR_LoIfTxConfirmation(PduIdType PduId, Std_ReturnType (*LoIf_Transmit)(PduIdType, const PduInfoType*)) {\r
+\r
+void PduR_LoIfTxConfirmation(PduIdType PduId) {\r
+\r
+ // Perform routing lookup.\r
+ PduRRoutingPath_type *route = &PduRConfig->PduRRoutingTable->PduRRoutingPath[PduId];\r
+\r
+ // Find out if this is a gateway or ordinary confirmation.\r
+\r
+ if (route->PduR_GatewayMode == 0) {\r
+ // This is an ordinary request.\r
+ route->FctPtrs->TargetConfirmationFctPtr(route->PduRDestPdu.DestPduId); // Forward confirmation\r
+\r
+ } else if (route->PduR_GatewayMode == 1 && route->PduRDestPdu.DataProvision == PDUR_NO_PROVISION) {\r
+ // A gateway request without provision. Just forward confirmation.\r
+ route->FctPtrs->TargetConfirmationFctPtr(route->PduRDestPdu.DestPduId); // Forward confirmation\r
+\r
+\r
+ } else if (route->PduR_GatewayMode == 1 && route->PduRDestPdu.DataProvision == PDUR_TRIGGER_TRANSMIT) {\r
+ // The route is using gateway mode and trigger transmit data provision. PDUR256\r
+ DEBUG(DEBUG_LOW,"\tUsing gateway mode with trigger transmit data provision.\n", PduId);\r
+\r
+ while (1) {\r
+\r
+ // If TxConfP is set process confirmation, ignore otherwise.\r
+ if (!route->PduRDestPdu.TxBufferRef->TxConfP) { // TxConfP not set, ignore!\r
+ DEBUG(DEBUG_LOW,"\tTxConfP was not set, ignoring confirmation.\n");\r
+ break;\r
+\r
+\r
+ } else { // TxConfP is set\r
+ if (route->PduRDestPdu.TxBufferRef->NrItems == 1) { // Only one entry in buffer.\r
+ clearTxConfP(route); // Clear TxConfP\r
+ DEBUG(DEBUG_LOW,"\tOnly one entry in buffer and TxConfP set, cleared TxConfP.\n");\r
+ break;\r
+\r
+\r
+ } else { // Buffer is not empty\r
+ // Dequeue the first fifo item.\r
+ DEBUG(DEBUG_LOW,"\tMore than one entry in buffer and TxConfP set, transmitting the next fifo entry.\n");\r
+ uint8 val[route->SduLength];\r
+ PduR_BufferDeQueue(route->PduRDestPdu.TxBufferRef, val);\r
+\r
+ // TODO Does this need to be static?\r
+ PduInfoType PduInfo = {\r
+ .SduDataPtr = val,\r
+ .SduLength = route->SduLength\r
+ };\r
+ // Transmit this item.\r
+ if (route->FctPtrs->TargetTransmitFctPtr(route->PduRDestPdu.DestPduId, &PduInfo) == E_OK) {\r
+ DEBUG(DEBUG_LOW,"\tTransmit succeeded.\n");\r
+ break;\r
+\r
+\r
+ } else {\r
+ DEBUG(DEBUG_LOW,"\tTransmit failed. Retrying with the next fifo entry.\n");\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+\r
+ } else if (route->PduR_GatewayMode == 1 && route->PduRDestPdu.DataProvision == PDUR_DIRECT) {\r
+ // The route is using a direct data provision fifo. PDUR259\r
+ DEBUG(DEBUG_LOW,"\tUsing gateway mode with direct data provision.\n", PduId);\r
+\r
+ while (1) {\r
+\r
+ // If TxConfP is set process confirmation, ignore otherwise.\r
+ if (!route->PduRDestPdu.TxBufferRef->TxConfP) { // TxConfP not set, ignore!\r
+ DEBUG(DEBUG_LOW,"\tTxConfP was not set, ignoring confirmation.\n");\r
+ break;\r
+\r
+\r
+ } else { // TxConfP is set\r
+ if (route->PduRDestPdu.TxBufferRef->NrItems == 0) { // Buffer is empty\r
+ clearTxConfP(route); // Clear TxConfP\r
+ DEBUG(DEBUG_LOW,"\tBuffer was empty and TxConfP set, cleared TxConfP.\n");\r
+ break;\r
+\r
+\r
+ } else { // Buffer is not empty\r
+ // Dequeue the first fifo item.\r
+ DEBUG(DEBUG_LOW,"\tBuffer was not empty and TxConfP set, transmitting the next fifo entry.\n");\r
+ uint8 val[route->SduLength];\r
+ PduR_BufferDeQueue(route->PduRDestPdu.TxBufferRef, val);\r
+\r
+ // TODO Does this need to be static?\r
+ PduInfoType PduInfo = {\r
+ .SduDataPtr = val,\r
+ .SduLength = route->SduLength\r
+ };\r
+ // Transmit this item.\r
+ if (route->FctPtrs->TargetTransmitFctPtr(route->PduRDestPdu.DestPduId, &PduInfo) == E_OK) {\r
+ DEBUG(DEBUG_LOW,"\tTransmit succeeded.\n");\r
+ break;\r
+\r
+\r
+ } else {\r
+ DEBUG(DEBUG_LOW,"\tTransmit failed. Retrying with the next fifo entry.\n");\r
+ }\r
+ }\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+void PduR_LoIfTriggerTransmit(PduIdType PduId, uint8* SduPtr) {\r
+ // Perform routing lookup.\r
+ PduRRoutingPath_type *route = &PduRConfig->PduRRoutingTable->PduRRoutingPath[PduId];\r
+\r
+ // Find out if this is a gateway or ordinary trigger.\r
+ //if (route->PduRDestPdu.DataProvision == PDUR_NO_PROVISION) { // This is an ordinary trigger.\r
+ if (route->PduR_GatewayMode == 0) { // This is an ordinary trigger.\r
+ route->FctPtrs->TargetTriggerTransmitFctPtr(route->PduRDestPdu.DestPduId, SduPtr);\r
+\r
+ } else if (route->PduR_GatewayMode == 1 && route->PduRDestPdu.DataProvision == PDUR_TRIGGER_TRANSMIT) { // The route is using a trigger transmit fifo. PDUR256\r
+ DEBUG(DEBUG_LOW,"\tUsing gateway mode with trigger transmit data provision.\n", PduId);\r
+ memcpy((void *)SduPtr, (void *)route->PduRDestPdu.TxBufferRef->First, sizeof(uint8) * route->SduLength);\r
+\r
+ }\r
+}\r
+\r
+#endif\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef PDUR_IF_H_\r
+#define PDUR_IF_H_\r
+\r
+#include "PduR.h"\r
+#include "Det.h"\r
+\r
+void PduR_LoIfRxIndication(PduIdType PduId, const uint8* SduPtr);\r
+void PduR_LoIfTxConfirmation(PduIdType PduId);\r
+void PduR_LoIfTriggerTransmit(PduIdType PduId, uint8* SduPtr);\r
+\r
+#endif /* PDUR_IF_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include "PduR_Ipdum.h"\r
+\r
+#ifdef PDUR_IPDUM_SUPPORT\r
+\r
+Std_ReturnType PduR_IpdumTransmit(PduIdType IpdumTxPduId, const PduInfoType* PduInfoPtr) {\r
+\r
+#ifdef PDUR_DEV_ERROR_DETECT\r
+ DevCheck(IpdumTxPduId,PduInfoPtr,0x19);\r
+#endif\r
+\r
+}\r
+\r
+void PduR_IpdumTxConfirmation(PduIdType IpdumLoTxPduId) {\r
+\r
+#ifdef PDUR_DEV_ERROR_DETECT\r
+ DevCheck(IpdumLoTxPduId,0,0x1a);\r
+#endif\r
+\r
+}\r
+\r
+void PduR_IpdumRxIndication(PduIdType IpdumLoRxPduId, const uint8* IpdumSduPtr) {\r
+\r
+#ifdef PDUR_DEV_ERROR_DETECT\r
+ DevCheck(IpdumLoRxPduId,IpdumSduPtr,0x1b);\r
+#endif\r
+\r
+}\r
+\r
+#endif\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef PDUR_IPDUM_H_\r
+#define PDUR_IPDUM_H_\r
+\r
+#include "PduR.h"\r
+\r
+#ifdef PDUR_IPDUM_SUPPORT\r
+\r
+Std_ReturnType PduR_IpdumTransmit(PduIdType IpdumTxPduId, const PduInfoType* PduInfoPtr);\r
+\r
+void PduR_IpdumTxConfirmation(PduIdType IpdumLoTxPduId);\r
+\r
+void PduR_IpdumRxIndication(PduIdType IpdumLoRxPduId, const uint8* IpdumSduPtr);\r
+\r
+#endif\r
+\r
+#endif /* PDUR_IPDUM_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include "PduR_LinIf.h"\r
+//#include "LinIf.h"\r
+#include "PduR_If.h"\r
+#include "Trace.h"\r
+\r
+#ifndef PDUR_ZERO_COST_OPERATION\r
+#ifdef PDUR_LINIF_SUPPORT\r
+\r
+void PduR_LinIfRxIndication(PduIdType LinRxPduId, const uint8* LinSduPtr) {\r
+ Enter(LinRxPduId);\r
+ DevCheck(LinRxPduId,LinSduPtr,0x0e);\r
+\r
+ DEBUG(DEBUG_LOW,"----------------------\n");\r
+ DEBUG(DEBUG_LOW,"PduR_LinIfRxIndication: received indication with id %d and data %d\n", LinRxPduId, *LinSduPtr);\r
+\r
+ PduR_LoIfRxIndication(LinRxPduId, LinSduPtr);\r
+\r
+ DEBUG(DEBUG_LOW,"----------------------\n");\r
+ Exit();\r
+}\r
+\r
+void PduR_LinIfTxConfirmation(PduIdType LinTxPduId) {\r
+ Enter(LinTxPduId);\r
+ DevCheck(LinTxPduId,1,0x0f);\r
+\r
+ DEBUG(DEBUG_LOW,"----------------------\n");\r
+ DEBUG(DEBUG_LOW,"PduR_LinIfTxConfirmation: received confirmation with id %d\n", LinTxPduId);\r
+\r
+ PduR_LoIfTxConfirmation(LinTxPduId);\r
+\r
+ DEBUG(DEBUG_LOW,"----------------------\n");\r
+ Exit();\r
+}\r
+\r
+void PduR_LinIfTriggerTransmit(PduIdType LinTxPduId, uint8* LinSduPtr) {\r
+ Enter(LinTxPduId);\r
+ DevCheck(LinTxPduId,LinSduPtr,0x10);\r
+\r
+ DEBUG(DEBUG_LOW,"----------------------\n");\r
+ DEBUG(DEBUG_LOW,"PduR_LinIfTriggerTransmit: received request with id %d\n", LinTxPduId);\r
+\r
+ PduR_LoIfTriggerTransmit(LinTxPduId, LinSduPtr);\r
+\r
+ DEBUG(DEBUG_LOW,"----------------------\n");\r
+ Exit();\r
+}\r
+\r
+#endif\r
+#endif\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef PDUR_LINIF_H_\r
+#define PDUR_LINIF_H_\r
+\r
+#include "PduR.h"\r
+\r
+\r
+#ifdef PDUR_LINIF_SUPPORT\r
+#ifndef PDUR_ZERO_COST_OPERATION\r
+\r
+void PduR_LinIfRxIndication(PduIdType LinRxPduId,const uint8* LinSduPtr);\r
+void PduR_LinIfTxConfirmation(PduIdType LinTxPduId);\r
+void PduR_LinIfTriggerTransmit(PduIdType LinTxPduId,uint8* LinSduPtr);\r
+\r
+#else\r
+\r
+#define PduR_LinIfRxIndication Com_RxIndication\r
+#define PduR_LinIfTxConfirmation Com_TxConfirmation\r
+#define PduR_LinIfTriggerTransmit Com_TriggerTransmit\r
+\r
+#endif\r
+#endif\r
+\r
+#endif /*PDUR_LINIF_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include "PduR.h"\r
+\r
+PduIdType LOIf_ReceivedPduId;\r
+uint8 LOIf_ReceivedData[] = {9,9,9,9,9,9,9,9};\r
+uint8 LOIf_TriggerMode = 0; // 1 => TriggerTransmit mode. 0 => Ordinary mode.\r
+uint8 LOIf_SendConfirmation = 1; // 0 => No confirmation.\r
+Std_ReturnType LOIf_Transmit_TEST(PduIdType LOTxPduId,const PduInfoType* PduInfoPtr)\r
+{\r
+ //debug("LinIf_Transmit_TEST: Received data with id %d\n", LinTxPduId);\r
+ LOIf_ReceivedPduId = LOTxPduId;\r
+\r
+ if (LOIf_TriggerMode) {\r
+ PduR_LinIfTriggerTransmit(LOTxPduId, LOIf_ReceivedData);\r
+ } else {\r
+ memcpy(&LOIf_ReceivedData, PduInfoPtr->SduDataPtr, PduInfoPtr->SduLength * (sizeof (uint8)));\r
+ }\r
+\r
+ if (LOIf_SendConfirmation) {\r
+ PduR_LinIfTxConfirmation(LOTxPduId);\r
+ }\r
+\r
+ return E_OK;\r
+}\r
+\r
+Std_ReturnType LOIf_ErroneousTransmit_TEST(PduIdType LOTxPduId,const PduInfoType* PduInfoPtr) {\r
+ return E_NOT_OK;\r
+}\r
+\r
+PduIdType UP_ReceivedPduId;\r
+const uint8 UP_ReceivedData[] = {9,9,9,9,9,9,9,9};\r
+Std_ReturnType UP_RxIndication_TEST(PduIdType UPRxPduId, const uint8* PduInfoPtr)\r
+{\r
+ //debug("Com_RxIndication_TEST: received indication with id %d and data %d\n", ComRxPduId, *PduInfoPtr);\r
+ UP_ReceivedPduId = UPRxPduId;\r
+\r
+ memcpy(&UP_ReceivedData, PduInfoPtr, PduR_RTable_LoIf.RoutingTable[UPRxPduId].SduLength * (sizeof (uint8)));\r
+ return E_OK;\r
+}\r
+\r
+Std_ReturnType UP_TxConfirmation_TEST(PduIdType PduId) {\r
+ //debug("Com_TxConfirmation_TEST: Received confirmation with id %d\n", PduId);\r
+ UP_ReceivedPduId = PduId;\r
+ return E_OK;\r
+}\r
+\r
+Std_ReturnType UP_TriggerTransmit_TEST(PduIdType PduId, uint8 *PduInfoPtr) {\r
+ //debug("Com_TriggerTransmit: Received trigger with id %d and data %d\n", PduId, *PduInfoPtr);\r
+ UP_ReceivedPduId = PduId;\r
+ memcpy(PduInfoPtr, &CanSduPtr, PduR_RTable_LoIf.RoutingTable[PduId].SduLength * (sizeof (uint8)));\r
+ return E_OK;\r
+}\r
+\r
+PduR_FctPtrType PduR_Callbacks_TEST = {\r
+ .TargetIndicationFctPtr = UP_RxIndication_TEST,\r
+ .TargetTransmitFctPtr = LOIf_Transmit_TEST,\r
+ .TargetConfirmationFctPtr = UP_TxConfirmation_TEST,\r
+ .TargetTriggerTransmitFctPtr = UP_TriggerTransmit_TEST,\r
+};\r
+\r
+PduR_FctPtrType PduR_ErroneousCallbacks_TEST = {\r
+ //.TargetIndicationFctPtr = UP_RxIndication_TEST,\r
+ .TargetTransmitFctPtr = LOIf_ErroneousTransmit_TEST,\r
+ //.TargetConfirmationFctPtr = UP_TxConfirmation_TEST,\r
+ //.TargetTriggerTransmitFctPtr = UP_TriggerTransmit_TEST,\r
+};\r
+\r
+\r
+// DET_REPORTERROR(PDUR_MODULE_ID, PDUR_INSTANCE_ID, 0x00, PDUR_E_CONFIG_PTR_INVALID);\r
+\r
+void PduRclearError(void)\r
+{\r
+ error.ApiId=0;\r
+ error.ErrorId=0;\r
+ error.InstanceId=0;\r
+ error.ModuleId=0;\r
+\r
+ UP_ReceivedPduId = -1;\r
+ memset(&UP_ReceivedData, 9, sizeof(uint8) * 8);\r
+\r
+ LOIf_ReceivedPduId = -1;\r
+ memset(&LOIf_ReceivedData, 9, sizeof(uint8) * 8);\r
+}\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*\r
+ * PduR_Test.h\r
+ *\r
+ * Created on: 2008-nov-05\r
+ * Author: Mattias\r
+ */\r
+\r
+#ifndef PDUR_TEST_H_\r
+#define PDUR_TEST_H_\r
+\r
+\r
+#endif /* PDUR_TEST_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef _PDUR_TYPES_H\r
+#define _PDUR_TYPES_H\r
+\r
+#include "ComStack_Types.h"\r
+\r
+/* PduR_StateType defines the states of which the PDU router can be in */\r
+typedef enum {\r
+ PDUR_UNINIT, // PDU Router is not initialized.\r
+ PDUR_ONLINE, // PDU Router initialized successfully.\r
+ PDUR_REDUCED // PDU Router initialization did not succeed. Only minimum routing is provided.\r
+} PduR_StateType;\r
+\r
+typedef enum {\r
+ PDU_CNLDO, // Cancel transfer since data is outdated.\r
+ PDU_CNLNB, // Cancel transfer since buffer is full.\r
+ PDU_CNLOR // Cancel transfer of another reason.\r
+} PduR_CancelReasonType;\r
+\r
+typedef uint8 PduR_ParameterValueType;\r
+\r
+typedef enum {\r
+ PDUR_NO_PROVISION, // No data provision.\r
+ PDUR_TRIGGER_TRANSMIT, // Trigger transmit type.\r
+ PDUR_DIRECT // Data provision type.\r
+} PduR_DataProvisionType;\r
+\r
+\r
+/* ################## EXTERNAL STRUCTURES ##################\r
+ *\r
+ * These structures will be external in final implementation\r
+ */\r
+typedef struct {\r
+ const int foo;\r
+} PduR_LConfigType;\r
+\r
+\r
+\r
+\r
+/* ################ NEW DEFINITIONS ################### */\r
+typedef struct {\r
+ Std_ReturnType (*TargetIndicationFctPtr)(PduIdType, const uint8*); // Pointer to target function in layer above PDU router.\r
+ Std_ReturnType (*TargetTransmitFctPtr)(PduIdType, const PduInfoType*); // Pointer to target function below PDU router.\r
+\r
+\r
+ void (*TargetConfirmationFctPtr)(PduIdType);\r
+\r
+ /*\r
+ * Target function for trigger transmit requests from the interface modules, e.g. Com_TriggerTransmit. Only\r
+ * needed if gateway mode is not used, that is, if .DataProvision is set to PDUR_NO_PROVISION.\r
+ */\r
+ Std_ReturnType (*TargetTriggerTransmitFctPtr)(PduIdType, uint8*);\r
+\r
+\r
+ Std_ReturnType (*TargetGatewayFctPtr)(PduIdType, const PduInfoType*);\r
+\r
+} PduR_FctPtrType;\r
+\r
+typedef struct {\r
+ /*\r
+ * Not part of autosar standard. Added by Ecore.
+ */\r
+ int BufferId;\r
+ PduR_DataProvisionType BufferType;\r
+ //uint8 SduLength;\r
+ uint8 *Last;\r
+ uint8 *First;\r
+ uint8 NrItems;\r
+ uint8 TxConfP;\r
+ // uint8 TxIdx; // This is the same as First, hence left out.\r
+ uint8 *Buffer;\r
+\r
+ /*\r
+ * Depth of buffer
+ */\r
+ uint8 Depth;\r
+\r
+ /*\r
+ * Length of buffer
+ */\r
+ uint8 Length;\r
+\r
+} PduRTxBuffer_type;\r
+\r
+typedef struct {\r
+ /*\r
+ * The maximum numbers of Tx buffers.
+ */\r
+ uint16 PduRMaxTxBufferNumber; // ???\r
+\r
+ PduRTxBuffer_type PduRTxBuffer[];\r
+} PduRTxBufferTable_type;\r
+\r
+typedef struct {\r
+ /*\r
+ * PDU identifier assigned by the PDU router.
+ */\r
+ uint16 HandleId;\r
+\r
+ /*\r
+ * Reference to unique PDU identifier.
+ */\r
+ // SrcPduRef\r
+\r
+} PduRSrcPdu_type;\r
+\r
+typedef struct {\r
+\r
+ /*\r
+ * Data provision mode for this PDU.
+ */\r
+ PduR_DataProvisionType DataProvision;\r
+\r
+ /*\r
+ * Reference to unique PDU identifier which shall\r
+ * be used by the PDU router instead of the source identifier.
+ */\r
+ //DestPduRef\r
+ // For the moment replaced by this\r
+ uint16 DestPduId;\r
+\r
+ /*\r
+ * Reference to the assigned Tx buffer.\r
+ *\r
+ * Comment: Only required for non-TP gateway PDUs.
+ */\r
+ PduRTxBuffer_type *TxBufferRef;\r
+\r
+} PduRDestPdu_type;\r
+\r
+typedef struct {\r
+ uint8 ElementBytePosition;\r
+ uint8 DefaultValueElement[];\r
+} PduRDefaultValueElement_type;\r
+\r
+\r
+typedef struct {\r
+ uint8 PduREcoreDummy; // Needed in order to compile without errors.\r
+ PduRDefaultValueElement_type *PduRDefaultValueElement;\r
+} PduRDefaultValue_type;\r
+\r
+typedef struct {\r
+ /*\r
+ * Not part of standard
+ */\r
+ PduR_FctPtrType *FctPtrs;\r
+ uint8 PduREcoreEOL;\r
+ uint8 PduR_GatewayMode;\r
+\r
+ /*\r
+ * Length of PDU data.\r
+ *\r
+ * Comment: Only required if a TX buffer is configured.
+ */\r
+ uint8 SduLength;\r
+\r
+ /*\r
+ * Chunk size for routing on the fly.\r
+ *\r
+ * Comment: Only required for TP gateway PDUs.
+ */\r
+ uint16 TpChunkSize;\r
+\r
+ /*\r
+ * Specifies the default value of the PDU.\r
+ *\r
+ * Comment: Only require for gateway operation.
+ */\r
+ PduRDefaultValue_type PduRDefaultValue;\r
+\r
+ /*\r
+ * Specifies the source of the PDU to be routed.
+ */\r
+ PduRSrcPdu_type PduRSrcPdu;\r
+\r
+ /*\r
+ * Specifies the destination(s) of the PDU to be routed.\r
+ *\r
+ * Comment: Multicast (many destinations) is not supported in this implementation.\r
+ */\r
+ PduRDestPdu_type PduRDestPdu;\r
+\r
+} PduRRoutingPath_type;\r
+\r
+typedef struct {\r
+ /*\r
+ * Non-standards
+ */\r
+ uint16 NRoutingPaths;\r
+\r
+ /*\r
+ * References to the routing paths defined for this configuration.
+ */\r
+ PduRRoutingPath_type PduRRoutingPath[];\r
+\r
+} PduRRoutingTable_type;\r
+\r
+\r
+typedef struct {\r
+ /*\r
+ * Unique configuration identifier.
+ */\r
+ uint8 PduRConfigurationId;\r
+\r
+ /*\r
+ * The routing table of this PDU router configuration.
+ */\r
+ PduRRoutingTable_type *PduRRoutingTable;\r
+\r
+\r
+ /*\r
+ * The buffers used for TP gateway operation.\r
+ *\r
+ * Comment: Not implemented in this version.
+ */\r
+ //PduRTpBufferTable_type PduRTpBufferTable;\r
+\r
+ /*\r
+ * The buffers used for non-TP gateway operation.
+ */\r
+ PduRTxBufferTable_type *PduRTxBufferTable;\r
+\r
+} PduR_PBConfigType;\r
+\r
+#endif\r
--- /dev/null
+
+
+#obj-y += xfls_test.o
+#obj-y += lin_test.o
+
+#VPATH += $(ROOTDIR)/arch/$(ARCH)/delivery/mpc5500_h7f/source
+#inc-y += $(ROOTDIR)/arch/$(ARCH)/delivery/mpc5500_h7f/include
+
+
+#linkfile
+#ldcmdfile-$(CFG_MPC55XX) = -T $(ROOTDIR)/arch/$(ARCH)/scripts/linkscript_gcc.ldf
+
+#build-exe-y = ../../../$(target)_$(ARCH).$(TE)
+
+
--- /dev/null
+\r
+\r
+obj-y += xfls_test.o\r
+obj-y += lin_test.o\r
+\r
+VPATH += $(ROOTDIR)/arch/$(ARCH)/delivery/mpc5500_h7f/source\r
+inc-y += $(ROOTDIR)/arch/$(ARCH)/delivery/mpc5500_h7f/include\r
+\r
+\r
+#linkfile\r
+ldcmdfile-$(CFG_ARCH_ppc55xx) = -T $(ROOTDIR)/arch/$(ARCH)/scripts/linkscript_gcc.ldf\r
+\r
+build-exe-y = ../../../$(target)_$(ARCH).$(TE)\r
+\r
+\r
+\r
+\r
+INCLUDE = $(ROOTDIR)/include\r
+DRIVER_INCLUDE = $(ROOTDIR)/drivers/include\r
+TYPEDEFS_INCLUDE = $(ROOTDIR)/arch/ppc55xx/drivers\r
+BOARD_INCLUDE = $(ROOTDIR)/boards/mpc5516it/config\r
+DEM_INCLUDE = $(ROOTDIR)/drivers/Dem\r
+\r
+gcc -I$(INCLUDE) -I$(DRIVER_INCLUDE) -I$(TYPEDEFS_INCLUDE) -I$(BOARD_INCLUDE) -I$(DEM_INCLUDE) -o$(ROOTDIR)/drivers/PduR/PduR $(ROOTDIR)/drivers/Det/Det.c $(ROOTDIR)/drivers/PduR/PduR_PbCfg.c $(ROOTDIR)/drivers/PduR/PduR_Com.c $(ROOTDIR)/drivers/PduR/PduR_CanIf.c $(ROOTDIR)/drivers/PduR/PduR_LinIf.c $(ROOTDIR)/drivers/PduR/PduR_Ipdum.c $(ROOTDIR)/drivers/PduR/PduR.c $(ROOTDIR)/drivers/PduR/PduR_Test.c\r
--- /dev/null
+
+
+
+# Gpt
+obj-y += Gpt.o
+obj-y += Gpt_Cfg.o
+
+# Mcu
+obj-y += Mcu.o
+obj-y += Mcu_Cfg.o
+obj-y += Mcu_Exceptions.o
+obj-y += Mcu_IntcVectors.o
+
+# Can
+obj-y += Can.o
+obj-y += Can_Lcfg.o
+obj-y += CanIf.o
+obj-y += CanIf_Cfg.o
+
+obj-y += Dio.o
+obj-y += Dio_Lcfg.o
+
+obj-y += Port.o
+obj-y += Port_Cfg.o
+
+# Spi
+obj-y += Spi.o
+obj-y += Spi_Lcfg.o
+
+#Eep
+obj-y += Eep.o
+obj-y += Eep_Lcfg.o
+obj-y += Eeprom_Lcfg.o
+
+#Fls ext
+obj-y += Fls_SST25xx.o
+obj-y += Fls_SST25xx_Cfg.o
+
+# Misc
+obj-y += Det.o
+
+# Lin
+obj-y += Lin_PBcfg.o
+obj-y += Lin_Lcfg.o
+obj-y += LinIf_Lcfg.o
+obj-y += LinIf_PBcfg.o
+obj-y += LinSM_Lcfg.o
+obj-y += LinSM_PBcfg.o
+obj-y += LinSM_Cfg.o
+obj-y += Lin.o
+obj-y += LinIf.o
+obj-y += LinSM.o
+
+# ComM
+obj-y += ComM.o
+
+# Com
+obj-y += Com.o
+
+
+# Common
+obj-y += xtoa.o
+obj-y += ramlog.o
+VPATH += $(ROOTDIR)/common
+
+
+VPATH += $(ROOTDIR)/arch/$(ARCH)/kernel
+VPATH += $(ROOTDIR)/arch/$(ARCH)/drivers
+#VPATH += $(ROOTDIR)/arch/$(ARCH)/config
+VPATH += $(ROOTDIR)/boards/$(BOARDDIR)/config
+VPATH += $(ROOTDIR)/drivers
+VPATH += $(ROOTDIR)/drivers/config
+VPATH += $(ROOTDIR)/drivers/Lin
+VPATH += $(ROOTDIR)/drivers/ComM
+VPATH += $(ROOTDIR)/drivers/Com
+
+
+inc-y += $(ROOTDIR)/drivers/PduR
+inc-y += $(ROOTDIR)/drivers/Com
+inc-y += $(ROOTDIR)/drivers/ComM
+inc-y += $(ROOTDIR)/drivers/config
+inc-y += $(ROOTDIR)/boards/$(BOARDDIR)/config
+inc-y += $(ROOTDIR)/drivers/include
+inc-y += $(ROOTDIR)/include
+#inc-y += $(ROOTDIR)/arch/$(ARCH)/config
+inc-y += $(ROOTDIR)/arch/$(ARCH)/drivers
+inc-y += $(ROOTDIR)/arch/$(ARCH)/kernel
+
+inc-y += $(ROOTDIR)/embunit/embUnit
+inc-y += $(ROOTDIR)/embunit/textui
+inc-y += $(ROOTDIR)/embunit
+
+
+#libs needed by us
+libitem-y += $(ROOTDIR)/embunit/embUnit/obj_$(ARCH)/libembunit.a
+libitem-y += $(ROOTDIR)/embunit/textui/obj_$(ARCH)/libtextui.a
+
+#linkfile
+ldcmdfile-$(CFG_MPC55XX) = -T $(ROOTDIR)/arch/$(ARCH)/scripts/linkscript_gcc.ldf
+
+build-exe-y = ../../../$(target)_$(ARCH).$(TE)
+
+
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*\r
+ * RTE.h\r
+ *\r
+ * Created on: 2009-jul-10\r
+ * Author: rosa\r
+ */\r
+\r
+#ifndef RTE_H_\r
+#define RTE_H_\r
+\r
+#include "Std_Types.h"\r
+\r
+void RTE_blinker_blink(uint8 arg);\r
+\r
+#endif /* RTE_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+#include <stdlib.h>\r
+\r
+#include "RTE_blinker.h"\r
+\r
+static uint8 blinkerStatus = STD_LOW;\r
+\r
+/*\r
+ * Updates the blinker.
+ */\r
+int blinker_component_main(void) {\r
+ if (blinkerStatus == STD_LOW) {\r
+ blinkerStatus = STD_HIGH;\r
+ }\r
+ else {\r
+ blinkerStatus = STD_LOW;\r
+ }\r
+ RTE_blinker_blink(blinkerStatus);\r
+ return 1;\r
+}\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+#ifndef BLINKER_H_\r
+#define BLINKER_H_\r
+\r
+#include "Std_Types.h"\r
+\r
+int blinker_component_main(void);\r
+\r
+#endif /* BLINKER_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+#ifndef RTE_FADING_LED_H_\r
+#define RTE_FADING_LED_H_\r
+\r
+#include "Std_Types.h"\r
+\r
+void fading_led_set_level(uint16 level);\r
+\r
+#endif /* RTE_FADING_LED_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+\r
+#ifndef RTE_PWM_NODE2_H_\r
+#define RTE_PWM_NODE2_H_\r
+\r
+#include "Std_Types.h"\r
+\r
+void RTE_set_led_pwm_level(uint16 level);\r
+\r
+#endif /* RTE_PWM_NODE2_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+#include <stdlib.h>\r
+// Use run-time environment from pwm_node2\r
+#include "RTE_pwm_node2.h"\r
+\r
+\r
+void fading_led_set_level(uint16 level) {\r
+// level = (level / 0xFFFF) * 0x8000;\r
+ RTE_set_led_pwm_level(level);\r
+}\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*\r
+ * RTE.h\r
+ *\r
+ * Created on: 2009-jul-10\r
+ * Author: rosa\r
+ */\r
+\r
+#ifndef RTE_H_\r
+#define RTE_H_\r
+\r
+#include "Std_Types.h"\r
+#include "Pwm.h"\r
+\r
+void RTE_pwm_sine_update(Pwm_ChannelType channel, Pwm_PeriodType arg);\r
+\r
+void RTE_pwm_enable_notifications(Pwm_ChannelType channel, Pwm_EdgeNotificationType type);\r
+\r
+#endif /* RTE_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include <stdlib.h>\r
+\r
+#include "Std_Types.h"\r
+#include "Pwm.h"\r
+#include "RTE_pwm_sine.h"\r
+\r
+\r
+static uint8 index[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};\r
+#define SINE_TABLE_SIZE 38\r
+const Pwm_PeriodType sine_table[SINE_TABLE_SIZE] = {0x4a03, 0x53c6, 0x5d0e, 0x659e, 0x6d41, 0x73c6,\r
+ 0x7906, 0x7cde, 0x7f36, 0x7fff, 0x7f36, 0x7cde, 0x7906, 0x73c6,\r
+ 0x6d41, 0x659e, 0x5d0e, 0x53c6, 0x4a03, 0x4000, 0x35fc, 0x2c39,\r
+ 0x22f1, 0x1a61, 0x12be, 0xc39, 0x6f9, 0x321, 0xc9, 0x0, 0xc9, 0x321,\r
+ 0x6f9, 0xc39, 0x12be, 0x1a61, 0x22f1, 0x2c39, 0x35fc};\r
+\r
+/*\r
+ * Next sine sample\r
+ */\r
+int pwm_sine_main(Pwm_ChannelType channel) {\r
+ uint8 cnt = index[channel];\r
+ if (cnt >= SINE_TABLE_SIZE) {\r
+ cnt = 0;\r
+ } else {\r
+ cnt++;\r
+ }\r
+\r
+ RTE_pwm_sine_update(channel, sine_table[cnt]);\r
+\r
+ index[channel] = cnt;\r
+\r
+ return 1;\r
+}\r
+\r
+\r
+/*\r
+ * Initialize notifications\r
+ */\r
+int pwm_enable_notifications() {\r
+ RTE_pwm_enable_notifications(PWM_CHANNEL_1, PWM_RISING_EDGE);\r
+ return 1;\r
+}\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+#ifndef BLINKER_H_\r
+#define BLINKER_H_\r
+\r
+#include "Std_Types.h"\r
+#include "Pwm.h"\r
+\r
+int pwm_sine_main(Pwm_ChannelType);\r
+void pwm_enable_notifications();\r
+\r
+#endif /* BLINKER_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+#ifndef RTE_SWITCH_H_\r
+#define RTE_SWITCH_H_\r
+\r
+#include "Std_Types.h"\r
+\r
+void switch_handle_switch1(void);\r
+void switch_handle_switch2(void);\r
+\r
+#endif /* RTE_SWITCH_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+\r
+#ifndef RTE_SWITCH_NODE_H_\r
+#define RTE_SWITCH_NODE_H_\r
+\r
+#include "Std_Types.h"\r
+\r
+void RTE_send_led_level(uint16 arg);\r
+\r
+#endif /* RTE_SWITCH_NODE_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+#include <stdlib.h>\r
+// Use run-time environment from switch_node\r
+#include "RTE_switch_node.h"\r
+\r
+uint16 level = 0;\r
+\r
+void switch_handle_switch1(void) {\r
+ RTE_send_led_level(level);\r
+\r
+ level -= 400;\r
+ if (level > 0x8000) {\r
+ level = 0;\r
+ }\r
+}\r
+\r
+void switch_handle_switch2(void) {\r
+ RTE_send_led_level(level);\r
+\r
+ level += 400;\r
+ if (level >= 0x8000) {\r
+ level = 0x7FFF;\r
+ }\r
+}\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+#include "Std_Types.h"\r
+#include "Rte.h"\r
+#include "Dem.h"\r
+#include "Dem_Lcfg.h"\r
+#include "Dem_PBcfg.h"\r
+//#include "NvM.h"\r
+// #include "Fim.h"\r
+// #include "Rte_Dem.h"\r
+#include "Dem_IntEvtId.h"\r
+#include "Dem_IntErrId.h"\r
+#include "Os.h"\r
+\r
+void Dem_PreInit( void ) {\r
+ \r
+}\r
+void Dem_Init( void ) {\r
+ \r
+}\r
+\r
+Std_ReturnType Dem_ReportErrorStatus( Dem_EventIdType id ,Dem_EventStatusType type ) {\r
+ (void )id;\r
+ (void )type;\r
+ return RTE_E_OK;\r
+}\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef DEM_INTERRID_H_\r
+#define DEM_INTERRID_H_\r
+\r
+#endif /*DEM_INTERRID_H_*/\r
+\r
+/* Added by Mattias Ekberg 2008-10-20 while implementing the PDU router. The value of PDUR_E_INSTANCE_LOST can\r
+ be changed without affecting the PDU router.*/\r
+#define PDUR_E_INSTANCE_LOST 0\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef DEMINTEVTID_H_\r
+#define DEMINTEVTID_H_\r
+\r
+#endif /*DEMINTEVTID_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef DEM_LCFG_H_\r
+#define DEM_LCFG_H_\r
+\r
+#endif /*DEM_LCFG_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef DEM_PBCFG_H_\r
+#define DEM_PBCFG_H_\r
+\r
+#endif /*DEM_PBCFG_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef DEM_TYPES_H_\r
+#define DEM_TYPES_H_\r
+\r
+#endif /*DEM_TYPES_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*\r
+ * Development Error Tracer driver\r
+ *\r
+ * Specification: Autosar v2.0.1, Final\r
+ *\r
+ */\r
+\r
+#include "Std_Types.h"\r
+#include "Det.h"\r
+#include "Cpu.h"\r
+#include "stdio.h"\r
+\r
+#define DEBUG_LVL 1\r
+#include "Trace.h"\r
+\r
+typedef enum\r
+{\r
+ DET_UNINITIALIZED = 0,\r
+ DET_INITIALIZED,\r
+ DET_STARTED\r
+} Det_StateType;\r
+\r
+static Det_StateType _detState = DET_UNINITIALIZED;\r
+\r
+#if ( DET_USE_RAMLOG == STD_ON )\r
+// TODO Put this in a section that is not initialised after a reset\r
+uint32 Det_RamlogIndex = 0;\r
+Det_EntryType Det_RamLog[DET_RAMLOG_SIZE];\r
+#endif\r
+\r
+#if ( DET_ENABLE_CALLBACKS == STD_ON )\r
+detCbk_t detCbk_List[DET_NUMBER_OF_CALLBACKS];\r
+\r
+uint8 Det_AddCbk(detCbk_t detCbk)\r
+{\r
+ if (_detState != DET_UNINITIALIZED)\r
+ {\r
+ for (uint32 i=0; i<DET_NUMBER_OF_CALLBACKS; i++)\r
+ {\r
+ if (NULL==detCbk_List[i])\r
+ {\r
+ detCbk_List[i]=detCbk;\r
+ return i;\r
+ }\r
+ }\r
+ }\r
+\r
+ Det_ReportError(DET_MODULE_ID, 0, DET_CALLBACK_API, DET_E_CBK_REGISTRATION_FAILED);\r
+ return (0xFF); // Return 0xff to indicate that the registration failed\r
+}\r
+\r
+void Det_RemoveCbk(uint8 detCbkIndex)\r
+{\r
+ // Validate the index\r
+ if (detCbkIndex >= DET_NUMBER_OF_CALLBACKS)\r
+ Det_ReportError(DET_MODULE_ID, 0, DET_CALLBACK_API, DET_E_INDEX_OUT_OF_RANGE);\r
+\r
+ detCbk_List[detCbkIndex]=NULL;\r
+}\r
+#endif\r
+\r
+\r
+void Det_Init(void)\r
+{\r
+#if ( DET_ENABLE_CALLBACKS == STD_ON )\r
+ for (uint32 i=0; i<DET_NUMBER_OF_CALLBACKS; i++)\r
+ {\r
+ detCbk_List[i]=NULL;\r
+ }\r
+#endif\r
+\r
+#if ( DET_USE_RAMLOG == STD_ON )\r
+ for(uint32 i=0; i < DET_RAMLOG_SIZE; i++)\r
+ {\r
+ Det_RamLog[i].moduleId = 0;\r
+ Det_RamLog[i].instanceId = 0;\r
+ Det_RamLog[i].apiId = 0;\r
+ Det_RamLog[i].errorId = 0;\r
+ }\r
+ Det_RamlogIndex = 0;\r
+#endif\r
+\r
+ _detState = DET_INITIALIZED;\r
+}\r
+\r
+#if DET_DEINIT_API == STD_ON\r
+void Det_DeInit( void )\r
+{\r
+ _detState = DET_UNINITIALIZED;\r
+}\r
+#endif\r
+\r
+void Det_ReportError(uint16 ModuleId, uint8 InstanceId, uint8 ApiId, uint8 ErrorId)\r
+{\r
+ if (_detState == DET_STARTED) // No action is taken if the module is not started\r
+ {\r
+#if ( DET_ENABLE_CALLBACKS == STD_ON )
+ long old1;\r
+ Irq_Save(old1);\r
+ for (uint32 i=0; i<DET_NUMBER_OF_CALLBACKS; i++)\r
+ {\r
+ if (NULL!=detCbk_List[i])\r
+ {\r
+ (*detCbk_List[i])(ModuleId, InstanceId, ApiId, ErrorId);\r
+ }\r
+ }\r
+ Irq_Restore(old1);\r
+#endif\r
+\r
+#if ( DET_USE_RAMLOG == STD_ON )
+ long old2;\r
+ Irq_Save(old2);\r
+ if (Det_RamlogIndex < DET_RAMLOG_SIZE)\r
+ {\r
+ Det_RamLog[Det_RamlogIndex].moduleId = ModuleId;\r
+ Det_RamLog[Det_RamlogIndex].instanceId = InstanceId;\r
+ Det_RamLog[Det_RamlogIndex].apiId = ApiId;\r
+ Det_RamLog[Det_RamlogIndex].errorId = ErrorId;\r
+ Det_RamlogIndex++;\r
+#if ( DET_WRAP_RAMLOG == STD_ON )\r
+ if (Det_RamlogIndex == DET_RAMLOG_SIZE)\r
+ Det_RamlogIndex = 0;\r
+#endif\r
+ }\r
+ Irq_Restore(old2);\r
+#endif\r
+\r
+#if ( DET_USE_STDERR == STD_ON )\r
+ simple_printf("Det Error: ModuleId=%d, InstanceId=%d, ApiId=%d, ErrorId=%d\n", ModuleId, InstanceId, ApiId, ErrorId);\r
+ //fprintf(stderr, "Det Error: ModuleId=%d, InstanceId=%d, ApiId=%d, ErrorId=%d\n", ModuleId, InstanceId, ApiId, ErrorId);\r
+#endif\r
+ }\r
+}\r
+\r
+void Det_Start(void)\r
+{\r
+ _detState = DET_STARTED;\r
+}\r
--- /dev/null
+In this folder should modules related to diagnostic services be placed.
\ No newline at end of file
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include "Os.h"
+#include <stdio.h>
+#include <assert.h>
+#define USE_TRACE 1
+#include "Trace.h"
+//#include "Hooks.h"
+
+
+#if 0
+#ifdef USE_STARTUPHOOK
+#ifdef CFG_MPC55XX
+#if !defined(USE_SIMULATOR)
+// Quick fix
+//#include "kernel_offset.h"
+#include "Mcu.h"
+
+extern uint8_t pcb_list[];
+
+#endif
+#endif
+#endif
+#endif
+
+
+
+/* Global hooks */
+ProtectionReturnType ProtectionHook( StatusType FatalError ) {
+ dbg_printf("## ProtectionHook\n");
+ return PRO_KILLAPPL;
+}
+
+void StartupHook( void ) {
+ dbg_printf("## StartupHook\n");
+
+ uint32_t sys_freq = McuE_GetSystemClock();
+
+ dbg_printf("Sys clock %d Hz\n",sys_freq);
+ Frt_Init();
+ Frt_Start(sys_freq/1000);
+
+}
+
+void ShutdownHook( StatusType Error ) {
+ dbg_printf("## ShutdownHook\n");
+ while(1);
+}
+
+void ErrorHook( StatusType Error ) {
+ DisableAllInterrupts();
+
+ dbg_printf("## ErrorHook err=%d\n",Error);
+ while(1);
+}
+
+void PreTaskHook( void ) {
+ TaskType task;
+ GetTaskID(&task);
+ if( task > 10 ) {
+ while(1);
+ }
+// dbg_printf("## PreTaskHook, taskid=%d\n",task);
+}
+
+void PostTaskHook( void ) {
+ TaskType task;
+ GetTaskID(&task);
+ if( task > 10 ) {
+ while(1);
+ }
+// dbg_printf("## PostTaskHook, taskid=%d\n",task);
+}
+
+#if 0
+struct os_conf_global_hooks_s os_conf_global_hooks = {
+ .StartupHook = StartupHook,
+ .ProtectionHook = ProtectionHook,
+ .ShutdownHook = ShutdownHook,
+ .ErrorHook = ErrorHook,
+ .PreTaskHook = PreTaskHook,
+ .PostTaskHook = PostTaskHook
+ };
+#endif
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*\r
+ * RTE.c\r
+ *\r
+ * Created on: 2009-jul-10\r
+ * Author: rosa\r
+ */\r
+\r
+#include "Dio.h"\r
+\r
+\r
+void RTE_blinker_blink(uint8 arg){\r
+ Dio_WriteChannel(LED_K2, arg);\r
+}\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*\r
+ * RTE.h\r
+ *\r
+ * Created on: 2009-jul-10\r
+ * Author: rosa\r
+ */\r
+\r
+#ifndef RTE_H_\r
+#define RTE_H_\r
+#include "RTE_blinker.h"\r
+\r
+#endif /* RTE_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include "Os.h"\r
+#include "os_config_macros.h"\r
+\r
+#include "EcuM.h"\r
+#include <stdio.h>\r
+#include <assert.h>\r
+#include "blinker_main.h"\r
+#include "Trace.h"\r
+#include "WdgM.h"\r
+\r
+\r
+void OsIdle( void ) {\r
+ for(;;);\r
+}\r
+\r
+/*\r
+ * This basic task should execute every 10 OS ticks\r
+ */\r
+\r
+void bTask10( void ) {\r
+\r
+ WdgM_MainFunction_Trigger();\r
+\r
+ TerminateTask();\r
+}\r
+\r
+/*\r
+ * This basic task should execute every 25 OS ticks\r
+ */\r
+void bTask25( void ) {\r
+\r
+ WdgM_UpdateAliveCounter(WDBG_ALIVE_LOOP_BLINK_COMPONENT);\r
+ blinker_component_main();\r
+\r
+ TerminateTask();\r
+}\r
+\r
+/*\r
+ * This basic task should execute every 100 OS ticks
+ */\r
+\r
+void bTask100( void ) {\r
+\r
+ WdgM_MainFunction_AliveSupervision();\r
+\r
+ TerminateTask();\r
+}\r
+/*\r
+ * This is the startup task. It is activated once immediately after the OS i started.
+ */\r
+void Startup( void ) {\r
+\r
+ // Call second phase of startup sequence.\r
+ EcuM_StartupTwo();\r
+\r
+ /*\r
+ * Activate scheduled tasks. OS tick is 1ms.\r
+ * The Blink is run every 25 ms with an offset of 25ms.\r
+ */\r
+ SetRelAlarm(ALARM_ID_bTask10, 10, 10); // ADC data acquisition\r
+ SetRelAlarm(ALARM_ID_bTask25, 25, 25); // ADC data acquisition\r
+ SetRelAlarm(ALARM_ID_bTask100, 100, 100); // ADC data acquisition\r
+\r
+ WdgM_ActivateAliveSupervision(WDBG_ALIVE_LOOP_BLINK_COMPONENT);\r
+\r
+ // End of startup_task().\r
+ TerminateTask();\r
+}\r
+\r
+\r
--- /dev/null
+\r
+MOD_USE+=KERNEL MCU WDG WDGM PORT DIO T32_TERM\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+#include "os_config_macros.h"\r
+#include "kernel.h"\r
+#include "Os_Cfg.h"\r
+#include "mcu.h"\r
+#include "kernel_offset.h"\r
+//#include "Hooks.h"\r
+\r
+extern void dec_exception( void );\r
+\r
+GEN_APPLICATION_HEAD {\r
+ GEN_APPLICATON(BLINKER_APP_ID,"BlinkerApp",true,NULL,NULL,NULL , 0,0,0,0,0,0 )\r
+};\r
+\r
+GEN_RESOURCE_HEAD {\r
+ GEN_RESOURCE(RES_SCHEDULER,RESOURCE_TYPE_STANDARD,0,0,0), // Standard resource..\r
+};\r
+\r
+//--- TASKS ----\r
+DECLARE_STACK(OsIdle,PRIO_STACK_SIZE);\r
+DECLARE_STACK(bTask25,PRIO_STACK_SIZE);\r
+DECLARE_STACK(bTask100,PRIO_STACK_SIZE);\r
+DECLARE_STACK(bTask10,PRIO_STACK_SIZE);\r
+DECLARE_STACK(Startup,PRIO_STACK_SIZE);\r
+\r
+GEN_TASK_HEAD {\r
+ GEN_ETASK( OsIdle,\r
+ TASK_ID_OsIdle,\r
+ true/*auto*/,\r
+ NULL/*tm*/,\r
+ BLINKER_APP_ID/*app*/,\r
+ NULL/*rsrc*/),\r
+\r
+ GEN_BTASK( bTask25,\r
+ TASK_ID_bTask25,\r
+ false/*auto*/,\r
+ NULL/*tm*/,\r
+ BLINKER_APP_ID/*app*/,\r
+ NULL/*rsrc*/),\r
+\r
+ GEN_BTASK( bTask100,\r
+ TASK_ID_bTask100,\r
+ false/*auto*/,\r
+ NULL/*tm*/,\r
+ BLINKER_APP_ID/*app*/,\r
+ NULL/*rsrc*/),\r
+\r
+ GEN_BTASK( bTask10,\r
+ TASK_ID_bTask10,\r
+ false/*auto*/,\r
+ NULL/*tm*/,\r
+ BLINKER_APP_ID/*app*/,\r
+ NULL/*rsrc*/),\r
+\r
+ GEN_BTASK( Startup,\r
+ TASK_ID_Startup,\r
+ true/*auto*/,\r
+ NULL/*tm*/,\r
+ BLINKER_APP_ID/*app*/,\r
+ NULL/*rsrc*/),\r
+};\r
+\r
+GEN_PCB_LIST()\r
+\r
+\r
+// --- INTERRUPTS ---\r
+uint8_t os_interrupt_stack[OS_INTERRUPT_STACK_SIZE] __attribute__ ((aligned (0x10)));\r
+\r
+// The vector table\r
+void * intc_vector_tbl[NUMBER_OF_INTERRUPTS_AND_EXCEPTIONS] __attribute__ ((aligned (0x0800),section(".data")))= {\r
+};\r
+\r
+// The type of vector\r
+uint8 intc_type_tbl[NUMBER_OF_INTERRUPTS_AND_EXCEPTIONS] = {\r
+};\r
+\r
+\r
+// --- COUNTERS ---\r
+GEN_COUNTER_HEAD {\r
+ GEN_COUNTER( OS_TICK_COUNTER,\r
+ "OS_TICK_COUNTER",\r
+ COUNTER_TYPE_HARD,\r
+ COUNTER_UNIT_NANO,\r
+ 0xffff,1,1,0 ),\r
+};\r
+\r
+// --- ALARMS ---\r
+GEN_ALARM_HEAD {\r
+ {\r
+ .expire_val = 10,\r
+ .active = FALSE,\r
+ .counter = &counter_list[OS_TICK_COUNTER],\r
+ .counter_id = OS_TICK_COUNTER,\r
+ .action =\r
+ {\r
+ .type = ALARM_ACTION_ACTIVATETASK,\r
+ .task_id = TASK_ID_bTask10,\r
+ .event_id = 0,\r
+ }\r
+ },\r
+ {\r
+ .expire_val = 25,\r
+ .active = FALSE,\r
+ .counter = &counter_list[OS_TICK_COUNTER],\r
+ .counter_id = OS_TICK_COUNTER,\r
+ .action =\r
+ {\r
+ .type = ALARM_ACTION_ACTIVATETASK,\r
+ .task_id = TASK_ID_bTask25,\r
+ .event_id = 0,\r
+ }\r
+ },\r
+ {\r
+ .expire_val = 100,\r
+ .active = FALSE,\r
+ .counter = &counter_list[OS_TICK_COUNTER],\r
+ .counter_id = OS_TICK_COUNTER,\r
+ .action =\r
+ {\r
+ .type = ALARM_ACTION_ACTIVATETASK,\r
+ .task_id = TASK_ID_bTask100,\r
+ .event_id = 0,\r
+ }\r
+ },\r
+};\r
+\r
+// --- HOOKS ---\r
+GEN_HOOKS( StartupHook, ProtectionHook, ShutdownHook, ErrorHook, PreTaskHook, PostTaskHook )\r
+\r
+// --- MISC ---\r
+uint32 os_dbg_mask = 0;\r
+\r
+// D_MASTER_PRINT |\\r
+// D_ISR_MASTER_PRINT |\\r
+// D_STDOUT |\\r
+// D_ISR_STDOUT |\r
+// D_ALARM | D_TASK;\r
+\r
+\r
+#include "os_config_funcs.h"\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*\r
+ * Os_Cfg.h\r
+ *\r
+ * Created on: 2008-dec-22\r
+ * Author: mahi\r
+ */\r
+#ifndef OS_CFG_H_\r
+#define OS_CFG_H_\r
+\r
+#include <limits.h>\r
+\r
+// APPS\r
+#define BLINKER_APP_ID 122\r
+#define APPLICATION_CNT 1\r
+\r
+// TASKS\r
+#define TASK_ID_OsIdle 0\r
+#define TASK_ID_bTask25 1\r
+#define TASK_ID_bTask100 2\r
+#define TASK_ID_bTask10 3\r
+#define TASK_ID_Startup 4\r
+\r
+void OsIdle( void );\r
+void Startup( void );\r
+void bTask10( void );\r
+void bTask25( void );\r
+void bTask100( void );\r
+\r
+// ALARMS\r
+#define ALARM_USE\r
+#define ALARM_ID_bTask10 0\r
+#define ALARM_ID_bTask25 1\r
+#define ALARM_ID_bTask100 2\r
+\r
+// RESOURCES\r
+#define RES_ID_BLINK 1 // Den mysko RES_SCHEDULER är ju nr 0\r
+\r
+// MISC\r
+#define USE_IDLE_TASK\r
+#define PRIO_STACK_SIZE 4096\r
+#define OS_INTERRUPT_STACK_SIZE 4096\r
+#define EVENT_BLINK (1<<0)\r
+\r
+#endif /* OS_CFG_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include "WdgM_Cfg.h"\r
+\r
+Wdgm_SupervisionType Wdgm_Supervision[WDBG_NBR_OF_ALIVE_SIGNALS];\r
+\r
+\r
+const WdgM_SupervisedEntityType WdgM_SupervisedEntity [WDBG_NBR_OF_ALIVE_SIGNALS] =\r
+{\r
+ {\r
+ .WdgM_SupervisedEntityID = WDBG_ALIVE_LOOP_BLINK_COMPONENT,\r
+ .WdgM_ActivationStatus = WDBG_SUPERVISION_DISABLED,\r
+ .WdgM_ExpectedAliveIndications = 4,\r
+ .WdgM_SupervisionReferenceCycle = 1,\r
+ .WdgM_FailedSupervisionReferenceCycleTolerance = 1,\r
+ .WdgM_MinMargin = 1,\r
+ .WdgM_MaxMargin = 1\r
+ },\r
+};\r
+\r
+const WdgM_ConfigType WdgMAliveSupervision =\r
+{\r
+ .WdgM_SupervisionCycle = 1,\r
+ .WdgM_NumberOfSupervisedEntities = WDBG_NBR_OF_ALIVE_SIGNALS,\r
+ .WdgM_ExpiredSupervisionCycleTolerance = 1,\r
+ .WdgM_SupervisedEntityPtr = WdgM_SupervisedEntity,\r
+ .Wdgm_SupervisionPtr = Wdgm_Supervision\r
+};\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*\r
+ * WdgM_Lcfg.h\r
+ *\r
+ * Created on: 2009-jul-22\r
+ * Author: rosa\r
+ */\r
+\r
+#ifndef WDGM_LCFG_H_\r
+#define WDGM_LCFG_H_\r
+\r
+typedef enum\r
+{\r
+ WDBG_ALIVE_LOOP_BLINK_COMPONENT,\r
+ WDBG_NBR_OF_ALIVE_SIGNALS\r
+}WdgM_SupervisedEntityIdType;\r
+\r
+#endif /* WDGM_LCFG_H_ */\r
--- /dev/null
+
+# Our object files
+obj-y += blinker_main.o
+obj-y += Tasks.o
+obj-y += Hooks.o
+obj-y += Rte.o
+
+# OS object files.
+obj-y += Os_Cfg.o
+# Board object files
+include $(ROOTDIR)/boards/board_common.mk
+
+ABSDIR := $(subst $(TOPDIR)/,,$(CURDIR))
+
+# The more precise configuration, the higher preceedance.
+VPATH := ../config/$(BOARDDIR) ../config $(VPATH)
+inc-y := ../config/$(BOARDDIR) ../config $(inc-y)
+
+inc-y += $(ROOTDIR)/system/kernel/$(objdir)
+inc-y += $(ROOTDIR)/system/kernel/include
+
+#TODO: Remove?, Build other way?
+VPATH += $(ROOTDIR)/$(SUBDIR)/Rte
+inc-y += $(ROOTDIR)/$(SUBDIR)/Rte
+VPATH += $(ROOTDIR)/components/blinker
+inc-y += $(ROOTDIR)/components/blinker
+
+
+# libs needed by us
+libitem-y += $(ROOTDIR)/libs/libkernel_$(ARCH_MCU).a
+
+#linkfile
+ldcmdfile-y = -T $(ROOTDIR)/$(ARCH_PATH-y)/scripts/linkscript_gcc.ldf
+
+# What I want to build
+build-exe-y = blinker_node.elf
+
+
+
+
+
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include "Os.h"
+#include "Pwm.h"
+#include <stdio.h>
+#include <assert.h>
+#define USE_TRACE 1
+#define USE_DEBUG 1
+#include "Trace.h"
+
+/* Notification callback from channel 0 */
+void MyPwmNotificationRoutine(void) {
+ static uint32 count = 0;
+ static uint32 highcount = 0;
+ static uint32 lowcount = 0;
+ Pwm_OutputStateType outputState = Pwm_GetOutputState(PWM_CHANNEL_1);
+
+ if (outputState == PWM_HIGH) {
+ highcount++;
+ } else {
+ lowcount++;
+ }
+
+ count++;
+}
+
+
+/* Global hooks */
+ProtectionReturnType ProtectionHook( StatusType FatalError ) {
+ dbg_printf("## ProtectionHook\n");
+ return PRO_KILLAPPL;
+}
+
+void StartupHook( void ) {
+ dbg_printf("## StartupHook\n");
+
+ uint32_t sys_freq = McuE_GetSystemClock();
+
+ dbg_printf("Sys clock %d Hz\n",sys_freq);
+ Frt_Init();
+ Frt_Start(sys_freq/1000);
+
+}
+
+void ShutdownHook( StatusType Error ) {
+ dbg_printf("## ShutdownHook\n");
+ while(1);
+}
+
+void ErrorHook( StatusType Error ) {
+ DisableAllInterrupts();
+
+ dbg_printf("## ErrorHook err=%d\n",Error);
+ while(1);
+}
+
+void PreTaskHook( void ) {
+ TaskType task;
+ GetTaskID(&task);
+ if( task > 10 ) {
+ while(1);
+ }
+// dbg_printf("## PreTaskHook, taskid=%d\n",task);
+}
+
+void PostTaskHook( void ) {
+ TaskType task;
+ GetTaskID(&task);
+ if( task > 10 ) {
+ while(1);
+ }
+// dbg_printf("## PostTaskHook, taskid=%d\n",task);
+}
+
+#if 0
+struct os_conf_global_hooks_s os_conf_global_hooks = {
+ .StartupHook = StartupHook,
+ .ProtectionHook = ProtectionHook,
+ .ShutdownHook = ShutdownHook,
+ .ErrorHook = ErrorHook,
+ .PreTaskHook = PreTaskHook,
+ .PostTaskHook = PostTaskHook
+ };
+#endif
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*\r
+ * RTE.c\r
+ *\r
+ * Created on: 2009-jul-10\r
+ * Author: rosa\r
+ */\r
+\r
+#include "Pwm.h"\r
+\r
+\r
+void RTE_pwm_sine_update(Pwm_ChannelType channel, Pwm_PeriodType arg){\r
+ Pwm_SetDutyCycle(channel, arg);\r
+}\r
+\r
+\r
+void RTE_pwm_enable_notifications(Pwm_ChannelType channel, Pwm_EdgeNotificationType type) {\r
+ Pwm_EnableNotification(channel, type);\r
+}\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*\r
+ * RTE.h\r
+ *\r
+ * Created on: 2009-jul-10\r
+ * Author: rosa\r
+ */\r
+\r
+#ifndef RTE_H_\r
+#define RTE_H_\r
+#include "RTE_pwm_sine.h"\r
+\r
+#endif /* RTE_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include "Os.h"\r
+#include "os_config_macros.h"\r
+\r
+#include "EcuM.h"\r
+#include <stdio.h>\r
+#include <assert.h>\r
+#include "pwm_sine_main.h"\r
+#include "Trace.h"\r
+//#include "WdgM.h"\r
+\r
+\r
+void OsIdle( void ) {\r
+ for(;;);\r
+}\r
+\r
+/*\r
+ * This basic task should execute every 25 OS ticks\r
+ */\r
+void bTask25( void ) {\r
+\r
+ // Update PWM_CHANNEL_1 every 25th OS tick\r
+ pwm_sine_main(PWM_CHANNEL_1);\r
+\r
+ TerminateTask();\r
+}\r
+\r
+/*\r
+ * This basic task should execute every 100 OS ticks
+ */\r
+\r
+void bTask100( void ) {\r
+\r
+ // Update PWM_CHANNEL_2 every 100th OS tick\r
+ pwm_sine_main(PWM_CHANNEL_2);\r
+\r
+ TerminateTask();\r
+}\r
+\r
+/*\r
+ * This is the startup task. It is activated once immediately after the OS i started.
+ */\r
+void Startup( void ) {\r
+\r
+ // Call second phase of startup sequence.\r
+ EcuM_StartupTwo();\r
+\r
+ pwm_enable_notifications();\r
+\r
+ /*\r
+ * Activate scheduled tasks. OS tick is 1ms.\r
+ */\r
+ SetRelAlarm(ALARM_ID_bTask25, 25, 25); // Task for pwm channel 1\r
+ SetRelAlarm(ALARM_ID_bTask100, 100, 100); // Task for pwm channel 2\r
+\r
+\r
+ // End of startup_task().\r
+ TerminateTask();\r
+}\r
+\r
+\r
--- /dev/null
+\r
+MOD_USE+=KERNEL MCU PORT PWM WINIDEA_TERM\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+#include "os_config_macros.h"\r
+#include "kernel.h"\r
+#include "Os_Cfg.h"\r
+#include "Mcu.h"\r
+#include "kernel_offset.h"\r
+//#include "Hooks.h"\r
+\r
+extern void dec_exception( void );\r
+\r
+GEN_APPLICATION_HEAD {\r
+ GEN_APPLICATON(BLINKER_APP_ID,"PwmApp",true,NULL,NULL,NULL , 0,0,0,0,0,0 )\r
+};\r
+\r
+GEN_RESOURCE_HEAD {\r
+ GEN_RESOURCE(RES_SCHEDULER,RESOURCE_TYPE_STANDARD,0,0,0), // Standard resource..\r
+};\r
+\r
+//--- TASKS ----\r
+DECLARE_STACK(OsIdle,PRIO_STACK_SIZE);\r
+DECLARE_STACK(bTask25,PRIO_STACK_SIZE);\r
+DECLARE_STACK(bTask100,PRIO_STACK_SIZE);\r
+DECLARE_STACK(Startup,PRIO_STACK_SIZE);\r
+\r
+GEN_TASK_HEAD {\r
+ GEN_ETASK( OsIdle,\r
+ TASK_ID_OsIdle,\r
+ true/*auto*/,\r
+ NULL/*tm*/,\r
+ BLINKER_APP_ID/*app*/,\r
+ NULL/*rsrc*/),\r
+\r
+ GEN_BTASK( bTask25,\r
+ TASK_ID_bTask25,\r
+ false/*auto*/,\r
+ NULL/*tm*/,\r
+ BLINKER_APP_ID/*app*/,\r
+ NULL/*rsrc*/),\r
+\r
+ GEN_BTASK( bTask100,\r
+ TASK_ID_bTask100,\r
+ false/*auto*/,\r
+ NULL/*tm*/,\r
+ BLINKER_APP_ID/*app*/,\r
+ NULL/*rsrc*/),\r
+\r
+ GEN_BTASK( Startup,\r
+ TASK_ID_Startup,\r
+ true/*auto*/,\r
+ NULL/*tm*/,\r
+ BLINKER_APP_ID/*app*/,\r
+ NULL/*rsrc*/),\r
+};\r
+\r
+GEN_PCB_LIST()\r
+\r
+\r
+// --- INTERRUPTS ---\r
+uint8_t os_interrupt_stack[OS_INTERRUPT_STACK_SIZE] __attribute__ ((aligned (0x10)));\r
+\r
+// The vector table\r
+void * intc_vector_tbl[NUMBER_OF_INTERRUPTS_AND_EXCEPTIONS] __attribute__ ((aligned (0x0800),section(".data")))= {\r
+};\r
+\r
+// The type of vector\r
+uint8 intc_type_tbl[NUMBER_OF_INTERRUPTS_AND_EXCEPTIONS] = {\r
+};\r
+\r
+\r
+// --- COUNTERS ---\r
+GEN_COUNTER_HEAD {\r
+ GEN_COUNTER( OS_TICK_COUNTER,\r
+ "OS_TICK_COUNTER",\r
+ COUNTER_TYPE_HARD,\r
+ COUNTER_UNIT_NANO,\r
+ 0xffff,1,1,0 ),\r
+};\r
+\r
+// --- ALARMS ---\r
+GEN_ALARM_HEAD {\r
+ {\r
+ .expire_val = 25,\r
+ .active = FALSE,\r
+ .counter = &counter_list[OS_TICK_COUNTER],\r
+ .counter_id = OS_TICK_COUNTER,\r
+ .action =\r
+ {\r
+ .type = ALARM_ACTION_ACTIVATETASK,\r
+ .task_id = TASK_ID_bTask25,\r
+ .event_id = 0,\r
+ }\r
+ },\r
+ {\r
+ .expire_val = 100,\r
+ .active = FALSE,\r
+ .counter = &counter_list[OS_TICK_COUNTER],\r
+ .counter_id = OS_TICK_COUNTER,\r
+ .action =\r
+ {\r
+ .type = ALARM_ACTION_ACTIVATETASK,\r
+ .task_id = TASK_ID_bTask100,\r
+ .event_id = 0,\r
+ }\r
+ },\r
+};\r
+\r
+// --- HOOKS ---\r
+GEN_HOOKS( StartupHook, ProtectionHook, ShutdownHook, ErrorHook, PreTaskHook, PostTaskHook )\r
+\r
+// --- MISC ---\r
+uint32 os_dbg_mask = 0;\r
+\r
+// D_MASTER_PRINT |\\r
+// D_ISR_MASTER_PRINT |\\r
+// D_STDOUT |\\r
+// D_ISR_STDOUT |\r
+// D_ALARM | D_TASK;\r
+\r
+\r
+#include "os_config_funcs.h"\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*\r
+ * Os_Cfg.h\r
+ *\r
+ * Created on: 2008-dec-22\r
+ * Author: mahi\r
+ */\r
+#ifndef OS_CFG_H_\r
+#define OS_CFG_H_\r
+\r
+#include <limits.h>\r
+\r
+// APPS\r
+#define BLINKER_APP_ID 122\r
+#define APPLICATION_CNT 1\r
+\r
+// TASKS\r
+#define TASK_ID_OsIdle 0\r
+#define TASK_ID_bTask25 1\r
+#define TASK_ID_bTask100 2\r
+#define TASK_ID_Startup 3\r
+\r
+void OsIdle( void );\r
+void Startup( void );\r
+void bTask25( void );\r
+void bTask100( void );\r
+\r
+// ALARMS\r
+#define ALARM_USE\r
+#define ALARM_ID_bTask25 0\r
+#define ALARM_ID_bTask100 1\r
+\r
+// RESOURCES\r
+#define RES_ID_BLINK 1 // Den mysko RES_SCHEDULER är ju nr 0\r
+\r
+// MISC\r
+#define USE_IDLE_TASK\r
+#define PRIO_STACK_SIZE 4096\r
+#define OS_INTERRUPT_STACK_SIZE 4096\r
+#define EVENT_BLINK (1<<0)\r
+\r
+#endif /* OS_CFG_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef PORT_CFG_H_\r
+#define PORT_CFG_H_\r
+\r
+#include "Std_Types.h"\r
+\r
+#define PORT_VERSION_INFO_API STD_ON\r
+#define PORT_DEV_ERROR_DETECT STD_ON\r
+#define PORT_PIN_DIRECTION_CHANGES_ALLOWED STD_ON\r
+\r
+typedef enum\r
+{\r
+ PA0,\r
+ PA1,\r
+ PA2,\r
+ PA3,\r
+ PA4,\r
+ PA5,\r
+ PA6,\r
+ PA7,\r
+ PA8,\r
+ PA9,\r
+ PA10,\r
+ PA11,\r
+ PA12,\r
+ PA13,\r
+ PA14,\r
+ PA15,\r
+ PB0,\r
+ PB1,\r
+ PB2,\r
+ PB3,\r
+ PB4,\r
+ PB5,\r
+ PB6,\r
+ PB7,\r
+ PB8,\r
+ PB9,\r
+ PB10,\r
+ PB11,\r
+ PB12,\r
+ PB13,\r
+ PB14,\r
+ PB15,\r
+ PC0,\r
+ PC1,\r
+ PC2,\r
+ PC3,\r
+ PC4,\r
+ PC5,\r
+ PC6,\r
+ PC7,\r
+ PC8,\r
+ PC9,\r
+ PC10,\r
+ PC11,\r
+ PC12,\r
+ PC13,\r
+ PC14,\r
+ PC15,\r
+ PD0,\r
+ PD1,\r
+ PD2,\r
+ PD3,\r
+ PD4,\r
+ PD5,\r
+ PD6,\r
+ PD7,\r
+ PD8,\r
+ PD9,\r
+ PD10,\r
+ PD11,\r
+ PD12,\r
+ PD13,\r
+ PD14,\r
+ PD15,\r
+ PE0,\r
+ PE1,\r
+ PE2,\r
+ PE3,\r
+ PE4,\r
+ PE5,\r
+ PE6,\r
+ PE7,\r
+ PE8,\r
+ PE9,\r
+ PE10,\r
+ PE11,\r
+ PE12,\r
+ PE13,\r
+ PE14,\r
+ PE15,\r
+ PF0,\r
+ PF1,\r
+ PF2,\r
+ PF3,\r
+ PF4,\r
+ PF5,\r
+ PF6,\r
+ PF7,\r
+ PF8,\r
+ PF9,\r
+ PF10,\r
+ PF11,\r
+ PF12,\r
+ PF13,\r
+ PF14,\r
+ PF15,\r
+ PG0,\r
+ PG1,\r
+ PG2,\r
+ PG3,\r
+ PG4,\r
+ PG5,\r
+ PG6,\r
+ PG7,\r
+ PG8,\r
+ PG9,\r
+ PG10,\r
+ PG11,\r
+ PG12,\r
+ PG13,\r
+ PG14,\r
+ PG15,\r
+ PH0,\r
+ PH1,\r
+ PH2,\r
+ PH3,\r
+ PH4,\r
+ PH5,\r
+ PH6,\r
+ PH7,\r
+ PH8,\r
+ PH9,\r
+ PH10,\r
+ PH11,\r
+ PH12,\r
+ PH13,\r
+ PH14,\r
+ PH15,\r
+ PJ0,\r
+ PJ1,\r
+ PJ2,\r
+ PJ3,\r
+ PJ4,\r
+ PJ5,\r
+ PJ6,\r
+ PJ7,\r
+ PJ8,\r
+ PJ9,\r
+ PJ10,\r
+ PJ11,\r
+ PJ12,\r
+ PJ13,\r
+ PJ14,\r
+ PJ15,\r
+ PK0,\r
+ PK1\r
+} Port_PinType;\r
+\r
+#define BIT0 (1<<15)\r
+#define BIT1 (1<<14)\r
+#define BIT2 (1<<13)\r
+#define BIT3 (1<<12)\r
+#define BIT4 (1<<11)\r
+#define BIT5 (1<<10)\r
+#define BIT6 (1<<9)\r
+#define BIT7 (1<<8)\r
+#define BIT8 (1<<7)\r
+#define BIT9 (1<<6)\r
+#define BIT10 (1<<5)\r
+#define BIT11 (1<<4)\r
+#define BIT12 (1<<3)\r
+#define BIT13 (1<<2)\r
+#define BIT14 (1<<1)\r
+#define BIT15 (1<<0)\r
+\r
+#define WPE_BIT BIT14\r
+#define WPS_BIT BIT15\r
+#define SRC0 BIT12\r
+#define SRC1 BIT13\r
+\r
+#define PULL_UP (WPE_BIT|WPS_BIT)\r
+#define PULL_DOWN (WPE_BIT)\r
+#define PULL_NONE 0\r
+#define SLEW_RATE_MIN 0\r
+#define SLEW_RATE_MED BIT13\r
+#define SLEW_RATE_MAX (BIT12|BIT13)\r
+#define HYS_ENABLE BIT11\r
+#define ODE_ENABLE BIT10\r
+#define IBE_ENABLE BIT7\r
+#define OBE_ENABLE BIT6\r
+#define PA_IO 0\r
+#define PA_FUNC1 (BIT5)\r
+#define PA_FUNC2 (BIT4)\r
+#define PA_FUNC3 (BIT4|BIT5)\r
+\r
+#define NORMAL_INPUT (BIT15)\r
+\r
+// Should be this out of reset\r
+#define PCR_RESET (0)\r
+#define PCR_BOOTCFG (IBE_ENABLE|PULL_DOWN)\r
+\r
+typedef struct\r
+{\r
+ uint16_t padCnt;\r
+ const uint16_t *padConfig;\r
+ uint16_t outCnt;\r
+ const uint8_t *outConfig;\r
+// uint16_t inCnt;\r
+// const uint8_t *inConfig;\r
+} Port_ConfigType;\r
+\r
+extern const Port_ConfigType PortConfigData;\r
+\r
+#endif /*PORT_CFG_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*\r
+ * Pwm_Cfg.c\r
+ *\r
+ * Created on: 2009-jul-09\r
+ * Author: nian\r
+ */\r
+\r
+#include "Pwm.h"\r
+#include "Pwm_Cfg.h"\r
+\r
+extern void MyPwmNotificationRoutine(void);\r
+\r
+const Pwm_ConfigType PwmConfig = {\r
+ .Channels = {\r
+ PWM_CHANNEL_CONFIG(PWM_CHANNEL_1, 3000, 0x6000, PWM_CHANNEL_PRESCALER_4, PWM_HIGH),\r
+ PWM_CHANNEL_CONFIG(PWM_CHANNEL_2, 2000, 0x2000, PWM_CHANNEL_PRESCALER_2, PWM_LOW)\r
+ },\r
+#if PWM_NOTIFICATION_SUPPORTED==ON\r
+ .NotificationHandlers = {\r
+ MyPwmNotificationRoutine, // PWM_CHANNEL_1\r
+ NULL // PWM_CHANNEL_2\r
+ }\r
+#endif\r
+};\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*\r
+ * Pwm_Cfg.h\r
+ *\r
+ * Created on: 2009-jul-09\r
+ * Author: nian\r
+ */\r
+\r
+#ifndef PWM_CFG_H_\r
+#define PWM_CFG_H_\r
+\r
+/****************************************************************************\r
+ * Global configuration options and defines\r
+ */\r
+\r
+#define ON 1\r
+#define OFF 0\r
+\r
+/*\r
+ * PWM003: The detection of development errors is configurable (ON/OFF) at\r
+ * pre-compile time. The switch PwmDevErorDetect shall activate or disable\r
+ * the detection of all development errors\r
+ */\r
+#define PWM_DEV_EROR_DETECT ON\r
+#define PWM_GET_OUTPUT_STATE ON\r
+#define PWM_STATICALLY_CONFIGURED OFF\r
+#define PWM_NOTIFICATION_SUPPORTED ON\r
+\r
+#define PWM_SET_PERIOD_AND_DUTY ON\r
+\r
+/*\r
+ * PWM132: Switch for enabling the update of duty cycle parameter at the end\r
+ * of the current period.\r
+ *\r
+ * Note: Currently only ON mode is supported.\r
+ */\r
+#define PWM_DUTYCYCLE_UPDATED_ENDPERIOD ON\r
+\r
+/****************************************************************************\r
+ * Not defined in AUTOSAR.\r
+ */\r
+#define PWM_ISR_PRIORITY 1\r
+#define PWM_PRESCALER 64\r
+/*\r
+ * Setting to ON freezes the current output state of a PWM channel when in\r
+ * debug mode.\r
+ */\r
+#define PWM_FREEZE_ENABLE ON\r
+\r
+/****************************************************************************\r
+ * Enumeration of channels\r
+ * Maps a symbolic name to a hardware channel\r
+ */\r
+typedef enum {\r
+#if defined(CFG_BRD_MPC5516IT)\r
+ PWM_CHANNEL_1 = 13, /* Emios channel 13 and 12 map to the */\r
+ PWM_CHANNEL_2 = 12, /* LEDs LD4 and LD5 of MPC5516IT */\r
+\r
+#elif defined(CFG_BRD_MPC5567QRTECH)\r
+ PWM_CHANNEL_1 = 10, /* Emios channel 10 maps to PCR189 which\r
+ * is available on pin 54 of the\r
+ * ERNI 154822 connector\r
+ */\r
+ PWM_CHANNEL_2 = 12, /* Channel 12 goes to PCR191, also\r
+ * available on the ERNI 154822 connector\r
+ */\r
+#else\r
+#warning "Unknown board or CFG_BRD_* undefined"\r
+#endif\r
+ PWM_NUMBER_OF_CHANNELS = 2\r
+} Pwm_NamedChannelsType;\r
+\r
+#endif /* PWM_CFG_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+#include "Port_Cfg.h"\r
+\r
+// All: PA,OBE,IBE,ODE,HYS,SRC,WPE,WPS\r
+// Input: PA,OBE,IBE,HYS,WPE,WPS\r
+// Output: PA,OBE,IBE,ODE,SRC,(WPE,WPS)\r
+\r
+#define PCR_PWM PCR_BOOTCFG\r
+#define PCR_ADC (0)\r
+#define PCR_IO_INPUT PCR_BOOTCFG\r
+#define PCR_IO_OUTPUT OBE_ENABLE\r
+#define PCR_CAN (0)\r
+#define PCR_SPI PCR_BOOTCFG\r
+#define PCR_I2C PCR_BOOTCFG\r
+\r
+const uint16_t PortPadConfigData[] =\r
+{\r
+ // pad 0-15\r
+ PCR_RESET, /* PA0, AN0 */\r
+ PCR_RESET, /* PA1 */\r
+ PCR_RESET, /* PA2 */\r
+ PCR_RESET, /* PA3 */\r
+ PCR_RESET, /* PA4 */\r
+ PCR_RESET, /* PA5 */\r
+ PCR_RESET, /* PA6, */\r
+ PCR_RESET, /* PA7(input only) */\r
+ PCR_RESET, /* PA8(input only) */\r
+ PCR_RESET, /* PA9(input only) */\r
+ PCR_RESET, /* PA10(input only) */\r
+ PCR_RESET, /* PA11(input only) */\r
+ PCR_RESET, /* PA12(input only) */\r
+ PCR_RESET, /* PA13(input only) */\r
+ PCR_RESET, /* PA14(input only) */\r
+ PCR_RESET, /* PA15(input only) */\r
+\r
+ // pad 16-31\r
+ PCR_RESET, /* PB0 */\r
+ PCR_RESET, /* PB1 */\r
+ PCR_RESET, /* PB2 */\r
+ PCR_RESET, /* PB3 */\r
+ PCR_RESET, /* PB4 */\r
+ PCR_RESET, /* PB5 */\r
+ PCR_RESET, /* PB6 */\r
+ PCR_RESET, /* PB7 */\r
+ PCR_RESET, /* PB8 */\r
+ PCR_RESET, /* PB9 */\r
+ PCR_RESET, /* PB10 */\r
+ PCR_RESET, /* PB11 */\r
+ PCR_RESET, /* PB12 */\r
+ PCR_RESET, /* PB13 */\r
+ PCR_RESET, /* PB14 */\r
+ PCR_RESET, /* PB15 */\r
+\r
+ // pad 32-47\r
+ PA_FUNC1|OBE_ENABLE, /* PC0/emios0 */\r
+ PCR_RESET, // PC1\r
+ PCR_RESET, // PC2\r
+ PA_FUNC1|OBE_ENABLE, /* PC3 emios3, pin 117 */\r
+ PCR_RESET, /* PC4 */\r
+ PCR_RESET, /* PC5 */\r
+ PCR_RESET, /* PC6 */\r
+ PCR_RESET, /* PC7 */\r
+ PCR_RESET, /* PC8 */\r
+ PCR_RESET, /* PC9 */\r
+ PCR_RESET, /* PC10 */\r
+ PCR_RESET, /* PC11 */\r
+ PCR_RESET, /* PC12 */\r
+ PCR_RESET, /* PC13 */\r
+ PCR_RESET, /* PC14 */\r
+ PCR_RESET, /* PC15 */\r
+\r
+ // pad 48-63\r
+ PCR_RESET, /* PD0, CAN_A, Tx */\r
+ PCR_RESET, /* PD1, CAN_A, Rx */\r
+ PCR_BOOTCFG, /* PD2 */\r
+ PCR_RESET, /* PD3 */\r
+ PA_FUNC2|OBE_ENABLE, /* PD4, LED */\r
+ PA_FUNC2|OBE_ENABLE, /* PD5, LED */\r
+ PCR_RESET, /* PD6 , SCI_RS232??*/\r
+ PCR_RESET, /* PD7 , SCI_RS232??*/\r
+ (PA_FUNC1 | OBE_ENABLE | SLEW_RATE_MAX), /* PD8 LIN TX */\r
+ (PA_FUNC1 | IBE_ENABLE), /* PD9 LIN RX */\r
+ PCR_RESET, /* PD10 */\r
+ PCR_RESET, /* PD11 */\r
+ (PA_FUNC1 | OBE_ENABLE | SLEW_RATE_MAX), /* PD12 SPIB_CS0 */\r
+ (PA_FUNC1 | OBE_ENABLE | SLEW_RATE_MAX), /* PD13 SPIB_CLK*/\r
+ (PA_FUNC1 | OBE_ENABLE | SLEW_RATE_MAX), /* PD14 SPIB_SO*/\r
+ (PA_FUNC1 | IBE_ENABLE), /* PD15 SPIB_SI*/\r
+\r
+ // pad 64-79\r
+ (PA_FUNC1 | OBE_ENABLE | SLEW_RATE_MAX), /* PE0 SPIA_CS1 */\r
+ (PA_FUNC1 | OBE_ENABLE | SLEW_RATE_MAX), /* PE1 SPIA_CS2*/\r
+ PCR_RESET, /* PE2 */\r
+ (PA_FUNC1 | OBE_ENABLE | SLEW_RATE_MAX), /* PE3 SPIA_CLK*/\r
+ (PA_FUNC1 | OBE_ENABLE | SLEW_RATE_MAX), /* PE4 SPIA_SO*/\r
+ (PA_FUNC1 | IBE_ENABLE), /* PE5 SPIA_SI*/\r
+ PCR_RESET, /* PE6 */\r
+ PCR_RESET, /* PE7 */\r
+ PCR_RESET, /* PE8 */\r
+ PCR_RESET, /* PE9 */\r
+ PCR_RESET, /* PE10 */\r
+ PCR_RESET, /* PE11 */\r
+ PCR_RESET, /* PE12 */\r
+ PCR_RESET, /* PE13 */\r
+ PCR_RESET, /* PE14 */\r
+ PCR_RESET, /* PE15 */\r
+\r
+ // pad 80-95\r
+ PCR_RESET, /* PF0 */\r
+ PCR_RESET, /* PF1 */\r
+ PCR_RESET, /* PF2 */\r
+ PCR_RESET, /* PF3 */\r
+ PCR_RESET, /* PF4 */\r
+ PCR_RESET, /* PF5 */\r
+ PCR_RESET, /* PF6 */\r
+ PCR_RESET, /* PF7 */\r
+ PCR_RESET, /* PF8 */\r
+ PCR_RESET, /* PF9 */\r
+ PCR_RESET, /* PF10 */\r
+ PCR_RESET, /* PF11 */\r
+ PA_FUNC2|OBE_ENABLE|PULL_UP, /* PF12 SCI_D Transmit, J1708 Tx*/\r
+ PA_FUNC2|IBE_ENABLE|PULL_UP, /* PF13 SCI_D Receive, J1708 Rx*/\r
+ PCR_RESET, /* PF14 */\r
+ PCR_RESET, /* PF15 */\r
+\r
+ // pad 96-111\r
+ PCR_RESET, /* PG0 */\r
+ PA_FUNC2|IBE_ENABLE|PULL_UP, /* PG1 eMIOS[17], J1708 Edgedetect*/\r
+ PCR_RESET, /* PG2 */\r
+ PCR_RESET, /* PG3 */\r
+ PCR_RESET, /* PG4 */\r
+ PCR_RESET, /* PG5 */\r
+ PCR_RESET, /* PG6 */\r
+ PCR_RESET, /* PG7 */\r
+ PCR_RESET, /* PG8 */\r
+ PCR_RESET, /* PG9 */\r
+ PCR_RESET, /* PG10 */\r
+ PCR_RESET, /* PG11 */\r
+ PCR_RESET, /* PG12 */\r
+ PCR_RESET, /* PG13 */\r
+ PCR_RESET, /* PG14 */\r
+ PCR_RESET, /* PG15 */\r
+\r
+ // pad 112-127\r
+ PCR_RESET, /* PH0 */\r
+ PCR_RESET, /* PH1 */\r
+ PCR_RESET, /* PH2 */\r
+ PCR_RESET, /* PH3 */\r
+ PCR_RESET, /* PH4 */\r
+ PCR_RESET, /* PH5 */\r
+ PCR_RESET, /* PH6 */\r
+ PCR_RESET, /* PH7 */\r
+ PCR_RESET, /* PH8 */\r
+ PCR_RESET, /* PH9 */\r
+ PCR_RESET, /* PH10 */\r
+ PCR_RESET, /* PH11 */\r
+ PCR_RESET, /* PH12 */\r
+ PCR_RESET, /* PH13 */\r
+ PCR_RESET, /* PH14 */\r
+ PCR_RESET, /* PH15 */\r
+\r
+ // pad 128-143\r
+ PCR_RESET, /* PJ0 */\r
+ PCR_RESET, /* PJ1 */\r
+ PCR_RESET, /* PJ2 */\r
+ PCR_RESET, /* PJ3 */\r
+ PCR_RESET, /* PJ4 */\r
+ PCR_RESET, /* PJ5 */\r
+ PCR_RESET, /* PJ6 */\r
+ PCR_RESET, /* PJ7 */\r
+ PCR_RESET, /* PJ8 */\r
+ PCR_RESET, /* PJ9 */\r
+ PCR_RESET, /* PJ10 */\r
+ PCR_RESET, /* PJ11 */\r
+ PCR_RESET, /* PJ12 */\r
+ PCR_RESET, /* PJ13 */\r
+ PCR_RESET, /* PJ14 */\r
+ PCR_RESET, /* PJ15 */\r
+\r
+ // pad 144-145\r
+ PCR_RESET, /* PK0 (input only) */\r
+ PCR_RESET, /* PK1 (input only)*/\r
+};\r
+\r
+#define GPDO_RESET 0\r
+\r
+const uint8_t PortOutConfigData[] =\r
+{\r
+ // pad 16-31\r
+ GPDO_RESET, /* PB0 */\r
+ GPDO_RESET, /* PB1 */\r
+ GPDO_RESET, /* PB2 */\r
+ GPDO_RESET, /* PB3 */\r
+ GPDO_RESET, /* PB4 */\r
+ GPDO_RESET, /* PB5 */\r
+ GPDO_RESET, /* PB6 */\r
+ GPDO_RESET, /* PB7 */\r
+ GPDO_RESET, /* PB8 */\r
+ GPDO_RESET, /* PB9 */\r
+ GPDO_RESET, /* PB10 */\r
+ GPDO_RESET, /* PB11 */\r
+ GPDO_RESET, /* PB12 */\r
+ GPDO_RESET, /* PB13 */\r
+ GPDO_RESET, /* PB14 */\r
+ GPDO_RESET, /* PB15 */\r
+\r
+ // pad 32-47\r
+ GPDO_RESET, /* PC0 */\r
+ GPDO_RESET, /* PC1 */\r
+ GPDO_RESET, /* PC2 */\r
+ GPDO_RESET, /* PC3 */\r
+ GPDO_RESET, /* PC4 */\r
+ GPDO_RESET, /* PC5 */\r
+ GPDO_RESET, /* PC6 */\r
+ GPDO_RESET, /* PC7 */\r
+ GPDO_RESET, /* PC8 */\r
+ GPDO_RESET, /* PC9 */\r
+ GPDO_RESET, /* PC10 */\r
+ GPDO_RESET, /* PC11 */\r
+ GPDO_RESET, /* PC12 */\r
+ GPDO_RESET, /* PC13 */\r
+ GPDO_RESET, /* PC14 */\r
+ GPDO_RESET, /* PC15 */\r
+\r
+ // pad 48-63\r
+ GPDO_RESET, /* PD0 */\r
+ GPDO_RESET, /* PD1 */\r
+ GPDO_RESET, /* PD2 */\r
+ GPDO_RESET, /* PD3 */\r
+ GPDO_RESET, /* PD4 */\r
+ GPDO_RESET, /* PD5 */\r
+ GPDO_RESET, /* PD6 */\r
+ GPDO_RESET, /* PD7 */\r
+ GPDO_RESET, /* PD8 */\r
+ GPDO_RESET, /* PD9 */\r
+ GPDO_RESET, /* PD10 */\r
+ GPDO_RESET, /* PD11 */\r
+ GPDO_RESET, /* PD12 */\r
+ GPDO_RESET, /* PD13 */\r
+ GPDO_RESET, /* PD14 */\r
+ GPDO_RESET, /* PD15 */\r
+\r
+ // pad 64-79\r
+ GPDO_RESET, /* PE0 */\r
+ GPDO_RESET, /* PE1 */\r
+ GPDO_RESET, /* PE2 */\r
+ GPDO_RESET, /* PE3 */\r
+ GPDO_RESET, /* PE4 */\r
+ GPDO_RESET, /* PE5 */\r
+ GPDO_RESET, /* PE6 */\r
+ GPDO_RESET, /* PE7 */\r
+ GPDO_RESET, /* PE8 */\r
+ GPDO_RESET, /* PE9 */\r
+ GPDO_RESET, /* PE10 */\r
+ GPDO_RESET, /* PE11 */\r
+ GPDO_RESET, /* PE12 */\r
+ GPDO_RESET, /* PE13 */\r
+ GPDO_RESET, /* PE14 */\r
+ GPDO_RESET, /* PE15 */\r
+\r
+ // pad 80-95\r
+ GPDO_RESET, /* PF0 */\r
+ GPDO_RESET, /* PF1 */\r
+ GPDO_RESET, /* PF2 */\r
+ GPDO_RESET, /* PF3 */\r
+ GPDO_RESET, /* PF4 */\r
+ GPDO_RESET, /* PF5 */\r
+ GPDO_RESET, /* PF6 */\r
+ GPDO_RESET, /* PF7 */\r
+ GPDO_RESET, /* PF8 */\r
+ GPDO_RESET, /* PF9 */\r
+ GPDO_RESET, /* PF10 */\r
+ GPDO_RESET, /* PF11 */\r
+ GPDO_RESET, /* PF12 */\r
+ GPDO_RESET, /* PF13 */\r
+ GPDO_RESET, /* PF14 */\r
+ GPDO_RESET, /* PF15 */\r
+\r
+ // pad 96-111\r
+ GPDO_RESET, /* PG0 */\r
+ GPDO_RESET, /* PG1 */\r
+ GPDO_RESET, /* PG2 */\r
+ GPDO_RESET, /* PG3 */\r
+ GPDO_RESET, /* PG4 */\r
+ GPDO_RESET, /* PG5 */\r
+ GPDO_RESET, /* PG6 */\r
+ GPDO_RESET, /* PG7 */\r
+ GPDO_RESET, /* PG8 */\r
+ GPDO_RESET, /* PG9 */\r
+ GPDO_RESET, /* PG10 */\r
+ GPDO_RESET, /* PG11 */\r
+ GPDO_RESET, /* PG12 */\r
+ GPDO_RESET, /* PG13 */\r
+ GPDO_RESET, /* PG14 */\r
+ GPDO_RESET, /* PG15 */\r
+\r
+ // pad 112-127\r
+ GPDO_RESET, /* PH0 */\r
+ GPDO_RESET, /* PH1 */\r
+ GPDO_RESET, /* PH2 */\r
+ GPDO_RESET, /* PH3 */\r
+ GPDO_RESET, /* PH4 */\r
+ GPDO_RESET, /* PH5 */\r
+ GPDO_RESET, /* PH6 */\r
+ GPDO_RESET, /* PH7 */\r
+ GPDO_RESET, /* PH8 */\r
+ GPDO_RESET, /* PH9 */\r
+ GPDO_RESET, /* PH10 */\r
+ GPDO_RESET, /* PH11 */\r
+ GPDO_RESET, /* PH12 */\r
+ GPDO_RESET, /* PH13 */\r
+ GPDO_RESET, /* PH14 */\r
+ GPDO_RESET, /* PH15 */\r
+\r
+ // pad 128-143\r
+ GPDO_RESET, /* PJ0 */\r
+ GPDO_RESET, /* PJ1 */\r
+ GPDO_RESET, /* PJ2 */\r
+ GPDO_RESET, /* PJ3 */\r
+ GPDO_RESET, /* PJ4 */\r
+ GPDO_RESET, /* PJ5 */\r
+ GPDO_RESET, /* PJ6 */\r
+ GPDO_RESET, /* PJ7 */\r
+ GPDO_RESET, /* PJ8 */\r
+ GPDO_RESET, /* PJ9 */\r
+ GPDO_RESET, /* PJ10 */\r
+ GPDO_RESET, /* PJ11 */\r
+ GPDO_RESET, /* PJ12 */\r
+ GPDO_RESET, /* PJ13 */\r
+ GPDO_RESET, /* PJ14 */\r
+ GPDO_RESET, /* PJ15 */\r
+};\r
+\r
+//#define GPDI_RESET 0\r
+//const uint8_t PortInConfigData[] =\r
+//{\r
+// // pad 0-15\r
+// GPDI_RESET, /* PA0(input only) */\r
+// GPDI_RESET, /* PA1(input only) */\r
+// GPDI_RESET, /* PA2(input only) */\r
+// GPDI_RESET, /* PA3(input only) */\r
+// GPDI_RESET, /* PA4(input only) */\r
+// GPDI_RESET, /* PA5(input only) */\r
+// GPDI_RESET, /* PA6(input only) */\r
+// GPDI_RESET, /* PA7(input only) */\r
+// GPDI_RESET, /* PA8(input only) */\r
+// GPDI_RESET, /* PA9(input only) */\r
+// GPDI_RESET, /* PA10(input only) */\r
+// GPDI_RESET, /* PA11(input only) */\r
+// GPDI_RESET, /* PA12(input only) */\r
+// GPDI_RESET, /* PA13(input only) */\r
+// GPDI_RESET, /* PA14(input only) */\r
+// GPDI_RESET, /* PA15(input only) */\r
+//\r
+// // pad 16-31\r
+// GPDI_RESET, /* PB0 */\r
+// GPDI_RESET, /* PB1 */\r
+// GPDI_RESET, /* PB2 */\r
+// GPDI_RESET, /* PB3 */\r
+// GPDI_RESET, /* PB4 */\r
+// GPDI_RESET, /* PB5 */\r
+// GPDI_RESET, /* PB6 */\r
+// GPDI_RESET, /* PB7 */\r
+// GPDI_RESET, /* PB8 */\r
+// GPDI_RESET, /* PB9 */\r
+// GPDI_RESET, /* PB10 */\r
+// GPDI_RESET, /* PB11 */\r
+// GPDI_RESET, /* PB12 */\r
+// GPDI_RESET, /* PB13 */\r
+// GPDI_RESET, /* PB14 */\r
+// GPDI_RESET, /* PB15 */\r
+//\r
+// // pad 32-47\r
+// GPDI_RESET, /* PC0 */\r
+// GPDI_RESET, /* PC1 */\r
+// GPDI_RESET, /* PC2 */\r
+// GPDI_RESET, /* PC3 */\r
+// GPDI_RESET, /* PC4 */\r
+// GPDI_RESET, /* PC5 */\r
+// GPDI_RESET, /* PC6 */\r
+// GPDI_RESET, /* PC7 */\r
+// GPDI_RESET, /* PC8 */\r
+// GPDI_RESET, /* PC9 */\r
+// GPDI_RESET, /* PC10 */\r
+// GPDI_RESET, /* PC11 */\r
+// GPDI_RESET, /* PC12 */\r
+// GPDI_RESET, /* PC13 */\r
+// GPDI_RESET, /* PC14 */\r
+// GPDI_RESET, /* PC15 */\r
+//\r
+// // pad 48-63\r
+// GPDI_RESET, /* PD0 */\r
+// GPDI_RESET, /* PD1 */\r
+// GPDI_RESET, /* PD2 */\r
+// GPDI_RESET, /* PD3 */\r
+// GPDI_RESET, /* PD4 */\r
+// GPDI_RESET, /* PD5 */\r
+// GPDI_RESET, /* PD6 */\r
+// GPDI_RESET, /* PD7 */\r
+// GPDI_RESET, /* PD8 */\r
+// GPDI_RESET, /* PD9 */\r
+// GPDI_RESET, /* PD10 */\r
+// GPDI_RESET, /* PD11 */\r
+// GPDI_RESET, /* PD12 */\r
+// GPDI_RESET, /* PD13 */\r
+// GPDI_RESET, /* PD14 */\r
+// GPDI_RESET, /* PD15 */\r
+//\r
+// // pad 64-79\r
+// GPDI_RESET, /* PE0 */\r
+// GPDI_RESET, /* PE1 */\r
+// GPDI_RESET, /* PE2 */\r
+// GPDI_RESET, /* PE3 */\r
+// GPDI_RESET, /* PE4 */\r
+// GPDI_RESET, /* PE5 */\r
+// GPDI_RESET, /* PE6 */\r
+// GPDI_RESET, /* PE7 */\r
+// GPDI_RESET, /* PE8 */\r
+// GPDI_RESET, /* PE9 */\r
+// GPDI_RESET, /* PE10 */\r
+// GPDI_RESET, /* PE11 */\r
+// GPDI_RESET, /* PE12 */\r
+// GPDI_RESET, /* PE13 */\r
+// GPDI_RESET, /* PE14 */\r
+// GPDI_RESET, /* PE15 */\r
+//\r
+// // pad 80-95\r
+// GPDI_RESET, /* PF0 */\r
+// GPDI_RESET, /* PF1 */\r
+// GPDI_RESET, /* PF2 */\r
+// GPDI_RESET, /* PF3 */\r
+// GPDI_RESET, /* PF4 */\r
+// GPDI_RESET, /* PF5 */\r
+// GPDI_RESET, /* PF6 */\r
+// GPDI_RESET, /* PF7 */\r
+// GPDI_RESET, /* PF8 */\r
+// GPDI_RESET, /* PF9 */\r
+// GPDI_RESET, /* PF10 */\r
+// GPDI_RESET, /* PF11 */\r
+// GPDI_RESET, /* PF12 */\r
+// GPDI_RESET, /* PF13 */\r
+// GPDI_RESET, /* PF14 */\r
+// GPDI_RESET, /* PF15 */\r
+//\r
+// // pad 96-111\r
+// GPDI_RESET, /* PG0 */\r
+// GPDI_RESET, /* PG1 */\r
+// GPDI_RESET, /* PG2 */\r
+// GPDI_RESET, /* PG3 */\r
+// GPDI_RESET, /* PG4 */\r
+// GPDI_RESET, /* PG5 */\r
+// GPDI_RESET, /* PG6 */\r
+// GPDI_RESET, /* PG7 */\r
+// GPDI_RESET, /* PG8 */\r
+// GPDI_RESET, /* PG9 */\r
+// GPDI_RESET, /* PG10 */\r
+// GPDI_RESET, /* PG11 */\r
+// GPDI_RESET, /* PG12 */\r
+// GPDI_RESET, /* PG13 */\r
+// GPDI_RESET, /* PG14 */\r
+// GPDI_RESET, /* PG15 */\r
+//\r
+// // pad 112-127\r
+// GPDI_RESET, /* PH0 */\r
+// GPDI_RESET, /* PH1 */\r
+// GPDI_RESET, /* PH2 */\r
+// GPDI_RESET, /* PH3 */\r
+// GPDI_RESET, /* PH4 */\r
+// GPDI_RESET, /* PH5 */\r
+// GPDI_RESET, /* PH6 */\r
+// GPDI_RESET, /* PH7 */\r
+// GPDI_RESET, /* PH8 */\r
+// GPDI_RESET, /* PH9 */\r
+// GPDI_RESET, /* PH10 */\r
+// GPDI_RESET, /* PH11 */\r
+// GPDI_RESET, /* PH12 */\r
+// GPDI_RESET, /* PH13 */\r
+// GPDI_RESET, /* PH14 */\r
+// GPDI_RESET, /* PH15 */\r
+//\r
+// // pad 128-143\r
+// GPDI_RESET, /* PJ0 */\r
+// GPDI_RESET, /* PJ1 */\r
+// GPDI_RESET, /* PJ2 */\r
+// GPDI_RESET, /* PJ3 */\r
+// GPDI_RESET, /* PJ4 */\r
+// GPDI_RESET, /* PJ5 */\r
+// GPDI_RESET, /* PJ6 */\r
+// GPDI_RESET, /* PJ7 */\r
+// GPDI_RESET, /* PJ8 */\r
+// GPDI_RESET, /* PJ9 */\r
+// GPDI_RESET, /* PJ10 */\r
+// GPDI_RESET, /* PJ11 */\r
+// GPDI_RESET, /* PJ12 */\r
+// GPDI_RESET, /* PJ13 */\r
+// GPDI_RESET, /* PJ14 */\r
+// GPDI_RESET, /* PJ15 */\r
+//\r
+// // pad 144-145\r
+// GPDI_RESET, /* PK0 (input only) */\r
+// GPDI_RESET, /* PK1 (input only) */\r
+//};\r
+\r
+const Port_ConfigType PortConfigData =\r
+{\r
+ .padCnt = sizeof(PortPadConfigData),\r
+ .padConfig = PortPadConfigData,\r
+ .outCnt = sizeof(PortOutConfigData),\r
+ .outConfig = PortOutConfigData,\r
+// .inCnt = sizeof(PortInConfigData),\r
+// .inConfig = PortInConfigData,\r
+};\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef PORT_CFG_H_\r
+#define PORT_CFG_H_\r
+\r
+#include "Std_Types.h"\r
+\r
+#define PORT_VERSION_INFO_API STD_ON\r
+#define PORT_DEV_ERROR_DETECT STD_ON\r
+#define PORT_PIN_DIRECTION_CHANGES_ALLOWED STD_ON\r
+\r
+typedef enum\r
+{\r
+ PA0,\r
+ PA1,\r
+ PA2,\r
+ PA3,\r
+ PA4,\r
+ PA5,\r
+ PA6,\r
+ PA7,\r
+ PA8,\r
+ PA9,\r
+ PA10,\r
+ PA11,\r
+ PA12,\r
+ PA13,\r
+ PA14,\r
+ PA15,\r
+ PB0,\r
+ PB1,\r
+ PB2,\r
+ PB3,\r
+ PB4,\r
+ PB5,\r
+ PB6,\r
+ PB7,\r
+ PB8,\r
+ PB9,\r
+ PB10,\r
+ PB11,\r
+ PB12,\r
+ PB13,\r
+ PB14,\r
+ PB15,\r
+ PC0,\r
+ PC1,\r
+ PC2,\r
+ PC3,\r
+ PC4,\r
+ PC5,\r
+ PC6,\r
+ PC7,\r
+ PC8,\r
+ PC9,\r
+ PC10,\r
+ PC11,\r
+ PC12,\r
+ PC13,\r
+ PC14,\r
+ PC15,\r
+ PD0,\r
+ PD1,\r
+ PD2,\r
+ PD3,\r
+ PD4,\r
+ PD5,\r
+ PD6,\r
+ PD7,\r
+ PD8,\r
+ PD9,\r
+ PD10,\r
+ PD11,\r
+ PD12,\r
+ PD13,\r
+ PD14,\r
+ PD15,\r
+ PE0,\r
+ PE1,\r
+ PE2,\r
+ PE3,\r
+ PE4,\r
+ PE5,\r
+ PE6,\r
+ PE7,\r
+ PE8,\r
+ PE9,\r
+ PE10,\r
+ PE11,\r
+ PE12,\r
+ PE13,\r
+ PE14,\r
+ PE15,\r
+ PF0,\r
+ PF1,\r
+ PF2,\r
+ PF3,\r
+ PF4,\r
+ PF5,\r
+ PF6,\r
+ PF7,\r
+ PF8,\r
+ PF9,\r
+ PF10,\r
+ PF11,\r
+ PF12,\r
+ PF13,\r
+ PF14,\r
+ PF15,\r
+ PG0,\r
+ PG1,\r
+ PG2,\r
+ PG3,\r
+ PG4,\r
+ PG5,\r
+ PG6,\r
+ PG7,\r
+ PG8,\r
+ PG9,\r
+ PG10,\r
+ PG11,\r
+ PG12,\r
+ PG13,\r
+ PG14,\r
+ PG15,\r
+ PH0,\r
+ PH1,\r
+ PH2,\r
+ PH3,\r
+ PH4,\r
+ PH5,\r
+ PH6,\r
+ PH7,\r
+ PH8,\r
+ PH9,\r
+ PH10,\r
+ PH11,\r
+ PH12,\r
+ PH13,\r
+ PH14,\r
+ PH15,\r
+ PJ0,\r
+ PJ1,\r
+ PJ2,\r
+ PJ3,\r
+ PJ4,\r
+ PJ5,\r
+ PJ6,\r
+ PJ7,\r
+ PJ8,\r
+ PJ9,\r
+ PJ10,\r
+ PJ11,\r
+ PJ12,\r
+ PJ13,\r
+ PJ14,\r
+ PJ15,\r
+ PK0,\r
+ PK1\r
+} Port_PinType;\r
+\r
+#define BIT0 (1<<15)\r
+#define BIT1 (1<<14)\r
+#define BIT2 (1<<13)\r
+#define BIT3 (1<<12)\r
+#define BIT4 (1<<11)\r
+#define BIT5 (1<<10)\r
+#define BIT6 (1<<9)\r
+#define BIT7 (1<<8)\r
+#define BIT8 (1<<7)\r
+#define BIT9 (1<<6)\r
+#define BIT10 (1<<5)\r
+#define BIT11 (1<<4)\r
+#define BIT12 (1<<3)\r
+#define BIT13 (1<<2)\r
+#define BIT14 (1<<1)\r
+#define BIT15 (1<<0)\r
+\r
+#define WPE_BIT BIT14\r
+#define WPS_BIT BIT15\r
+#define SRC0 BIT12\r
+#define SRC1 BIT13\r
+\r
+#define PULL_UP (WPE_BIT|WPS_BIT)\r
+#define PULL_DOWN (WPE_BIT)\r
+#define PULL_NONE 0\r
+#define SLEW_RATE_MIN 0\r
+#define SLEW_RATE_MED BIT13\r
+#define SLEW_RATE_MAX (BIT12|BIT13)\r
+#define HYS_ENABLE BIT11\r
+#define ODE_ENABLE BIT10\r
+#define IBE_ENABLE BIT7\r
+#define OBE_ENABLE BIT6\r
+#define PA_IO 0\r
+#define PA_FUNC1 (BIT5)\r
+#define PA_FUNC2 (BIT4)\r
+#define PA_FUNC3 (BIT4|BIT5)\r
+\r
+#define NORMAL_INPUT (BIT15)\r
+\r
+// Should be this out of reset\r
+#define PCR_RESET (0)\r
+#define PCR_BOOTCFG (IBE_ENABLE|PULL_DOWN)\r
+\r
+#define EVB_TEST_CONFIG (&PortConfigData)\r
+\r
+typedef struct\r
+{\r
+ uint16_t padCnt;\r
+ const uint16_t *padConfig;\r
+ uint16_t outCnt;\r
+ const uint8_t *outConfig;\r
+// uint16_t inCnt;\r
+// const uint8_t *inConfig;\r
+} Port_ConfigType;\r
+\r
+extern const Port_ConfigType PortConfigData;\r
+\r
+#endif /*PORT_CFG_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*\r
+ * Port_Cfg.c\r
+ *\r
+ * Created on: 2009-jul-08\r
+ * Author: rosa\r
+ */\r
+\r
+#include "Port_Cfg.h"\r
+\r
+\r
+const uint16_t PortPadConfigData[] = {\r
+ PCR_RESET, // SIU_PCR0\r
+ PCR_RESET, // SIU_PCR1\r
+ PCR_RESET, // SIU_PCR2\r
+ PCR_RESET, // SIU_PCR3\r
+ PCR_RESET, // SIU_PCR4\r
+ PCR_RESET, // SIU_PCR5\r
+ PCR_RESET, // SIU_PCR6\r
+ PCR_RESET, // SIU_PCR7\r
+ PCR_RESET, // SIU_PCR8\r
+ PCR_RESET, // SIU_PCR9\r
+ PCR_RESET, // SIU_PCR10\r
+ PCR_RESET, // SIU_PCR11\r
+ PCR_RESET, // SIU_PCR12\r
+ PCR_RESET, // SIU_PCR13\r
+ PCR_RESET, // SIU_PCR14\r
+ PCR_RESET, // SIU_PCR15\r
+ PCR_RESET, // SIU_PCR16\r
+ PCR_RESET, // SIU_PCR17\r
+ PCR_RESET, // SIU_PCR18\r
+ PCR_RESET, // SIU_PCR19\r
+ PCR_RESET, // SIU_PCR20\r
+ PCR_RESET, // SIU_PCR21\r
+ PCR_RESET, // SIU_PCR22\r
+ PCR_RESET, // SIU_PCR23\r
+ PCR_RESET, // SIU_PCR24\r
+ PCR_RESET, // SIU_PCR25\r
+ PCR_RESET, // SIU_PCR26\r
+ PCR_RESET, // SIU_PCR27\r
+ PCR_RESET, // SIU_PCR28\r
+ PCR_RESET, // SIU_PCR29\r
+ PCR_RESET, // SIU_PCR30\r
+ PCR_RESET, // SIU_PCR31\r
+ PCR_RESET, // SIU_PCR32\r
+ PCR_RESET, // SIU_PCR33\r
+ PCR_RESET, // SIU_PCR34\r
+ PCR_RESET, // SIU_PCR35\r
+ PCR_RESET, // SIU_PCR36\r
+ PCR_RESET, // SIU_PCR37\r
+ PCR_RESET, // SIU_PCR38\r
+ PCR_RESET, // SIU_PCR39\r
+ PCR_RESET, // SIU_PCR40\r
+ PCR_RESET, // SIU_PCR41\r
+ PCR_RESET, // SIU_PCR42\r
+ PCR_RESET, // SIU_PCR43\r
+ PCR_RESET, // SIU_PCR44\r
+ PCR_RESET, // SIU_PCR45\r
+ PCR_RESET, // SIU_PCR46\r
+ PCR_RESET, // SIU_PCR47\r
+ PCR_RESET, // SIU_PCR48\r
+ PCR_RESET, // SIU_PCR49\r
+ PCR_RESET, // SIU_PCR50\r
+ PCR_RESET, // SIU_PCR51\r
+ PCR_RESET, // SIU_PCR52\r
+ PCR_RESET, // SIU_PCR53\r
+ PCR_RESET, // SIU_PCR54\r
+ PCR_RESET, // SIU_PCR55\r
+ PCR_RESET, // SIU_PCR56\r
+ PCR_RESET, // SIU_PCR57\r
+ PCR_RESET, // SIU_PCR58\r
+ PCR_RESET, // SIU_PCR59\r
+ PCR_RESET, // SIU_PCR60\r
+ PCR_RESET, // SIU_PCR61\r
+ PCR_RESET, // SIU_PCR62\r
+ PCR_RESET, // SIU_PCR63\r
+ PCR_RESET, // SIU_PCR64\r
+ PCR_RESET, // SIU_PCR65\r
+ PCR_RESET, // SIU_PCR66\r
+ PCR_RESET, // SIU_PCR67\r
+ PCR_RESET, // SIU_PCR68\r
+ PCR_RESET, // SIU_PCR69\r
+ PCR_RESET, // SIU_PCR70\r
+ PCR_RESET, // SIU_PCR71\r
+ PCR_RESET, // SIU_PCR72\r
+ PCR_RESET, // SIU_PCR73\r
+ PCR_RESET, // SIU_PCR74\r
+ PCR_RESET, // SIU_PCR75\r
+ PCR_RESET, // SIU_PCR76\r
+ PCR_RESET, // SIU_PCR77\r
+ PCR_RESET, // SIU_PCR78\r
+ PCR_RESET, // SIU_PCR79\r
+ PCR_RESET, // SIU_PCR80\r
+ PCR_RESET, // SIU_PCR81\r
+ PCR_RESET, // SIU_PCR82\r
+ PCR_RESET, // SIU_PCR83\r
+ PCR_RESET, // SIU_PCR84\r
+ PCR_RESET, // SIU_PCR85\r
+ PCR_RESET, // SIU_PCR86\r
+ PCR_RESET, // SIU_PCR87\r
+ PCR_RESET, // SIU_PCR88\r
+ PCR_RESET, // SIU_PCR89\r
+ PCR_RESET, // SIU_PCR90\r
+ PCR_RESET, // SIU_PCR91\r
+ PCR_RESET, // SIU_PCR92\r
+ PCR_RESET, // SIU_PCR93\r
+ PCR_RESET, // SIU_PCR94\r
+ PCR_RESET, // SIU_PCR95\r
+ PCR_RESET, // SIU_PCR96\r
+ PCR_RESET, // SIU_PCR97\r
+ PCR_RESET, // SIU_PCR98\r
+ PCR_RESET, // SIU_PCR99\r
+ PCR_RESET, // SIU_PCR100\r
+ PCR_RESET, // SIU_PCR101\r
+ PCR_RESET, // SIU_PCR102\r
+ PCR_RESET, // SIU_PCR103\r
+ PCR_RESET, // SIU_PCR104\r
+ PCR_RESET, // SIU_PCR105\r
+ PCR_RESET, // SIU_PCR106\r
+ PCR_RESET, // SIU_PCR107\r
+ PCR_RESET, // SIU_PCR108\r
+ PCR_RESET, // SIU_PCR109\r
+ PCR_RESET, // SIU_PCR110\r
+ PCR_RESET, // SIU_PCR111\r
+ PCR_RESET, // SIU_PCR112\r
+ PCR_RESET, // SIU_PCR113\r
+ PCR_RESET, // SIU_PCR114\r
+ PCR_RESET, // SIU_PCR115\r
+ PCR_RESET, // SIU_PCR116\r
+ PCR_RESET, // SIU_PCR117\r
+ PCR_RESET, // SIU_PCR118\r
+ PCR_RESET, // SIU_PCR119\r
+ PCR_RESET, // SIU_PCR120\r
+ PCR_RESET, // SIU_PCR121\r
+ PCR_RESET, // SIU_PCR122\r
+ PCR_RESET, // SIU_PCR123\r
+ PCR_RESET, // SIU_PCR124\r
+ PCR_IO_OUTPUT, // SIU_PCR125 detta borde vara dioden som sitter på K2\r
+ PCR_RESET, // SIU_PCR126\r
+ PCR_RESET, // SIU_PCR127\r
+ PCR_RESET, // SIU_PCR128\r
+ PCR_RESET, // SIU_PCR129\r
+ PCR_RESET, // SIU_PCR130\r
+ PCR_RESET, // SIU_PCR131\r
+ PCR_RESET, // SIU_PCR132\r
+ PCR_RESET, // SIU_PCR133\r
+ PCR_RESET, // SIU_PCR134\r
+ PCR_RESET, // SIU_PCR135\r
+ PCR_RESET, // SIU_PCR136\r
+ PCR_RESET, // SIU_PCR137\r
+ PCR_RESET, // SIU_PCR138\r
+ PCR_RESET, // SIU_PCR139\r
+ PCR_RESET, // SIU_PCR140\r
+ PCR_RESET, // SIU_PCR141\r
+ PCR_RESET, // SIU_PCR142\r
+ PCR_RESET, // SIU_PCR143\r
+ PCR_RESET, // SIU_PCR144\r
+ PCR_RESET, // SIU_PCR145\r
+ PCR_RESET, // SIU_PCR146\r
+ PCR_RESET, // SIU_PCR147\r
+ PCR_RESET, // SIU_PCR148\r
+ PCR_RESET, // SIU_PCR149\r
+ PCR_RESET, // SIU_PCR150\r
+ PCR_RESET, // SIU_PCR151\r
+ PCR_RESET, // SIU_PCR152\r
+ PCR_RESET, // SIU_PCR153\r
+ PCR_RESET, // SIU_PCR154\r
+ PCR_RESET, // SIU_PCR155\r
+ PCR_RESET, // SIU_PCR156\r
+ PCR_RESET, // SIU_PCR157\r
+ PCR_RESET, // SIU_PCR158\r
+ PCR_RESET, // SIU_PCR159\r
+ PCR_RESET, // SIU_PCR160\r
+ PCR_RESET, // SIU_PCR161\r
+ PCR_RESET, // SIU_PCR162\r
+ PCR_RESET, // SIU_PCR163\r
+ PCR_RESET, // SIU_PCR164\r
+ PCR_RESET, // SIU_PCR165\r
+ PCR_RESET, // SIU_PCR166\r
+ PCR_RESET, // SIU_PCR167\r
+ PCR_RESET, // SIU_PCR168\r
+ PCR_RESET, // SIU_PCR169\r
+ PCR_RESET, // SIU_PCR170\r
+ PCR_RESET, // SIU_PCR171\r
+ PCR_RESET, // SIU_PCR172\r
+ PCR_RESET, // SIU_PCR173\r
+ PCR_RESET, // SIU_PCR174\r
+ PCR_RESET, // SIU_PCR175\r
+ PCR_RESET, // SIU_PCR176\r
+ PCR_RESET, // SIU_PCR177\r
+ PCR_RESET, // SIU_PCR178\r
+ PCR_RESET, // SIU_PCR179\r
+ PCR_RESET, // SIU_PCR180\r
+ PCR_RESET, // SIU_PCR181\r
+ PCR_RESET, // SIU_PCR182\r
+ PCR_RESET, // SIU_PCR183\r
+ PCR_RESET, // SIU_PCR184\r
+ PCR_RESET, // SIU_PCR185\r
+ PCR_RESET, // SIU_PCR186\r
+ PCR_RESET, // SIU_PCR187\r
+ PCR_RESET, // SIU_PCR188\r
+ PA_PRIMARY_FUNC|OBE_ENABLE, // SIU_PCR189; This one should be EMIOS channel 10\r
+ PCR_RESET, // SIU_PCR190\r
+ PA_PRIMARY_FUNC|OBE_ENABLE, // SIU_PCR191; EMIOS channel 12\r
+ PCR_RESET, // SIU_PCR192\r
+ PCR_RESET, // SIU_PCR193\r
+ PCR_RESET, // SIU_PCR194\r
+ PCR_RESET, // SIU_PCR195\r
+ PCR_RESET, // SIU_PCR196\r
+ PCR_RESET, // SIU_PCR197\r
+ PCR_RESET, // SIU_PCR198\r
+ PCR_RESET, // SIU_PCR199\r
+ PCR_RESET, // SIU_PCR200\r
+ PCR_RESET, // SIU_PCR201\r
+ PCR_RESET, // SIU_PCR202\r
+ PCR_RESET, // SIU_PCR203\r
+ PCR_RESET, // SIU_PCR204\r
+ PCR_RESET, // SIU_PCR205\r
+ PCR_RESET, // SIU_PCR206\r
+ PCR_RESET, // SIU_PCR207\r
+ PCR_RESET, // SIU_PCR208\r
+ PCR_RESET, // SIU_PCR209\r
+ PCR_RESET, // SIU_PCR210\r
+ PCR_RESET, // SIU_PCR211\r
+ PCR_RESET, // SIU_PCR212\r
+ PCR_RESET, // SIU_PCR213\r
+ PCR_RESET, // SIU_PCR214\r
+ PCR_RESET, // SIU_PCR215\r
+ PCR_RESET, // SIU_PCR216\r
+ PCR_RESET, // SIU_PCR217\r
+ PCR_RESET, // SIU_PCR218\r
+ PCR_RESET, // SIU_PCR219\r
+ PCR_RESET, // SIU_PCR220\r
+ PCR_RESET, // SIU_PCR221\r
+ PCR_RESET, // SIU_PCR222\r
+ PCR_RESET, // SIU_PCR223\r
+ PCR_RESET, // SIU_PCR224\r
+ PCR_RESET, // SIU_PCR225\r
+ PCR_RESET, // SIU_PCR226\r
+ PCR_RESET, // SIU_PCR227\r
+ PCR_RESET, // SIU_PCR228\r
+ PCR_RESET, // SIU_PCR229\r
+ PCR_RESET, // SIU_PCR230\r
+ };\r
+\r
+const uint8_t PortOutConfigData[] = {\r
+ GPDO_RESET, // SIU_GPDO0\r
+ GPDO_RESET, // SIU_GPDO1\r
+ GPDO_RESET, // SIU_GPDO2\r
+ GPDO_RESET, // SIU_GPDO3\r
+ GPDO_RESET, // SIU_GPDO4\r
+ GPDO_RESET, // SIU_GPDO5\r
+ GPDO_RESET, // SIU_GPDO6\r
+ GPDO_RESET, // SIU_GPDO7\r
+ GPDO_RESET, // SIU_GPDO8\r
+ GPDO_RESET, // SIU_GPDO9\r
+ GPDO_RESET, // SIU_GPDO10\r
+ GPDO_RESET, // SIU_GPDO11\r
+ GPDO_RESET, // SIU_GPDO12\r
+ GPDO_RESET, // SIU_GPDO13\r
+ GPDO_RESET, // SIU_GPDO14\r
+ GPDO_RESET, // SIU_GPDO15\r
+ GPDO_RESET, // SIU_GPDO16\r
+ GPDO_RESET, // SIU_GPDO17\r
+ GPDO_RESET, // SIU_GPDO18\r
+ GPDO_RESET, // SIU_GPDO19\r
+ GPDO_RESET, // SIU_GPDO20\r
+ GPDO_RESET, // SIU_GPDO21\r
+ GPDO_RESET, // SIU_GPDO22\r
+ GPDO_RESET, // SIU_GPDO23\r
+ GPDO_RESET, // SIU_GPDO24\r
+ GPDO_RESET, // SIU_GPDO25\r
+ GPDO_RESET, // SIU_GPDO26\r
+ GPDO_RESET, // SIU_GPDO27\r
+ GPDO_RESET, // SIU_GPDO28\r
+ GPDO_RESET, // SIU_GPDO29\r
+ GPDO_RESET, // SIU_GPDO30\r
+ GPDO_RESET, // SIU_GPDO31\r
+ GPDO_RESET, // SIU_GPDO32\r
+ GPDO_RESET, // SIU_GPDO33\r
+ GPDO_RESET, // SIU_GPDO34\r
+ GPDO_RESET, // SIU_GPDO35\r
+ GPDO_RESET, // SIU_GPDO36\r
+ GPDO_RESET, // SIU_GPDO37\r
+ GPDO_RESET, // SIU_GPDO38\r
+ GPDO_RESET, // SIU_GPDO39\r
+ GPDO_RESET, // SIU_GPDO40\r
+ GPDO_RESET, // SIU_GPDO41\r
+ GPDO_RESET, // SIU_GPDO42\r
+ GPDO_RESET, // SIU_GPDO43\r
+ GPDO_RESET, // SIU_GPDO44\r
+ GPDO_RESET, // SIU_GPDO45\r
+ GPDO_RESET, // SIU_GPDO46\r
+ GPDO_RESET, // SIU_GPDO47\r
+ GPDO_RESET, // SIU_GPDO48\r
+ GPDO_RESET, // SIU_GPDO49\r
+ GPDO_RESET, // SIU_GPDO50\r
+ GPDO_RESET, // SIU_GPDO51\r
+ GPDO_RESET, // SIU_GPDO52\r
+ GPDO_RESET, // SIU_GPDO53\r
+ GPDO_RESET, // SIU_GPDO54\r
+ GPDO_RESET, // SIU_GPDO55\r
+ GPDO_RESET, // SIU_GPDO56\r
+ GPDO_RESET, // SIU_GPDO57\r
+ GPDO_RESET, // SIU_GPDO58\r
+ GPDO_RESET, // SIU_GPDO59\r
+ GPDO_RESET, // SIU_GPDO60\r
+ GPDO_RESET, // SIU_GPDO61\r
+ GPDO_RESET, // SIU_GPDO62\r
+ GPDO_RESET, // SIU_GPDO63\r
+ GPDO_RESET, // SIU_GPDO64\r
+ GPDO_RESET, // SIU_GPDO65\r
+ GPDO_RESET, // SIU_GPDO66\r
+ GPDO_RESET, // SIU_GPDO67\r
+ GPDO_RESET, // SIU_GPDO68\r
+ GPDO_RESET, // SIU_GPDO69\r
+ GPDO_RESET, // SIU_GPDO70\r
+ GPDO_RESET, // SIU_GPDO71\r
+ GPDO_RESET, // SIU_GPDO72\r
+ GPDO_RESET, // SIU_GPDO73\r
+ GPDO_RESET, // SIU_GPDO74\r
+ GPDO_RESET, // SIU_GPDO75\r
+ GPDO_RESET, // SIU_GPDO76\r
+ GPDO_RESET, // SIU_GPDO77\r
+ GPDO_RESET, // SIU_GPDO78\r
+ GPDO_RESET, // SIU_GPDO79\r
+ GPDO_RESET, // SIU_GPDO80\r
+ GPDO_RESET, // SIU_GPDO81\r
+ GPDO_RESET, // SIU_GPDO82\r
+ GPDO_RESET, // SIU_GPDO83\r
+ GPDO_RESET, // SIU_GPDO84\r
+ GPDO_RESET, // SIU_GPDO85\r
+ GPDO_RESET, // SIU_GPDO86\r
+ GPDO_RESET, // SIU_GPDO87\r
+ GPDO_RESET, // SIU_GPDO88\r
+ GPDO_RESET, // SIU_GPDO89\r
+ GPDO_RESET, // SIU_GPDO90\r
+ GPDO_RESET, // SIU_GPDO91\r
+ GPDO_RESET, // SIU_GPDO92\r
+ GPDO_RESET, // SIU_GPDO93\r
+ GPDO_RESET, // SIU_GPDO94\r
+ GPDO_RESET, // SIU_GPDO95\r
+ GPDO_RESET, // SIU_GPDO96\r
+ GPDO_RESET, // SIU_GPDO97\r
+ GPDO_RESET, // SIU_GPDO98\r
+ GPDO_RESET, // SIU_GPDO99\r
+ GPDO_RESET, // SIU_GPDO100\r
+ GPDO_RESET, // SIU_GPDO101\r
+ GPDO_RESET, // SIU_GPDO102\r
+ GPDO_RESET, // SIU_GPDO103\r
+ GPDO_RESET, // SIU_GPDO104\r
+ GPDO_RESET, // SIU_GPDO105\r
+ GPDO_RESET, // SIU_GPDO106\r
+ GPDO_RESET, // SIU_GPDO107\r
+ GPDO_RESET, // SIU_GPDO108\r
+ GPDO_RESET, // SIU_GPDO109\r
+ GPDO_RESET, // SIU_GPDO110\r
+ GPDO_RESET, // SIU_GPDO111\r
+ GPDO_RESET, // SIU_GPDO112\r
+ GPDO_RESET, // SIU_GPDO113\r
+ GPDO_RESET, // SIU_GPDO114\r
+ GPDO_RESET, // SIU_GPDO115\r
+ GPDO_RESET, // SIU_GPDO116\r
+ GPDO_RESET, // SIU_GPDO117\r
+ GPDO_RESET, // SIU_GPDO118\r
+ GPDO_RESET, // SIU_GPDO119\r
+ GPDO_RESET, // SIU_GPDO120\r
+ GPDO_RESET, // SIU_GPDO121\r
+ GPDO_RESET, // SIU_GPDO122\r
+ GPDO_RESET, // SIU_GPDO123\r
+ GPDO_RESET, // SIU_GPDO124\r
+ GPDO_RESET, // SIU_GPDO125\r
+ GPDO_RESET, // SIU_GPDO126\r
+ GPDO_RESET, // SIU_GPDO127\r
+ GPDO_RESET, // SIU_GPDO128\r
+ GPDO_RESET, // SIU_GPDO129\r
+ GPDO_RESET, // SIU_GPDO130\r
+ GPDO_RESET, // SIU_GPDO131\r
+ GPDO_RESET, // SIU_GPDO132\r
+ GPDO_RESET, // SIU_GPDO133\r
+ GPDO_RESET, // SIU_GPDO134\r
+ GPDO_RESET, // SIU_GPDO135\r
+ GPDO_RESET, // SIU_GPDO136\r
+ GPDO_RESET, // SIU_GPDO137\r
+ GPDO_RESET, // SIU_GPDO138\r
+ GPDO_RESET, // SIU_GPDO139\r
+ GPDO_RESET, // SIU_GPDO140\r
+ GPDO_RESET, // SIU_GPDO141\r
+ GPDO_RESET, // SIU_GPDO142\r
+ GPDO_RESET, // SIU_GPDO143\r
+ GPDO_RESET, // SIU_GPDO144\r
+ GPDO_RESET, // SIU_GPDO145\r
+ GPDO_RESET, // SIU_GPDO146\r
+ GPDO_RESET, // SIU_GPDO147\r
+ GPDO_RESET, // SIU_GPDO148\r
+ GPDO_RESET, // SIU_GPDO149\r
+ GPDO_RESET, // SIU_GPDO150\r
+ GPDO_RESET, // SIU_GPDO151\r
+ GPDO_RESET, // SIU_GPDO152\r
+ GPDO_RESET, // SIU_GPDO153\r
+ GPDO_RESET, // SIU_GPDO154\r
+ GPDO_RESET, // SIU_GPDO155\r
+ GPDO_RESET, // SIU_GPDO156\r
+ GPDO_RESET, // SIU_GPDO157\r
+ GPDO_RESET, // SIU_GPDO158\r
+ GPDO_RESET, // SIU_GPDO159\r
+ GPDO_RESET, // SIU_GPDO160\r
+ GPDO_RESET, // SIU_GPDO161\r
+ GPDO_RESET, // SIU_GPDO162\r
+ GPDO_RESET, // SIU_GPDO163\r
+ GPDO_RESET, // SIU_GPDO164\r
+ GPDO_RESET, // SIU_GPDO165\r
+ GPDO_RESET, // SIU_GPDO166\r
+ GPDO_RESET, // SIU_GPDO167\r
+ GPDO_RESET, // SIU_GPDO168\r
+ GPDO_RESET, // SIU_GPDO169\r
+ GPDO_RESET, // SIU_GPDO170\r
+ GPDO_RESET, // SIU_GPDO171\r
+ GPDO_RESET, // SIU_GPDO172\r
+ GPDO_RESET, // SIU_GPDO173\r
+ GPDO_RESET, // SIU_GPDO174\r
+ GPDO_RESET, // SIU_GPDO175\r
+ GPDO_RESET, // SIU_GPDO176\r
+ GPDO_RESET, // SIU_GPDO177\r
+ GPDO_RESET, // SIU_GPDO178\r
+ GPDO_RESET, // SIU_GPDO179\r
+ GPDO_RESET, // SIU_GPDO180\r
+ GPDO_RESET, // SIU_GPDO181\r
+ GPDO_RESET, // SIU_GPDO182\r
+ GPDO_RESET, // SIU_GPDO183\r
+ GPDO_RESET, // SIU_GPDO184\r
+ GPDO_RESET, // SIU_GPDO185\r
+ GPDO_RESET, // SIU_GPDO186\r
+ GPDO_RESET, // SIU_GPDO187\r
+ GPDO_RESET, // SIU_GPDO188\r
+ GPDO_RESET, // SIU_GPDO189\r
+ GPDO_RESET, // SIU_GPDO190\r
+ GPDO_RESET, // SIU_GPDO191\r
+ GPDO_RESET, // SIU_GPDO192\r
+ GPDO_RESET, // SIU_GPDO193\r
+ GPDO_RESET, // SIU_GPDO194\r
+ GPDO_RESET, // SIU_GPDO195\r
+ GPDO_RESET, // SIU_GPDO196\r
+ GPDO_RESET, // SIU_GPDO197\r
+ GPDO_RESET, // SIU_GPDO198\r
+ GPDO_RESET, // SIU_GPDO199\r
+ GPDO_RESET, // SIU_GPDO200\r
+ GPDO_RESET, // SIU_GPDO201\r
+ GPDO_RESET, // SIU_GPDO202\r
+ GPDO_RESET, // SIU_GPDO203\r
+ GPDO_RESET, // SIU_GPDO204\r
+ GPDO_RESET, // SIU_GPDO205\r
+ GPDO_RESET, // SIU_GPDO206\r
+ GPDO_RESET, // SIU_GPDO207\r
+ GPDO_RESET, // SIU_GPDO208\r
+ GPDO_RESET, // SIU_GPDO209\r
+ GPDO_RESET, // SIU_GPDO210\r
+ GPDO_RESET, // SIU_GPDO211\r
+ GPDO_RESET, // SIU_GPDO212\r
+ GPDO_RESET, // SIU_GPDO213\r
+};\r
+\r
+const Port_ConfigType PortConfigData =\r
+{\r
+ .padCnt = sizeof(PortPadConfigData),\r
+ .padConfig = PortPadConfigData,\r
+ .outCnt = sizeof(PortOutConfigData),\r
+ .outConfig = PortOutConfigData,\r
+};\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef PORT_CFG_H_\r
+#define PORT_CFG_H_\r
+\r
+#include "Std_Types.h"\r
+\r
+#define PORT_VERSION_INFO_API STD_ON\r
+#define PORT_DEV_ERROR_DETECT STD_ON\r
+#define PORT_PIN_DIRECTION_CHANGES_ALLOWED STD_ON\r
+\r
+typedef uint16 Port_PinType;\r
+\r
+#define BIT0 (1<<15)\r
+#define BIT1 (1<<14)\r
+#define BIT2 (1<<13)\r
+#define BIT3 (1<<12)\r
+#define BIT4 (1<<11)\r
+#define BIT5 (1<<10)\r
+#define BIT6 (1<<9)\r
+#define BIT7 (1<<8)\r
+#define BIT8 (1<<7)\r
+#define BIT9 (1<<6)\r
+#define BIT10 (1<<5)\r
+#define BIT11 (1<<4)\r
+#define BIT12 (1<<3)\r
+#define BIT13 (1<<2)\r
+#define BIT14 (1<<1)\r
+#define BIT15 (1<<0)\r
+\r
+#define WPS_BIT BIT15\r
+#define WPE_BIT BIT14\r
+#define SRC1_BIT BIT13\r
+#define SRC0_BIT BIT12\r
+#define HYS_BIT BIT11\r
+#define ODE_BIT BIT10\r
+#define DSC1_BIT BIT9\r
+#define DSC0_BIT BIT8\r
+#define IBE_BIT BIT7\r
+#define OBE_BIT BIT6\r
+#define PA2_BIT BIT5\r
+#define PA1_BIT BIT4\r
+#define PA0_BIT BIT3\r
+\r
+#define PULL_UP (WPE_BIT|WPS_BIT)\r
+#define PULL_DOWN (WPE_BIT)\r
+#define PULL_NONE (0)\r
+#define SLEW_RATE_MIN (0)\r
+#define SLEW_RATE_MED (SRC1_BIT)\r
+#define SLEW_RATE_MAX (SRC1_BIT|SRC0_BIT)\r
+#define HYS_ENABLE (HYS_BIT)\r
+#define ODE_ENABLE (ODE_BIT)\r
+#define IBE_ENABLE (IBE_BIT)\r
+#define OBE_ENABLE (OBE_BIT)\r
+\r
+#define PA_IO (0)\r
+#define PA_PRIMARY_FUNC (PA2_BIT)\r
+#define PA_ALTERNATE_FUNC1 (PA1_BIT)\r
+#define PA_PRIMARY_FUNC1 (PA1_BIT|PA2_BIT)\r
+#define PA_ALTERNATE_FUNC2 (PA0_BIT)\r
+\r
+#define PCR_IO_INPUT (IBE_ENABLE|PULL_DOWN)\r
+#define PCR_IO_OUTPUT (OBE_ENABLE)\r
+\r
+// Should be this out of reset\r
+#define PCR_RESET (0)\r
+#define PCR_BOOTCFG (PCR_IO_INPUT)\r
+#define GPDO_RESET (0)\r
+\r
+typedef struct\r
+{\r
+ uint16_t padCnt;\r
+ const uint16_t *padConfig;\r
+ uint16_t outCnt;\r
+ const uint8_t *outConfig;\r
+} Port_ConfigType;\r
+\r
+extern const Port_ConfigType PortConfigData;\r
+\r
+#endif /*PORT_CFG_H_*/\r
--- /dev/null
+
+# Our object files
+obj-y += pwm_sine_main.o
+obj-y += Tasks.o
+obj-y += Hooks.o
+obj-y += Rte.o
+
+# OS object files.
+obj-y += Os_Cfg.o
+# Board object files
+include $(ROOTDIR)/boards/board_common.mk
+
+ABSDIR := $(subst $(TOPDIR)/,,$(CURDIR))
+
+# The more precise configuration, the higher preceedance.
+VPATH := ../config/$(BOARDDIR) ../config $(VPATH)
+inc-y := ../config/$(BOARDDIR) ../config $(inc-y)
+
+
+
+inc-y += $(ROOTDIR)/system/kernel/$(objdir)
+inc-y += $(ROOTDIR)/system/kernel/include
+
+#TODO: Remove?, Build other way?
+VPATH += $(ROOTDIR)/$(SUBDIR)/Rte
+inc-y += $(ROOTDIR)/$(SUBDIR)/Rte
+VPATH += $(ROOTDIR)/components/pwm_sine
+inc-y += $(ROOTDIR)/components/pwm_sine
+
+
+# libs needed by us
+libitem-y += $(ROOTDIR)/libs/libkernel_$(ARCH_MCU).a
+
+#linkfile
+ldcmdfile-y = -T $(ROOTDIR)/$(ARCH_PATH-y)/scripts/linkscript_gcc.ldf
+
+# What I want to build
+build-exe-y = pwm_node.elf
+
+
+
+
+
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include "Os.h"
+#include <stdio.h>
+#include <assert.h>
+#define USE_TRACE 1
+#include "Trace.h"
+//#include "Hooks.h"
+
+
+#if 0
+#ifdef USE_STARTUPHOOK
+#ifdef CFG_MPC55XX
+#if !defined(USE_SIMULATOR)
+// Quick fix
+//#include "Kernel_Offset.h"
+#include "Mcu.h"
+
+extern uint8_t pcb_list[];
+
+#endif
+#endif
+#endif
+#endif
+
+
+
+/* Global hooks */
+ProtectionReturnType ProtectionHook( StatusType FatalError ) {
+ dbg_printf("## ProtectionHook\n");
+ return PRO_KILLAPPL;
+}
+
+void StartupHook( void ) {
+ dbg_printf("## StartupHook\n");
+
+ uint32_t sys_freq = McuE_GetSystemClock();
+
+ dbg_printf("Sys clock %d Hz\n",sys_freq);
+ Frt_Init();
+ Frt_Start(sys_freq/1000);
+
+}
+
+void ShutdownHook( StatusType Error ) {
+ dbg_printf("## ShutdownHook\n");
+ while(1);
+}
+
+void ErrorHook( StatusType Error ) {
+ DisableAllInterrupts();
+
+ dbg_printf("## ErrorHook err=%d\n",Error);
+ while(1);
+}
+
+void PreTaskHook( void ) {
+// dbg_printf("## PreTaskHook, taskid=%d\n",task);
+}
+
+void PostTaskHook( void ) {
+// dbg_printf("## PostTaskHook, taskid=%d\n",task);
+}
+
+#if 0
+struct os_conf_global_hooks_s os_conf_global_hooks = {
+ .StartupHook = StartupHook,
+ .ProtectionHook = ProtectionHook,
+ .ShutdownHook = ShutdownHook,
+ .ErrorHook = ErrorHook,
+ .PreTaskHook = PreTaskHook,
+ .PostTaskHook = PostTaskHook
+ };
+#endif
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+#include "Pwm.h"\r
+\r
+\r
+void RTE_set_led_pwm_level(Pwm_PeriodType arg){\r
+ Pwm_SetDutyCycle(PWM_CHANNEL_1, arg);\r
+}\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+\r
+#ifndef RTE_H_\r
+#define RTE_H_\r
+#include "RTE_fading_led.h"\r
+\r
+#endif /* RTE_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include "Os.h"\r
+\r
+#include "EcuM.h"\r
+#include <stdio.h>\r
+#include <assert.h>\r
+#include "Trace.h"\r
+#include "Com.h"\r
+#include "Adc.h"\r
+\r
+\r
+void OsIdle( void ) {\r
+ for(;;);\r
+}\r
+\r
+\r
+void ComTask( void ) {\r
+ // Run COM scheduled functions.\r
+ Com_MainFunctionTx();\r
+ Com_MainFunctionRx();\r
+\r
+ can_node_receive();\r
+}\r
+\r
+/*\r
+ * This is the startup task. It is activated once immediately after the OS i started.
+ */\r
+void StartupTask( void ) {\r
+\r
+ // Call second phase of startup sequence.\r
+ EcuM_StartupTwo();\r
+\r
+ // Make sure that the right PDU-groups are ready for communication.\r
+ Com_IpduGroupStart(RxGroup, 0);\r
+\r
+ // End of startup_task().\r
+// TerminateTask();\r
+}\r
+\r
+\r
--- /dev/null
+\r
+MOD_USE+=KERNEL MCU PORT COM CAN CANIF WINIDEA_TERM PWM\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include "CanIf.h"\r
+#include <stdlib.h>\r
+\r
+// Imported structs from Can_Lcfg.c\r
+extern const Can_ControllerConfigType CanControllerConfigData[];\r
+extern const Can_ConfigSetType CanConfigSetData;\r
+\r
+\r
+// Container that gets slamed into CanIf_InitController()\r
+// Inits ALL controllers\r
+// Multiplicity 1..*\r
+const CanIf_ControllerConfigType CanIfControllerConfig[] =\r
+{\r
+ { // This is the ConfigurationIndex in CanIf_InitController()\r
+ .WakeupSupport = CANIF_WAKEUP_SUPPORT_NO_WAKEUP,\r
+ .CanIfControllerIdRef = CAN_CTRL_A,\r
+ .CanIfDriverNameRef = "FLEXCAN", // Not used\r
+ .CanIfInitControllerRef = &CanControllerConfigData[0],\r
+ },\r
+ {\r
+ .WakeupSupport = CANIF_WAKEUP_SUPPORT_NO_WAKEUP,\r
+ .CanIfControllerIdRef = CAN_CTRL_C,\r
+ .CanIfDriverNameRef = "FLEXCAN", // Not used\r
+ .CanIfInitControllerRef = &CanControllerConfigData[1],\r
+ }\r
+};\r
+\r
+// Function callbacks for higher layers\r
+const CanIf_DispatchConfigType CanIfDispatchConfig =\r
+{\r
+ .CanIfBusOffNotification = NULL,\r
+ .CanIfWakeUpNotification = NULL, // Not used\r
+ .CanIfWakeupValidNotification = NULL, // Not used\r
+ .CanIfErrorNotificaton = NULL,\r
+};\r
+\r
+//-------------------------------------------------------------------\r
+const CanIf_HthConfigType CanIfHthConfigData[] =\r
+{\r
+ {\r
+ .CanIfHthType = CAN_ECORE_HANDLE_TYPE_BASIC,\r
+ .CanIfCanControllerIdRef = CAN_CTRL_A,\r
+ .CanIfHthIdSymRef = CAN_HTH_A_1, // Ref to the HTH\r
+ .CanIfEcoreEOL = 0,\r
+ },\r
+ {\r
+ .CanIfHthType = CAN_ECORE_HANDLE_TYPE_BASIC,\r
+ .CanIfCanControllerIdRef = CAN_CTRL_C,\r
+ .CanIfHthIdSymRef = CAN_HTH_C_1, // Ref to the HTH\r
+ .CanIfEcoreEOL = 1,\r
+ },\r
+};\r
+\r
+//-------------------------------------------------------------------\r
+const CanIf_HrhConfigType CanIfHrhConfigData[] =\r
+{\r
+ {\r
+ .CanIfHrhType = CAN_ECORE_HANDLE_TYPE_BASIC,\r
+ .CanIfSoftwareFilterHrh = TRUE, // Disable software filtering\r
+ .CanIfCanControllerHrhIdRef = CAN_CTRL_A,\r
+ .CanIfHrhIdSymRef = CAN_HRH_A_1, // Ref to the HRH\r
+ .CanIfEcoreEOL = 0,\r
+ },\r
+ {\r
+ .CanIfHrhType = CAN_ECORE_HANDLE_TYPE_BASIC,\r
+ .CanIfSoftwareFilterHrh = TRUE, // Disable software filtering\r
+ .CanIfCanControllerHrhIdRef = CAN_CTRL_C,\r
+ .CanIfHrhIdSymRef = CAN_HRH_C_1, // Ref to the HRH\r
+ .CanIfEcoreEOL = 1,\r
+ },\r
+};\r
+//-------------------------------------------------------------------\r
+\r
+/*\r
+ * TX PDUs\r
+ */\r
+const CanIf_TxPduConfigType CanIfTxPduConfigData[] =\r
+{\r
+};\r
+//-------------------------------------------------------------------\r
+\r
+/*\r
+ * RX PDUs\r
+ */\r
+const CanIf_RxPduConfigType CanIfRxPduConfigData[] =\r
+{\r
+ {\r
+ .CanIfCanRxPduId = LedCommandRx,\r
+ .CanIfCanRxPduCanId = 0x123, // CAN ID\r
+ .CanIfCanRxPduDlc = 2, //DLC\r
+#if ( CANIF_CANPDUID_READDATA_API == STD_ON )\r
+ .CanIfReadRxPduData = FALSE, // no buffering\r
+#endif\r
+#if ( CANIF_READRXPDU_NOTIF_STATUS_API == STD_ON )\r
+ .CanIfReadRxPduNotifyStatus = FALSE, // No indication\r
+#endif\r
+ .CanIfRxPduIdCanIdType = CANIF_CAN_ID_TYPE_29,\r
+ .CanIfRxUserType = CANIF_USER_TYPE_CAN_PDUR,\r
+ .CanIfUserRxIndication = PduR_CanIfRxIndication, // No indication\r
+ .CanIfCanRxPduHrhRef = &CanIfHrhConfigData[0], // Received on controller A\r
+ .PduIdRef = NULL, // Could be used by upper layers\r
+ .CanIfSoftwareFilterType = CANIF_SOFTFILTER_TYPE_MASK, // Not enabled in HRH\r
+ .CanIfCanRxPduCanIdMask = 0xFFF,\r
+ },\r
+};\r
+\r
+//-------------------------------------------------------------------\r
+const CanIf_InitHohConfigType CanIfHohConfigData[] =\r
+{\r
+ {\r
+ .CanConfigSet = &CanConfigSetData,\r
+ .CanIfHrhConfig = CanIfHrhConfigData,\r
+ .CanIfHthConfig = CanIfHthConfigData,\r
+ .CanIfEcoreEOL = 1,\r
+ },\r
+};\r
+\r
+// This container contains the init parameters of the CAN\r
+// Multiplicity 1..*\r
+const CanIf_InitConfigType CanIfInitConfig =\r
+{\r
+ .CanIfConfigSet = 0, // Not used\r
+ .CanIfNumberOfCanRxPduIds = sizeof(CanIfRxPduConfigData)/sizeof(CanIf_RxPduConfigType),\r
+ .CanIfNumberOfCanTXPduIds = sizeof(CanIfTxPduConfigData)/sizeof(CanIf_TxPduConfigType),\r
+ .CanIfNumberOfDynamicCanTXPduIds = 0, // Not used\r
+\r
+ // Containers\r
+ .CanIfHohConfigPtr = CanIfHohConfigData,\r
+ .CanIfRxPduConfigPtr = CanIfRxPduConfigData,\r
+ .CanIfTxPduConfigPtr = CanIfTxPduConfigData,\r
+};\r
+\r
+// This container includes all necessary configuration sub-containers\r
+// according the CAN Interface configuration structure.\r
+CanIf_ConfigType CanIf_Config =\r
+{\r
+ .ControllerConfig = CanIfControllerConfig,\r
+ .DispatchConfig = &CanIfDispatchConfig,\r
+ .InitConfig = &CanIfInitConfig,\r
+ .TransceiverConfig = NULL, // Not used\r
+};\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*
+* Module vendor: Autocore
+* Module version: 1.0.0
+* Specification: Autosar v3.0.1, Final
+*
+*/
+
+\r
+#ifndef COMGLOBALS_H_\r
+#define COMGLOBALS_H_\r
+\r
+// PDU handle id definitions.\r
+enum {\r
+ LedCommandRx = 0,\r
+};\r
+\r
+#endif
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*
+* Module vendor: Autocore
+* Module version: 1.0.0
+* Specification: Autosar v3.0.1, Final
+*
+*/
+
+\r
+#ifndef COM_CFG_H_\r
+#define COM_CFG_H_\r
+\r
+#define COM_MODULE_ID 20\r
+#define COM_INSTANCE_ID 1\r
+\r
+#define COM_DEV_ERROR_DETECT\r
+\r
+#define COM_MAX_NR_IPDU 5\r
+#define COM_MAX_NR_SIGNAL 6\r
+#define COM_MAX_NR_GROUPSIGNAL 10\r
+\r
+#define COM_MAX_NR_SIGNALS_PER_IPDU 4\r
+#define COM_MAX_NR_SIGNALGROUPS_PER_IPDU 4\r
+#define COM_MAX_NR_SIGNALS_PER_SIGNAL_GROUP 5\r
+\r
+#define COM_E_INVALID_FILTER_CONFIGURATION 101\r
+#define COM_E_INITIALIZATION_FAILED 102\r
+#define COM_E_INVALID_SIGNAL_CONFIGURATION 103\r
+#define COM_INVALID_PDU_ID 104\r
+#define COM_ERROR_SIGNAL_IS_SIGNALGROUP 105\r
+\r
+#define COM_E_TOO_MANY_IPDU 106\r
+#define COM_E_TOO_MANY_SIGNAL 107\r
+#define COM_E_TOO_MANY_GROUPSIGNAL 108\r
+\r
+#define CPU_ENDIANESS BIG_ENDIAN\r
+\r
+/*\r
+ * ComGeneral pre-compile time configuration parameters.\r
+ */\r
+#define ComConfigurationTimeBase NULL\r
+#define ComConfigurationUseDet \r
+#define ComVersionInfoApi\r
+\r
+#endif /*COM_CFG_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*
+* Module vendor: Autocore
+* Module version: 1.0.0
+* Specification: Autosar v3.0.1, Final
+*
+*/
+
+\r
+#include "Com_PbCfg.h"\r
+#include "stdlib.h"\r
+\r
+\r
+/*\r
+ * Group signal definitions\r
+ */\r
+ComGroupSignal_type ComGroupSignal[] = {\r
+ {\r
+ .ComEcoreEOL = 1\r
+ }\r
+};\r
+\r
+\r
+/*\r
+ * Signal definitions\r
+ */\r
+ComSignal_type ComSignal[] = {\r
+ {\r
+ .ComHandleId = SetLedLevelRx,\r
+ .ComFirstTimeoutFactor = 0,\r
+ .ComNotification = NULL,\r
+ .ComTimeoutFactor = 0,\r
+ .ComTimeoutNotification = NULL,\r
+ .ComTransferProperty = TRIGGERED,\r
+\r
+\r
+ .ComSignalInitValue = 0,\r
+ .ComBitPosition = 0,\r
+ .ComBitSize = 16,\r
+ .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalType = UINT16,
+ .ComEcoreIsSignalGroup = 0,\r
+\r
+ },\r
+ {\r
+ .ComEcoreEOL = 1\r
+ }\r
+};\r
+\r
+\r
+/*\r
+ * I-PDU group definitions\r
+ */\r
+ComIPduGroup_type ComIPduGroup[] = {\r
+ {\r
+ .ComIPduGroupHandleId = RxGroup\r
+ },\r
+\r
+ {\r
+ .ComEcoreEOL = 1\r
+ }\r
+};\r
+\r
+\r
+/*\r
+ * I-PDU definitions\r
+ */\r
+ComIPdu_type ComIPdu[] = {\r
+\r
+ {\r
+ .ComIPduRxHandleId = LedCommandRx,\r
+ .ComIPduCallout = NULL,\r
+ .ComIPduSignalProcessing = IMMEDIATE,\r
+ .ComIPduSize = 2,\r
+ .ComIPduDirection = RECEIVE,\r
+ .ComIPduGroupRef = RxGroup,\r
+\r
+ .ComIPduSignalRef = {\r
+\r
+ &ComSignal[ SetLedLevelRx ],\r
+\r
+ NULL,\r
+ },\r
+ },\r
+\r
+ {\r
+ .ComEcoreEOL = 1\r
+ }\r
+};\r
+\r
+const Com_ConfigType ComConfiguration = {\r
+ .ComConfigurationId = 1,\r
+ .ComIPdu = ComIPdu,\r
+ .ComIPduGroup = ComIPduGroup,\r
+ .ComSignal = ComSignal,\r
+ .ComGroupSignal = ComGroupSignal\r
+};\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*
+* Module vendor: Autocore
+* Module version: 1.0.0
+* Specification: Autosar v3.0.1, Final
+*
+*/
+
+#ifndef COM_PBCFG_H_\r
+#define COM_PBCFG_H_\r
+\r
+#include "Com_Types.h"\r
+\r
+extern const Com_ConfigType ComConfiguration;\r
+\r
+// PDU group definitions\r
+enum {\r
+ RxGroup = 0,\r
+};\r
+\r
+\r
+// Signal definitions\r
+enum {\r
+ SetLedLevelRx = 0,\r
+};\r
+\r
+\r
+#endif /* COM_PBCFG_H_ */
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*
+* Module vendor: Autocore
+* Module version: 1.0.0
+* Specification: Autosar v3.0.1, Final
+*
+*/
+
+\r
+// File generated on Tue Aug 18 13:49:03 CEST 2009\r
+\r
+#include <stdlib.h>\r
+#include <stdint.h>\r
+#include "os_config_macros.h"\r
+#include "Platform_Types.h"\r
+#include "Os.h" // includes Os_Cfg.h\r
+#include "Kernel.h"\r
+#include "Kernel_Offset.h"\r
+#include "alist_i.h"\r
+#include "Mcu.h"\r
+\r
+// ################################## DEBUG #################################\r
+// All output on as standard\r
+uint32 os_dbg_mask =\r
+ D_MASTER_PRINT ;\r
+// D_ISR_MASTER_PRINT |\r
+// D_STDOUT |\r
+// D_ISR_STDOUT | D_TASK | D_ALARM;\r
+\r
+// ############################### APPLICATION ##############################\r
+// A single, non-configurable application for now\r
+rom_app_t rom_app_list[] = {\r
+ {\r
+ .application_id = APPLICATION_ID_application_1,\r
+ .name = "application_1",\r
+ .trusted = true,\r
+ .StartupHook = NULL,\r
+ .ShutdownHook = NULL,\r
+ .ErrorHook = NULL,\r
+ .isr_mask = 0,\r
+ .scheduletable_mask = 0,\r
+ .alarm_mask = 0,\r
+ .counter_mask = 0,\r
+ .resource_mask = 0,\r
+ .message_mask = 0,\r
+ }\r
+};\r
+\r
+\r
+// ################################# COUNTERS ###############################\r
+counter_obj_t counter_list[] = {\r
+ {\r
+ .name = "OsTick",\r
+ .type = COUNTER_TYPE_HARD,\r
+ .unit = COUNTER_UNIT_NANO,\r
+ .alarm_base.maxallowedvalue = 65535,\r
+ .alarm_base.tickperbase = 1,\r
+ .alarm_base.mincycle = 0,\r
+ },\r
+};\r
+\r
+// ################################## ALARMS ################################\r
+alarm_obj_t alarm_list[] = {\r
+ {\r
+ .name = "ComAlarm",\r
+ .counter = &counter_list[COUNTER_ID_OsTick],\r
+ .counter_id = COUNTER_ID_OsTick,\r
+ .autostart = {\r
+ .active = TRUE,\r
+ .alarmtime = 5,\r
+ .cycletime = 20,\r
+ .appmode_mask = APPLICATION_ID_application_1, //___ARCTICSTUDIO_GENERATOR_TODO___,\r
+ },\r
+ .action = {\r
+ .type = ALARM_ACTION_ACTIVATETASK,\r
+ .task_id = TASK_ID_ComTask,\r
+ },\r
+ },\r
+};\r
+\r
+\r
+// ################################ RESOURCES ###############################\r
+resource_obj_t resource_list[] = {\r
+ {\r
+ .nr = RES_SCHEDULER,\r
+ .type = RESOURCE_TYPE_STANDARD,\r
+ .ceiling_priority = 0,\r
+ .application_owner_id = 0,\r
+ .task_mask = 0,\r
+ .owner = (-1),\r
+ },\r
+};\r
+\r
+// ############################## STACKS (TASKS) ############################\r
+uint8_t stack_ComTask[PRIO_STACK_SIZE];\r
+uint8_t stack_OsIdle[PRIO_STACK_SIZE];\r
+uint8_t stack_StartupTask[PRIO_STACK_SIZE];\r
+\r
+// ##################### TIMING PROTECTIONS (TASKS, ISRS) ###################\r
+timing_protection_t timing_protection_list[] = {\r
+};\r
+\r
+rom_pcb_t rom_pcb_list[] = {\r
+// ################################## TASKS #################################\r
+ {\r
+ .pid = TASK_ID_ComTask,\r
+ .name = "ComTask",\r
+ .entry = ComTask,\r
+ .prio = 10,\r
+ .proc_type = PROC_BASIC,\r
+ .stack.size = sizeof stack_ComTask,\r
+ .stack.top = stack_ComTask,\r
+ .autostart = false,\r
+ .application_id = APPLICATION_ID_application_1,\r
+ },\r
+ {\r
+ .pid = TASK_ID_OsIdle,\r
+ .name = "OsIdle",\r
+ .entry = OsIdle,\r
+ .prio = 1,\r
+ .proc_type = PROC_EXTENDED,\r
+ .stack.size = sizeof stack_OsIdle,\r
+ .stack.top = stack_OsIdle,\r
+ .autostart = true,\r
+ .application_id = APPLICATION_ID_application_1,\r
+ },
+ {\r
+ .pid = TASK_ID_StartupTask,\r
+ .name = "StartupTask",\r
+ .entry = StartupTask,\r
+ .prio = 100,\r
+ .proc_type = PROC_BASIC,\r
+ .stack.size = sizeof stack_StartupTask,\r
+ .stack.top = stack_StartupTask,\r
+ .autostart = true,\r
+ .application_id = APPLICATION_ID_application_1,\r
+ },\r
+};\r
+\r
+uint8_t pcb_list[PCB_T_SIZE*ARRAY_SIZE(rom_pcb_list)];\r
+\r
+uint8_t os_interrupt_stack[OS_INTERRUPT_STACK_SIZE] __attribute__ ((aligned (0x10)));\r
+\r
+// The vector table\r
+void * intc_vector_tbl[NUMBER_OF_INTERRUPTS_AND_EXCEPTIONS] __attribute__ ((aligned (0x1000),section(".data")))= {\r
+};\r
+\r
+// The type of vector\r
+uint8 intc_type_tbl[NUMBER_OF_INTERRUPTS_AND_EXCEPTIONS] = {\r
+};\r
+\r
+\r
+// ################################## HOOKS ##################################\r
+struct os_conf_global_hooks_s os_conf_global_hooks = {\r
+ .StartupHook = StartupHook,\r
+ .ProtectionHook = ProtectionHook,\r
+ .ShutdownHook = ShutdownHook,\r
+ .ErrorHook = ErrorHook,\r
+ .PreTaskHook = PreTaskHook,\r
+ .PostTaskHook = PostTaskHook,\r
+};\r
+\r
+#include "os_config_funcs.h"
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*
+* Module vendor: Autocore
+* Module version: 1.0.0
+* Specification: Autosar v3.0.1, Final
+*
+*/
+
+\r
+#ifndef OS_CFG_H_\r
+#define OS_CFG_H_\r
+\r
+#define ALARM_USE\r
+
+// Application\r
+#define APPLICATION_ID_application_1 0\r
+#define APPLICATION_CNT 1\r
+\r
+// Alarm Id's\r
+#define ALARM_ID_ComAlarm 0
+\r
+// Counter Id's\r
+#define COUNTER_ID_OsTick 0\r
+\r
+// Event Id's\r
+\r
+// Event masks\r
+\r
+// Isr Id's\r
+\r
+// Resource Id's\r
+\r
+// Task Id's\r
+#define TASK_ID_ComTask 0\r
+#define TASK_ID_OsIdle 1
+#define TASK_ID_StartupTask 2\r
+\r
+// Task entry points\r
+void ComTask( void );\r
+void OsIdle( void );\r
+void StartupTask( void );\r
+\r
+// Stack sizes\r
+#define PRIO_STACK_SIZE 2048\r
+#define OS_INTERRUPT_STACK_SIZE 2048\r
+\r
+// Hooks\r
+#define USE_ERRORHOOK\r
+#define USE_POSTTASKHOOK\r
+#define USE_PRETASKHOOK\r
+#define USE_PROTECTIONHOOK\r
+#define USE_SHUTDOWNHOOK\r
+#define USE_STARTUPHOOK\r
+\r
+#endif /*OS_CFG_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*
+* Module vendor: Autocore
+* Module version: 1.0.0
+* Specification: Autosar v3.0.1, Final
+*
+*/
+
+\r
+// File generated on Mon Aug 17 14:11:26 CEST 2009\r
+// File generated by org.autocore.modules.port.mpc5516\r
+\r
+#include "Port_Cfg.h"\r
+\r
+const uint16_t PortPadConfigData[] = {\r
+ PCR_RESET, /* PCR 0 */\r
+ PCR_RESET, /* PCR 1 */\r
+ PCR_RESET, /* PCR 2 */\r
+ PCR_RESET, /* PCR 3 */\r
+ PCR_RESET, /* PCR 4 */\r
+ PCR_RESET, /* PCR 5 */\r
+ PCR_RESET, /* PCR 6 */\r
+ PCR_RESET, /* PCR 7 */\r
+ PCR_RESET, /* PCR 8 */\r
+ PCR_RESET, /* PCR 9 */\r
+ PCR_RESET, /* PCR 10 */
+ PCR_RESET,
+ PCR_RESET,\r
+ PCR_RESET, /* PCR 13 */\r
+ PCR_RESET, /* PCR 14 */\r
+ PCR_RESET, /* PCR 15 */\r
+ PCR_RESET, /* PCR 16 */\r
+ PCR_RESET, /* PCR 17 */\r
+ PCR_RESET, /* PCR 18 */\r
+ PCR_RESET, /* PCR 19 */\r
+ PCR_RESET, /* PCR 20 */\r
+ PCR_RESET, /* PCR 21 */\r
+ PCR_RESET, /* PCR 22 */\r
+ PCR_RESET, /* PCR 23 */\r
+ PCR_RESET, /* PCR 24 */\r
+ PCR_RESET, /* PCR 25 */\r
+ PCR_RESET, /* PCR 26 */\r
+ PCR_RESET, /* PCR 27 */\r
+ PCR_RESET, /* PCR 28 */\r
+ PCR_RESET, /* PCR 29 */\r
+ PCR_RESET, /* PCR 30 */\r
+ PCR_RESET, /* PCR 31 */\r
+ PCR_RESET, /* PCR 32 */\r
+ PCR_RESET, /* PCR 33 */\r
+ PCR_RESET, /* PCR 34 */\r
+ PCR_RESET, /* PCR 35 */\r
+ PCR_RESET, /* PCR 36 */\r
+ PCR_RESET, /* PCR 37 */\r
+ PCR_RESET, /* PCR 38 */\r
+ PCR_RESET, /* PCR 39 */\r
+ PCR_RESET, /* PCR 40 */\r
+ PCR_RESET, /* PCR 41 */\r
+ PCR_RESET, /* PCR 42 */\r
+ PCR_RESET, /* PCR 43 */\r
+ PCR_RESET, /* PCR 44 */\r
+ PCR_RESET, /* PCR 45 */\r
+ PCR_RESET, /* PCR 46 */\r
+ PCR_RESET, /* PCR 47 */\r
+ ( PA_FUNC1 | OBE_ENABLE | SLEW_RATE_MIN | PULL_NONE ), /* PCR 48 : CNTX_A */\r
+ ( PA_FUNC1 | IBE_ENABLE | SLEW_RATE_MIN | PULL_NONE ), /* PCR 49 : CNRX_A */\r
+ PCR_RESET, /* PCR 50 */\r
+ PCR_RESET, /* PCR 51 */\r
+ ( PA_FUNC2 | OBE_ENABLE | SLEW_RATE_MIN | PULL_NONE ), /* PCR 52 : PD[4] */\r
+ PCR_RESET, /* PCR 53 */\r
+ PCR_RESET, /* PCR 54 */\r
+ PCR_RESET, /* PCR 55 */\r
+ PCR_RESET, /* PCR 56 */\r
+ PCR_RESET, /* PCR 57 */\r
+ PCR_RESET, /* PCR 58 */\r
+ PCR_RESET, /* PCR 59 */\r
+ PCR_RESET, /* PCR 60 */\r
+ PCR_RESET, /* PCR 61 */\r
+ PCR_RESET, /* PCR 62 */\r
+ PCR_RESET, /* PCR 63 */\r
+ PCR_RESET, /* PCR 64 */\r
+ PCR_RESET, /* PCR 65 */\r
+ PCR_RESET, /* PCR 66 */\r
+ PCR_RESET, /* PCR 67 */\r
+ PCR_RESET, /* PCR 68 */\r
+ PCR_RESET, /* PCR 69 */\r
+ PCR_RESET, /* PCR 70 */\r
+ PCR_RESET, /* PCR 71 */\r
+ PCR_RESET, /* PCR 72 */\r
+ PCR_RESET, /* PCR 73 */\r
+ PCR_RESET, /* PCR 74 */\r
+ PCR_RESET, /* PCR 75 */\r
+ PCR_RESET, /* PCR 76 */\r
+ PCR_RESET, /* PCR 77 */\r
+ PCR_RESET, /* PCR 78 */\r
+ PCR_RESET, /* PCR 79 */\r
+ PCR_RESET, /* PCR 80 */\r
+ PCR_RESET, /* PCR 81 */\r
+ PCR_RESET, /* PCR 82 */\r
+ PCR_RESET, /* PCR 83 */\r
+ PCR_RESET, /* PCR 84 */\r
+ PCR_RESET, /* PCR 85 */\r
+ PCR_RESET, /* PCR 86 */\r
+ PCR_RESET, /* PCR 87 */\r
+ PCR_RESET, /* PCR 88 */\r
+ PCR_RESET, /* PCR 89 */\r
+ PCR_RESET, /* PCR 90 */\r
+ PCR_RESET, /* PCR 91 */\r
+ PCR_RESET, /* PCR 92 */\r
+ PCR_RESET, /* PCR 93 */\r
+ PCR_RESET, /* PCR 94 */\r
+ PCR_RESET, /* PCR 95 */\r
+ PCR_RESET, /* PCR 96 */\r
+ PCR_RESET, /* PCR 97 */\r
+ PCR_RESET, /* PCR 98 */\r
+ PCR_RESET, /* PCR 99 */\r
+ PCR_RESET, /* PCR 100 */\r
+ PCR_RESET, /* PCR 101 */\r
+ PCR_RESET, /* PCR 102 */\r
+ PCR_RESET, /* PCR 103 */\r
+ PCR_RESET, /* PCR 104 */\r
+ PCR_RESET, /* PCR 105 */\r
+ PCR_RESET, /* PCR 106 */\r
+ PCR_RESET, /* PCR 107 */\r
+ PCR_RESET, /* PCR 108 */\r
+ PCR_RESET, /* PCR 109 */\r
+ PCR_RESET, /* PCR 110 */\r
+ PCR_RESET, /* PCR 111 */\r
+ PCR_RESET, /* PCR 112 */\r
+ PCR_RESET, /* PCR 113 */\r
+ PCR_RESET, /* PCR 114 */\r
+ PCR_RESET, /* PCR 115 */\r
+ PCR_RESET, /* PCR 116 */\r
+ PCR_RESET, /* PCR 117 */\r
+ PCR_RESET, /* PCR 118 */\r
+ PCR_RESET, /* PCR 119 */\r
+ PCR_RESET, /* PCR 120 */\r
+ PCR_RESET, /* PCR 121 */\r
+ PCR_RESET, /* PCR 122 */\r
+ PCR_RESET, /* PCR 123 */\r
+ PCR_RESET, /* PCR 124 */\r
+ PCR_RESET, /* PCR 125 */\r
+ PCR_RESET, /* PCR 126 */\r
+ PCR_RESET, /* PCR 127 */\r
+ PCR_RESET, /* PCR 128 */\r
+ PCR_RESET, /* PCR 129 */\r
+ PCR_RESET, /* PCR 130 */\r
+ PCR_RESET, /* PCR 131 */\r
+ PCR_RESET, /* PCR 132 */\r
+ PCR_RESET, /* PCR 133 */\r
+ PCR_RESET, /* PCR 134 */\r
+ PCR_RESET, /* PCR 135 */\r
+ PCR_RESET, /* PCR 136 */\r
+ PCR_RESET, /* PCR 137 */\r
+ PCR_RESET, /* PCR 138 */\r
+ PCR_RESET, /* PCR 139 */\r
+ PCR_RESET, /* PCR 140 */\r
+ PCR_RESET, /* PCR 141 */\r
+ PCR_RESET, /* PCR 142 */\r
+ PCR_RESET, /* PCR 143 */\r
+ PCR_RESET, /* PCR 144 */\r
+};\r
+\r
+const uint8_t PortOutConfigData[] = {\r
+ GPDO_RESET, /* GPDO 0 */\r
+ GPDO_RESET, /* GPDO 1 */\r
+ GPDO_RESET, /* GPDO 2 */\r
+ GPDO_RESET, /* GPDO 3 */\r
+ GPDO_RESET, /* GPDO 4 */\r
+ GPDO_RESET, /* GPDO 5 */\r
+ GPDO_RESET, /* GPDO 6 */\r
+ GPDO_RESET, /* GPDO 7 */\r
+ GPDO_RESET, /* GPDO 8 */\r
+ GPDO_RESET, /* GPDO 9 */\r
+ GPDO_RESET, /* GPDO 10 */\r
+ GPDO_RESET, /* GPDO 11 */\r
+ GPDO_RESET, /* GPDO 12 */\r
+ GPDO_RESET, /* GPDO 13 */\r
+ GPDO_RESET, /* GPDO 14 */\r
+ GPDO_RESET, /* GPDO 15 */\r
+ GPDO_RESET, /* GPDO 16 */\r
+ GPDO_RESET, /* GPDO 17 */\r
+ GPDO_RESET, /* GPDO 18 */\r
+ GPDO_RESET, /* GPDO 19 */\r
+ GPDO_RESET, /* GPDO 20 */\r
+ GPDO_RESET, /* GPDO 21 */\r
+ GPDO_RESET, /* GPDO 22 */\r
+ GPDO_RESET, /* GPDO 23 */\r
+ GPDO_RESET, /* GPDO 24 */\r
+ GPDO_RESET, /* GPDO 25 */\r
+ GPDO_RESET, /* GPDO 26 */\r
+ GPDO_RESET, /* GPDO 27 */\r
+ GPDO_RESET, /* GPDO 28 */\r
+ GPDO_RESET, /* GPDO 29 */\r
+ GPDO_RESET, /* GPDO 30 */\r
+ GPDO_RESET, /* GPDO 31 */\r
+ GPDO_RESET, /* GPDO 32 */\r
+ GPDO_RESET, /* GPDO 33 */\r
+ GPDO_RESET, /* GPDO 34 */\r
+ GPDO_RESET, /* GPDO 35 */\r
+ GPDO_RESET, /* GPDO 36 */\r
+ GPDO_RESET, /* GPDO 37 */\r
+ GPDO_RESET, /* GPDO 38 */\r
+ GPDO_RESET, /* GPDO 39 */\r
+ GPDO_RESET, /* GPDO 40 */\r
+ GPDO_RESET, /* GPDO 41 */\r
+ GPDO_RESET, /* GPDO 42 */\r
+ GPDO_RESET, /* GPDO 43 */\r
+ GPDO_RESET, /* GPDO 44 */\r
+ GPDO_RESET, /* GPDO 45 */\r
+ GPDO_RESET, /* GPDO 46 */\r
+ GPDO_RESET, /* GPDO 47 */\r
+ GPDO_RESET, /* GPDO 48 */\r
+ GPDO_HIGH, /* GPDO 49 */\r
+ GPDO_RESET, /* GPDO 50 */\r
+ GPDO_RESET, /* GPDO 51 */\r
+ GPDO_RESET, /* GPDO 52 */\r
+ GPDO_RESET, /* GPDO 53 */\r
+ GPDO_RESET, /* GPDO 54 */\r
+ GPDO_RESET, /* GPDO 55 */\r
+ GPDO_RESET, /* GPDO 56 */\r
+ GPDO_RESET, /* GPDO 57 */\r
+ GPDO_RESET, /* GPDO 58 */\r
+ GPDO_RESET, /* GPDO 59 */\r
+ GPDO_RESET, /* GPDO 60 */\r
+ GPDO_RESET, /* GPDO 61 */\r
+ GPDO_RESET, /* GPDO 62 */\r
+ GPDO_RESET, /* GPDO 63 */\r
+ GPDO_RESET, /* GPDO 64 */\r
+ GPDO_RESET, /* GPDO 65 */\r
+ GPDO_RESET, /* GPDO 66 */\r
+ GPDO_RESET, /* GPDO 67 */\r
+ GPDO_RESET, /* GPDO 68 */\r
+ GPDO_RESET, /* GPDO 69 */\r
+ GPDO_RESET, /* GPDO 70 */\r
+ GPDO_RESET, /* GPDO 71 */\r
+ GPDO_RESET, /* GPDO 72 */\r
+ GPDO_RESET, /* GPDO 73 */\r
+ GPDO_RESET, /* GPDO 74 */\r
+ GPDO_RESET, /* GPDO 75 */\r
+ GPDO_RESET, /* GPDO 76 */\r
+ GPDO_RESET, /* GPDO 77 */\r
+ GPDO_RESET, /* GPDO 78 */\r
+ GPDO_RESET, /* GPDO 79 */\r
+ GPDO_RESET, /* GPDO 80 */\r
+ GPDO_RESET, /* GPDO 81 */\r
+ GPDO_RESET, /* GPDO 82 */\r
+ GPDO_RESET, /* GPDO 83 */\r
+ GPDO_RESET, /* GPDO 84 */\r
+ GPDO_RESET, /* GPDO 85 */\r
+ GPDO_RESET, /* GPDO 86 */\r
+ GPDO_RESET, /* GPDO 87 */\r
+ GPDO_RESET, /* GPDO 88 */\r
+ GPDO_RESET, /* GPDO 89 */\r
+ GPDO_RESET, /* GPDO 90 */\r
+ GPDO_RESET, /* GPDO 91 */\r
+ GPDO_RESET, /* GPDO 92 */\r
+ GPDO_RESET, /* GPDO 93 */\r
+ GPDO_RESET, /* GPDO 94 */\r
+ GPDO_RESET, /* GPDO 95 */\r
+ GPDO_RESET, /* GPDO 96 */\r
+ GPDO_RESET, /* GPDO 97 */\r
+ GPDO_RESET, /* GPDO 98 */\r
+ GPDO_RESET, /* GPDO 99 */\r
+ GPDO_RESET, /* GPDO 100 */\r
+ GPDO_RESET, /* GPDO 101 */\r
+ GPDO_RESET, /* GPDO 102 */\r
+ GPDO_RESET, /* GPDO 103 */\r
+ GPDO_RESET, /* GPDO 104 */\r
+ GPDO_RESET, /* GPDO 105 */\r
+ GPDO_RESET, /* GPDO 106 */\r
+ GPDO_RESET, /* GPDO 107 */\r
+ GPDO_RESET, /* GPDO 108 */\r
+ GPDO_RESET, /* GPDO 109 */\r
+ GPDO_RESET, /* GPDO 110 */\r
+ GPDO_RESET, /* GPDO 111 */\r
+ GPDO_RESET, /* GPDO 112 */\r
+ GPDO_RESET, /* GPDO 113 */\r
+ GPDO_RESET, /* GPDO 114 */\r
+ GPDO_RESET, /* GPDO 115 */\r
+ GPDO_RESET, /* GPDO 116 */\r
+ GPDO_RESET, /* GPDO 117 */\r
+ GPDO_RESET, /* GPDO 118 */\r
+ GPDO_RESET, /* GPDO 119 */\r
+ GPDO_RESET, /* GPDO 120 */\r
+ GPDO_RESET, /* GPDO 121 */\r
+ GPDO_RESET, /* GPDO 122 */\r
+ GPDO_RESET, /* GPDO 123 */\r
+ GPDO_RESET, /* GPDO 124 */\r
+ GPDO_RESET, /* GPDO 125 */\r
+ GPDO_RESET, /* GPDO 126 */\r
+ GPDO_RESET, /* GPDO 127 */\r
+ GPDO_RESET, /* GPDO 128 */\r
+ GPDO_RESET, /* GPDO 129 */\r
+ GPDO_RESET, /* GPDO 130 */\r
+ GPDO_RESET, /* GPDO 131 */\r
+ GPDO_RESET, /* GPDO 132 */\r
+ GPDO_RESET, /* GPDO 133 */\r
+ GPDO_RESET, /* GPDO 134 */\r
+ GPDO_RESET, /* GPDO 135 */\r
+ GPDO_RESET, /* GPDO 136 */\r
+ GPDO_RESET, /* GPDO 137 */\r
+ GPDO_RESET, /* GPDO 138 */\r
+ GPDO_RESET, /* GPDO 139 */\r
+ GPDO_RESET, /* GPDO 140 */\r
+ GPDO_RESET, /* GPDO 141 */\r
+ GPDO_RESET, /* GPDO 142 */\r
+};\r
+\r
+const Port_ConfigType PortConfigData =\r
+{\r
+ .padCnt = sizeof(PortPadConfigData),\r
+ .padConfig = PortPadConfigData,\r
+ .outCnt = sizeof(PortOutConfigData),\r
+ .outConfig = PortOutConfigData,\r
+};
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*
+* Module vendor: Autocore
+* Module version: 1.0.0
+* Specification: Autosar v3.0.1, Final
+*
+*/
+
+// File generated on Mon Aug 17 14:11:22 CEST 2009\r
+// File generated by org.autocore.modules.port.mpc5516\r
+\r
+#ifndef PORT_CFG_H_\r
+#define PORT_CFG_H_\r
+\r
+#include "Std_Types.h"\r
+\r
+#define PORT_VERSION_INFO_API STD_ON\r
+#define PORT_DEV_ERROR_DETECT STD_ON\r
+#define PORT_PIN_DIRECTION_CHANGES_ALLOWED STD_ON\r
+\r
+#define BIT0 (1<<15)\r
+#define BIT1 (1<<14)\r
+#define BIT2 (1<<13)\r
+#define BIT3 (1<<12)\r
+#define BIT4 (1<<11)\r
+#define BIT5 (1<<10)\r
+#define BIT6 (1<<9)\r
+#define BIT7 (1<<8)\r
+#define BIT8 (1<<7)\r
+#define BIT9 (1<<6)\r
+#define BIT10 (1<<5)\r
+#define BIT11 (1<<4)\r
+#define BIT12 (1<<3)\r
+#define BIT13 (1<<2)\r
+#define BIT14 (1<<1)\r
+#define BIT15 (1<<0)\r
+\r
+#define WPE_BIT BIT14\r
+#define WPS_BIT BIT15\r
+#define SRC0 BIT12\r
+#define SRC1 BIT13\r
+\r
+#define PULL_UP (WPE_BIT|WPS_BIT)\r
+#define PULL_DOWN (WPE_BIT)\r
+#define PULL_NONE 0\r
+#define SLEW_RATE_MIN 0\r
+#define SLEW_RATE_MED BIT13\r
+#define SLEW_RATE_MAX (BIT12|BIT13)\r
+#define HYS_ENABLE BIT11\r
+#define ODE_ENABLE BIT10\r
+#define IBE_ENABLE BIT7\r
+#define OBE_ENABLE BIT6\r
+#define PA_IO (0)\r
+#define PA_FUNC0 (0)\r
+#define PA_FUNC1 (BIT5)\r
+#define PA_FUNC2 (BIT4)\r
+#define PA_FUNC3 (BIT4|BIT5)\r
+#define PA_FUNC4 (BIT3)\r
+\r
+#define PCR_RESET (0)\r
+#define GPDO_RESET (0)\r
+\r
+#define GPDO_HIGH (1)\r
+\r
+// Could also use an enum to name the pins here\r
+typedef int Port_PinType;\r
+\r
+typedef struct\r
+{\r
+ uint16_t padCnt;\r
+ const uint16_t *padConfig;\r
+ uint16_t outCnt;\r
+ const uint8_t *outConfig;\r
+// uint16_t inCnt;\r
+// const uint8_t *inConfig;\r
+} Port_ConfigType;\r
+\r
+extern const Port_ConfigType PortConfigData;\r
+\r
+#endif /*PORT_CFG_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*\r
+ * Pwm_Cfg.c\r
+ *\r
+ * Created on: 2009-jul-09\r
+ * Author: nian\r
+ */\r
+\r
+#include "Pwm.h"\r
+#include "Pwm_Cfg.h"\r
+\r
+extern void MyPwmNotificationRoutine(void);\r
+\r
+const Pwm_ConfigType PwmConfig = {\r
+ .Channels = {\r
+ PWM_CHANNEL_CONFIG(PWM_CHANNEL_1, 3000, 0x6000, PWM_CHANNEL_PRESCALER_4, PWM_HIGH),\r
+ },\r
+#if PWM_NOTIFICATION_SUPPORTED==ON\r
+ .NotificationHandlers = {\r
+ NULL, // PWM_CHANNEL_1\r
+ }\r
+#endif\r
+};\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*\r
+ * Pwm_Cfg.h\r
+ *\r
+ * Created on: 2009-jul-09\r
+ * Author: nian\r
+ */\r
+\r
+#ifndef PWM_CFG_H_\r
+#define PWM_CFG_H_\r
+\r
+/****************************************************************************\r
+ * Global configuration options and defines\r
+ */\r
+\r
+#define ON 1\r
+#define OFF 0\r
+\r
+/*\r
+ * PWM003: The detection of development errors is configurable (ON/OFF) at\r
+ * pre-compile time. The switch PwmDevErorDetect shall activate or disable\r
+ * the detection of all development errors\r
+ */\r
+#define PWM_DEV_EROR_DETECT ON\r
+#define PWM_GET_OUTPUT_STATE ON\r
+#define PWM_STATICALLY_CONFIGURED OFF\r
+#define PWM_NOTIFICATION_SUPPORTED ON\r
+\r
+#define PWM_SET_PERIOD_AND_DUTY ON\r
+\r
+/*\r
+ * PWM132: Switch for enabling the update of duty cycle parameter at the end\r
+ * of the current period.\r
+ *\r
+ * Note: Currently only ON mode is supported.\r
+ */\r
+#define PWM_DUTYCYCLE_UPDATED_ENDPERIOD ON\r
+\r
+/****************************************************************************\r
+ * Not defined in AUTOSAR.\r
+ */\r
+#define PWM_ISR_PRIORITY 1\r
+#define PWM_PRESCALER 64\r
+/*\r
+ * Setting to ON freezes the current output state of a PWM channel when in\r
+ * debug mode.\r
+ */\r
+#define PWM_FREEZE_ENABLE ON\r
+\r
+/****************************************************************************\r
+ * Enumeration of channels\r
+ * Maps a symbolic name to a hardware channel\r
+ */\r
+typedef enum {\r
+#if defined(CFG_BRD_MPC5516IT)\r
+ PWM_CHANNEL_1 = 12,\r
+\r
+#elif defined(CFG_BRD_MPC5567QRTECH)\r
+ PWM_CHANNEL_1 = 10, /* Emios channel 10 maps to PCR189 which\r
+ * is available on pin 54 of the\r
+ * ERNI 154822 connector\r
+ */\r
+ PWM_CHANNEL_2 = 12, /* Channel 12 goes to PCR191, also\r
+ * available on the ERNI 154822 connector\r
+ */\r
+#else\r
+#warning "Unknown board or CFG_BRD_* undefined"\r
+#endif\r
+ PWM_NUMBER_OF_CHANNELS = 1,\r
+} Pwm_NamedChannelsType;\r
+\r
+#endif /* PWM_CFG_H_ */\r
--- /dev/null
+
+# Our object files
+obj-y += pwm_node2_helpers.o
+obj-y += fading_led.o
+obj-y += Rte.o
+obj-y += Tasks.o
+obj-y += Hooks.o
+
+inc-y += $(ROOTDIR)/system/kernel/$(objdir)
+inc-y += $(ROOTDIR)/system/kernel/include
+
+# OS object files.
+obj-y += Os_Cfg.o
+# Board object files
+include $(ROOTDIR)/boards/board_common.mk
+
+ABSDIR := $(subst $(TOPDIR)/,,$(CURDIR))
+
+# The more precise configuration, the higher preceedance.
+VPATH := ../config/$(BOARDDIR) ../config $(VPATH)
+inc-y := ../config/$(BOARDDIR) ../config $(inc-y)
+
+inc-y += $(ROOTDIR)/system/kernel/$(objdir)
+
+#TODO: Remove?, Build other way?
+VPATH += $(ROOTDIR)/$(SUBDIR)/Rte
+inc-y += $(ROOTDIR)/$(SUBDIR)/Rte
+VPATH += $(ROOTDIR)/components/fading_led
+inc-y += $(ROOTDIR)/components/fading_led
+
+
+# libs needed by us
+libitem-y += $(ROOTDIR)/libs/libkernel_$(ARCH_MCU).a
+
+#linkfile
+ldcmdfile-y = -T $(ROOTDIR)/$(ARCH_PATH-y)/scripts/linkscript_gcc.ldf
+
+# What I want to build
+build-exe-y = pwm_node2.elf
+
+
+
+
+
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+#include "Adc.h"\r
+#include "Com.h"\r
+#include "Trace.h"\r
+#include "RTE_fading_led.h"\r
+\r
+\r
+uint16 rx_data = 0;\r
+\r
+void can_node_receive(void) {\r
+ Com_ReceiveSignal(SetLedLevelRx, &rx_data);\r
+ fading_led_set_level(rx_data);\r
+}\r
--- /dev/null
+\r
+MOD_USE+=KERNEL MCU T32_TERM\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*\r
+ * Os_Cfg.c\r
+ *\r
+ * Created on: 15 jul 2009\r
+ * Author: mahi\r
+ */\r
+\r
+#include <stdlib.h>\r
+#include <stdint.h>\r
+#include "os_config_macros.h"\r
+#include "Platform_Types.h"\r
+#include "Os.h" // includes Os_Cfg.h\r
+#include "kernel.h"\r
+#include "kernel_offset.h"\r
+#include "alist_i.h"\r
+#include "Mcu.h"\r
+\r
+extern void dec_exception( void );\r
+\r
+// atleast 1\r
+#define SERVICE_CNT 1\r
+\r
+GEN_TRUSTEDFUNCTIONS_LIST\r
+\r
+//--- APPLICATIONS ----\r
+\r
+GEN_APPLICATION_HEAD {\r
+\r
+ GEN_APPLICATON( 0,\r
+ "application_1",\r
+ true,\r
+ NULL,NULL,NULL , 0,0,0,0,0,0 )\r
+};\r
+\r
+// --- RESOURCES ---\r
+\r
+GEN_RESOURCE_HEAD {\r
+ GEN_RESOURCE(RES_SCHEDULER,RESOURCE_TYPE_STANDARD,0,0,0), // Standard resource..\r
+};\r
+\r
+//--- TASKS ----\r
+\r
+DECLARE_STACK(OsIdle,PRIO_STACK_SIZE);\r
+DECLARE_STACK(etask_1,PRIO_STACK_SIZE);\r
+DECLARE_STACK(etask_2,PRIO_STACK_SIZE);\r
+DECLARE_STACK(btask_3,PRIO_STACK_SIZE);\r
+\r
+GEN_TASK_HEAD {\r
+ GEN_ETASK( OsIdle,\r
+ 0,\r
+ true/*auto*/,\r
+ NULL/*tm*/,\r
+ APPLICATION_ID_application_1/*app*/,\r
+ NULL/*rsrc*/),\r
+\r
+ GEN_ETASK( etask_1,\r
+ 1,\r
+ true/*auto*/,\r
+ NULL/*tm*/,\r
+ APPLICATION_ID_application_1/*app*/,\r
+ NULL/*rsrc*/),\r
+\r
+ GEN_ETASK( etask_2,\r
+ 2,\r
+ true/*auto*/,\r
+ NULL/*tm*/,\r
+ APPLICATION_ID_application_1/*app*/,\r
+ NULL/*rsrc*/),\r
+\r
+\r
+ GEN_BTASK( btask_3,\r
+ 3,\r
+ false/*auto*/,\r
+ NULL/*tm*/,\r
+ APPLICATION_ID_application_1/*app*/,\r
+ NULL/*rsrc*/),\r
+};\r
+\r
+GEN_PCB_LIST()\r
+\r
+// --- INTERRUPTS ---\r
+\r
+uint8_t os_interrupt_stack[OS_INTERRUPT_STACK_SIZE] __attribute__ ((aligned (0x10)));\r
+\r
+// The vector table\r
+void * intc_vector_tbl[NUMBER_OF_INTERRUPTS_AND_EXCEPTIONS] __attribute__ ((aligned (0x1000),section(".data")))= {\r
+};\r
+\r
+// The type of vector\r
+uint8 intc_type_tbl[NUMBER_OF_INTERRUPTS_AND_EXCEPTIONS] = {\r
+};\r
+\r
+// --- COUNTERS ---\r
+GEN_COUNTER_HEAD {\r
+ GEN_COUNTER( OS_TICK_COUNTER,\r
+ "OS_TICK_COUNTER",\r
+ COUNTER_TYPE_HARD,\r
+ COUNTER_UNIT_NANO,\r
+ 0xffff,1,1,0 ),\r
+};\r
+\r
+// --- MESSAGES ---\r
+\r
+// --- ALARMS ---\r
+#define ALARM_USE\r
+\r
+GEN_ALARM_HEAD {\r
+ GEN_ALARM( 0,"Alarm1",OS_TICK_COUNTER,\r
+ 1,100,10,0, /*active,start,cycle,app_mask */\r
+ ALARM_ACTION_SETEVENT, TASK_ID_etask_1, 2, 0 ),\r
+};\r
+\r
+// --- SCHEDULETABLES ---\r
+\r
+// --- HOOKS ---\r
+\r
+GEN_HOOKS( StartupHook, ProtectionHook, ShutdownHook, ErrorHook, PreTaskHook, PostTaskHook )\r
+\r
+\r
+\r
+// --- MISC ---\r
+\r
+uint32 os_dbg_mask = \\r
+ D_MASTER_PRINT |\\r
+ D_ISR_MASTER_PRINT |\\r
+ D_RAMLOG |\\r
+ D_ISR_RAMLOG | D_TASK | D_ALARM;\r
+\r
+\r
+// | D_ALARM | D_TASK;\r
+\r
+\r
+#include "os_config_funcs.h"\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*\r
+ * Os_Cfg.h\r
+ *\r
+ * Created on: 2008-dec-22\r
+ * Author: mahi\r
+ */\r
+\r
+#ifndef OS_CFG_H_\r
+#define OS_CFG_H_\r
+\r
+/* os_config.h */\r
+\r
+#define APPLICATION_ID_application_1 0\r
+#define APPLICATION_CNT 1\r
+\r
+#define TASK_ID_OsIdle 0\r
+#define TASK_ID_etask_1 1\r
+#define TASK_ID_etask_2 2\r
+#define TASK_ID_btask_3 3\r
+\r
+void etask_1( void );\r
+void etask_2( void );\r
+void btask_3( void );\r
+\r
+//#define TASK_ID_os_tick 8\r
+\r
+\r
+// OS_TICK_COUNTER located in Os.h\r
+\r
+// NOT GENERATED( for test system only )\r
+#define SYSTEM_COUNTER_PERIOD 100\r
+\r
+#define PRIO_STACK_SIZE 2600\r
+#define OS_INTERRUPT_STACK_SIZE 2048\r
+\r
+// Just define them if you want to use them.\r
+#undef ALARM_USE\r
+#undef SCHEDULETABLE_USE\r
+#undef MESSAGE_USE\r
+#undef EVENT_USE\r
+#undef SERVICE_USE\r
+\r
+#define EVENT_0 (1<<0)\r
+#define EVENT_1 (1<<1)\r
+#define EVENT_2 (1<<2)\r
+\r
+\r
+#endif /* OS_CFG_H_ */\r
--- /dev/null
+\r
+# Our object files\r
+obj-y += simple_main.o\r
+# OS object files.\r
+obj-y += Os_Cfg.o\r
+\r
+VPATH += ..\r
+VPATH += ../config\r
+\r
+inc-y += ../config\r
+inc-y += $(ROOTDIR)/system/kernel/$(objdir)\r
+inc-y += $(ROOTDIR)/system/kernel/include\r
+\r
+# The more precise configuration, the higher preceedance.\r
+VPATH := ../config/$(BOARDDIR) ../config $(VPATH)\r
+inc-y := ../config/$(BOARDDIR) ../config $(inc-y)\r
+\r
+# Board object files\r
+include $(ROOTDIR)/boards/board_common.mk\r
+\r
+# libs needed by us \r
+libitem-y += $(ROOTDIR)/libs/libkernel_$(ARCH_MCU).a\r
+\r
+#linkfile\r
+ldcmdfile-y = -T $(ROOTDIR)/$(ARCH_PATH-y)/scripts/linkscript_gcc.ldf\r
+\r
+# What I want to build\r
+build-exe-y = simple.elf\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+#include "Os.h"\r
+#include "Mcu.h"\r
+\r
+#define USE_DEBUG\r
+#include "Trace.h"\r
+\r
+// How many errors to keep in error log.\r
+#define ERROR_LOG_SIZE 20\r
+\r
+\r
+/**\r
+ * Just an example of a basic task.\r
+ */\r
+\r
+void btask_3( void ) {\r
+ StackInfoType si;\r
+ TaskType currTask;\r
+ dbg_printf("[%08d] btask_3 start\n", GetOsTick() );\r
+\r
+ GetTaskID(&currTask);\r
+ Os_GetStackInfo(currTask,&si);\r
+ dbg_printf("btask_3: Stack usage %d%%\n",OS_STACK_USAGE(&si));\r
+\r
+ TerminateTask();\r
+}\r
+\r
+/**\r
+ * An extended task is auto-started and is also triggered by an alarm\r
+ * that sets event 2.\r
+ */\r
+\r
+void etask_1( void ) {\r
+ volatile float tryFloatingPoint = 0.0F;\r
+ StackInfoType si;\r
+ TaskType currTask;\r
+\r
+\r
+ dbg_printf("etask_1 start\n");\r
+ for(;;) {\r
+ SetEvent(TASK_ID_etask_2,1);\r
+ WaitEvent(2);\r
+ ClearEvent(2);\r
+ tryFloatingPoint += 1.0F;\r
+ GetTaskID(&currTask);\r
+ Os_GetStackInfo(currTask,&si);\r
+ dbg_printf("etask_1: Stack usage %d%% \n",OS_STACK_USAGE(&si));\r
+\r
+ }\r
+}\r
+\r
+/**\r
+ * An extended task that receives events from someone\r
+ * and activates task: btask_3.
+ */\r
+void etask_2( void ) {\r
+ dbg_printf("etask_2 start\n");\r
+\r
+ for(;;) {\r
+ WaitEvent(1);\r
+ ClearEvent(1);\r
+ ActivateTask(TASK_ID_btask_3);\r
+ {\r
+ StackInfoType si;\r
+ TaskType currTask;\r
+ GetTaskID(&currTask);\r
+ Os_GetStackInfo(currTask,&si);\r
+ dbg_printf("etask_1: Stack usage %d%% \n",OS_STACK_USAGE(&si));\r
+ }\r
+ }\r
+}\r
+\r
+\r
+/*\r
+ * Functions that must be supplied by the example\r
+ */\r
+\r
+void OsIdle( void ) {\r
+ for(;;);\r
+}\r
+\r
+\r
+/* Global hooks */\r
+ProtectionReturnType ProtectionHook( StatusType FatalError ) {\r
+ dbg_printf("## ProtectionHook\n");\r
+ return PRO_KILLAPPL;\r
+}\r
+\r
+void StartupHook( void ) {\r
+ uint32_t sys_freq = McuE_GetSystemClock();\r
+\r
+ dbg_printf("## StartupHook\n");\r
+\r
+ dbg_printf("Sys clock %d Hz\n",sys_freq);\r
+ Frt_Init();\r
+ Frt_Start(sys_freq/1000);\r
+}\r
+\r
+void ShutdownHook( StatusType Error ) {\r
+ dbg_printf("## ShutdownHook\n");\r
+ while(1);\r
+}\r
+\r
+struct LogBad_s {\r
+ uint32_t param1;\r
+ uint32_t param2;\r
+ uint32_t param3;\r
+ TaskType taskId;\r
+ OsServiceIdType serviceId;\r
+ StatusType error;\r
+};\r
+\r
+void ErrorHook( StatusType Error ) {\r
+\r
+ TaskType task;\r
+ static struct LogBad_s LogBad[ERROR_LOG_SIZE];\r
+ static uint8_t ErrorCount = 0;\r
+\r
+ GetTaskID(&task);\r
+\r
+\r
+ OsServiceIdType service = OSErrorGetServiceId();\r
+\r
+ /* Grab the arguments to the functions\r
+ * This is the standard way, see 11.2 in OSEK spec
+ */\r
+ switch(service) {\r
+ case OSServiceId_SetRelAlarm:\r
+ {\r
+ // Read the arguments to the faulty functions...\r
+ AlarmType alarm_id = OSError_SetRelAlarm_AlarmId;\r
+ TickType increment = OSError_SetRelAlarm_Increment;\r
+ TickType cycle = OSError_SetRelAlarm_Cycle;\r
+ // ... Handle this some way.\r
+ break;\r
+ }\r
+ /*\r
+ * The same pattern as above applies for all other OS functions.\r
+ * See Os.h for names and definitions.
+ */\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ dbg_printf("## ErrorHook err=%d\n",Error);\r
+\r
+ /* Log the errors in a buffer for later review */\r
+ LogBad[ErrorCount].param1 = os_error.param1;\r
+ LogBad[ErrorCount].param2 = os_error.param2;\r
+ LogBad[ErrorCount].param3 = os_error.param3;\r
+ LogBad[ErrorCount].serviceId = service;\r
+ LogBad[ErrorCount].taskId = task;\r
+ LogBad[ErrorCount].error = Error;\r
+\r
+ ErrorCount++;\r
+\r
+ // Stall if buffer is full.\r
+ while(ErrorCount >= ERROR_LOG_SIZE);\r
+}\r
+\r
+void PreTaskHook( void ) {\r
+ TaskType task;\r
+ GetTaskID(&task);\r
+// dbg_printf("## PreTaskHook, taskid=%d\n",task);\r
+}\r
+\r
+void PostTaskHook( void ) {\r
+ TaskType task;\r
+ GetTaskID(&task);\r
+// dbg_printf("## PostTaskHook, taskid=%d\n",task);\r
+}\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include "Os.h"
+#include <stdio.h>
+#include <assert.h>
+#define USE_TRACE 1
+#include "Trace.h"
+//#include "Hooks.h"
+
+
+#if 0
+#ifdef USE_STARTUPHOOK
+#ifdef CFG_MPC55XX
+#if !defined(USE_SIMULATOR)
+// Quick fix
+//#include "Kernel_Offset.h"
+#include "Mcu.h"
+
+extern uint8_t pcb_list[];
+
+#endif
+#endif
+#endif
+#endif
+
+
+
+/* Global hooks */
+ProtectionReturnType ProtectionHook( StatusType FatalError ) {
+ dbg_printf("## ProtectionHook\n");
+ return PRO_KILLAPPL;
+}
+
+void StartupHook( void ) {
+ dbg_printf("## StartupHook\n");
+
+ uint32_t sys_freq = McuE_GetSystemClock();
+
+ dbg_printf("Sys clock %d Hz\n",sys_freq);
+ Frt_Init();
+ Frt_Start(sys_freq/1000);
+
+}
+
+void ShutdownHook( StatusType Error ) {
+ dbg_printf("## ShutdownHook\n");
+ while(1);
+}
+
+void ErrorHook( StatusType Error ) {
+ DisableAllInterrupts();
+
+ dbg_printf("## ErrorHook err=%d\n",Error);
+ while(1);
+}
+
+void PreTaskHook( void ) {
+// dbg_printf("## PreTaskHook, taskid=%d\n",task);
+}
+
+void PostTaskHook( void ) {
+// dbg_printf("## PostTaskHook, taskid=%d\n",task);
+}
+
+#if 0
+struct os_conf_global_hooks_s os_conf_global_hooks = {
+ .StartupHook = StartupHook,
+ .ProtectionHook = ProtectionHook,
+ .ShutdownHook = ShutdownHook,
+ .ErrorHook = ErrorHook,
+ .PreTaskHook = PreTaskHook,
+ .PostTaskHook = PostTaskHook
+ };
+#endif
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+#include "Com.h"\r
+\r
+void RTE_send_led_level(uint16 arg){\r
+ Com_SendSignal(SetLedLevelTx, &arg);\r
+}\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+\r
+#ifndef RTE_H_\r
+#define RTE_H_\r
+#include "RTE_switch.h"\r
+\r
+#endif /* RTE_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include "Os.h"\r
+\r
+#include "EcuM.h"\r
+#include <stdio.h>\r
+#include <assert.h>\r
+#include "Trace.h"\r
+#include "Com.h"\r
+#include "Adc.h"\r
+\r
+void OsIdle( void ) {\r
+ for(;;);\r
+}\r
+\r
+\r
+void ComTask( void ) {\r
+ // Run COM scheduled functions.\r
+ Com_MainFunctionTx();\r
+ Com_MainFunctionRx();\r
+\r
+ TerminateTask();\r
+}\r
+\r
+void ReadSwitches( void ) {\r
+ // Trigger update of switch readings\r
+ Adc_StartGroupConversion(ADC_SWITCHES); // Read the switches\r
+ Adc_StartGroupConversion(ADC_POTENTIOMETERS);\r
+\r
+ TerminateTask();\r
+}\r
+\r
+/*\r
+ * This is the startup task. It is activated once immediately after the OS i started.
+ */\r
+void StartupTask( void ) {\r
+\r
+ // Call second phase of startup sequence.\r
+ EcuM_StartupTwo();\r
+\r
+ // Make sure that the right PDU-groups are ready for communication.\r
+ Com_IpduGroupStart(TxGroup, 0);\r
+\r
+ // End of startup_task().\r
+ TerminateTask();\r
+}\r
+\r
+\r
--- /dev/null
+\r
+MOD_USE+=KERNEL MCU ADC DMA PORT COM CAN CANIF WINIDEA_TERM\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include "Adc.h"\r
+#include "Dma.h"\r
+#include "mpc5516.h"\r
+\r
+const struct tcd_t AdcGroupDMACommandConfig [ADC_NBR_OF_GROUPS];\r
+const struct tcd_t AdcGroupDMAResultConfig [ADC_NBR_OF_GROUPS];\r
+\r
+Adc_GroupStatus AdcGroupStatus[ADC_NBR_OF_GROUPS] = {\r
+ {\r
+ .notifictionEnable = 1,\r
+ },\r
+ {\r
+ .notifictionEnable = 1,\r
+ }\r
+};\r
+\r
+extern void switch_node_switches_callback (void);\r
+extern void switch_node_potentiometers_callback (void);\r
+\r
+\r
+const Adc_HWConfigurationType AdcHWUnitConfiguration =\r
+{\r
+ .hwUnitId = 0,\r
+ .adcPrescale = ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_8,\r
+ .clockSource = ADC_SYSTEM_CLOCK,\r
+};\r
+\r
+const Adc_ChannelConfigurationType AdcChannelConfiguration [ADC_NBR_OF_CHANNELS] =\r
+{\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_DISABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+};\r
+\r
+/*\r
+ * The switches
+ */\r
+const Adc_ChannelType Adc_Group0ChannelList[ADC_NBR_OF_SWITCH_CHANNELS] =\r
+{\r
+ ADC_CH11, ADC_CH12\r
+};\r
+\r
+\r
+/*\r
+ * The potentiometers\r
+ */\r
+const Adc_ChannelType Adc_Group1ChannelList[ADC_NBR_OF_POTENTIOMETER_CHANNELS] =\r
+{\r
+ ADC_CH8, ADC_CH9, ADC_CH10\r
+};\r
+\r
+\r
+/* Ram buffers for command and result queues. These are located here in the\r
+ configuration to be able to reconfigure system without recompiling the\r
+ drivers. */\r
+Adc_ValueGroupType Adc_Group0Buffer [sizeof(Adc_Group0ChannelList)/sizeof(Adc_Group0ChannelList[0])];\r
+Adc_CommandType Adc_Group0Commands [sizeof(Adc_Group0ChannelList)/sizeof(Adc_Group0ChannelList[0])];\r
+\r
+Adc_ValueGroupType Adc_Group1Buffer [sizeof(Adc_Group1ChannelList)/sizeof(Adc_Group1ChannelList[0])];\r
+Adc_CommandType Adc_Group1Commands [sizeof(Adc_Group1ChannelList)/sizeof(Adc_Group1ChannelList[0])];\r
+\r
+/*\r
+Adc_ValueGroupType Adc_Group2Buffer [sizeof(Adc_Group2ChannelList)/sizeof(Adc_Group2ChannelList[0])];\r
+Adc_CommandType Adc_Group2Commands [sizeof(Adc_Group2ChannelList)/sizeof(Adc_Group2ChannelList[0])];\r
+\r
+Adc_ValueGroupType Adc_Group3Buffer [sizeof(Adc_Group3ChannelList)/sizeof(Adc_Group3ChannelList[0])];\r
+Adc_CommandType Adc_Group3Commands [sizeof(Adc_Group3ChannelList)/sizeof(Adc_Group3ChannelList[0])];\r
+*/\r
+\r
+const Adc_GroupDefType AdcGroupConfiguration [] =\r
+{\r
+ { .accessMode = ADC_ACCESS_MODE_SINGLE, .conversionMode = ADC_CONV_MODE_ONESHOT,\r
+ .triggerSrc = ADC_TRIGG_SRC_SW, .hwTriggerSignal = ADC_NO_HW_TRIG,\r
+ .hwTriggerTimer = ADC_NO_TIMER,\r
+ .groupCallback = switch_node_switches_callback,\r
+ .streamBufferMode = ADC_NO_STREAMING, .streamNumSamples = 0,\r
+ .channelList = Adc_Group0ChannelList,\r
+ .resultBuffer = Adc_Group0Buffer,\r
+ .commandBuffer = Adc_Group0Commands,\r
+ .numberOfChannels = sizeof(Adc_Group0Commands)/sizeof(Adc_Group0Commands[0]),\r
+ .status = &AdcGroupStatus[ADC_GROUP0],\r
+ .dmaCommandChannel = DMA_ADC_GROUP0_COMMAND_CHANNEL,\r
+ .dmaResultChannel = DMA_ADC_GROUP0_RESULT_CHANNEL,\r
+ .groupDMACommands = &AdcGroupDMACommandConfig[ADC_GROUP0],\r
+ .groupDMAResults = &AdcGroupDMAResultConfig[ADC_GROUP0]},\r
+\r
+ { .accessMode = ADC_ACCESS_MODE_SINGLE, .conversionMode = ADC_CONV_MODE_ONESHOT,\r
+ .triggerSrc = ADC_TRIGG_SRC_SW, .hwTriggerSignal = ADC_NO_HW_TRIG,\r
+ .hwTriggerTimer = ADC_NO_TIMER,\r
+ .groupCallback = switch_node_potentiometers_callback,\r
+ .streamBufferMode = ADC_NO_STREAMING, .streamNumSamples = 0,\r
+ .channelList = Adc_Group1ChannelList,\r
+ .resultBuffer = Adc_Group1Buffer,\r
+ .commandBuffer = Adc_Group1Commands,\r
+ .numberOfChannels = sizeof(Adc_Group1Commands)/sizeof(Adc_Group1Commands[0]),\r
+ .status = &AdcGroupStatus[ADC_GROUP1],\r
+ .dmaCommandChannel = DMA_ADC_GROUP1_COMMAND_CHANNEL,\r
+ .dmaResultChannel = DMA_ADC_GROUP1_RESULT_CHANNEL,\r
+ .groupDMACommands = &AdcGroupDMACommandConfig[ADC_GROUP1],\r
+ .groupDMAResults = &AdcGroupDMAResultConfig[ADC_GROUP1]}\r
+};\r
+\r
+\r
+/******************************************************************/\r
+/* */\r
+/* End of user configuration area. DO NOT modify the code below!! */\r
+/* */\r
+/******************************************************************/\r
+const Adc_ConfigType AdcConfig [] =\r
+{\r
+ {\r
+ .hwConfigPtr = &AdcHWUnitConfiguration,\r
+ .channelConfigPtr = AdcChannelConfiguration,\r
+ .nbrOfChannels = sizeof(AdcChannelConfiguration)/sizeof(AdcChannelConfiguration[0]),\r
+ .groupConfigPtr = AdcGroupConfiguration,\r
+ .nbrOfGroups = sizeof(AdcGroupConfiguration)/sizeof(AdcGroupConfiguration[0])}\r
+};\r
+\r
+/* DMA configuration. */\r
+const struct tcd_t AdcGroupDMACommandConfig [ADC_NBR_OF_GROUPS] =\r
+{\r
+ {\r
+ .SADDR = (uint32_t)Adc_Group0Commands,\r
+ .SMOD = 0,\r
+ .SSIZE = DMA_TRANSFER_SIZE_32BITS,\r
+ .DMOD = 0,\r
+ .DSIZE = DMA_TRANSFER_SIZE_32BITS,\r
+ .SOFF = sizeof(Adc_CommandType),\r
+ .NBYTES = sizeof(Adc_CommandType),\r
+ .SLAST = -sizeof(Adc_Group0Commands),\r
+ .DADDR = (vint32_t)&EQADC.CFPR[ADC_GROUP0].R,\r
+ .CITERE_LINK = 0,\r
+ .CITER = sizeof(Adc_Group0Commands)/sizeof(Adc_Group0Commands[0]),\r
+ .DOFF = 0,\r
+ .DLAST_SGA = 0,\r
+ .BITERE_LINK = 0,\r
+ .BITER = sizeof(Adc_Group0Commands)/sizeof(Adc_Group0Commands[0]),\r
+ .BWC = 0,\r
+ .MAJORLINKCH = 0,\r
+ .DONE = 0,\r
+ .ACTIVE = 0,\r
+ .MAJORE_LINK = 0,\r
+ .E_SG = 0,\r
+ .D_REQ = 0,\r
+ .INT_HALF = 0,\r
+ .INT_MAJ = 0,\r
+ .START = 0\r
+ },\r
+ {\r
+ .SADDR = (uint32_t)Adc_Group1Commands,\r
+ .SMOD = 0,\r
+ .SSIZE = DMA_TRANSFER_SIZE_32BITS,\r
+ .DMOD = 0,\r
+ .DSIZE = DMA_TRANSFER_SIZE_32BITS,\r
+ .SOFF = sizeof(Adc_CommandType),\r
+ .NBYTES = sizeof(Adc_CommandType),\r
+ .SLAST = -sizeof(Adc_Group1Commands),\r
+ .DADDR = (vint32_t)&EQADC.CFPR[ADC_GROUP1].R,\r
+ .CITERE_LINK = 0,\r
+ .CITER = sizeof(Adc_Group1Commands)/sizeof(Adc_Group1Commands[0]),\r
+ .DOFF = 0,\r
+ .DLAST_SGA = 0,\r
+ .BITERE_LINK = 0,\r
+ .BITER = sizeof(Adc_Group1Commands)/sizeof(Adc_Group1Commands[0]),\r
+ .BWC = 0,\r
+ .MAJORLINKCH = 0,\r
+ .DONE = 0,\r
+ .ACTIVE = 0,\r
+ .MAJORE_LINK = 0,\r
+ .E_SG = 0,\r
+ .D_REQ = 0,\r
+ .INT_HALF = 0,\r
+ .INT_MAJ = 0,\r
+ .START = 0\r
+ }\r
+};\r
+\r
+const struct tcd_t AdcGroupDMAResultConfig [ADC_NBR_OF_GROUPS]=\r
+{\r
+ {\r
+ .SADDR = (vint32_t)&EQADC.RFPR[ADC_GROUP0].R + 2,\r
+ .SMOD = 0,\r
+ .SSIZE = DMA_TRANSFER_SIZE_16BITS,\r
+ .DMOD = 0,\r
+ .DSIZE = DMA_TRANSFER_SIZE_16BITS,\r
+ .SOFF = 0,\r
+ .NBYTES = sizeof(Adc_ValueGroupType),\r
+ .SLAST = 0,\r
+ .DADDR = (uint32_t)Adc_Group0Buffer,\r
+ .CITERE_LINK = 0,\r
+ .CITER = sizeof(Adc_Group0Buffer)/sizeof(Adc_Group0Buffer[0]),\r
+ .DOFF = sizeof(Adc_ValueGroupType),\r
+ .DLAST_SGA = -sizeof(Adc_Group0Buffer),\r
+ .BITERE_LINK = 0,\r
+ .BITER = sizeof(Adc_Group0Buffer)/sizeof(Adc_Group0Buffer[0]),\r
+ .BWC = 0,\r
+ .MAJORLINKCH = 0,\r
+ .DONE = 0,\r
+ .ACTIVE = 0,\r
+ .MAJORE_LINK = 0,\r
+ .E_SG = 0,\r
+ .D_REQ = 0,\r
+ .INT_HALF = 0,\r
+ .INT_MAJ = 0,\r
+ .START = 0\r
+ },\r
+ {\r
+ .SADDR = (vint32_t)&EQADC.RFPR[ADC_GROUP1].R + 2,\r
+ .SMOD = 0,\r
+ .SSIZE = DMA_TRANSFER_SIZE_16BITS,\r
+ .DMOD = 0,\r
+ .DSIZE = DMA_TRANSFER_SIZE_16BITS,\r
+ .SOFF = 0,\r
+ .NBYTES = sizeof(Adc_ValueGroupType),\r
+ .SLAST = 0,\r
+ .DADDR = (uint32_t)Adc_Group1Buffer,\r
+ .CITERE_LINK = 0,\r
+ .CITER = sizeof(Adc_Group1Buffer)/sizeof(Adc_Group1Buffer[0]),\r
+ .DOFF = sizeof(Adc_ValueGroupType),\r
+ .DLAST_SGA = -sizeof(Adc_Group1Buffer),\r
+ .BITERE_LINK = 0,\r
+ .BITER = sizeof(Adc_Group1Buffer)/sizeof(Adc_Group1Buffer[0]),\r
+ .BWC = 0,\r
+ .MAJORLINKCH = 0,\r
+ .DONE = 0,\r
+ .ACTIVE = 0,\r
+ .MAJORE_LINK = 0,\r
+ .E_SG = 0,\r
+ .D_REQ = 0,\r
+ .INT_HALF = 0,\r
+ .INT_MAJ = 0,\r
+ .START = 0\r
+}\r
+};\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef ADC_CFG_H_\r
+#define ADC_CFG_H_\r
+\r
+#define ADC_PRIORITY_HW 0\r
+#define ADC_PRIORITY_HW_SW 1\r
+#define ADC_PRIORITY_NONE 2\r
+\r
+#define ADC_DEINIT_API STD_ON\r
+#define ADC_DEV_ERROR_DETECT STD_ON\r
+#define ADC_ENABLE_QUEUING STD_ON\r
+#define ADC_ENABLE_START_STOP_GROUP_API STD_ON\r
+#define ADC_GRP_NOTIF_CAPABILITY STD_ON\r
+#define ADC_HW_TRIGGER_API STD_OFF /* Not implemented. */\r
+#define ADC_PRIORITY_IMPLEMENTATION ADC_PRIORITY_HW\r
+#define ADC_READ_GROUP_API STD_ON\r
+#define ADC_VERSION_API STD_ON /* Not implemented. */\r
+\r
+/* Group definitions. */\r
+\r
+\r
+typedef enum\r
+{\r
+ ADC_SWITCHES,\r
+ ADC_POTENTIOMETERS\r
+}Adc_GroupType_NiceNames;\r
+\r
+typedef enum\r
+{\r
+ ADC_GROUP0,\r
+ ADC_GROUP1,\r
+ ADC_NBR_OF_GROUPS\r
+}Adc_GroupType;\r
+\r
+typedef enum\r
+{\r
+ ADC_CH0,\r
+ ADC_CH1,\r
+ ADC_CH2,\r
+ ADC_CH3,\r
+ ADC_CH4,\r
+ ADC_CH5,\r
+ ADC_CH6,\r
+ ADC_CH7,\r
+ ADC_CH8,\r
+ ADC_CH9,\r
+ ADC_CH10,\r
+ ADC_CH11,\r
+ ADC_CH12,\r
+ ADC_CH13,\r
+ ADC_CH14,\r
+ ADC_CH15,\r
+ ADC_CH16,\r
+ ADC_CH17,\r
+ ADC_CH18,\r
+ ADC_CH19,\r
+ ADC_CH20,\r
+ ADC_NBR_OF_CHANNELS,\r
+}Adc_ChannelType;\r
+\r
+typedef enum\r
+{\r
+ ADC_SWITCH_RED,\r
+ ADC_SWITCH_BLACK,\r
+ ADC_NBR_OF_SWITCH_CHANNELS,\r
+}Adc_SwitchesSignalType;\r
+\r
+typedef enum\r
+{\r
+ ADC_POTENTIOMETER_NOT_USED,\r
+ ADC_POTENTIOMETER_0,\r
+\r
+ ADC_POTENTIOMETER_1,\r
+ ADC_NBR_OF_POTENTIOMETER_CHANNELS,\r
+}Adc_PotentiometersSignals;\r
+\r
+extern const struct tcd_t AdcGroupDMACommandConfig [ADC_NBR_OF_GROUPS];\r
+extern const struct tcd_t AdcGroupDMAResultConfig [ADC_NBR_OF_GROUPS];\r
+\r
+#endif /*ADC_CFG_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include "CanIf.h"\r
+#include <stdlib.h>\r
+\r
+// Imported structs from Can_Lcfg.c\r
+extern const Can_ControllerConfigType CanControllerConfigData[];\r
+extern const Can_ConfigSetType CanConfigSetData;\r
+\r
+\r
+// Container that gets slamed into CanIf_InitController()\r
+// Inits ALL controllers\r
+// Multiplicity 1..*\r
+const CanIf_ControllerConfigType CanIfControllerConfig[] =\r
+{\r
+ { // This is the ConfigurationIndex in CanIf_InitController()\r
+ .WakeupSupport = CANIF_WAKEUP_SUPPORT_NO_WAKEUP,\r
+ .CanIfControllerIdRef = CAN_CTRL_A,\r
+ .CanIfDriverNameRef = "FLEXCAN", // Not used\r
+ .CanIfInitControllerRef = &CanControllerConfigData[0],\r
+ },\r
+};\r
+\r
+// Function callbacks for higher layers\r
+const CanIf_DispatchConfigType CanIfDispatchConfig =\r
+{\r
+ .CanIfBusOffNotification = NULL,\r
+ .CanIfWakeUpNotification = NULL, // Not used\r
+ .CanIfWakeupValidNotification = NULL, // Not used\r
+ .CanIfErrorNotificaton = NULL,\r
+};\r
+\r
+//-------------------------------------------------------------------\r
+const CanIf_HthConfigType CanIfHthConfigData[] =\r
+{\r
+ {\r
+ .CanIfHthType = CAN_ECORE_HANDLE_TYPE_BASIC,\r
+ .CanIfCanControllerIdRef = CAN_CTRL_A,\r
+ .CanIfHthIdSymRef = CAN_HTH_A_1, // Ref to the HTH\r
+ .CanIfEcoreEOL = 0,\r
+ },\r
+};\r
+\r
+//-------------------------------------------------------------------\r
+const CanIf_HrhConfigType CanIfHrhConfigData[] =\r
+{\r
+ {\r
+ .CanIfHrhType = CAN_ECORE_HANDLE_TYPE_BASIC,\r
+ .CanIfSoftwareFilterHrh = TRUE, // Disable software filtering\r
+ .CanIfCanControllerHrhIdRef = CAN_CTRL_A,\r
+ .CanIfHrhIdSymRef = CAN_HRH_A_1, // Ref to the HRH\r
+ .CanIfEcoreEOL = 0,\r
+ },\r
+};\r
+//-------------------------------------------------------------------\r
+\r
+/*\r
+ * TX PDUs\r
+ */\r
+const CanIf_TxPduConfigType CanIfTxPduConfigData[] =\r
+{\r
+ {\r
+ .CanIfTxPduId = LedCommandTx,\r
+ .CanIfCanTxPduIdCanId = 0x123,\r
+ .CanIfCanTxPduIdDlc = 8,\r
+ .CanIfCanTxPduType = CANIF_PDU_TYPE_STATIC,\r
+#if ( CANIF_READTXPDU_NOTIFY_STATUS_API == STD_ON )\r
+ .CanIfReadTxPduNotifyStatus = FALSE,\r
+#endif\r
+ .CanIfTxPduIdCanIdType = CANIF_CAN_ID_TYPE_29,\r
+ .CanIfUserTxConfirmation = PduR_CanIfTxConfirmation,\r
+ .CanIfCanTxPduHthRef = &CanIfHthConfigData[0],\r
+ .PduIdRef = NULL,\r
+ },\r
+};\r
+//-------------------------------------------------------------------\r
+\r
+/*\r
+ * RX PDUs\r
+ */\r
+const CanIf_RxPduConfigType CanIfRxPduConfigData[] =\r
+{\r
+};\r
+\r
+//-------------------------------------------------------------------\r
+const CanIf_InitHohConfigType CanIfHohConfigData[] =\r
+{\r
+ {\r
+ .CanConfigSet = &CanConfigSetData,\r
+ .CanIfHrhConfig = CanIfHrhConfigData,\r
+ .CanIfHthConfig = CanIfHthConfigData,\r
+ .CanIfEcoreEOL = 1,\r
+ },\r
+};\r
+\r
+// This container contains the init parameters of the CAN\r
+// Multiplicity 1..*\r
+const CanIf_InitConfigType CanIfInitConfig =\r
+{\r
+ .CanIfConfigSet = 0, // Not used\r
+ .CanIfNumberOfCanRxPduIds = sizeof(CanIfRxPduConfigData)/sizeof(CanIf_RxPduConfigType),\r
+ .CanIfNumberOfCanTXPduIds = sizeof(CanIfTxPduConfigData)/sizeof(CanIf_TxPduConfigType),\r
+ .CanIfNumberOfDynamicCanTXPduIds = 0, // Not used\r
+\r
+ // Containers\r
+ .CanIfHohConfigPtr = CanIfHohConfigData,\r
+ .CanIfRxPduConfigPtr = CanIfRxPduConfigData,\r
+ .CanIfTxPduConfigPtr = CanIfTxPduConfigData,\r
+};\r
+\r
+// This container includes all necessary configuration sub-containers\r
+// according the CAN Interface configuration structure.\r
+CanIf_ConfigType CanIf_Config =\r
+{\r
+ .ControllerConfig = CanIfControllerConfig,\r
+ .DispatchConfig = &CanIfDispatchConfig,\r
+ .InitConfig = &CanIfInitConfig,\r
+ .TransceiverConfig = NULL, // Not used\r
+};\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*
+* Module vendor: Autocore
+* Module version: 1.0.0
+* Specification: Autosar v3.0.1, Final
+*
+*/
+
+\r
+#ifndef COMGLOBALS_H_\r
+#define COMGLOBALS_H_\r
+\r
+// PDU handle id definitions.\r
+enum {\r
+ LedCommandTx = 0,\r
+};\r
+\r
+#endif
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*
+* Module vendor: Autocore
+* Module version: 1.0.0
+* Specification: Autosar v3.0.1, Final
+*
+*/
+
+\r
+#ifndef COM_CFG_H_\r
+#define COM_CFG_H_\r
+\r
+#define COM_MODULE_ID 20\r
+#define COM_INSTANCE_ID 1\r
+\r
+#define COM_DEV_ERROR_DETECT\r
+\r
+#define COM_MAX_NR_IPDU 5\r
+#define COM_MAX_NR_SIGNAL 6\r
+#define COM_MAX_NR_GROUPSIGNAL 10\r
+\r
+#define COM_MAX_NR_SIGNALS_PER_IPDU 4\r
+#define COM_MAX_NR_SIGNALGROUPS_PER_IPDU 4\r
+#define COM_MAX_NR_SIGNALS_PER_SIGNAL_GROUP 5\r
+\r
+#define COM_E_INVALID_FILTER_CONFIGURATION 101\r
+#define COM_E_INITIALIZATION_FAILED 102\r
+#define COM_E_INVALID_SIGNAL_CONFIGURATION 103\r
+#define COM_INVALID_PDU_ID 104\r
+#define COM_ERROR_SIGNAL_IS_SIGNALGROUP 105\r
+\r
+#define COM_E_TOO_MANY_IPDU 106\r
+#define COM_E_TOO_MANY_SIGNAL 107\r
+#define COM_E_TOO_MANY_GROUPSIGNAL 108\r
+\r
+#define CPU_ENDIANESS BIG_ENDIAN\r
+\r
+/*\r
+ * ComGeneral pre-compile time configuration parameters.\r
+ */\r
+#define ComConfigurationTimeBase NULL\r
+#define ComConfigurationUseDet \r
+#define ComVersionInfoApi\r
+\r
+#endif /*COM_CFG_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*
+* Module vendor: Autocore
+* Module version: 1.0.0
+* Specification: Autosar v3.0.1, Final
+*
+*/
+
+\r
+#include "Com_PbCfg.h"\r
+#include "stdlib.h"\r
+\r
+\r
+/*\r
+ * Group signal definitions\r
+ */\r
+ComGroupSignal_type ComGroupSignal[] = {\r
+ {\r
+ .ComEcoreEOL = 1\r
+ }\r
+};\r
+\r
+\r
+/*\r
+ * Signal definitions\r
+ */\r
+ComSignal_type ComSignal[] = {\r
+ {\r
+ .ComHandleId = SetLedLevelTx,\r
+ .ComFirstTimeoutFactor = 0,\r
+ .ComNotification = NULL,\r
+ .ComTimeoutFactor = 0,\r
+ .ComTimeoutNotification = NULL,\r
+ .ComTransferProperty = TRIGGERED,\r
+\r
+\r
+ .ComSignalInitValue = 0,\r
+ .ComBitPosition = 0,\r
+ .ComBitSize = 16,\r
+ .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalType = UINT16,
+ .ComEcoreIsSignalGroup = 0,\r
+\r
+ },\r
+ {\r
+ .ComEcoreEOL = 1\r
+ }\r
+};\r
+\r
+\r
+/*\r
+ * I-PDU group definitions\r
+ */\r
+ComIPduGroup_type ComIPduGroup[] = {\r
+ {\r
+ .ComIPduGroupHandleId = TxGroup\r
+ },\r
+\r
+ {\r
+ .ComEcoreEOL = 1\r
+ }\r
+};\r
+\r
+\r
+/*\r
+ * I-PDU definitions\r
+ */\r
+ComIPdu_type ComIPdu[] = {\r
+\r
+ {\r
+ .ComIPduRxHandleId = LedCommandTx,\r
+ .ComIPduCallout = NULL,\r
+ .ComIPduSignalProcessing = IMMEDIATE,\r
+ .ComIPduSize = 2,\r
+ .ComIPduDirection = SEND,\r
+ .ComIPduGroupRef = TxGroup,\r
+\r
+ .ComTxIPdu = {\r
+ .ComTxIPduMinimumDelayFactor = 0,\r
+ .ComTxIPduUnusedAreasDefault = 0,\r
+ .ComTxModeTrue = {\r
+ .ComTxModeMode = DIRECT,\r
+ .ComTxModeNumberOfRepetitions = 0,\r
+ .ComTxModeRepetitionPeriodFactor = 0,\r
+ .ComTxModeTimeOffsetFactor = 0,\r
+ .ComTxModeTimePeriodFactor = 0,\r
+ },\r
+ },\r
+\r
+ .ComIPduSignalRef = {\r
+\r
+ &ComSignal[ SetLedLevelTx ],\r
+\r
+ NULL,\r
+ },\r
+ },\r
+ {\r
+ .ComEcoreEOL = 1\r
+ }\r
+};\r
+\r
+const Com_ConfigType ComConfiguration = {\r
+ .ComConfigurationId = 1,\r
+ .ComIPdu = ComIPdu,\r
+ .ComIPduGroup = ComIPduGroup,\r
+ .ComSignal = ComSignal,\r
+ .ComGroupSignal = ComGroupSignal\r
+};\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*
+* Module vendor: Autocore
+* Module version: 1.0.0
+* Specification: Autosar v3.0.1, Final
+*
+*/
+
+#ifndef COM_PBCFG_H_\r
+#define COM_PBCFG_H_\r
+\r
+#include "Com_Types.h"\r
+\r
+extern const Com_ConfigType ComConfiguration;\r
+\r
+// PDU group definitions\r
+enum {\r
+ TxGroup = 0,\r
+};\r
+\r
+\r
+// Signal definitions\r
+enum {\r
+ SetLedLevelTx = 0,\r
+};\r
+\r
+\r
+#endif /* COM_PBCFG_H_ */
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*
+* Module vendor: Autocore
+* Module version: 1.0.0
+* Specification: Autosar v3.0.1, Final
+*
+*/
+
+\r
+// File generated on Tue Aug 18 13:49:03 CEST 2009\r
+\r
+#include <stdlib.h>\r
+#include <stdint.h>\r
+#include "os_config_macros.h"\r
+#include "Platform_Types.h"\r
+#include "Os.h" // includes Os_Cfg.h\r
+#include "Kernel.h"\r
+#include "Kernel_Offset.h"\r
+#include "alist_i.h"\r
+#include "Mcu.h"\r
+\r
+// ################################## DEBUG #################################\r
+// All output on as standard\r
+uint32 os_dbg_mask = 0;\r
+// D_MASTER_PRINT ;\r
+// D_ISR_MASTER_PRINT |\r
+// D_STDOUT |\r
+// D_ISR_STDOUT | D_TASK | D_ALARM;\r
+\r
+// ############################### APPLICATION ##############################\r
+// A single, non-configurable application for now\r
+rom_app_t rom_app_list[] = {\r
+ {\r
+ .application_id = APPLICATION_ID_application_1,\r
+ .name = "application_1",\r
+ .trusted = true,\r
+ .StartupHook = NULL,\r
+ .ShutdownHook = NULL,\r
+ .ErrorHook = NULL,\r
+ .isr_mask = 0,\r
+ .scheduletable_mask = 0,\r
+ .alarm_mask = 0,\r
+ .counter_mask = 0,\r
+ .resource_mask = 0,\r
+ .message_mask = 0,\r
+ }\r
+};\r
+\r
+\r
+// ################################# COUNTERS ###############################\r
+counter_obj_t counter_list[] = {\r
+ {\r
+ .name = "OsTick",\r
+ .type = COUNTER_TYPE_HARD,\r
+ .unit = COUNTER_UNIT_NANO,\r
+ .alarm_base.maxallowedvalue = 65535,\r
+ .alarm_base.tickperbase = 1,\r
+ .alarm_base.mincycle = 0,\r
+ },\r
+};\r
+\r
+// ################################## ALARMS ################################\r
+alarm_obj_t alarm_list[] = {\r
+ {\r
+ .name = "ComAlarm",\r
+ .counter = &counter_list[COUNTER_ID_OsTick],\r
+ .counter_id = COUNTER_ID_OsTick,\r
+ .autostart = {\r
+ .active = TRUE,\r
+ .alarmtime = 5,\r
+ .cycletime = 20,\r
+ .appmode_mask = APPLICATION_ID_application_1, //___ARCTICSTUDIO_GENERATOR_TODO___,\r
+ },\r
+ .action = {\r
+ .type = ALARM_ACTION_ACTIVATETASK,\r
+ .task_id = TASK_ID_ComTask,\r
+ },\r
+ },\r
+ {\r
+ .name = "ReadSwAlarm",\r
+ .counter = &counter_list[COUNTER_ID_OsTick],\r
+ .counter_id = COUNTER_ID_OsTick,\r
+ .autostart = {\r
+ .active = TRUE,\r
+ .alarmtime = 10,\r
+ .cycletime = 30,\r
+ .appmode_mask = APPLICATION_ID_application_1, //___ARCTICSTUDIO_GENERATOR_TODO___,\r
+ },\r
+ .action = {\r
+ .type = ALARM_ACTION_ACTIVATETASK,\r
+ .task_id = TASK_ID_ReadSwitches,\r
+ },\r
+ },\r
+};\r
+\r
+\r
+// ################################ RESOURCES ###############################\r
+resource_obj_t resource_list[] = {\r
+ {\r
+ .nr = RES_SCHEDULER,\r
+ .type = RESOURCE_TYPE_STANDARD,\r
+ .ceiling_priority = 0,\r
+ .application_owner_id = 0,\r
+ .task_mask = 0,\r
+ .owner = (-1),\r
+ },\r
+};\r
+\r
+// ############################## STACKS (TASKS) ############################\r
+uint8_t stack_ComTask[PRIO_STACK_SIZE];\r
+uint8_t stack_OsIdle[PRIO_STACK_SIZE];\r
+uint8_t stack_ReadSwitches[PRIO_STACK_SIZE];\r
+uint8_t stack_StartupTask[PRIO_STACK_SIZE];\r
+\r
+// ##################### TIMING PROTECTIONS (TASKS, ISRS) ###################\r
+timing_protection_t timing_protection_list[] = {\r
+};\r
+\r
+rom_pcb_t rom_pcb_list[] = {\r
+// ################################## TASKS #################################\r
+ {\r
+ .pid = TASK_ID_ComTask,\r
+ .name = "ComTask",\r
+ .entry = ComTask,\r
+ .prio = 20,\r
+ .proc_type = PROC_BASIC,\r
+ .stack.size = sizeof stack_ComTask,\r
+ .stack.top = stack_ComTask,\r
+ .autostart = false,\r
+ .application_id = APPLICATION_ID_application_1,\r
+ },\r
+ {\r
+ .pid = TASK_ID_OsIdle,\r
+ .name = "OsIdle",\r
+ .entry = OsIdle,\r
+ .prio = 1,\r
+ .proc_type = PROC_EXTENDED,\r
+ .stack.size = sizeof stack_OsIdle,\r
+ .stack.top = stack_OsIdle,\r
+ .autostart = true,\r
+ .application_id = APPLICATION_ID_application_1,\r
+ },\r
+ {\r
+ .pid = TASK_ID_ReadSwitches,\r
+ .name = "ReadSwitches",\r
+ .entry = ReadSwitches,\r
+ .prio = 10,\r
+ .proc_type = PROC_BASIC,\r
+ .stack.size = sizeof stack_ReadSwitches,\r
+ .stack.top = stack_ReadSwitches,\r
+ .autostart = false,\r
+ .application_id = APPLICATION_ID_application_1,\r
+ },\r
+ {\r
+ .pid = TASK_ID_StartupTask,\r
+ .name = "StartupTask",\r
+ .entry = StartupTask,\r
+ .prio = 100,\r
+ .proc_type = PROC_BASIC,\r
+ .stack.size = sizeof stack_StartupTask,\r
+ .stack.top = stack_StartupTask,\r
+ .autostart = true,\r
+ .application_id = APPLICATION_ID_application_1,\r
+ },\r
+};\r
+\r
+uint8_t pcb_list[PCB_T_SIZE*ARRAY_SIZE(rom_pcb_list)];\r
+\r
+uint8_t os_interrupt_stack[OS_INTERRUPT_STACK_SIZE] __attribute__ ((aligned (0x10)));\r
+\r
+// The vector table\r
+void * intc_vector_tbl[NUMBER_OF_INTERRUPTS_AND_EXCEPTIONS] __attribute__ ((aligned (0x1000),section(".data")))= {\r
+};\r
+\r
+// The type of vector\r
+uint8 intc_type_tbl[NUMBER_OF_INTERRUPTS_AND_EXCEPTIONS] = {\r
+};\r
+\r
+\r
+// ################################## HOOKS ##################################\r
+struct os_conf_global_hooks_s os_conf_global_hooks = {\r
+ .StartupHook = StartupHook,\r
+ .ProtectionHook = ProtectionHook,\r
+ .ShutdownHook = ShutdownHook,\r
+ .ErrorHook = ErrorHook,\r
+ .PreTaskHook = PreTaskHook,\r
+ .PostTaskHook = PostTaskHook,\r
+};\r
+\r
+#include "os_config_funcs.h"
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*
+* Module vendor: Autocore
+* Module version: 1.0.0
+* Specification: Autosar v3.0.1, Final
+*
+*/
+
+\r
+#ifndef OS_CFG_H_\r
+#define OS_CFG_H_\r
+\r
+#define ALARM_USE\r
+
+// Application\r
+#define APPLICATION_ID_application_1 0\r
+#define APPLICATION_CNT 1\r
+\r
+// Alarm Id's\r
+#define ALARM_ID_ComAlarm 0\r
+#define ALARM_ID_ReadSwAlarm 1\r
+\r
+// Counter Id's\r
+#define COUNTER_ID_OsTick 0\r
+\r
+// Event Id's\r
+\r
+// Event masks\r
+\r
+// Isr Id's\r
+\r
+// Resource Id's\r
+\r
+// Task Id's\r
+#define TASK_ID_ComTask 0\r
+#define TASK_ID_OsIdle 1\r
+#define TASK_ID_ReadSwitches 2\r
+#define TASK_ID_StartupTask 3\r
+\r
+// Task entry points\r
+void ComTask( void );\r
+void OsIdle( void );\r
+void ReadSwitches( void );\r
+void StartupTask( void );\r
+\r
+// Stack sizes\r
+#define PRIO_STACK_SIZE 2048\r
+#define OS_INTERRUPT_STACK_SIZE 2048\r
+\r
+// Hooks\r
+#define USE_ERRORHOOK\r
+#define USE_POSTTASKHOOK\r
+#define USE_PRETASKHOOK\r
+#define USE_PROTECTIONHOOK\r
+#define USE_SHUTDOWNHOOK\r
+#define USE_STARTUPHOOK\r
+\r
+#endif /*OS_CFG_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*
+* Module vendor: Autocore
+* Module version: 1.0.0
+* Specification: Autosar v3.0.1, Final
+*
+*/
+
+\r
+// File generated on Mon Aug 17 14:11:26 CEST 2009\r
+// File generated by org.autocore.modules.port.mpc5516\r
+\r
+#include "Port_Cfg.h"\r
+\r
+const uint16_t PortPadConfigData[] = {\r
+ PCR_RESET, /* PCR 0 */\r
+ PCR_RESET, /* PCR 1 */\r
+ PCR_RESET, /* PCR 2 */\r
+ PCR_RESET, /* PCR 3 */\r
+ PCR_RESET, /* PCR 4 */\r
+ PCR_RESET, /* PCR 5 */\r
+ PCR_RESET, /* PCR 6 */\r
+ PCR_RESET, /* PCR 7 */\r
+ PA_FUNC1, /* PCR 8 */\r
+ PA_FUNC1, /* PCR 9 */\r
+ PA_FUNC1, /* PCR 10 */
+ PA_FUNC1,
+ PA_FUNC1,\r
+ PCR_RESET, /* PCR 13 */\r
+ PCR_RESET, /* PCR 14 */\r
+ PCR_RESET, /* PCR 15 */\r
+ PCR_RESET, /* PCR 16 */\r
+ PCR_RESET, /* PCR 17 */\r
+ PCR_RESET, /* PCR 18 */\r
+ PCR_RESET, /* PCR 19 */\r
+ PCR_RESET, /* PCR 20 */\r
+ PCR_RESET, /* PCR 21 */\r
+ PCR_RESET, /* PCR 22 */\r
+ PCR_RESET, /* PCR 23 */\r
+ PCR_RESET, /* PCR 24 */\r
+ PCR_RESET, /* PCR 25 */\r
+ PCR_RESET, /* PCR 26 */\r
+ PCR_RESET, /* PCR 27 */\r
+ PCR_RESET, /* PCR 28 */\r
+ PCR_RESET, /* PCR 29 */\r
+ PCR_RESET, /* PCR 30 */\r
+ PCR_RESET, /* PCR 31 */\r
+ PCR_RESET, /* PCR 32 */\r
+ PCR_RESET, /* PCR 33 */\r
+ PCR_RESET, /* PCR 34 */\r
+ PCR_RESET, /* PCR 35 */\r
+ PCR_RESET, /* PCR 36 */\r
+ PCR_RESET, /* PCR 37 */\r
+ PCR_RESET, /* PCR 38 */\r
+ PCR_RESET, /* PCR 39 */\r
+ PCR_RESET, /* PCR 40 */\r
+ PCR_RESET, /* PCR 41 */\r
+ PCR_RESET, /* PCR 42 */\r
+ PCR_RESET, /* PCR 43 */\r
+ PCR_RESET, /* PCR 44 */\r
+ PCR_RESET, /* PCR 45 */\r
+ PCR_RESET, /* PCR 46 */\r
+ PCR_RESET, /* PCR 47 */\r
+ ( PA_FUNC1 | OBE_ENABLE | SLEW_RATE_MIN | PULL_NONE ), /* PCR 48 : CNTX_A */\r
+ ( PA_FUNC1 | IBE_ENABLE | SLEW_RATE_MIN | PULL_NONE ), /* PCR 49 : CNRX_A */\r
+ PCR_RESET, /* PCR 50 */\r
+ PCR_RESET, /* PCR 51 */\r
+ PCR_RESET, /* PCR 52 */\r
+ PCR_RESET, /* PCR 53 */\r
+ PCR_RESET, /* PCR 54 */\r
+ PCR_RESET, /* PCR 55 */\r
+ PCR_RESET, /* PCR 56 */\r
+ PCR_RESET, /* PCR 57 */\r
+ PCR_RESET, /* PCR 58 */\r
+ PCR_RESET, /* PCR 59 */\r
+ PCR_RESET, /* PCR 60 */\r
+ PCR_RESET, /* PCR 61 */\r
+ PCR_RESET, /* PCR 62 */\r
+ PCR_RESET, /* PCR 63 */\r
+ PCR_RESET, /* PCR 64 */\r
+ PCR_RESET, /* PCR 65 */\r
+ PCR_RESET, /* PCR 66 */\r
+ PCR_RESET, /* PCR 67 */\r
+ PCR_RESET, /* PCR 68 */\r
+ PCR_RESET, /* PCR 69 */\r
+ PCR_RESET, /* PCR 70 */\r
+ PCR_RESET, /* PCR 71 */\r
+ PCR_RESET, /* PCR 72 */\r
+ PCR_RESET, /* PCR 73 */\r
+ PCR_RESET, /* PCR 74 */\r
+ PCR_RESET, /* PCR 75 */\r
+ PCR_RESET, /* PCR 76 */\r
+ PCR_RESET, /* PCR 77 */\r
+ PCR_RESET, /* PCR 78 */\r
+ PCR_RESET, /* PCR 79 */\r
+ PCR_RESET, /* PCR 80 */\r
+ PCR_RESET, /* PCR 81 */\r
+ PCR_RESET, /* PCR 82 */\r
+ PCR_RESET, /* PCR 83 */\r
+ PCR_RESET, /* PCR 84 */\r
+ PCR_RESET, /* PCR 85 */\r
+ PCR_RESET, /* PCR 86 */\r
+ PCR_RESET, /* PCR 87 */\r
+ PCR_RESET, /* PCR 88 */\r
+ PCR_RESET, /* PCR 89 */\r
+ PCR_RESET, /* PCR 90 */\r
+ PCR_RESET, /* PCR 91 */\r
+ PCR_RESET, /* PCR 92 */\r
+ PCR_RESET, /* PCR 93 */\r
+ PCR_RESET, /* PCR 94 */\r
+ PCR_RESET, /* PCR 95 */\r
+ PCR_RESET, /* PCR 96 */\r
+ PCR_RESET, /* PCR 97 */\r
+ PCR_RESET, /* PCR 98 */\r
+ PCR_RESET, /* PCR 99 */\r
+ PCR_RESET, /* PCR 100 */\r
+ PCR_RESET, /* PCR 101 */\r
+ PCR_RESET, /* PCR 102 */\r
+ PCR_RESET, /* PCR 103 */\r
+ PCR_RESET, /* PCR 104 */\r
+ PCR_RESET, /* PCR 105 */\r
+ PCR_RESET, /* PCR 106 */\r
+ PCR_RESET, /* PCR 107 */\r
+ PCR_RESET, /* PCR 108 */\r
+ PCR_RESET, /* PCR 109 */\r
+ PCR_RESET, /* PCR 110 */\r
+ PCR_RESET, /* PCR 111 */\r
+ PCR_RESET, /* PCR 112 */\r
+ PCR_RESET, /* PCR 113 */\r
+ PCR_RESET, /* PCR 114 */\r
+ PCR_RESET, /* PCR 115 */\r
+ PCR_RESET, /* PCR 116 */\r
+ PCR_RESET, /* PCR 117 */\r
+ PCR_RESET, /* PCR 118 */\r
+ PCR_RESET, /* PCR 119 */\r
+ PCR_RESET, /* PCR 120 */\r
+ PCR_RESET, /* PCR 121 */\r
+ PCR_RESET, /* PCR 122 */\r
+ PCR_RESET, /* PCR 123 */\r
+ PCR_RESET, /* PCR 124 */\r
+ PCR_RESET, /* PCR 125 */\r
+ PCR_RESET, /* PCR 126 */\r
+ PCR_RESET, /* PCR 127 */\r
+ PCR_RESET, /* PCR 128 */\r
+ PCR_RESET, /* PCR 129 */\r
+ PCR_RESET, /* PCR 130 */\r
+ PCR_RESET, /* PCR 131 */\r
+ PCR_RESET, /* PCR 132 */\r
+ PCR_RESET, /* PCR 133 */\r
+ PCR_RESET, /* PCR 134 */\r
+ PCR_RESET, /* PCR 135 */\r
+ PCR_RESET, /* PCR 136 */\r
+ PCR_RESET, /* PCR 137 */\r
+ PCR_RESET, /* PCR 138 */\r
+ PCR_RESET, /* PCR 139 */\r
+ PCR_RESET, /* PCR 140 */\r
+ PCR_RESET, /* PCR 141 */\r
+ PCR_RESET, /* PCR 142 */\r
+ PCR_RESET, /* PCR 143 */\r
+ PCR_RESET, /* PCR 144 */\r
+};\r
+\r
+const uint8_t PortOutConfigData[] = {\r
+ GPDO_RESET, /* GPDO 0 */\r
+ GPDO_RESET, /* GPDO 1 */\r
+ GPDO_RESET, /* GPDO 2 */\r
+ GPDO_RESET, /* GPDO 3 */\r
+ GPDO_RESET, /* GPDO 4 */\r
+ GPDO_RESET, /* GPDO 5 */\r
+ GPDO_RESET, /* GPDO 6 */\r
+ GPDO_RESET, /* GPDO 7 */\r
+ GPDO_RESET, /* GPDO 8 */\r
+ GPDO_RESET, /* GPDO 9 */\r
+ GPDO_RESET, /* GPDO 10 */\r
+ GPDO_RESET, /* GPDO 11 */\r
+ GPDO_RESET, /* GPDO 12 */\r
+ GPDO_RESET, /* GPDO 13 */\r
+ GPDO_RESET, /* GPDO 14 */\r
+ GPDO_RESET, /* GPDO 15 */\r
+ GPDO_RESET, /* GPDO 16 */\r
+ GPDO_RESET, /* GPDO 17 */\r
+ GPDO_RESET, /* GPDO 18 */\r
+ GPDO_RESET, /* GPDO 19 */\r
+ GPDO_RESET, /* GPDO 20 */\r
+ GPDO_RESET, /* GPDO 21 */\r
+ GPDO_RESET, /* GPDO 22 */\r
+ GPDO_RESET, /* GPDO 23 */\r
+ GPDO_RESET, /* GPDO 24 */\r
+ GPDO_RESET, /* GPDO 25 */\r
+ GPDO_RESET, /* GPDO 26 */\r
+ GPDO_RESET, /* GPDO 27 */\r
+ GPDO_RESET, /* GPDO 28 */\r
+ GPDO_RESET, /* GPDO 29 */\r
+ GPDO_RESET, /* GPDO 30 */\r
+ GPDO_RESET, /* GPDO 31 */\r
+ GPDO_RESET, /* GPDO 32 */\r
+ GPDO_RESET, /* GPDO 33 */\r
+ GPDO_RESET, /* GPDO 34 */\r
+ GPDO_RESET, /* GPDO 35 */\r
+ GPDO_RESET, /* GPDO 36 */\r
+ GPDO_RESET, /* GPDO 37 */\r
+ GPDO_RESET, /* GPDO 38 */\r
+ GPDO_RESET, /* GPDO 39 */\r
+ GPDO_RESET, /* GPDO 40 */\r
+ GPDO_RESET, /* GPDO 41 */\r
+ GPDO_RESET, /* GPDO 42 */\r
+ GPDO_RESET, /* GPDO 43 */\r
+ GPDO_RESET, /* GPDO 44 */\r
+ GPDO_RESET, /* GPDO 45 */\r
+ GPDO_RESET, /* GPDO 46 */\r
+ GPDO_RESET, /* GPDO 47 */\r
+ GPDO_RESET, /* GPDO 48 */\r
+ GPDO_HIGH, /* GPDO 49 */\r
+ GPDO_RESET, /* GPDO 50 */\r
+ GPDO_RESET, /* GPDO 51 */\r
+ GPDO_RESET, /* GPDO 52 */\r
+ GPDO_RESET, /* GPDO 53 */\r
+ GPDO_RESET, /* GPDO 54 */\r
+ GPDO_RESET, /* GPDO 55 */\r
+ GPDO_RESET, /* GPDO 56 */\r
+ GPDO_RESET, /* GPDO 57 */\r
+ GPDO_RESET, /* GPDO 58 */\r
+ GPDO_RESET, /* GPDO 59 */\r
+ GPDO_RESET, /* GPDO 60 */\r
+ GPDO_RESET, /* GPDO 61 */\r
+ GPDO_RESET, /* GPDO 62 */\r
+ GPDO_RESET, /* GPDO 63 */\r
+ GPDO_RESET, /* GPDO 64 */\r
+ GPDO_RESET, /* GPDO 65 */\r
+ GPDO_RESET, /* GPDO 66 */\r
+ GPDO_RESET, /* GPDO 67 */\r
+ GPDO_RESET, /* GPDO 68 */\r
+ GPDO_RESET, /* GPDO 69 */\r
+ GPDO_RESET, /* GPDO 70 */\r
+ GPDO_RESET, /* GPDO 71 */\r
+ GPDO_RESET, /* GPDO 72 */\r
+ GPDO_RESET, /* GPDO 73 */\r
+ GPDO_RESET, /* GPDO 74 */\r
+ GPDO_RESET, /* GPDO 75 */\r
+ GPDO_RESET, /* GPDO 76 */\r
+ GPDO_RESET, /* GPDO 77 */\r
+ GPDO_RESET, /* GPDO 78 */\r
+ GPDO_RESET, /* GPDO 79 */\r
+ GPDO_RESET, /* GPDO 80 */\r
+ GPDO_RESET, /* GPDO 81 */\r
+ GPDO_RESET, /* GPDO 82 */\r
+ GPDO_RESET, /* GPDO 83 */\r
+ GPDO_RESET, /* GPDO 84 */\r
+ GPDO_RESET, /* GPDO 85 */\r
+ GPDO_RESET, /* GPDO 86 */\r
+ GPDO_RESET, /* GPDO 87 */\r
+ GPDO_RESET, /* GPDO 88 */\r
+ GPDO_RESET, /* GPDO 89 */\r
+ GPDO_RESET, /* GPDO 90 */\r
+ GPDO_RESET, /* GPDO 91 */\r
+ GPDO_RESET, /* GPDO 92 */\r
+ GPDO_RESET, /* GPDO 93 */\r
+ GPDO_RESET, /* GPDO 94 */\r
+ GPDO_RESET, /* GPDO 95 */\r
+ GPDO_RESET, /* GPDO 96 */\r
+ GPDO_RESET, /* GPDO 97 */\r
+ GPDO_RESET, /* GPDO 98 */\r
+ GPDO_RESET, /* GPDO 99 */\r
+ GPDO_RESET, /* GPDO 100 */\r
+ GPDO_RESET, /* GPDO 101 */\r
+ GPDO_RESET, /* GPDO 102 */\r
+ GPDO_RESET, /* GPDO 103 */\r
+ GPDO_RESET, /* GPDO 104 */\r
+ GPDO_RESET, /* GPDO 105 */\r
+ GPDO_RESET, /* GPDO 106 */\r
+ GPDO_RESET, /* GPDO 107 */\r
+ GPDO_RESET, /* GPDO 108 */\r
+ GPDO_RESET, /* GPDO 109 */\r
+ GPDO_RESET, /* GPDO 110 */\r
+ GPDO_RESET, /* GPDO 111 */\r
+ GPDO_RESET, /* GPDO 112 */\r
+ GPDO_RESET, /* GPDO 113 */\r
+ GPDO_RESET, /* GPDO 114 */\r
+ GPDO_RESET, /* GPDO 115 */\r
+ GPDO_RESET, /* GPDO 116 */\r
+ GPDO_RESET, /* GPDO 117 */\r
+ GPDO_RESET, /* GPDO 118 */\r
+ GPDO_RESET, /* GPDO 119 */\r
+ GPDO_RESET, /* GPDO 120 */\r
+ GPDO_RESET, /* GPDO 121 */\r
+ GPDO_RESET, /* GPDO 122 */\r
+ GPDO_RESET, /* GPDO 123 */\r
+ GPDO_RESET, /* GPDO 124 */\r
+ GPDO_RESET, /* GPDO 125 */\r
+ GPDO_RESET, /* GPDO 126 */\r
+ GPDO_RESET, /* GPDO 127 */\r
+ GPDO_RESET, /* GPDO 128 */\r
+ GPDO_RESET, /* GPDO 129 */\r
+ GPDO_RESET, /* GPDO 130 */\r
+ GPDO_RESET, /* GPDO 131 */\r
+ GPDO_RESET, /* GPDO 132 */\r
+ GPDO_RESET, /* GPDO 133 */\r
+ GPDO_RESET, /* GPDO 134 */\r
+ GPDO_RESET, /* GPDO 135 */\r
+ GPDO_RESET, /* GPDO 136 */\r
+ GPDO_RESET, /* GPDO 137 */\r
+ GPDO_RESET, /* GPDO 138 */\r
+ GPDO_RESET, /* GPDO 139 */\r
+ GPDO_RESET, /* GPDO 140 */\r
+ GPDO_RESET, /* GPDO 141 */\r
+ GPDO_RESET, /* GPDO 142 */\r
+};\r
+\r
+const Port_ConfigType PortConfigData =\r
+{\r
+ .padCnt = sizeof(PortPadConfigData),\r
+ .padConfig = PortPadConfigData,\r
+ .outCnt = sizeof(PortOutConfigData),\r
+ .outConfig = PortOutConfigData,\r
+};
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*
+* Module vendor: Autocore
+* Module version: 1.0.0
+* Specification: Autosar v3.0.1, Final
+*
+*/
+
+// File generated on Mon Aug 17 14:11:22 CEST 2009\r
+// File generated by org.autocore.modules.port.mpc5516\r
+\r
+#ifndef PORT_CFG_H_\r
+#define PORT_CFG_H_\r
+\r
+#include "Std_Types.h"\r
+\r
+#define PORT_VERSION_INFO_API STD_ON\r
+#define PORT_DEV_ERROR_DETECT STD_ON\r
+#define PORT_PIN_DIRECTION_CHANGES_ALLOWED STD_ON\r
+\r
+#define BIT0 (1<<15)\r
+#define BIT1 (1<<14)\r
+#define BIT2 (1<<13)\r
+#define BIT3 (1<<12)\r
+#define BIT4 (1<<11)\r
+#define BIT5 (1<<10)\r
+#define BIT6 (1<<9)\r
+#define BIT7 (1<<8)\r
+#define BIT8 (1<<7)\r
+#define BIT9 (1<<6)\r
+#define BIT10 (1<<5)\r
+#define BIT11 (1<<4)\r
+#define BIT12 (1<<3)\r
+#define BIT13 (1<<2)\r
+#define BIT14 (1<<1)\r
+#define BIT15 (1<<0)\r
+\r
+#define WPE_BIT BIT14\r
+#define WPS_BIT BIT15\r
+#define SRC0 BIT12\r
+#define SRC1 BIT13\r
+\r
+#define PULL_UP (WPE_BIT|WPS_BIT)\r
+#define PULL_DOWN (WPE_BIT)\r
+#define PULL_NONE 0\r
+#define SLEW_RATE_MIN 0\r
+#define SLEW_RATE_MED BIT13\r
+#define SLEW_RATE_MAX (BIT12|BIT13)\r
+#define HYS_ENABLE BIT11\r
+#define ODE_ENABLE BIT10\r
+#define IBE_ENABLE BIT7\r
+#define OBE_ENABLE BIT6\r
+#define PA_IO (0)\r
+#define PA_FUNC0 (0)\r
+#define PA_FUNC1 (BIT5)\r
+#define PA_FUNC2 (BIT4)\r
+#define PA_FUNC3 (BIT4|BIT5)\r
+#define PA_FUNC4 (BIT3)\r
+\r
+#define PCR_RESET (0)\r
+#define GPDO_RESET (0)\r
+\r
+#define GPDO_HIGH (1)\r
+\r
+// Could also use an enum to name the pins here\r
+typedef int Port_PinType;\r
+\r
+typedef struct\r
+{\r
+ uint16_t padCnt;\r
+ const uint16_t *padConfig;\r
+ uint16_t outCnt;\r
+ const uint8_t *outConfig;\r
+// uint16_t inCnt;\r
+// const uint8_t *inConfig;\r
+} Port_ConfigType;\r
+\r
+extern const Port_ConfigType PortConfigData;\r
+\r
+#endif /*PORT_CFG_H_*/\r
--- /dev/null
+
+# Our object files
+obj-y += switch_node_helpers.o
+obj-y += switch.o
+obj-y += Rte.o
+obj-y += Tasks.o
+obj-y += Hooks.o
+
+inc-y += $(ROOTDIR)/system/kernel/$(objdir)
+inc-y += $(ROOTDIR)/system/kernel/include
+
+# OS object files.
+obj-y += Os_Cfg.o
+# Board object files
+include $(ROOTDIR)/boards/board_common.mk
+
+ABSDIR := $(subst $(TOPDIR)/,,$(CURDIR))
+
+# The more precise configuration, the higher preceedance.
+VPATH := ../config/$(BOARDDIR) ../config $(VPATH)
+inc-y := ../config/$(BOARDDIR) ../config $(inc-y)
+
+inc-y += $(ROOTDIR)/system/kernel/$(objdir)
+
+#TODO: Remove?, Build other way?
+VPATH += $(ROOTDIR)/$(SUBDIR)/Rte
+inc-y += $(ROOTDIR)/$(SUBDIR)/Rte
+VPATH += $(ROOTDIR)/components/switch
+inc-y += $(ROOTDIR)/components/switch
+
+
+# libs needed by us
+libitem-y += $(ROOTDIR)/libs/libkernel_$(ARCH_MCU).a
+
+#linkfile
+ldcmdfile-y = -T $(ROOTDIR)/$(ARCH_PATH-y)/scripts/linkscript_gcc.ldf
+
+# What I want to build
+build-exe-y = switch_node.elf
+
+
+
+
+
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+#include "Adc.h"\r
+#include "Com.h"\r
+#include "Trace.h"\r
+#include "RTE_switch.h"\r
+\r
+#define SWITCH_LOW_THRESHOLD 100\r
+\r
+/*\r
+ * ADC callback. This function is called each time the switches are read.\r
+ */\r
+static uint8 ModeSwitchCounter = 0; // Add some delay to the mode switch\r
+static Adc_ValueGroupType switchValues[ADC_NBR_OF_SWITCH_CHANNELS];\r
+void switch_node_switches_callback(void) {\r
+\r
+ if (E_OK == Adc_ReadGroup(ADC_SWITCHES, switchValues)) {\r
+\r
+ if (switchValues[ADC_SWITCH_RED] <= SWITCH_LOW_THRESHOLD) {\r
+ switch_handle_switch1();\r
+ } else if (switchValues[ADC_SWITCH_BLACK] <= SWITCH_LOW_THRESHOLD) {\r
+ switch_handle_switch2();\r
+ }\r
+\r
+ } else {\r
+ DEBUG(DEBUG_HIGH, "Switches failed!\n");\r
+ }\r
+}\r
+\r
+\r
+/*\r
+ * Read values from Adc channels connected to potentiometers.\r
+ * Nothing is done with their values though.
+ */\r
+static Adc_ValueGroupType potentiometerValues[ADC_NBR_OF_POTENTIOMETER_CHANNELS];\r
+void switch_node_potentiometers_callback(void){\r
+\r
+ if (E_OK == Adc_ReadGroup(ADC_POTENTIOMETERS, potentiometerValues)) {\r
+ DEBUG(DEBUG_MEDIUM, "Potentiometers read successfully! %d %d\n", potentiometerValues[ADC_POTENTIOMETER_0], potentiometerValues[ADC_POTENTIOMETER_1]);\r
+\r
+ } else {\r
+ DEBUG(DEBUG_HIGH, "Potentiometers failed!\n");\r
+ }\r
+}\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef ADC_H_\r
+#define ADC_H_\r
+\r
+#include "Std_Types.h"\r
+#include "Dma.h"\r
+#include "Adc_Cfg.h"\r
+\r
+typedef uint16_t Adc_ValueGroupType;\r
+\r
+typedef union\r
+{\r
+ vuint32_t R;\r
+ struct\r
+ {\r
+ vuint32_t EOQ:1;\r
+ vuint32_t PAUSE:1;\r
+ vuint32_t :4;\r
+ vuint32_t BN:1;\r
+ vuint32_t CAL:1;\r
+ vuint32_t MESSAGE_TAG:4;\r
+ vuint32_t LST:2;\r
+ vuint32_t TSR:1;\r
+ vuint32_t FMT:1;\r
+ vuint32_t CHANNEL_NUMBER:8;\r
+ vuint32_t :8;\r
+ } B;\r
+}Adc_CommandType;\r
+\r
+typedef enum\r
+{\r
+ ADC_SYSTEM_CLOCK\r
+}Adc_ClockSourceType;\r
+\r
+typedef enum\r
+{\r
+ ADC_SYSTEM_CLOCK_DISABLED,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_1,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_2,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_4,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_6,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_8,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_10,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_12,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_14,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_16,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_18,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_20,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_22,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_24,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_26,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_28,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_30,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_32,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_34,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_36,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_38,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_40,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_42,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_44,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_46,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_48,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_50,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_52,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_54,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_56,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_58,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_60,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_62,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_64,\r
+}Adc_PrescaleType;\r
+\r
+typedef struct\r
+{\r
+ Adc_ClockSourceType clockSource;\r
+ uint8_t hwUnitId;\r
+ Adc_PrescaleType adcPrescale;\r
+}Adc_HWConfigurationType;\r
+\r
+typedef enum\r
+{\r
+ ADC_REFERENCE_VOLTAGE_GROUND,\r
+ ADC_REFERENCE_VOLTAGE_5V,\r
+}Adc_VoltageSourceType;\r
+\r
+typedef enum\r
+{\r
+ ADC_CONVERSION_TIME_2_CLOCKS,\r
+ ADC_CONVERSION_TIME_8_CLOCKS,\r
+ ADC_CONVERSION_TIME_64_CLOCKS,\r
+ ADC_CONVERSION_TIME_128_CLOCKS\r
+}Adc_ConversionTimeType;\r
+\r
+typedef enum\r
+{\r
+ ADC_CALIBRATION_DISABLED,\r
+ ADC_CALIBRATION_ENABLED\r
+}Adc_CalibrationType;\r
+\r
+typedef enum\r
+{\r
+ ADC_RESOLUTION_12BITS\r
+}Adc_ResolutionType;\r
+\r
+/* Channel definitions. */\r
+typedef struct\r
+{\r
+ Adc_ConversionTimeType adcChannelConvTime;\r
+ Adc_VoltageSourceType adcChannelRefVoltSrcLow;\r
+ Adc_VoltageSourceType adcChannelRefVoltSrcHigh;\r
+ Adc_ResolutionType adcChannelResolution;\r
+ Adc_CalibrationType adcChannelCalibrationEnable;\r
+}Adc_ChannelConfigurationType;\r
+\r
+typedef enum\r
+{\r
+ ADC_ACCESS_MODE_SINGLE,\r
+ ADC_ACCESS_MODE_STREAMING\r
+}Adc_GroupAccessModeType;\r
+\r
+typedef enum\r
+{\r
+ ADC_TRIGG_SRC_HW,\r
+ ADC_TRIGG_SRC_SW,\r
+}Adc_TriggerSourceType;\r
+\r
+typedef enum\r
+{\r
+ ADC_NO_HW_TRIG,\r
+ ADC_HW_TRIG_BOTH_EDGES,\r
+ ADC_HW_TRIG_FALLING_EDGE,\r
+ ADC_HW_TRIG_RISING_EDGE,\r
+}Adc_HwTriggerSignalType;\r
+\r
+/* TODO list timer sources here. */\r
+typedef enum\r
+{\r
+ ADC_NO_TIMER,\r
+}Adc_HwTriggerTimerType;\r
+\r
+typedef enum\r
+{\r
+ ADC_NO_STREAMING,\r
+ ADC_STREAM_BUFFER_CIRCULAR,\r
+ ADC_STREAM_BUFFER_LINEAR,\r
+}Adc_StreamBufferModeType;\r
+\r
+typedef uint16_t Adc_StreamNumSampleType;\r
+\r
+typedef enum\r
+{\r
+ ADC_CONV_MODE_DISABLED,\r
+ ADC_CONV_MODE_ONESHOT = 1,\r
+ ADC_CONV_MODE_CONTINOUS = 9,\r
+}Adc_GroupConvModeType;\r
+\r
+typedef enum\r
+{\r
+ ADC_IDLE,\r
+ ADC_BUSY,\r
+ ADC_COMPLETED,\r
+ ADC_STREAM_COMPLETED,\r
+}Adc_StatusType;\r
+\r
+typedef struct\r
+{\r
+ uint8 notifictionEnable;\r
+ Adc_ValueGroupType *resultBufferPtr;\r
+ Adc_StatusType groupStatus;\r
+}Adc_GroupStatus;\r
+\r
+\r
+typedef struct\r
+{\r
+ Adc_GroupAccessModeType accessMode;\r
+ Adc_GroupConvModeType conversionMode;\r
+ Adc_TriggerSourceType triggerSrc;\r
+ Adc_HwTriggerSignalType hwTriggerSignal;\r
+ Adc_HwTriggerTimerType hwTriggerTimer;\r
+ void (*groupCallback)(void);\r
+ Adc_StreamBufferModeType streamBufferMode;\r
+ Adc_StreamNumSampleType streamNumSamples;\r
+ const Adc_ChannelType *channelList;\r
+ Adc_ValueGroupType *resultBuffer;\r
+ Adc_CommandType *commandBuffer;\r
+ Adc_ChannelType numberOfChannels;\r
+ Adc_GroupStatus *status;\r
+ Dma_ChannelType dmaCommandChannel;\r
+ Dma_ChannelType dmaResultChannel;\r
+ const struct tcd_t *groupDMACommands;\r
+ const struct tcd_t *groupDMAResults;\r
+}Adc_GroupDefType;\r
+\r
+\r
+/* Det error that the adc can produce. */\r
+typedef enum\r
+{\r
+ ADC_E_UNINIT = 0x0A,\r
+ ADC_E_BUSY = 0x0B,\r
+ ADC_E_IDLE = 0x0C,\r
+ ADC_E_ALREADY_INITIALIZED = 0x0D,\r
+ ADC_E_PARAM_CONFIG = 0x0E,\r
+ ADC_E_PARAM_GROUP = 0x15,\r
+ ADC_E_WRONG_CONV_MODE = 0x16,\r
+ ADC_E_WRONG_TRIGG_SRC = 0x17,\r
+ ADC_E_NOTIF_CAPABILITY = 0x18,\r
+ ADC_E_BUFFER_UNINIT = 0x19\r
+}Adc_DetErrorType;\r
+\r
+/* API service ID's */\r
+typedef enum\r
+{\r
+ ADC_INIT_ID = 0x00,\r
+ ADC_DEINIT_ID = 0x01,\r
+ ADC_STARTGROUPCONVERSION_ID = 0x02,\r
+ ADC_STOPGROUPCONVERSION_ID = 0x03,\r
+ ADC_READGROUP_ID = 0x04,\r
+ ADC_ENABLEHARDWARETRIGGER_ID = 0x05,\r
+ ADC_DISBALEHARDWARETRIGGER_ID = 0x06,\r
+ ADC_ENABLEGROUPNOTIFICATION_ID = 0x07,\r
+ ADC_DISABLEGROUPNOTIFICATION_ID = 0x08,\r
+ ADC_GETGROUPSTATUS_ID = 0x09,\r
+ ADC_GETVERSIONINFO_ID = 0x0A,\r
+ ADC_GETSTREAMLASTPOINTER_ID = 0x0B,\r
+ ADC_SETUPRESULTBUFFER_ID = 0x0C,\r
+}Adc_APIServiceIDType;\r
+\r
+\r
+typedef struct\r
+{\r
+ const Adc_HWConfigurationType* hwConfigPtr;\r
+ const Adc_ChannelConfigurationType* channelConfigPtr;\r
+ const uint16_t nbrOfChannels;\r
+ const Adc_GroupDefType* groupConfigPtr;\r
+ const uint16_t nbrOfGroups;\r
+}Adc_ConfigType;\r
+\r
+extern const Adc_ConfigType AdcConfig [];\r
+\r
+/* Function interface. */\r
+Std_ReturnType Adc_Init (const Adc_ConfigType *ConfigPtr);\r
+#if (ADC_DEINIT_API == STD_ON)\r
+Std_ReturnType Adc_DeInit (const Adc_ConfigType *ConfigPtr);\r
+#endif\r
+Std_ReturnType Adc_SetupResultBuffer (Adc_GroupType group, Adc_ValueGroupType *bufferPtr);\r
+#if (ADC_ENABLE_START_STOP_GROUP_API == STD_ON)\r
+void Adc_StartGroupConversion (Adc_GroupType group);\r
+//void Adc_StopGroupConversion (Adc_GroupType group);\r
+#endif\r
+#if (ADC_READ_GROUP_API == STD_ON)\r
+Std_ReturnType Adc_ReadGroup (Adc_GroupType group, Adc_ValueGroupType *dataBufferPtr);\r
+#endif\r
+#if (ADC_GRP_NOTIF_CAPABILITY == STD_ON)\r
+void Adc_EnableGroupNotification (Adc_GroupType group);\r
+void Adc_DisableGroupNotification (Adc_GroupType group);\r
+#endif\r
+Adc_StatusType Adc_GetGroupStatus (Adc_GroupType group);\r
+\r
+#endif /*ADC_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef BYTEORDER_H_\r
+#define BYTEORDER_H_\r
+\r
+// NOTE!\r
+// Implements only big endian stuff\r
+\r
+//#define BE_TO_CPU_32(x) ((uint8_t*)(x))[0] + (((uint8_t*)(x))[1]<<8) + (((uint8_t*)(x))[2]<<16) + (((uint8_t*)(x))[3]<<24)\r
+//#define BIG_ENDIAN\r
+\r
+// a,b,c,d -> d,c,b,a\r
+#define bswap32(x) (((uint32)(x) >> 24) | (((uint32)(x) >> 8) & 0xff00) | (((uint32)(x) & 0xff00 ) << 8) | (((uint32)(x) & 0xff) << 24) )\r
+#define bswap16(x) (((uint16)(x) >> 8) | (((uint16)(x) & 0xff) << 8))\r
+\r
+#if 0 //defined(BIG_ENDIAN)\r
+#define cpu_to_le32(_x) bswap32(_x)\r
+#define cpu_to_be32(_x)\r
+#define le32_to_cpu(_x)\r
+#define be32_to_cpu(_x)\r
+#endif\r
+\r
+\r
+#endif /*BYTEORDER_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef CAN_H_\r
+#define CAN_H_\r
+\r
+#define CAN_VENDOR_ID 1\r
+#define CAN_MODULE_ID MODULE_ID_CAN\r
+#define CAN_AR_MAJOR_VERSION 2\r
+#define CAN_AR_MINOR_VERSION 2\r
+#define CAN_AR_PATCH_VERSION 2\r
+#define CAN_SW_MAJOR_VERSION 0\r
+#define CAN_SW_MINOR_VERSION 1\r
+#define CAN_SW_PATCH_VERSION 0\r
+\r
+#define CAN_E_PARAM_POINTER 0x01\r
+#define CAN_E_PARAM_HANDLE 0x02\r
+#define CAN_E_PARAM_DLC 0x03\r
+#define CAN_E_PARAM_CONTROLLER 0x04\r
+// API service used without initialization\r
+#define CAN_E_UNINIT 0x05\r
+// Init transition for current mode\r
+#define CAN_E_TRANSITION 0x06\r
+\r
+#define CAN_E_TIMEOUT 0x10 // Should be defined by DEM\r
+\r
+\r
+#include "Std_Types.h"\r
+#include "CanIf_Types.h"\r
+#include "ComStack_Types.h"\r
+#include "Mcu.h"\r
+\r
+typedef struct {\r
+ uint32 txSuccessCnt;\r
+ uint32 rxSuccessCnt;\r
+ uint32 txErrorCnt;\r
+ uint32 rxErrorCnt;\r
+ uint32 boffCnt;\r
+ uint32 fifoOverflow;\r
+ uint32 fifoWarning;\r
+} Can_EcoreStatisticsType;\r
+\r
+\r
+// uint16: if only Standard IDs are used\r
+// uint32: if also Extended IDs are used\r
+typedef uint32 Can_IdType;\r
+\r
+/* Good things to know\r
+ * L-PDU - Link PDU\r
+ *\r
+ *\r
+ */\r
+\r
+typedef struct Can_PduType_s {\r
+ // the CAN ID, 29 or 11-bit\r
+ Can_IdType id;\r
+ // Length, max 8 bytes\r
+ uint8 length;\r
+ // data ptr\r
+ uint8 *sdu;\r
+ // private data for CanIf,just save and use for callback\r
+ PduIdType swPduHandle;\r
+} Can_PduType;\r
+\r
+\r
+typedef enum {\r
+ CAN_T_START,\r
+ CAN_T_STOP,\r
+ CAN_T_SLEEP,\r
+ CAN_T_WAKEUP\r
+} Can_StateTransitionType;\r
+\r
+typedef enum {\r
+ CAN_OK,\r
+ CAN_NOT_OK,\r
+ CAN_BUSY,\r
+// CAN_WAKEUP, // Removed in 3.0\r
+} Can_ReturnType;\r
+\r
+/* Error from CAN controller */\r
+typedef union {\r
+ volatile uint32_t R;\r
+ struct {\r
+ volatile uint32_t:24;\r
+ volatile uint32_t BIT1ERR:1;\r
+ volatile uint32_t BIT0ERR:1;\r
+ volatile uint32_t ACKERR:1;\r
+ volatile uint32_t CRCERR:1;\r
+ volatile uint32_t FRMERR:1;\r
+ volatile uint32_t STFERR:1;\r
+ volatile uint32_t TXWRN:1;\r
+ volatile uint32_t RXWRN:1;\r
+ } B;\r
+ } Can_EcoreErrorType;\r
+\r
+// Each controller has 32 hth's, so the division of 32 will give the\r
+// controller.\r
+#define GET_CANCONTROLLER(a) (a / HTH_DIVIDER)\r
+\r
+#include "Can_Cfg.h"\r
+\r
+void Can_Init( const Can_ConfigType *Config );\r
+void Can_DeInit();\r
+\r
+#if ( CAN_VERSION_INFO_API == STD_ON )\r
+#define Can_GetVersionInfo(_vi) STD_GET_VERSION_INFO(_vi,CAN)\r
+#endif\r
+\r
+void Can_InitController( uint8 controller, const Can_ControllerConfigType *config);\r
+Can_ReturnType Can_SetControllerMode( uint8 Controller, Can_StateTransitionType transition );\r
+void Can_DisableControllerInterrupts( uint8 controller );\r
+void Can_EnableControllerInterrupts( uint8 controller );\r
+// Hth - for Flexcan, the hardware message box number... .We don't care\r
+\r
+\r
+Can_ReturnType Can_Write( Can_EcoreHTHType hth, Can_PduType *pduInfo );\r
+\r
+void Can_Cbk_CheckWakeup( uint8 controller );\r
+void Can_MainFunction_Write( void );\r
+void Can_MainFunction_Read( void );\r
+void Can_MainFunction_BusOff( void );\r
+void Can_MainFunction_Wakeup( void );\r
+\r
+void Can_EcoreGetStatistics( uint8 controller, Can_EcoreStatisticsType * stat);\r
+\r
+#endif /*CAN_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef CANIF_H_
+#define CANIF_H_
+
+// Added by Mattias
+#include "PduR.h"
+#include "Com.h"
+
+
+#include "Det.h"
+#include "CanIf_Types.h"
+#include "CanIf_Cfg.h"
+
+#define CANIF_VENDOR_ID 1
+#define CANIF_MODULE_ID MODULE_ID_CANIF
+#define CANIF_AR_MAJOR_VERSION 3
+#define CANIF_AR_MINOR_VERSION 0
+#define CANIF_AR_PATCH_VERSION 2
+#define CANIF_SW_MAJOR_VERSION 0
+#define CANIF_SW_MINOR_VERSION 1
+#define CANIF_SW_PATCH_VERSION 0
+
+// Service IDs
+#define CANIF_INIT_ID 0x01
+#define CANIF_INIT_CONTROLLER_ID 0x02
+#define CANIF_SET_CONTROLLER_MODE_ID 0x03
+#define CANIF_GET_CONTROLLER_MODE_ID 0x04
+#define CANIF_TRANSMIT_ID 0x05
+#define CANIF_READTXPDUDATA_ID 0x06
+#define CANIF_READTXNOTIFSTATUS_ID 0x07
+#define CANIF_READRXNOTIFSTATUS_ID 0x08
+#define CANIF_SETPDUMODE_ID 0x09
+#define CANIF_GETPDUMODE_ID 0x0A
+#define CANIF_SETDYNAMICTX_ID 0x0C
+#define CANIF_SET_TRANSCEIVERMODE_ID 0x0D
+#define CANIF_GET_TRANSCEIVERMODE_ID 0x0E
+#define CANIF_GET_TRCVMODEREASON_ID 0x0F
+#define CANIF_SET_TRANSCEIVERWAKEMODE_ID 0x10
+#define CANIF_CHECKWAKEUP_ID 0x11
+#define CANIF_CHECKVALIDATION_ID 0x12
+#define CANIF_TXCONFIRMATION_ID 0x13
+#define CANIF_RXINDICATION_ID 0x14
+#define CANIF_CANCELTXCONFIRMATION_ID 0x15
+#define CANIF_CONTROLLER_BUSOFF_ID 0x16
+
+#define CANIF_SETWAKEUPEVENT_ID 0x40
+#define CANIF_ECOREERROR_ID 0x41
+
+void CanIf_Init(const CanIf_ConfigType *ConfigPtr);
+
+void CanIf_InitController(uint8 Controller,
+ uint8 ConfigurationIndex);
+
+Std_ReturnType CanIf_SetControllerMode(uint8 Controller,
+ CanIf_ControllerModeType ControllerMode);
+
+Std_ReturnType CanIf_GetControllerMode(uint8 Controller,
+ CanIf_ControllerModeType *ControllerModePtr);
+
+Std_ReturnType CanIf_Transmit(PduIdType CanTxPduId,
+ const PduInfoType *PduInfoPtr);
+
+#if ( CANIF_READRXPDU_DATA_API == STD_ON )
+Std_ReturnType CanIf_ReadRxPduData(PduIdType CanRxPduId,
+ PduInfoType *PduInfoPtr);
+#endif
+
+#if ( CANIF_READTXPDU_NOTIFY_STATUS_API == STD_ON )
+CanIf_NotifStatusType CanIf_ReadTxNotifStatus(PduIdType CanTxPduId);
+#endif
+
+#if ( CANIF_READTXPDU_NOTIFY_STATUS_API == STD_ON )
+CanIf_NotifStatusType CanIf_ReadRxNotifStatus(PduIdType CanRxPduId);
+#endif
+
+Std_ReturnType CanIf_SetPduMode( uint8 Controller, CanIf_ChannelSetModeType PduModeRequest );
+Std_ReturnType CanIf_GetPduMode( uint8 Controller, CanIf_ChannelGetModeType *PduModePtr );
+
+#if ( CANIF_SETDYNAMICTXID_API == STD_ON )
+void CanIf_SetDynamicTxId( PduIdType CanTxPduId, Can_IdType CanId );
+#endif
+
+#if ( CANIF_TRANSCEIVER_API == STD_ON )
+Std_ReturnType CanIf_SetTransceiverMode( uint8 Transceiver, CanIf_TransceiverModeType TransceiverMode );
+Std_ReturnType CanIf_GetTransceiverMode( uint8 Transceiver, CanIf_TransceiverModeType *TransceiverModePtr );
+Std_ReturnType CanIf_GetTrcvWakeupReason( uint8 Transceiver, CanIf_TrcvWakeupReasonType *TrcvWuReasonPtr );
+Std_ReturnType CanIf_SetTransceiverWakeupMode( uint8 Transceiver, CanIf_TrcvWakeupModeType *TrcvWakeupMode );
+#endif
+
+#if ( CANIF_WAKEUP_EVENT_API == STD_ON )
+Std_ReturnType CanIf_CheckWakeup( EcuM_WakeupSourceType WakeupSource );
+Std_ReturnType CanIf_CheckValidation( EcuM_WakeupSourceType WakeupSource );
+#endif
+
+#if ( CANIF_VERSION_INFO_API == STD_ON )
+#define CanIf_GetVersionInfo(_vi) STD_GET_VERSION_INFO(_vi,CANIF)
+#endif
+
+#endif /*CANIF_H_*/
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef CANIF_CBK_H_\r
+#define CANIF_CBK_H_\r
+\r
+void CanIf_TxConfirmation( PduIdType canTxPduId );\r
+void CanIf_RxIndication( uint8 Hrh, Can_IdType CanId, uint8 CanDlc, const uint8 *CanSduPtr );\r
+\r
+#if ( CANIF_TRANSMIT_CANCELLATION == STD_ON )\r
+void CanIf_CancelTxConfirmation( const Can_PduType *PduInfoPtr );\r
+#endif\r
+\r
+void CanIf_ControllerBusOff( uint8 Controller );\r
+void CanIf_SetWakeupEvent( uint8 Controller );\r
+\r
+/* Ecore extensions */\r
+void CanIf_EcoreError( uint8 Controller, Can_EcoreErrorType Error );\r
+\r
+#endif /*CANIF_CBK_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef CANIF_TYPES_H_
+#define CANIF_TYPES_H_
+
+#include "ComStack_Types.h"
+
+// API service with wrong parameter
+#define CANIF_E_PARAM_CANID 10
+#define CANIF_E_PARAM_DLC 11
+#define CANIF_E_PARAM_HRH 12
+#define CANIF_E_PARAM_CHANNEL 13
+#define CANIF_E_PARAM_CONTROLLER 14
+#define CANIF_E_PARAM_WAKEUPSOURCE 15
+
+#define CANIF_E_PARAM_HTH 17
+#define CANIF_E_PARAM_LPDU 18
+#define CANIF_E_PARAM_CONTROLLER_MODE 19
+
+#define CANIF_E_PARAM_POINTER 20
+#define CANIF_E_UNINIT 30
+#define CANIF_E_NOK_NOSUPPORT 40
+#define CANIF_TRCV_E_TRCV_NOT_STANDBY 60
+#define CANIF_TRCV_E_TRCV_NOT_NORMAL 70
+#define CANIF_E_INVALID_TXPDUID 80
+#define CANIF_E_INVALID_RXPDUID 90
+
+typedef enum {
+ // UNINIT mode. Default mode of the CAN driver and all
+ // CAN controllers connected to one CAN network after
+ // power on.
+ CANIF_CS_UNINIT = 0,
+
+ // STOPPED mode. At least one of all CAN controllers
+ // connected to one CAN network are halted and does
+ // not operate on the bus.
+ CANIF_CS_STOPPED,
+
+ // STARTED mode. All CAN controllers connected to
+ // one CAN network are started by the CAN driver and
+ // in full-operational mode.
+ CANIF_CS_STARTED,
+
+ // SLEEP mode. At least one of all CAN controllers
+ // connected to one CAN network are set into the
+ // SLEEP mode and can be woken up by request of the
+ // CAN driver or by a network event (must be supported
+ // by CAN hardware)
+ CANIF_CS_SLEEP,
+} CanIf_ControllerModeType;
+
+// Status of the PDU channel group. Current mode of the channel defines its
+// transmit or receive activity. Communication direction (transmission and/or
+// reception) of the channel can be controlled separately or together by upper
+// layers.
+typedef enum {
+ // Channel shall be set to the offline mode
+ // => no transmission and reception
+ CANIF_SET_OFFLINE = 0,
+
+ // Receive path of the corresponding channel
+ // shall be disabled
+ CANIF_SET_RX_OFFLINE,
+
+ // Receive path of the corresponding channel
+ // shall be enabled
+ CANIF_SET_RX_ONLINE,
+
+ // Transmit path of the corresponding channel
+ // shall be disabled
+ CANIF_SET_TX_OFFLINE,
+
+ // Transmit path of the corresponding channel
+ // shall be enabled
+ CANIF_SET_TX_ONLINE,
+
+ // Channel shall be set to online mode
+ // => full operation mode
+ CANIF_SET_ONLINE,
+
+ // Transmit path of the corresponding channel
+ // shall be set to the offline active mode
+ // => notifications are processed but transmit
+ // requests are blocked.
+ CANIF_SET_TX_OFFLINE_ACTIVE,
+} CanIf_ChannelSetModeType;
+
+
+typedef enum {
+ // Channel is in the offline mode ==> no transmission or reception
+ CANIF_GET_OFFLINE = 0,
+ // Receive path of the corresponding channel is enabled and
+ // transmit path is disabled
+ CANIF_GET_RX_ONLINE,
+ // Transmit path of the corresponding channel is enabled and
+ // receive path is disabled
+ CANIF_GET_TX_ONLINE,
+ // Channel is in the online mode ==> full operation mode
+ CANIF_GET_ONLINE,
+ // Transmit path of the corresponding channel is in
+ // the offline mode ==> transmit notifications are processed but
+ // transmit requests are blocked. The receiver path is disabled.
+ CANIF_GET_OFFLINE_ACTIVE,
+ // Transmit path of the corresponding channel is in the offline
+ // active mode ==> transmit notifications are processed but transmit
+ // requests are blocked. The receive path is enabled.
+ CANIF_GET_OFFLINE_ACTIVE_RX_ONLINE
+
+} CanIf_ChannelGetModeType;
+
+typedef enum {
+ // No transmit or receive event occurred for
+ // the requested L-PDU.
+ CANIF_NO_NOTIFICATION = 0,
+ // The requested Rx/Tx CAN L-PDU was
+ // successfully transmitted or received.
+ CANIF_TX_RX_NOTIFICATION,
+
+} CanIf_NotifStatusType;
+
+typedef enum {
+ // Transceiver mode NORMAL
+ CANIF_TRCV_MODE_NORMAL = 0,
+ // Transceiver mode STANDBY
+ CANIF_TRCV_MODE_STANDBY,
+ //Transceiver mode SLEEP
+ CANIF_TRCV_MODE_SLEEP
+} CanIf_TransceiverModeType;
+
+typedef enum {
+ // Due to an error wake up reason was not detected.
+ // This value may only be reported when error was
+ // reported to DEM before.
+ CANIF_TRCV_WU_ERROR = 0,
+ // The transceiver does not support any information
+ // for the wakeup reason.
+ CANIF_TRCV_WU_NOT_SUPPORTED,
+ // The transceiver has detected, that the network has
+ // caused the wake up of the ECU
+ CANIF_TRCV_WU_BY_BUS,
+ // The transceiver detected, that the network has woken
+ // the ECU via a request to NORMAL mode
+ CANIF_TRCV_WU_INTERNALLY,
+ // The transceiver has detected, that the "wake up"
+ // is due to an ECU reset
+ CANIF_TRCV_WU_RESET,
+ // The transceiver has detected, that the "wake up"
+ // is due to an ECU reset after power on.
+ CANIF_TRCV_WU_POWER_ON
+} CanIf_TrcvWakeupReasonType;
+
+typedef enum {
+ // The notification for wakeup events is enabled
+ // on the addressed network.
+ CANIF_TRCV_WU_ENABLE = 0,
+ // The notification for wakeup events is disabled
+ // on the addressed network.
+ CANIF_TRCV_WU_DISABLE,
+ // A stored wakeup event is cleared on the addressed network
+ CANIF_TRCV_WU_CLEAR
+} CanIf_TrcvWakeupModeType;
+
+#endif /*CANIF_TYPES_H_*/
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef COM_H_\r
+#define COM_H_\r
+\r
+#include "Std_Types.h"\r
+#include "Com_Types.h"\r
+#include "Com_EcoreTypes.h"\r
+\r
+\r
+#ifdef COM_DEV_ERROR_DETECT\r
+#include "Det.h"\r
+#endif\r
+\r
+#include "Com_Cfg.h"\r
+#include "Com_PbCfg.h"\r
+#include "Com_Com.h"\r
+#include "Com_Sched.h"\r
+\r
+const Com_ConfigType * ComConfig;\r
+\r
+ComEcoreConfig_type ComEcoreConfig;\r
+\r
+\r
+\r
+#ifdef COM_DEV_ERROR_DETECT\r
+\r
+#undef DET_REPORTERROR\r
+#define DET_REPORTERROR(_x,_y,_z,_q) Det_ReportError(_x,_y,_z,_q)\r
+\r
+\r
+// Define macro for parameter check.\r
+#define PduIdCheck(PduId,ApiId,...) \\r
+ if (PduId >= ComEcoreConfig.ComNIPdu) { \\r
+ DET_REPORTERROR(COM_MODULE_ID, COM_INSTANCE_ID, ApiId, COM_INVALID_PDU_ID); \\r
+ return __VA_ARGS__; \\r
+ } \\r
+\r
+#define COM_VALIDATE_SIGNAL(SignalId, ApiId, ...) \\r
+ if (ComConfig->ComSignal[SignalId].ComEcoreIsSignalGroup) { \\r
+ DET_REPORTERROR(COM_MODULE_ID, COM_INSTANCE_ID, ApiId, COM_ERROR_SIGNAL_IS_SIGNALGROUP); \\r
+ return __VA_ARGS__; \\r
+ } \\r
+\r
+\r
+#else\r
+\r
+#undef DET_REPORTERROR\r
+#define DET_REPORTERROR(_x,_y,_z,_q)\r
+\r
+#define PduIdCheck(PduId,ApiId,...)\r
+#define COM_VALIDATE_SIGNAL(PduId, ApiId, ...)\r
+#endif\r
+\r
+\r
+#define testBit(source,bit) (*((uint8 *)source + (bit / 8)) & (1 << (bit % 8)))\r
+#define setBit(dest,bit) *((uint8 *)dest + (bit / 8)) |= (1 << (bit % 8))\r
+#define clearBit(dest,bit) *((uint8 *)dest + (bit / 8)) &= ~(1 << (bit % 8))\r
+\r
+#define ComGetSignal(SignalId) \\r
+ const ComSignal_type * Signal = &ComConfig->ComSignal[SignalId]\\r
+\r
+#define ComGetEcoreSignal(SignalId) \\r
+ ComEcoreSignal_type * EcoreSignal = &ComEcoreConfig.ComSignal[SignalId]\\r
+\r
+#define ComGetIPdu(IPduId) \\r
+ const ComIPdu_type *IPdu = &ComConfig->ComIPdu[IPduId]\\r
+\r
+#define ComGetEcoreIPdu(IPduId) \\r
+ ComEcoreIPdu_type *EcoreIPdu = &ComEcoreConfig.ComIPdu[IPduId]\\r
+\r
+#define ComGetGroupSignal(GroupSignalId) \\r
+ const ComGroupSignal_type *GroupSignal = &ComConfig->ComGroupSignal[GroupSignalId]\\r
+\r
+#define ComGetEcoreGroupSignal(GroupSignalId) \\r
+ ComEcoreGroupSignal_type *EcoreGroupSignal = &ComEcoreConfig.ComGroupSignal[GroupSignalId]\\r
+\r
+//-------------------------------------------------------------------\r
+// From OSEK_VDX spec...\r
+//\r
+//typedef uint32 MessageIdentifier;\r
+// TODO: Have no idea here..\r
+//typedef void * ApplicationDataRef;\r
+\r
+\r
+\r
+\r
+\r
+\r
+//-------------------------------------------------------------------\r
+\r
+// From OSEK_VDX\r
+\r
+/* The service SendMessage updates the message object identified by\r
+ * <Message> with the application message referenced by the\r
+ * <DataRef> parameter.\r
+ *\r
+ * Internal communication:\r
+ * The message <Message> is routed to the receiving part of the IL.\r
+ */\r
+// Update 2008-10-30, SendMessage and ReceiveMessage should not be required. ensured by RTE. COM013\r
+//StatusType SendMessage(MessageIdentifier , ApplicationDataRef );\r
+\r
+// The service ReceiveMessage updates the application message\r
+// referenced by <DataRef> with the data in the message object\r
+// identified by <Message>. It resets all flags (Notification classes 1 and\r
+// 3) associated with <Message>.\r
+//StatusType ReceiveMessage ( MessageIdentifier , ApplicationDataRef );\r
+\r
+\r
+// From Autosar\r
+void Com_Init( const Com_ConfigType * ConfigPtr);\r
+void Com_DeInit( void );\r
+\r
+void Com_IpduGroupStart(Com_PduGroupIdType IpduGroupId, boolean Initialize);\r
+void Com_IpduGroupStop(Com_PduGroupIdType IpduGroupId);\r
+\r
+\r
+#endif /*COM_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef COMM_TYPES_H_\r
+#define COMM_TYPES_H_\r
+\r
+typedef enum {\r
+COMM_NO_COMMUNICATION,\r
+COMM_SILENT_COMMUNICATION,\r
+COMM_FULL_COMMUNICATION,\r
+}ComM_ModeType;\r
+\r
+#endif /*COMM_TYPES_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef COMSTACK_TYPES_H_\r
+#define COMSTACK_TYPES_H_\r
+\r
+#include "Std_Types.h"\r
+\r
+// Proposed by Mattias\r
+// We need a place to store the global PDU ids?\r
+#include "ComGlobals.h"\r
+\r
+\r
+// Zero-based integer number\r
+// The size of this global type depends on the maximum\r
+// number of PDUs used within one software module.\r
+// Example :\r
+// If no software module deals with more PDUs that\r
+// 256, this type can be set to uint8.\r
+// If at least one software module handles more than\r
+// 256 PDUs, this type must globally be set to uint16.\r
+\r
+// In order to be able to perform table-indexing within a software\r
+// module, variables of this type shall be zero-based and consecutive.\r
+// There might be several ranges of PduIds in a module, one for each type of\r
+// operation performed within that module (e.g. sending and receiving).\r
+\r
+typedef uint16 PduIdType;\r
+typedef uint16 PduLengthType;\r
+typedef struct {\r
+ uint8 *SduDataPtr; // payload\r
+ PduLengthType SduLength; // length of SDU\r
+} PduInfoType;\r
+\r
+/*\r
+typedef struct {\r
+ P2VAR(uint8,AUTOMATIC,AUTOSAR_COMSTACKDATA) SduDataPtr\r
+ PduLengthType SduLength;\r
+} PduInfoType;\r
+*/\r
+\r
+typedef enum {\r
+ BEFREQ_OK=0,\r
+ BEFREQ_NOT_OK,\r
+ BEFREQ_BUSY,\r
+ BEFREQ_OVFL,\r
+} BufReq_ReturnType;\r
+\r
+// 0x00--0x1e General return types\r
+// 0x1f--0x3c Error notif, CAN\r
+// 0x3d--0x5a Error notif, LIN\r
+// more\r
+typedef uint8 NotifResultType;\r
+\r
+#define NTFRSLT_OK 0\r
+#define NTFRSLT_NOT_OK 1\r
+// TODO, more\r
+\r
+typedef uint8 BusTrcvErrorType;\r
+\r
+\r
+#define BUSTRCV_NO_ERROR 0x00\r
+#define BUSBUSTRCV_E_ERROR 0x01\r
+\r
+\r
+#define COMSTACKTYPE_AR_MINOR_VERSION 1\r
+#define COMSTACKTYPE_AR_MAJOR_VERSION 0\r
+#define COMSTACKTYPE_AR_PATCH_VERSION 0\r
+\r
+typedef uint8 NetworkHandleType;\r
+\r
+#endif /*COMSTACK_TYPES_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef COM_TYPES_H_\r
+#define COM_TYPES_H_\r
+\r
+#include "ComStack_Types.h"\r
+#include "Com_Cfg.h"\r
+\r
+typedef uint8 Com_PduGroupIdType;\r
+typedef uint16 Com_SignalIdType;\r
+typedef uint8 Com_SignalGroupIdType;\r
+\r
+typedef enum {\r
+ IMMEDIATE,\r
+ DEFERRED,\r
+} Com_IPduSignalProcessingMode;\r
+\r
+typedef enum {\r
+ RECEIVE,\r
+ SEND\r
+} Com_IPduDirection;\r
+\r
+typedef enum {\r
+ BOOLEAN,\r
+ UINT8,\r
+ UINT16,\r
+ UINT32,\r
+ UINT8_N,\r
+ SINT8,\r
+ SINT16,\r
+ SINT32\r
+} Com_SignalType;\r
+\r
+typedef enum {\r
+ PENDING,\r
+ TRIGGERED,\r
+} ComTransferProperty_type;\r
+\r
+typedef enum {\r
+ DIRECT,\r
+ MIXED,\r
+ NONE,\r
+ PERIODIC,\r
+} ComTxModeMode_type;\r
+\r
+\r
+typedef enum {\r
+ ALWAYS,\r
+ MASKED_NEW_DIFFERS_MASKED_OLD,\r
+ MASKED_NEW_DIFFERS_X,\r
+ MASKED_NEW_EQUALS_X,\r
+ NEVER,\r
+ NEW_IS_OUTSIDE,\r
+ NEW_IS_WITHIN,\r
+ ONE_EVERY_N,\r
+} ComFilterAlgorithm_type;\r
+\r
+typedef enum {\r
+ BIG_ENDIAN,\r
+ LITTLE_ENDIAN,\r
+ OPAQUE,\r
+} ComSignalEndianess_type;\r
+\r
+typedef enum {\r
+ COM_TIMEOUT_DATA_ACTION_NONE,\r
+ COM_TIMEOUT_DATA_ACTION_REPLACE\r
+} ComRxDataTimeoutAction_type;\r
+\r
+/*\r
+typedef enum {\r
+\r
+} ComTransmissionMode_type;\r
+*/\r
+\r
+// Shortcut macros\r
+#define M_BOOLEAN boolean\r
+#define M_UINT8 uint8\r
+#define M_UINT16 uint16\r
+#define M_UINT32 uint32\r
+#define M_UINT8_N uint8\r
+#define M_SINT8 sint8\r
+#define M_SINT16 sint16\r
+#define M_SINT32 sint32\r
+\r
+#define SignalTypeToSize(type,length) \\r
+ (type == UINT8 ? sizeof(uint8) : \\r
+ type == UINT16 ? sizeof(uint16) : \\r
+ type == UINT32 ? sizeof(uint32) : \\r
+ type == UINT8_N ? sizeof(uint8) * length : \\r
+ type == SINT8 ? sizeof(sint8) : \\r
+ type == SINT16 ? sizeof(sint16) : \\r
+ type == SINT32 ? sizeof(sint32) : sizeof(boolean)) \\r
+\r
+\r
+typedef struct {\r
+ ComFilterAlgorithm_type ComFilterAlgorithm;\r
+ uint32 ComFilterMask;\r
+ uint32 ComFilterMax;\r
+ uint32 ComFilterMin;\r
+ uint32 ComFilterOffset;\r
+ uint32 ComFilterPeriodFactor;\r
+ uint32 ComFilterX;\r
+\r
+\r
+ uint32 ComFilterEcoreN;\r
+ uint32 ComFilterEcoreNewValue;\r
+ uint32 ComFilterEcoreOldValue;\r
+\r
+} ComFilter_type;\r
+\r
+\r
+typedef struct {\r
+ /* Starting position (bit) of the signal within the IPDU.\r
+ *\r
+ * Context:\r
+ * - Send and receive.\r
+ * - Required.\r
+ *\r
+ * Comment: Range 0 to 63.\r
+ */\r
+ const uint8 ComBitPosition;\r
+\r
+ /* The size of the signal in bits.\r
+ *\r
+ * Context:\r
+ * - Send and receive.\r
+ * - Required.\r
+ *\r
+ * Comment: Range 0 to 64.\r
+ */\r
+ const uint8 ComBitSize;\r
+\r
+ /* Identifier for the signal.\r
+ *\r
+ * Context:\r
+ * - Send and receive.\r
+ * - Required.\r
+ *\r
+ * Comment: Should be the same value as the index in the COM signal array.\r
+ */\r
+ const uint8 ComHandleId;\r
+\r
+ /* Callback function used when an invalid signal is received.\r
+ *\r
+ * Context:\r
+ * - Receive.\r
+ * - Not required.\r
+ */\r
+ // ComInvalidNotification;\r
+\r
+ /*\r
+ *\r
+ * Context:\r
+ * - Send and receive.\r
+ * - Not required.\r
+ */\r
+ //uint8 ComSignalDataInvalidValue;\r
+\r
+ /* Defines the endianess of the signal's network representation.\r
+ *\r
+ * Context:\r
+ * - Send and receive.\r
+ * - Required.\r
+ */\r
+ const ComSignalEndianess_type ComSignalEndianess;\r
+\r
+ /*\r
+ * Value used to initialized this signal.\r
+ *\r
+ * Context:\r
+ * - Send\r
+ * - Required\r
+ */\r
+ const uint32 ComSignalInitValue;\r
+\r
+ /* The number of bytes if the signal has type UINT8_N;\r
+ *\r
+ * Context:\r
+ * - Send and receive.\r
+ * - Required if type of signal is UINT8_N\r
+ *\r
+ * Comment: Range 1 to 8.\r
+ */\r
+ const uint8 ComSignalLength;\r
+\r
+ /* Defines the type of the signal\r
+ *\r
+ * Context:\r
+ * - Send and receive.\r
+ * - Required.\r
+ */\r
+ const Com_SignalType ComSignalType;\r
+\r
+\r
+ /* Filter for this signal\r
+ *\r
+ * Context:\r
+ * - Send.\r
+ * - Required.\r
+ */\r
+ const ComFilter_type ComFilter;\r
+\r
+ /* Pointer to the shadow buffer of the signal group that this group signal is contained in.\r
+ *\r
+ * Comment: This is initialized by Com_Init() and should not be configured.\r
+ */\r
+ //void *ComEcoreShadowBuffer;\r
+\r
+\r
+ /* IPDU id of the IPDU that this signal belongs to.\r
+ *\r
+ * Comment: This is initialized by Com_Init() and should not be configured.\r
+ */\r
+\r
+ //const uint8 ComIPduHandleId;\r
+ //const uint8 ComSignalUpdated;\r
+\r
+ const uint8 ComEcoreEOL;\r
+} ComGroupSignal_type;\r
+\r
+typedef struct {\r
+\r
+ /* Starting position (bit) of the signal within the IPDU.\r
+ *\r
+ * Context:\r
+ * - Send and receive.\r
+ * - Required.\r
+ *\r
+ * Comment: Range 0 to 63.
+ */\r
+ const uint8 ComBitPosition;\r
+\r
+ /* The size of the signal in bits.\r
+ *\r
+ * Context:\r
+ * - Send and receive.\r
+ * - Required.\r
+ *\r
+ * Comment: Range 0 to 64.
+ */\r
+ const uint8 ComBitSize;\r
+\r
+\r
+ /* Action to be taken if an invalid signal is received.\r
+ *\r
+ * Context:\r
+ * -
+ */\r
+ // ComDataInvalidAction;\r
+\r
+ /* Notification function for error notification.\r
+ *\r
+ * Context:\r
+ * - Send.\r
+ * - Not required.\r
+ *
+ */\r
+ void (*ComErrorNotification) (void);\r
+\r
+ /* First timeout period for deadline monitoring.\r
+ *\r
+ * Context:\r
+ * - Receive\r
+ * - Not required.
+ */\r
+ const uint32 ComFirstTimeoutFactor;\r
+\r
+ /* Identifier for the signal.\r
+ *\r
+ * Context:\r
+ * - Send and receive.\r
+ * - Required.\r
+ *\r
+ * Comment: Should be the same value as the index in the COM signal array.
+ */\r
+ const uint8 ComHandleId;\r
+\r
+ /* Callback function used when an invalid signal is received.\r
+ *\r
+ * Context:\r
+ * - Receive.\r
+ * - Not required.
+ */\r
+ // ComInvalidNotification;\r
+\r
+ /* Tx and Rx notification function.\r
+ *\r
+ * Context:\r
+ * - Send and receive.\r
+ * - Not required.
+ */\r
+ void (*ComNotification) (void);\r
+\r
+ /* Action to be performed when a reception timeout occurs.\r
+ *\r
+ * Context:\r
+ * - Receive.\r
+ * - Required.
+ */\r
+ const ComRxDataTimeoutAction_type ComRxDataTimeoutAction;\r
+\r
+ /*\r
+ *\r
+ * Context:\r
+ * - Send and receive.\r
+ * - Not required.
+ */\r
+ //uint8 ComSignalDataInvalidValue;\r
+\r
+ /* Defines the endianess of the signal's network representation.\r
+ *\r
+ * Context:\r
+ * - Send and receive.\r
+ * - Required.
+ */\r
+ const ComSignalEndianess_type ComSignalEndianess;\r
+\r
+ /*\r
+ * Value used to initialized this signal.\r
+ *\r
+ * Context:\r
+ * - Send\r
+ * - Required
+ */\r
+ const uint32 ComSignalInitValue;\r
+\r
+ /* The number of bytes if the signal has type UINT8_N;\r
+ *\r
+ * Context:\r
+ * - Send and receive.\r
+ * - Required if type of signal is UINT8_N\r
+ *\r
+ * Comment: Range 1 to 8.
+ */\r
+ const uint8 ComSignalLength;\r
+\r
+ /* Defines the type of the signal\r
+ *\r
+ * Context:\r
+ * - Send and receive.\r
+ * - Required.
+ */\r
+ const Com_SignalType ComSignalType;\r
+\r
+ /* Timeout period for deadline monitoring.\r
+ *\r
+ * Context:\r
+ * - Receive\r
+ * - Not required.\r
+ */\r
+ //const uint32 ComEcoreDeadlineCounter;\r
+ const uint32 ComTimeoutFactor;\r
+\r
+ /* Timeout notification function\r
+ *\r
+ * Context:\r
+ * - Receive and send\r
+ * - Not required.\r
+ */\r
+ void (*ComTimeoutNotification) (void);\r
+\r
+ const ComTransferProperty_type ComTransferProperty;\r
+\r
+ /*\r
+ * The bit position in the PDU for this signals update bit.\r
+ *\r
+ * Context:\r
+ * - Send and receive.\r
+ * - Not required.\r
+ *\r
+ * Comment: Range 0 to 63. If update bit is used for this signal, then the corresponding parameter ComSignalEcoreUseUpdateBit\r
+ * needs to be set to one.
+ */\r
+ const uint8 ComUpdateBitPosition;\r
+ const uint8 ComSignalEcoreUseUpdateBit;\r
+\r
+ /* Filter for this signal\r
+ *\r
+ * Context:\r
+ * - Send.\r
+ * - Required.
+ */\r
+ const ComFilter_type ComFilter;\r
+\r
+\r
+ /**** SIGNAL GROUP DATA ****/\r
+ const uint8 ComEcoreIsSignalGroup;\r
+ const ComGroupSignal_type *ComGroupSignal[COM_MAX_NR_SIGNALS_PER_SIGNAL_GROUP];\r
+ //void *ComEcoreShadowBuffer;\r
+ //void *ComEcoreIPduDataPtr;\r
+\r
+\r
+ /* Pointer to the data storage of this signals IPDU.\r
+ *\r
+ * Comment: This is initialized by Com_Init() and should not be configured.
+ */\r
+ //const void *ComIPduDataPtr;\r
+\r
+ /* IPDU id of the IPDU that this signal belongs to.\r
+ *\r
+ * Comment: This is initialized by Com_Init() and should not be configured.\r
+ */\r
+\r
+ //const uint8 ComIPduHandleId;\r
+ //const uint8 ComSignalUpdated;\r
+\r
+\r
+ const uint8 ComEcoreEOL;\r
+} ComSignal_type;\r
+\r
+\r
+typedef struct {\r
+ /* Transmission mode for this IPdu.\r
+ *\r
+ * Context:\r
+ * - Send.\r
+ * - Required.
+ */\r
+ const ComTxModeMode_type ComTxModeMode;\r
+\r
+ /* Defines the number of times this IPdu will be sent in each IPdu cycle.\r
+ *\r
+ * Context:\r
+ * - Send.\r
+ * - Required for transmission modes DIRECT/N-times and MIXED.\r
+ *\r
+ * Comment: Should be set to 0 for DIRECT transmission mode and >0 for DIRECT/N-times mode.
+ */\r
+ const uint8 ComTxModeNumberOfRepetitions;\r
+\r
+ /* Defines the period of the transmissions in DIRECT/N-times and MIXED\r
+ * transmission modes.\r
+ *\r
+ * Context:\r
+ * - Send.\r
+ * - Required for DIRECT/N-times and MIXED transmission modes.
+ */\r
+ const uint32 ComTxModeRepetitionPeriodFactor;\r
+\r
+ /* Time before first transmission of this IPDU. (i.e. between the ipdu group start\r
+ * and this IPDU is sent for the first time.\r
+ *\r
+ * Context:\r
+ * - Send.\r
+ * - Required for all transmission modes except NONE.
+ */\r
+ const uint32 ComTxModeTimeOffsetFactor;\r
+\r
+ /* Period of cyclic transmission.\r
+ *\r
+ * Context:\r
+ * - Send.\r
+ * - Required for CYCLIC and MIXED transmission mode.
+ */\r
+ const uint32 ComTxModeTimePeriodFactor;\r
+} ComTxMode_type;\r
+\r
+\r
+typedef struct {\r
+\r
+ /* Minimum delay between successive transmissions of the IPdu.\r
+ *\r
+ * Context:\r
+ * - Send.\r
+ * - Not required.
+ */\r
+ const uint32 ComTxIPduMinimumDelayFactor;\r
+\r
+ /* COM will fill unused areas within an IPdu with this bit patter.\r
+ *\r
+ * Context:\r
+ * - Send.\r
+ * - Required.
+ */\r
+ const uint8 ComTxIPduUnusedAreasDefault;\r
+\r
+ /* Transmission modes for this IPdu.\r
+ *\r
+ * Context:\r
+ * - Send.\r
+ * - Not required.\r
+ *\r
+ * Comment: TMS is not implemented so only one static transmission\r
+ * mode is supported.
+ */\r
+ const ComTxMode_type ComTxModeTrue;\r
+ //ComTxMode_type ComTxModeFalse;\r
+\r
+} ComTxIPdu_type;\r
+\r
+/*\r
+typedef struct {\r
+ uint8 ComTxIPduNumberOfRepetitionsLeft;\r
+ uint32 ComTxModeRepetitionPeriodTimer;\r
+ uint32 ComTxIPduMinimumDelayTimer;\r
+ uint32 ComTxModeTimePeriodTimer;\r
+} ComTxIPduTimer_type;\r
+*/\r
+\r
+typedef struct ComIPduGroup_type {\r
+ // ID of this group. 0-31.\r
+ const uint8 ComIPduGroupHandleId;\r
+\r
+ // reference to the group that this group possibly belongs to.\r
+ //struct ComIPduGroup_type *ComIPduGroupRef;\r
+\r
+ const uint8 ComEcoreEOL;\r
+} ComIPduGroup_type;\r
+\r
+\r
+typedef struct {\r
+\r
+ /* Callout function of this IPDU.\r
+ * The callout function is an optional function used both on sender and receiver side.\r
+ * If configured, it determines whether an IPdu is considered for further processing. If\r
+ * the callout return false the IPdu will not be received/sent.\r
+ *\r
+ * Context:\r
+ * - Send and receive.\r
+ * - Not required.
+ */\r
+ boolean (*ComIPduCallout)(PduIdType PduId, const uint8 *IPduData);\r
+\r
+\r
+ /* The ID of this IPDU.\r
+ *\r
+ * Context:\r
+ * - Send and receive.\r
+ * - Required.\r
+ *\r
+ * Comment:
+ */\r
+ const uint8 ComIPduRxHandleId;\r
+\r
+ /* Signal processing mode for this IPDU.\r
+ *\r
+ * Context:\r
+ * - Receive.\r
+ * - Required.
+ */\r
+ const Com_IPduSignalProcessingMode ComIPduSignalProcessing;\r
+\r
+ /* Size of the IPDU in bytes. 0-8 for CAN and LIN and 0-256 for FlexRay.\r
+ *\r
+ * Context:\r
+ * - Send and receive.\r
+ * - Required.
+ */\r
+ const uint8 ComIPduSize;\r
+\r
+ /* The direction of the IPDU. Receive or Send.\r
+ *\r
+ * Context:\r
+ * - Receive or send.\r
+ * - Required.
+ */\r
+ const Com_IPduDirection ComIPduDirection;\r
+\r
+ /* Reference to the IPDU group that this IPDU belongs to.\r
+ *\r
+ * Context:\r
+ * - Send and receive.\r
+ * - Required.
+ */\r
+ const uint8 ComIPduGroupRef;\r
+\r
+ /* Reference to global PDU structure. ???\r
+ *\r
+ * No global PDU structure defined so this variable is left out.
+ */\r
+ // PduIdRef\r
+\r
+ /* Container of transmission related parameters.\r
+ *\r
+ * Context:\r
+ * - Send\r
+ * - Required.
+ */\r
+ const ComTxIPdu_type ComTxIPdu;\r
+\r
+ /* Transmission related timers and parameters.\r
+ *\r
+ * Context:\r
+ * - Send\r
+ * - Not required.\r
+ * - Not part of the AUTOSAR standard.\r
+ *\r
+ * Comment: These are internal variables and should not be configured.
+ */\r
+ //ComTxIPduTimer_type ComEcoreTxIPduTimers;\r
+\r
+ /* Pointer to data storage of this IPDU.\r
+ *\r
+ * Context:\r
+ * - Send and receive.\r
+ *\r
+ * Comment: this memory will be initialized dynamically in Com_Init();
+ */\r
+ //void *ComIPduDataPtr;\r
+\r
+ /* References to all signals contained in this IPDU.\r
+ *\r
+ * Context:\r
+ * - Send and receive.\r
+ * - Not required.\r
+ *\r
+ * Comment: It probably makes little sense not to define at least one signal for each IPDU.\r
+ */\r
+ //const uint8 ComEcoreNIPduSignalGroupRef;\r
+ const ComSignal_type *ComIPduSignalGroupRef[COM_MAX_NR_SIGNALS_PER_IPDU];\r
+\r
+\r
+ /* References to all signals contained in this IPDU.\r
+ *\r
+ * Context:\r
+ * - Send and receive.\r
+ * - Not required.\r
+ *\r
+ * Comment: It probably makes little sense not to define at least one signal for each IPDU.\r
+ */\r
+ //const uint8 NComIPduSignalRef;\r
+ const ComSignal_type *ComIPduSignalRef[COM_MAX_NR_SIGNALS_PER_IPDU];\r
+\r
+ /*\r
+ * The following two variables are used to control the per I-PDU based Rx/Tx-deadline monitoring.\r
+ */\r
+ //const uint32 ComEcoreDeadlineCounter;\r
+ //const uint32 ComEcoreTimeoutFactor;\r
+\r
+ const uint8 ComEcoreEOL;\r
+\r
+} ComIPdu_type;\r
+\r
+\r
+// Contains configuration specific configuration parameters. Exists once per configuration.\r
+typedef struct {\r
+\r
+ // The ID of this configuration. This is returned by Com_GetConfigurationId();\r
+ const uint8 ComConfigurationId;\r
+\r
+ /*\r
+ * Signal Gateway mappings.\r
+ * Not Implemented yet.\r
+ ComGwMapping_type ComGwMapping[];\r
+ */\r
+\r
+ // IPDU definitions. At least one\r
+ const ComIPdu_type *ComIPdu;\r
+\r
+ //uint16 ComEcoreNIPdu;\r
+\r
+ // IPDU group definitions\r
+ const ComIPduGroup_type *ComIPduGroup;\r
+\r
+ // Signal definitions\r
+ const ComSignal_type *ComSignal;\r
+\r
+ // Signal group definitions\r
+ //ComSignalGroup_type *ComSignalGroup;\r
+\r
+ // Group signal definitions\r
+ const ComGroupSignal_type *ComGroupSignal;\r
+\r
+} Com_ConfigType;\r
+\r
+#endif /*COM_TYPES_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+/* See CopmpilerAbstraction.pdf */\r
+#ifndef COMPILER_H\r
+#define COMPILER_H\r
+\r
+/* REQ:COMPILER040,049,051 */\r
+#define AUTOMATIC\r
+#define _STATIC_ static\r
+#define NULL_PTR ((void *)0)\r
+\r
+/* REQ:COMPILER005 */\r
+/* TODO: skip the memclass for now */\r
+#define FUNC(rettype,memclass) rettype\r
+\r
+/* REQ:COMPILER006 */\r
+#define P2VAR(ptrtype, memclass, ptrclass) ptrtype\r
+\r
+/* TODO: memclass and more */\r
+#define P2CONST(ptrtype, memclass, ptrclass) ptrtype\r
+\r
+/* TODO: memclass and more */\r
+#define CONSTP2VAR(ptrtype,memclass,ptrclass) ptrclass ptrtype * const\r
+\r
+/* TODO: */\r
+#define P2FUNC(rettype,ptrclass,fctname) retype (*ptrclass,fctname)\r
+\r
+/* TODO: */\r
+#define CONST(consttype,memclass) const consttype\r
+\r
+/* TODO: */\r
+#define VAR(vartype,memclass) vartype\r
+\r
+\r
+\r
+#endif /* COMPILER_H */ \r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/* See CompilerAbstraction.pdf */\r
+\r
+/* REQ:COMPILER040 */\r
+\r
+// Huhh, \r
+\r
+#if 0\r
+#define TESTMOD_CODE __attribute__()\r
+#endif\r
+\r
+/* */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef DEM_H_\r
+#define DEM_H_\r
+\r
+#include "Std_Types.h"\r
+#include "Dem_Types.h"\r
+#include "Dem_IntErrId.h"\r
+\r
+typedef uint16 Dem_EventIdType;\r
+typedef uint8 Dem_EventStatusType;\r
+\r
+void Dem_PreInit( void );\r
+void Dem_Init( void );\r
+Std_ReturnType Dem_ReportErrorStatus( Dem_EventIdType,Dem_EventStatusType);\r
+\r
+\r
+#endif /*DEM_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*\r
+ * Development Error Tracer driver\r
+ *\r
+ * Specification: Autosar v2.0.1, Final\r
+ *\r
+ */\r
+\r
+#ifndef _DET_H_\r
+#define _DET_H_\r
+#include "Std_Types.h"\r
+#include "Det_Cfg.h"\r
+#include "Modules.h"\r
+\r
+#define DET_MODULE_ID MODULE_ID_DET\r
+\r
+#define DET_SW_MAJOR_VERSION 1\r
+#define DET_SW_MINOR_VERSION 0\r
+#define DET_SW_PATCH_VERSION 0\r
+#define DET_AR_MAJOR_VERSION 2\r
+#define DET_AR_MINOR_VERSION 0\r
+#define DET_AR_PATCH_VERSION 1\r
+\r
+// Error codes\r
+#define DET_E_CBK_REGISTRATION_FAILED 0x01\r
+#define DET_E_INDEX_OUT_OF_RANGE 0x02\r
+\r
+#define DET_CALLBACK_API 0xFF\r
+\r
+// Type used to store errors\r
+typedef struct\r
+{\r
+ uint16 moduleId;\r
+ uint8 instanceId;\r
+ uint8 apiId;\r
+ uint8 errorId;\r
+} Det_EntryType;\r
+\r
+#if ( DET_ENABLE_CALLBACKS == STD_ON )\r
+typedef void *(*detCbk_t)( uint16 ModuleId, uint8 InstanceId , uint8 ApiId, uint8 ErrorId);\r
+\r
+/*\r
+ * Add a callback function to the array of callback. After a call to Det_ReportError the callback\r
+ * is called. This can be used in for instance unit tests to verify that correct errors are\r
+ * reported when sending invalid parameters to a function.\r
+ * This function returns the index of the callback in the array when registration is successful. If\r
+ * not -1 is returned. The index can be used to remove a callback with the Det_RemoveCbk.\r
+ */\r
+uint8 Det_AddCbk ( detCbk_t detCbk);\r
+void Det_RemoveCbk ( uint8 detCbkIndex);\r
+#endif\r
+\r
+void Det_Init( void );\r
+#if DET_DEINIT_API == STD_ON\r
+void Det_DeInit( void );\r
+#endif\r
+void Det_ReportError( uint16 ModuleId, uint8 InstanceId, uint8 ApiId, uint8 ErrorId);\r
+void Det_Start( void );\r
+#endif /*_DET_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef DIO_H_\r
+#define DIO_H_\r
+\r
+#include "Std_Types.h"\r
+\r
+// API Service ID's\r
+#define DIO_READCHANNEL_ID 0x00\r
+#define DIO_WRITECHANNEL_ID 0x01\r
+#define DIO_READPORT_ID 0x02\r
+#define DIO_WRITEPORT_ID 0x03\r
+#define DIO_READCHANNELGROUP_ID 0x04\r
+#define DIO_WRITECHANNELGROUP_ID 0x05\r
+#define DIO_GETVERSIONINFO_ID 0x12\r
+\r
+#define DIO_E_PARAM_INVALID_CHANNEL_ID 10\r
+#define DIO_E_PARAM_INVALID_PORT_ID 20\r
+#define DIO_E_PARAM_INVALID_GROUP_ID 31\r
+\r
+typedef uint32 Dio_ChannelType;\r
+typedef uint32 Dio_PortType;\r
+typedef struct\r
+{\r
+ Dio_PortType port;\r
+ uint8 offset;\r
+ uint32 mask;\r
+} Dio_ChannelGroupType;\r
+\r
+#if 0 // Gone from 3.0\r
+typedef enum\r
+{\r
+ STD_LOW,\r
+ STD_HIGH,\r
+}Dio_LevelType;\r
+#endif\r
+\r
+typedef uint32 Dio_LevelType;\r
+\r
+typedef uint16 Dio_PortLevelType;\r
+\r
+#include "Dio_Cfg.h"\r
+\r
+#if ( DIO_VERSION_INFO_API == STD_ON)\r
+#define DIO_SW_MAJOR_VERSION 1 \r
+#define DIO_SW_MINOR_VERSION 0 \r
+#define DIO_SW_PATCH_VERSION 0 \r
+#define DIO_AR_MAJOR_VERSION 2\r
+#define DIO_AR_MINOR_VERSION 2 \r
+#define DIO_AR_PATCH_VERSION 1 \r
+\r
+void Dio_GetVersionInfo( Std_VersionInfoType *versionInfo );\r
+#endif\r
+\r
+Dio_LevelType Dio_ReadChannel(Dio_ChannelType channelId);\r
+void Dio_WriteChannel(Dio_ChannelType channelId, Dio_LevelType level);\r
+Dio_PortLevelType Dio_ReadPort(Dio_PortType portId);\r
+void Dio_WritePort(Dio_PortType portId, Dio_PortLevelType level);\r
+Dio_PortLevelType Dio_ReadChannelGroup( const Dio_ChannelGroupType *channelGroupIdPtr );\r
+void Dio_WriteChannelGroup(const Dio_ChannelGroupType *channelGroupIdPtr, Dio_PortLevelType level);\r
+\r
+#endif /*DIO_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef ECUM_H_\r
+#define ECUM_H_\r
+\r
+#include "Std_Types.h"\r
+#include "Os.h"\r
+#if defined(USE_COM)\r
+#include "ComStack_Types.h"\r
+#endif\r
+\r
+// Error codes produced by this module\r
+#define ECUM_E_NOT_INITIATED (0x10)\r
+#define ECUM_E_SERVICE_DISABLED (0x11)\r
+#define ECUM_E_NULL_POINTER (0x12)\r
+#define ECUM_E_INVALID_PAR (0x13)\r
+#define ECUM_E_MULTIPLE_RUN_REQUESTS (0x14)\r
+#define ECUM_E_MISMATCHED_RUN_RELEASE (0x15)\r
+#define ECUM_E_STATE_PAR_OUT_OF_RANGE (0x16)\r
+#define ECUM_E_UNKNOWN_WAKEUP_SOURCE (0x17)\r
+\r
+// Service ID in this module\r
+#define ECUM_GETSTATE_ID (0x07)\r
+#define ECUM_SELECTAPPMODE_ID (0x0f)\r
+#define ECUM_GETAPPMODE_ID (0x11)\r
+#define ECUM_SELECT_BOOTARGET_ID (0x12)\r
+#define ECUM_GET_BOOTARGET_ID (0x13)\r
+#define ECUM_MAINFUNCTION_ID (0x18)\r
+\r
+typedef enum {\r
+ ECUM_STATE_APP_RUN = 0x32,\r
+ ECUM_STATE_SHUTDOWN = 0x40,\r
+ ECUM_STATE_WAKEUP = 0x20,\r
+ ECUM_SUBSTATE_MASK = 0x0F,\r
+ ECUM_STATE_WAKEUP_WAKESLEEP = 0x25,\r
+ ECUM_STATE_WAKEUP_ONE = 0x21,\r
+ ECUM_STATE_OFF = 0x80,\r
+ ECUM_STATE_STARTUP = 0x10,\r
+ ECUM_STATE_PREP_SHUTDOWN = 0x44,\r
+ ECUM_STATE_RUN = 0x30,\r
+ ECUM_STATE_STARTUP_TWO = 0x12,\r
+ ECUM_STATE_WAKEUP_TTII = 0x26,\r
+ ECUM_STATE_WAKEUP_VALIDATION = 0x22,\r
+ ECUM_STATE_GO_SLEEP = 0x49,\r
+ ECUM_STATE_STARTUP_ONE = 0x11,\r
+ ECUM_STATE_WAKEUP_TWO = 0x24,\r
+ ECUM_STATE_SLEEP = 0x50,\r
+ ECUM_STATE_WAKEUP_REACTION = 0x23,\r
+ ECUM_STATE_APP_POST_RUN = 0x33,\r
+ ECUM_STATE_GO_OFF_TWO = 0x4e,\r
+ ECUM_STATE_RESET = 0x90,\r
+ ECUM_STATE_GO_OFF_ONE = 0x4d\r
+} EcuM_StateType;\r
+\r
+typedef uint8 EcuM_UserType;\r
+\r
+enum {\r
+ // Internal reset of µC (bit 2)\r
+ // The internal reset typically only resets the µC\r
+ // core but not peripherals or memory\r
+ // controllers. The exact behavior is hardware\r
+ // specific.\r
+ // This source may also indicate an unhandled\r
+ // exception.\r
+ ECUM_WKSOURCE_INTERNAL_RESET = 0x04,\r
+\r
+ // Reset by external watchdog (bit 4), if\r
+ // detection supported by hardware\r
+ ECUM_WKSOURCE_EXTERNAL_WDG = 0x10,\r
+\r
+ // Reset by internal watchdog (bit 3)\r
+ ECUM_WKSOURCE_INTERNAL_WDG = 0x08,\r
+\r
+ // Power cycle (bit 0)\r
+ ECUM_WKSOURCE_POWER = 0x01,\r
+\r
+ // ~0 to the power of 29\r
+ ECUM_WKSOURCE_ALL_SOURCES = 0x3FFFFFFF,\r
+\r
+ // Hardware reset (bit 1).\r
+ // If hardware cannot distinguish between a\r
+ // power cycle and a reset reason, then this\r
+ // shall be the default wakeup source\r
+ ECUM_WKSOURCE_RESET = 0x02,\r
+};\r
+\r
+typedef uint32 EcuM_WakeupSourceType;\r
+\r
+typedef enum\r
+{\r
+ ECUM_WKSTATUS_NONE = 0, // No pending wakeup event was detected\r
+ ECUM_WKSTATUS_PENDING = 1, // The wakeup event was detected but not yet validated\r
+ ECUM_WKSTATUS_VALIDATED = 2, // The wakeup event is valid\r
+ ECUM_WKSTATUS_EXPIRED = 3, // The wakeup event has not been validated and has expired therefore\r
+} EcuM_WakeupStatusType;\r
+\r
+typedef enum\r
+{\r
+ ECUM_WWKACT_RUN = 0, // Initialization into RUN state\r
+ ECUM_WKACT_TTII = 2, // Execute time triggered increased inoperation protocol and shutdown\r
+ ECUM_WKACT_SHUTDOWN = 3, // Immediate shutdown\r
+} EcuM_WakeupReactionType;\r
+\r
+typedef enum\r
+{\r
+ ECUM_BOOT_TARGET_APP = 0, // The Ecu will boot into the application\r
+ ECUM_BOOT_TARGET_BOOTLOADER = 1, // The Ecu will boot into the bootloader\r
+} EcuM_BootTargetType;\r
+\r
+#include "EcuM_Cfg.h"\r
+\r
+#if ( ECUM_VERSION_INFO_API == STD_ON)\r
+#define ECUM_SW_MAJOR_VERSION 1\r
+#define ECUM_SW_MINOR_VERSION 0\r
+#define ECUM_SW_PATCH_VERSION 0\r
+#define ECUM_AR_MAJOR_VERSION 1\r
+#define ECUM_AR_MINOR_VERSION 2\r
+#define ECUM_AR_PATCH_VERSION 2\r
+\r
+void EcuM_GetVersionInfo( Std_VersionInfoType *versionInfo );\r
+#endif\r
+\r
+void EcuM_Init( void );\r
+void EcuM_StartupTwo();\r
+void EcuM_Shutdown();\r
+\r
+Std_ReturnType EcuM_GetState(EcuM_StateType* state);\r
+\r
+Std_ReturnType EcuM_RequestRUN(EcuM_UserType user);\r
+Std_ReturnType EcuM_ReleaseRUN(EcuM_UserType user);\r
+\r
+Std_ReturnType EcuM_RequestPOST_RUN(EcuM_UserType user);\r
+Std_ReturnType EcuM_ReleasePOST_RUN(EcuM_UserType user);\r
+\r
+void EcuM_KillAllRUNRequests();\r
+\r
+#if defined(USE_COM)\r
+Std_ReturnType EcuM_ComM_RequestRUN(NetworkHandleType channel);\r
+Std_ReturnType EcuM_ComM_ReleaseRUN(NetworkHandleType channel);\r
+boolean EcuM_ComM_HasRequestedRUN(NetworkHandleType channel);\r
+#endif\r
+\r
+Std_ReturnType EcuM_SelectShutdownTarget(EcuM_StateType target, uint8 mode);\r
+Std_ReturnType EcuM_GetShutdownTarget(EcuM_StateType* target, uint8* mode);\r
+Std_ReturnType EcuM_GetLastShutdownTarget(EcuM_StateType* target, uint8* mode);\r
+\r
+EcuM_WakeupSourceType EcuM_GetPendingWakeupEvents();\r
+void EcuM_ClearWakeupEvent(EcuM_WakeupSourceType sources);\r
+EcuM_WakeupSourceType EcuM_GetValidatedWakeupEvents();\r
+EcuM_WakeupSourceType EcuM_GetExpiredWakeupEvents();\r
+EcuM_WakeupStatusType EcuM_GetStatusOfWakeupSource(EcuM_WakeupSourceType sources);\r
+\r
+Std_ReturnType EcuM_SelectApplicationMode(AppModeType appMode);\r
+Std_ReturnType EcuM_GetApplicationMode(AppModeType* appMode);\r
+\r
+Std_ReturnType EcuM_SelectBootTarget(EcuM_BootTargetType target);\r
+Std_ReturnType EcuM_GetBootTarget(EcuM_BootTargetType* target);\r
+\r
+void EcuM_MainFunction(void);\r
+\r
+void EcuM_OnGoOffTwo( void );\r
+void EcuM_AL_SwitchOff( void );\r
+\r
+#endif /*ECUM_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef ECUM_CBK_H_\r
+#define ECUM_CBK_H_\r
+\r
+//void EcuM_CB_NfyNvMJobEnd(uint8 ServiceId, NvM_RequestResultType JobResult);\r
+\r
+void EcuM_SetWakeupEvent(EcuM_WakeupSourceType sources);\r
+void EcuM_ValidateWakeupEvent(EcuM_WakeupSourceType sources);\r
+\r
+void EcuM_ErrorHook(Std_ReturnType reason);\r
+\r
+void EcuM_AL_DriverInitZero();\r
+EcuM_ConfigType* EcuM_DeterminePbConfiguration();\r
+void EcuM_AL_DriverInitOne(const EcuM_ConfigType* ConfigPtr);\r
+void EcuM_AL_DriverInitTwo(const EcuM_ConfigType* ConfigPtr);\r
+void EcuM_AL_DriverInitThree(const EcuM_ConfigType* ConfigPtr);\r
+\r
+void EcuM_OnRTEStartup();\r
+\r
+void EcuM_OnEnterRUN();\r
+void EcuM_OnExitRun();\r
+void EcuM_OnExitPostRun();\r
+\r
+void EcuM_OnPrepShutdown();\r
+void EcuM_OnGoSleep();\r
+void EcuM_OnGoOffOne();\r
+void EcuM_OnGoOffTwo();\r
+\r
+void EcuM_EnableWakeupSources(EcuM_WakeupSourceType wakeupSource);\r
+void Ecum_DisableWakeupSources(EcuM_WakeupSourceType wakeupSource);\r
+\r
+void EcuM_GenerateRamHash();\r
+uint8 EcuM_CheckRamHash();\r
+\r
+void EcuM_AL_SwitchOff();\r
+void Ecum_AL_DriverRestart();\r
+\r
+void EcuM_StartWakeupSources(EcuM_WakeupSourceType wakeupSource);\r
+void EcuM_CheckValidation(EcuM_WakeupSourceType wakeupSource);\r
+void EcuM_StopWakeupSources(EcuM_WakeupSourceType wakeupSource);\r
+\r
+EcuM_WakeupReactionType EcuM_OnWakeupReaction(EcuM_WakeupReactionType wact);\r
+\r
+void EcuM_CheckWakeup(EcuM_WakeupSourceType wakeupSource);\r
+void EcuM_SleepActivity();\r
+\r
+#endif /*ECUM_CBK_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef EEP_H_
+#define EEP_H_
+
+#include "Std_Types.h"
+#include "MemIf_Types.h"
+
+/* Standard info */
+#define EEP_VENDOR_ID 1
+#define EEP_MODULE_ID MODULE_ID_EEP
+#define EEP_SW_MAJOR_VERSION 1
+#define EEP_SW_MINOR_VERSION 0
+#define EEP_SW_PATCH_VERSION 1
+#define EEP_AR_MAJOR_VERSION 2
+#define EEP_AR_MINOR_VERSION 2
+#define EEP_AR_PATCH_VERSION 1
+
+typedef uint32 Eep_AddressType;
+typedef Eep_AddressType Eep_LengthType;
+
+/* Development errors */
+// API parameter checking
+#define EEP_E_PARAM_CONFIG 0x10
+#define EEP_E_PARAM_ADDRESS 0x11
+#define EEP_E_PARAM_DATA 0x12
+#define EEP_E_PARAM_LENGTH 0x13
+// EEPROM state checking
+#define EEP_E_UNINIT 0x20
+#define EEP_E_BUSY 0x21
+
+/* Service id's for fls functions */
+#define EEP_INIT_ID 0x00
+#define EEP_SETMODE_ID 0x01
+#define EEP_READ_ID 0x02
+#define EEP_WRITE_ID 0x03
+#define EEP_ERASE_ID 0x04
+#define EEP_COMPARE_ID 0x05
+#define EEP_CANCEL_ID 0x06
+#define EEP_GETSTATUS_ID 0x07
+#define EEP_GETJOBSTATUS_ID 0x08
+#define EEP_GETVERSIONINFO_ID 0x0A
+
+
+#include "Eep_Cfg.h"
+
+void Eep_Init( const Eep_ConfigType *ConfigPtr );
+Std_ReturnType Eep_Erase( Eep_AddressType EepromAddress,
+ Eep_LengthType Length );
+
+
+Std_ReturnType Eep_Write ( Eep_AddressType EepromAddress,
+ const uint8 *SourceAddressPtr,
+ Eep_LengthType Length );
+
+void Eep_Cancel( void );
+MemIf_StatusType Eep_GetStatus( void );
+MemIf_JobResultType Eep_GetJobResult( void );
+
+void Eep_MainFunction( void );
+
+Std_ReturnType Eep_Read ( Eep_AddressType EepromAddress,
+ uint8 *TargetAddressPtr,
+ Eep_LengthType Length );
+
+Std_ReturnType Eep_Compare( Eep_AddressType EepromAddress,
+ uint8 *TargetAddressPtr,
+ Eep_LengthType Length );
+
+void Eep_SetMode( MemIf_ModeType Mode );
+
+#if ( EEP_VERSION_INFO_API == STD_ON )
+#define Eep_GetVersionInfo(_vi) STD_GET_VERSION_INFO(_vi,EEP)
+#endif
+
+#endif /*EEP_H_*/
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef FLS_H_
+#define FLS_H_
+
+// Only if external flash device
+//#include "Spi.h"
+#include "Std_Types.h"
+#include "Det.h"
+//#include "MemIf_Types.h"
+// TODO: not yet #include "Dem.h"
+
+// SW ans Autosar spec versions
+#define FLS_SW_MAJOR_VERSION 1
+#define FLS_SW_MINOR_VERSION 0
+#define FLS_SW_PATCH_VERSION 1
+#define FLS_AR_MAJOR_VERSION 3
+#define FLS_AR_MINOR_VERSION 0
+#define FLS_AR_PATCH_VERSION 2
+
+// API service called with wrong parameter
+#define FLS_E_PARAM_CONFIG 0x01
+#define FLS_E_PARAM_ADDRESS 0x02
+#define FLS_E_PARAM_LENGTH 0x03
+#define FLS_E_PARAM_DATA 0x04
+// API service called without module initialization
+#define FLS_E_UNINIT 0x05
+// API service called while driver still busy
+#define FLS_E_BUSY 0x06
+// Erase verification (blank check) failed
+#define FLS_E_VERIFY_ERASE_FAILED 0x07
+// Write verification (compare) failed
+#define FLS_E_VERIFY_WRITE_FAILED 0x08
+
+// These should be assigned by the DEM module
+#define FLS_E_ERASED_FAILED 0x09
+#define FLS_E_WRITE_FAILED 0x0A
+#define FLS_E_READ_FAILED 0x0B
+#define FLS_E_COMPARE_FAILED 0x0C
+#define FLS_E_UNEXPECTED_FLASH_ID 0x0D
+
+// Service id's for fls functions
+#define FLS_INIT_ID 0x00
+#define FLS_ERASE_ID 0x01
+#define FLS_WRITE_ID 0x02
+#define FLS_CANCEL_ID 0x03
+#define FLS_GET_STATUS_ID 0x04
+#define FLS_GET_JOB_RESULT_ID 0x05
+#define FLS_MAIN_FUNCTION_ID 0x06
+#define FLS_READ_ID 0x07
+#define FLS_COMPARE_ID 0x08
+#define FLS_SET_MODE_ID 0x09
+#define FLS_GET_VERSION_INFO_ID 0x10
+
+// Used as address offset from the configured flash base address to access a certain
+// flash memory area.
+typedef uint32 Fls_AddressType;
+
+// Specifies the number of bytes to read/write/erase/compare
+//
+// Note!
+// Shall be the same type as Fls_AddressType because of
+// arithmetic operations. Size depends on target platform and
+// flash device.
+typedef uint32 Fls_LengthType;
+
+#include "Fls_Cfg.h"
+
+/**
+ * Initializes the Flash Driver.
+ *
+ * @param ConfigPtr Pointer to flash driver configuration set.
+ */
+void Fls_Init( const Fls_ConfigType *ConfigPtr );
+
+
+/**
+ * Erases flash sector(s).
+ *
+ * @param TargetAddress Target address in flash memory.
+ * This address offset will be
+ * added to the flash memory base address.
+ * Min.: 0
+ * Max.: FLS_SIZE - 1
+ *
+ * @param Length Number of bytes to erase
+ * Min.: 1
+ * Max.: FLS_SIZE - TargetAddress
+ *
+ * @return E_OK: erase command has been accepted
+ * E_NOT_OK: erase command has not been accepted
+ */
+
+Std_ReturnType Fls_Erase( Fls_AddressType TargetAddress,
+ Fls_LengthType Length );
+
+
+Std_ReturnType Fls_Write ( Fls_AddressType TargetAddress,
+ const uint8 *SourceAddressPtr,
+ Fls_LengthType Length );
+
+#if ( FLS_CANCEL_API == STD_ON )
+void Fls_Cancel( void );
+#endif
+
+#if ( FLS_GET_STATUS_API == STD_ON )
+MemIf_StatusType Fls_GetStatus( void );
+#endif
+
+#if ( FLS_GET_JOB_RESULT_API == STD_ON )
+MemIf_JobResultType Fls_GetJobResult( void );
+#endif
+
+void Fls_MainFunction( void );
+
+Std_ReturnType Fls_Read ( Fls_AddressType SourceAddress,
+ uint8 *TargetAddressPtr,
+ Fls_LengthType Length );
+
+#if ( FLS_COMPARE_API == STD_ON )
+Std_ReturnType Fls_Compare( Fls_AddressType SourceAddress,
+ uint8 *TargetAddressPtr,
+ Fls_LengthType Length );
+#endif
+
+#if ( FLS_SET_MODE_API == STD_ON )
+void Fls_SetMode( Fls_ModeType Mode );
+#endif
+
+void Fls_GetVersionInfo( Std_VersionInfoType *VersioninfoPtr );
+
+
+#endif /*FLS_H_*/
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+#ifndef FLS_SST25XX_H_\r
+#define FLS_SST25XX_H_\r
+\r
+\r
+// Only if external flash device\r
+//#include "Spi.h"\r
+#include "Std_Types.h"\r
+#include "Det.h"\r
+#include "Fls.h"\r
+\r
+// SW ans Autosar spec versions\r
+#define FLS_SST25XX_SW_MAJOR_VERSION 1\r
+#define FLS_SST25XX_SW_MINOR_VERSION 0\r
+#define FLS_SST25XX_SW_PATCH_VERSION 0\r
+#define FLS_SST25XX_AR_MAJOR_VERSION 3\r
+#define FLS_SST25XX_AR_MINOR_VERSION 0\r
+#define FLS_SST25XX_AR_PATCH_VERSION 2\r
+\r
+#if 0\r
+// Used as address offset from the configured flash base address to access a certain\r
+// flash memory area.\r
+typedef uint32 Fls_AddressType;\r
+\r
+// Specifies the number of bytes to read/write/erase/compare\r
+//\r
+// Note!\r
+// Shall be the same type as Fls_AddressType because of\r
+// arithmetic operations. Size depends on target platform and\r
+// flash device.\r
+typedef uint32 Fls_LengthType;\r
+#endif\r
+\r
+#include "Fls_SST25xx_Cfg.h"\r
+\r
+/**\r
+ * Initializes the Flash Driver.\r
+ *\r
+ * @param ConfigPtr Pointer to flash driver configuration set.\r
+ */\r
+void Fls_SST25xx_Init( const Fls_ConfigType *ConfigPtr );\r
+\r
+\r
+/**\r
+ * Erases flash sector(s).\r
+ *\r
+ * @param TargetAddress Target address in flash memory.\r
+ * This address offset will be\r
+ * added to the flash memory base address.\r
+ * Min.: 0\r
+ * Max.: FLS_SIZE - 1\r
+ *\r
+ * @param Length Number of bytes to erase\r
+ * Min.: 1\r
+ * Max.: FLS_SIZE - TargetAddress\r
+ *\r
+ * @return E_OK: erase command has been accepted\r
+ * E_NOT_OK: erase command has not been accepted\r
+ */\r
+#if 0\r
+typedef uint32 Fls_AddressType;\r
+\r
+// Specifies the number of bytes to read/write/erase/compare\r
+//\r
+// Note!\r
+// Shall be the same type as Fls_AddressType because of\r
+// arithmetic operations. Size depends on target platform and\r
+// flash device.\r
+typedef uint32 Fls_LengthType;\r
+#endif\r
+\r
+\r
+Std_ReturnType Fls_SST25xx_Erase( Fls_AddressType TargetAddress,\r
+ Fls_LengthType Length );\r
+\r
+\r
+Std_ReturnType Fls_SST25xx_Write ( Fls_AddressType TargetAddress,\r
+ const uint8 *SourceAddressPtr,\r
+ Fls_LengthType Length );\r
+\r
+#if ( FLS_CANCEL_API == STD_ON )\r
+void Fls_SST25xx_Cancel( void );\r
+#endif\r
+\r
+MemIf_StatusType Fls_SST25xx_GetStatus( void );\r
+MemIf_JobResultType Fls_SST25xx_GetJobResult( void );\r
+\r
+void Fls_SST25xx_MainFunction( void );\r
+\r
+Std_ReturnType Fls_SST25xx_Read ( Fls_AddressType SourceAddress,\r
+ uint8 *TargetAddressPtr,\r
+ Fls_LengthType Length );\r
+\r
+#if ( FLS_COMPARE_API == STD_ON )\r
+Std_ReturnType Fls_SST25xx_Compare( Fls_AddressType SourceAddress,\r
+ uint8 *TargetAddressPtr,\r
+ Fls_LengthType Length );\r
+#endif\r
+\r
+#if ( FLS_SET_MODE_API == STD_ON )\r
+void Fls_SST25xx_SetMode( Fls_ModeType Mode );\r
+#endif\r
+\r
+void Fls_SST25xx_GetVersionInfo( Std_VersionInfoType *VersioninfoPtr );\r
+\r
+\r
+#endif /* FLS_SST25XX_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef GPT_H_
+#define GPT_H_
+
+#include "Std_Types.h"
+//#include "EcuM.h" mahi: What for ???
+
+/* ERROR CODES */
+#define GPT_E_UNINIT 0x0a
+#define GPT_E_BUSY 0x0b
+#define GPT_E_NOT_STARTED 0x0c
+#define GPT_E_ALREADY_INITIALIZED 0x0d
+#define GPT_E_PARAM_CHANNEL 0x14
+#define GPT_E_PARAM_VALUE 0x15
+#define GPT_E_PARAM_MODE 0x1f
+#define GPT_E_PARAM_CONFIG 0x0e // TODO: Not in spec. Find real value
+
+/* SERVICE_ID's */
+#define GPT_INIT_SERVICE_ID 0x01
+#define GPT_DEINIT_SERVICE_ID 0x02
+#define GPT_GETTIMEELAPSED_SERVICE_ID 0x03
+#define GPT_GETTIMEREMAINING_SERVICE_ID 0x04
+#define GPT_STARTTIMER_SERVICE_ID 0x05
+#define GPT_STOPTIMER_SERVICE_ID 0x06
+#define GPT_ENABLENOTIFICATION_SERVICE_ID 0x07
+#define GPT_DISABLENOTIFICATION_SERVICE_ID 0x08
+#define GPT_SETMODE_SERVIVCE_ID 0x09
+#define GPT_DISABLEWAKEUP_SERVICE_ID 0x0a
+#define GPT_ENABLEWAKEUP_SERVICE_ID 0x0b
+#define GPT_CBK_CHECKWAKEUP_SERVICE_ID 0x0c
+
+typedef uint8_t Gpt_ChannelType;
+
+typedef uint32_t Gpt_ValueType;
+
+typedef enum
+{
+ GPT_MODE_ONESHOT=0,
+ GPT_MODE_CONTINUOUS
+} Gpt_ChannelMode;
+
+typedef enum
+{
+ GPT_MODE_NORMAL=0,
+ GPT_MODE_SLEEP
+} Gpt_ModeType;
+
+#include "Gpt_Cfg.h"
+
+#if (GPT_VERSION_INFO_API == STD_ON)
+
+#define GPT_VENDOR_ID 1
+#define GPT_MODULE_ID 1
+#define GPT_SW_MAJOR_VERSION 1
+#define GPT_SW_MINOR_VERSION 0
+#define GPT_SW_PATCH_VERSION 0
+#define GPT_AR_MAJOR_VERSION 2
+#define GPT_AR_MINOR_VERSION 2
+#define GPT_AR_PATCH_VERSION 1
+
+#define Gpt_GetVersionInfo(_vi) STD_GET_VERSION_INFO(_vi,GPT)
+#endif
+
+void Gpt_Init( const Gpt_ConfigType * );
+
+#if GPT_DEINIT_API == STD_ON
+void Gpt_DeInit( void );
+#endif
+
+#if ( GPT_TIME_ELAPSED_API == STD_ON )
+Gpt_ValueType Gpt_GetTimeElapsed(Gpt_ChannelType channel);
+#endif
+
+#if ( GPT_TIME_REMAINING_API == STD_ON )
+Gpt_ValueType Gpt_GetTimeRemaining( Gpt_ChannelType channel );
+#endif
+
+void Gpt_StartTimer(Gpt_ChannelType channel, Gpt_ValueType value);
+
+void Gpt_StopTimer(Gpt_ChannelType channel);
+
+#if ( GPT_ENABLE_DISABLE_NOTIFICATION_API == STD_ON )
+void Gpt_EnableNotification( Gpt_ChannelType channel);
+
+void Gpt_DisableNotification( Gpt_ChannelType channel);
+#endif
+
+#if ( GPT_WAKEUP_FUNCTIONALITY_API == STD_ON )
+void Gpt_SetMode( Gpt_ModeType mode );
+
+void Gpt_DisableWakeup( Gpt_ChannelType channel );
+
+void Gpt_EnableWakeup( Gpt_ChannelType channel );
+
+void Gpt_Cbk_CheckWakeup( EcuM_WakeupSourceType wakeupSource );
+#endif
+
+#endif /*GPT_H_*/
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef LIN_H_\r
+#define LIN_H_\r
+\r
+#include "Std_Types.h"\r
+#include "Lin_Cfg.h"\r
+#include "ComStack_Types.h"\r
+\r
+#if (LIN_VERSION_INFO_API == STD_ON)\r
+\r
+#define LIN_SW_MAJOR_VERSION 1\r
+#define LIN_SW_MINOR_VERSION 0\r
+#define LIN_SW_PATCH_VERSION 0\r
+#define LIN_AR_MAJOR_VERSION 1\r
+#define LIN_AR_MINOR_VERSION 2\r
+#define LIN_AR_PATCH_VERSION 1\r
+\r
+void Lin_GetVersionInfo( Std_VersionInfoType *versionInfo );\r
+#define Lin_GetVersionInfo(_vi) STD_GET_VERSION_INFO(_vi,LIN)\r
+#endif\r
+\r
+/* This is the type of the external data structure containing the overall\r
+ * initialization data for the LIN driver and SFR settings affecting all\r
+ * LIN channels. A pointer to such a structure is provided to the LIN driver\r
+ * initialization routine for configuration of the driver and LIN hardware unit. */\r
+typedef struct {\r
+} Lin_ConfigType;\r
+\r
+/* Represents all valid protected Identifier used by Lin_SendHeader(). */\r
+typedef uint8 Lin_FramePidType;\r
+\r
+/* This type is used to specify the Checksum model to be used for the LIN Frame. */\r
+typedef enum {\r
+ LIN_ENHANCED_CS,\r
+ LIN_CLASSIC_CS,\r
+} Lin_FrameCsModelType;\r
+\r
+// This type is used to specify whether the frame processor is required to transmit the\r
+// response part of the LIN frame.\r
+typedef enum {\r
+ // Response is generated from this (master) node\r
+ LIN_MASTER_RESPONSE=0,\r
+ // Response is generated from a remote slave node\r
+ LIN_SLAVE_RESPONSE,\r
+ // Response is generated from one slave to another slave,\r
+ // for the master the response will be anonymous, it does not\r
+ // have to receive the response.\r
+ IN_SLAVE_TO_SLAVE,\r
+\r
+} Lin_FrameResponseType;\r
+\r
+// This type is used to specify the number of SDU data bytes to copy.\r
+typedef uint8 Lin_FrameDIType;\r
+\r
+// This Type is used to provide PID, checksum model, data length and SDU pointer\r
+// from the LIN Interface to the LIN driver.\r
+typedef struct {\r
+ Lin_FrameCsModelType Cs;\r
+ Lin_FramePidType Pid;\r
+ uint8* SduPtr;\r
+ Lin_FrameDIType DI;\r
+ Lin_FrameResponseType Drc;\r
+} Lin_PduType;\r
+\r
+typedef enum {\r
+ LIN_UNINIT,\r
+ LIN_INIT,\r
+}Lin_DriverStatusType;\r
+\r
+typedef enum {\r
+ // LIN frame operation return value.\r
+ // Development or production error occurred\r
+ LIN_NOT_OK,\r
+\r
+ // LIN frame operation return value.\r
+ // Successful transmission.\r
+ LIN_TX_OK,\r
+\r
+ // LIN frame operation return value.\r
+ // Ongoing transmission (Header or Response).\r
+ LIN_TX_BUSY,\r
+\r
+ // LIN frame operation return value.\r
+ // Erroneous header transmission such as:\r
+ // - Mismatch between sent and read back data\r
+ // - Identifier parity error or\r
+ // - Physical bus error\r
+ LIN_TX_HEADER_ERRORLIN,\r
+\r
+ // LIN frame operation return value.\r
+ // Erroneous response transmission such as:\r
+ // - Mismatch between sent and read back data\r
+ // - Physical bus error\r
+ LIN_TX_ERROR,\r
+\r
+ // LIN frame operation return value.\r
+ // Reception of correct response.\r
+ LIN_RX_OK,\r
+\r
+ // LIN frame operation return value. Ongoing reception: at\r
+ // least one response byte has been received, but the\r
+ // checksum byte has not been received.\r
+ LIN_RX_BUSY,\r
+\r
+ // LIN frame operation return value.\r
+ // Erroneous response reception such as:\r
+ // - Framing error\r
+ // - Overrun error\r
+ // - Checksum error or\r
+ // - Short response\r
+ LIN_RX_ERROR,\r
+\r
+\r
+ // LIN frame operation return value.\r
+ // No response byte has been received so far.\r
+ LIN_RX_NO_RESPONSE,\r
+\r
+ // LIN channel state return value.\r
+ // LIN channel not initialized.\r
+ LIN_CH_UNINIT,\r
+\r
+ // LIN channel state return value.\r
+ // Normal operation; the related LIN channel is ready to\r
+ // transmit next header. No data from previous frame\r
+ // available (e.g. after initialization)\r
+ LIN_CH_OPERATIONAL,\r
+\r
+ // LIN channel state return value.\r
+ // Sleep mode operation; in this mode wake-up detection\r
+ // from slave nodes is enabled.\r
+ LIN_CH_SLEEP\r
+\r
+} Lin_StatusType;\r
+\r
+/* --- Service IDs --- */\r
+#define LIN_INIT_SERVICE_ID 0x00\r
+#define LIN_GETVERSIONINFO_SERVICE_ID 0x01\r
+#define LIN_WAKEUPVALIDATION_SERVICE_ID 0x0A\r
+#define LIN_INIT_CHANNEL_SERVICE_ID 0x02\r
+#define LIN_DEINIT_CHANNEL_SERVICE_ID 0x03\r
+#define LIN_SEND_HEADER_SERVICE_ID 0x04\r
+#define LIN_SEND_RESPONSE_SERVICE_ID 0x05\r
+#define LIN_GO_TO_SLEEP_SERVICE_ID 0x06\r
+#define LIN_WAKE_UP_SERVICE_ID 0x07\r
+#define LIN_GETSTATUS_SERVICE_ID 0x08\r
+#define LIN_GO_TO_SLEEP_INTERNAL_SERVICE_ID 0x09\r
+\r
+/* --- Error codes --- */\r
+#define LIN_E_UNINIT 0x00\r
+#define LIN_E_CHANNEL_UNINIT 0x01\r
+#define LIN_E_INVALID_CHANNEL 0x02\r
+#define LIN_E_INVALID_POINTER 0x03\r
+#define LIN_E_STATE_TRANSITION 0x04\r
+#define LIN_E_TIMEOUT 0x05 //TODO Assigned by DEM\r
+\r
+void Lin_Init( const Lin_ConfigType* Config );\r
+\r
+void Lin_DeInit();\r
+\r
+void Lin_WakeupValidation( void );\r
+\r
+void Lin_InitChannel( uint8 Channel, const Lin_ChannelConfigType* Config );\r
+\r
+void Lin_DeInitChannel( uint8 Channel );\r
+\r
+Std_ReturnType Lin_SendHeader( uint8 Channel, Lin_PduType* PduInfoPtr );\r
+\r
+Std_ReturnType Lin_SendResponse( uint8 Channel, Lin_PduType* PduInfoPtr );\r
+\r
+Std_ReturnType Lin_GoToSleep( uint8 Channel );\r
+\r
+Std_ReturnType Lin_GoToSleepInternal( uint8 Channel );\r
+\r
+Std_ReturnType Lin_WakeUp( uint8 Channel );\r
+\r
+Lin_StatusType Lin_GetStatus( uint8 Channel, uint8** Lin_SduPtr );\r
+\r
+#endif\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef LINIF_H_\r
+#define LINIF_H_\r
+\r
+#include "Std_Types.h"\r
+#include "LinIf_Cfg.h"\r
+#include "LinIf_Types.h"\r
+#include "ComStack_Types.h"\r
+#include "ComM_Types.h"\r
+\r
+#if (LINIF_VERSION_INFO_API == STD_ON)\r
+\r
+#define LINIF_SW_MAJOR_VERSION 1\r
+#define LINIF_SW_MINOR_VERSION 0\r
+#define LINIF_SW_PATCH_VERSION 0\r
+#define LINIF_AR_MAJOR_VERSION 2\r
+#define LINIF_AR_MINOR_VERSION 0\r
+#define LINIF_AR_PATCH_VERSION 1\r
+\r
+/* --- Service IDs --- */\r
+#define LINIF_INIT_SERVICE_ID 0x00\r
+#define LINIF_GETVERSIONINFO_SERVICE_ID 0x03\r
+#define LINIF_SCHEDULEREQUEST_SERVICE_ID 0x05\r
+#define LINIF_GOTOSLEEP_SERVICE_ID 0x06\r
+#define LINIF_WAKEUP_SERVICE_ID 0x07\r
+#define LINIF_MAINFUNCTION_SERVICE_ID 0x80\r
+\r
+/* --- Error codes --- */\r
+#define LINIF_E_UNINIT 0x00\r
+#define LINIF_E_ALREADY_INITIALIZED 0x10\r
+#define LINIF_E_NONEXISTENT_CHANNEL 0x20\r
+#define LINIF_E_PARAMETER 0x30\r
+#define LINIF_E_PARAMETER_POINTER 0x40\r
+#define LINIF_E_SCHEDULE_OVERFLOW 0x50\r
+#define LINIF_E_SCHEDULE_REQUEST_ERROR 0x51\r
+#define LINIF_E_RESPONSE 0x52 //Assigned\r
+#define LINIF_E_NC_NO_RESPONSE 0x53 //Assigned by DEM\r
+#define LINIF_E_CHANNEL_X_SLAVE_Y 0x54 //Assigned by DEM\r
+\r
+void LinIf_GetVersionInfo( Std_VersionInfoType *versionInfo );\r
+#define LinIf_GetVersionInfo(_vi) STD_GET_VERSION_INFO(_vi,LINIF)\r
+#endif\r
+\r
+void LinIf_Init( const void* ConfigPtr );\r
+\r
+void LinIf_DeInit();\r
+\r
+Std_ReturnType LinIf_Transmit(PduIdType LinTxPduId,const PduInfoType* PduInfoPtr);\r
+\r
+Std_ReturnType LinIf_ScheduleRequest(NetworkHandleType Channel,LinIf_SchHandleType Schedule);\r
+\r
+Std_ReturnType LinIf_GotoSleep(NetworkHandleType Channel);\r
+\r
+Std_ReturnType LinIf_WakeUp(NetworkHandleType Channel);\r
+\r
+void LinIf_MainFunction();\r
+\r
+#endif\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef LINIF_CBK_H_\r
+#define LINIF_CBK_H_\r
+\r
+#include "Std_Types.h"\r
+\r
+void LinIf_Cbk_CheckWakeup(NetworkHandleType Channel);\r
+\r
+#endif\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef LINIF_TYPES_H_\r
+#define LINIF_TYPES_H_\r
+\r
+#include "Std_Types.h"\r
+\r
+typedef uint8 LinIf_SchHandleType;\r
+\r
+#endif\r
+\r
+\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef LINSM_H_\r
+#define LINSM_H_\r
+\r
+#include "ComStack_Types.h"\r
+#include "Std_Types.h"\r
+#include "LinSM_Cfg.h"\r
+#include "Com_Types.h"\r
+#include "Com.h"\r
+#include "ComM_Types.h"\r
+#include "LinIf.h"\r
+\r
+#if (LINSM_VERSION_INFO_API == STD_ON)\r
+\r
+#define LINSM_SW_MAJOR_VERSION 1\r
+#define LINSM_SW_MINOR_VERSION 0\r
+#define LINSM_SW_PATCH_VERSION 0\r
+#define LINSM_AR_MAJOR_VERSION 1\r
+#define LINSM_AR_MINOR_VERSION 0\r
+#define LINSM_AR_PATCH_VERSION 1\r
+\r
+#define LINSM_INIT_SERVICE_ID 0x01\r
+#define LINSM_REQUEST_COM_MODE_SERVICE_ID 0x10\r
+#define LINSM_GET_CURRENT_COM_MODE_SERVICE_ID 0x11\r
+#define LINSM_SCHEDULE_REQUEST_SERVICE_ID 0x12\r
+#define LINSM_GOTO_SLEEP_CONF_SERVICE_ID 0x20\r
+#define LINSM_WAKEUP_CONF_SERVICE_ID 0x21\r
+#define LINSM_SCHEDULE_REQUEST_CONF_SERVICE_ID 0x22\r
+\r
+/* --- Error codes --- */\r
+#define LINSM_E_UNINIT 0x00\r
+#define LINSM_E_ALREADY_INITIALIZED 0x10\r
+#define LINSM_E_NOXEXISTENT_CHANNEL 0x20\r
+#define LINSM_E_PARAMETER 0x30\r
+#define LINSM_E_PARAMETER_POINTER 0x40\r
+#define LINSM_E_NOT_IN_RUN_SCHEDULE 0x50\r
+#define LINSM_E_CONFIRMATION_TIMEOUT 0x60 //Assigned by DEM\r
+\r
+typedef enum {\r
+ LINSM_UNINIT,\r
+ LINSM_INIT,\r
+ LINSM_NO_COM,\r
+ LINSM_FULL_COM,\r
+ LINSM_RUN_SCHEDULE,\r
+ LINSM_GOTO_SLEEP,\r
+}LinSM_StatusType;\r
+\r
+void LinSM_GetVersionInfo( Std_VersionInfoType *versionInfo );\r
+#define LinSM_GetVersionInfo(_vi) STD_GET_VERSION_INFO(_vi,LINSM)\r
+#endif\r
+\r
+void LinSM_Init(const void* ConfigPtr);\r
+void LinSM_DeInit();\r
+\r
+Std_ReturnType LinSM_ScheduleRequest(NetworkHandleType channel,LinIf_SchHandleType schedule);\r
+\r
+Std_ReturnType LinSM_GetCurrentComMode(NetworkHandleType network,ComM_ModeType* mode);\r
+\r
+Std_ReturnType LinSM_RequestComMode(NetworkHandleType network,ComM_ModeType mode);\r
+\r
+\r
+#endif\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef LINSM_CBK_H_\r
+#define LINSM_CBK_H_\r
+\r
+#include "Std_Types.h"\r
+\r
+void LinSM_ScheduleRequest_Confirmation(NetworkHandleType channel);\r
+\r
+void LinSM_WakeUp_Confirmation(NetworkHandleType channel,boolean success);\r
+\r
+void LinSM_GotoSleep_Confirmation(NetworkHandleType channel,boolean success);\r
+\r
+// Own timer tick function for internal timers\r
+void LinSM_TimerTick();\r
+\r
+#endif\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef LIN_TYPES_H_\r
+#define LIN_TYPES_H_\r
+\r
+#include "Std_Types.h"\r
+\r
+#endif
\ No newline at end of file
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef MCU_H_\r
+#define MCU_H_\r
+\r
+#include "Cpu.h"\r
+#include "irq.h"\r
+//#include "mpc55xx_aos.h"\r
+\r
+/* Service ID's */\r
+#define MCU_INIT_SERVICE_ID 0x00\r
+#define MCU_INITRAMSECTION_SERVICE_ID 0x01\r
+#define MCU_INITCLOCK_SERVICE_ID 0x02\r
+#define MCU_DISTRIBUTEPLLCLOCK_SERVICE_ID 0x03\r
+#define MCU_GETPLLSTATUS_SERVICE_ID 0x04\r
+#define MCU_GETRESETREASON_SERVICE_ID 0x05\r
+#define MCU_GETRESETRAWVALUE_SERVICE_ID 0x06\r
+#define MCU_PERFORMRESET_SERVICE_ID 0x07\r
+#define MCU_SETMODE_SERVICE_ID 0x08\r
+#define MCU_GETVERSIONINFO_SERVICE_ID 0x09\r
+#define MCU_INTCVECTORINSTALL_SERVICE_ID 0x0A // Not in spec but follows pattern\r
+\r
+/* Development error codes */\r
+#define MCU_E_PARAM_CONFIG 0x0A\r
+#define MCU_E_PARAM_CLOCK 0x0B\r
+#define MCU_E_PARAM_MODE 0x0C\r
+#define MCU_E_PARAM_RAMSECTION 0x0D\r
+#define MCU_E_PLL_NOT_LOCKED 0x0E\r
+#define MCU_E_UNINIT 0x0F\r
+\r
+/* Specific return values */\r
+#define MCU_GETRESETRAWVALUE_NORESETREG_RV 0x00 // MCU006\r
+#define MCU_GETRESETRAWVALUE_UNINIT_RV 0xffffffff // MCU135\r
+\r
+typedef enum {\r
+ MCU_PLL_LOCKED,\r
+ MCU_PLL_UNLOCKED,\r
+ MCU_PLL_STATUS_UNDEFINED,\r
+} Mcu_PllStatusType;\r
+\r
+\r
+typedef enum {\r
+ MCU_MODE_NORMAL=0\r
+} Mcu_ModeType;\r
+\r
+//TODO\r
+typedef uint8 Mcu_RamSectionType;\r
+\r
+typedef uint32 Mcu_RawResetType;\r
+\r
+typedef enum {\r
+ MCU_POWER_ON_RESET,\r
+ MCU_WATCHDOG_RESET,\r
+ MCU_SW_RESET,\r
+ MCU_RESET_UNDEFINED\r
+} Mcu_ResetType;\r
+\r
+#include "Mcu_Cfg.h"\r
+\r
+void Mcu_Init( const Mcu_ConfigType *configPtr );\r
+void Mcu_DeInit();\r
+Std_ReturnType Mcu_InitRamSection( const Mcu_RamSectionType RamSection );\r
+Std_ReturnType Mcu_InitClock( const Mcu_ClockType ClockSetting );\r
+void Mcu_DistributePllClock( void );\r
+Mcu_PllStatusType Mcu_GetPllStatus( void );\r
+Mcu_ResetType Mcu_GetResetReason( void );\r
+Mcu_RawResetType Mcu_GetResetRawValue( void );\r
+#if ( MCU_PERFORM_RESET_API == STD_ON )\r
+void Mcu_PerformReset( void );\r
+#endif\r
+void Mcu_SetMode( const Mcu_ModeType McuMode );\r
+\r
+#if ( MCU_VERSION_INFO_API == STD_ON )\r
+#define MCU_SW_MAJOR_VERSION 1\r
+#define MCU_SW_MINOR_VERSION 0\r
+#define MCU_SW_PATCH_VERSION 0\r
+#define MCU_AR_MAJOR_VERSION 2\r
+#define MCU_AR_MINOR_VERSION 2\r
+#define MCU_AR_PATCH_VERSION 2\r
+\r
+#define Mcu_GetVersionInfo(_vi) STD_GET_VERSION_INFO(_vi,MCU)\r
+#endif\r
+\r
+typedef uint32_t imask_t;\r
+\r
+/* ecore extensions */\r
+void IntCtrl_InstallVector(void (*func)(), IrqType vector, uint8_t priority, Cpu_t cpu );\r
+void IntCtrl_GenerateSoftInt( IrqType vector );\r
+uint8_t IntCtrl_GetCurrentPriority( Cpu_t cpu);\r
+uint32_t McuE_GetSystemClock( void );\r
+#if defined(CFG_MPC55XX)\r
+uint32_t McuE_GetPeripheralClock( McuE_PeriperalClock_t type );\r
+#endif\r
+imask_t McuE_EnterCriticalSection(void);\r
+void McuE_ExitCriticalSection(imask_t old_state);\r
+void McuE_EnableInterrupts(void);\r
+void McuE_DisableInterrupts(void);\r
+\r
+\r
+\r
+#endif /*MCU_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef MEMIF_H_
+#define MEMIF_H_
+
+/* TODO: Not really know how this is connected with the rest, yet :) */
+#define MemIf_SetMode( _mode )
+#define MemIf_Read(_deviceIndex,_blockNumber,_blockOffset,_dataBufferPtr,_length)
+#define MemIf_Write(_deviceIndex,_blockNumber,_dataBufferPtr)
+#define MemIf_Cancel( _deviceIndex )
+#define MemIf_GetStatus( _deviceIndex )
+#define MemIf_GetJobResult( _deviceIndex )
+#define MemIf_InvalidateBlock( _deviceIndex, _block )
+#define MemIf_GetVersionInfo( _versionInfo )
+#define MemIf_EraseImmediateBlock( _deviceIndex,_blockNumber );
+
+#endif /*MEMIF_H_*/
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef MEMIF_TYPES_H_
+#define MEMIF_TYPES_H_
+
+typedef enum {
+
+ // The underlying abstraction module or device driver has
+ // not been initialized (yet).
+ MEMIF_UNINIT,
+ // The underlying abstraction module or device driver is
+ // currently idle.
+ MEMIF_IDLE,
+
+ // The underlying abstraction module or device driver is
+ // currently busy.
+ MEMIF_BUSY,
+
+ // The underlying abstraction module is busy with internal
+ // management operations. The underlying device driver
+ // can be busy or idle.
+ MEMIF_BUSY_INTERNAL
+} MemIf_StatusType;
+
+typedef enum {
+ //The job has been finished successfully.
+ MEMIF_JOB_OK,
+ // The job has not been finished successfully.
+ MEMIF_JOB_FAILED,
+ // The job has not yet been finished.
+ MEMIF_JOB_PENDING,
+ // The job has been cancelled.
+ MEMIF_JOB_CANCELLED,
+ // The requested block is inconsistent, it may contain
+ // corrupted data.
+ MEMIF_BLOCK_INCONSISTENT,
+ // The requested block has been marked as invalid,
+ // the requested operation can not be performed.
+ MEMIF_BLOCK_INVALID,
+
+} MemIf_JobResultType;
+
+
+typedef enum {
+ // The underlying memory abstraction modules and
+ // drivers are working in slow mode.
+ MEMIF_MODE_SLOW,
+ // The underlying memory abstraction modules and
+ // drivers are working in fast mode.
+ MEMIF_MODE_FAST,
+} MemIf_ModeType;
+
+// TODO: I have no idea where the types below are specified
+// In Eep these are defined in the header file
+// In Fls these are not found in the spec at all..
+typedef uint32 MemIf_AddressType;
+typedef uint32 MemIf_LengthType;
+
+#endif /*MEMIF_TYPES_H_*/
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/* See MemoryMapping.pdf */\r
+\r
+/* This is module include file */\r
+\r
+/* TODO:This file is crap, crap and crap.\r
+ * This assumes that you can define a section for multiple variables.\r
+ * GCC can't handle that..and hence cannot be used in the final product\r
+ */\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+//\r
+// Module Id:s from document "List of Basic Sofware Modules" Rev 1.2.1 Part of release 3.0\r
+//\r
+\r
+#ifndef _MODULES_H_\r
+#define _MODULES_H_\r
+\r
+#include "Std_Types.h"\r
+\r
+#define MODULE_ID_OS (1) // Os\r
+\r
+#define MODULE_ID_ECUM (10) // ECU state manager\r
+#define MODULE_ID_FIM (11) // Function Inhibition Manager\r
+#define MODULE_ID_COMM (12) // Communication manager\r
+#define MODULE_ID_WDGM (13) // Watchdog manager\r
+\r
+#define MODULE_ID_DET (15) // Development Error Tracer\r
+\r
+#define MODULE_ID_NVM (20) // NVRAM Manager\r
+#define MODULE_ID_FEE (21) // Flash EEPROM Emulation\r
+#define MODULE_ID_MEMIF (22) // Memory Abstraction Interface\r
+#define MODULE_ID_NM (29) // Generic networw management\r
+\r
+#define MODULE_ID_CANNM (31) // Can network management\r
+#define MODULE_ID_FRNM (32) // Flexray network management\r
+#define MODULE_ID_CANTP (35) // Can transport layer\r
+#define MODULE_ID_FRTP (36) // Flexray transport protocol\r
+\r
+#define MODULE_ID_EA (40) // EEPROM Abstraction\r
+\r
+#define MODULE_ID_WDGIF (43) // Watchdog interface\r
+\r
+#define MODULE_ID_COM (50) // Autosar COM\r
+#define MODULE_ID_PDUR (51) // PDU router\r
+#define MODULE_ID_IPDUM (52) // IPDU Multiplexer\r
+#define MODULE_ID_DCM (53) // Diagnostic Communication Manager\r
+#define MODULE_ID_DEM (54) // Diagnostic Event Manager\r
+\r
+#define MODULE_ID_CANIF (60) // CAN Interface\r
+#define MODULE_ID_FRIF (61) // Flexray interface\r
+#define MODULE_ID_LINIF (62) // LIN interface\r
+#define MODULE_ID_LINNM (63) // LIN network management\r
+\r
+#define MODULE_ID_CANTRCV (70) // Can tranceiver driver\r
+#define MODULE_ID_FRTRCV (71) // Flexray tranceiver driver\r
+\r
+#define MODULE_ID_CAN (80) // Can Driver\r
+#define MODULE_ID_FR (81) // Flexray driver\r
+#define MODULE_ID_LIN (82) // LIN Driver\r
+#define MODULE_ID_SPI (83) // SPI Handler Driver\r
+\r
+#define MODULE_ID_EEP (90) // EEPROM Driver\r
+#define MODULE_ID_FLS (92) // Flash driver\r
+#define MODULE_ID_RAMTST (93) // RAM test\r
+\r
+#define MODULE_ID_GPT (100) // GPT driver\r
+#define MODULE_ID_MCU (101) // MCU driver\r
+#define MODULE_ID_WDG (102) // Watchdog driver\r
+\r
+#define MODULE_ID_DIO (120) // Dio driver\r
+#define MODULE_ID_PWM (121) // PWM driver\r
+#define MODULE_ID_ICU (122) // ICU Driver\r
+#define MODULE_ID_ADC (123) // ADC driver\r
+#define MODULE_ID_PORT (124) // Port driver\r
+\r
+#define MODULE_ID_SCHM (130) // BSW Scheduler Module\r
+\r
+#define MODULE_ID_CANSM (140) // Can state manager\r
+#define MODULE_ID_LINSM (141) // LIN state manager\r
+#define MODULE_ID_FRSM (142) // Flexray state manager\r
+\r
+#define MODULE_ID_CRC (201) // CRC Routines\r
+\r
+#define MODULE_ID_C2CAN (220) // CAN\r
+#define MODULE_ID_C2COM (221) // COM Services\r
+#define MODULE_ID_C2DIAG (222) // Diagnostic\r
+#define MODULE_ID_C2FW (223) // ECU Firmware\r
+#define MODULE_ID_C2FR (224) // FlexRay\r
+#define MODULE_ID_C2LIN (225) // LIN\r
+#define MODULE_ID_C2MMGT (226) // Mode Management\r
+\r
+#define MODULE_ID_IO (254) // IO Hardware Abstraction\r
+#define MODULE_ID_CPLX (255) // Complex drivers\r
+\r
+#endif\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*\r
+ * (C) Copyright 2008 ecore, www.ecore.se\r
+ */\r
+\r
+#ifndef OS_H_\r
+#define OS_H_\r
+\r
+\r
+\r
+#include "Std_Types.h"\r
+#if !defined(CC_KERNEL)\r
+#include "Os_Cfg.h"\r
+#endif\r
+#include "MemMap.h"\r
+#include "Cpu.h"\r
+\r
+/* TODO: remove this... */\r
+// #include "pcb.h"\r
+/* 13.5.1 */\r
+/*\r
+typedef procid_t TaskType;\r
+typedef event_t EventMaskType;\r
+*/\r
+typedef uint32 EventMaskType;\r
+typedef EventMaskType *EventMaskRefType;\r
+typedef uint16 TaskType;\r
+typedef TaskType *TaskRefType;\r
+\r
+typedef enum {\r
+ TASK_STATE_WAITING,\r
+ TASK_STATE_READY,\r
+ TASK_STATE_SUSPENDED,\r
+ TASK_STATE_RUNNING,\r
+} TaskStateType;\r
+\r
+\r
+/*\r
+ * Macros for error handling\r
+ * Registers service id of the erroneous function and the applicable parameters\r
+ * to os_error. Functions that have less than three parameters do not touch\r
+ * os_error.param3. Same rule follows for other parameter counts.
+ */\r
+\r
+/* Error handling for functions that take no arguments */\r
+#define OS_STD_END(_service_id) \\r
+ goto ok; \\r
+ err: \\r
+ os_error.serviceId=_service_id;\\r
+ ERRORHOOK(rv); \\r
+ ok: \\r
+ return rv;\r
+\r
+/* Error handling for functions that take one argument */\r
+#define OS_STD_END_1(_service_id, _p1) \\r
+ goto ok; \\r
+ err: \\r
+ os_error.serviceId=_service_id;\\r
+ os_error.param1 = (uint32_t) _p1; \\r
+ ERRORHOOK(rv); \\r
+ ok: \\r
+ return rv;\r
+\r
+/* Error handling for functions that take two arguments */\r
+#define OS_STD_END_2(_service_id, _p1,_p2) \\r
+ goto ok; \\r
+ err: \\r
+ os_error.serviceId=_service_id;\\r
+ os_error.param1 = (uint32_t) _p1; \\r
+ os_error.param2 = (uint32_t) _p2; \\r
+ ERRORHOOK(rv); \\r
+ ok: \\r
+ return rv;\r
+\r
+/* Error handling for functions that take three arguments */\r
+#define OS_STD_END_3(_service_id,_p1,_p2,_p3) \\r
+ goto ok; \\r
+ err: \\r
+ os_error.serviceId=_service_id;\\r
+ os_error.param1 = (uint32_t) _p1; \\r
+ os_error.param2 = (uint32_t) _p2; \\r
+ os_error.param3 = (uint32_t) _p3; \\r
+ ERRORHOOK(rv); \\r
+ ok: \\r
+ return rv;\r
+\r
+\r
+typedef TaskStateType *TaskStateRefType;\r
+\r
+/* FIXME: OSMEMORY_IS__ , see 8.2*/\r
+\r
+\r
+#define INVALID_OSAPPLICATION (-1)\r
+\r
+/* TODO, I have no idea what this should be*/\r
+typedef sint32 ApplicationType;\r
+\r
+/* See oil config for defines */\r
+typedef sint32 AppModeType;\r
+\r
+/* FIXME: more types here */\r
+typedef uint16 ScheduleTableType;\r
+typedef uint16 GlobalTimeTickType;\r
+\r
+\r
+typedef enum {\r
+ SCHEDULETABLE_STOPPED,\r
+ SCHEDULETABLE_NEXT,\r
+ SCHEDULETABLE_WAITING,\r
+ SCHEDULETABLE_RUNNING,\r
+ SCHEDULETABLE_RUNNING_AND_SYNCHRONOUS\r
+} ScheduleTableStatusType;\r
+\r
+typedef ScheduleTableStatusType *ScheduleTableStatusRefType;\r
+\r
+/* Flags for AccessType */\r
+#define ACCESSTYPE_W 1\r
+#define ACCESSTYPE_R (1<<1)\r
+\r
+typedef uint32 AccessType;\r
+\r
+typedef enum {\r
+ ACCESS,\r
+ NO_ACCESS\r
+} ObjectAccessType;\r
+\r
+typedef enum {\r
+ OBJECT_TASK,\r
+ OBJECT_ISR,\r
+ OBJECT_ALARM,\r
+ OBJECT_RESOURCE,\r
+ OBJECT_COUNTER,\r
+ OBJECT_SCHEDULETABLE,\r
+ OBJECT_MESSAGE\r
+} ObjectTypeType;\r
+\r
+typedef enum {\r
+ PRO_KILLTASKISR,\r
+ PRO_KILLAPPL,\r
+ PRO_KILLAPPL_RESTART,\r
+ PRO_SHUTDOWN\r
+} ProtectionReturnType;\r
+\r
+typedef enum {\r
+ RESTART,\r
+ NO_RESTART\r
+} RestartType;\r
+\r
+\r
+typedef ProtectionReturnType (*ProtectionHookType)( StatusType);\r
+typedef void (*StartupHookType)( void );\r
+typedef void (*ShutdownHookType)( StatusType );\r
+typedef void (*ErrorHookType)( StatusType );\r
+typedef void (*PreTaskHookType)( void );\r
+typedef void (*PostTaskHookType)( void );\r
+\r
+ProtectionReturnType ProtectionHook( StatusType FatalError );\r
+void StartupHook( void );\r
+void ShutdownHook( StatusType Error );\r
+void ErrorHook( StatusType Error );\r
+void PreTaskHook( void );\r
+void PostTaskHook( void );\r
+\r
+typedef uint16 TrustedFunctionIndexType;\r
+typedef void * TrustedFunctionParameterRefType;\r
+\r
+\r
+/* See 8.3.9 */\r
+#define INVALID_ISR ((sint16)(-1))\r
+typedef sint16 ISRType;\r
+\r
+typedef void * MemoryStartAddressType;\r
+typedef uint32 MemorySizeType;\r
+\r
+//#define WaitEvent(...) _WaitEvent(__VA_ARGS__)\r
+#if 0\r
+#define WaitEvent(...) SC_CALL(WaitEvent,1,1,__VA_ARGS__)\r
+#define SetEvent(...) SC_CALL(SetEvent,2,2,__VA_ARGS__)\r
+#define ClearEvent(...) SC_CALL(ClearEvent,3,1,__VA_ARGS__)\r
+#endif\r
+StatusType WaitEvent( EventMaskType Mask );\r
+StatusType SetEvent( TaskType TaskID, EventMaskType Mask );\r
+StatusType ClearEvent( EventMaskType Mask);\r
+StatusType GetEvent( TaskType TaskId, EventMaskRefType Mask);\r
+\r
+\r
+ApplicationType GetApplicationID( void );\r
+ISRType GetISRID( void );\r
+\r
+\r
+#define EnableAllInterrupts() Irq_Enable()\r
+#define DisableAllInterrupts() Irq_Disable()\r
+#define ResumeAllInterrupts() Irq_Enable()\r
+#define SuspendAllInterrupts() Irq_Disable()\r
+#define ResumeOSInterrupts() Irq_Enable()\r
+#define SuspendOSInterrupts() Irq_Disable()\r
+\r
+#if 0\r
+void EnableAllInterrups( void ) Irq_Enable()\r
+void DisableAllInterrupts( void ) Irq_Disable()\r
+void ResumeAllInterrupts( void ) Irq_Enable()\r
+void SuspendAllInterrupts( void ) Irq_Disable()\r
+void ResumeOSInterrupts( void ) Irq_Enable()\r
+void SuspendOSInterrupts( void ) Irq_Disable()\r
+#endif\r
+\r
+StatusType EnableInterruptSource( ISRType EnableISR );\r
+StatusType DisableInterruptSource( ISRType EnableISR );\r
+\r
+\r
+ApplicationType GetApplicationID( void );\r
+ISRType GetISRID( void );\r
+AccessType CheckISRMemoryAccess( ISRType ISRID,\r
+ MemoryStartAddressType Address,\r
+ MemorySizeType Size );\r
+\r
+AccessType CheckTaskMemoryAccess( TaskType TaskID,\r
+ MemoryStartAddressType Address,\r
+ MemorySizeType Size );\r
+void InitOS( void );\r
+void StartOS( AppModeType Mode );\r
+\r
+StatusType CallTrustedFunction( TrustedFunctionIndexType FunctionIndex,\r
+ TrustedFunctionParameterRefType FunctionParams );\r
+\r
+StatusType GetTaskID( TaskRefType TaskID );\r
+StatusType GetTaskState(TaskType task_id, TaskStateRefType state);\r
+\r
+void ShutdownOS( StatusType );\r
+StatusType ActivateTask( TaskType TaskID );\r
+StatusType TerminateTask( void );\r
+StatusType ChainTask( TaskType TaskID );\r
+StatusType Schedule( void );\r
+\r
+/* TODO: This def. is wrong wrong wrong */\r
+\r
+/* Hmm, OS188 indicates that we must have a locking time here ..*/\r
+/* and we at least have prio here */\r
+//typedef const uint32 ResourceType;\r
+#if 0\r
+\r
+#define DeclareResource(x) extern ResourceType *(x);\r
+\r
+StatusType GetResource( ResourceType *ResID );\r
+StatusType ReleaseResource( ResourceType *ResID);\r
+\r
+#else\r
+\r
+typedef uint32 ResourceType;\r
+#define DeclareResource(x) extern ResourceType (x);\r
+StatusType GetResource( ResourceType ResID );\r
+StatusType ReleaseResource( ResourceType ResID);\r
+\r
+#endif\r
+\r
+#define RES_SCHEDULER 0\r
+//DeclareResource(RES_SCHEDULER);\r
+\r
+typedef struct OsDriver_s {\r
+ int OsGptChannelRef;\r
+} OsDriver;\r
+\r
+/*-------------------------------------------------------------------\r
+ * Free running timer\r
+ *-----------------------------------------------------------------*/\r
+void Frt_Init( void );\r
+void Frt_Start(uint32_t period_ticks);\r
+uint32_t Frt_GetTimeElapsed( void );\r
+\r
+/*-------------------------------------------------------------------\r
+ * Counters\r
+ *-----------------------------------------------------------------*/\r
+typedef uint16 CounterType;\r
+\r
+typedef uint32 TickType;\r
+typedef TickType *TickRefType;\r
+\r
+StatusType IncrementCounter( CounterType );\r
+StatusType GetCounterValue( CounterType, TickRefType );\r
+StatusType GetElapsedCounterValue( CounterType, TickRefType val, TickRefType elapsed_val);\r
+\r
+/*-------------------------------------------------------------------\r
+ * Schedule Tables\r
+ *-----------------------------------------------------------------*/\r
+\r
+StatusType StartScheduleTableRel(ScheduleTableType sid, TickType offset);\r
+StatusType StartScheduleTableAbs(ScheduleTableType sid, TickType val );\r
+StatusType StartScheduleTableSynchron(ScheduleTableType sid );\r
+StatusType StopScheduleTable(ScheduleTableType sid);\r
+StatusType NextScheduleTable( ScheduleTableType sid_curr, ScheduleTableType sid_next);\r
+StatusType SyncScheduleTable( ScheduleTableType sid, GlobalTimeTickType global_time );\r
+StatusType GetScheduleTableStatus( ScheduleTableType sid, ScheduleTableStatusRefType status );\r
+StatusType SetScheduleTableAsync( ScheduleTableType sid );\r
+\r
+\r
+/*-------------------------------------------------------------------\r
+ * Alarms\r
+ *-----------------------------------------------------------------*/\r
+\r
+typedef uint16 AlarmType;\r
+\r
+typedef struct {\r
+ TickType maxallowedvalue;\r
+ TickType tickperbase;\r
+ TickType mincycle;\r
+} AlarmBaseType;\r
+\r
+typedef AlarmBaseType *AlarmBaseRefType;\r
+\r
+StatusType GetAlarmBase( AlarmType AlarmId, AlarmBaseRefType Info );\r
+StatusType GetAlarm(AlarmType AlarmId, TickRefType Tick);\r
+StatusType SetRelAlarm(AlarmType AlarmId, TickType Increment, TickType Cycle);\r
+StatusType SetAbsAlarm(AlarmType AlarmId, TickType Start, TickType Cycle);\r
+StatusType CancelAlarm(AlarmType AlarmId);\r
+\r
+\r
+/*-------------------------------------------------------------------\r
+ * Error's\r
+ *-----------------------------------------------------------------*/\r
+typedef enum {\r
+ OSServiceId_ActivateTask,\r
+ OSServiceId_TerminateTask,\r
+ OSServiceId_ChainTask,\r
+ OSServiceId_Schedule,\r
+ OSServiceId_GetTaskID,\r
+ OSServiceId_GetResource,\r
+ OSServiceId_ReleaseResource,\r
+ OSServiceId_SetEvent,\r
+ OSServiceId_ClearEvent,\r
+ OSServiceId_GetEvent,\r
+ OSServiceId_WaitEvent,\r
+ OSServiceId_GetAlarmBase,\r
+ OSServiceId_GetAlarm,\r
+ OSServiceId_SetRelAlarm,\r
+ OSServiceId_SetAbsAlarm,\r
+ OSServiceId_CancelAlarm,\r
+ OSServiceId_StartOS,\r
+ OSServiceId_ShutdownOS,\r
+ OSServiceId_ErrorHook,\r
+ OSServiceId_PreTaskHook,\r
+ OSServiceId_PostTaskHook,\r
+ OSServiceId_StartupHook,\r
+ OSServiceId_ShutdownHook,\r
+ OSServiceId_GetTaskState,\r
+} OsServiceIdType;;\r
+\r
+typedef struct os_error_s {\r
+ OsServiceIdType serviceId;\r
+ uint32_t param1;\r
+ uint32_t param2;\r
+ uint32_t param3;\r
+} os_error_t;\r
+\r
+extern os_error_t os_error;\r
+\r
+// TODO: Add the service id to all OS service methods.\r
+static inline OsServiceIdType OSErrorGetServiceId(void) {\r
+ return os_error.serviceId;\r
+}\r
+\r
+extern os_error_t os_error;\r
+\r
+#define OSError_ActivateTask_TaskID ((TaskType) os_error.param1)\r
+#define OSError_ChainTask_TaskID ((TaskType) os_error.param1)\r
+#define OSError_GetTaskID_TaskID ((TaskRefType) os_error.param1)\r
+#define OSError_GetResource_ResID ((ResourceType) os_error.param1)\r
+#define OSError_ReleaseResource_ResID ((ResourceType) os_error.param1)\r
+#define OSError_SetEvent_TaskID ((TaskType) os_error.param1)\r
+#define OSError_SetEvent_Mask ((EventMaskType) os_error.param2)\r
+#define OSError_ClearEvent_Mask ((EventMaskType) os_error.param1)\r
+#define OSError_GetEvent_TaskId ((TaskType) os_error.param1)\r
+#define OSError_GetEvent_Mask ((EventMaskRefType) os_error.param2)\r
+#define OSError_WaitEvent_Mask ((EventMaskType) os_error.param1)\r
+#define OSError_GetAlarmBase_AlarmId ((AlarmType) os_error.param1)\r
+#define OSError_GetAlarmBase_Info ((AlarmBaseRefType) os_error.param2)\r
+#define OSError_GetAlarm_AlarmId ((AlarmType) os_error.param1)\r
+#define OSError_GetAlarm_Tick ((TickRefType) os_error.param2)\r
+#define OSError_SetRelAlarm_AlarmId ((AlarmType) os_error.param1)\r
+#define OSError_SetRelAlarm_Increment ((TickType) os_error.param2)\r
+#define OSError_SetRelAlarm_Cycle ((TickType) os_error.param3)\r
+#define OSError_SetAbsAlarm_AlarmId ((AlarmType) os_error.param1)\r
+#define OSError_SetAbsAlarm_Start ((TickType) os_error.param2)\r
+#define OSError_SetAbsAlarm_Cycle ((TickType) os_error.param3)\r
+#define OSError_CancelAlarm_AlarmId ((AlarmType) os_error.param1)\r
+#define OSError_StartOS_Mode ((AppModeType) os_error.param1)\r
+#define OSError_ErrorHook_Error ((StatusType) os_error.param1)\r
+#define OSError_ShutdownHook_Error ((StatusType) os_error.param1)\r
+#define OSError_GetTaskState_TaskId ((TaskType) os_error.param1)\r
+#define OSError_GetTaskState_State ((TaskStateRefType) os_error.param2)\r
+\r
+/*-------------------------------------------------------------------\r
+ * COM ( TODO : move )\r
+ *-----------------------------------------------------------------*/\r
+\r
+/*\r
+ * The only information about the COM that is valid is\r
+ * in the COM specification ..SWS_COM.pdf.\r
+ *\r
+ * The most important requirements are COM010 and COM013\r
+ *\r
+ * Com_Init()\r
+ * Com_DeInit()\r
+ *\r
+ * No error hooks..\r
+ * No. GetMessageStatus()\r
+ * No. SendZeroMessage()\r
+ * No. SendDynamicMessage(), RecieveDynamicMessage()\r
+ *\r
+ * Yes. SendMessage()\r
+ *\r
+ * */\r
+\r
+\r
+typedef uint32 MessageType;\r
+typedef void *ApplicationDataRef;\r
+\r
+\r
+StatusType SendMessage( MessageType message_id, ApplicationDataRef dataRef );\r
+StatusType ReceiveMessage( MessageType message_id, ApplicationDataRef dataRef );\r
+\r
+/*\r
+ * ecore extensions\r
+ */\r
+TickType GetOsTick();\r
+void OsTick(void);\r
+void OsIdle(void);\r
+\r
+/* The OS always have counter 0 */\r
+#define OS_TICK_COUNTER 0\r
+\r
+// Generate conversion macro'\r
+// Todo\r
+#define OS_TICK2NS_OS_TICK_COUNTER(_x)\r
+#define OS_TICK2US_OS_TICK_COUNTER(_x)\r
+#define OS_TICK2MS_OS_TICK_COUNTER(_x)\r
+#define OS_TICK2SEC_OS_TICK_COUNTER(_x)\r
+\r
+#define OS_ISR_TYPE2 0\r
+#define OS_ISR_TYPE1 1\r
+\r
+union isr_attr {\r
+ TaskType tid;\r
+ void (*entry)(void);\r
+};\r
+\r
+typedef struct StackInfo_s {\r
+ void *at_swap; // This task was swapped in with this stack\r
+ void *top; // Top of the stack\r
+ int size; // Size of the stack\r
+\r
+ void *curr; // current stack ptr\r
+ void *usage; // Usage in %\r
+} StackInfoType;\r
+\r
+void Os_GetStackInfo( TaskType pid, StackInfoType *s );\r
+\r
+#define OS_STACK_USAGE(_x) ((((_x)->size - (uint32_t)((_x)->usage - (_x)->top))*100)/(_x)->size)\r
+\r
+int simple_printf(const char *format, ...);\r
+\r
+#define ARRAY_SIZE(_x) sizeof(_x)/sizeof((_x)[0])\r
+\r
+#define OS_STR__(x) #x\r
+#define OS_STRSTR__(x) STR__(x)\r
+\r
+\r
+TaskType Os_CreateIsr( void (*entry)(void), uint8_t prio, const char *name );\r
+void IntCtrl_AttachIsr1( void (*entry)(void), void *int_ctrl, uint32_t vector,uint8_t prio);\r
+void IntCtrl_AttachIsr2(TaskType tid,void *int_ctrl, uint32_t vector );\r
+\r
+\r
+#endif /*OS_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef _PLATFORM_TYPES_H_\r
+#define _PLATFORM_TYPES_H_\r
+\r
+#define CPU_TYPE CPU_TYPE_32 \r
+#define CPU_BIT_ORDER MSB_FIRST \r
+#define CPU_BYTE_ORDER HIGH_BYTE_FIRST\r
+\r
+#define FALSE 0\r
+#define TRUE 1\r
+\r
+typedef unsigned long boolean; \r
+typedef signed char sint8; \r
+typedef unsigned char uint8; \r
+typedef signed short sint16; \r
+typedef unsigned short uint16; \r
+typedef signed long sint32; \r
+typedef unsigned long uint32; \r
+typedef unsigned long long uint64;\r
+typedef unsigned long uint8_least; \r
+typedef unsigned long uint16_least; \r
+typedef unsigned long uint32_least; \r
+typedef signed long sint8_least; \r
+typedef signed long sint16_least; \r
+typedef signed long sint32_least; \r
+typedef float float32; \r
+typedef double float64; \r
+\r
+#endif\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef PORT_H_\r
+#define PORT_H_\r
+\r
+#include "Port_Cfg.h"\r
+#if PORT_VERSION_INFO_API == STD_ON\r
+\r
+#define PORT_SW_MAJOR_VERSION 1 \r
+#define PORT_SW_MINOR_VERSION 0 \r
+#define PORT_SW_PATCH_VERSION 0 \r
+#define PORT_AR_MAJOR_VERSION 3\r
+#define PORT_AR_MINOR_VERSION 0 \r
+#define PORT_AR_PATCH_VERSION 2 \r
+\r
+void Port_GetVersionInfo( Std_VersionInfoType *versionInfo );\r
+#endif \r
+\r
+#define PORT_E_PARAM_PIN 0x0a\r
+#define PORT_E_DIRECTION_UNCHANGEABLE 0x0b\r
+#define PORT_E_PARAM_CONFIG 0x0c\r
+#define PORT_E_PARAM_INVALID_MODE 0x0d\r
+#define PORT_E_MODE_UNCHANGEABLE 0x0e\r
+#define PORT_E_UNINIT 0x0f\r
+\r
+#define PORT_INIT_ID 0x00\r
+#define PORT_SET_PIN_DIRECTION_ID 0x01\r
+#define PORT_REFRESH_PORT_DIRECTION_ID 0x02\r
+#define PORT_GET_VERSION_INFO_ID 0x03\r
+#define PORT_SET_PIN_MODE_ID 0x04\r
+\r
+/*\r
+ * PORT046: The type Port_PinDirectionType is a type for defining the direction of a Port Pin. \r
+ * PORT_PIN_IN Sets port pin as input. \r
+ * PORT_PIN_OUT Sets port pin as output. \r
+ */\r
+typedef enum\r
+{\r
+ PORT_PIN_IN = 0,\r
+ PORT_PIN_OUT,\r
+} Port_PinDirectionType;\r
+\r
+typedef uint32 Port_PinModeType;\r
+typedef enum\r
+{\r
+ PORT_UNINITIALIZED = 0,\r
+ PORT_INITIALIZED,\r
+} Port_StateType;\r
+\r
+void Port_Init( const Port_ConfigType *configType );\r
+void Port_SetPinDirection( Port_PinType pin, Port_PinDirectionType direction );\r
+void Port_RefreshPortDirection( void );\r
+void Port_SetPinMode( Port_PinType Pin, Port_PinModeType Mode );\r
+\r
+#endif /*PORT_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*
+ * Pwm.h
+ *
+ * Created on: 2009-jul-09
+ * Author: nian
+ */
+
+#ifndef PWM_H_
+#define PWM_H_
+
+// Channel configuration macro.
+#define PWM_CHANNEL_CONFIG(_hwchannel, _period, _duty, _prescaler, _polarity) \
+ {\
+ .channel = _hwchannel,\
+ .r = {\
+ DUTY_AND_PERIOD(_duty, _period),\
+ .freezeEnable = 1,\
+ .outputDisable = 0,\
+ .usePrescaler = 1,\
+ .prescaler = _prescaler,\
+ .useDma = 0,\
+ .flagEnable = 0, /* See PWM052 */ \
+ .busSelect = 3, /* Use the internal counter bus */\
+ .edgePolarity = _polarity,\
+ .mode = PWM_EMIOS_OPWM\
+ }\
+ }
+
+/*
+ * PWM094: Std_VersionInfoType shall be imported from Std_Types.h
+ */
+#include "Std_Types.h"
+#include "Pwm_Cfg.h"
+
+/*
+ * PWM003: The detection of development errors is configurable (ON/OFF) at pre-
+ * compile time. The switch PwmDevErorDetect shall activate or deactivate the
+ * detection of all development errors.
+ *
+ * PWM064: If the PwmDevErorDetect switch is enabled, API parameter checking is
+ * enabled.
+ *
+ * PWM078: Detected development errors shall be reported to the Det_ReportError
+ * service of the Development Error Tracer (DET) if the pre-processor
+ * PwmDevErorDetect is set.
+ */
+#if PWM_DEV_EROR_DETECT==ON
+# define Pwm_ReportError(ErrorId) Det_ReportError( MODULE_ID_PWM, 0, 0, ErrorId);
+#else
+# define Pwm_ReportError(ErrorId)
+#endif
+
+/**************************************************************
+ * Type definitions
+ **************************************************************/
+// PWM002: Development error values are of type uint8
+typedef uint8 Pwm_ErrorType;
+
+/*
+ * PWM058: The width of the duty cycle parameter is 16 bits
+ *
+ * PWM059: The PWM module shall comply with the following scaling scheme
+ * for the duty cycle:
+ * 0x0 = 0%,
+ * 0x8000 = 100% */
+typedef uint16 Pwm_DutyCycleType;
+
+#define Pwm_100_Procent 0x8000
+#define Pwm_0_Procent 0
+
+/*
+ * PWM106: This is implementation specific but not all values may be valid
+ * within the type. This shall be chosen in order to have the most efficient
+ * implementation on a specific microcontroller platform.
+ *
+ * PWM106 => Pwm_ChannelType == eemios channel id.
+ */
+typedef uint8 Pwm_ChannelType;
+
+/*
+ * PWM070: All time units used within the API services of the PWM module shall
+ * be of the unit ticks.
+ */
+typedef uint16 Pwm_PeriodType;
+
+typedef enum {
+ PWM_LOW, PWM_HIGH
+} Pwm_OutputStateType;
+
+typedef enum {
+ PWM_FALLING_EDGE=PWM_LOW, PWM_RISING_EDGE = PWM_HIGH, PWM_BOTH_EDGES
+} Pwm_EdgeNotificationType;
+#define PWM_NO_EDGES (PWM_BOTH_EDGES + 1)
+
+typedef enum {
+ PWM_VARIABLE_PERIOD, PWM_FIXED_PERIOD, PWM_FIXED_PERIOD_SHIFTED
+} Pwm_ChannelClassType;
+
+typedef void (*Pwm_NotificationHandlerType)();
+
+//#define Pwm_ChannelConfiguration(DefaultPeriod)
+
+typedef enum {
+ PWM_CHANNEL_PRESCALER_1=0,
+ PWM_CHANNEL_PRESCALER_2,
+ PWM_CHANNEL_PRESCALER_3,
+ PWM_CHANNEL_PRESCALER_4,
+} Pwm_ChannelPrescalerType;
+
+/*
+ * Since the AUTOSAR PWM specification uses a different unit for the duty,
+ * the following macro can be used to convert between that format and the
+ * mpc5516 format.
+ */
+#define DUTY_AND_PERIOD(_duty,_period) .duty = (_duty*_period)>>15, .period = _period
+
+#if defined(CFG_MPC5516)
+ /* Mode is buffered PWM output (OPWM) */
+ /* Mode is buffered Output PW and frequency modulation mode */
+#define PWM_EMIOS_OPWM 0x5A
+#elif defined(CFG_MPC5567)
+ /* Mode is buffered OPWM with frequency modulation (allows change of
+ * period) */
+#define PWM_EMIOS_OPWM 0x19
+#endif
+
+
+typedef struct {
+ /* Number of duty ticks */
+ uint32_t duty:32;
+ /* Length of period, in ticks */
+ uint32_t period:32;
+ /* Counter */
+ uint32_t counter:32;
+ /* Enable freezing the channel when in debug mode */
+ uint32_t freezeEnable:1;
+ /* Disable output */
+ uint32_t outputDisable:1;
+ /* Select which bus disables the bus
+ * TODO: Figure out how this works, i.e. what bus does it refer to? */
+ uint32_t outputDisableSelect:2;
+ /* Prescale the emios clock some more? */
+ Pwm_ChannelPrescalerType prescaler:2;
+ /* Prescale the emios clock some more? */
+ uint32_t usePrescaler:1;
+ /* Whether to use DMA. Currently unsupported */
+ uint32_t useDma:1;
+ uint32_t reserved_2:1;
+ /* Input filter. Ignored in output mode. */
+ uint32_t inputFilter:4;
+ /* Input filter clock source. Ignored in output mode */
+ uint32_t filterClockSelect:1;
+ /* Enable interrupts/flags on this channel? Required for DMA as well. */
+ uint32_t flagEnable:1;
+ uint32_t reserved_3:3;
+ /* Trigger a match on channel A */
+ uint32_t forceMatchA:1;
+ /* Triggers a match on channel B */
+ uint32_t forceMatchB:1;
+ uint32_t reserved_4:1;
+ /* We can use different buses for the counter. Use the internal counter */
+ uint32_t busSelect:2;
+ /* What edges to flag on? */
+ uint32_t edgeSelect:1;
+ /* Polarity of the channel */
+ uint32_t edgePolarity:1;
+ /* EMIOS mode. 0x58 for buffered output PWM */
+ uint32_t mode:7;
+} Pwm_ChannelRegisterType;
+
+typedef struct {
+ Pwm_ChannelRegisterType r;
+ Pwm_ChannelType channel;
+} Pwm_ChannelConfigurationType;
+
+typedef struct {
+ Pwm_ChannelConfigurationType Channels[PWM_NUMBER_OF_CHANNELS];
+#if PWM_NOTIFICATION_SUPPORTED==ON
+ Pwm_NotificationHandlerType NotificationHandlers[PWM_NUMBER_OF_CHANNELS];
+#endif
+} Pwm_ConfigType;
+
+extern const Pwm_ConfigType PwmConfig;
+
+/*
+ * With MPC551x, only the first 16 eMIOS channels are of the usable class for
+ * hardware PWM.
+ */
+#if PWM_NUMBER_OF_CHANNELS > 16
+#error "PWM_NUMBER_OF_CHANNELS is larger than supported by the target platform."
+#endif
+
+#if PWM_DUTYCYCLE_UPDATED_ENDPERIOD!=ON
+#error "Unbuffered PWM currently not supported by this driver."
+#endif
+
+/*
+ * Constants
+ *****************/
+
+/* Pwm_Init called with the wrong parameter */
+//const Pwm_ErrorType PWM_E_PARAM_CONFIG = 0x10;
+#define PWM_E_PARAM_CONFIG 0x10
+
+/* PWM is not initialized yet */
+//const Pwm_ErrorType PWM_E_UNINIT = 0x11;
+#define PWM_E_UNINIT 0x11
+
+/* Invalid PWM channel identifier */
+//const Pwm_ErrorType PWM_E_PARAM_CHANNEL = 0x12;
+#define PWM_E_PARAM_CHANNEL 0x12
+
+/* Use of unauthorized service on PWM channel configured fixed period */
+//const Pwm_ErrorType PWM_E_PERIOD_UNCHANGEABLE = 0x13;
+#define PWM_E_PERIOD_UNCHANGEABLE 0x13
+
+/* Pwm_Init called when already initialized */
+//const Pwm_ErrorType PWM_E_ALREADY_INITIALIZED = 0x14;
+#define PWM_E_ALREADY_INITIALIZED 0x14
+
+/*
+ * Implemented functions
+ ****************************/
+void Pwm_Init(const Pwm_ConfigType* ConfigPtr);
+void Pwm_DeInit();
+void Pwm_GetVersionInfo(Std_VersionInfoType* VersionInfo);
+#if PWM_SET_PERIOD_AND_DUTY==ON
+void Pwm_SetPeriodAndDuty(Pwm_ChannelType Channel, Pwm_PeriodType Period,
+ Pwm_DutyCycleType DutyCycle);
+#endif
+
+void Pwm_SetDutyCycle(Pwm_ChannelType Channel, Pwm_DutyCycleType DutyCycle);
+void Pwm_SetOutputToIdle(Pwm_ChannelType ChannelNumber);
+/*
+ * PWM085: The function Pwm_GetOutputState shall be pre compile configurable
+ * ON/OFF by the configuration parameter PwmGetOutputState
+ */
+#if PWM_GET_OUTPUT_STATE==ON
+Pwm_OutputStateType Pwm_GetOutputState(Pwm_ChannelType Channel);
+#endif
+
+/*
+ * PWM113: The function EnableNotification shall be pre compile configurable
+ * ON/OFF by the configuration parameter PwmNotificationSupported
+ *
+ * PWM112: The function DisableNotification shall be pre compile configurable
+ * ON/OFF by the configuration parameter PwmNotificationSupported
+ */
+#if PWM_NOTIFICATION_SUPPORTED==ON
+void Pwm_DisableNotification(Pwm_ChannelType Channel);
+void Pwm_EnableNotification(Pwm_ChannelType ChannelNumber,
+ Pwm_EdgeNotificationType Notification);
+#endif
+
+#endif /* PWM_H_ */
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*\r
+ * Ramlog.h\r
+ *\r
+ * Created on: 2009-apr-19\r
+ * Author: mahi\r
+ */\r
+\r
+#ifndef RAMLOG_H_\r
+#define RAMLOG_H_\r
+\r
+#include "xtoa.h"\r
+\r
+void ramlog_puts( char *str );\r
+\r
+/*\r
+ * Fast ramlog functions
+ */\r
+static inline void ramlog_str( char *str ) {\r
+ ramlog_puts(str);\r
+}\r
+\r
+static inline void ramlog_dec( int val ) {\r
+ char str[10]; // include '-' and \0\r
+ ultoa(val,str,10);\r
+ ramlog_str(str);\r
+}\r
+\r
+static inline void ramlog_hex( uint32_t val ) {\r
+ char str[10]; // include '-' and \0\r
+ ultoa(val,str,16);\r
+ ramlog_str(str);\r
+}\r
+\r
+/*\r
+ * var args ramlog functions\r
+ */\r
+int ramlog_printf(const char *format, ...);\r
+\r
+#endif /* RAMLOG_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+\r
+#ifndef RTE_H_\r
+#define RTE_H_\r
+\r
+\r
+\r
+/* Contract \r
+ * rte_sws_1143\r
+ * <name>_<c>_<p>_<o>\r
+ * <p> - port name, e.g \r
+ * <c> - component name, e.g. doors, lights\r
+ * <o> - operation name or element name\r
+ *\r
+ * and more \r
+ * Rte_Pim?\r
+ * Rte_CData?\r
+ */\r
+\r
+/* \r
+ * Generated, rte_sws_3730(p.154)\r
+ */\r
+#define Rte_Send_p_d\r
+#define Rte_Switch_p_m\r
+#define Rte_Write_p_d\r
+#define Rte_Invalidate_p_d\r
+#define Rte_Feedback_p_d\r
+#define Rte_Read_p_d\r
+#define Rte_Receive_p_d\r
+#define Rte_Call_p_o\r
+#define Rte_Result_p_o\r
+#define Rte_Mode_p_o\r
+\r
+\r
+// Errors\r
+typedef uint8 Std_ReturnType;\r
+#define RTE_E_OK ((Std_ReturnType) 0)\r
+#define RTE_E_INVALID ((Std_ReturnType) 1)\r
+#define RTE_E_COMMS_ERROR ((Std_ReturnType) 128)\r
+#define RTE_E_TIMEOUT ((Std_ReturnType) 129)\r
+#define RTE_E_LIMIT ((Std_ReturnType) 130)\r
+#define RTE_E_NO_DATA ((Std_ReturnType) 131)\r
+#define RTE_E_TRANSMIT_ACK ((Std_ReturnType) 132)\r
+// Overlayd errors\r
+#define RTE_E_LOST_DATA ((Std_ReturnType) 64)\r
+#define RTE_E_MAX_AGE_EXCEEDED ((Std_ReturnType) 64)\r
+\r
+\r
+// RTE Mode, TODO\r
+\r
+// Rte_Ports\r
+#define Rte_PortHandle_i_RP\r
+#define Rte_Ports_i_RP\r
+\r
+// Rte_NPorts\r
+#define Rte_NPorts_i_RP\r
+\r
+// Rte_Port\r
+//#define Rte_PortHandle_i_RP\r
+#define Rte_Port_RP\r
+\r
+// Rte_Send/Rte_Write/Rte_Switch\r
+#define Rte_Write_p_o\r
+#define Rte_Send_p_o\r
+#define Rte_Swich_p_o\r
+\r
+// Rte_Invalidate\r
+#define Rte_Invalidate_p_o\r
+\r
+// Rte_Feedback\r
+#define Rte_Feedback_p_o\r
+\r
+// Rte_Read\r
+#define Rte_Read_p_o\r
+\r
+// Rte_Receive\r
+#define Rte_Receive_p_o\r
+\r
+// Rte_Call\r
+#define Rte_Call_p_o\r
+\r
+// Rte_Result\r
+#define Rte_Result_p_o\r
+\r
+//Rte_Pim\r
+#define Rte_Pim_name\r
+\r
+// Rte_CData\r
+#define Rte_CData_name\r
+\r
+// Rte_IRead\r
+#define Rte_IRead_re_p_d\r
+\r
+// Rte_IWrite\r
+#define Rte_IWrite_re_p_d\r
+\r
+// Rte_IInvalidate\r
+#define Rte_IInvalidate_re_p_d\r
+\r
+// Rte_IStatus\r
+#define Rte_IStatus_re_p_d\r
+\r
+// Rte_IrvIRead\r
+#define Rte_IrvIRead_re_name\r
+\r
+// TODO: bla bla bla .. more methods\r
+//\r
+\r
+\r
+// RTE Lifecycle API reference.( see chap 5.8 )\r
+Std_ReturnType Rte_Start( void );\r
+Std_ReturnType Rte_Stop( void );\r
+\r
+#endif /*RTE_H_*/\r
+\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef SPI_H_
+#define SPI_H_
+
+#include "Std_Types.h"
+
+/* Standard info */
+#define SPI_VENDOR_ID 1
+#define SPI_MODULE_ID MODULE_ID_SPI
+#define SPI_SW_MAJOR_VERSION 1
+#define SPI_SW_MINOR_VERSION 0
+#define SPI_SW_PATCH_VERSION 2
+#define SPI_AR_MAJOR_VERSION 2
+#define SPI_AR_MINOR_VERSION 2
+#define SPI_AR_PATCH_VERSION 2
+
+
+/* --- Service IDs --- */
+#define SPI_INIT_SERVICE_ID 0x00
+#define SPI_DEINIT_SERVICE_ID 0x01
+#define SPI_WRITEIB_SERVICE_ID 0x02
+#define SPI_ASYNCTRANSMIT_SERVICE_ID 0x03
+#define SPI_READIB_SERVICE_ID 0x04
+#define SPI_SETUPEB_SERVICE_ID 0x05
+#define SPI_GETSTATUS_SERVICE_ID 0x06
+#define SPI_GETJOBRESULT_SERVICE_ID 0x07
+#define SPI_GETSEQUENCERESULT_SERVICE_ID 0x08
+#define SPI_GETVERSIONINFO_SERVICE_ID 0x09
+#define SPI_SYNCTRANSMIT_SERVICE_ID 0x0A
+#define SPI_GETHWUNITSTATUS_SERVICE_ID 0x0B
+#define SPI_CANCEL_SERVICE_ID 0x0C
+#define SPI_SETASYNCMODE_SERVICE_ID 0x0D
+
+/* --- Error codes --- */
+#define SPI_E_PARAM_CHANNEL 0x0A
+#define SPI_E_PARAM_JOB 0x0B
+#define SPI_E_PARAM_SEQ 0x0C
+#define SPI_E_PARAM_LENGTH 0x0D
+#define SPI_E_PARAM_UNIT 0x0E
+#define SPI_E_UNINIT 0x1A
+#define SPI_E_SEQ_PENDING 0x2A
+#define SPI_E_SEQ_IN_PROCESS 0x3A
+#define SPI_E_ALREADY_INITIALIZED 0x4A
+
+typedef enum {
+ SPI_UNINIT=0, // The SPI Handler/Driver is not initialized or not usable.
+ // SPI011: This shall be the default value after reset. This
+ // status shall have the value 0.
+
+ SPI_IDLE, // The SPI Handler/Driver is not currently transmitting any
+ // Job.
+
+ SPI_BUSY, // The SPI Handler/Driver is performing a SPI Job( transmit )
+} Spi_StatusType;
+
+typedef enum {
+ SPI_JOB_OK=0, // The last transmission of the Job has been finished
+ // successfully.
+ // SPI012: This shall be the default value after reset.
+ // This status shall have the value 0.
+
+ SPI_JOB_PENDING, // The SPI Handler/Driver is performing a SPI Job.
+ // The meaning of this status is equal to SPI_BUSY.
+
+ SPI_JOB_FAILED, // The last transmission of the Job has failed.
+} Spi_JobResultType;
+
+typedef enum {
+
+ SPI_SEQ_OK, // The last transmission of the Sequence has been
+ // finished successfully.
+ // SPI017: This shall be the default value after reset.
+ // This status shall have the value 0.
+
+ SPI_SEQ_PENDING, // The SPI Handler/Driver is performing a SPI
+ // Sequence. The meaning of this status is equal to
+ // SPI_BUSY.
+
+ SPI_SEQ_FAILED, // The last transmission of the Sequence has failed.
+
+ SPI_SEQ_CANCELLED, // The last transmission of the Sequence has been
+ // cancelled by user.
+} Spi_SeqResultType;
+
+
+// Type for defining the number of data elements of the type Spi_DataType to
+// send and / or receive by Channel
+typedef uint16 Spi_NumberOfDataType;
+
+
+// Specifies the asynchronous mechanism mode for SPI busses handled
+// asynchronously in LEVEL 2.
+// SPI150: This type is available or not accordint to the pre compile time parameter:
+// SPI_LEVEL_DELIVERED. This is only relevant for LEVEL 2.
+
+typedef enum {
+
+ // The asynchronous mechanism is ensured by
+ // polling, so interrupts related to SPI busses
+ // handled asynchronously are disabled.
+ SPI_POLLING_MODE,
+
+ // The asynchronous mechanism is ensured by
+ // interrupt, so interrupts related to SPI busses
+ // handled asynchronously are enabled.
+
+ SPI_INTERRUPT_MODE,
+} Spi_AsyncModeType;
+
+
+#include "Spi_Cfg.h"
+
+void Spi_Init( const Spi_ConfigType *ConfigPtr );
+Std_ReturnType Spi_DeInit( void );
+Std_ReturnType Spi_WriteIB( Spi_ChannelType Channel, const Spi_DataType *DataBufferPtr );
+Std_ReturnType Spi_AsyncTransmit( Spi_SequenceType Sequence );
+Std_ReturnType Spi_ReadIB( Spi_ChannelType Channel, Spi_DataType *const DataBufferPtr ) ;
+Std_ReturnType Spi_SetupEB( Spi_ChannelType Channel,
+ const Spi_DataType* SrcDataBufferPtr,
+ Spi_DataType* DesDataBufferPtr,
+ Spi_NumberOfDataType Length );
+
+Spi_StatusType Spi_GetStatus( void );
+Spi_JobResultType Spi_GetJobResult ( Spi_JobType Job );
+Spi_SeqResultType Spi_GetSequenceResult(Spi_SequenceType Sequence );
+
+#if ( SPI_VERSION_INFO_API == STD_ON )
+#define Spi_GetVersionInfo(_vi) STD_GET_VERSION_INFO(_vi,SPI)
+#endif
+
+Std_ReturnType Spi_SyncTransmit( Spi_SequenceType Sequence );
+Spi_StatusType Spi_GetHWUnitStatus(Spi_HWUnitType HWUnit);
+
+#if (SPI_CANCEL_API == STD_ON )
+void Spi_Cancel( Spi_SequenceType Sequence );
+#endif
+
+Std_ReturnType Spi_SetAsyncMode( Spi_AsyncModeType Mode );
+void Spi_MainFunction_Handling( void );
+void Spi_MainFunction_Driving( void );
+
+#endif /*SPI_H_*/
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+#ifndef _STD_TYPES_H\r
+#define _STD_TYPES_H\r
+\r
+// Autosar include files....\r
+// TODO: we haven't really defined the autosar types yet.\r
+// the standard types are uint8, etc.\r
+\r
+#ifndef NULL\r
+#define NULL 0\r
+#endif\r
+\r
+#if !defined(USE_KERNEL)\r
+#include "typedefs.h"\r
+#else\r
+#include <stdint.h>\r
+#endif\r
+\r
+#include "Platform_Types.h" // TODO: move\r
+#include "Compiler.h"\r
+\r
+//typedef uint8_t uint8;\r
+//typedef uint16_t uint16;\r
+//typedef uint32_t uint32;\r
+\r
+\r
+typedef struct {\r
+ // TODO: not done!!\r
+ uint16 vendorID;\r
+ uint16 moduleID;\r
+ uint8 instanceID;\r
+ /* Vendor numbers */\r
+ uint8 sw_major_version;\r
+ uint8 sw_minor_version;\r
+ uint8 sw_patch_version;\r
+ /* Autosar spec. numbers */\r
+ uint8 ar_major_version;\r
+ uint8 ar_minor_version;\r
+ uint8 ar_patch_version;\r
+} Std_VersionInfoType;\r
+\r
+/* make compare number... #if blabla > 10203 ( 1.2.3 ) */\r
+#define STD_GET_VERSION (_major,_minor,_patch) (_major * 10000 + _minor * 100 + _patch)\r
+\r
+/* Non-standard macro */\r
+#define STD_GET_VERSION_INFO(_vi,_module) \\r
+ ((_vi)->vendorID = _module ## _VENDOR_ID);\\r
+ ((_vi)->moduleID = _module ## _MODULE_ID);\\r
+ ((_vi)->sw_major_version = _module ## _SW_MAJOR_VERSION);\\r
+ ((_vi)->sw_minor_version = _module ## _SW_MINOR_VERSION);\\r
+ ((_vi)->sw_patch_version = _module ## _SW_PATCH_VERSION);\\r
+ ((_vi)->ar_major_version = _module ## _AR_MAJOR_VERSION);\\r
+ ((_vi)->ar_minor_version = _module ## _AR_MINOR_VERSION);\\r
+ ((_vi)->ar_patch_version = _module ## _AR_PATCH_VERSION);\r
+\r
+\r
+// TODO: Move to OSEK implementation, See 8.2 in SWS_StandardTypes\r
+\r
+#define STATUSTYPEDEFINED\r
+typedef enum {\r
+ E_OK = 0,\r
+ /* STD OSEK */\r
+ E_OS_ACCESS = 1,\r
+ E_OS_CALLEVEL = 2,\r
+ E_OS_ID = 3,\r
+ E_OS_LIMIT = 4,\r
+ E_OS_NOFUNC = 5,\r
+ E_OS_RESOURCE = 6,\r
+ E_OS_STATE = 7,\r
+ E_OS_VALUE = 8,\r
+\r
+ /* AUTOSAR, see 7.10 */\r
+ E_OS_SERVICEID,\r
+ E_OS_RATE ,\r
+ E_OS_ILLEGAL_ADDRESS ,\r
+ E_OS_MISSINGEND ,\r
+ E_OS_DISABLEDINT ,\r
+ E_OS_STACKFAULT ,\r
+ E_OS_PROTECTION_MEMORY ,\r
+ E_OS_PROTECTION_TIME ,\r
+ E_OS_PROTECTION_LOCKED ,\r
+ E_OS_PROTECTION_EXCEPTION ,\r
+ E_OS_PROTECTION_RATE,\r
+\r
+ /* COM.. TODO: move ?? */\r
+ E_COM_ID,\r
+\r
+\r
+ /* Implementation specific */\r
+ E_OS_SYS_APA,\r
+\r
+ E_NOT_OK,\r
+} StatusType;\r
+\r
+\r
+// TODO: really ???\r
+typedef uint8 Std_ReturnType;\r
+\r
+\r
+#ifndef STATUSTYPEDEFINED\r
+#define STATUSTYPEDEFINED\r
+#define E_OK 0\r
+typedef unsigned char StatusType;\r
+#endif\r
+\r
+#define E_NOT_OK 1\r
+\r
+#define STD_HIGH 0x01\r
+#define STD_LOW 0x00\r
+\r
+#define STD_ACTIVE 0x01\r
+#define STD_IDLE 0x00\r
+\r
+#define STD_ON 0x01\r
+#define STD_OFF 0x00\r
+\r
+\r
+#endif\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef TEST_CBK_\r
+#define TEST_CBK_\r
+\r
+\r
+#define USE_TEST_CBK 1\r
+\r
+#if defined(USE_TEST_CBK)\r
+#include "Can_Test.h"\r
+#endif\r
+\r
+#if defined(USE_TEST_CBK)\r
+#define CANIF_TXCONFIRMATION_CALL(canTxPduId) \\r
+ CT_CanIf_TxConfirmation_Called( canTxPduId );\r
+#define CANIF_RXINDICATION_CALL(Hrh,CanId,CanDlc,CanSduPtr) \\r
+ CT_CanIf_RxIndication_Called( Hrh, CanId, CanDlc, CanSduPtr );\r
+#define CANIF_CANCELTXCONFIRMATION_CALL(PduInfoPtr) \\r
+ CT_CanIf_CancelTxConfirmation_Called( PduInfoPtr );\r
+#define CANIF_CONTROLLERBUSOFF_CALL(Controller) \\r
+ CT_CanIf_ControllerBusOff_Called( Controller );\r
+#define CANIF_CONTROLLERWAKEUP_CALL(Controller) \\r
+ CT_CanIf_ControllerWakeup_Called( Controller );\r
+#else\r
+#define CANIF_TXCONFIRMATION_CALL(canTxPduId) \r
+#define CANIF_RXINDICATION_CALL(Hrh,CanId,CanDlc,CanSduPtr) \r
+#define CANIF_CANCELTXCONFIRMATION_CALL(PduInfoPtr) \r
+#define CANIF_CONTROLLERBUSOFF_CALL(Controller) \r
+#define CANIF_CONTROLLERWAKEUP_CALL(Controller) \r
+#endif\r
+\r
+\r
+#endif /*TEST_CBK_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef TRACE_H_\r
+#define TRACE_H_\r
+\r
+/**\r
+ *\r
+ * NOTE!!!!\r
+ * Do not use this in a header file. Should be used in the *.c file like this.\r
+ *\r
+ * #define USE_TRACE\r
+ * #include "Trace.h"\r
+ *\r
+ * Macro's for debugging and tracing\r
+ *\r
+ * Define USE_DEBUG and DBG_LEVEL either globally( e.g. a makefile )\r
+ * or in a specific file. The DBG_LEVEL macro controls the amount\r
+ * of detail you want in the debug printout.\r
+ * There are 3 levels:\r
+ * DEBUG_LOW - Used mainly by drivers to get very detailed\r
+ * DEBUG_MEDIUM - Medium detail\r
+ * DEBUG_HIGH - General init\r
+ *\r
+ * Example:\r
+ * #define DEBUG_LVL DEBUG_HIGH\r
+ * DEBUG(DEBUG_HIGH,"Starting GPT");\r
+ *\r
+ * TRACE\r
+ * TODO:\r
+ *\r
+ */\r
+\r
+#define DEBUG_LOW 1\r
+#define DEBUG_MEDIUM 2\r
+#define DEBUG_HIGH 3\r
+\r
+#ifndef DEBUG_LVL\r
+#define DEBUG_LVL 2\r
+#endif\r
+\r
+extern int simple_printf(const char *format, ...);\r
+\r
+//#define USE_DEBUG\r
+//#define USE_TRACE\r
+\r
+#define CH_ISR 0\r
+#define CH_PROC 1\r
+\r
+#if defined(USE_DEBUG)\r
+#define DEBUG(_level,...) \\r
+ do { \\r
+ if(_level>=DEBUG_LVL) { \\r
+ simple_printf (__VA_ARGS__); \\r
+ }; \\r
+ } while(0);\r
+\r
+#else\r
+#define DEBUG(_level,...)\r
+#endif\r
+\r
+#if defined(USE_DEBUG)\r
+#define dbg_printf(format,...) simple_printf(format,## __VA_ARGS__ )\r
+#else\r
+#define dbg_printf(format,...)\r
+#endif\r
+\r
+\r
+#endif /*RAMLOG_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef ALIST_I_H_\r
+#define ALIST_I_H_\r
+\r
+/*\r
+ * Some macros to handle a static array and it's data.\r
+ *\r
+ *\r
+ * Usage:\r
+ * struct foo_s {\r
+ * int foo_data;\r
+ * };\r
+ *\r
+ * struct foo_s my_data[5];\r
+ *\r
+ * // Create the head\r
+ * SA_LIST_HEAD(foo,foo_s) arr_list;\r
+ * // Init the head with data.\r
+ * arr_list = SA_LIST_HEAD_INITIALIZER(5,my_data);\r
+ *\r
+ */\r
+\r
+\r
+/**\r
+ * @def ALIST_HEAD(name, type)\r
+ * Declare the head for the static list\r
+ *\r
+ * @param name - name of the struct\r
+ * @param type - struct type for the array\r
+ */\r
+\r
+\r
+#define SA_LIST_HEAD(name, type) \\r
+struct name { \\r
+ int cnt; \\r
+ struct type *data; \\r
+}\r
+\r
+#define SA_LIST_HEAD_INITIALIZER(elem_cnt, data_p ) \\r
+{ \\r
+ .cnt = (elem_cnt), \\r
+ .data = (data_p) \\r
+}\r
+\r
+#define SA_LIST_CNT(head) (head)->cnt\r
+#define SA_LIST_GET( head, index ) (&(head)->data[(index)])\r
+#define SA_LIST_FOREACH( head, ivar) for( (ivar)=0;(ivar)<SA_LIST_CNT(head);(ivar)++)\r
+\r
+#endif /*ALIST_I_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+#ifndef CPU_H_
+#define CPU_H_
+
+#include <stdint.h>
+#include "stm32f10x.h"
+#include "core_cm3.h"
+
+#define SIMULATOR() (0==0)
+
+
+//#define isync() asm volatile(" isync");
+//#define sync() asm volatile(" sync");
+//#define msync() asm volatile(" msync");
+
+/* Call intrinsic functions directly */
+#define Irq_Disable() __disable_irq()
+#define Irq_Enable() __enable_irq()
+
+/* TODO: This is of course wrong */
+#define Irq_Save(_flags) __disable_irq();
+#define Irq_Restore(_flags) __enable_irq();
+
+#endif /* CPU_H_ */
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*
+ * int_ctrl.h
+ *
+ * Created on: Jul 31, 2009
+ * Author: mahi
+ */
+
+#ifndef INT_CTRL_H_
+#define INT_CTRL_H_
+
+#include "irq.h"
+
+typedef void ( * func_t)(void);
+
+
+/**
+ * Init the interrupt controller
+ */
+void IntCtrl_Init( void );
+
+/**
+ * End-Of-Interrupt. Called by the OS it wants to clear the interrupt.
+ */
+void IntCtrl_EOI( void );
+
+
+/**
+ *
+ * @param stack_p Ptr to the current stack.
+ *
+ * The stack holds C, NVGPR, VGPR and the EXC frame.
+ *
+ */
+void *IntCtrl_Entry( void *stack_p );
+
+/**
+ * Attach an ISR type 1 to the interrupt controller.
+ *
+ * @param entry
+ * @param int_ctrl
+ * @param vector
+ * @param prio
+ */
+void IntCtrl_AttachIsr1( void (*entry)(void), void *int_ctrl, uint32_t vector, uint8_t prio);
+
+/**
+ * Attach a ISR type 2 to the interrupt controller.
+ *
+ * @param tid The task id
+ * @param int_ctrl The interrupt controller, The is NULL for now.
+ * @param vector The vector to attach to
+ */
+void IntCtrl_AttachIsr2(TaskType tid,void *int_ctrl,uint32_t vector );
+
+/**
+ * Generates a soft interrupt
+ * @param vector
+ */
+void IntCtrl_GenerateSoftInt( IrqType vector );
+/**
+ * Get the current priority from the interrupt controller.
+ * @param cpu
+ * @return
+ */
+uint8_t IntCtrl_GetCurrentPriority( Cpu_t cpu);
+
+#if 0
+typedef struct {
+ uint32_t dummy;
+} exc_stack_t;
+#endif
+
+
+#endif /* INT_CTRL_H_ */
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+/*\r
+ * This file only be use with the Os_Cfg.c file and os_config_macros.h\r
+ */\r
+#include "kernel.h"\r
+#include "Os_Cfg.h"\r
+\r
+// COUNTER, RESOURCE, TSAK, must be at least 1\r
+#define COUNTER_CNT ARRAY_SIZE(counter_list)\r
+#define RESOURCE_CNT ARRAY_SIZE(resource_list)\r
+#define TASK_CNT ARRAY_SIZE(rom_pcb_list)\r
+\r
+#if defined(ALARM_USE)\r
+#define ALARM_CNT ARRAY_SIZE(alarm_list)\r
+#else\r
+#define ALARM_CNT 0\r
+#endif\r
+\r
+#if defined(SCHEDULETABLE_USE)\r
+#define SCHEDULETABLE_CNT ARRAY_SIZE(sched_list)\r
+#else\r
+#define SCHEDULETABLE_CNT 0\r
+#endif\r
+\r
+#if defined(MESSAGE_CNT)\r
+#undef MESSAGE_CNT\r
+#define MESSAGE_CNT ARRAY_SIZE(message_list)\r
+#else\r
+#define MESSAGE_CNT 0\r
+#endif\r
+\r
+#if defined(EVENT_CNT)\r
+#undef EVENT_CNT\r
+#define EVENT_CNT ARRAY_SIZE(event_list)\r
+#else\r
+#define EVENT_CNT 0\r
+#endif\r
+\r
+#if defined(SERVICE_CNT)\r
+#undef SERVICE_CNT\r
+#define SERVICE_CNT ARRAY_SIZE(os_cfg_trusted_list)\r
+#else\r
+#define SERVICE_CNT 0\r
+#endif\r
+\r
+os_error_t os_error;\r
+\r
+//-------------------------------------------------------------------\r
+\r
+\r
+/*\r
+ * Accessor functions for os_config.c\r
+ */\r
+\r
+#if 0\r
+#if SERVICE_CNT!=0\r
+trusted_func_t oil_trusted_func_list[SERVICE_CNT];\r
+#endif\r
+#endif\r
+\r
+/*-----------------------------------------------------------------*/\r
+int Oil_GetApplCnt(void) {\r
+ return APPLICATION_CNT;\r
+}\r
+\r
+rom_app_t *Oil_GetApplObj( ApplicationType application_id ) {\r
+ return &rom_app_list[application_id];\r
+}\r
+\r
+/*-----------------------------------------------------------------*/\r
+int Oil_GetTaskCnt(void) {\r
+ return TASK_CNT;\r
+}\r
+/*-----------------------------------------------------------------*/\r
+\r
+resource_obj_t *Oil_GetResource( ResourceType resource ) {\r
+ return &resource_list[resource];\r
+}\r
+\r
+int Oil_GetResourceCnt() {\r
+ return RESOURCE_CNT;\r
+}\r
+\r
+/*-----------------------------------------------------------------*/\r
+\r
+counter_obj_t *Oil_GetCounter(CounterType count_id) {\r
+ return &counter_list[count_id];\r
+}\r
+\r
+uint32 Oil_GetCounterCnt(void ) {\r
+ return COUNTER_CNT;\r
+// return sizeof(counter_list)/sizeof(counter_obj_t);\r
+}\r
+/*-----------------------------------------------------------------*/\r
+\r
+uint32 Oil_GetSchedCnt( void ) {\r
+ return SCHEDULETABLE_CNT;\r
+}\r
+\r
+sched_table_t *Oil_GetSched( ScheduleTableType sched_id ) {\r
+#if defined(SCHEDULETABLE_USE)\r
+ if(sched_id < SCHEDULETABLE_CNT) {\r
+ return &sched_list[sched_id];\r
+ } else {\r
+ return NULL;\r
+ }\r
+#else\r
+ return NULL;\r
+#endif\r
+}\r
+\r
+/*-----------------------------------------------------------------*/\r
+\r
+uint32 Oil_GetAlarmCnt(void) {\r
+ return ALARM_CNT;\r
+}\r
+\r
+alarm_obj_t *Oil_GetAlarmObj( AlarmType alarm_id ) {\r
+#if defined(ALARM_USE)\r
+ if( alarm_id < ALARM_CNT) {\r
+ return &alarm_list[alarm_id];\r
+ } else {\r
+ return NULL;\r
+ }\r
+#else\r
+ return NULL;\r
+#endif\r
+}\r
+\r
+StatusType Oil_GetAlarmBase(AlarmType alarm_id, AlarmBaseRefType info) {\r
+\r
+ StatusType rv = E_OK;\r
+\r
+ if( alarm_id >= Oil_GetAlarmCnt() ) {\r
+ rv = E_OS_ID;\r
+ }\r
+#if defined(ALARM_USE)\r
+ *info = alarm_list[alarm_id].counter->alarm_base;\r
+#endif\r
+ return rv;\r
+}\r
+\r
+\r
+/*-----------------------------------------------------------------*/\r
+\r
+message_obj_t *Oil_GetMessage(MessageType message_id) {\r
+#if MESSAGE_CNT!=0\r
+ return &message_list[message_id];\r
+#else\r
+ return NULL;\r
+#endif\r
+}\r
+\r
+uint32 Oil_GetMessageCnt(void ) {\r
+ return MESSAGE_CNT;\r
+}\r
+\r
+/*-----------------------------------------------------------------*/\r
+\r
+uint32 Oil_GetServiceCnt( void ) {\r
+ return SERVICE_CNT;\r
+}\r
+\r
+\r
+/*-----------------------------------------------------------------*/\r
+\r
+void Oil_GetInterruptStackInfo( stack_t *stack ) {\r
+ stack->top = os_interrupt_stack;\r
+ stack->size = sizeof(os_interrupt_stack);\r
+}\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+/*\r
+ * Hold macros for the generator\r
+ */\r
+#ifndef _OS_CONFIG_MACROS_H\r
+#define _OS_CONFIG_MACROS_H\r
+\r
+#define false 0\r
+#define true 1\r
+\r
+// +1 here.. easy to have a reference..\r
+#define GEN_TRUSTEDFUNCTIONS_LIST trusted_func_t os_cfg_trusted_list[SERVICE_CNT];\r
+\r
+#define GEN_APPLICATION_HEAD rom_app_t rom_app_list[] =\r
+\r
+#define GEN_APPLICATON( _id,_name,_trusted,_startuphook,_shutdownhook, \\r
+ _errorhook,_isr_mask,_scheduletable_mask, _alarm_mask, \\r
+ _counter_mask,_resource_mask,_message_mask ) \\r
+{ \\r
+ .application_id = _id, \\r
+ .name = _name, \\r
+ .trusted = _trusted, \\r
+ .StartupHook = _startuphook, \\r
+ .ShutdownHook = _shutdownhook, \\r
+ .ErrorHook = _errorhook, \\r
+ .isr_mask = _isr_mask, \\r
+ .scheduletable_mask = _scheduletable_mask, \\r
+ .alarm_mask = _alarm_mask, \\r
+ .counter_mask = _counter_mask, \\r
+ .resource_mask = _resource_mask, \\r
+ .message_mask = _message_mask, \\r
+}\r
+\r
+\r
+#define GEN_TASK_HEAD rom_pcb_t rom_pcb_list[] =\r
+\r
+\r
+#define GEN_ETASK( _id, _priority, _autostart, _timing_protection, _application_id, _resource_int_p ) \\r
+{ \\r
+ .pid = TASK_ID_##_id, \\r
+ .name = #_id, \\r
+ .entry = _id, \\r
+ .prio = _priority, \\r
+ .proc_type = PROC_EXTENDED, \\r
+ .stack.size = sizeof stack_##_id, \\r
+ .stack.top = stack_##_id, \\r
+ .autostart = _autostart, \\r
+ .timing_protection = _timing_protection,\\r
+ .application_id = _application_id, \\r
+ .resource_int_p = _resource_int_p, \\r
+}\r
+\r
+#define GEN_BTASK( _id, _priority, _autostart, _timing_protection, _application_id, _resource_int_p ) \\r
+{ \\r
+ .pid = TASK_ID_##_id, \\r
+ .name = #_id, \\r
+ .entry = _id, \\r
+ .prio = _priority, \\r
+ .proc_type = PROC_BASIC, \\r
+ .stack.size = sizeof stack_##_id, \\r
+ .stack.top = stack_##_id, \\r
+ .autostart = _autostart, \\r
+ .timing_protection = _timing_protection,\\r
+ .application_id = _application_id, \\r
+ .resource_int_p = _resource_int_p, \\r
+}\r
+\r
+\r
+#define GEN_TASK( _id, _name, _entry, _priority, _process_type, _stack_size, _stack_top, \\r
+ _autostart, _timing_protection, _application_id, _resource_int_p ) \\r
+{ \\r
+ .pid = _id, \\r
+ .name = _name, \\r
+ .entry = _entry, \\r
+ .prio = _priority, \\r
+ .proc_type = _process_type, \\r
+ .stack.size = _stack_size, \\r
+ .stack.top = _stack_top, \\r
+ .autostart = _autostart, \\r
+ .timing_protection = _timing_protection,\\r
+ .application_id = _application_id, \\r
+ .resource_int_p = _resource_int_p, \\r
+}\r
+\r
+#define GEN_ISR_2( _id, _name, _entry, _priority, _process_type, _vector, _timing_protection, _application_id ) \\r
+{ \\r
+ .pid = _id, \\r
+ .name = _name, \\r
+ .entry = _entry, \\r
+ .prio = _priority, \\r
+ .proc_type = _process_type, \\r
+ .vector = _vector, \\r
+ .timing_protection = _timing_protection,\\r
+ .application_id = _application_id, \\r
+}\r
+\r
+\r
+#define GEN_ISR_1( _id, _name, _entry, _priority , _vector ) \\r
+{ \\r
+ .pid = _id, \\r
+ .name = _name, \\r
+ .entry = _entry, \\r
+ .prio = _priority, \\r
+ .proc_type = PROC_ISR1, \\r
+ .vector = _vector, \\r
+}\r
+\r
+#define GEN_PCB_LIST() uint8_t pcb_list[PCB_T_SIZE*ARRAY_SIZE(rom_pcb_list)];\r
+\r
+#define GEN_RESOURCE_HEAD resource_obj_t resource_list[] =\r
+#define GEN_RESOURCE( _id, _type, _ceiling_priority, _application_id, _task_mask) \\r
+{ \\r
+ .nr= _id, \\r
+ .type= _type, \\r
+ .ceiling_priority = _ceiling_priority, \\r
+ .application_owner_id = _application_id, \\r
+ .task_mask = _task_mask, \\r
+ .owner = (-1), \\r
+}\r
+\r
+#define GEN_COUNTER_HEAD counter_obj_t counter_list[] =\r
+#define GEN_COUNTER( _id, _name, _type, _unit, \\r
+ _maxallowedvalue, \\r
+ _ticksperbase, \\r
+ _mincycle, \\r
+ _gpt_ch ) \\r
+{ \\r
+ .type = _type, \\r
+ .unit = _unit, \\r
+ .alarm_base.maxallowedvalue = _maxallowedvalue, \\r
+ .alarm_base.tickperbase = _ticksperbase, \\r
+ .alarm_base.mincycle = _mincycle, \\r
+ .driver.OsGptChannelRef = _gpt_ch \\r
+}\r
+\r
+#define GEN_ALARM_HEAD alarm_obj_t alarm_list[] =\r
+#define GEN_ALARM( _id, _name, _counter_id, \\r
+ _autostart_active, \\r
+ _autostart_alarmtime, \\r
+ _autostart_cycletime, \\r
+ _autostart_application_mode_mask,\\r
+ _action_type, \\r
+ _action_task_id, \\r
+ _action_event_id, \\r
+ _action_counter_id ) \\r
+{ \\r
+ .name = _name, \\r
+ .counter = &counter_list[_counter_id], \\r
+ .counter_id = _counter_id, \\r
+ .autostart = { \\r
+ .active = _autostart_active, \\r
+ .alarmtime = _autostart_alarmtime, \\r
+ .cycletime = _autostart_cycletime, \\r
+ .appmode_mask = _autostart_application_mode_mask, \\r
+ }, \\r
+ .action = { \\r
+ .type = _action_type, \\r
+ .task_id = _action_task_id, \\r
+ .event_id = _action_event_id, \\r
+ .counter_id = _action_counter_id \\r
+ }, \\r
+}\r
+\r
+#define GEN_SCHEDULETABLE_HEAD sched_table_t sched_list[] =\r
+#define GEN_SCHEDULETABLE( _id, _name, _counter, _repeating, _length, _application_mask, \\r
+ _action_cnt, _action_expire_ref, \\r
+ _autostart_active, _autostart_type, _autostart_rel_offset, _autostart_appmode, \\r
+ _sync_strategy, _sync_explicit_precision , \\r
+ _adj_max_advance,_adj_max_retard ) \\r
+{ \\r
+ .name = _name, \\r
+ .counter = &counter_list[_counter], \\r
+ .repeating = _repeating, \\r
+ .length = _length, \\r
+ .app_mask = _application_mask, \\r
+ .action_list = SA_LIST_HEAD_INITIALIZER(_action_cnt,_action_expire_ref), \\r
+ .autostart = { \\r
+ .active = _autostart_active, \\r
+ .type = _autostart_type, \\r
+ .relOffset = _autostart_rel_offset, \\r
+ .appModeRef = _autostart_appmode, \\r
+ }, \\r
+ .sync = { \\r
+ .syncStrategy = _sync_strategy, \\r
+ .explicitPrecision = _sync_explicit_precision, \\r
+ }, \\r
+ .adjExpPoint = { \\r
+ .maxAdvance = _adj_max_advance, \\r
+ .maxRetard = _adj_max_retard, \\r
+ } \\r
+}\r
+\r
+#define GEN_HOOKS( _startup, _protection, _shutdown, _error, _pretask, _posttask ) \\r
+struct os_conf_global_hooks_s os_conf_global_hooks = { \\r
+ .StartupHook = _startup, \\r
+ .ProtectionHook = _protection, \\r
+ .ShutdownHook = _shutdown, \\r
+ .ErrorHook = _error, \\r
+ .PreTaskHook = _pretask, \\r
+ .PostTaskHook = _posttask, \\r
+};\r
+\r
+\r
+#define ALIGN_16(x) (((x)>>4)<<4)\r
+\r
+#define DECLARE_STACK(_name,_size) \\r
+ uint8_t stack_##_name[_size]\r
+\r
+#define SECTION_BSS_SUPER __attribute__ ((aligned (16),section(".bss")))\r
+#define SECTION_BSS_USER __attribute__ ((aligned (16),section(".bss")))\r
+\r
+#undef ALARM_CNT\r
+#undef SCHEDULETABLE_CNT\r
+#undef MESSAGE_CNT\r
+#undef EVENT_CNT\r
+#undef SERVICE_CNT\r
+\r
+#endif\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+#ifndef CPU_H\r
+#define CPU_H\r
+\r
+#include "Std_Types.h"\r
+\r
+// Used if we are running a T32 instruction set simulator\r
+#define SIMULATOR() (SIU.MIDR.R==0)\r
+\r
+// 32-bit write to 32 bit register\r
+#define BIT32(x)\r
+// 16 bit write to 16 bit register\r
+#define BIT16(x)\r
+\r
+// Bits EREF and others define as 64 bit regs but in 32 bits regs.\r
+// E.g. #define MSR_PR BIT64TO32(49)\r
+#define BIT64TO32(x) (1<<(63-(x)))\r
+\r
+\r
+\r
+/*\r
+ * SPR numbers, Used by set_spr and get_spr macros\r
+ */\r
+#define SPR_LR 8\r
+#define SPR_IVPR 63\r
+#define SPR_IVOR0 400\r
+#define SPR_IVOR1 401\r
+#define SPR_IVOR2 402\r
+#define SPR_IVOR3 403\r
+#define SPR_IVOR4 404\r
+#define SPR_IVOR5 405\r
+#define SPR_IVOR6 406\r
+#define SPR_IVOR7 407\r
+#define SPR_IVOR8 408\r
+#define SPR_IVOR9 409\r
+#define SPR_IVOR10 410\r
+#define SPR_IVOR11 411\r
+#define SPR_IVOR12 412\r
+#define SPR_IVOR13 413\r
+#define SPR_IVOR14 414\r
+#define SPR_IVOR15 415\r
+\r
+#define SPR_IVOR32 528\r
+#define SPR_IVOR33 529\r
+#define SPR_IVOR34 530\r
+\r
+\r
+#define SPR_DEC 22\r
+#define SPR_DECAR 54\r
+\r
+#define SPR_TBU_R 269\r
+#define SPR_TBU_W 285\r
+#define SPR_TBL_R 268\r
+#define SPR_TBL_W 284\r
+\r
+#define SPR_TCR 340\r
+#define SPR_TSR 336\r
+\r
+#define SPR_HID0 1008\r
+\r
+#define SPR_L1CSR0 1010\r
+#define SPR_L1CFG0 515\r
+\r
+#define SPR_SRR0 26\r
+#define SPR_SRR1 27\r
+\r
+#define SPR_SPRG1_RW_S 273\r
+\r
+#define MSR_PR BIT64TO32(49)\r
+#define MSR_EE BIT64TO32(48)\r
+#define MSR_SPE BIT64TO32(38)\r
+#define MSR_DS BIT64TO32(58)\r
+#define MSR_IS BIT64TO32(59)\r
+\r
+//#define ESR_PTR BIT64TO32(38)\r
+\r
+\r
+/* Timer control regs\r
+ */\r
+#define TCR_DIE 0x04000000\r
+#define TCR_ARE 0x00400000\r
+#define TCR_FIE 0x00800000\r
+\r
+#define HID0_TBEN 0x4000\r
+\r
+/*\r
+ * String macros\r
+ */\r
+\r
+#define STR__(x) #x\r
+#define STRINGIFY__(x) STR__(x)\r
+\r
+\r
+#define Irq_Save(flags) flags = _Irq_Disable_save()\r
+#define Irq_Restore(flags) _Irq_Disable_restore(flags)\r
+\r
+/***********************************************************************\r
+ * Common macro's\r
+ */\r
+\r
+#define isync() asm volatile(" isync");\r
+#define sync() asm volatile(" sync");\r
+#define msync() asm volatile(" msync");\r
+\r
+#define Irq_Disable() asm volatile (" wrteei 0");\r
+#define Irq_Enable() asm volatile (" wrteei 1");\r
+\r
+/*-----------------------------------------------------------------*/\r
+\r
+/**\r
+ * Sets a value to a specific SPR register\r
+ */\r
+\r
+#define set_spr(spr_nr, val) \\r
+ asm volatile (" mtspr " STRINGIFY__(spr_nr) ",%[_val]" : : [_val] "r" (val))\r
+\r
+/**\r
+ * Gets the value from a specific SPR register\r
+ *\r
+ * Note! Tried lots of other ways to do this but came up empty\r
+ */\r
+\r
+#define get_spr(spr_nr) \\r
+({\\r
+ uint32_t __val;\\r
+ asm volatile (" mfspr %0," STRINGIFY__(spr_nr) : "=r"(__val) : );\\r
+ __val;\\r
+})\r
+\r
+\r
+/**\r
+ * Get current value of the msr register
+ * @return
+ */\r
+static inline unsigned long get_msr() {\r
+ uint32_t msr;\r
+ asm volatile("mfmsr %[msr]":[msr] "=r" (msr ) );\r
+ return msr;\r
+}\r
+\r
+/*-----------------------------------------------------------------*/\r
+\r
+/**\r
+ * Set the current msr to msr
+ * @param msr
+ */\r
+static inline void set_msr(unsigned long msr) {\r
+ asm volatile ("mtmsr %0" : : "r" (msr) );\r
+\r
+ // This is just necessary for some manipulations of MSR\r
+ isync();\r
+}\r
+/*-----------------------------------------------------------------*/\r
+\r
+/* Count the number of consecutive zero bits starting at ppc-bit 0 */\r
+static inline unsigned int cntlzw(unsigned int val)\r
+{\r
+ unsigned int result;\r
+ asm volatile ("cntlzw %[rv],%[val]" : [rv] "=r" (result) : [val] "r" (val) );\r
+ return result;\r
+}\r
+\r
+/* Something like the ilogb() functions in newlib but without math.h\r
+ * ( and with base 2 ) */\r
+static inline int ilog2( int val ) {\r
+ return 31 - cntlzw(val);\r
+}\r
+\r
+/* Standard newlib ffs() is REALLY slow since ot loops over all over the place\r
+ * TODO: Use _builin_ffs() instead.\r
+ */\r
+\r
+/*-----------------------------------------------------------------*/\r
+\r
+static inline unsigned long _Irq_Disable_save(void)\r
+{\r
+ unsigned long result;\r
+ asm volatile ("mfmsr %0" : "=r" (result) : );\r
+ Irq_Disable();\r
+ return result;\r
+}\r
+\r
+/*-----------------------------------------------------------------*/\r
+\r
+static inline void _Irq_Disable_restore(unsigned long flags)\r
+{\r
+ asm volatile ("mtmsr %0" : : "r" (flags) );\r
+}\r
+\r
+/*-----------------------------------------------------------------*/\r
+\r
+#define get_lr(var) \\r
+ do { \\r
+ unsigned long lr; \\r
+ asm volatile("mflr %[lr]":[lr] "=r" (lr ) ); \\r
+ var = lr; \\r
+ } while(0)\r
+\r
+\r
+/*-----------------------------------------------------------------*/\r
+\r
+static inline int in_user_mode( void ) {\r
+ unsigned long msr;\r
+ msr = get_msr();\r
+ // In user mode?\r
+ return (msr & MSR_PR);\r
+}\r
+\r
+\r
+#if 0\r
+#ifdef USE_T32_SIM\r
+ #define mode_to_kernel() k_arch_sim_trap()\r
+#else\r
+ #define mode_to_kernel() asm volatile(" sc");\r
+#endif\r
+#endif\r
+\r
+/*-----------------------------------------------------------------*/\r
+\r
+static inline void to_user_mode( void ) {\r
+ // Just set it back\r
+ unsigned long msr;\r
+ msr = get_msr();\r
+ set_msr(msr & ~MSR_PR);\r
+}\r
+\r
+#if 0\r
+#define SC_CALL(name,...) \\r
+ ({ \\r
+ int rv; \\r
+ unsigned int msr = get_msr(); \\r
+ if( msr & MSR_PR ) { \\r
+/* asm volatile(" sc"); */\\r
+ rv = _ ## name( __VA_ARGS__ ); \\r
+/* set_msr(msr); */ \\r
+ } else { \\r
+ rv = _ ## name( __VA_ARGS__ ); \\r
+ } \\r
+ rv; \\r
+ })\r
+#endif\r
+\r
+/*-----------------------------------------------------------------*/\r
+\r
+\r
+\r
+// StatusType CallService( TrustedFunctionIndexType ix,\r
+// TrustedFunctionParameterRefType params )\r
+\r
+typedef void ( * service_func_t)( uint16_t , void * );\r
+extern service_func_t oil_trusted_func_list[];\r
+\r
+/* Macros for SC_CALL macro */\r
+#define REG_DEF_1 register unsigned int r3 asm ("r3");\r
+#define REG_DEF_2 REG_DEF_1 register unsigned int r4 asm ("r4");\r
+\r
+/* Build argument list */\r
+#define REG_IN_1 "r" (r3)\r
+#define REG_IN_2 REG_IN_1 ,"r" (r4)\r
+\r
+\r
+#if defined(USE_MM_USER_MODE)\r
+/* TODO: Fix this.. */\r
+#define CallService(index,param) \\r
+ ({ \\r
+ register uint32_t r3 asm ("r3"); \\r
+ register void * r4 asm ("r4"); \\r
+ r3 = index; \\r
+ r4 = param; \\r
+ asm volatile( \\r
+ " sc\r\t" \\r
+ : \\r
+ : "r" (r3),"r" (r4) ); \\r
+ })\r
+#else\r
+#define CallService(index,param)\r
+#endif\r
+\r
+\r
+#if 0\r
+\r
+/* Macros for SC_CALL macro */\r
+#define REG_DEF_1 register unsigned int r3 asm ("r3");\r
+#define REG_DEF_2 REG_DEF_1 register unsigned int r4 asm ("r4");\r
+\r
+/* Split the __VA_ARGS__ */\r
+#define SPLIT_ARGS_1(_arg1) r3 = _arg1;\r
+#define SPLIT_ARGS_2(_arg1,_arg2) r3 = _arg1;r4 = _arg2;\r
+\r
+/* Build argument list */\r
+#define REG_IN_1 "r" (r3)\r
+#define REG_IN_2 REG_IN_1 ,"r" (r4)\r
+\r
+/* System call\r
+ *\r
+ * name - just for show\r
+ * index - The index to the function name above..\r
+ * arg_cnt - How many argument the function takes\r
+ * ... - var args list..\r
+ * */\r
+\r
+/*unsigned int t = index; \ */\r
+\r
+/* TODO: __VA_ARGS__ is ISO99 and not all compilers may have support for it*/\r
+#if __STDC_VERSION__ < 199901L\r
+#error Sorry, using macros iso99 VA_ARGS...implement in some other way\r
+#endif\r
+\r
+\r
+#define SC_CALL(name,index,arg_cnt,...) \\r
+ ({ \\r
+ void * t = _ ## name; \\r
+ REG_DEF_ ## arg_cnt \\r
+ SPLIT_ARGS_ ## arg_cnt(__VA_ARGS__) \\r
+ asm volatile( \\r
+ " mr 0,%[t];\r\t" \\r
+ " sc\r\t" \\r
+ : \\r
+ : [t] "r" (t), REG_IN_ ## arg_cnt ); \\r
+ })\r
+#endif\r
+\r
+/*\r
+ * asm volatile( " sc\r\t" ); \\r
+ */\r
+\r
+/*-----------------------------------------------------------------*/\r
+\r
+#if 0\r
+static inline unsigned int mode_to_kernel( void ) {\r
+ unsigned long msr;\r
+ msr = get_msr();\r
+ // In user mode?\r
+ if( msr & MSR_PR ) {\r
+ // switch to supervisor mode...\r
+#ifdef USE_T32_SIM\r
+ k_arch_sim_trap();\r
+#else\r
+ asm volatile(" tw");\r
+#endif\r
+ }\r
+ return msr;\r
+}\r
+#endif\r
+\r
+#endif /* CPU_H */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+
+#ifndef _ASM_BOOK_E_H
+#define _ASM_BOOK_E_H
+
+/*
+ *
+ *
+ *
+ *
+ *
+ *
+ */
+
+
+/*
+ * TODO: This file should be split in two. One handle the exceptions for book-e
+ * and one for this arch stack-frame-> asm_stack_frame.h
+ */
+
+/*
+
+ Mcu_Exceptions.S maps exceptions to the kernel through the exception_tbl.
+
+
+ exception_tbl: ( Mcu_Exceptions.S )
+ |
+ | exc_intc_pcb_tbl ( kernel )
+ |-----> exception_IVORx: ------> -------------
+ |-----> exception_IVORy: -, | 0 | ISR2
+ | | .. . |<>----------> my_isr_c_routine( C )
+ | | |
+ '----> | 32x |
+ | 324 |
+ | 3 | -----------> my_isr_routine: (assembler)
+ ' '
+ '-----------'
+ In kernel for IVOR4:
+ 1. Get vector through INTC_IACKR
+ 2. Get pcb for vector
+ If pcb==0, goto 10
+ 3. Get ISR type
+ if type==1, goto 5
+ 4. Save some GPR regs
+ 5. Call pcb->entry
+ 10: done!
+
+
+ ,--------,
+ | SP |
+ | Type | Context
+ | LR |
+ .....
+ +--------+
+ | | NVGPR's
+ .....
+ +--------+
+
+
+ b exception_IVOR4
+ {
+ save EF regs
+ get interrupt vector
+ if (soft int) {
+ ack int
+ }
+ get intc table
+ jump to function
+
+ }
+
+ The are two types of ISR, ISR1 and ISR2:
+ ISR1 - assembler routine, return with blr( Only EF exist on stack )
+ ISR2 - normal C-routine( can save small or big frame depending on config )
+
+
+ Use cases:
+ - InstallVector(vector, func, type )
+ 1. InstallVector( 320+10, exception_dec, 1 ); // dec exception
+ 2. InstallVector( 320+11, exception_fit, 2 ); // fit exception
+ 3. InstallVector( 5, softint , 2 ); // soft int
+ 4. InstallVector( 100, normal_int, 2 ) // normal int.
+ 5. InstallVector( 101, normal_int_2, 1 ) // normal int.
+
+ In case 1, the user have to install a prologue/epilogues to access
+ it from C( i.e store small frame )
+*/
+
+
+
+#define SC_PATTERN 0xde
+#define LC_PATTERN 0xad
+
+
+/* Alignment for architecture, see e500-ABI */
+#define ARCH_ALIGN 16
+
+#if defined(USE_KERNEL)
+#define C_SIZE 32
+#define C_SP_OFF 0
+// 4- backchain
+// 8 -padding
+#define C_CONTEXT_OFF 12
+#define C_LR_OFF 16
+#define C_CR_OFF 20
+#else
+#define C_SIZE 0
+#endif
+
+
+
+#if defined(CFG_SPE)
+//-----------------------------------------------------------------
+#define GPR_SIZE 8
+#elif defined(CFG_MPC5516)
+#define GPR_SIZE 4
+#else
+#error No MCU set
+#endif
+
+
+#if defined(USE_KERNEL)
+/* Small context */
+#define SC_GPRS_SIZE ((31-14+1)*GPR_SIZE)
+#define SC_GPRS_OFFS C_SIZE
+#define SC_SIZE (C_SIZE + SC_GPRS_SIZE)
+
+/* Large context */
+#define LC_GPRS_SIZE ((31-0+1)*GPR_SIZE)
+#define LC_SIZE (C_SIZE + LC_GPRS_SIZE)
+#endif
+
+// GPR save and restore macros
+
+#if defined(CFG_SPE)
+ #define SAVE_GPR(reg,_offset,rel_reg) evstdd reg,(((reg)*GPR_SIZE)+_offset)(rel_reg)
+ #define RESTORE_GPR(reg,_offset,rel_reg) evldd reg,(((reg)*GPR_SIZE)+_offset)(rel_reg)
+#elif defined(CFG_MPC5516)
+ #define SAVE_GPR(reg,_offset,rel_reg) stw reg,(((reg)*GPR_SIZE)+_offset)(rel_reg)
+ #define RESTORE_GPR(reg,_offset,rel_reg) lwz reg,(((reg)*GPR_SIZE)+_offset)(rel_reg)
+#endif
+
+#define SAVE_GPR2(reg,_offset,rel_reg) SAVE_GPR(reg,_offset,rel_reg);SAVE_GPR(reg+1,_offset,rel_reg)
+#define SAVE_GPR4(reg,_offset,rel_reg) SAVE_GPR2(reg,_offset,rel_reg);SAVE_GPR2(reg+2,_offset,rel_reg)
+#define SAVE_GPR8(reg,_offset,rel_reg) SAVE_GPR4(reg,_offset,rel_reg);SAVE_GPR4(reg+4,_offset,rel_reg)
+
+#define RESTORE_GPR2(reg,_offset,rel_reg) RESTORE_GPR(reg,_offset,rel_reg);RESTORE_GPR(reg+1,_offset,rel_reg)
+#define RESTORE_GPR4(reg,_offset,rel_reg) RESTORE_GPR2(reg,_offset,rel_reg);RESTORE_GPR2(reg+2,_offset,rel_reg)
+#define RESTORE_GPR8(reg,_offset,rel_reg) RESTORE_GPR4(reg,_offset,rel_reg);RESTORE_GPR4(reg+4,_offset,rel_reg)
+
+// Non volatile regs, 14-31( saved by function called )
+#define SAVE_NVGPR(rel_reg,_offset) SAVE_GPR2(14,_offset,rel_reg); \
+ SAVE_GPR8(16,_offset,rel_reg); \
+ SAVE_GPR8(24,_offset,rel_reg);
+
+#define RESTORE_NVGPR(rel_reg,_offset) RESTORE_GPR2(14,_offset,rel_reg); \
+ RESTORE_GPR8(16,_offset,rel_reg); \
+ RESTORE_GPR8(24,_offset,rel_reg);
+
+#define NVGPR_SIZE (18*GPR_SIZE)
+
+// Volatile regs, r0, r5-r12, [r13] ( r3, r4 are assumed to be save else where )
+#define SAVE_VGPR(rel_reg,_offset) SAVE_GPR(0,_offset,rel_reg);SAVE_GPR8(5,_offset, rel_reg)
+#define RESTORE_VGPR(rel_reg,_offset) RESTORE_GPR(0,_offset, rel_reg);RESTORE_GPR8(5,_offset, rel_reg)
+#define VGPR_SIZE (14*GPR_SIZE)
+
+#define EXC_BASE_OFF 0 //(VGPR_SIZE+NVGPR_SIZE+C_SIZE)
+#define EXC_OFF_FROM_BOTTOM (VGPR_SIZE+NVGPR_SIZE+C_SIZE)
+
+
+/* Exception frame */
+#if defined(CFG_SPE)
+#define EXC_SIZE 80
+#else
+#define EXC_SIZE 64 /* MUST be 16 byte aligned, again eabi */
+#endif
+
+#define EXC_SP_OFF (EXC_BASE_OFF+0)
+// 4 - backchain
+// 8 - padding
+#define EXC_SRR0_OFF (EXC_BASE_OFF+12)
+#define EXC_SRR1_OFF (EXC_BASE_OFF+16)
+#define EXC_LR_OFF (EXC_BASE_OFF+20)
+#define EXC_CTR_OFF (EXC_BASE_OFF+24)
+#define EXC_XER_OFF (EXC_BASE_OFF+28)
+#define EXC_CR_OFF (EXC_BASE_OFF+32)
+#define EXC_ESR_OFF (EXC_BASE_OFF+36)
+#define EXC_MCSR_OFF (EXC_BASE_OFF+40)
+#define EXC_DEAR_OFF (EXC_BASE_OFF+44)
+#define EXC_VECTOR_OFF (EXC_BASE_OFF+48)
+#if defined(CFG_SPE)
+#define EXC_SPEFSCR (EXC_BASE_OFF+52)
+#define EXC_R3_OFF (EXC_BASE_OFF+56) // 8 bytes..
+#define EXC_R4_OFF (EXC_BASE_OFF+64) // 8 bytes..
+#define EXC_SPE_ACC (EXC_BASE_OFF+72) // 8 bytes
+#else
+#define EXC_R3_OFF (EXC_BASE_OFF+52)
+#define EXC_R4_OFF (EXC_BASE_OFF+56)
+#endif
+
+
+/*-------------------------------------------------------------------
+ * Save exception frame macro
+ *-----------------------------------------------------------------*/
+
+#define SAVE_EXC_FRAME(work,rel_reg,_offset,xsrr0_spr,xsrr1_spr) \
+ mfspr work,xsrr0_spr; \
+ stw work,(EXC_SRR0_OFF+_offset)(rel_reg); \
+ mfspr work,xsrr1_spr; \
+ stw work,(EXC_SRR1_OFF+_offset)(rel_reg); \
+ mfspr work,SPR_XER; \
+ stw work,(EXC_XER_OFF+_offset)(rel_reg); \
+ mfspr work,SPR_CTR; \
+ stw work,(EXC_CTR_OFF+_offset)(rel_reg); \
+ mflr work; \
+ stw work,(EXC_LR_OFF+_offset)(rel_reg); \
+ /* TODO: all exceptions dont't need all the info below... but it's simple */ \
+ mfspr work,SPR_ESR; \
+ stw work,(EXC_ESR_OFF+_offset)(rel_reg); \
+ mfspr work,SPR_DEAR; \
+ stw work,(EXC_DEAR_OFF+_offset)(rel_reg); \
+ mfspr work,SPR_MCSR; \
+ stw work,(EXC_MCSR_OFF+_offset)(rel_reg); \
+ mfcr work; \
+ stw work,(EXC_CR_OFF+_offset)(rel_reg);
+
+
+/*-------------------------------------------------------------------
+ * Restore exception frame macro
+ *-----------------------------------------------------------------*/
+#define RESTORE_EXC_FRAME(work,rel_reg,_offset,xsrr0_spr,xsrr1_spr) \
+ lwz work,(EXC_SRR0_OFF+_offset)(rel_reg); \
+ mtspr xsrr0_spr,work; \
+ lwz work,(EXC_SRR1_OFF+_offset)(rel_reg); \
+ mtspr xsrr1_spr,work; \
+ lwz work,(EXC_XER_OFF+_offset)(rel_reg); \
+ mtspr SPR_XER,work; \
+ lwz work,(EXC_CTR_OFF+_offset)(rel_reg); \
+ mtspr SPR_CTR,work; \
+ lwz work,(EXC_LR_OFF+_offset)(rel_reg); \
+ mtlr work; \
+ lwz work,(EXC_ESR_OFF+_offset)(rel_reg); \
+ mtspr SPR_ESR,work; \
+ lwz work,(EXC_DEAR_OFF+_offset)(rel_reg); \
+ mtspr SPR_DEAR,work; \
+ lwz work,(EXC_MCSR_OFF+_offset)(rel_reg); \
+ mtspr SPR_MCSR,work; \
+ lwz work,(EXC_CR_OFF+_offset)(rel_reg); \
+ mtcr work; \
+
+
+
+#define EXCEPTION_CRITICAL_PROLOGUE(vector) \
+ addi sp,sp,-EXC_SIZE; \
+ stw r3,EXC_R3_OFF(r1); \
+ stw r4,EXC_R4_OFF(r1); \
+ li r4,vector; \
+ stw r4,EXC_VECTOR_OFF(r1); \
+ SAVE_EXC_FRAME(3,1,0,SPR_CSRR0,SPR_CSRR1)
+
+
+#define EXCEPTION_CRITICAL_EPILOGUE(vector) \
+ RESTORE_EXC_FRAME(3,1,0,SPR_CSRR0,SPR_CSRR1); \
+ lwz r3,EXC_R3_OFF(r1); \
+ lwz r4,EXC_R4_OFF(r1); \
+ addi sp,sp,EXC_SIZE;
+
+
+#define EXCEPTION_PROLOGUE(vector) \
+ addi sp,sp,-EXC_SIZE; \
+ stw r3,EXC_R3_OFF(r1); \
+ stw r4,EXC_R4_OFF(r1); \
+ li r4,vector; \
+ stw r4,EXC_VECTOR_OFF(r1); \
+ SAVE_EXC_FRAME(3,1,0,SPR_SRR0,SPR_SRR1)
+
+
+#define EXCEPTION_EPILOGUE() \
+ RESTORE_EXC_FRAME(3,1,0,SPR_SRR0,SPR_SRR1); \
+ lwz r3,EXC_R3_OFF(r1); \
+ lwz r4,EXC_R4_OFF(r1); \
+ addi sp,sp,EXC_SIZE;
+
+
+#define CALL_HANDLER() CALL_HANDLER_(intc_vector_tbl)
+
+//-------------------------------------------------------------------
+
+#define CALL_HANDLER_(_table) \
+ lis r3, _table@h; \
+ ori r3, r3, _table@l; \
+ slwi r4,r4,2; /* times 4 */ \
+ add r3,r3,r4; \
+ lwz r3,0(r3); /* get the entry */ \
+ cmpli 0,r3,0; \
+ beq+ bad_int; \
+ mtctr r3; \
+ mr r3,r1; /* use stack as arg */ \
+ subi r1,r1,16; /* space for backchain */ \
+ bctrl; \
+ addi r1,r1,16
+
+//-------------------------------------------------------------------
+
+#define EXCEPTION_CSRRx(_section,_vector) \
+ .global _section; \
+ .balign 16; \
+_section:; \
+ EXCEPTION_CRITICAL_PROLOGUE(_vector); \
+ CALL_HANDLER(); \
+ EXCEPTION_CRITICAL_EPILOGUE(); \
+ rfci
+
+
+#define EXCEPTION_SRRx(_section,_vector) \
+ .global _section; \
+ .balign 16; \
+_section:; \
+ EXCEPTION_PROLOGUE(_vector); \
+ CALL_HANDLER(); \
+ EXCEPTION_EPILOGUE(); \
+ rfi
+
+
+#if defined(_ASSEMBLER_)
+#if defined(CFG_SPE)
+
+.macro save_work_and_more
+ // work on the exception frame for now..
+ addi sp,sp,-(EXC_SIZE)
+
+ mtspr SPR_SPRG0_RW_S,r3
+ // Enable SPE (exceptions turns it off)
+ mfmsr r3
+ oris r3,r3,0x0200
+ mtmsr r3
+ isync
+
+ mfspr r3, SPR_SPRG0_RW_S
+
+ // Save 64-bit r3 and r4
+ evstdd r3,EXC_R3_OFF(r1)
+ evstdd r4,EXC_R4_OFF(r1)
+
+ // SPEFSCR
+ mfspr r3,SPR_SPEFSCR
+ clrlwi r3,r3,24 /* Mask off non-status bits */
+ stw r3,EXC_SPEFSCR(sp)
+
+ // Save SPE acc
+ evsubfw r3,r3,r3 // zero r3
+ evaddumiaaw r3,r3 // Add r3 = r3 + acc -> r3 = acc
+ evstdd r3,EXC_SPE_ACC(r1)
+
+ SAVE_EXC_FRAME(3,1,0,SPR_SRR0,SPR_SRR1)
+
+ // Save access through r4
+ mr r4,r1
+ // Make place for the other stack frames.
+ addi sp,sp,-(VGPR_SIZE+NVGPR_SIZE+C_SIZE)
+.endm
+
+.macro restore_work_and_more
+ // Stack is below C frame.... access EXC frame.
+ addi sp,sp,(C_SIZE+NVGPR_SIZE+VGPR_SIZE)
+
+ // Store the SPE control/status reg.
+ lwz r3,EXC_SPEFSCR(sp)
+ mtspr SPR_CSRR0,r3
+
+ /* Load SPE acc */
+ evldd r3,EXC_SPE_ACC(r1)
+ evmra r3,r3
+
+ RESTORE_EXC_FRAME(3,1,0,SPR_SRR0,SPR_SRR1);
+
+ evldd r3,EXC_R3_OFF(r1)
+ evldd r4,EXC_R4_OFF(r1)
+
+ addi sp,sp,EXC_SIZE
+
+.endm
+#else
+.macro save_work_and_more
+ addi sp,sp,-(EXC_SIZE)
+
+ stw r3,EXC_R3_OFF(r1)
+ stw r4,EXC_R4_OFF(r1)
+
+ SAVE_EXC_FRAME(3,1,0,SPR_SRR0,SPR_SRR1)
+
+ // Save access through r4
+ mr r4,r1
+ // Make place for the other stack frames.
+ addi sp,sp,-(VGPR_SIZE+NVGPR_SIZE+C_SIZE)
+.endm
+
+.macro restore_work_and_more
+ // Work on the exception frame.
+ addi sp,sp,(VGPR_SIZE+NVGPR_SIZE+C_SIZE)
+
+ RESTORE_EXC_FRAME(3,1,0,SPR_SRR0,SPR_SRR1);
+
+ lwz r3,EXC_R3_OFF(r1);
+ lwz r4,EXC_R4_OFF(r1);
+
+ addi sp,sp,EXC_SIZE
+.endm
+#endif
+#endif
+
+#endif /* _ASM_BOOK_E_H */
+
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef PPC_ASM_H_\r
+#define PPC_ASM_H\r
+\r
+/* Context\r
+ * =================================================\r
+ * We have two context's large and small. Large is saved on\r
+ * interrupt and small is saved for everything else.\r
+ *\r
+ * Layout:\r
+ *\r
+ * offset\r
+ * -------------------------------\r
+ * 0--1 : context indicator, 0xde - small, 0xad - large\r
+ * 4 : lr\r
+ * 8 : cr\r
+ * 12 : sp\r
+ *\r
+ * small layout\r
+ * 16-- : General regs r14--r31\r
+ *\r
+ * large layout\r
+ * 16-- : General regs r0--r31\r
+ *\r
+ */\r
+\r
+/*\r
+ * -------- botton(high address )\r
+ * Context\r
+ * --------\r
+ *\r
+ * -------- top\r
+ *\r
+ * kind of frames...\r
+ * -------------------------------\r
+ * C_xxxx - common frame to both large and small context\r
+ * EXC_xxx - exception frame\r
+ * SC_xxx - small context frame\r
+ * LC_xxx - large context frame\r
+ *\r
+ *\r
+ *\r
+ *\r
+ */\r
+\r
+\r
+#define SPR_SRR0 26\r
+#define SPR_SRR1 27\r
+\r
+#define SPR_CSRR0 58\r
+#define SPR_CSRR1 59\r
+\r
+#define SPR_SPRG0_RW_S 272\r
+#define SPR_SPRG1_RW_S 273\r
+\r
+#define SPR_DEAR 61\r
+#define SPR_ESR 62\r
+#define SPR_TSR 336\r
+#define SPR_SPEFSCR 512\r
+#define SPR_MCSR 572\r
+\r
+#define ESR_PTR (1<<(38-32))\r
+\r
+#define SPR_XER 1\r
+#define SPR_CTR 9\r
+\r
+\r
+/*\r
+ * Misc macros\r
+ */\r
+#define LOAD_IND_32( reg, addr) \\r
+ lis reg, addr@ha; \\r
+ lwz reg, addr@l(reg)\r
+\r
+#define LOAD_ADDR_32(reg, addr ) \\r
+ addis reg, 0, addr@ha; \\r
+ addi reg, reg, addr@l\r
+\r
+\r
+/* GPRS */\r
+#define sp 1\r
+#define r0 0\r
+#define r1 1\r
+#define r2 2\r
+#define r3 3\r
+#define r4 4\r
+#define r5 5\r
+#define r6 6\r
+#define r7 7\r
+#define r8 8\r
+#define r9 9\r
+#define r10 10\r
+#define r11 11\r
+#define r12 12\r
+#define r13 13\r
+#define r14 14\r
+#define r15 15\r
+#define r16 16\r
+#define r17 17\r
+#define r18 18\r
+#define r19 19\r
+#define r20 20\r
+#define r21 21\r
+#define r22 22\r
+#define r23 23\r
+#define r24 24\r
+#define r25 25\r
+#define r26 26\r
+#define r27 27\r
+#define r28 28\r
+#define r29 29\r
+#define r30 30\r
+#define r31 31\r
+\r
+#endif /*PPC_ASM_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*\r
+ * mpc55xx.h\r
+ *\r
+ * Created on: Jul 13, 2009\r
+ * Author: mahi\r
+ */\r
+\r
+#ifndef MPC55XX_H_\r
+#define MPC55XX_H_\r
+\r
+\r
+#if defined(CFG_MPC5554)\r
+#include "mpc5554.h"\r
+#elif defined(CFG_MPC5516) || defined(MPC5517)\r
+#include "mpc5516.h"\r
+#elif defined(CFG_MPC5567)\r
+#include "mpc5567.h"\r
+#else\r
+#error NO MCU SELECTED!!!!\r
+#endif\r
+\r
+//#include "mpc55xx_aos.h"\r
+\r
+#endif /* MPC55XX_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*
+ * strace.h
+ *
+ * Created on: May 11, 2009
+ * Author: mahi
+ */
+
+#ifndef STRACE_H_
+#define STRACE_H_
+
+#ifdef USE_STRACE
+#define STRACE(_x) strace((_x))
+#else
+#define STRACE(_x)
+#endif
+
+#endif /* STRACE_H_ */
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*
+ * xtoa.h
+ *
+ * Created on: May 3, 2009
+ * Author: mahi
+ */
+
+#ifndef XTOA_H_
+#define XTOA_H_
+
+void xtoa(unsigned long val, char* str, int base,int negative);
+// unsigned long to string
+void ultoa(unsigned long value, char* str, int base);
+// int to string
+void itoa(int value, char* str, int base);
+
+
+#endif /* XTOA_H_ */
--- /dev/null
+\r
+# build with:\r
+# make subdir1 - build the subdir1 \r
+# make subdir1/subdir2 - build subdir2\r
+# \r
+# clean:\r
+# Removed all generated files \r
+#\r
+# BOARDDIR=<board dir> \r
+# Select what board to build for \r
+\r
+# BOARDDIR=<board dir> \r
+# Select what board to build for\r
+# \r
+# Q=[(@)/empty] \r
+# If Q=@ cmd's will not be echoed.\r
+# \r
+# Build\r
+# >make BOARDDIR=mpc551xsim BDIR=system/kernel,examples/simple all \r
+# Clean \r
+# >make BOARDDIR=mpc551xsim BDIR=system/kernel,examples/simple clean\r
+#\r
+\r
+\r
+\r
+#-include board_config.mk\r
+#export ARCH\r
+#export ARCH_FAM\r
+#export BOARDDIR\r
+\r
+UNAME:=$(shell uname)\r
+\r
+ifneq ($(findstring Darwin,$(UNAME)),)\r
+ SHELL:=/bin/bash\r
+ export SED=/opt/local/bin/gsed\r
+else\r
+ export SED=sed\r
+endif\r
+\r
+USE_DBG_PRINTF?=y\r
+\r
+Q?=@\r
+export Q\r
+export TOPDIR = $(CURDIR)\r
+export RELEASE = n\r
+export PATH\r
+\r
+#ifeq (${BDIR},)\r
+# -include saved_config.mk\r
+#endif\r
+\r
+ifneq ($(filter clean_all,$(MAKECMDGOALS)),clean_all)\r
+ ifeq (${BOARDDIR},)\r
+ $(error BOARDDIR is empty) \r
+ endif\r
+endif\r
+\r
+USE_T32_SIM?=n\r
+export USE_T32_SIM\r
+\r
+export BUILD_TREE=y\r
+export RELEASE_TREE=n\r
+\r
+override BDIR := system/kernel ${BDIR} \r
+#BDIR += system/kernel/testsystem\r
+\r
+# Misc\r
+#subdir-y += ecum\r
+# Drivers\r
+\r
+\r
+# Tools\r
+# Ugly thing to make things work under cmd.exe \r
+PATH := /usr/bin/:$(PATH) \r
+find := $(shell which find)\r
+\r
+export objdir = obj_$(BOARDDIR)\r
+\r
+#comma = ,\r
+#empty = \r
+#space = $(empty) $(empty) \r
+\r
+.PHONY: clean\r
+.PHONY: release\r
+\r
+.PHONY: help\r
+help:\r
+ @echo "Make kernel and a simple example"\r
+ @echo " > make BOARDDIR=mpc551xsim CROSS_COMPILE=/opt/powerpc-eabi/bin/powerpc-eabi- BDIR=system/kernel,examples/simple all"\r
+ @echo ""\r
+ @echo "Save the config (CROSS_COMPILE and BDIR)"\r
+ @echo " > make BOARDDIR=mpc551xsim CROSS_COMPILE=/opt/powerpc-eabi/bin/powerpc-eabi- BDIR=system/kernel,examples/simple save"\r
+ @echo ""\r
+ @echo "Clean"\r
+ @echo " > make clean"\r
+ @echo ""\r
+ @echo "Present config:"\r
+ @echo " ARCH=$(ARCH)"\r
+ @echo " ARCH_FAM=$(ARCH_FAM)"\r
+ @echo " BOARDDIR =$(BOARDDIR)"\r
+ @echo " CROSS_COMPILE =$(CROSS_COMPILE)"\r
+ @echo ""\r
+ \r
+def-$(USE_T32_SIM) += USE_T32_SIM\r
+def-$(USE_DBG_PRINTF) += USE_DBG_PRINTF\r
+\r
+\r
+export CFG_MCU \r
+export CFG_CPU\r
+export MCU\r
+export def-y+=$(CFG_ARCH_$(ARCH)) $(CFG_MCU) $(CFG_CPU)\r
+\r
+BASEDIR = $(TOPDIR)/$(MOD)\r
+\r
+# We descend into the object directories and build the. That way it's easier to build\r
+# multi-arch support and we don't have to use objdir everywhere.\r
+# ROOTDIR - The top-most directory\r
+# SUBDIR - The current subdirectory it's building.\r
+\r
+test:\r
+ make embUnit/textui embunit/embUnit drivers/test all\r
+\r
+comma:= ,\r
+split = $(subst $(comma), ,$(1))\r
+\r
+\r
+#dir_cmd_goals := $(filter-out %_config config testa all install uninstall clean test save,$(MAKECMDGOALS))\r
+dir_cmd_goals := $(call split,$(BDIR))\r
+\r
+cmd_cmd_goals := $(filter clean all install,$(MAKECMDGOALS))\r
+\r
+#$(error $(dir_cmd_goals) $(MAKECMDGOALS))\r
+\r
+libs:\r
+ mkdir -p $@\r
+\r
+all: libs $(dir_cmd_goals)\r
+\r
+show_build:\r
+ @echo Building for $(dir_cmd_goals)\r
+ @echo BOARDDIR: $(BOARDDIR)\r
+ @echo ARCH_FAM/ARCH: $(ARCH_FAM)/$(ARCH)\r
+ \r
+\r
+$(dir_cmd_goals) :: show_build FORCE \r
+ @echo ==========[ $@ ]===========\r
+ +@[ -d $@/$(objdir) ] || mkdir -p $@/$(objdir)\r
+ @chmod 777 $@/$(objdir)\r
+ $(Q)$(MAKE) -r -C $@/$(objdir) -f $(CURDIR)/scripts/rules.mk ROOTDIR=$(CURDIR) SUBDIR=$@ $(cmd_cmd_goals)\r
+\r
+\r
+# --no-print-directory\r
+\r
+.PHONY: test \r
+\r
+FORCE:\r
+\r
+clean_all:\r
+ @find . -type d -name obj_* | xargs rm -rf\r
+ @find . -type f -name *.a | xargs rm -rf\r
+ echo Done!\r
+ \r
+clean: $(dir_cmd_goals)\r
+ @echo "Clean:"\r
+ @echo " Removing objectfiles and libs for ARCH=$(ARCH)"\r
+ @find . -type d -name $(objdir) | xargs rm -rf\r
+ @find . -type f -name *.a| xargs rm -rf\r
+ @rm -rf libs/*\r
+ @echo Done!\r
+\r
+ \r
+ \r
+\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+
+#include "NvM.h"
+#include "Rte.h"
+#include "Dem.h"
+//#include "Crc.h"
+
+void NvM_Init( void ){
+
+}
+
+void NvM_ReadAll( void ) {
+
+}
+
+void NvM_WriteAll( void ) {
+
+}
+
+void NvM_CancelWriteAll( void ) {
+
+}
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef NVM_H_
+#define NVM_H_
+
+#include "NvM_Cfg.h"
+
+void NvM_Init( void );
+void NvM_ReadAll( void );
+void NvM_WriteAll( void );
+void NvM_CancelWriteAll( void );
+
+#endif /*NVM_H_*/
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+\r
+#ifndef NVM_CFG_H_\r
+#define NVM_CFG_H_\r
+\r
+#include "NvM_Types.h"\r
+\r
+#endif /*NVM_CFG_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef NVM_TYPES_H_
+#define NVM_TYPES_H_
+
+#include "Std_Types.h"
+
+typedef uint8 NvM_RequestResultType;
+
+typedef uint16 NvM_BlockIdType;
+
+void NvM_Init( void );
+void NvM_SetDataIndex( NvM_BlockIdType BlockId, uint8 DataIndex );
+void NvM_GetDataIndex( NvM_BlockIdType BlockId,uint8 *DataIndexPtr );
+void NvM_SetBlockProtection( NvM_BlockIdType BlockId, boolean ProtectionEnabled );
+void NvM_GetErrorStatus( NvM_BlockIdType BlockId, uint8 *RequestResultPtr );
+void NvM_GetVersionInfo( Std_VersionInfoType *VersionInfo );
+void Nvm_SetRamBlockStatus( NvM_BlockIdType BlockId, boolean BlockChanged );
+void Nvm_ReadBlock( NvM_BlockIdType BlockId, uint8 *NvM_DstPtr );
+void NvM_WriteBlock( NvM_BlockIdType BlockId, const uint8 *NvM_SrcPtr );
+void Nvm_RestoreBlockDefaults( NvM_BlockIdType BlockId, uint8 *NvM_DstPtr );
+void NvM_EraseNvBlock( NvM_BlockIdType BlockId );
+void NvM_CancelWriteAll( void );
+void NvM_InvalidateNvBlock( NvM_BlockIdType BlockId );
+void NvM_ReadAll( void );
+void NvM_WriteAll( void );
+
+#endif /*NVM_TYPES_H_*/
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#if 1\r
+\r
+\r
+/* CONFIGURATION NOTES\r
+ * The configuration is simple, use the template supplied.\r
+ * Changing the configuration is NOT recommended.\r
+ */\r
+\r
+/* REQUIREMENTS:\r
+ * - Variant PB is supported not PC ( FLS203,FLS204 )\r
+ * - Since DEM is NOT supported all those requirements are not supported.\r
+ * - AC is not supported since it makes no sense for a SPI flash.\r
+ *
+ */\r
+\r
+/* IMPLEMENTATION NOTES\r
+ * - The only SPI flash supported is the SST25VF016B although the\r
+ * entire SST25XX should work through configuration changes\r
+ * - Commands that are used by this module are:\r
+ * WREN,WRDI,WRSR,byte write and erase 4K\r
+ * - AC is not supported since the there's no use for it.\r
+ * - Supports 64 bytes read, byte write and 4K erase\r
+ * - The implementation very much dependent on the configuration\r
+ * of the SPI( Spi_Cfg.c )\r
+ * - Calls from SPI are not checked( Only makes sense if DEM is supported )\r
+ *\r
+ */\r
+\r
+\r
+\r
+#include "Fls.h"\r
+#include "Fls_SST25xx.h"\r
+#include "Spi.h"\r
+//#include "Dem.h"\r
+#include "Det.h"\r
+#include <stdlib.h>\r
+#include <assert.h>\r
+//#include <stdio.h>\r
+#include <string.h>\r
+\r
+//#define USE_DEBUG\r
+#include "Trace.h"\r
+#define MODULE_NAME "/driver/Fls_25"\r
+\r
+\r
+/* The width in bytes used by this flash */\r
+#define ADDR_LENGTH 3\r
+\r
+/* Helper macro for the process function */\r
+#define SET_STATE(_done,_state) done=(_done);job->state=(_state)\r
+\r
+/* How many loops to wait for SPI to go back to "normal" state after\r
+ * read/write/erase */
+ #define TIMER_BUSY_WAIT 100000\r
+\r
+#if FLS_SST25XX_DEV_ERROR_DETECT\r
+#define FLS_VALIDATE_PARAM_ADDRESS_SECTOR_W_RV(_addr, _api, _rv)\\r
+ int sectorIndex;\\r
+ int addrOk=0;\\r
+ Fls_SectorType sector;\\r
+ for (sectorIndex=0; sectorIndex<Fls_SST25xx_Global.config->FlsSectorListSize;sectorIndex++) {\\r
+ sector = Fls_SST25xx_Global.config->FlsSectorList[sectorIndex];\\r
+ if((((uint32)_addr-sector.FlsSectorStartaddress) / sector.FlsSectorSize)<sector.FlsNumberOfSectors){\\r
+ /* Within the right adress space */\\r
+ if (!(((uint32)_addr-sector.FlsSectorStartaddress) % sector.FlsSectorSize)){\\r
+ /* Address is correctly aligned */\\r
+ addrOk=1;\\r
+ break;\\r
+ }\\r
+ }\\r
+ }\\r
+ if (1!=addrOk){\\r
+ Det_ReportError(MODULE_ID_FLS,0,_api,FLS_E_PARAM_ADDRESS ); \\r
+ return _rv; \\r
+ }\r
+\r
+#define FLS_VALIDATE_PARAM_ADDRESS_PAGE_W_RV(_addr, _api, _rv)\\r
+ int sectorIndex;\\r
+ int addrOk=0;\\r
+ Fls_SectorType sector;\\r
+ for (sectorIndex=0; sectorIndex<Fls_SST25xx_Global.config->FlsSectorListSize;sectorIndex++) {\\r
+ sector = Fls_SST25xx_Global.config->FlsSectorList[sectorIndex];\\r
+ if((((uint32)_addr-sector.FlsSectorStartaddress) / sector.FlsSectorSize)<sector.FlsNumberOfSectors){\\r
+ /* Within the right adress space */\\r
+ if (!(((uint32)_addr-sector.FlsSectorStartaddress) % sector.FlsPageSize)){\\r
+ /* Address is correctly aligned */\\r
+ addrOk=1;\\r
+ break;\\r
+ }\\r
+ }\\r
+ }\\r
+ if (1!=addrOk){\\r
+ Det_ReportError(MODULE_ID_FLS,0,_api,FLS_E_PARAM_ADDRESS ); \\r
+ return _rv; \\r
+ }\r
+\r
+#define FLS_VALIDATE_PARAM_LENGTH_PAGE_W_RV(_addr, _length, _api, _rv)\\r
+ int i;\\r
+ int lengthOk=0;\\r
+ const Fls_SectorType* sectorPtr= &Fls_SST25xx_Global.config->FlsSectorList[0];\\r
+ for (i=0; i<Fls_SST25xx_Global.config->FlsSectorListSize;i++) {\\r
+ if ((sectorPtr->FlsSectorStartaddress + (sectorPtr->FlsNumberOfSectors * sectorPtr->FlsSectorSize))>=(uint32_t)(_addr+(_length))){\\r
+ if ((0!=_length)&&!(_length % sectorPtr->FlsPageSize)){\\r
+ lengthOk=1;\\r
+ break;\\r
+ }\\r
+ }\\r
+ sectorPtr++;\\r
+ }\\r
+ if (!lengthOk){\\r
+ Det_ReportError(MODULE_ID_FLS,0,_api,FLS_E_PARAM_LENGTH ); \\r
+ return _rv; \\r
+ }\r
+\r
+#define FLS_VALIDATE_PARAM_LENGTH_SECTOR_W_RV(_addr, _length, _api, _rv)\\r
+ int i;\\r
+ int lengthOk=0;\\r
+ const Fls_SectorType* sectorPtr= &Fls_SST25xx_Global.config->FlsSectorList[0];\\r
+ for (i=0; i<Fls_SST25xx_Global.config->FlsSectorListSize;i++) {\\r
+ if ((sectorPtr->FlsSectorStartaddress + (sectorPtr->FlsNumberOfSectors * sectorPtr->FlsSectorSize))>=(uint32_t)(_addr+(_length))){\\r
+ if ((0!=_length)&& !(_length % sectorPtr->FlsSectorSize)){\\r
+ lengthOk=1;\\r
+ break;\\r
+ }\\r
+ }\\r
+ sectorPtr++;\\r
+ }\\r
+ if (!lengthOk){\\r
+ Det_ReportError(MODULE_ID_FLS,0,_api,FLS_E_PARAM_LENGTH ); \\r
+ return _rv; \\r
+ }\r
+\r
+#define FLS_VALIDATE_STATUS_UNINIT_W_RV(_status, _api, _rv)\\r
+ if (MEMIF_UNINIT == _status){\\r
+ Det_ReportError(MODULE_ID_FLS,0,_api,FLS_E_UNINIT); \\r
+ return _rv; \\r
+ }\r
+\r
+#define FLS_VALIDATE_STATUS_BUSY(_status, _api)\\r
+ if (MEMIF_BUSY == _status){\\r
+ Det_ReportError(MODULE_ID_FLS,0,_api,FLS_E_BUSY); \\r
+ return; \\r
+ }\r
+\r
+#define FLS_VALIDATE_STATUS_BUSY_W_RV(_status, _api, _rv)\\r
+ if (MEMIF_BUSY == _status){\\r
+ Det_ReportError(MODULE_ID_FLS,0,_api,FLS_E_BUSY); \\r
+ return _rv; \\r
+ }\r
+\r
+#define FLS_VALIDATE_PARAM_DATA_W_RV(_ptr,_api, _rv) \\r
+ if( (_ptr)==((void *)0)) { \\r
+ Det_ReportError(MODULE_ID_FLS,0,_api,FLS_E_PARAM_DATA); \\r
+ return _rv; \\r
+ }\r
+#else\r
+ #define FLS_VALIDATE_PARAM_ADDRESS_SECTOR_W_RV(_addr, _api, _rv)\r
+ #define FLS_VALIDATE_PARAM_ADDRESS_PAGE_W_RV(_addr, _api, _rv)\r
+ #define FLS_VALIDATE_PARAM_LENGTH_SECTOR_W_RV(_addr, _length, _api, _rv)\r
+ #define FLS_VALIDATE_PARAM_LENGTH_PAGE_W_RV(_addr, _length, _api, _rv)\r
+ #define FLS_VALIDATE_STATUS_UNINIT_W_RV(_status, _api, _rv)\r
+ #define FLS_VALIDATE_STATUS_BUSY(_status, _api)\r
+ #define FLS_VALIDATE_STATUS_BUSY_W_RV(_status, _api, _rv)\r
+ #define FLS_VALIDATE_PARAM_DATA_W_RV(_ptr,_api,_rv)\r
+#endif\r
+\r
+#if ( FLS_DEV_ERROR_DETECT == STD_ON )\r
+#define VALIDATE_CONFIG(_x) assert(_x)\r
+#define DET_REPORTERROR(_x,_y,_z,_q) Det_ReportError(MODULE_ID_FLS, _y, _z, _q)\r
+#else\r
+#define VALIDATE_CONFIG(_x)\r
+#define DET_REPORTERROR(_x,_y,_z,_q)\r
+#endif\r
+\r
+#if ( FLS_GET_JOB_RESULT_API == STD_ON )\r
+#define FEE_JOB_END_NOTIFICATION() \\r
+ if( Fls_SST25xx_Global.config->FlsJobEndNotification != NULL ) { \\r
+ Fls_SST25xx_Global.config->FlsJobEndNotification(); \\r
+ }\r
+#define FEE_JOB_ERROR_NOTIFICATION() \\r
+ if( Fls_SST25xx_Global.config->FlsJobErrorNotification != NULL ) { \\r
+ Fls_SST25xx_Global.config->FlsJobErrorNotification(); \\r
+ }\r
+#else\r
+#define FEE_JOB_END_NOTIFICATION()\r
+#define FEE_JOB_ERROR_NOTIFICATION()\r
+#endif\r
+\r
+\r
+\r
+#if ( FLS_SST25XX_DEV_ERROR_DETECT == STD_ON ) // Report DEV errors\r
+#define VALIDATE(_exp,_api,_err ) \\r
+ if( !(_exp) ) { \\r
+ Det_ReportError(MODULE_ID_FLS,0,_api,_err); \\r
+ return; \\r
+ }\r
+#endif\r
+\r
+#define VALIDATE_W_RV(_exp,_api,_err,_rv ) \\r
+ if( !(_exp) ) { \\r
+ Det_ReportError(MODULE_ID_FLS,0,_api,_err); \\r
+ return (_rv); \\r
+ }\r
+\r
+#define VALID_CHANNEL(_ch) ( Gpt_Global.configured & (1<<(_ch)) )\r
+\r
+#else // Validate but do not report\r
+#define VALIDATE(_exp,_api,_err )\\r
+ if( !(_exp) ) { \\r
+ return; \\r
+ }\r
+#define VALIDATE_W_RV(_exp,_api,_err,_rv )\\r
+ if( !(_exp) ) { \\r
+ return (_rv); \\r
+ }\r
+#endif\r
+\r
+const Fls_ConfigType* _Fls_SST25xx_ConfigPtr;\r
+\r
+#if ( FLS_SST25XX_VERSION_INFO_API == STD_ON )\r
+static Std_VersionInfoType Fls_SST25XX_VersionInfo = {\r
+ .vendorID = (uint16)1,\r
+ .moduleID = (uint16) MODULE_ID_FLS,\r
+ .instanceID = (uint8)1,\r
+ /* Vendor numbers */\r
+ .sw_major_version = (uint8)FLS_SST25XX_SW_MAJOR_VERSION,\r
+ .sw_minor_version = (uint8)FLS_SST25XX_SW_MINOR_VERSION,\r
+ .sw_patch_version = (uint8)FLS_SST25XX_SW_PATCH_VERSION,\r
+ .ar_major_version = (uint8)FLS_SST25XX_AR_MAJOR_VERSION,\r
+ .ar_minor_version = (uint8)FLS_SST25XX_AR_MINOR_VERSION,\r
+ .ar_patch_version = (uint8)FLS_SST25XX_AR_PATCH_VERSION,\r
+};\r
+#endif\r
+\r
+/* Job state */\r
+typedef enum {\r
+ FLS_SST25XX_NONE,\r
+ FLS_SST25XX_COMPARE,\r
+ FLS_SST25XX_ERASE,\r
+ FLS_SST25XX_READ,\r
+ FLS_SST25XX_WRITE,\r
+} Fls_SST25xx_EcoreJobType;\r
+\r
+/* Spi job state */\r
+typedef enum {\r
+ JOB_MAIN,\r
+ JOB_READ_STATUS,\r
+ JOB_READ_STATUS_RESULT,\r
+} Job_StateType;\r
+\r
+/* Information about a job */\r
+typedef struct {\r
+ uint8 *targetAddr;\r
+ Fls_AddressType flsAddr;\r
+ uint32 left;\r
+ Job_StateType state;\r
+ Fls_SST25xx_EcoreJobType mainState;\r
+ Spi_SequenceType currSeq;\r
+ uint32 chunkSize;\r
+} Fls_SST25xx_JobInfoType;\r
+\r
+#define JOB_SET_STATE(_x,_y) job->state=(_x);job->mainState=(_y)\r
+\r
+\r
+typedef struct {\r
+ const Fls_ConfigType *config;\r
+\r
+ // Status of driver\r
+ MemIf_StatusType status;\r
+ MemIf_JobResultType jobResultType;\r
+ Fls_SST25xx_EcoreJobType jobType;\r
+\r
+ // Saved information from API calls.\r
+ Fls_AddressType flsAddr;\r
+ uint8 *targetAddr;\r
+ Fls_LengthType length;\r
+\r
+ // Data containers for EB buffers\r
+ Spi_DataType ebCmd;\r
+ Spi_DataType ebReadStatus;\r
+ Spi_DataType ebFlsAddr[ADDR_LENGTH];\r
+\r
+ // What mode we are in ( normal/fast )\r
+ MemIf_ModeType mode;\r
+\r
+ // Hold job information\r
+ Fls_SST25xx_JobInfoType job;\r
+\r
+} Fls_SST25xx_GlobalType;\r
+\r
+Fls_SST25xx_GlobalType Fls_SST25xx_Global;\r
+\r
+#if 0\r
+#define SPI_TRANSMIT_FUNC(_x) Spi_SyncTransmit(_x)\r
+#else\r
+#define SPI_TRANSMIT_FUNC(_x,_y) Fls_SST25xx_AsyncTransmit(_x,_y)\r
+\r
+Std_ReturnType Fls_SST25xx_AsyncTransmit(Spi_SequenceType Sequence,Fls_SST25xx_JobInfoType *job) {\r
+ Std_ReturnType rv;\r
+ job->currSeq = Sequence;\r
+ rv = Spi_AsyncTransmit(Sequence);\r
+ return rv;\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ * Convert Fls_AddressType to something used by SPI\r
+ *\r
+ * @param spiAddr Address to convert to SPI address\r
+ * @param addr Pointer to the SPI address to be written\r
+ *\r
+ */\r
+static void Spi_ConvertToSpiAddr(Spi_DataType *spiAddr, Fls_AddressType addr ) {\r
+\r
+ spiAddr[0] = (addr>>16)&0xff; // MSB first\r
+ spiAddr[1] = (addr>>8)&0xff;\r
+ spiAddr[2] = (addr)&0xff;\r
+\r
+}\r
+\r
+/**\r
+ * Get configuration sector information from a flash address\r
+ *\r
+ * @param addr The address
+ */\r
+\r
+static const Fls_SectorType * Fls_SST25xx_GetSector( Fls_AddressType addr ) {\r
+ int sectorIndex;\r
+ const Fls_SectorType *sector;\r
+\r
+ for (sectorIndex=0; sectorIndex<Fls_SST25xx_Global.config->FlsSectorListSize;sectorIndex++) {\r
+ sector = &Fls_SST25xx_Global.config->FlsSectorList[sectorIndex];\r
+ if((((uint32)addr-sector->FlsSectorStartaddress) / sector->FlsSectorSize)<sector->FlsNumberOfSectors){\r
+ return sector;\r
+ }\r
+ }\r
+ assert(0);\r
+ return NULL;\r
+ }\r
+\r
+void Fls_SST25xx_Init( const Fls_ConfigType* ConfigPtr ){\r
+\r
+ FLS_VALIDATE_STATUS_BUSY(Fls_SST25xx_Global.status, FLS_INIT_ID);\r
+\r
+#if ( FLS_SST25XX_VARIANT_PB == STD_ON )\r
+ VALIDATE( (ConfigPtr != NULL) , FLS_INIT_ID, FLS_E_PARAM_CONFIG );\r
+#endif\r
+\r
+ Fls_SST25xx_Global.config = ConfigPtr;\r
+ Spi_DataType data = 0;\r
+ int timer = 0;\r
+ Std_ReturnType rv = E_OK;\r
+ Spi_DataType jedecId[3];\r
+\r
+\r
+\r
+ // Do some basic testing of configuration data, FLS205\r
+ VALIDATE_CONFIG(ConfigPtr->FlsMaxReadFastMode != 0 );\r
+ VALIDATE_CONFIG(ConfigPtr->FlsMaxReadNormalMode != 0 );\r
+ VALIDATE_CONFIG(ConfigPtr->FlsMaxWriteFastMode != 0 );\r
+ VALIDATE_CONFIG(ConfigPtr->FlsMaxWriteNormalMode != 0 );\r
+\r
+ VALIDATE_CONFIG(ConfigPtr->FlsAcWrite == NULL ); // NOT supported\r
+ VALIDATE_CONFIG(ConfigPtr->FlsAcErase == NULL ); // NOT supported\r
+\r
+ // Setup External buffers for jobs and sequences\r
+ Spi_SetupEB( SPI_CH_FLASH_CMD, &Fls_SST25xx_Global.ebCmd,NULL,sizeof(Fls_SST25xx_Global.ebCmd)/sizeof(Fls_SST25xx_Global.ebCmd));\r
+ Spi_SetupEB( SPI_CH_FLASH_ADDR, Fls_SST25xx_Global.ebFlsAddr,NULL,sizeof(Fls_SST25xx_Global.ebFlsAddr)/sizeof(Fls_SST25xx_Global.ebFlsAddr[0]));\r
+ Spi_SetupEB( SPI_CH_FLASH_WREN, NULL,NULL,1);\r
+ Spi_SetupEB( SPI_CH_FLASH_WRDI, NULL,NULL,1);\r
+ Spi_SetupEB( SPI_CH_FLASH_WRSR, NULL,NULL,1);\r
+\r
+ /* Check that the JEDEC ID can be read */\r
+ Spi_SetupEB( SPI_CH_FLASH_DATA, NULL ,jedecId,3);\r
+\r
+ Fls_SST25xx_Global.ebCmd = FLASH_JEDEC_ID;\r
+ Spi_SyncTransmit(SPI_SEQ_FLASH_CMD_DATA );\r
+\r
+ if( ((jedecId[0]<<16) + (jedecId[1]<<8) + jedecId[2]) != 0xbf2541 ) {\r
+ dbg_printf("JEDEC: %02x %02x %02x\n",jedecId[0],jedecId[1],jedecId[2]);\r
+ assert(0);\r
+ }\r
+\r
+ /* The flash comes locked from factory so it must be unlocked.\r
+ * The unlock is done in here instead before each write to reduce overhead.\r
+ * ( The flash is still protected by WREN )\r
+ */\r
+\r
+ /* Unlock flash with sync API. */\r
+ Spi_SetupEB( SPI_CH_FLASH_DATA, &data, NULL,1);\r
+ rv = Spi_SyncTransmit(SPI_SEQ_FLASH_WRSR);\r
+\r
+ // Busy wait\r
+ Spi_SetupEB( SPI_CH_FLASH_DATA, NULL, &Fls_SST25xx_Global.ebReadStatus, 1);\r
+ do {\r
+ Fls_SST25xx_Global.ebCmd = FLASH_RDSR;\r
+ Spi_SyncTransmit(SPI_SEQ_FLASH_CMD2);\r
+ timer++;\r
+ } while( (Fls_SST25xx_Global.ebReadStatus != 0) && (timer < TIMER_BUSY_WAIT ));\r
+\r
+ assert(timer!=TIMER_BUSY_WAIT);\r
+\r
+ Fls_SST25xx_Global.status = MEMIF_IDLE;\r
+ Fls_SST25xx_Global.jobResultType = MEMIF_JOB_PENDING;\r
+\r
+ // Set currSeq to any sequence we use\r
+ Fls_SST25xx_Global.job.currSeq = SPI_SEQ_FLASH_WRSR;\r
+\r
+}\r
+\r
+#if ( FLS_SST25XX_SET_MODE_API == STD_ON )\r
+void Fls_SST25xx_SetMode( MemIf_ModeType Mode ){\r
+ VALIDATE( ( Fls_SST25xx_Global.status != MEMIF_UNINIT ), FLS_SET_MODE_ID, FLS_E_UNINIT );\r
+ VALIDATE( ( Fls_SST25xx_Global.status != MEMIF_BUSY ), FLS_SET_MODE_ID, FLS_E_BUSY );\r
+\r
+ Fls_SST25xx_Global.mode = Mode;\r
+}\r
+#endif\r
+\r
+Std_ReturnType Fls_SST25xx_Read ( Fls_AddressType SourceAddress,\r
+ uint8 *TargetAddressPtr,\r
+ Fls_LengthType Length )\r
+{\r
+ Fls_SST25xx_JobInfoType *job = &Fls_SST25xx_Global.job;\r
+\r
+ FLS_VALIDATE_STATUS_UNINIT_W_RV(Fls_SST25xx_Global.status, FLS_READ_ID, E_NOT_OK);\r
+ FLS_VALIDATE_STATUS_BUSY_W_RV(Fls_SST25xx_Global.status, FLS_READ_ID, E_NOT_OK);\r
+ FLS_VALIDATE_PARAM_ADDRESS_PAGE_W_RV(SourceAddress, FLS_READ_ID, E_NOT_OK);\r
+ FLS_VALIDATE_PARAM_LENGTH_PAGE_W_RV(SourceAddress, Length, FLS_READ_ID, E_NOT_OK);\r
+ FLS_VALIDATE_PARAM_DATA_W_RV((void*)TargetAddressPtr, FLS_READ_ID, E_NOT_OK)\r
+\r
+ Fls_SST25xx_Global.status = MEMIF_BUSY;\r
+ Fls_SST25xx_Global.jobResultType = MEMIF_JOB_PENDING;\r
+ Fls_SST25xx_Global.jobType = FLS_SST25XX_READ;\r
+\r
+ if( Fls_SST25xx_Global.mode == MEMIF_MODE_FAST ) {\r
+ job->chunkSize = Fls_SST25xx_Global.config->FlsMaxReadFastMode;\r
+ } else {\r
+ job->chunkSize = Fls_SST25xx_Global.config->FlsMaxReadNormalMode;\r
+ }\r
+\r
+ job->flsAddr = SourceAddress;\r
+ job->targetAddr = TargetAddressPtr;\r
+ job->left = Length;\r
+\r
+ JOB_SET_STATE(JOB_MAIN,FLS_SST25XX_READ);\r
+\r
+ return E_OK;\r
+\r
+}\r
+\r
+Std_ReturnType Fls_SST25xx_Erase( Fls_AddressType TargetAddress, Fls_LengthType Length ){\r
+ Fls_SST25xx_JobInfoType *job = &Fls_SST25xx_Global.job;\r
+\r
+ FLS_VALIDATE_STATUS_UNINIT_W_RV(Fls_SST25xx_Global.status, FLS_ERASE_ID, E_NOT_OK);\r
+ FLS_VALIDATE_STATUS_BUSY_W_RV(Fls_SST25xx_Global.status, FLS_ERASE_ID, E_NOT_OK);\r
+ FLS_VALIDATE_PARAM_ADDRESS_SECTOR_W_RV(TargetAddress, FLS_ERASE_ID, E_NOT_OK);\r
+ FLS_VALIDATE_PARAM_LENGTH_SECTOR_W_RV(TargetAddress, Length, FLS_ERASE_ID, E_NOT_OK);\r
+\r
+ Fls_SST25xx_Global.status = MEMIF_BUSY;\r
+ Fls_SST25xx_Global.jobResultType = MEMIF_JOB_PENDING;\r
+ Fls_SST25xx_Global.jobType = FLS_SST25XX_ERASE;\r
+\r
+ job->flsAddr = TargetAddress;\r
+ // Not used, so set to illegal value\r
+ job->targetAddr = (uint8 *)0;\r
+ job->left = Length;\r
+ job->chunkSize = Fls_SST25xx_GetSector(TargetAddress)->FlsSectorSize;\r
+\r
+ JOB_SET_STATE(JOB_MAIN,FLS_SST25XX_ERASE);\r
+\r
+ return E_OK;\r
+}\r
+\r
+Std_ReturnType Fls_SST25xx_Write( Fls_AddressType TargetAddress, const uint8* SourceAddressPtr, Fls_LengthType Length ){\r
+\r
+ Fls_SST25xx_JobInfoType *job = &Fls_SST25xx_Global.job;\r
+\r
+ FLS_VALIDATE_STATUS_UNINIT_W_RV(Fls_SST25xx_Global.status, FLS_WRITE_ID, E_NOT_OK);\r
+ FLS_VALIDATE_STATUS_BUSY_W_RV(Fls_SST25xx_Global.status, FLS_WRITE_ID, E_NOT_OK);\r
+ FLS_VALIDATE_PARAM_ADDRESS_PAGE_W_RV(TargetAddress, FLS_WRITE_ID, E_NOT_OK);\r
+ FLS_VALIDATE_PARAM_LENGTH_PAGE_W_RV(TargetAddress, Length, FLS_WRITE_ID, E_NOT_OK);\r
+ FLS_VALIDATE_PARAM_DATA_W_RV(SourceAddressPtr, FLS_WRITE_ID, E_NOT_OK)\r
+\r
+ Fls_SST25xx_Global.jobResultType = MEMIF_JOB_PENDING;\r
+ Fls_SST25xx_Global.status = MEMIF_BUSY;\r
+ Fls_SST25xx_Global.jobType = FLS_SST25XX_WRITE;\r
+\r
+ if( Fls_SST25xx_Global.mode == MEMIF_MODE_FAST ) {\r
+ job->chunkSize = Fls_SST25xx_Global.config->FlsMaxWriteFastMode;\r
+ } else {\r
+ job->chunkSize = Fls_SST25xx_Global.config->FlsMaxWriteNormalMode;\r
+ }\r
+\r
+ job->flsAddr = TargetAddress;\r
+ job->targetAddr = (uint8 *)SourceAddressPtr;\r
+ job->left = Length;\r
+\r
+ JOB_SET_STATE(JOB_MAIN,FLS_SST25XX_WRITE);\r
+\r
+ return E_OK;\r
+}\r
+\r
+\r
+Std_ReturnType Fls_SST25xx_Compare( Fls_AddressType SourceAddress, uint8 *TargetAddressPtr, Fls_LengthType Length )\r
+{\r
+ Fls_SST25xx_JobInfoType *job = &Fls_SST25xx_Global.job;\r
+\r
+ FLS_VALIDATE_STATUS_UNINIT_W_RV(Fls_SST25xx_Global.status, FLS_COMPARE_ID, E_NOT_OK);\r
+ FLS_VALIDATE_STATUS_BUSY_W_RV(Fls_SST25xx_Global.status, FLS_COMPARE_ID, E_NOT_OK);\r
+ FLS_VALIDATE_PARAM_ADDRESS_PAGE_W_RV(SourceAddress, FLS_COMPARE_ID, E_NOT_OK);\r
+ FLS_VALIDATE_PARAM_LENGTH_PAGE_W_RV(SourceAddress, Length, FLS_COMPARE_ID, E_NOT_OK);\r
+ FLS_VALIDATE_PARAM_DATA_W_RV((void*)SourceAddress,FLS_COMPARE_ID, E_NOT_OK)\r
+\r
+ Fls_SST25xx_Global.status = MEMIF_BUSY;\r
+ Fls_SST25xx_Global.jobResultType = MEMIF_JOB_PENDING;\r
+ Fls_SST25xx_Global.jobType = FLS_SST25XX_COMPARE;\r
+\r
+ /* This is a compare job but the compare jobs really issues read in portions\r
+ * big enough to fit it's static buffers
+ */\r
+ if( Fls_SST25xx_Global.mode == MEMIF_MODE_FAST ) {\r
+ job->chunkSize = Fls_SST25xx_Global.config->FlsMaxReadFastMode;\r
+ } else {\r
+ job->chunkSize = Fls_SST25xx_Global.config->FlsMaxReadNormalMode;\r
+ }\r
+\r
+ job->flsAddr = SourceAddress;\r
+ job->targetAddr = TargetAddressPtr;\r
+ job->left = Length;\r
+\r
+ JOB_SET_STATE(JOB_MAIN,FLS_SST25XX_COMPARE);\r
+\r
+ return E_OK;\r
+}\r
+\r
+\r
+#if ( FLS_SST25XX_CANCEL_API == STD_ON )\r
+\r
+/* API NOT SUPPORTED */\r
+\r
+void Fls_SST25xx_Cancel( void ){\r
+ if (Fls_SST25xx_Global.config->FlsJobEndNotification!=NULL) Fls_SST25xx_Global.config->FlsJobEndNotification();\r
+\r
+ if (MEMIF_JOB_PENDING==Fls_SST25xx_Global.jobResultType) {\r
+ Fls_SST25xx_Global.jobResultType=MEMIF_JOB_CANCELLED;\r
+ }\r
+\r
+ Fls_SST25xx_Global.status = MEMIF_IDLE;\r
+}\r
+#endif\r
+\r
+\r
+#if ( FLS_GET_STATUS_API == STD_ON )\r
+MemIf_StatusType Fls_SST25xx_GetStatus( void ){\r
+ return Fls_SST25xx_Global.status;\r
+}\r
+#endif\r
+\r
+MemIf_JobResultType Fls_SST25xx_GetJobResult( void ){\r
+ return Fls_SST25xx_Global.jobResultType;\r
+}\r
+\r
+\r
+/**\r
+ * Function that process read/write/erase requests to the SPI\r
+ *\r
+ * @param job The present job
+ */\r
+\r
+static Spi_SeqResultType Fls_SST25xx_ProcessJob( Fls_SST25xx_JobInfoType *job ) {\r
+ Spi_SeqResultType rv;\r
+ _Bool done = 0;\r
+\r
+ /* Check if previous sequence is OK */\r
+ rv = Spi_GetSequenceResult(job->currSeq);\r
+ if( rv != SPI_SEQ_OK ) {\r
+ return rv;\r
+ }\r
+\r
+ rv = SPI_SEQ_PENDING;\r
+\r
+ do {\r
+ switch(job->state ) {\r
+ case JOB_READ_STATUS:\r
+ DEBUG(DEBUG_LOW,"%s: READ_STATUS\n",MODULE_NAME);\r
+ /* Check status from erase cmd, read status from flash */\r
+ Spi_SetupEB( SPI_CH_FLASH_DATA, NULL, &Fls_SST25xx_Global.ebReadStatus, 1);\r
+ Fls_SST25xx_Global.ebCmd = FLASH_RDSR;\r
+ if( SPI_TRANSMIT_FUNC(SPI_SEQ_FLASH_CMD2,job ) != E_OK ) {\r
+ assert(0);\r
+ }\r
+ SET_STATE(1,JOB_READ_STATUS_RESULT);\r
+ break;\r
+\r
+ case JOB_READ_STATUS_RESULT:\r
+ DEBUG(DEBUG_LOW,"%s: READ_STATUS_RESULT\n",MODULE_NAME);\r
+ if( Fls_SST25xx_Global.ebReadStatus&1 ) {\r
+ SET_STATE(0,JOB_READ_STATUS);\r
+ } else {\r
+ SET_STATE(0,JOB_MAIN);\r
+ }\r
+ break;\r
+\r
+ case JOB_MAIN:\r
+ if( job->left != 0 ) {\r
+ if( job->left <= job->chunkSize ) {\r
+ job->chunkSize = job->left;\r
+ }\r
+\r
+ Spi_ConvertToSpiAddr(Fls_SST25xx_Global.ebFlsAddr,job->flsAddr);\r
+\r
+ switch(job->mainState) {\r
+ case FLS_SST25XX_ERASE:\r
+ DEBUG(DEBUG_LOW,"%s: Erase 4K s:%04x\n",MODULE_NAME,job->flsAddr);\r
+ Fls_SST25xx_Global.ebCmd = FLASH_ERASE_4K;\r
+ SPI_TRANSMIT_FUNC(SPI_SEQ_FLASH_WRITE,job );\r
+ break;\r
+\r
+ case FLS_SST25XX_READ:\r
+ case FLS_SST25XX_COMPARE:\r
+ DEBUG(DEBUG_LOW,"%s: READ s:%04x d:%04x l:%04x\n",MODULE_NAME,job->flsAddr, job->targetAddr, job->left);\r
+ Fls_SST25xx_Global.ebCmd = FLASH_READ_25;\r
+ Spi_SetupEB( SPI_CH_FLASH_DATA, NULL ,job->targetAddr,job->chunkSize);\r
+ SPI_TRANSMIT_FUNC(SPI_SEQ_FLASH_READ,job );\r
+ break;\r
+\r
+ case FLS_SST25XX_WRITE:\r
+ DEBUG(DEBUG_LOW,"%s: WRITE d:%04x s:%04x first data:%02x\n",MODULE_NAME,job->flsAddr,job->targetAddr,*job->targetAddr);\r
+ Fls_SST25xx_Global.ebCmd = FLASH_BYTE_WRITE;\r
+ Spi_ConvertToSpiAddr(Fls_SST25xx_Global.ebFlsAddr,job->flsAddr);\r
+ Spi_SetupEB( SPI_CH_FLASH_DATA, job->targetAddr, NULL, job->chunkSize);\r
+ SPI_TRANSMIT_FUNC(SPI_SEQ_FLASH_WRITE,job );\r
+ break;\r
+\r
+ default:\r
+ assert(0);\r
+ break;\r
+ }\r
+\r
+ job->flsAddr += job->chunkSize;\r
+ job->targetAddr += job->chunkSize;\r
+ job->left -= job->chunkSize;\r
+ SET_STATE(1,JOB_READ_STATUS);\r
+\r
+ } else {\r
+ /* We are done :) */\r
+ SET_STATE(1,JOB_MAIN);\r
+ job->mainState = FLS_SST25XX_NONE;\r
+ rv = SPI_SEQ_OK;\r
+ }\r
+ break;\r
+\r
+ default:\r
+ assert(0);\r
+ break;\r
+\r
+ }\r
+ } while(!done);\r
+ return rv;\r
+}\r
+\r
+\r
+#define CMP_BUFF_SIZE SPI_EB_MAX_LENGTH\r
+\r
+void Fls_SST25xx_MainFunction( void )\r
+{\r
+ Spi_SeqResultType jobResult;\r
+\r
+ if( Fls_SST25xx_Global.jobResultType == MEMIF_JOB_PENDING ) {\r
+ switch (Fls_SST25xx_Global.jobType) {\r
+ case FLS_SST25XX_COMPARE: {\r
+ static Fls_SST25xx_JobInfoType readJob;\r
+ static uint8 Fls_SST25xx_CompareBuffer[SPI_EB_MAX_LENGTH];\r
+ Fls_SST25xx_JobInfoType *gJob = &Fls_SST25xx_Global.job;\r
+ static _Bool firstTime = 1;\r
+ static uint32 readSize;\r
+\r
+ /* Compare jobs must use a local buffer to hold one portion\r
+ * of the job. Since Fls_SST25xx_ProcessJob() also manipulates the\r
+ * job structure we need to create a new local job each time.\r
+ * The global job updates is updated for each process job.
+ */\r
+\r
+ if (firstTime == 1) {\r
+ readJob = *gJob;\r
+\r
+ if ( gJob->left <= CMP_BUFF_SIZE ) {\r
+ readSize = gJob->left;\r
+ } else {\r
+ readSize = CMP_BUFF_SIZE;\r
+ }\r
+ readJob.left = readSize;\r
+ readJob.targetAddr = Fls_SST25xx_CompareBuffer;\r
+ firstTime = 0;\r
+ }\r
+\r
+ jobResult = Fls_SST25xx_ProcessJob(&readJob);\r
+\r
+ if( jobResult == SPI_SEQ_PENDING ) {\r
+ /* Do nothing */\r
+ } else if( jobResult == SPI_SEQ_OK ) {\r
+\r
+ if( memcmp(Fls_SST25xx_CompareBuffer,gJob->targetAddr, readSize) != 0 ) {\r
+ DET_REPORTERROR(MODULE_ID_FLS,0, 0x6, FLS_E_COMPARE_FAILED );\r
+ FEE_JOB_ERROR_NOTIFICATION();\r
+ return;\r
+ }\r
+ // Update the global comare job\r
+ gJob->targetAddr += readSize;\r
+ gJob->flsAddr += readSize;\r
+ gJob->left -= readSize;\r
+\r
+ // Check if we are done\r
+ if( gJob->left == 0 ) {\r
+ Fls_SST25xx_Global.jobResultType = MEMIF_JOB_OK;\r
+ Fls_SST25xx_Global.jobType = FLS_SST25XX_NONE;\r
+ Fls_SST25xx_Global.status = MEMIF_IDLE;\r
+ FEE_JOB_END_NOTIFICATION();\r
+ firstTime = 1;\r
+ return;\r
+ }\r
+ // Calculate new readSize\r
+ if ( gJob->left <= CMP_BUFF_SIZE ) {\r
+ readSize = gJob->left;\r
+ } else {\r
+ readSize = CMP_BUFF_SIZE;\r
+ }\r
+\r
+ // Update the readjob for next session\r
+ readJob = *gJob;\r
+ readJob.left = readSize;\r
+ readJob.targetAddr = Fls_SST25xx_CompareBuffer;\r
+ } else {\r
+ // all other cases are bad\r
+ firstTime = 1;\r
+ Fls_SST25xx_Global.jobResultType = MEMIF_JOB_FAILED;\r
+ Fls_SST25xx_Global.jobType = FLS_SST25XX_NONE;\r
+ Fls_SST25xx_Global.status = MEMIF_IDLE;\r
+\r
+ DET_REPORTERROR(MODULE_ID_FLS,0, 0x6, FLS_E_COMPARE_FAILED );\r
+ FEE_JOB_ERROR_NOTIFICATION();\r
+ }\r
+ }\r
+ break;\r
+\r
+ case FLS_SST25XX_ERASE:\r
+ case FLS_SST25XX_READ:\r
+ case FLS_SST25XX_WRITE:\r
+\r
+ jobResult = Fls_SST25xx_ProcessJob(&Fls_SST25xx_Global.job);\r
+\r
+ if( jobResult == SPI_SEQ_OK ) {\r
+\r
+ Fls_SST25xx_Global.jobResultType = MEMIF_JOB_OK;\r
+ Fls_SST25xx_Global.jobType = FLS_SST25XX_NONE;\r
+ Fls_SST25xx_Global.status = MEMIF_IDLE;\r
+ FEE_JOB_END_NOTIFICATION();\r
+ } else if( jobResult == SPI_SEQ_PENDING ) {\r
+ /* Busy, Do nothing */\r
+ } else {\r
+ // Error\r
+ Fls_SST25xx_Global.jobResultType = MEMIF_JOB_FAILED;\r
+\r
+ switch(Fls_SST25xx_Global.jobType) {\r
+ case FLS_SST25XX_ERASE:\r
+ DET_REPORTERROR(MODULE_ID_FLS,0, 0x6, FLS_E_ERASED_FAILED );\r
+ break;\r
+ case FLS_SST25XX_READ:\r
+ DET_REPORTERROR(MODULE_ID_FLS,0, 0x6, FLS_E_READ_FAILED );\r
+ break;\r
+ case FLS_SST25XX_WRITE:\r
+ DET_REPORTERROR(MODULE_ID_FLS,0, 0x6, FLS_E_WRITE_FAILED );\r
+ break;\r
+ default:\r
+ assert(0);\r
+ }\r
+\r
+ FEE_JOB_ERROR_NOTIFICATION();\r
+ }\r
+ break;\r
+ case FLS_SST25XX_NONE:\r
+ assert(0);\r
+ break;\r
+ }\r
+ }\r
+}\r
+\r
+\r
+#if ( FLS_SST25XX_VERSION_INFO_API == STD_ON )\r
+void Fls_SST25XX_GetVersionInfo( Std_VersionInfoType *VersioninfoPtr )\r
+{\r
+ memcpy(VersioninfoPtr, &Fls_SST25XX_VersionInfo, sizeof(Std_VersionInfoType));\r
+}\r
+\r
+#endif\r
+\r
--- /dev/null
+\r
+Urgent:\r
+Problems with paths and stuff:\r
+ - New project\r
+ - File->New->C Project->Makefile Project->Empty project\r
+ - Do NOT select any toolchain.\r
+ - SELECT the project location where the project is and name it.\r
+- Project->Properties\r
+ - Add to environment\r
+ CROSS_COMPILE:\r
+ /cygdrive/c/devtools/gcc/4.1.2/powerpc-eabispe/bin/powerpc-eabispe-\r
+ PATH\r
+ c:\cygwin\bin\r
+ BDIR\r
+ system/kernel\r
+\r
+MAC specific:\r
+ CROSS_COMPILE=/opt/powerpc-eabi/bin/powerpc-eabi-\r
+\r
+\r
+\r
+Known problems:\r
+- Problems clicking on cygwin paths. Hmm can change rules to something like: $(subst /cygdrive/c/,c:/,$<)\r
+- I thought this worked before....\r
+\r
+\r
+Next thing todo\r
+ - resource\r
+ - trusted functions\r
+ COMPLETE IT!!!!\r
+ ( The os is trusted and have their own indexes.. "OSServiceID_...." )\r
+\r
+ - ISR 2 !!!\r
+ - trusted functions\r
+ COMPLETE IT!!!!\r
+ - protection hook\r
+ - Stack check( for LC context )\r
+ - Seperate the ROM setup for pcb etc. in Oil_Config.c\r
+ ( must have rom_pcb_t ?? )\r
+ ( Remove pcb.h from Oil_config.c/.h )\r
+ - Lots and lots of critical sections out there. PROTECT THEM!!!\r
+ - DeclareResource() declares ok, DeclareTask() does not.. remove lists??\r
+\r
+ Conformance classes:\r
+ - For OSEK, ECC2 ( See chap. 3.2 in OSEK spec )\r
+ - For Autosar( Scalability class, chap. 7.8 Autosar SWS OS )\r
+ Class 3-4 would be best....\r
+\r
+ Maybe:\r
+ - Change type from xxx_t to xxxType as Autosar ???\r
+ ( remove own types.. )\r
+\r
+ DONE!\r
+ - TRAP_PROGRAM() defines in cpu.h ongoing...\r
+ - dbg printf.. so that we can use the T32 'term' window...\r
+ - Implement the trap interface, see k_arch_..IVOR6 for more info.\r
+ - Hooks\r
+ - Stack check for SC context\r
+ - basic tasks...ActivateTask, TerminateTask, ChainTask, Schedule\r
+\r
+What it can do:\r
+ - SetEvent, WaitEvent, ClearEvent seems to work\r
+ - the decrementer interrupt also seems to work ok.\r
+\r
+Repository:\r
+ //balder/svn_tree/autosar\r
+\r
+Preparations:\r
+ * You must have the path to cygwin stuff in path\r
+ * You must install GCC at C:\devtools\gcc, version 4.1.2 is assumed\r
+ ( you can of course change this in the makefiles )\r
+\r
+Building:\r
+ From cygwin prompt\r
+ Test system\r
+ >make BDIR=kernel,kernel/test ARCH=ppc55xx all\r
+\r
+ Example, simple\r
+ >make BDIR=kernel,examples/simple ARCH=ppc55xx all\r
+\r
+ Installing\r
+ >make BDIR=kernel,examples/simple ARCH=ppc55xx all install\r
+\r
+\r
+Software used:\r
+ T32\r
+ T32 instruction simulator, www.lauterbach.com -> demo download(right menu) ->\r
+ press "download" on second row of text -> save "Simulator for PowerPC"\r
+\r
+ or find the one I used on //breidablick/Our Software/T32_simppc_20070322.zip\r
+\r
+ Eclipse\r
+ Platform 3.2.0\r
+ CDT 4.0.0 M6\r
+\r
+Debugging:\r
+ 1. when debugger started\r
+ 2. >cd <where you have checked out the project>\r
+ 3. >cd scripts\r
+ 4. >do start\r
+[5.] >do lay // for some windows.. that are good.\r
+\r
+File structure:\r
+-------------------------------------------------------\r
+kernel/ext_config.h\r
+ Declaration of functions and variables in from config( Oil_Config.c )\r
+\r
+include/Common_Cfg.h\r
+ Shared types between config and os.\r
+ ( generated later ?? )\r
+\r
+Oil_Config.c\r
+ Generated by OIL tool. Compiled by user\r
+\r
+Oil_Config.h\r
+ Generated by OIL tool. Included by user.\r
+\r
+\r
+Service\r
+-------------------------------------------------------\r
+ActivateTask 80\r
+TerminateTask 80\r
+ChainTask 80\r
+Schedule 80\r
+GetTaskID 100\r
+GetTaskState 80\r
+DisableAllInterrupts 100\r
+EnableAllInterrupts 100\r
+SuspendAllInterrupts 20\r
+ResumeAllInterrupts 20\r
+SuspendOSInterrupts 20\r
+ResumeOSInterrupts 20\r
+GetResource 100\r
+ReleaseResource 50\r
+SetEvent 100\r
+ClearEvent 100\r
+GetEvent 100\r
+WaitEvent 100\r
+GetAlarmBase 80\r
+GetAlarm 80\r
+SetRelAlarm 100\r
+SetAbsAlarm 0\r
+CancelAlarm 100\r
+GetActiveApplicationMode 0\r
+StartOS 50\r
+ShutdownOS 50\r
+GetApplicationID 0\r
+GetISRID 0\r
+CallTrustedFunction 50\r
+CheckISRMemoryAccess 0\r
+CheckTaskMemoryAccess 0\r
+CheckObjectAccess 0\r
+CheckObjectOwnership 0\r
+StartScheduleTableRel 50\r
+StartScheduleTableAbs 0\r
+StopScheduleTable 0\r
+NextScheduleTable 0\r
+SyncScheduleTable 0\r
+GetScheduleTableStatus 0\r
+SetScheduleTableAsync 0\r
+IncrementCounter 100\r
+TerminateApplication 0\r
+DisableInterruptSource 0\r
+EnableInterruptSource 0\r
+\r
+\r
+\r
+Kod:\r
+------------------------------------------------\r
+Adding a new architecture and board:\r
+1. Add the configuration for the board in the top makefile. See the XXXX_config rules\r
+2. Add the new board directory under /boards\r
+3. Create the config.h file\r
+4. If it's a new architecture create the directory under /arch.\r
+ If it's an variant to an existing one. #ifdef'ing the code should be enough\r
+\r
+\r
+See if it works:\r
+1. > make XXX_config\r
+2. Check that a valid "boards/<board_dir>/config.mk" was created\r
+\r
+\r
+Vilken core:\r
+CFG_E200Z?\r
+\r
+Vilken CPU:\r
+CFG_MPC5567\r
+\r
+Vilken board:\r
+CFG_BRD_MPC5567??\r
+\r
+\r
+* Om man ska anv\8anda SPE'n s\8c m\8cste man l\8agga till CFG_MPC5567 till asm_book_e.h\r
+ (detta f\9aruts\8atter att man ocks\8c anv\8ander spe varianten av kompilatorn (powerpc-eabispe- ist\8allet f\9ar powerpc-eabi-))\r
+* Har s\8akert en MMU s\8c ni m\8cste s\8atta upp den med.\r
+ L\8agg denna under /arch/ppc/mm/blaj.c d\8c den s\8akert kommer att g\8c att anv\8anda till andra\r
+ powerpc arch's. Header filerna l\8agger ni under /include/ppc\r
+\r
+CM:\r
+------------------------------------------------\r
+* Skapa en branch under aos-crew repot. Typ: mpc5567\r
+ (jag fyller aos-crew repot under kv\8allen)\r
+* N\8ar den \8ar klar g\9ar ni en merge mot trunk.\r
+* Jag lyfter den sedan till aos repot.\r
+\r
+\r
+\r
+\r
+boards\r
+|--- mpc5516it\r
+| |--- config\r
+| | |--- Gpt_Cfg.c/h <-- default config\r
+| | |--- Dio_Cfg.c/.h\r
+| | |--- mcu_aconfig.h\r
+|\r
+|--- examples\r
+| |--- simple\r
+| | |--- config\r
+| | | |--- Gpt_Cfg.c/h <-- if exist, overrides default config\r
+| | | |--- board_aconfig.h\r
+\r
+\r
+So, in this case it would take the default config for Dio and the example config for Gpt.\r
+\r
+Component more likely to find under boards:\r
+- Mcu\r
+- Can\r
+...\r
+\r
+More likely under examples:\r
+- Gpt\r
+- Com\r
+...\r
+\r
+Weak config targets: Mcu_Cfg.o\r
+Strong config targets: Gpt_Cfg.o Com_Cfg.o\r
+\r
+\r
+make BOARDDIR=boards/mpc5516it all\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+/* This file contains all runnable and instansiation */\r
+\r
+//-------------------------------------------------------------------\r
+// \r
+// Runnable entity\r
+//\r
+//<void|Std_ReturnType> Rte_<name>( [IN Rte_Instance <instance>], [role parameters])\r
+\r
+// Triggered by RTEEvent(always) \r
+void Rte_Runnable_10ms( Rte_Instance ) {\r
+ \r
+} \r
+\r
+\r
+//-------------------------------------------------------------------\r
+// Applicatio headers\r
+\r
+typedef struct {\r
+ uint8 value;\r
+} Rte_DE_uint8;\r
+\r
+typedef struct {\r
+ uint8 value;\r
+ Std_ReturnType status;\r
+} Rte_DES_uint8;\r
+\r
+// re - runnable entity\r
+Rte_DE_uint8* re1_doors_get_status; \r
+\r
+#define Rte_IRead_re1_doors_get_status(inst, data) ((inst)->doors_get_status\r
+\r
+//-------------------------------------------------------------------\r
+// Application code\r
+\r
+void Doors( void ) {\r
+ \r
+}\r
+\r
+// Call in runnable\r
+void Doors_periodic( void ) {\r
+ // read the door status from I/O HW\r
+ int door_status;\r
+ Rte_Read_io_\r
+ Rte_IRead_Runnable_10ms_io_ \r
+ \r
+}\r
+\r
+\r
--- /dev/null
+#/bin/bash
+
+function quit {
+ echo
+ echo "### BUILD FAILED"
+ echo
+ exit $1
+}
+
+
+oo="aa $CROSS_COMPILE aa";
+echo "oo = $oo";
+if [ "aa $CROSS_COMPILE aa" == "aa aa" ]; then
+ os=`uname`
+ echo $os
+ if [ "$os"=="Darwin" ]; then
+ export CROSS_COMPILE=/opt/powerpc-eabi/bin/powerpc-eabi-
+ else
+ export CROSS_COMPILE=/cygdrive/c/devtools/gcc/4.1.2/powerpc-eabispe/bin/powerpc-eabispe-
+ fi
+fi;
+
+export BDIR=system/kernel/testsystem
+make BOARDDIR=mpc5554sim clean all
+if [ $? -ne 0 ]; then quit 1
+fi
+
+make BOARDDIR=mpc551xsim clean all
+if [ $? -ne 0 ]; then quit 1
+fi
+
+make BOARDDIR=mpc5516it clean all
+if [ $? -ne 0 ]; then quit 1
+fi
+
+export BDIR=system/kernel/testsystem,examples/blinker_node
+make BOARDDIR=mpc5567qrtech clean all
+if [ $? -ne 0 ]; then quit 1
+fi
+
+exit 0
+
+
+
+
+
+
+
+
+
--- /dev/null
+#/bin/bash
+
+function quit {
+ echo
+ echo "### BUILD FAILED"
+ echo
+ exit $1
+}
+
+
+oo="aa $CROSS_COMPILE aa";
+echo "oo = $oo";
+if [ "aa $CROSS_COMPILE aa" == "aa aa" ]; then
+ os=`uname`
+ echo $os
+ if [ "$os" == "Darwin" ]; then
+ export CROSS_COMPILE=/opt/arm-elf/bin/arm-elf-
+ else
+ export CROSS_COMPILE=/cygdrive/c/devtools/CodeSourcery/Lite/bin/arm-none-eabi-
+ fi
+fi;
+
+export BDIR=system/kernel/testsystem
+make BOARDDIR=et_stm32_stamp clean
+make BOARDDIR=et_stm32_stamp all
+if [ $? -ne 0 ]; then quit 1
+fi
--- /dev/null
+\r
+\r
+HOST := $(shell uname)\r
+export prefix\r
+\r
+# If we are using codesourcery and cygwin..\r
+export CYGPATH=c:/cygwin/bin/cygpath\r
+\r
+# ---------------------------------------------------------------------------\r
+# Compiler\r
+# CCFLAGS - compile flags\r
+\r
+CC = $(CROSS_COMPILE)gcc\r
+cflags-y += -O0\r
+#cflags-y += -O0\r
+#cflags-y += -O3\r
+\r
+ifneq ($(filter -O2 -O3 -O1,$(cflags-y)),) \r
+ cflags-y += -fno-schedule-insns -fno-schedule-insns2\r
+endif\r
+\r
+# Remove sections if needed.. may be problems with other compilers here.\r
+#cflags-$(CFG_MPC55XX) += -ffunction-sections\r
+\r
+\r
+#cflags-y += -c \r
+#cflags-y += -fno-common\r
+cflags-y += -std=gnu99\r
+\r
+# Generate dependencies\r
+cflags-y += -MMD\r
+\r
+# Warnings\r
+cflags-y += -Wall\r
+cflags-y += -Winline # warn if inline failed\r
+\r
+# Conformance\r
+cflags-y += -fno-strict-aliasing\r
+cflags-y += -fno-builtin\r
+\r
+# Get machine cflags\r
+#cflags-y += $(cflags-$(ARCH))\r
+\r
+CFLAGS = $(cflags-y) $(cflags-yy)\r
+\r
+CCOUT = -o $@ \r
+\r
+# ---------------------------------------------------------------------------\r
+# Preprocessor\r
+\r
+CPP = $(CC) -E\r
+\r
+# Note!\r
+# Libs related to GCC(libgcc.a, libgcov.a) is located under \r
+# lib/gcc/<machine>/<version>/<multilib>\r
+# Libs related to the library (libc.a,libm.a,etc) are under:\r
+# <machine>/lib/<multilib>\r
+gcc_lib_path := $(dir $(shell $(CC) $(CFLAGS) --print-libgcc-file-name $(conv_path)))\r
+lib_lib_path := $(dir $(shell $(CC) $(CFLAGS) --print-file-name\=libc.a $(conv_path)))\r
+libpath-y += -L$(lib_lib_path)\r
+libpath-y += -L$(gcc_lib_path)\r
+\r
+# ---------------------------------------------------------------------------\r
+# Linker\r
+#\r
+# LDFLAGS - linker flags\r
+# LDOUT - How to Generate linker output file\r
+# LDMAPFILE - How to generate mapfile \r
+# ldcmdfile-y - link cmd file\r
+# libpath-y - lib paths\r
+# libitem-y - the libs with path\r
+# lib-y - the libs, without path\r
+\r
+\r
+LD = $(CROSS_COMPILE)ld\r
+\r
+LDOUT = -o $@\r
+TE = elf\r
+LDMAPFILE = -M > $(subst .$(TE),.map, $@)\r
+\r
+libitem-y += $(libitem-yy)\r
+\r
+# ---------------------------------------------------------------------------\r
+# Assembler\r
+#\r
+# ASFLAGS - assembler flags\r
+# ASOUT - how to generate output file\r
+\r
+AS = $(CROSS_COMPILE)as\r
+\r
+ASFLAGS += --gdwarf2\r
+ASOUT = -o $@\r
+\r
+# ---------------------------------------------------------------------------\r
+# Dumper\r
+\r
+#DDUMP = $(Q)$(COMPILER_ROOT)/$(cross_machine-y)-objcopy\r
+#DDUMP_FLAGS = -O srec\r
+OBJCOPY = $(CROSS_COMPILE)objcopy\r
+\r
+# ---------------------------------------------------------------------------\r
+# Archiver\r
+#\r
+# AROUT - archiver flags\r
+\r
+AR = $(CROSS_COMPILE)ar\r
+AROUT = $@\r
+\r
+\r
+\r
+\r
--- /dev/null
+# Doxyfile 1.4.4\r
+\r
+# This file describes the settings to be used by the documentation system\r
+# doxygen (www.doxygen.org) for a project\r
+#\r
+# All text after a hash (#) is considered a comment and will be ignored\r
+# The format is:\r
+# TAG = value [value, ...]\r
+# For lists items can also be appended using:\r
+# TAG += value [value, ...]\r
+# Values that contain spaces should be placed between quotes (" ")\r
+\r
+#---------------------------------------------------------------------------\r
+# Project related configuration options\r
+#---------------------------------------------------------------------------\r
+\r
+# The PROJECT_NAME tag is a single word (or a sequence of words surrounded \r
+# by quotes) that should identify the project.\r
+\r
+PROJECT_NAME = "can"\r
+\r
+# The PROJECT_NUMBER tag can be used to enter a project or revision number. \r
+# This could be handy for archiving the generated documentation or \r
+# if some version control system is used.\r
+\r
+PROJECT_NUMBER = \r
+\r
+# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) \r
+# base path where the generated documentation will be put. \r
+# If a relative path is entered, it will be relative to the location \r
+# where doxygen was started. If left blank the current directory will be used.\r
+\r
+OUTPUT_DIRECTORY = doxygen_doc\r
+\r
+# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create \r
+# 4096 sub-directories (in 2 levels) under the output directory of each output \r
+# format and will distribute the generated files over these directories. \r
+# Enabling this option can be useful when feeding doxygen a huge amount of \r
+# source files, where putting all generated files in the same directory would \r
+# otherwise cause performance problems for the file system.\r
+\r
+CREATE_SUBDIRS = NO\r
+\r
+# The OUTPUT_LANGUAGE tag is used to specify the language in which all \r
+# documentation generated by doxygen is written. Doxygen will use this \r
+# information to generate all constant output in the proper language. \r
+# The default language is English, other supported languages are: \r
+# Brazilian, Catalan, Chinese, Chinese-Traditional, Croatian, Czech, Danish, \r
+# Dutch, Finnish, French, German, Greek, Hungarian, Italian, Japanese, \r
+# Japanese-en (Japanese with English messages), Korean, Korean-en, Norwegian, \r
+# Polish, Portuguese, Romanian, Russian, Serbian, Slovak, Slovene, Spanish, \r
+# Swedish, and Ukrainian.\r
+\r
+OUTPUT_LANGUAGE = English\r
+\r
+# This tag can be used to specify the encoding used in the generated output. \r
+# The encoding is not always determined by the language that is chosen, \r
+# but also whether or not the output is meant for Windows or non-Windows users. \r
+# In case there is a difference, setting the USE_WINDOWS_ENCODING tag to YES \r
+# forces the Windows encoding (this is the default for the Windows binary), \r
+# whereas setting the tag to NO uses a Unix-style encoding (the default for \r
+# all platforms other than Windows).\r
+\r
+USE_WINDOWS_ENCODING = YES\r
+\r
+# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will \r
+# include brief member descriptions after the members that are listed in \r
+# the file and class documentation (similar to JavaDoc). \r
+# Set to NO to disable this.\r
+\r
+BRIEF_MEMBER_DESC = YES\r
+\r
+# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend \r
+# the brief description of a member or function before the detailed description. \r
+# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the \r
+# brief descriptions will be completely suppressed.\r
+\r
+REPEAT_BRIEF = YES\r
+\r
+# This tag implements a quasi-intelligent brief description abbreviator \r
+# that is used to form the text in various listings. Each string \r
+# in this list, if found as the leading text of the brief description, will be \r
+# stripped from the text and the result after processing the whole list, is \r
+# used as the annotated text. Otherwise, the brief description is used as-is. \r
+# If left blank, the following values are used ("$name" is automatically \r
+# replaced with the name of the entity): "The $name class" "The $name widget" \r
+# "The $name file" "is" "provides" "specifies" "contains" \r
+# "represents" "a" "an" "the"\r
+\r
+ABBREVIATE_BRIEF = \r
+\r
+# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then \r
+# Doxygen will generate a detailed section even if there is only a brief \r
+# description.\r
+\r
+ALWAYS_DETAILED_SEC = NO\r
+\r
+# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all \r
+# inherited members of a class in the documentation of that class as if those \r
+# members were ordinary class members. Constructors, destructors and assignment \r
+# operators of the base classes will not be shown.\r
+\r
+INLINE_INHERITED_MEMB = NO\r
+\r
+# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full \r
+# path before files name in the file list and in the header files. If set \r
+# to NO the shortest path that makes the file name unique will be used.\r
+\r
+FULL_PATH_NAMES = YES\r
+\r
+# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag \r
+# can be used to strip a user-defined part of the path. Stripping is \r
+# only done if one of the specified strings matches the left-hand part of \r
+# the path. The tag can be used to show relative paths in the file list. \r
+# If left blank the directory from which doxygen is run is used as the \r
+# path to strip.\r
+\r
+STRIP_FROM_PATH = \r
+\r
+# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of \r
+# the path mentioned in the documentation of a class, which tells \r
+# the reader which header file to include in order to use a class. \r
+# If left blank only the name of the header file containing the class \r
+# definition is used. Otherwise one should specify the include paths that \r
+# are normally passed to the compiler using the -I flag.\r
+\r
+STRIP_FROM_INC_PATH = \r
+\r
+# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter \r
+# (but less readable) file names. This can be useful is your file systems \r
+# doesn't support long names like on DOS, Mac, or CD-ROM.\r
+\r
+SHORT_NAMES = NO\r
+\r
+# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen \r
+# will interpret the first line (until the first dot) of a JavaDoc-style \r
+# comment as the brief description. If set to NO, the JavaDoc \r
+# comments will behave just like the Qt-style comments (thus requiring an \r
+# explicit @brief command for a brief description.\r
+\r
+JAVADOC_AUTOBRIEF = NO\r
+\r
+# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen \r
+# treat a multi-line C++ special comment block (i.e. a block of //! or /// \r
+# comments) as a brief description. This used to be the default behaviour. \r
+# The new default is to treat a multi-line C++ comment block as a detailed \r
+# description. Set this tag to YES if you prefer the old behaviour instead.\r
+\r
+MULTILINE_CPP_IS_BRIEF = NO\r
+\r
+# If the DETAILS_AT_TOP tag is set to YES then Doxygen \r
+# will output the detailed description near the top, like JavaDoc.\r
+# If set to NO, the detailed description appears after the member \r
+# documentation.\r
+\r
+DETAILS_AT_TOP = NO\r
+\r
+# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented \r
+# member inherits the documentation from any documented member that it \r
+# re-implements.\r
+\r
+INHERIT_DOCS = YES\r
+\r
+# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC \r
+# tag is set to YES, then doxygen will reuse the documentation of the first \r
+# member in the group (if any) for the other members of the group. By default \r
+# all members of a group must be documented explicitly.\r
+\r
+DISTRIBUTE_GROUP_DOC = NO\r
+\r
+# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce \r
+# a new page for each member. If set to NO, the documentation of a member will \r
+# be part of the file/class/namespace that contains it.\r
+\r
+SEPARATE_MEMBER_PAGES = NO\r
+\r
+# The TAB_SIZE tag can be used to set the number of spaces in a tab. \r
+# Doxygen uses this value to replace tabs by spaces in code fragments.\r
+\r
+TAB_SIZE = 8\r
+\r
+# This tag can be used to specify a number of aliases that acts \r
+# as commands in the documentation. An alias has the form "name=value". \r
+# For example adding "sideeffect=\par Side Effects:\n" will allow you to \r
+# put the command \sideeffect (or @sideeffect) in the documentation, which \r
+# will result in a user-defined paragraph with heading "Side Effects:". \r
+# You can put \n's in the value part of an alias to insert newlines.\r
+\r
+ALIASES = \r
+\r
+# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C \r
+# sources only. Doxygen will then generate output that is more tailored for C. \r
+# For instance, some of the names that are used will be different. The list \r
+# of all members will be omitted, etc.\r
+\r
+OPTIMIZE_OUTPUT_FOR_C = NO\r
+\r
+# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java sources \r
+# only. Doxygen will then generate output that is more tailored for Java. \r
+# For instance, namespaces will be presented as packages, qualified scopes \r
+# will look different, etc.\r
+\r
+OPTIMIZE_OUTPUT_JAVA = NO\r
+\r
+# Set the SUBGROUPING tag to YES (the default) to allow class member groups of \r
+# the same type (for instance a group of public functions) to be put as a \r
+# subgroup of that type (e.g. under the Public Functions section). Set it to \r
+# NO to prevent subgrouping. Alternatively, this can be done per class using \r
+# the \nosubgrouping command.\r
+\r
+SUBGROUPING = YES\r
+\r
+#---------------------------------------------------------------------------\r
+# Build related configuration options\r
+#---------------------------------------------------------------------------\r
+\r
+# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in \r
+# documentation are documented, even if no documentation was available. \r
+# Private class members and static file members will be hidden unless \r
+# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES\r
+\r
+EXTRACT_ALL = YES\r
+\r
+# If the EXTRACT_PRIVATE tag is set to YES all private members of a class \r
+# will be included in the documentation.\r
+\r
+EXTRACT_PRIVATE = NO\r
+\r
+# If the EXTRACT_STATIC tag is set to YES all static members of a file \r
+# will be included in the documentation.\r
+\r
+EXTRACT_STATIC = NO\r
+\r
+# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) \r
+# defined locally in source files will be included in the documentation. \r
+# If set to NO only classes defined in header files are included.\r
+\r
+EXTRACT_LOCAL_CLASSES = YES\r
+\r
+# This flag is only useful for Objective-C code. When set to YES local \r
+# methods, which are defined in the implementation section but not in \r
+# the interface are included in the documentation. \r
+# If set to NO (the default) only methods in the interface are included.\r
+\r
+EXTRACT_LOCAL_METHODS = NO\r
+\r
+# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all \r
+# undocumented members of documented classes, files or namespaces. \r
+# If set to NO (the default) these members will be included in the \r
+# various overviews, but no documentation section is generated. \r
+# This option has no effect if EXTRACT_ALL is enabled.\r
+\r
+HIDE_UNDOC_MEMBERS = NO\r
+\r
+# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all \r
+# undocumented classes that are normally visible in the class hierarchy. \r
+# If set to NO (the default) these classes will be included in the various \r
+# overviews. This option has no effect if EXTRACT_ALL is enabled.\r
+\r
+HIDE_UNDOC_CLASSES = NO\r
+\r
+# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all \r
+# friend (class|struct|union) declarations. \r
+# If set to NO (the default) these declarations will be included in the \r
+# documentation.\r
+\r
+HIDE_FRIEND_COMPOUNDS = NO\r
+\r
+# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any \r
+# documentation blocks found inside the body of a function. \r
+# If set to NO (the default) these blocks will be appended to the \r
+# function's detailed documentation block.\r
+\r
+HIDE_IN_BODY_DOCS = NO\r
+\r
+# The INTERNAL_DOCS tag determines if documentation \r
+# that is typed after a \internal command is included. If the tag is set \r
+# to NO (the default) then the documentation will be excluded. \r
+# Set it to YES to include the internal documentation.\r
+\r
+INTERNAL_DOCS = NO\r
+\r
+# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate \r
+# file names in lower-case letters. If set to YES upper-case letters are also \r
+# allowed. This is useful if you have classes or files whose names only differ \r
+# in case and if your file system supports case sensitive file names. Windows \r
+# and Mac users are advised to set this option to NO.\r
+\r
+CASE_SENSE_NAMES = YES\r
+\r
+# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen \r
+# will show members with their full class and namespace scopes in the \r
+# documentation. If set to YES the scope will be hidden.\r
+\r
+HIDE_SCOPE_NAMES = NO\r
+\r
+# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen \r
+# will put a list of the files that are included by a file in the documentation \r
+# of that file.\r
+\r
+SHOW_INCLUDE_FILES = YES\r
+\r
+# If the INLINE_INFO tag is set to YES (the default) then a tag [inline] \r
+# is inserted in the documentation for inline members.\r
+\r
+INLINE_INFO = YES\r
+\r
+# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen \r
+# will sort the (detailed) documentation of file and class members \r
+# alphabetically by member name. If set to NO the members will appear in \r
+# declaration order.\r
+\r
+SORT_MEMBER_DOCS = YES\r
+\r
+# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the \r
+# brief documentation of file, namespace and class members alphabetically \r
+# by member name. If set to NO (the default) the members will appear in \r
+# declaration order.\r
+\r
+SORT_BRIEF_DOCS = NO\r
+\r
+# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be \r
+# sorted by fully-qualified names, including namespaces. If set to \r
+# NO (the default), the class list will be sorted only by class name, \r
+# not including the namespace part. \r
+# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES.\r
+# Note: This option applies only to the class list, not to the \r
+# alphabetical list.\r
+\r
+SORT_BY_SCOPE_NAME = NO\r
+\r
+# The GENERATE_TODOLIST tag can be used to enable (YES) or \r
+# disable (NO) the todo list. This list is created by putting \todo \r
+# commands in the documentation.\r
+\r
+GENERATE_TODOLIST = YES\r
+\r
+# The GENERATE_TESTLIST tag can be used to enable (YES) or \r
+# disable (NO) the test list. This list is created by putting \test \r
+# commands in the documentation.\r
+\r
+GENERATE_TESTLIST = YES\r
+\r
+# The GENERATE_BUGLIST tag can be used to enable (YES) or \r
+# disable (NO) the bug list. This list is created by putting \bug \r
+# commands in the documentation.\r
+\r
+GENERATE_BUGLIST = YES\r
+\r
+# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or \r
+# disable (NO) the deprecated list. This list is created by putting \r
+# \deprecated commands in the documentation.\r
+\r
+GENERATE_DEPRECATEDLIST= YES\r
+\r
+# The ENABLED_SECTIONS tag can be used to enable conditional \r
+# documentation sections, marked by \if sectionname ... \endif.\r
+\r
+ENABLED_SECTIONS = \r
+\r
+# The MAX_INITIALIZER_LINES tag determines the maximum number of lines \r
+# the initial value of a variable or define consists of for it to appear in \r
+# the documentation. If the initializer consists of more lines than specified \r
+# here it will be hidden. Use a value of 0 to hide initializers completely. \r
+# The appearance of the initializer of individual variables and defines in the \r
+# documentation can be controlled using \showinitializer or \hideinitializer \r
+# command in the documentation regardless of this setting.\r
+\r
+MAX_INITIALIZER_LINES = 30\r
+\r
+# Set the SHOW_USED_FILES tag to NO to disable the list of files generated \r
+# at the bottom of the documentation of classes and structs. If set to YES the \r
+# list will mention the files that were used to generate the documentation.\r
+\r
+SHOW_USED_FILES = YES\r
+\r
+# If the sources in your project are distributed over multiple directories \r
+# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy \r
+# in the documentation. The default is YES.\r
+\r
+SHOW_DIRECTORIES = YES\r
+\r
+# The FILE_VERSION_FILTER tag can be used to specify a program or script that \r
+# doxygen should invoke to get the current version for each file (typically from the \r
+# version control system). Doxygen will invoke the program by executing (via \r
+# popen()) the command <command> <input-file>, where <command> is the value of \r
+# the FILE_VERSION_FILTER tag, and <input-file> is the name of an input file \r
+# provided by doxygen. Whatever the progam writes to standard output \r
+# is used as the file version. See the manual for examples.\r
+\r
+FILE_VERSION_FILTER = \r
+\r
+#---------------------------------------------------------------------------\r
+# configuration options related to warning and progress messages\r
+#---------------------------------------------------------------------------\r
+\r
+# The QUIET tag can be used to turn on/off the messages that are generated \r
+# by doxygen. Possible values are YES and NO. If left blank NO is used.\r
+\r
+QUIET = NO\r
+\r
+# The WARNINGS tag can be used to turn on/off the warning messages that are \r
+# generated by doxygen. Possible values are YES and NO. If left blank \r
+# NO is used.\r
+\r
+WARNINGS = YES\r
+\r
+# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings \r
+# for undocumented members. If EXTRACT_ALL is set to YES then this flag will \r
+# automatically be disabled.\r
+\r
+WARN_IF_UNDOCUMENTED = YES\r
+\r
+# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for \r
+# potential errors in the documentation, such as not documenting some \r
+# parameters in a documented function, or documenting parameters that \r
+# don't exist or using markup commands wrongly.\r
+\r
+WARN_IF_DOC_ERROR = YES\r
+\r
+# This WARN_NO_PARAMDOC option can be abled to get warnings for \r
+# functions that are documented, but have no documentation for their parameters \r
+# or return value. If set to NO (the default) doxygen will only warn about \r
+# wrong or incomplete parameter documentation, but not about the absence of \r
+# documentation.\r
+\r
+WARN_NO_PARAMDOC = NO\r
+\r
+# The WARN_FORMAT tag determines the format of the warning messages that \r
+# doxygen can produce. The string should contain the $file, $line, and $text \r
+# tags, which will be replaced by the file and line number from which the \r
+# warning originated and the warning text. Optionally the format may contain \r
+# $version, which will be replaced by the version of the file (if it could \r
+# be obtained via FILE_VERSION_FILTER)\r
+\r
+WARN_FORMAT = "$file:$line: $text"\r
+\r
+# The WARN_LOGFILE tag can be used to specify a file to which warning \r
+# and error messages should be written. If left blank the output is written \r
+# to stderr.\r
+\r
+WARN_LOGFILE = \r
+\r
+#---------------------------------------------------------------------------\r
+# configuration options related to the input files\r
+#---------------------------------------------------------------------------\r
+\r
+# The INPUT tag can be used to specify the files and/or directories that contain \r
+# documented source files. You may enter file names like "myfile.cpp" or \r
+# directories like "/usr/src/myproject". Separate the files or directories \r
+# with spaces.\r
+\r
+INPUT = can\r
+\r
+# If the value of the INPUT tag contains directories, you can use the \r
+# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp \r
+# and *.h) to filter out the source-files in the directories. If left \r
+# blank the following patterns are tested: \r
+# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx \r
+# *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm\r
+\r
+FILE_PATTERNS = *.c *.h *.inc\r
+\r
+# The RECURSIVE tag can be used to turn specify whether or not subdirectories \r
+# should be searched for input files as well. Possible values are YES and NO. \r
+# If left blank NO is used.\r
+\r
+RECURSIVE = YES\r
+\r
+# The EXCLUDE tag can be used to specify files and/or directories that should \r
+# excluded from the INPUT source files. This way you can easily exclude a \r
+# subdirectory from a directory tree whose root is specified with the INPUT tag.\r
+\r
+EXCLUDE = \r
+\r
+# The EXCLUDE_SYMLINKS tag can be used select whether or not files or \r
+# directories that are symbolic links (a Unix filesystem feature) are excluded \r
+# from the input.\r
+\r
+EXCLUDE_SYMLINKS = NO\r
+\r
+# If the value of the INPUT tag contains directories, you can use the \r
+# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude \r
+# certain files from those directories. Note that the wildcards are matched \r
+# against the file with absolute path, so to exclude all test directories \r
+# for example use the pattern */test/*\r
+\r
+EXCLUDE_PATTERNS = \r
+\r
+# The EXAMPLE_PATH tag can be used to specify one or more files or \r
+# directories that contain example code fragments that are included (see \r
+# the \include command).\r
+\r
+EXAMPLE_PATH = \r
+\r
+# If the value of the EXAMPLE_PATH tag contains directories, you can use the \r
+# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp \r
+# and *.h) to filter out the source-files in the directories. If left \r
+# blank all files are included.\r
+\r
+EXAMPLE_PATTERNS = \r
+\r
+# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be \r
+# searched for input files to be used with the \include or \dontinclude \r
+# commands irrespective of the value of the RECURSIVE tag. \r
+# Possible values are YES and NO. If left blank NO is used.\r
+\r
+EXAMPLE_RECURSIVE = NO\r
+\r
+# The IMAGE_PATH tag can be used to specify one or more files or \r
+# directories that contain image that are included in the documentation (see \r
+# the \image command).\r
+\r
+IMAGE_PATH = \r
+\r
+# The INPUT_FILTER tag can be used to specify a program that doxygen should \r
+# invoke to filter for each input file. Doxygen will invoke the filter program \r
+# by executing (via popen()) the command <filter> <input-file>, where <filter> \r
+# is the value of the INPUT_FILTER tag, and <input-file> is the name of an \r
+# input file. Doxygen will then use the output that the filter program writes \r
+# to standard output. If FILTER_PATTERNS is specified, this tag will be \r
+# ignored.\r
+\r
+INPUT_FILTER = \r
+\r
+# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern \r
+# basis. Doxygen will compare the file name with each pattern and apply the \r
+# filter if there is a match. The filters are a list of the form: \r
+# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further \r
+# info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER \r
+# is applied to all files.\r
+\r
+FILTER_PATTERNS = \r
+\r
+# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using \r
+# INPUT_FILTER) will be used to filter the input files when producing source \r
+# files to browse (i.e. when SOURCE_BROWSER is set to YES).\r
+\r
+FILTER_SOURCE_FILES = NO\r
+\r
+#---------------------------------------------------------------------------\r
+# configuration options related to source browsing\r
+#---------------------------------------------------------------------------\r
+\r
+# If the SOURCE_BROWSER tag is set to YES then a list of source files will \r
+# be generated. Documented entities will be cross-referenced with these sources. \r
+# Note: To get rid of all source code in the generated output, make sure also \r
+# VERBATIM_HEADERS is set to NO.\r
+\r
+SOURCE_BROWSER = NO\r
+\r
+# Setting the INLINE_SOURCES tag to YES will include the body \r
+# of functions and classes directly in the documentation.\r
+\r
+INLINE_SOURCES = NO\r
+\r
+# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct \r
+# doxygen to hide any special comment blocks from generated source code \r
+# fragments. Normal C and C++ comments will always remain visible.\r
+\r
+STRIP_CODE_COMMENTS = YES\r
+\r
+# If the REFERENCED_BY_RELATION tag is set to YES (the default) \r
+# then for each documented function all documented \r
+# functions referencing it will be listed.\r
+\r
+REFERENCED_BY_RELATION = YES\r
+\r
+# If the REFERENCES_RELATION tag is set to YES (the default) \r
+# then for each documented function all documented entities \r
+# called/used by that function will be listed.\r
+\r
+REFERENCES_RELATION = YES\r
+\r
+# If the USE_HTAGS tag is set to YES then the references to source code \r
+# will point to the HTML generated by the htags(1) tool instead of doxygen \r
+# built-in source browser. The htags tool is part of GNU's global source \r
+# tagging system (see http://www.gnu.org/software/global/global.html). You \r
+# will need version 4.8.6 or higher.\r
+\r
+USE_HTAGS = NO\r
+\r
+# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen \r
+# will generate a verbatim copy of the header file for each class for \r
+# which an include is specified. Set to NO to disable this.\r
+\r
+VERBATIM_HEADERS = YES\r
+\r
+#---------------------------------------------------------------------------\r
+# configuration options related to the alphabetical class index\r
+#---------------------------------------------------------------------------\r
+\r
+# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index \r
+# of all compounds will be generated. Enable this if the project \r
+# contains a lot of classes, structs, unions or interfaces.\r
+\r
+ALPHABETICAL_INDEX = NO\r
+\r
+# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then \r
+# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns \r
+# in which this list will be split (can be a number in the range [1..20])\r
+\r
+COLS_IN_ALPHA_INDEX = 5\r
+\r
+# In case all classes in a project start with a common prefix, all \r
+# classes will be put under the same header in the alphabetical index. \r
+# The IGNORE_PREFIX tag can be used to specify one or more prefixes that \r
+# should be ignored while generating the index headers.\r
+\r
+IGNORE_PREFIX = \r
+\r
+#---------------------------------------------------------------------------\r
+# configuration options related to the HTML output\r
+#---------------------------------------------------------------------------\r
+\r
+# If the GENERATE_HTML tag is set to YES (the default) Doxygen will \r
+# generate HTML output.\r
+\r
+GENERATE_HTML = YES\r
+\r
+# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. \r
+# If a relative path is entered the value of OUTPUT_DIRECTORY will be \r
+# put in front of it. If left blank `html' will be used as the default path.\r
+\r
+HTML_OUTPUT = html\r
+\r
+# The HTML_FILE_EXTENSION tag can be used to specify the file extension for \r
+# each generated HTML page (for example: .htm,.php,.asp). If it is left blank \r
+# doxygen will generate files with .html extension.\r
+\r
+HTML_FILE_EXTENSION = .html\r
+\r
+# The HTML_HEADER tag can be used to specify a personal HTML header for \r
+# each generated HTML page. If it is left blank doxygen will generate a \r
+# standard header.\r
+\r
+HTML_HEADER = \r
+\r
+# The HTML_FOOTER tag can be used to specify a personal HTML footer for \r
+# each generated HTML page. If it is left blank doxygen will generate a \r
+# standard footer.\r
+\r
+HTML_FOOTER = \r
+\r
+# The HTML_STYLESHEET tag can be used to specify a user-defined cascading \r
+# style sheet that is used by each HTML page. It can be used to \r
+# fine-tune the look of the HTML output. If the tag is left blank doxygen \r
+# will generate a default style sheet. Note that doxygen will try to copy \r
+# the style sheet file to the HTML output directory, so don't put your own \r
+# stylesheet in the HTML output directory as well, or it will be erased!\r
+\r
+HTML_STYLESHEET = \r
+\r
+# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes, \r
+# files or namespaces will be aligned in HTML using tables. If set to \r
+# NO a bullet list will be used.\r
+\r
+HTML_ALIGN_MEMBERS = YES\r
+\r
+# If the GENERATE_HTMLHELP tag is set to YES, additional index files \r
+# will be generated that can be used as input for tools like the \r
+# Microsoft HTML help workshop to generate a compressed HTML help file (.chm) \r
+# of the generated HTML documentation.\r
+\r
+GENERATE_HTMLHELP = NO\r
+\r
+# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can \r
+# be used to specify the file name of the resulting .chm file. You \r
+# can add a path in front of the file if the result should not be \r
+# written to the html output directory.\r
+\r
+CHM_FILE = \r
+\r
+# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can \r
+# be used to specify the location (absolute path including file name) of \r
+# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run \r
+# the HTML help compiler on the generated index.hhp.\r
+\r
+HHC_LOCATION = \r
+\r
+# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag \r
+# controls if a separate .chi index file is generated (YES) or that \r
+# it should be included in the master .chm file (NO).\r
+\r
+GENERATE_CHI = NO\r
+\r
+# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag \r
+# controls whether a binary table of contents is generated (YES) or a \r
+# normal table of contents (NO) in the .chm file.\r
+\r
+BINARY_TOC = NO\r
+\r
+# The TOC_EXPAND flag can be set to YES to add extra items for group members \r
+# to the contents of the HTML help documentation and to the tree view.\r
+\r
+TOC_EXPAND = NO\r
+\r
+# The DISABLE_INDEX tag can be used to turn on/off the condensed index at \r
+# top of each HTML page. The value NO (the default) enables the index and \r
+# the value YES disables it.\r
+\r
+DISABLE_INDEX = NO\r
+\r
+# This tag can be used to set the number of enum values (range [1..20]) \r
+# that doxygen will group on one line in the generated HTML documentation.\r
+\r
+ENUM_VALUES_PER_LINE = 4\r
+\r
+# If the GENERATE_TREEVIEW tag is set to YES, a side panel will be\r
+# generated containing a tree-like index structure (just like the one that \r
+# is generated for HTML Help). For this to work a browser that supports \r
+# JavaScript, DHTML, CSS and frames is required (for instance Mozilla 1.0+, \r
+# Netscape 6.0+, Internet explorer 5.0+, or Konqueror). Windows users are \r
+# probably better off using the HTML help feature.\r
+\r
+GENERATE_TREEVIEW = NO\r
+\r
+# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be \r
+# used to set the initial width (in pixels) of the frame in which the tree \r
+# is shown.\r
+\r
+TREEVIEW_WIDTH = 250\r
+\r
+#---------------------------------------------------------------------------\r
+# configuration options related to the LaTeX output\r
+#---------------------------------------------------------------------------\r
+\r
+# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will \r
+# generate Latex output.\r
+\r
+GENERATE_LATEX = YES\r
+\r
+# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. \r
+# If a relative path is entered the value of OUTPUT_DIRECTORY will be \r
+# put in front of it. If left blank `latex' will be used as the default path.\r
+\r
+LATEX_OUTPUT = latex\r
+\r
+# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be \r
+# invoked. If left blank `latex' will be used as the default command name.\r
+\r
+LATEX_CMD_NAME = latex\r
+\r
+# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to \r
+# generate index for LaTeX. If left blank `makeindex' will be used as the \r
+# default command name.\r
+\r
+MAKEINDEX_CMD_NAME = makeindex\r
+\r
+# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact \r
+# LaTeX documents. This may be useful for small projects and may help to \r
+# save some trees in general.\r
+\r
+COMPACT_LATEX = NO\r
+\r
+# The PAPER_TYPE tag can be used to set the paper type that is used \r
+# by the printer. Possible values are: a4, a4wide, letter, legal and \r
+# executive. If left blank a4wide will be used.\r
+\r
+PAPER_TYPE = a4wide\r
+\r
+# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX \r
+# packages that should be included in the LaTeX output.\r
+\r
+EXTRA_PACKAGES = \r
+\r
+# The LATEX_HEADER tag can be used to specify a personal LaTeX header for \r
+# the generated latex document. The header should contain everything until \r
+# the first chapter. If it is left blank doxygen will generate a \r
+# standard header. Notice: only use this tag if you know what you are doing!\r
+\r
+LATEX_HEADER = \r
+\r
+# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated \r
+# is prepared for conversion to pdf (using ps2pdf). The pdf file will \r
+# contain links (just like the HTML output) instead of page references \r
+# This makes the output suitable for online browsing using a pdf viewer.\r
+\r
+PDF_HYPERLINKS = NO\r
+\r
+# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of \r
+# plain latex in the generated Makefile. Set this option to YES to get a \r
+# higher quality PDF documentation.\r
+\r
+USE_PDFLATEX = NO\r
+\r
+# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode. \r
+# command to the generated LaTeX files. This will instruct LaTeX to keep \r
+# running if errors occur, instead of asking the user for help. \r
+# This option is also used when generating formulas in HTML.\r
+\r
+LATEX_BATCHMODE = NO\r
+\r
+# If LATEX_HIDE_INDICES is set to YES then doxygen will not \r
+# include the index chapters (such as File Index, Compound Index, etc.) \r
+# in the output.\r
+\r
+LATEX_HIDE_INDICES = NO\r
+\r
+#---------------------------------------------------------------------------\r
+# configuration options related to the RTF output\r
+#---------------------------------------------------------------------------\r
+\r
+# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output \r
+# The RTF output is optimized for Word 97 and may not look very pretty with \r
+# other RTF readers or editors.\r
+\r
+GENERATE_RTF = NO\r
+\r
+# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. \r
+# If a relative path is entered the value of OUTPUT_DIRECTORY will be \r
+# put in front of it. If left blank `rtf' will be used as the default path.\r
+\r
+RTF_OUTPUT = rtf\r
+\r
+# If the COMPACT_RTF tag is set to YES Doxygen generates more compact \r
+# RTF documents. This may be useful for small projects and may help to \r
+# save some trees in general.\r
+\r
+COMPACT_RTF = NO\r
+\r
+# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated \r
+# will contain hyperlink fields. The RTF file will \r
+# contain links (just like the HTML output) instead of page references. \r
+# This makes the output suitable for online browsing using WORD or other \r
+# programs which support those fields. \r
+# Note: wordpad (write) and others do not support links.\r
+\r
+RTF_HYPERLINKS = NO\r
+\r
+# Load stylesheet definitions from file. Syntax is similar to doxygen's \r
+# config file, i.e. a series of assignments. You only have to provide \r
+# replacements, missing definitions are set to their default value.\r
+\r
+RTF_STYLESHEET_FILE = \r
+\r
+# Set optional variables used in the generation of an rtf document. \r
+# Syntax is similar to doxygen's config file.\r
+\r
+RTF_EXTENSIONS_FILE = \r
+\r
+#---------------------------------------------------------------------------\r
+# configuration options related to the man page output\r
+#---------------------------------------------------------------------------\r
+\r
+# If the GENERATE_MAN tag is set to YES (the default) Doxygen will \r
+# generate man pages\r
+\r
+GENERATE_MAN = NO\r
+\r
+# The MAN_OUTPUT tag is used to specify where the man pages will be put. \r
+# If a relative path is entered the value of OUTPUT_DIRECTORY will be \r
+# put in front of it. If left blank `man' will be used as the default path.\r
+\r
+MAN_OUTPUT = man\r
+\r
+# The MAN_EXTENSION tag determines the extension that is added to \r
+# the generated man pages (default is the subroutine's section .3)\r
+\r
+MAN_EXTENSION = .3\r
+\r
+# If the MAN_LINKS tag is set to YES and Doxygen generates man output, \r
+# then it will generate one additional man file for each entity \r
+# documented in the real man page(s). These additional files \r
+# only source the real man page, but without them the man command \r
+# would be unable to find the correct page. The default is NO.\r
+\r
+MAN_LINKS = NO\r
+\r
+#---------------------------------------------------------------------------\r
+# configuration options related to the XML output\r
+#---------------------------------------------------------------------------\r
+\r
+# If the GENERATE_XML tag is set to YES Doxygen will \r
+# generate an XML file that captures the structure of \r
+# the code including all documentation.\r
+\r
+GENERATE_XML = NO\r
+\r
+# The XML_OUTPUT tag is used to specify where the XML pages will be put. \r
+# If a relative path is entered the value of OUTPUT_DIRECTORY will be \r
+# put in front of it. If left blank `xml' will be used as the default path.\r
+\r
+XML_OUTPUT = xml\r
+\r
+# The XML_SCHEMA tag can be used to specify an XML schema, \r
+# which can be used by a validating XML parser to check the \r
+# syntax of the XML files.\r
+\r
+XML_SCHEMA = \r
+\r
+# The XML_DTD tag can be used to specify an XML DTD, \r
+# which can be used by a validating XML parser to check the \r
+# syntax of the XML files.\r
+\r
+XML_DTD = \r
+\r
+# If the XML_PROGRAMLISTING tag is set to YES Doxygen will \r
+# dump the program listings (including syntax highlighting \r
+# and cross-referencing information) to the XML output. Note that \r
+# enabling this will significantly increase the size of the XML output.\r
+\r
+XML_PROGRAMLISTING = YES\r
+\r
+#---------------------------------------------------------------------------\r
+# configuration options for the AutoGen Definitions output\r
+#---------------------------------------------------------------------------\r
+\r
+# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will \r
+# generate an AutoGen Definitions (see autogen.sf.net) file \r
+# that captures the structure of the code including all \r
+# documentation. Note that this feature is still experimental \r
+# and incomplete at the moment.\r
+\r
+GENERATE_AUTOGEN_DEF = NO\r
+\r
+#---------------------------------------------------------------------------\r
+# configuration options related to the Perl module output\r
+#---------------------------------------------------------------------------\r
+\r
+# If the GENERATE_PERLMOD tag is set to YES Doxygen will \r
+# generate a Perl module file that captures the structure of \r
+# the code including all documentation. Note that this \r
+# feature is still experimental and incomplete at the \r
+# moment.\r
+\r
+GENERATE_PERLMOD = NO\r
+\r
+# If the PERLMOD_LATEX tag is set to YES Doxygen will generate \r
+# the necessary Makefile rules, Perl scripts and LaTeX code to be able \r
+# to generate PDF and DVI output from the Perl module output.\r
+\r
+PERLMOD_LATEX = NO\r
+\r
+# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be \r
+# nicely formatted so it can be parsed by a human reader. This is useful \r
+# if you want to understand what is going on. On the other hand, if this \r
+# tag is set to NO the size of the Perl module output will be much smaller \r
+# and Perl will parse it just the same.\r
+\r
+PERLMOD_PRETTY = YES\r
+\r
+# The names of the make variables in the generated doxyrules.make file \r
+# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. \r
+# This is useful so different doxyrules.make files included by the same \r
+# Makefile don't overwrite each other's variables.\r
+\r
+PERLMOD_MAKEVAR_PREFIX = \r
+\r
+#---------------------------------------------------------------------------\r
+# Configuration options related to the preprocessor \r
+#---------------------------------------------------------------------------\r
+\r
+# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will \r
+# evaluate all C-preprocessor directives found in the sources and include \r
+# files.\r
+\r
+ENABLE_PREPROCESSING = YES\r
+\r
+# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro \r
+# names in the source code. If set to NO (the default) only conditional \r
+# compilation will be performed. Macro expansion can be done in a controlled \r
+# way by setting EXPAND_ONLY_PREDEF to YES.\r
+\r
+MACRO_EXPANSION = NO\r
+\r
+# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES \r
+# then the macro expansion is limited to the macros specified with the \r
+# PREDEFINED and EXPAND_AS_PREDEFINED tags.\r
+\r
+EXPAND_ONLY_PREDEF = NO\r
+\r
+# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files \r
+# in the INCLUDE_PATH (see below) will be search if a #include is found.\r
+\r
+SEARCH_INCLUDES = YES\r
+\r
+# The INCLUDE_PATH tag can be used to specify one or more directories that \r
+# contain include files that are not input files but should be processed by \r
+# the preprocessor.\r
+\r
+INCLUDE_PATH = \r
+\r
+# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard \r
+# patterns (like *.h and *.hpp) to filter out the header-files in the \r
+# directories. If left blank, the patterns specified with FILE_PATTERNS will \r
+# be used.\r
+\r
+INCLUDE_FILE_PATTERNS = \r
+\r
+# The PREDEFINED tag can be used to specify one or more macro names that \r
+# are defined before the preprocessor is started (similar to the -D option of \r
+# gcc). The argument of the tag is a list of macros of the form: name \r
+# or name=definition (no spaces). If the definition and the = are \r
+# omitted =1 is assumed. To prevent a macro definition from being \r
+# undefined via #undef or recursively expanded use the := operator \r
+# instead of the = operator.\r
+\r
+PREDEFINED = \r
+\r
+# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then \r
+# this tag can be used to specify a list of macro names that should be expanded. \r
+# The macro definition that is found in the sources will be used. \r
+# Use the PREDEFINED tag if you want to use a different macro definition.\r
+\r
+EXPAND_AS_DEFINED = \r
+\r
+# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then \r
+# doxygen's preprocessor will remove all function-like macros that are alone \r
+# on a line, have an all uppercase name, and do not end with a semicolon. Such \r
+# function macros are typically used for boiler-plate code, and will confuse \r
+# the parser if not removed.\r
+\r
+SKIP_FUNCTION_MACROS = YES\r
+\r
+#---------------------------------------------------------------------------\r
+# Configuration::additions related to external references \r
+#---------------------------------------------------------------------------\r
+\r
+# The TAGFILES option can be used to specify one or more tagfiles. \r
+# Optionally an initial location of the external documentation \r
+# can be added for each tagfile. The format of a tag file without \r
+# this location is as follows: \r
+# TAGFILES = file1 file2 ... \r
+# Adding location for the tag files is done as follows: \r
+# TAGFILES = file1=loc1 "file2 = loc2" ... \r
+# where "loc1" and "loc2" can be relative or absolute paths or \r
+# URLs. If a location is present for each tag, the installdox tool \r
+# does not have to be run to correct the links.\r
+# Note that each tag file must have a unique name\r
+# (where the name does NOT include the path)\r
+# If a tag file is not located in the directory in which doxygen \r
+# is run, you must also specify the path to the tagfile here.\r
+\r
+TAGFILES = \r
+\r
+# When a file name is specified after GENERATE_TAGFILE, doxygen will create \r
+# a tag file that is based on the input files it reads.\r
+\r
+GENERATE_TAGFILE = \r
+\r
+# If the ALLEXTERNALS tag is set to YES all external classes will be listed \r
+# in the class index. If set to NO only the inherited external classes \r
+# will be listed.\r
+\r
+ALLEXTERNALS = NO\r
+\r
+# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed \r
+# in the modules index. If set to NO, only the current project's groups will \r
+# be listed.\r
+\r
+EXTERNAL_GROUPS = YES\r
+\r
+# The PERL_PATH should be the absolute path and name of the perl script \r
+# interpreter (i.e. the result of `which perl').\r
+\r
+PERL_PATH = /usr/bin/perl\r
+\r
+#---------------------------------------------------------------------------\r
+# Configuration options related to the dot tool \r
+#---------------------------------------------------------------------------\r
+\r
+# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will \r
+# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base \r
+# or super classes. Setting the tag to NO turns the diagrams off. Note that \r
+# this option is superseded by the HAVE_DOT option below. This is only a \r
+# fallback. It is recommended to install and use dot, since it yields more \r
+# powerful graphs.\r
+\r
+CLASS_DIAGRAMS = YES\r
+\r
+# If set to YES, the inheritance and collaboration graphs will hide \r
+# inheritance and usage relations if the target is undocumented \r
+# or is not a class.\r
+\r
+HIDE_UNDOC_RELATIONS = YES\r
+\r
+# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is \r
+# available from the path. This tool is part of Graphviz, a graph visualization \r
+# toolkit from AT&T and Lucent Bell Labs. The other options in this section \r
+# have no effect if this option is set to NO (the default)\r
+\r
+HAVE_DOT = NO\r
+\r
+# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen \r
+# will generate a graph for each documented class showing the direct and \r
+# indirect inheritance relations. Setting this tag to YES will force the \r
+# the CLASS_DIAGRAMS tag to NO.\r
+\r
+CLASS_GRAPH = YES\r
+\r
+# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen \r
+# will generate a graph for each documented class showing the direct and \r
+# indirect implementation dependencies (inheritance, containment, and \r
+# class references variables) of the class with other documented classes.\r
+\r
+COLLABORATION_GRAPH = YES\r
+\r
+# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen \r
+# will generate a graph for groups, showing the direct groups dependencies\r
+\r
+GROUP_GRAPHS = YES\r
+\r
+# If the UML_LOOK tag is set to YES doxygen will generate inheritance and \r
+# collaboration diagrams in a style similar to the OMG's Unified Modeling \r
+# Language.\r
+\r
+UML_LOOK = NO\r
+\r
+# If set to YES, the inheritance and collaboration graphs will show the \r
+# relations between templates and their instances.\r
+\r
+TEMPLATE_RELATIONS = NO\r
+\r
+# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT \r
+# tags are set to YES then doxygen will generate a graph for each documented \r
+# file showing the direct and indirect include dependencies of the file with \r
+# other documented files.\r
+\r
+INCLUDE_GRAPH = YES\r
+\r
+# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and \r
+# HAVE_DOT tags are set to YES then doxygen will generate a graph for each \r
+# documented header file showing the documented files that directly or \r
+# indirectly include this file.\r
+\r
+INCLUDED_BY_GRAPH = YES\r
+\r
+# If the CALL_GRAPH and HAVE_DOT tags are set to YES then doxygen will \r
+# generate a call dependency graph for every global function or class method. \r
+# Note that enabling this option will significantly increase the time of a run. \r
+# So in most cases it will be better to enable call graphs for selected \r
+# functions only using the \callgraph command.\r
+\r
+CALL_GRAPH = NO\r
+\r
+# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen \r
+# will graphical hierarchy of all classes instead of a textual one.\r
+\r
+GRAPHICAL_HIERARCHY = YES\r
+\r
+# If the DIRECTORY_GRAPH, SHOW_DIRECTORIES and HAVE_DOT tags are set to YES \r
+# then doxygen will show the dependencies a directory has on other directories \r
+# in a graphical way. The dependency relations are determined by the #include\r
+# relations between the files in the directories.\r
+\r
+DIRECTORY_GRAPH = YES\r
+\r
+# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images \r
+# generated by dot. Possible values are png, jpg, or gif\r
+# If left blank png will be used.\r
+\r
+DOT_IMAGE_FORMAT = png\r
+\r
+# The tag DOT_PATH can be used to specify the path where the dot tool can be \r
+# found. If left blank, it is assumed the dot tool can be found in the path.\r
+\r
+DOT_PATH = \r
+\r
+# The DOTFILE_DIRS tag can be used to specify one or more directories that \r
+# contain dot files that are included in the documentation (see the \r
+# \dotfile command).\r
+\r
+DOTFILE_DIRS = \r
+\r
+# The MAX_DOT_GRAPH_WIDTH tag can be used to set the maximum allowed width \r
+# (in pixels) of the graphs generated by dot. If a graph becomes larger than \r
+# this value, doxygen will try to truncate the graph, so that it fits within \r
+# the specified constraint. Beware that most browsers cannot cope with very \r
+# large images.\r
+\r
+MAX_DOT_GRAPH_WIDTH = 1024\r
+\r
+# The MAX_DOT_GRAPH_HEIGHT tag can be used to set the maximum allows height \r
+# (in pixels) of the graphs generated by dot. If a graph becomes larger than \r
+# this value, doxygen will try to truncate the graph, so that it fits within \r
+# the specified constraint. Beware that most browsers cannot cope with very \r
+# large images.\r
+\r
+MAX_DOT_GRAPH_HEIGHT = 1024\r
+\r
+# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the \r
+# graphs generated by dot. A depth value of 3 means that only nodes reachable \r
+# from the root by following a path via at most 3 edges will be shown. Nodes \r
+# that lay further from the root node will be omitted. Note that setting this \r
+# option to 1 or 2 may greatly reduce the computation time needed for large \r
+# code bases. Also note that a graph may be further truncated if the graph's \r
+# image dimensions are not sufficient to fit the graph (see MAX_DOT_GRAPH_WIDTH \r
+# and MAX_DOT_GRAPH_HEIGHT). If 0 is used for the depth value (the default), \r
+# the graph is not depth-constrained.\r
+\r
+MAX_DOT_GRAPH_DEPTH = 0\r
+\r
+# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent \r
+# background. This is disabled by default, which results in a white background. \r
+# Warning: Depending on the platform used, enabling this option may lead to \r
+# badly anti-aliased labels on the edges of a graph (i.e. they become hard to \r
+# read).\r
+\r
+DOT_TRANSPARENT = NO\r
+\r
+# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output \r
+# files in one run (i.e. multiple -o and -T options on the command line). This \r
+# makes dot run faster, but since only newer versions of dot (>1.8.10) \r
+# support this, this feature is disabled by default.\r
+\r
+DOT_MULTI_TARGETS = NO\r
+\r
+# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will \r
+# generate a legend page explaining the meaning of the various boxes and \r
+# arrows in the dot generated graphs.\r
+\r
+GENERATE_LEGEND = YES\r
+\r
+# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will \r
+# remove the intermediate dot files that are used to generate \r
+# the various graphs.\r
+\r
+DOT_CLEANUP = YES\r
+\r
+#---------------------------------------------------------------------------\r
+# Configuration::additions related to the search engine \r
+#---------------------------------------------------------------------------\r
+\r
+# The SEARCHENGINE tag specifies whether or not a search engine should be \r
+# used. If set to NO the values of all tags below this one will be ignored.\r
+\r
+SEARCHENGINE = NO\r
--- /dev/null
+#!/bin/bash
+
+DIR=`pwd`;
+
+HEADER_FILES=`find $DIR -name '*.h'`;
+
+#echo "Header files: $HEADER_FILES"
+echo "Mismatches:"
+for HEADER_FILE in $HEADER_FILES; do
+ SHORTNAME=`basename $HEADER_FILE`
+ MATCHNAME=`echo $SHORTNAME|sed 's/\./\\\\./'`
+ echo "Investigating references to $SHORTNAME (found at $HEADER_FILE)..."
+ grep -rniI [/\"]$MATCHNAME --exclude '*.d' $DIR/* | grep -v $MATCHNAME
+done;
+
+echo "Done!";
+
--- /dev/null
+\r
+\r
+include scripts/config.mk\r
+export ARCH\r
+\r
+Q?=@\r
+export Q\r
+export TOPDIR = $(CURDIR)\r
+export RELEASE = n\r
+export PATH\r
+export BUILD_TREE=n\r
+export RELEASE_TREE=y\r
+\r
+\r
+USE_DBG_PRINTF?=y\r
+\r
+# Directories we can build\r
+subdir-y += examples/simple\r
+\r
+# Cmd.exe fix \r
+PATH := /usr/bin/:$(PATH) \r
+find := $(shell which find)\r
+\r
+all:\r
+\r
+ifneq ($(MAKECMDGOALS),clean) \r
+ ifeq ($(ARCH),) \r
+ $(error no ARCH=[ppc55xx], $(ARCH))\r
+ endif\r
+ \r
+ ifeq ($(ARCH),)\r
+ ARCH_LIST = ppc55xx ppc5xx win32\r
+ else \r
+ ARCH_LIST = $(ARCH)\r
+ endif\r
+endif\r
+\r
+\r
+export CFG_MCU \r
+export CFG_CPU\r
+export MCU\r
+export def-y=$(CFG_ARCH_$(ARCH)) $(CFG_MCU) $(CFG_CPU)\r
+\r
+objdir = obj_$(ARCH)\r
+\r
+\r
+builddir-y = $(filter $(MAKECMDGOALS),$(subdir-y)) \r
+\r
+.PHONY: $(builddir-y)\r
+.PHONY: clean\r
+\r
+.PHONY: help\r
+help:\r
+ @echo "make [all|clean] ARCH=[ppc55xx]"\r
+\r
+export def-y\r
+\r
+# The interesting things in this makefile( uses ideas from http://make.paulandlesley.org/ ) \r
+# \r
+# We descend into the object directories and build the. That way it's easier to build\r
+# multi-arch support and we don't have to use objdir everywhere. \r
+# \r
+# ROOTDIR - The top-most directory ( this directory ) \r
+# SUBDIR - The subdirectory we decend into\r
+\r
+$(builddir-y):\r
+ +@[ -d $@/$(objdir) ] || mkdir -p $@/$(objdir)\r
+ $(Q)$(MAKE) -r -C $@/$(objdir) -f $(CURDIR)/scripts/rules.mk ROOTDIR=$(CURDIR) SUBDIR=$@ all\r
+ \r
+clean:\r
+ @echo "Clean:"\r
+ @echo " Removing objectfiles and libs for ARCH=$(ARCH)"\r
+ $(Q)find $(foreach tmp, $(ARCH_LIST),$(addsuffix /obj_$(tmp),$(subdir-y))) -type f -name '*' | xargs rm -f\r
+\r
+\r
+\r
--- /dev/null
+\r
+# incoming \r
+# SUBDIR - also the same as the MAKECMDGOAL\r
+# ROOTDIR \r
+\r
+# environment should handle\r
+# Targets\r
+# pc: gcc(_WIN32), ppc: gcc(_PPC) and diab(_PPC) \r
+\r
+CFG_ARCH_$(ARCH):=y\r
+\r
+RELDIR := $(subst $(TOPDIR)/,,$(CURDIR))\r
+\r
+dummy:\r
+\r
+COMPILER?=gcc\r
+include $(ROOTDIR)/scripts/cc_$(COMPILER).mk\r
+\r
+# Create the target name... \r
+target := $(subst /,_,$(SUBDIR))\r
+\r
+# Get object files\r
+include ../makefile\r
+\r
+# build- targets are "end" target that the included makefile want's to build\r
+all: $(build-lib-y) $(build-exe-y)\r
+\r
+# Determine what kind of filetype to build from \r
+VPATH += ../src\r
+VPATH += ..\r
+\r
+inc-y += ../include\r
+\r
+.SUFFIXES:\r
+\r
+# Extremly simple depencendy stuff\r
+-include $(subst .o,.d,$(obj-y))\r
+\r
+# Compile\r
+%.o: %.c\r
+ @echo " >> CC $<"\r
+ $(CC) -c $(CFLAGS) -o $@ $(addprefix -I ,$(inc-y)) $(addprefix -D,$(def-y)) $<\r
+\r
+# Assembler\r
+%.o: %.s\r
+ $(AS) $(ASFLAGS) -o $@ $<\r
+ \r
+# PP Assembler \r
+%.s: %.S\r
+ @echo " >> CPP $<"\r
+ $(CPP) -o $@ $(addprefix -I ,$(inc-y)) $(addprefix -D,$(def-y)) $<\r
+ \r
+# lib \r
+$(build-lib-y): $(dep-y) $(obj-y)\r
+ @echo " >> AR $(RELDIR)/$@" \r
+ $(AR) -r -o $@ $(obj-y) 2> /dev/null\r
+ $(Q)cp $@ ../lib\r
+\r
+# exe\r
+$(build-exe-y): $(obj-y) $(sim-y) $(libitem-y)\r
+ @echo " >> LD $(RELDIR)/$@" \r
+ $(LD) $(LDFLAGS) $(ldcmdfile-y) -o $@ $(obj-y) $(libpath-y) --start-group $(lib-y) $(libitem-y) --end-group $(LDMAPFILE)\r
+ @echo " >>>>>>> DONE <<<<<<<<<"\r
+
\ No newline at end of file
--- /dev/null
+\r
+CFG_ARCH_$(ARCH):=y\r
+\r
+RELDIR := $(subst $(TOPDIR)/,,$(CURDIR))\r
+\r
+# Create the target name... \r
+target := $(subst /,_,$(SUBDIR))\r
+\r
+#===== MODULE CONFIGURATION =====\r
+include $(ROOTDIR)/boards/$(BOARDDIR)/build_config.mk\r
+-include ../build_config.mk\r
+\r
+define MOD_AVAIL_template\r
+ MOD_$(1)=y\r
+endef\r
+\r
+define MOD_USE_template\r
+ USE_$(1)=y\r
+ def-y += USE_$(1)\r
+endef\r
+\r
+define CFG_template\r
+ CFG_$(1)=y\r
+ def-y += CFG_$(1)\r
+endef\r
+\r
+\r
+$(foreach mod,$(MOD_AVAIL),$(eval $(call MOD_AVAIL_template,${mod})))\r
+$(foreach mod,$(MOD_USE),$(eval $(call MOD_USE_template,${mod})))\r
+$(foreach mod,$(CFG),$(eval $(call CFG_template,${mod})))\r
+def-y += $(ARCH) $(ARCH_FAM) $(ARCH_MCU) \r
+\r
+not_avail = $(filter-out $(MOD_AVAIL),$(MOD_USE))\r
+ifneq ($(not_avail),)\r
+$(error Trying to build a module that is not available: $(not_avail))\r
+endif\r
+\r
+#===== COMPILER CONFIG =====\r
+\r
+ARCH_PATH-y = arch/$(ARCH_FAM)/$(ARCH)\r
+\r
+# Include compiler generic and arch specific\r
+COMPILER?=gcc\r
+ifneq ($(ARCH),)\r
+include $(ROOTDIR)/$(ARCH_PATH-y)/scripts/gcc.mk\r
+endif\r
+include $(ROOTDIR)/scripts/cc_$(COMPILER).mk\r
+\r
+# Get object files\r
+include ../makefile\r
+\r
+inc-y += $(ROOTDIR)/include\r
+inc-$(CFG_PPC) += $(ROOTDIR)/include/ppc\r
+inc-$(CFG_ARM) += $(ROOTDIR)/include/arm\r
+\r
+.PHONY config:\r
+\r
+config:\r
+ @echo "board modules:" $(MOD_AVAIL)\r
+ @echo "example modules:" $(MOD_USE)\r
+ @echo $(MOD) ${def-y}\r
+\r
+# build- targets are "end" target that the included makefile want's to build\r
+all: $(build-lib-y) $(build-exe-y)\r
+\r
+# Determine what kind of filetype to build from \r
+VPATH += $(ROOTDIR)/$(SUBDIR)/src\r
+VPATH += $(ROOTDIR)/$(SUBDIR)\r
+\r
+inc-y += ../include\r
+\r
+.SUFFIXES:\r
+\r
+# Simple depencendy stuff\r
+-include $(subst .o,.d,$(obj-y))\r
+# Some dependency for xxx_offset.c/h also\r
+-include $(subst .h,.d,$(dep-y))\r
+\r
+# Compile\r
+%.o: %.c\r
+ @echo " >> CC $<"\r
+ $(Q)$(CC) -c $(CFLAGS) -o $(abspath $@) $(addprefix -I ,$(inc-y)) $(addprefix -D,$(def-y)) $(realpath $<)\r
+\r
+# Assembler\r
+\r
+%.o: %.s\r
+ @echo " >> AS $< $(ASFLAGS)"\r
+ $(Q)$(AS) $(ASFLAGS) -o $@ $<\r
+ \r
+#$(Q)$(AS) -o /cygdrive/c/apa.o $<\r
+\r
+\r
+# PP Assembler \r
+.SECONDARY %.s:\r
+\r
+%.s: %.S\r
+ @echo " >> CPP $<"\r
+ $(Q)$(CPP) -o $@ $(addprefix -I ,$(inc-y)) $(addprefix -D,$(def-y)) $<\r
+\r
+# @cat $@ \r
+ \r
+.PHONY $(ROOTDIR)/libs:\r
+$(ROOTDIR)/libs:\r
+ mkdir -p $@\r
+\r
+dep-y += $(ROOTDIR)/libs\r
+ \r
+# lib \r
+$(build-lib-y): $(dep-y) $(obj-y)\r
+ @echo " >> AR $(RELDIR)/$@" \r
+ $(Q)$(AR) -r -o $@ $(obj-y) 2> /dev/null\r
+\r
+# Could use readelf -S instead of parsing the *.map file.\r
+$(build-exe-y): $(obj-y) $(sim-y) $(libitem-y) \r
+ @echo " >> LD $@"\r
+ $(LD) $(LDFLAGS) $(ldcmdfile-y) -o $@ $(libpath-y) --start-group $(obj-y) $(lib-y) $(libitem-y) --end-group $(LDMAPFILE)\r
+ @echo "Image size: (decimal)"\r
+ @gawk --non-decimal-data '/^\.text/ { print " text:" $$3+0 " bytes"; rom+=$$3 };\\r
+ /^\.data/ { print " data:" $$3+0 " bytes"; rom+=$$3; ram+=$$3}; \\r
+ /^\.bss/ { print " bss :" $$3+0 " bytes"; ram+=$$3}; \\r
+ END { print " ROM: ~" rom " bytes"; print " RAM: ~" ram " bytes"}' $(subst .elf,.map,$@)\r
+ @echo " >>>>>>> DONE <<<<<<<<<"\r
+ \r
+\r
+$(size-exe-y): $(build-exe-y)\r
+ $(Q)$(OBJDUMP) -h $<\r
+ @echo TODO: Parse the file....\r
+\r
+.PHONY clean:\r
+ @-rm -f *.o *.d *.h *.elf *.a\r
--- /dev/null
+\r
+CFG_ARCH_$(ARCH):=y\r
+\r
+RELDIR := $(subst $(TOPDIR)/,,$(CURDIR))\r
+\r
+-include $(ROOTDIR)/boards/$(BOARDDIR)/config.mk\r
+\r
+ARCH_PATH-y = arch/$(ARCH_FAM)/$(ARCH)\r
+\r
+# Include compiler generic and arch specific\r
+COMPILER?=gcc\r
+include $(ROOTDIR)/scripts/cc_$(COMPILER).mk\r
+#include $(ROOTDIR)/$(ARCH_PATH-y)/scripts/gcc.mk\r
+\r
+# Create the target name... \r
+target := $(subst /,_,$(SUBDIR))\r
+\r
+# Get object files\r
+include ../makefile\r
+\r
+inc-y += $(ROOTDIR)/include\r
+inc-$(CFG_PPC) += $(ROOTDIR)/include/ppc \r
+# Build config.mk from config.h \r
+$(ROOTDIR)/boards/$(BOARDDIR)/config.mk: $(ROOTDIR)/boards/$(BOARDDIR)/config.h $(ROOTDIR)/board_config.mk\r
+ @echo Generating config for $(BOARDDIR)\r
+ $(CC) -E -dM $(ROOTDIR)/boards/$(BOARDDIR)/config.h -o config_$(BOARDDIR).h\r
+ @$(SED) -n -f $(ROOTDIR)/scripts/define2make.sed config_$(BOARDDIR).h > $@\r
+# @$(SED) -n -f $(ROOTDIR)/scripts/define2make.sed config_$(BOARDDIR).h > $@ \r
+\r
+\r
+# build- targets are "end" target that the included makefile want's to build\r
+all: $(ROOTDIR)/boards/$(BOARDDIR)/config.mk $(build-lib-y) $(build-exe-y)\r
+\r
+# Determine what kind of filetype to build from \r
+VPATH += $(ROOTDIR)/$(SUBDIR)/src\r
+VPATH += $(ROOTDIR)/$(SUBDIR)\r
+\r
+inc-y += ../include\r
+\r
+.SUFFIXES:\r
+\r
+# Simple depencendy stuff\r
+-include $(subst .o,.d,$(obj-y))\r
+# Some dependency for xxx_offset.c/h also\r
+-include $(subst .h,.d,$(dep-y))\r
+\r
+# Compile\r
+%.o: %.c\r
+ @echo " >> CC $<"\r
+ $(Q)$(CC) -c $(CFLAGS) -o $@ $(addprefix -I ,$(inc-y)) $(addprefix -D,$(def-y)) $<\r
+ \r
+# $(subst /cygdrive/c/,c:/,$<)\r
+\r
+# Assembler\r
+%.o: %.s\r
+ $(Q)$(AS) $(ASFLAGS) -o $@ $<\r
+ \r
+# PP Assembler \r
+%.s: %.S\r
+ @echo " >> CPP $<"\r
+ $(Q)$(CPP) -o $@ $(addprefix -I ,$(inc-y)) $(addprefix -D,$(def-y)) $<\r
+ \r
+#$(warning RULES $(target) $(ARCH) $(MCU) $(build-lib-y)) \r
+ \r
+# lib \r
+$(build-lib-y): $(dep-y) $(obj-y)\r
+ @echo " >> AR $(RELDIR)/$@" \r
+ $(Q)$(AR) -r -o $@ $(obj-y) 2> /dev/null\r
+\r
+# $(Q)cp $@ ../lib\r
+\r
+# @echo " >> LD $(RELDIR)/$@"\r
+# exe\r
+$(build-exe-y): $(obj-y) $(sim-y) $(libitem-y) \r
+ @echo " >> LD $@"\r
+ $(LD) $(LDFLAGS) $(ldcmdfile-y) -o $@ $(libpath-y) --start-group $(obj-y) $(lib-y) $(libitem-y) --end-group $(LDMAPFILE)\r
+ @echo " >>>>>>> DONE <<<<<<<<<"\r
+ \r
+\r
+$(size-exe-y): $(build-exe-y)\r
+ $(Q)$(OBJDUMP) -h $<\r
+ @echo TODO: Parse the file....\r
+#\r
+# Installation\r
+# \r
+#\r
+#$(foreach obj,$(obj-y),$(shell cp $(obj) $(INSTALL_PATH)))\r
+#\r
+#define mkdir\r
+#+@[ -d $@/$(objdir) ] || mkdir -p $@/$(objdir)\r
+#endef\r
+include $(ROOTDIR)/scripts/rules_install.mk\r
+\r
+install:\r
+ $(Q)$(call cmd_mkdir,$(install-mkdir-y))\r
+ $(Q)$(call cmd_install_dir,$(install-dir-y)) \r
+ $(Q)$(call cmd_install_file,$(install-file-y))\r
+\r
+\r
+#\r
+# @echo $(install-dir-y)\r
+# @echo $(call split,$(install-dir-y))\r
+# @echo $(word 1,$(call split,$(install-dir-y)))\r
+# $(foreach dir, $(install-dir-y), $(shell cp -r $(word 1,$(call split,$(dir))) $(INSTALL_PATH)/$(word 2,$(call split,$(dir)))))\r
+# $(foreach file, $(install-file-y), $(shell cp $(word 1,$(call split,$(file))) $(INSTALL_PATH)/$(word 2,$(call split,$(file)))))\r
+#\r
+#\r
+# @echo $(word 1,$(subst \,, ,$(install-dir-y)))\r
+# $(foreach dir,$(install-dir-y),$(shell cp $(word 1,$(subst , ,$(dir))) $(INSTALL_PATH)/$(word 2,$(dir)))) \r
+
\ No newline at end of file
--- /dev/null
+\r
+define test\r
+ print &$arg0\r
+ print &($arg0.ready_list)\r
+ print $arg0.ready_list\r
+end\r
+\r
+echo \n\n\r
+set print address on\r
+print &k_sys.ready_head\r
+print k_sys.ready_head\r
+test pcb_list[0]\r
+test pcb_list[1]\r
+\r
+#printf "k_sys.ready_head(location)=0x%x\n",&k_sys.ready_head\r
+#printf "pcb_list[0](loc)=0x%x\n",(&((pcb_t *)pcb_list)[0])\r
+#print (&((pcb_t *)pcb_list)[0])->ready_list\r
+#printf "pcb_list[1](loc)=0x%x\n",(&((pcb_t *)pcb_list)[1])\r
+#print (&((pcb_t *)pcb_list)[1])->ready_list\r
+\r
+#echo \n\r
+#output k_sys.ready_head\r
+#echo \npcb_list[0]\n\r
+#echo &pcb_list[0]\n\r
+#output (&((pcb_t *)pcb_list)[0])\r
+#echo \nready_list\n\r
+#output &(&((pcb_t *)pcb_list)[0])->ready_list\r
+#echo \n\r
+#output (&((pcb_t *)pcb_list)[0])->ready_list\r
+\r
+#echo \n\n&pcb_list[1]\n\r
+#output (&((pcb_t *)pcb_list)[1])\r
+#echo \nready_list\n\r
+#output &(&((pcb_t *)pcb_list)[1])->ready_list\r
+#echo \n\r
+#output (&((pcb_t *)pcb_list)[1])->ready_list\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include "EcuM.h"\r
+#include "Modules.h"\r
+#include "string.h"\r
+#include "Os.h"\r
+#include "EcuM_Internals.h"\r
+#include "EcuM_Cbk.h"\r
+#include "Mcu.h"\r
+#include "Det.h"\r
+#include "int_ctrl.h"\r
+\r
+EcuM_GobalType internal_data;\r
+\r
+#if ( ECUM_VERSION_INFO_API == STD_ON )\r
+static Std_VersionInfoType _EcuM_VersionInfo =\r
+{\r
+ .vendorID = (uint16)1,\r
+ .moduleID = (uint16)1,\r
+ .instanceID = (uint8)1,\r
+ .sw_major_version = (uint8)ECUM_SW_MAJOR_VERSION,\r
+ .sw_minor_version = (uint8)ECUM_SW_MINOR_VERSION,\r
+ .sw_patch_version = (uint8)ECUM_SW_PATCH_VERSION,\r
+ .ar_major_version = (uint8)ECUM_AR_MAJOR_VERSION,\r
+ .ar_minor_version = (uint8)ECUM_AR_MINOR_VERSION,\r
+ .ar_patch_version = (uint8)ECUM_AR_PATCH_VERSION,\r
+};\r
+#endif\r
+\r
+void EcuM_Init( void )\r
+{\r
+ internal_data.current_state = ECUM_STATE_STARTUP_ONE;\r
+\r
+ // Initialise drivers that are needed to determine PostBuild configuration\r
+ EcuM_AL_DriverInitZero();\r
+\r
+ // Initialise the OS\r
+ InitOS();\r
+\r
+ // Enable interrupts\r
+ IntCtrl_Init();\r
+\r
+\r
+ // Determine PostBuild configuration\r
+ internal_data.config = EcuM_DeterminePbConfiguration();\r
+\r
+ // Check consistensy of PB configuration\r
+ // TODO\r
+\r
+ // Initialise drivers needed before the OS-starts\r
+ EcuM_AL_DriverInitOne(internal_data.config);\r
+\r
+ // Determine the reset/wakeup reason\r
+ // TODO Mcu_ResetType type = Mcu_GetResetReason();\r
+\r
+ // Set default shutdown target\r
+ internal_data.shutdown_target = internal_data.config->EcuMDefaultShutdownTarget;\r
+ internal_data.shutdown_mode = internal_data.config->EcuMDefaultShutdownMode;\r
+\r
+ // Set default appliaction mode\r
+ internal_data.app_mode = internal_data.config->EcuMDefaultAppMode;\r
+\r
+ internal_data.initiated = TRUE;\r
+\r
+ // Start this baby up\r
+ StartOS(internal_data.app_mode);\r
+}\r
+\r
+void EcuM_StartupTwo()\r
+{\r
+#if (ECUM_INCLUDE_NVRAM_MGR == STD_ON)\r
+ uint32 timer;\r
+#endif\r
+\r
+ internal_data.current_state = ECUM_STATE_STARTUP_TWO;\r
+\r
+ // Initialse the BSW scheduler\r
+ // TODO SchM_Init();\r
+\r
+ // Initialize drivers that don't need NVRAM data\r
+ EcuM_AL_DriverInitTwo(internal_data.config);\r
+\r
+#if (ECUM_INCLUDE_NVRAM_MGR == STD_ON)\r
+ // Start timer to wait for NVM job to complete\r
+ timer = Frt_GetTimeElapsed();\r
+#endif\r
+\r
+ // Prepare the system to startup RTE\r
+ // TODO EcuM_OnRTEStartup();\r
+\r
+ //Rte_Start();\r
+\r
+#if (ECUM_INCLUDE_NVRAM_MGR == STD_ON)\r
+ // Wait for the NVM job to terminate\r
+ while(Frt_GetTimeElapsed()-timer < internal_data.config.EcuMNvramReadAllTimeout)\r
+ {\r
+ //TODO\r
+ }\r
+#endif\r
+\r
+ // Initialse drivers that need NVRAM data\r
+ EcuM_AL_DriverInitThree(internal_data.config);\r
+\r
+ // Indicate mode change to RTE\r
+ // TODO\r
+}\r
+\r
+// Typically called from OS shutdown hook\r
+void EcuM_Shutdown()\r
+{\r
+ internal_data.current_state = ECUM_STATE_GO_OFF_TWO;\r
+\r
+ // Let the last drivers do a nice shutdown\r
+ EcuM_OnGoOffTwo();\r
+\r
+ if (internal_data.shutdown_target == ECUM_STATE_OFF)\r
+ EcuM_AL_SwitchOff();\r
+ else\r
+ Mcu_PerformReset();\r
+}\r
+\r
+Std_ReturnType EcuM_GetState(EcuM_StateType* state)\r
+{\r
+#if (ECUM_DEV_ERROR_DETECT == STD_ON)\r
+ if (state == NULL)\r
+ {\r
+ Det_ReportError(MODULE_ID_ECUM, 1, ECUM_GETSTATE_ID, ECUM_E_NULL_POINTER);\r
+ return E_NOT_OK;\r
+ }\r
+#endif\r
+\r
+ *state = internal_data.current_state;\r
+\r
+ return E_OK;\r
+}\r
+\r
+Std_ReturnType EcuM_SelectApplicationMode(AppModeType appMode)\r
+{\r
+#if (ECUM_DEV_ERROR_DETECT == STD_ON)\r
+ if (!internal_data.initiated)\r
+ {\r
+ Det_ReportError(MODULE_ID_ECUM, 1, ECUM_SELECTAPPMODE_ID, ECUM_E_NOT_INITIATED);\r
+ return E_NOT_OK;\r
+ }\r
+#endif\r
+\r
+ // TODO Save this application mode for next startup\r
+\r
+ return E_NOT_OK;\r
+}\r
+\r
+Std_ReturnType EcuM_GetApplicationMode(AppModeType* appMode)\r
+{\r
+#if (ECUM_DEV_ERROR_DETECT == STD_ON)\r
+ if (!internal_data.initiated)\r
+ {\r
+ Det_ReportError(MODULE_ID_ECUM, 1, ECUM_GETAPPMODE_ID, ECUM_E_NOT_INITIATED);\r
+ return E_NOT_OK;\r
+ }\r
+\r
+ if (appMode == NULL)\r
+ {\r
+ Det_ReportError(MODULE_ID_ECUM, 1, ECUM_GETAPPMODE_ID, ECUM_E_NULL_POINTER);\r
+ return E_NOT_OK;\r
+ }\r
+#endif\r
+\r
+ *appMode = internal_data.app_mode;\r
+\r
+ return E_OK;\r
+}\r
+\r
+Std_ReturnType EcuM_SelectBootTarget(EcuM_BootTargetType target)\r
+{\r
+#if (ECUM_DEV_ERROR_DETECT == STD_ON)\r
+ if (!internal_data.initiated)\r
+ {\r
+ Det_ReportError(MODULE_ID_ECUM, 1, ECUM_SELECT_BOOTARGET_ID, ECUM_E_NOT_INITIATED);\r
+ return E_NOT_OK;\r
+ }\r
+#endif\r
+\r
+ // TODO Do something great here\r
+\r
+ return E_NOT_OK;\r
+}\r
+\r
+Std_ReturnType EcuM_GetBootTarget(EcuM_BootTargetType* target)\r
+{\r
+#if (ECUM_DEV_ERROR_DETECT == STD_ON)\r
+ if (!internal_data.initiated)\r
+ {\r
+ Det_ReportError(MODULE_ID_ECUM, 1, ECUM_GET_BOOTARGET_ID, ECUM_E_NOT_INITIATED);\r
+ return E_NOT_OK;\r
+ }\r
+\r
+ if (target == NULL)\r
+ {\r
+ Det_ReportError(MODULE_ID_ECUM, 1, ECUM_GET_BOOTARGET_ID, ECUM_E_NULL_POINTER);\r
+ return E_NOT_OK;\r
+ }\r
+#endif\r
+\r
+ // TODO Return selected boot target here\r
+\r
+ return E_NOT_OK;\r
+}\r
+\r
+#if (ECUM_VERSION_INFO_API == STD_ON)\r
+void EcuM_GetVersionInfo(Std_VersionInfoType *versionInfo)\r
+{\r
+ memcpy(versionInfo, &_EcuM_VersionInfo, sizeof(Std_VersionInfoType));\r
+}\r
+#endif\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+// This file is just examples of implementation for the stubs needed by\r
+// the EcuM. Every Autocore application should use an own version of this\r
+// file to implement the setup and tear down of the system.\r
+\r
+#include "EcuM.h"\r
+#include "Det.h"\r
+#if defined(USE_MCU)\r
+#include "Mcu.h"\r
+#endif\r
+#if defined(USE_GPT)\r
+#include "Gpt.h"\r
+#endif\r
+#if defined(USE_CAN)\r
+#include "Can.h"\r
+#endif\r
+#if defined(USE_CANIF)\r
+#include "CanIf.h"\r
+#endif\r
+#if defined(USE_PDUR)\r
+#include "PduR.h"\r
+#endif\r
+#if defined(USE_COM)\r
+#include "Com.h"\r
+#endif\r
+#if defined(USE_PWM)\r
+#include "Pwm.h"\r
+#endif\r
+\r
+void EcuM_AL_DriverInitZero()\r
+{\r
+ Det_Init();\r
+ Det_Start();\r
+}\r
+\r
+EcuM_ConfigType* EcuM_DeterminePbConfiguration()\r
+{\r
+ return &EcuMConfig;\r
+}\r
+\r
+void EcuM_AL_DriverInitOne(const EcuM_ConfigType *ConfigPtr)\r
+{\r
+#if defined(USE_MCU)\r
+ Mcu_Init(ConfigPtr->McuConfig);\r
+\r
+ // Set up default clock (Mcu_InitClock requires initRun==1)\r
+ Mcu_InitClock( ConfigPtr->McuConfig->McuDefaultClockSettings );\r
+\r
+ // Wait for PLL to sync.\r
+ while (Mcu_GetPllStatus() != MCU_PLL_LOCKED)\r
+ ;\r
+#endif\r
+\r
+#if defined(USE_PORT)\r
+ // Setup Port\r
+ Port_Init(ConfigPtr->PortConfig);\r
+#endif\r
+\r
+\r
+#if defined(USE_GPT)\r
+ // Setup the GPT\r
+ Gpt_Init(ConfigPtr->GptConfig);\r
+#endif\r
+\r
+ // Setup watchdog\r
+ // TODO\r
+\r
+#if defined(USE_DMA)\r
+ // Setup DMA\r
+ Dma_Init(ConfigPtr->DmaConfig);\r
+#endif\r
+\r
+#if defined(USE_ADC)\r
+ // Setup ADC\r
+ Adc_Init(ConfigPtr->AdcConfig);\r
+#endif\r
+\r
+ // Setup ICU\r
+ // TODO\r
+\r
+ // Setup PWM\r
+#if defined(USE_PWM)\r
+ // Setup PWM\r
+ Pwm_Init(ConfigPtr->PwmConfig);\r
+#endif\r
+}\r
+\r
+void EcuM_AL_DriverInitTwo(const EcuM_ConfigType* ConfigPtr)\r
+{\r
+#if defined(USE_SPI)\r
+ // Setup SPI\r
+ Spi_Init(ConfigPtr->SpiConfig);\r
+#endif\r
+\r
+#if defined(USE_EEP)\r
+ // Setup EEP\r
+ Eep_Init(ConfigPtr->EEpConfig);\r
+#endif\r
+\r
+#if defined(USE_FLS)\r
+ // Setup Flash\r
+ FlashInit(ConfigPtr->FlashConfig);\r
+#endif\r
+\r
+ // Setup NVRAM Manaager\r
+ // TODO\r
+\r
+ // Setup CAN tranceiver\r
+ // TODO\r
+\r
+#if defined(USE_CAN)\r
+ // Setup Can driver\r
+ Can_Init(ConfigPtr->CanConfig);\r
+#endif\r
+\r
+#if defined(USE_CANIF)\r
+ // Setup CanIf\r
+ CanIf_Init(ConfigPtr->CanIfConfig);\r
+#endif\r
+\r
+ // Setup LIN\r
+ // TODO\r
+\r
+#if defined(USE_PDUR)\r
+ // Setup PDU Router\r
+ PduR_Init(ConfigPtr->PduRConfig);\r
+#endif\r
+\r
+#if defined(USE_COM)\r
+ // Setup COM layer\r
+ Com_Init(ConfigPtr->ComConfig);\r
+#endif\r
+\r
+}\r
+\r
+void EcuM_AL_DriverInitThree(const EcuM_ConfigType ConfigPtr)\r
+{\r
+#if defined(USE_CANIF)\r
+ // Startup the CAN interafce; due to the missing COM manager\r
+ CanIf_InitController(CAN_CTRL_A, 0);\r
+ CanIf_SetControllerMode(CAN_CTRL_A, CANIF_CS_STARTED);\r
+#endif\r
+}\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include "EcuM.h"\r
+\r
+EcuM_ConfigType EcuMConfig =\r
+{\r
+ .EcuMDefaultShutdownTarget = ECUM_STATE_RESET,\r
+ .EcuMDefaultShutdownMode = 0, // Don't care\r
+ .EcuMDefaultAppMode = 0, // Don't care\r
+\r
+#if defined(USE_MCU)\r
+ .McuConfig = McuConfigData,\r
+#endif\r
+#if defined(USE_PORT)\r
+ .PortConfig = &PortConfigData,\r
+#endif\r
+#if defined(USE_CAN)\r
+ .CanConfig = &CanConfigData,\r
+#endif\r
+#if defined(USE_CANIF)\r
+ .CanIfConfig = &CanIf_Config,\r
+#endif\r
+#if defined(USE_COM)\r
+ .ComConfig = &ComConfiguration,\r
+#endif\r
+#if defined(USE_DMA)\r
+ .DmaConfig = DmaConfig,\r
+#endif\r
+#if defined(USE_ADC)\r
+ .AdcConfig = AdcConfig,\r
+#endif\r
+#if defined(USE_PWM)\r
+ .PwmConfig = &PwmConfig,\r
+#endif\r
+};\r
+\r
+void EcuM_OnGoOffTwo( void ) {\r
+\r
+}\r
+\r
+void EcuM_AL_SwitchOff( void ) {\r
+\r
+}\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef ECUM_CFG_H_\r
+#define ECUM_CFG_H_\r
+\r
+#define ECUM_VERSION_INFO_API STD_ON\r
+#define ECUM_INCLUDE_NVRAM_MGR STD_OFF\r
+#define ECUM_DEV_ERROR_DETECT STD_ON\r
+\r
+#include "EcuM_Generated_Types.h"\r
+\r
+extern EcuM_ConfigType EcuMConfig;\r
+\r
+\r
+#endif /*ECUM_CFG_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+// Struct generated by the code generator depends on the\r
+// included modules\r
+\r
+#ifndef _ECUM_GENERATED_TYPES_H_\r
+#define _ECUM_GENERATED_TYPES_H_\r
+\r
+#if defined(USE_MCU)\r
+#include "Mcu.h"\r
+#endif\r
+#if defined(USE_PORT)\r
+#include "Port.h"\r
+#endif\r
+#if defined(USE_CAN)\r
+#include "Can.h"\r
+#endif\r
+#if defined(USE_CANIF)\r
+#include "CanIf.h"\r
+#endif\r
+#if defined(USE_PWM)\r
+#include "Pwm.h"\r
+#endif\r
+#if defined(USE_COM)\r
+#include "Com.h"\r
+#endif\r
+#if defined(USE_DMA)\r
+#include "Dma.h"\r
+#endif\r
+#if defined(USE_ADC)\r
+#include "Adc.h"\r
+#endif\r
+\r
+typedef struct\r
+{\r
+ EcuM_StateType EcuMDefaultShutdownTarget;\r
+ uint8 EcuMDefaultShutdownMode;\r
+ AppModeType EcuMDefaultAppMode;\r
+\r
+#if defined(USE_MCU)\r
+ const Mcu_ConfigType* McuConfig;\r
+#endif\r
+#if defined(USE_PORT)\r
+ const Port_ConfigType* PortConfig;\r
+#endif\r
+#if defined(USE_CAN)\r
+ const Can_ConfigType* CanConfig;\r
+#endif\r
+#if defined(USE_CANIF)\r
+ const CanIf_ConfigType* CanIfConfig;\r
+#endif\r
+#if defined(USE_COM)\r
+ const Com_ConfigType* ComConfig;\r
+#endif\r
+#if defined(USE_PWM)\r
+ const Pwm_ConfigType* PwmConfig;\r
+#endif\r
+#if defined(USE_DMA)\r
+ const Dma_ConfigType* DmaConfig;\r
+#endif\r
+#if defined(USE_ADC)\r
+ const Adc_ConfigType* AdcConfig;\r
+#endif\r
+} EcuM_ConfigType;\r
+\r
+#endif /*_ECUM_GENERATED_TYPES_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+// Struct generated by the code generator depends on the\r
+// included modules\r
+\r
+#ifndef _ECUM_GENERATED_TYPES_H_\r
+#define _ECUM_GENERATED_TYPES_H_\r
+\r
+#if defined(USE_MCU)\r
+#include "Mcu.h"\r
+#endif\r
+#if defined(USE_PORT)\r
+#include "Port.h"\r
+#endif\r
+#if defined(USE_CAN)\r
+#include "Can.h"\r
+#endif\r
+#if defined(USE_CANIF)\r
+#include "CanIf.h"\r
+#endif\r
+#if defined(USE_PWM)\r
+#include "Pwm.h"\r
+#endif\r
+\r
+typedef struct\r
+{\r
+ EcuM_StateType EcuMDefaultShutdownTarget;\r
+ uint8 EcuMDefaultShutdownMode;\r
+ AppModeType EcuMDefaultAppMode;\r
+\r
+#if defined(USE_MCU)\r
+ const Mcu_ConfigType* McuConfig;\r
+#endif\r
+#if defined(USE_PORT)\r
+ const Port_ConfigType* PortConfig;\r
+#endif\r
+#if defined(USE_CAN)\r
+ const Can_ConfigType* CanConfig;\r
+#endif\r
+#if defined(USE_CANIF)\r
+ const CanIf_ConfigType* CanIfConfig;\r
+#endif\r
+#if defined(USE_COM)\r
+ const Com_ConfigType* ComConfig;\r
+#endif\r
+#if defined(USE_PWM)\r
+ const Pwm_ConfigType* PwmConfig;\r
+#endif\r
+} EcuM_ConfigType;\r
+\r
+#endif /*_ECUM_GENERATED_TYPES_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+// Structs and types used internal in the module\r
+\r
+#ifndef _ECUM_INTERNALS_H_\r
+#define _ECUM_INTERNALS_H_\r
+\r
+typedef struct\r
+{\r
+ boolean initiated;\r
+ EcuM_ConfigType* config;\r
+ EcuM_StateType shutdown_target;\r
+ uint8 shutdown_mode;\r
+ AppModeType app_mode;\r
+ EcuM_StateType current_state;\r
+} EcuM_GobalType;\r
+\r
+extern EcuM_GobalType internal_data;\r
+\r
+#endif /*_ECUM_INTERNALS_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include "EcuM.h"\r
+#include "EcuM_Internals.h"\r
+\r
+void EcuM_MainFunction(void)\r
+{\r
+#if (ECUM_DEV_ERROR_DETECT == STD_ON)\r
+ if (!internal_data->initiated)\r
+ {\r
+ Det_ReportError(MODULE_ID_ECUM, 1, ECUM_MAINFUNCTION_ID, ECUM_E_NOT_INITIATED);\r
+ return;\r
+ }\r
+#endif\r
+\r
+ // If coming from startup sequence, enter Run mode\r
+ if (internal_data->current_state == ECUM_STATE_STARTUP_TWO)\r
+ enter_run_mode();\r
+\r
+ if (internal_data->current_state == ECUM_STATE_APP_RUN)\r
+ {\r
+ if (!hasRunRequests() && (internal_data_run_state_timeout == 0))\r
+ {\r
+ enter_post_run_mode();\r
+ return;\r
+ }\r
+ }\r
+\r
+ if (internal_data->current_state == ECUM_STATE_APP_POST_RUN)\r
+ {\r
+ if (hasRunRequests())\r
+ {\r
+ enter_run_mode(); // ECUM_2866\r
+ return;\r
+ }\r
+\r
+ if (!hasPostRunRequests())\r
+ {\r
+ EcuM_OnExitPostRun(); // ECUM_2761\r
+ enter_prep_shutdown_mode();\r
+ return;\r
+ }\r
+ }\r
+}\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+/* Post Build time configuration */\r
+\r
+unsigned char ECUM_DEFAULT_APP_MODE = 0; \r
+unsigned char ECUM_DEFAULT_SHUTDOWN_TARGET = 0;\r
+unsigned char ECUM_RUN_SELF_REQUEST_PERIOD = 0;\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+#include "SchM.h"\r
+\r
+\r
+void SchM_Init( void ) {\r
+ \r
+}\r
+void SchM_Deinit( void ) {\r
+ \r
+}\r
+\r
+void SchM_GetVersionInfo( Std_VersionInfoType *versionInfo ) {\r
+ \r
+}\r
+\r
+/* \r
+ * Implement\r
+ */\r
+// Critical sections\r
+// void SchM_Enter_<ModulePrefix>( uint8 instance, uint8 exclusiveArea )\r
+// void SchM_Exit_<ModulePrefix>( uint8 instance, uint8 exclusiveArea )\r
+\r
+// Triggers\r
+// SchM_ReturnType SchM_ActMainFunction_<ModulePrefix>( uint8 instance, uint8 activationPoint );\r
+// SchM_ReturnType SchM_CancelMainFunction_<ModulePrefix>( uint8 instance, uint8 activationPoint );\r
+\r
+/* \r
+ * Callable functions in the <ModulePrefix>\r
+ */ \r
+// <ModulePrefix>_MainFunction_<name>()\r
+// <ModulePrefix>_MainFunction_<name>()\r
+\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef SCHM_H_\r
+#define SCHM_H_\r
+\r
+#include "Std_Types.h"\r
+\r
+void SchM_Init( void );\r
+void SchM_Deinit( void );\r
+void SchM_GetVersionInfo( Std_VersionInfoType *versionInfo );\r
+\r
+#endif /*SCHM_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef SCHM_CFG_H_\r
+#define SCHM_CFG_H_\r
+\r
+#endif /*SCHM_CFG_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include "WdgM.h"\r
+#include "Mcu.h"\r
+\r
+const WdgM_ConfigType *wdgMConfigPtr;\r
+static WdgM_SupervisedStatusType WdgM_GlobalSupervisionStatus = WDBG_ALIVE_OK;\r
+\r
+Std_ReturnType WdgM_UpdateAliveCounter (WdgM_SupervisedEntityIdType SEid)\r
+{\r
+ Wdgm_SupervisionType *supervisionPtr = &(wdgMConfigPtr->Wdgm_SupervisionPtr)[SEid];\r
+\r
+ if (supervisionPtr->ActivationStatus == WDBG_SUPERVISION_ENABLED)\r
+ {\r
+ supervisionPtr->AliveCounter++;\r
+ }\r
+ return (E_OK);\r
+}\r
+\r
+Std_ReturnType WdgM_ActivateAliveSupervision (WdgM_SupervisedEntityIdType SEid)\r
+{\r
+ Wdgm_SupervisionType *supervisionPtr = &(wdgMConfigPtr->Wdgm_SupervisionPtr)[SEid];\r
+\r
+ supervisionPtr->ActivationStatus = WDBG_SUPERVISION_ENABLED;\r
+\r
+ return (E_OK);\r
+}\r
+\r
+Std_ReturnType WdgM_DeactivateAliveSupervision (WdgM_SupervisedEntityIdType SEid)\r
+{\r
+ Wdgm_SupervisionType *supervisionPtr = &(wdgMConfigPtr->Wdgm_SupervisionPtr)[SEid];\r
+\r
+ supervisionPtr->ActivationStatus = WDBG_SUPERVISION_DISABLED;\r
+ return (E_OK);\r
+}\r
+\r
+void WdgM_Init(const WdgM_ConfigType *ConfigPtr)\r
+{\r
+ WdgM_SupervisedEntityIdType SEid;\r
+ Wdgm_SupervisionType *supervisionPtr;\r
+ WdgM_SupervisedEntityType* supervisedEntityPtr;\r
+\r
+ for (SEid = 0; SEid < WDBG_NBR_OF_ALIVE_SIGNALS; SEid++)\r
+ {\r
+ supervisionPtr = &(ConfigPtr->Wdgm_SupervisionPtr)[SEid];\r
+ supervisedEntityPtr = (WdgM_SupervisedEntityType*)&(ConfigPtr->WdgM_SupervisedEntityPtr)[SEid];\r
+ supervisionPtr->ActivationStatus = supervisedEntityPtr->WdgM_ActivationStatus;\r
+ }\r
+ wdgMConfigPtr = ConfigPtr;\r
+\r
+}\r
+\r
+void WdgM_MainFunction_AliveSupervision (void)\r
+{\r
+ WdgM_SupervisedEntityIdType SEid;\r
+ Wdgm_SupervisionType *supervisionPtr;\r
+ const WdgM_SupervisedEntityType *entityPtr;\r
+ WdgM_SupervisionCounterType aliveCalc, nSC, nAl, eai;\r
+ WdgM_SupervisedStatusType maxLocal = WDBG_ALIVE_OK;\r
+ static WdgM_SupervisionCounterType expiredSupervisionCycles = 0;\r
+\r
+ for (SEid = 0; SEid < WDBG_NBR_OF_ALIVE_SIGNALS; SEid++)\r
+ {\r
+ supervisionPtr = &(wdgMConfigPtr->Wdgm_SupervisionPtr)[SEid];\r
+ entityPtr = &(wdgMConfigPtr->WdgM_SupervisedEntityPtr)[SEid];\r
+\r
+ if (WDBG_SUPERVISION_ENABLED == supervisionPtr->ActivationStatus)\r
+ {\r
+ supervisionPtr->SupervisionCycle++;\r
+ /* Only perform supervision on the reference cycle. */\r
+ if (supervisionPtr->SupervisionCycle == entityPtr->WdgM_SupervisionReferenceCycle)\r
+ {\r
+ /* Alive algorithm. *\r
+ * n (Al) - n(SC) + EAI == 0 */\r
+ if (entityPtr->WdgM_ExpectedAliveIndications > entityPtr->WdgM_SupervisionReferenceCycle)\r
+ {\r
+ /* Scenario A */\r
+ eai = -entityPtr->WdgM_ExpectedAliveIndications + 1;\r
+\r
+ }\r
+ else\r
+ {\r
+ /* Scenario B */\r
+ eai = entityPtr->WdgM_SupervisionReferenceCycle - 1;\r
+ }\r
+ nSC = supervisionPtr->SupervisionCycle;\r
+ nAl = supervisionPtr->AliveCounter;\r
+ aliveCalc = nAl - nSC + eai;\r
+\r
+ if ((aliveCalc <= entityPtr->WdgM_MaxMargin) &&\r
+ (aliveCalc >= -entityPtr->WdgM_MinMargin))\r
+ {\r
+ /* Entity alive OK. */\r
+ supervisionPtr->SupervisionStatus = WDBG_ALIVE_OK;\r
+ }\r
+ else\r
+ {\r
+ /* Entity alive NOK. */\r
+ supervisionPtr->SupervisionStatus = WDBG_ALIVE_FAILED;\r
+ if (WDBG_ALIVE_FAILED > maxLocal)\r
+ {\r
+ maxLocal = WDBG_ALIVE_FAILED;\r
+ }\r
+ }\r
+\r
+ if (WDBG_ALIVE_FAILED == supervisionPtr->SupervisionStatus)\r
+ {\r
+ if (supervisionPtr->NbrOfFailedRefCycles > entityPtr->WdgM_FailedSupervisionReferenceCycleTolerance)\r
+ {\r
+ supervisionPtr->SupervisionStatus = WDBG_ALIVE_EXPIRED;\r
+ if (WDBG_ALIVE_EXPIRED > maxLocal)\r
+ {\r
+ maxLocal = WDBG_ALIVE_EXPIRED;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ supervisionPtr->NbrOfFailedRefCycles++;\r
+ }\r
+ }\r
+\r
+ /* Reset counters. */\r
+ supervisionPtr->SupervisionCycle = 0;\r
+ supervisionPtr->AliveCounter = 0;\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Try to heal global status. */\r
+ if (WDBG_ALIVE_EXPIRED != WdgM_GlobalSupervisionStatus)\r
+ {\r
+ WdgM_GlobalSupervisionStatus = maxLocal;\r
+ }\r
+ else\r
+ {\r
+ WdgM_GlobalSupervisionStatus = WDBG_ALIVE_EXPIRED;\r
+ }\r
+\r
+ if (WDBG_ALIVE_EXPIRED == WdgM_GlobalSupervisionStatus)\r
+ {\r
+ expiredSupervisionCycles++;\r
+ }\r
+\r
+ if (expiredSupervisionCycles >= wdgMConfigPtr->WdgM_ExpiredSupervisionCycleTolerance)\r
+ {\r
+ WdgM_GlobalSupervisionStatus = WDBG_ALIVE_STOPPED;\r
+ }\r
+}\r
+\r
+boolean WdgM_IsAlive(void)\r
+{\r
+\r
+ if ( WDBG_ALIVE_STOPPED > WdgM_GlobalSupervisionStatus )\r
+ {\r
+ return (TRUE);\r
+ }\r
+ else\r
+ {\r
+ return (FALSE);\r
+ }\r
+}\r
+\r
+void WdgM_MainFunction_Trigger (void)\r
+{\r
+ if ( WdgM_IsAlive() )\r
+ {\r
+ KickWatchdog();\r
+ }\r
+}\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include "WdgM_Cfg.h"\r
+\r
+Std_ReturnType WdgM_UpdateAliveCounter (WdgM_SupervisedEntityIdType SEid);\r
+Std_ReturnType WdgM_ActivateAliveSupervision (WdgM_SupervisedEntityIdType SEid);\r
+Std_ReturnType WdgM_DeactivateAliveSupervision (WdgM_SupervisedEntityIdType SEid);\r
+void WdgM_Init(const WdgM_ConfigType* ConfigPtr);\r
+void WdgM_MainFunction_AliveSupervision (void);\r
+void WdgM_MainFunction_Trigger (void);\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+#ifndef WDGM_CFG_H_\r
+#define WDGM_CFG_H_\r
+\r
+#include "Std_Types.h"\r
+#include "WdgM_Lcfg.h"\r
+\r
+typedef enum\r
+{\r
+ WDBG_ALIVE_OK,\r
+ WDBG_ALIVE_FAILED,\r
+ WDBG_ALIVE_EXPIRED,\r
+ WDBG_ALIVE_STOPPED,\r
+ WDBG_ALIVE_DEACTIVATED,\r
+}WdgM_SupervisedStatusType;\r
+\r
+typedef enum\r
+{\r
+ WDBG_SUPERVISION_DISABLED,\r
+ WDBG_SUPERVISION_ENABLED\r
+}WdgM_ActivationStatusType;\r
+\r
+typedef int16_t WdgM_SupervisionCounterType ;\r
+\r
+typedef struct\r
+{\r
+ WdgM_SupervisionCounterType AliveCounter;\r
+ WdgM_SupervisionCounterType SupervisionCycle;\r
+ WdgM_SupervisedStatusType SupervisionStatus;\r
+ WdgM_SupervisionCounterType NbrOfFailedRefCycles;\r
+ WdgM_ActivationStatusType ActivationStatus;\r
+}Wdgm_SupervisionType;\r
+\r
+typedef struct\r
+{\r
+ const WdgM_SupervisedEntityIdType WdgM_SupervisedEntityID;\r
+ const WdgM_ActivationStatusType WdgM_ActivationStatus;\r
+ const WdgM_SupervisionCounterType WdgM_ExpectedAliveIndications;\r
+ const WdgM_SupervisionCounterType WdgM_SupervisionReferenceCycle;\r
+ const WdgM_SupervisionCounterType WdgM_FailedSupervisionReferenceCycleTolerance;\r
+ const WdgM_SupervisionCounterType WdgM_MinMargin;\r
+ const WdgM_SupervisionCounterType WdgM_MaxMargin;\r
+}WdgM_SupervisedEntityType;\r
+\r
+typedef struct\r
+{\r
+ uint16 WdgM_SupervisionCycle;\r
+ uint16 WdgM_NumberOfSupervisedEntities;\r
+ uint16 WdgM_ExpiredSupervisionCycleTolerance;\r
+ const WdgM_SupervisedEntityType *WdgM_SupervisedEntityPtr;\r
+ Wdgm_SupervisionType *Wdgm_SupervisionPtr;\r
+}WdgM_ConfigType;\r
+\r
+extern const WdgM_ConfigType WdgMAliveSupervision;\r
+\r
+#endif /* WDGM_CFG_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+\r
+#include "Os.h"\r
+#include "types.h"\r
+#include "counter_i.h"\r
+#include "ext_config.h"\r
+#include "alarm_i.h"\r
+#include <assert.h>\r
+#include <stdlib.h>\r
+#include "hooks.h"\r
+#include "internal.h"\r
+#include "alarm_i.h"\r
+\r
+\r
+/**\r
+ * The system service GetAlarmBase reads the alarm base\r
+ * characteristics. The return value <Info> is a structure in which\r
+ * the information of data type AlarmBaseType is stored.\r
+ *
+ * @param alarm_id Reference to alarm
+ * @param info Reference to structure with constants of the alarm base.
+ * @return
+ */\r
+StatusType GetAlarmBase( AlarmType AlarmId, AlarmBaseRefType Info ) {\r
+ StatusType rv = Oil_GetAlarmBase(AlarmId,Info);\r
+ if (rv != E_OK) {\r
+ goto err;\r
+ }\r
+ OS_STD_END_2(OSServiceId_GetAlarmBase,AlarmId, Info);\r
+}\r
+\r
+StatusType GetAlarm(AlarmType AlarmId, TickRefType Tick) {\r
+ StatusType rv = E_OK;\r
+\r
+ (void)AlarmId;\r
+ (void)Tick;\r
+// TODO: What is this?\r
+\r
+ // Prevent label warning. Remove when proper error handling is implemented.\r
+ if (0) goto err;\r
+\r
+ OS_STD_END_2(OSServiceId_GetAlarm,AlarmId, Tick);\r
+}\r
+\r
+#define COUNTER_MAX(x) (x)->counter->alarm_base.maxallowedvalue\r
+#define COUNTER_MIN_CYCLE(x) (x)->counter->alarm_base.mincycle\r
+#define ALARM_CHECK_ID(x) \\r
+ if( (x) > Oil_GetAlarmCnt()) { \\r
+ rv = E_OS_ID; \\r
+ goto err; \\r
+ }\r
+\r
+\r
+\r
+\r
+\r
+/**\r
+ * The system service occupies the alarm <AlarmID> element.\r
+ * After <increment> ticks have elapsed, the task assigned to the\r
+ * alarm <AlarmID> is activated or the assigned event (only for\r
+ * extended tasks) is set or the alarm-callback routine is called.\r
+ *
+ * @param alarm_id Reference to the alarm element
+ * @param increment Relative value in ticks
+ * @param cycle Cycle value in case of cyclic alarm. In case of single alarms, cycle shall be zero.
+ * @return
+ */\r
+\r
+StatusType SetRelAlarm(AlarmType AlarmId, TickType Increment, TickType Cycle){\r
+ StatusType rv = E_OK;\r
+ alarm_obj_t *a_obj;\r
+\r
+ ALARM_CHECK_ID(AlarmId);\r
+\r
+ a_obj = Oil_GetAlarmObj(AlarmId);\r
+\r
+ os_isr_printf(D_ALARM,"SetRelAlarm id:%d inc:%d cycle:%d\n",AlarmId,Increment,Cycle);\r
+\r
+\r
+ if( (Increment == 0) ||\r
+ (Increment > COUNTER_MAX(a_obj)) ||\r
+ (Cycle < COUNTER_MIN_CYCLE(a_obj)) ||\r
+ (Cycle > COUNTER_MAX(a_obj)) )\r
+ {\r
+ /* See SWS, OS304 */\r
+ rv = E_OS_VALUE;\r
+ goto err;\r
+ }\r
+\r
+ {\r
+\r
+ Irq_Disable();\r
+ if( a_obj->active == 0 ) {\r
+ a_obj->active = 1;\r
+ } else {\r
+ rv = E_OS_STATE;\r
+ goto err;\r
+ }\r
+\r
+ TickType curr_val = a_obj->counter->val;\r
+ TickType left = COUNTER_MAX(a_obj) - curr_val;\r
+\r
+ a_obj->expire_val = (left < Increment ) ?\r
+ (curr_val + Increment) :\r
+ (Increment - curr_val);\r
+ a_obj->cycletime = Cycle;\r
+\r
+ Irq_Enable();\r
+ os_isr_printf(D_ALARM," expire:%d cycle:%d\n",a_obj->expire_val,a_obj->cycletime);\r
+ }\r
+\r
+ OS_STD_END_3(OSServiceId_SetRelAlarm,AlarmId, Increment, Cycle);\r
+}\r
+\r
+StatusType SetAbsAlarm(AlarmType AlarmId, TickType Start, TickType Cycle) {\r
+\r
+ alarm_obj_t *a_p;\r
+ long flags;\r
+ StatusType rv = E_OK;\r
+\r
+ a_p = Oil_GetAlarmObj(AlarmId);\r
+\r
+ if( a_p == NULL ) {\r
+ rv = E_OS_ID;\r
+ goto err;\r
+ }\r
+\r
+ if( (Start > COUNTER_MAX(a_p)) ||\r
+ (Cycle < COUNTER_MIN_CYCLE(a_p)) ||\r
+ (Cycle > COUNTER_MAX(a_p)) )\r
+ {\r
+ /* See SWS, OS304 */\r
+ rv = E_OS_VALUE;\r
+ goto err;\r
+ }\r
+\r
+ Irq_Save(flags);\r
+ if( a_p->active == 1 ) {\r
+ rv = E_OS_STATE;\r
+ goto err;\r
+ }\r
+\r
+ a_p->active = 1;\r
+\r
+ a_p->expire_val = Start;\r
+ a_p->cycletime = Cycle;\r
+ Irq_Restore(flags);\r
+\r
+ os_isr_printf(D_ALARM," expire:%d cycle:%d\n",a_p->expire_val,a_p->cycletime);\r
+\r
+ OS_STD_END_3(OSServiceId_SetAbsAlarm,AlarmId, Start, Cycle);\r
+}\r
+\r
+StatusType CancelAlarm(AlarmType AlarmId) {\r
+ StatusType rv = E_OK;\r
+ alarm_obj_t *a_obj;\r
+ long flags;\r
+\r
+ ALARM_CHECK_ID(AlarmId);\r
+\r
+ a_obj = Oil_GetAlarmObj(AlarmId);\r
+\r
+ Irq_Save(flags);\r
+ if( a_obj->active == 0 ) {\r
+ rv = E_OS_NOFUNC;\r
+ Irq_Restore(flags);\r
+ goto err;\r
+ }\r
+\r
+ a_obj->active = 0;\r
+\r
+ Irq_Restore(flags);\r
+\r
+ OS_STD_END_1(OSServiceId_CancelAlarm,AlarmId);\r
+}\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+/* A steal in an idea from\r
+ * http://blogs.sun.com/nickstephen/entry/some_assembly_required_-_down\r
+ * According to blog original BSD license..\r
+ *\r
+ * Generate assembler from this file( -S option for GNU ).\r
+ * extract the "#defines" with some tool e.g. "sed -n '/#define/p' <asm_file>"\r
+ */\r
+\r
+#include <stddef.h>\r
+\r
+#define DECLARE(sym,val) \\r
+ __asm("#define\t" #sym "\t%0" : : "n" ((val)))\r
+\r
+#include "pcb.h"\r
+#include "sys.h"\r
+#include "kernel.h"\r
+\r
+void asm_foo(void) {\r
+ DECLARE(PCB_STACK_CURR_P, offsetof(pcb_t, stack));\r
+ DECLARE(PCB_ENTRY_P, offsetof(pcb_t, entry));\r
+ DECLARE(SYS_CURR_PCB_P, offsetof(sys_t, curr_pcb));\r
+ DECLARE(SYS_INT_NEST_CNT, offsetof(sys_t, int_nest_cnt));\r
+ DECLARE(SYS_INT_STACK, offsetof(sys_t, int_stack));\r
+\r
+/*\r
+ DECLARE(SYS_HOOK_P, offsetof(sys_t, hooks));\r
+ DECLARE(HOOKS_PRETASK_P, offsetof(structos_conf_global_hooks_s, PreTaskHook));\r
+*/\r
+// DECLARE(SYS_HOOK_POSTTASK_P,offsetof(sys_t, PostTaskHook));\r
+}\r
+\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+/*\r
+ * Just a sample file to generate some assembler constructs if you are\r
+ * really bad at it.\r
+ *\r
+ * Add it to makefile and then examin it with objdump.\r
+ *\r
+ * Example:\r
+ * ${CROSS_COMPILE}objdump -S system/kernel/obj_et_stm32_stamp/asm_sample.o\r
+ *\r
+ */\r
+\r
+void __attribute__((__interrupt__)) interrupt( void ) {\r
+\r
+}\r
+\r
+void func1( int a ) {\r
+\r
+}\r
+\r
+int func2( void ) {\r
+ int a;\r
+ a = 3;\r
+\r
+ return 2;\r
+}\r
+\r
+\r
+void func( void ) {\r
+ func1(5);\r
+ func2();\r
+}\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+#include "Os.h"\r
+#include "kernel.h"\r
+#include "ext_config.h"\r
+#include <assert.h>\r
+#include <string.h>\r
+\r
+\r
+/* Queued message\r
+ * The messages are put in a queue. Copied to the destination...\r
+ *\r
+ * Unqueued message\r
+ * Latest message in queue. Put the message in a container ref by message_id.\r
+ * It's just a copy. The message can be read by "anyone" and as many times as you\r
+ * would like\r
+ *\r
+ * Add new functions ??\r
+ * SendMessageNoCopy( ) .. must have GetMsgApa().. this gets to be a resource lock... hmm\r
+ *\r
+ *\r
+ *\r
+ */\r
+\r
+StatusType SendMessage( MessageType message_id, ApplicationDataRef dataRef ) {\r
+\r
+\r
+ message_obj_t *msg;\r
+\r
+ // Is the message valid ?\r
+ if( message_id > Oil_GetMessageCnt() ) {\r
+ // TODO: Add error hook here\r
+ return E_COM_ID;\r
+ }\r
+\r
+ if( msg->property != SEND_STATIC_INTERNAL ) {\r
+ // TODO: Add error hook here\r
+ return E_COM_ID;\r
+ }\r
+\r
+ // Copy the data to interal buffers\r
+ msg = Oil_GetMessage(message_id);\r
+\r
+ // copy data\r
+ memcpy(msg->data,dataRef,msg->data_size);\r
+\r
+\r
+#if 0\r
+ // Is it a queue message?\r
+ switch( msg->notification ) {\r
+ case MESSAGE_NOTIFICATION_ACTION_ACTIVATETASK:\r
+ // TODO: Is this activatetask ???\r
+ break;\r
+ case MESSAGE_NOTIFICATION_ACTION_SETEVENT:\r
+ // TODO:\r
+ break;\r
+ case MESSAGE_NOTIFICATION_ACTION_NONE:\r
+ break;\r
+ default:\r
+ assert(0);\r
+ break;\r
+ }\r
+#endif\r
+\r
+ return E_OK;\r
+}\r
+\r
+StatusType ReceiveMessage( MessageType message_id, ApplicationDataRef dataRef ) {\r
+ message_obj_t *msg;\r
+ // Check if valid\r
+\r
+ // Copy from container to dataRef\r
+ msg = Oil_GetMessage(message_id);\r
+ memcpy(dataRef,msg->data,msg->data_size);\r
+\r
+ return E_OK;\r
+}\r
+\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+#include "Os.h"\r
+#include "types.h"\r
+#include "counter_i.h"\r
+#include "ext_config.h"\r
+#include "alarm_i.h"\r
+#include <assert.h>\r
+#include <stdlib.h>\r
+#include "hooks.h"\r
+#include "sched_table_i.h"\r
+#include "internal.h"\r
+\r
+#define MIN(_x,_y) (((_x) < (_y)) ? (_x) : (_y))\r
+#define MAX(_x,_y) (((_x) > (_y)) ? (_x) : (_y))\r
+\r
+\r
+#define COUNTER_MAX(x) (x)->counter->alarm_base.maxallowedvalue\r
+\r
+#define COUNTER_STD_END \\r
+ goto ok; \\r
+ err: \\r
+ ERRORHOOK(rv); \\r
+ ok: \\r
+ return rv;\r
+\r
+\r
+/* Accessor functions */\r
+static inline Stbl_AdjustableExpPointType *getAdjExpPoint( sched_table_t *stblPtr ) {\r
+ return &stblPtr->adjExpPoint;\r
+}\r
+\r
+static inline struct sched_table_autostart_s *getAutoStart( sched_table_t *stblPtr ) {\r
+ return &stblPtr->autostart;\r
+}\r
+\r
+static inline struct sched_table_sync_s *getSync( sched_table_t *stblPtr ) {\r
+ return &stblPtr->sync;\r
+}\r
+\r
+\r
+/**\r
+ *
+ * @param curr
+ * @param max
+ * @param add
+ * @return
+ */\r
+static TickType os_calc_modulo( TickType curr, TickType max, TickType add ) {\r
+ TickType diff = max - curr;\r
+// return (diff > add ) ? (curr + add) :\r
+// (add - curr);\r
+ return (add>diff) ? (add-diff) : (curr+add);\r
+}\r
+\r
+/**\r
+ *
+ * @param a_obj
+ */\r
+static void AlarmProcess( alarm_obj_t *a_obj ) {\r
+ if( a_obj->cycletime == 0 ) {\r
+ a_obj->active = 0;\r
+ } else {\r
+ // Calc new expire value..\r
+ a_obj->expire_val = os_calc_modulo( a_obj->expire_val,\r
+ COUNTER_MAX(a_obj),\r
+ a_obj->cycletime);\r
+ }\r
+}\r
+\r
+static void check_alarms( counter_obj_t *c_p ) {\r
+ alarm_obj_t *a_obj;\r
+\r
+ SLIST_FOREACH(a_obj,&c_p->alarm_head,alarm_list) {\r
+ if( a_obj->active && (c_p->val == a_obj->expire_val) ) {\r
+ /* Check if the alarms have expired */\r
+ os_isr_printf(D_ALARM,"expired %s id:%d val:%d\n",\r
+ a_obj->name,\r
+ a_obj->counter_id,\r
+ a_obj->expire_val);\r
+\r
+ switch( a_obj->action.type ) {\r
+ case ALARM_ACTION_ACTIVATETASK:\r
+ if( ActivateTask(a_obj->action.task_id) != E_OK ) {\r
+ assert(0);\r
+ }\r
+ AlarmProcess(a_obj);\r
+ break;\r
+ case ALARM_ACTION_SETEVENT:\r
+ if( SetEvent(a_obj->action.task_id,a_obj->action.event_id) != E_OK ) {\r
+ // TODO: Check what to do here..\r
+ assert(0);\r
+ }\r
+ AlarmProcess(a_obj);\r
+ break;\r
+ case ALARM_ACTION_ALARMCALLBACK:\r
+ /* TODO: not done */\r
+ break;\r
+ case ALARM_ACTION_INCREMENTCOUNTER:\r
+ /* Huh,, recursive....*/\r
+ IncrementCounter(a_obj->action.counter_id);\r
+ break;\r
+ default:\r
+ assert(0);\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * Go through the schedule tables connected to this counter\r
+ *
+ * @param c_p Pointer to counter object
+ */\r
+static void check_stbl( counter_obj_t *c_p ) {\r
+ sched_table_t *sched_obj;\r
+\r
+ /* Iterate through the schedule tables */\r
+ SLIST_FOREACH(sched_obj,&c_p->sched_head,sched_list) {\r
+\r
+ if( sched_obj->state == SCHEDULETABLE_STOPPED ) {\r
+ continue;\r
+ }\r
+\r
+ if( sched_obj->sync.syncStrategy == IMPLICIT ) {\r
+ // ....\r
+\r
+ } else {\r
+ int adj;\r
+ // Handle EXPLICIT\r
+ if( sched_obj->sync.deviation > 0 ) {\r
+ // The sync counter was set back ==\r
+ // we have more time to complete the table\r
+ adj = MIN(sched_obj->sync.deviation, getAdjExpPoint(sched_obj)->maxAdvance );\r
+ sched_obj->sync.deviation -= adj;\r
+\r
+ } else if( sched_obj->sync.deviation < 0 ) {\r
+ // The sync counter was set forward ==\r
+ // we have less time to complete the table\r
+ adj = MIN((-sched_obj->sync.deviation), getAdjExpPoint(sched_obj)->maxRetard);\r
+ sched_obj->sync.deviation -= adj;\r
+\r
+ } else {\r
+ // all is well\r
+ sched_obj->state = SCHEDULETABLE_RUNNING_AND_SYNCHRONOUS;\r
+ }\r
+ }\r
+\r
+ /* Check if the expire point have been hit */\r
+ if( (sched_obj->state == SCHEDULETABLE_RUNNING ||\r
+ SCHEDULETABLE_RUNNING_AND_SYNCHRONOUS ) &&\r
+ (c_p->val >= sched_obj->expire_val) ) {\r
+ sched_action_t * action;\r
+\r
+ action = SA_LIST_GET(&sched_obj->action_list,sched_obj->expire_curr_index);\r
+\r
+ switch( action->type ) {\r
+ case SCHEDULE_ACTION_ACTIVATETASK:\r
+ ActivateTask(action->task_id);\r
+ break;\r
+\r
+ case SCHEDULE_ACTION_SETEVENT:\r
+ SetEvent( action->task_id, action->event_id);\r
+ break;\r
+\r
+ default:\r
+ assert(0);\r
+ }\r
+ // Calc new expire val\r
+ os_stbl_calc_expire(sched_obj);\r
+ }\r
+\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * Increment a counter. Checks for wraps.\r
+ *
+ * @param counter Ptr to a counter object
+ */\r
+static void IncCounter( counter_obj_t *counter ) {\r
+ // Check for wrap of type\r
+ if( (counter->val+1) < (counter->val) ) {\r
+ counter->val = 0; // This wraps\r
+ } else {\r
+ if( counter->val > counter->alarm_base.maxallowedvalue ) {\r
+ counter->val = 0;\r
+ } else {\r
+ counter->val++;\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ *
+ * @param counter_id
+ * @return
+ */\r
+\r
+StatusType IncrementCounter( CounterType counter_id ) {\r
+ StatusType rv = E_OK;\r
+\r
+ /* Check the alarms associated with this timer */\r
+ counter_obj_t *counter;\r
+ counter = Oil_GetCounter(counter_id);\r
+\r
+ /* Check param */\r
+\r
+ if( ( counter->type != COUNTER_TYPE_SOFT ) ||\r
+ ( counter_id >= Oil_GetCounterCnt() ) ) {\r
+ rv = E_OS_ID;\r
+ goto err;\r
+ }\r
+\r
+ IncCounter(counter);\r
+\r
+ /* TODO: the other alarm_base.xxx values are still not done */\r
+ check_alarms(counter);\r
+ check_stbl(counter);\r
+\r
+ COUNTER_STD_END;\r
+}\r
+\r
+\r
+TickType GetCounterValue_( counter_obj_t *c_p ) {\r
+ if( c_p->type == COUNTER_TYPE_HARD ) {\r
+ /* Grab the GPT */\r
+#if 0\r
+ // TODO: Move this outside the OS??\r
+ // Is this the HW value??\r
+ // No good way to check if something went wrong here. Can check for != 0\r
+ // but that can really happen\r
+ return (TickType)Gpt_GetTimeElapsed(c_p->driver.OsGptChannelRef );\r
+#else\r
+ return Frt_GetTimeElapsed();\r
+#endif\r
+ } else {\r
+ return c_p->val;\r
+ }\r
+}\r
+\r
+\r
+StatusType GetCounterValue( CounterType counter_id , TickRefType tick_ref)\r
+{\r
+ counter_obj_t *counter;\r
+ counter = Oil_GetCounter(counter_id);\r
+\r
+ *tick_ref = GetCounterValue_(counter);\r
+ return E_OK;\r
+}\r
+\r
+StatusType GetElapsedCounterValue( CounterType counter_id, TickRefType val, TickRefType elapsed_val)\r
+{\r
+ return E_OK;\r
+}\r
+\r
+/*\r
+ * The OsTick():\r
+ * 1. The Decrementer is setup by Frt_Start(period_ticks)\r
+ * 2. Frt_Init() setup INTC[7] to trigger OsTick\r
+ * 3. OsTick() then increment counter 0\r
+ * ( COUNTER_ID_OS_TICK = OS_TICK_COUNTER )\r
+ */\r
+\r
+/*\r
+ * Non-Autosar stuff\r
+ */\r
+\r
+void OsTick( void ) {\r
+ counter_obj_t *c_p = Oil_GetCounter(OS_TICK_COUNTER);\r
+\r
+ os_sys.tick++;\r
+\r
+ IncCounter(c_p);\r
+\r
+// os_sys.tick = c_p->val;\r
+\r
+ check_alarms(c_p);\r
+ check_stbl(c_p);\r
+}\r
+\r
+#if 0\r
+void OsIdle( void ) {\r
+ for(;;);\r
+}\r
+#endif\r
+\r
+TickType GetOsTick( void ) {\r
+ return get_os_tick();\r
+}\r
+\r
+#if 0\r
+StatusType InitCounter(AlarmType alarm_id ) {\r
+\r
+ return E_OK;\r
+}\r
+\r
+StatusType StartCounter( AlarmType alarm_id ) {\r
+ return E_OK;\r
+}\r
+#endif\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*\r
+ * create.c\r
+ *\r
+ * Created on: 2009-jan-16\r
+ * Author: mahi\r
+ */\r
+\r
+#include <stdint.h>\r
+#include <stdlib.h>\r
+#include <assert.h>\r
+#include <sys/queue.h>\r
+#include <string.h>\r
+#include "sys.h"\r
+#include "pcb.h"\r
+#include "Os.h"\r
+\r
+#define os_alloc(_x) malloc(_x)\r
+\r
+pcb_t * os_alloc_new_pcb( void ) {\r
+ void *h = os_alloc(sizeof(pcb_t));\r
+ memset(h,0,sizeof(pcb_t));\r
+ assert(h!=NULL);\r
+ return h;\r
+}\r
+\r
+#if 0\r
+typedef void (*Os_IsrEntryType)(void);\r
+\r
+\r
+typedef Os_IsrInfo_s {\r
+ Os_IsrEntryType entry;\r
+ uint32_t vector;\r
+ uint8_t priority;\r
+} Os_IsrInfoType;\r
+#endif\r
+\r
+\r
+extern TaskType os_add_task( pcb_t *pcb );\r
+\r
+static uint8 stackTop = 0x42;\r
+\r
+TaskType Os_CreateIsr( void (*entry)(void ), uint8_t prio, const char *name )\r
+{\r
+ pcb_t *pcb = os_alloc_new_pcb();\r
+ strncpy(pcb->name,name,TASK_NAME_SIZE);\r
+ pcb->vector = -1;\r
+ pcb->prio = prio;\r
+ pcb->proc_type = PROC_ISR2;\r
+ pcb->state = ST_SUSPENDED;\r
+ pcb->entry = entry;\r
+ pcb->stack.top = &stackTop;\r
+\r
+ return os_add_task(pcb);\r
+}\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+#include "Os.h"\r
+#include "pcb.h"\r
+#include "sys/queue.h"\r
+#include "sys.h"\r
+#include <stdlib.h>\r
+#include "internal.h"\r
+#include "swap.h"\r
+#include "task_i.h"\r
+#include "hooks.h"\r
+\r
+#define VALIDATE_W_RV(_exp,_rv) \\r
+ if( (_exp) ) { \\r
+ ERRORHOOK(_rv); \\r
+ return _rv; \\r
+ }\r
+\r
+\r
+/**\r
+ * The state of the calling task is set to waiting, unless at least one\r
+ * of the events specified in <Mask> has already been set.\r
+ *\r
+ * This call enforces rescheduling, if the wait condition occurs. If\r
+ * rescheduling takes place, the internal resource of the task is\r
+ * released while the task is in the waiting state.\r
+ * This service shall only be called from the extended task owning\r
+ * the event.\r
+ *
+ * @param Mask Mask of the events waited for
+ * @return
+ */\r
+\r
+StatusType WaitEvent( EventMaskType Mask ) {\r
+\r
+ pcb_t *curr_pcb = get_curr_pcb();\r
+ StatusType rv = E_OK;\r
+\r
+ /* Remove from ready queue */\r
+ Irq_Disable();\r
+\r
+ // Reschedule if mask not set already\r
+ if( !(curr_pcb->ev_set & Mask) ) {\r
+\r
+ curr_pcb->ev_wait = Mask;\r
+ os_pcb_make_waiting(curr_pcb);\r
+ {\r
+ pcb_t *pcb;\r
+ pcb = os_find_top_prio_proc();\r
+ assert(pcb!=NULL);\r
+ os_swap_context(curr_pcb,pcb);\r
+ }\r
+ }\r
+\r
+ Irq_Enable();\r
+\r
+ // The following line disables the unused label warning. Remove when\r
+ // proper error handling is implemented.\r
+ if (0) goto err;\r
+\r
+ OS_STD_END_1(OSServiceId_WaitEvent,Mask);\r
+}\r
+\r
+/**\r
+ * The events of task <TaskID> are set according to the event\r
+ * mask <Mask>. Calling SetEvent causes the task <TaskID> to\r
+ * be transferred to the ready state, if it was waiting for at least\r
+ * one of the events specified in <Mask>.\r
+ *
+ * @param TaskID - Reference to the task for which one or several events are to be set.
+ * @param Mask - Mask of the events to be set
+ * @return
+ */\r
+\r
+StatusType SetEvent( TaskType TaskID, EventMaskType Mask ) {\r
+ StatusType rv = E_OK;\r
+ pcb_t *dest_pcb;\r
+\r
+ dest_pcb = os_get_pcb(TaskID);\r
+ Irq_Disable();\r
+\r
+ if( (dest_pcb->state & ST_SUSPENDED ) ) {\r
+ rv = E_OS_STATE;\r
+ goto err;\r
+ }\r
+\r
+ if( dest_pcb->proc_type != PROC_EXTENDED ) {\r
+ rv = E_OS_ACCESS;\r
+ goto err;\r
+ }\r
+\r
+ // If at least one of the events match, taskID from waiting to ready\r
+ // (if not already)\r
+ if( Mask & dest_pcb->ev_wait ) {\r
+ os_pcb_make_ready(dest_pcb);\r
+ }\r
+\r
+ dest_pcb->ev_set |= Mask;\r
+ Irq_Enable();\r
+\r
+ OS_STD_END_2(OSServiceId_SetEvent,TaskID, Mask);\r
+}\r
+\r
+StatusType GetEvent( TaskType TaskId, EventMaskRefType Mask) {\r
+\r
+ pcb_t *dest_pcb;\r
+ StatusType rv = E_OK;\r
+\r
+ dest_pcb = os_get_pcb(TaskId);\r
+\r
+ VALIDATE_W_RV(dest_pcb->state & ST_SUSPENDED,E_OS_STATE);\r
+ VALIDATE_W_RV(dest_pcb->proc_type != PROC_EXTENDED,E_OS_ACCESS);\r
+\r
+ *Mask = dest_pcb->ev_set;\r
+\r
+ if (0) goto err;\r
+\r
+ OS_STD_END_2(OSServiceId_GetEvent,TaskId, Mask);\r
+}\r
+\r
+\r
+StatusType ClearEvent( EventMaskType Mask) {\r
+ StatusType rv = E_OK;\r
+ pcb_t *pcb;\r
+ pcb = get_curr_pcb();\r
+ pcb->ev_set &= ~Mask;\r
+\r
+ if (0) goto err;\r
+\r
+ OS_STD_END_1(OSServiceId_ClearEvent,Mask);\r
+}\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef ALARM_I_H_\r
+#define ALARM_I_H_\r
+\r
+#include "counter_i.h"\r
+\r
+struct counter_obj_s;\r
+\r
+typedef enum alarm_action_type_e {\r
+ ALARM_ACTION_ACTIVATETASK=0,\r
+ ALARM_ACTION_SETEVENT,\r
+ ALARM_ACTION_ALARMCALLBACK, /* Only class 1 */\r
+ ALARM_ACTION_INCREMENTCOUNTER, /* SWS OS302 */\r
+} alarm_action_type_t;\r
+\r
+\r
+typedef struct alarm_action_s {\r
+ alarm_action_type_t type;\r
+ TaskType task_id;\r
+ EventMaskType event_id;\r
+ CounterType counter_id;\r
+} alarm_action_t;\r
+\r
+typedef struct alarm_autostart_s {\r
+ _Bool active;\r
+ uint32 alarmtime;\r
+ uint32 cycletime;\r
+ uint32 appmode_mask;\r
+} alarm_autostart_t;\r
+\r
+typedef struct alarm_obj_s {\r
+\r
+ char name[16];\r
+ /* Reference to counter */\r
+ struct counter_obj_s *counter;\r
+\r
+ CounterType counter_id;\r
+ /* cycle, 0 = no cycle */\r
+ uint32 alarmtime;\r
+ uint32 cycletime;\r
+ uint32 appmode_mask;\r
+\r
+ alarm_autostart_t autostart;\r
+\r
+ uint32 app_mask;\r
+\r
+ /* if the alarm is active or not */\r
+ _Bool active;\r
+ /* expire value */\r
+ uint32 expire_val;\r
+\r
+\r
+ // Action attributes when alarm expires.\r
+ alarm_action_t action;\r
+/*\r
+ alarm_action_type_t action_type;\r
+ TaskType action_pid;\r
+ EventMaskType action_event;\r
+ CounterType action_counter;\r
+*/\r
+ /* List of alarms connected to the same counter */\r
+ SLIST_ENTRY(alarm_obj_s) alarm_list;\r
+ /* TODO: OS242, callback in scalability class 1 only..*/\r
+#if 0\r
+ void (*cb)(void);\r
+#endif\r
+} alarm_obj_t;\r
+\r
+\r
+\r
+#endif /*ALARM_I_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*\r
+ * Porting interface. Should really be called port.h or something.\r
+\r
+ * The routines below + interrupt handing in Mcu_IntXX.c, should\r
+ * be all that needs to be implemented for a new port.
+ */\r
+\r
+#ifndef ARCH_H_\r
+#define ARCH_H_\r
+
+#define STACK_PATTERN 0x42
+\r
+/**\r
+ * Swap context.\r
+ * Sets the current pcb\r
+ *\r
+ * @param old - old ptr to pcb\r
+ * @return
+ */\r
+void os_arch_swap_context(void *old,void *new);\r
+\r
+/**\r
+ * Swap context for the first time for a task\r
+ *\r
+ * The only way to call this function right now is to:\r
+ * os_swap_context_to(NULL,<pcb>);\r
+ */\r
+void os_arch_swap_context_to(void *old,void *new);\r
+\r
+/**\r
+ * Setup a pcb before use.\r
+ *\r
+ * This function should setup:\r
+ * - context marker( SC_PATTERN, LC_PATTERN )\r
+ * - Arch specific register setup\r
+ * - Check that the stack is suffient for the arch\r
+ * - More...\r
+ *\r
+ * @param pcb Ptr to pcb
+ */\r
+void os_arch_setup_context( pcb_t *pcb );\r
+\r
+/**\r
+ * Get current stack pointer\r
+ *\r
+ * @return current stack pointer
+ */\r
+void *os_arch_get_stackptr( void );\r
+\r
+/**\r
+ * Initialize the hardware.\r
+ * This could be initialization of:\r
+ * - interrupt controller\r
+ * - timers\r
+ */\r
+void os_arch_init( void );\r
+\r
+/**\r
+ * Function that is used when task entry is called for the\r
+ * first time. For ports that don't support user mode it\r
+ * should just call entry entry() function of the current task.\r
+ *\r
+ * When user mode is supported a switch to user mode must be done\r
+ * in some way. A trap maybe?\r
+ */\r
+void os_arch_first_call( void );\r
+\r
+\r
+/**\r
+ * Get the small context size\r
+ *\r
+ * @return The small context size in bytes
+ */\r
+unsigned int os_arch_get_sc_size( void );\r
+
+#if 0\r
+\r
+void *os_arch_get_stack_usage( pcb_t * );\r
+\r
+_Bool os_arch_stack_endmark_ok( pcb_t *);
+#endif
+
+static inline _Bool os_arch_stack_endmark_ok( pcb_t *pcb ) {
+ uint8_t *end = pcb->stack.top;
+ return ( *end == STACK_PATTERN);
+}
+
+
+static inline void *os_arch_get_stack_usage( pcb_t *pcb ) {
+
+ uint8_t *p = pcb->stack.curr;
+ uint8_t *end = pcb->stack.top;
+
+ while( (*end == STACK_PATTERN) && (end<p)) {
+ end++;
+ }
+ return (void *)end;
+}
+
+\r
+\r
+#endif /*ARCH_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef COUNTER_I_H_\r
+#define COUNTER_I_H_\r
+\r
+#include "Os.h"\r
+#include "kernel.h"\r
+#include <sys/queue.h>\r
+\r
+#define COUNTER_TYPE_HARD 0\r
+#define COUNTER_TYPE_SOFT 1\r
+\r
+#define COUNTER_UNIT_TICKS 0\r
+#define COUNTER_UNIT_NANO 1\r
+\r
+/*-----------------------------------------------------------------*/\r
+typedef struct counter_obj_s {\r
+ // counter id( TODO: remove ?? I use index here )\r
+// uint32_t cid;\r
+ char name[16];\r
+ // hardware or software counter, SWS OS255\r
+ _Bool type;\r
+ // Ticks or nano, SWS OS331\r
+ _Bool unit;\r
+ // The counter value ( if software counter )\r
+ uint32_t val;\r
+ // Application mask, SWS OS317\r
+ uint32_t app_mask;\r
+ // hmm, strange to call it alarm base.... but see spec.\r
+ AlarmBaseType alarm_base;\r
+ /* Used only if we configure a GPT timer as os timer */\r
+ OsDriver driver;\r
+ /* List of alarms this counter is connected to\r
+ * Overkill ??? Could have list of id's here, but easier to debug this way*/\r
+ SLIST_HEAD(slist,alarm_obj_s) alarm_head;\r
+ /* List of scheduletable connected to this counter */\r
+ SLIST_HEAD(sclist,sched_table_s) sched_head;\r
+} counter_obj_t;\r
+\r
+TickType GetCounterValue_( counter_obj_t *c_p );\r
+\r
+#endif /*COUNTER_I_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef DEBUG_H_\r
+#define DEBUG_H_\r
+\r
+#include <stdio.h>\r
+\r
+#ifdef USE_DBG_PRINTF\r
+\r
+#define DBG_T32_TERMINAL 1\r
+// Swap hook\r
+#define DGB_HOOK_SWAP 1\r
+\r
+#define DBG_START_OS 1\r
+\r
+#define DBG_EXCEPTION 1\r
+\r
+// C99, see gcc manual for more info if no args..\r
+// WARNING!! This eats lots and lots of stack, about 500bytes ??\r
+\r
+//#defineos_printf(format,...) printf(format,__VA_ARGS__)\r
+#define os_printf(format,...) simple_printf(format,__VA_ARGS__)\r
+// #define os_printf(format,...) iprintf(format,__VA_ARGS__)\r
+\r
+// Macro's that don't take the whole stack...\r
+// #define os_print_hex()\r
+// #define os_print(char *str);\r
+\r
+#else\r
+\r
+#define os_printf(format,...)\r
+\r
+#endif\r
+\r
+\r
+\r
+\r
+#endif /*DEBUG_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef EXT_CONFIG_H_\r
+#define EXT_CONFIG_H_\r
+\r
+/* Created in Oil_Config */\r
+struct pcb_s;\r
+struct alarm_obj_s;\r
+struct counter_obj_s;\r
+struct sched_table_s;\r
+//struct app_s;\r
+struct rom_app_s;\r
+struct resource_obj_s;\r
+struct rom_app_s;\r
+struct message_obj_s;\r
+//extern struct pcb_s pcb_list[];\r
+//extern struct app_s app_list[];\r
+//extern struct rom_app_s rom_app_list[];\r
+\r
+int Oil_GetApplCnt(void);\r
+struct rom_app_s *Oil_GetApplObj( ApplicationType application_id );\r
+int Oil_GetTaskCnt(void);\r
+void *Oil_GetIdleProcStack(void);\r
+int Oil_GetResourceCnt(void);\r
+StatusType Oil_GetAlarmBase(AlarmType alarm_id, AlarmBaseRefType info);\r
+uint32 Oil_GetAlarmCnt(void);\r
+struct alarm_obj_s *Oil_GetAlarmObj( AlarmType alarm_id );\r
+struct counter_obj_s *Oil_GetCounter(CounterType);\r
+uint32 Oil_GetCounterCnt(void );\r
+uint32 Oil_GetSchedCnt( void );\r
+struct sched_table_s *Oil_GetSched( ScheduleTableType sched_id );\r
+uint32 Oil_GetServiceCnt( void ) ;\r
+struct resource_obj_s *Oil_GetResource( ResourceType resource );\r
+\r
+struct message_obj_s *Oil_GetMessage(MessageType message_id);\r
+uint32 Oil_GetMessageCnt(void );\r
+\r
+#endif /*EXT_CONFIG_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef HOOKS_H_\r
+#define HOOKS_H_\r
+\r
+#include "sys.h"\r
+#include "pcb.h"\r
+#include "kernel.h"\r
+\r
+/* Called for sequence of error hook calls in case a service\r
+ * does not return with E_OK. Note that in this case the general error hook and the OS-\r
+ * Application specific error hook are called.\r
+ */\r
+\r
+#define ERRORHOOK(x) \\r
+ if( os_sys.hooks->ErrorHook != NULL ) { \\r
+ os_sys.hooks->ErrorHook(x); \\r
+ }\r
+\r
+\r
+#define PRETASKHOOK() \\r
+ if( os_sys.hooks->PreTaskHook != NULL ) { \\r
+ os_sys.hooks->PreTaskHook(); \\r
+ }\r
+\r
+#define POSTTASKHOOK() \\r
+ if( os_sys.hooks->PostTaskHook != NULL ) { \\r
+ os_sys.hooks->PostTaskHook(); \\r
+ }\r
+\r
+\r
+\r
+#endif /*HOOKS_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef INTERNAL_H_\r
+#define INTERNAL_H_\r
+\r
+#include <assert.h>\r
+#include "Ramlog.h"\r
+\r
+\r
+extern uint32 os_dbg_mask;\r
+\r
+/*\r
+ * 0 master print normal, 1-print\r
+ * 1 master print isr 1-print\r
+ * 2 normal 0-stdout,1-ramlog\r
+ * 3 isr 0-stdout,\r
+ *\r
+ * 16 task_low\r
+ * 17 task high\r
+ *\r
+ * 20 alarm\r
+ *\r
+ *\r
+ * So when debugging the kernel using the ISS you want to use:\r
+ * 0xB\r
+ *\r
+ * Ramlog all the way:\r
+ * 0x7\r
+ */\r
+\r
+extern uint32 os_dbg_mask;\r
+\r
+#define STR_TASK "OS_TASK"\r
+#define STR_ALARM "OS_ALARM"\r
+#define STR_STBL "OS_STBL"\r
+\r
+\r
+#define os_dbg_printf(format,...) \\r
+ if( os_dbg_mask & OS_DBG_MASTER_PRINT ) { \\r
+ simple_printf(format,## __VA_ARGS__ ); \\r
+ }\r
+\r
+#define os_dbg_isr_printf(format,...) \\r
+ if( os_dbg_mask & OS_DBG_ISR_MASTER_PRINT ) { \\r
+ simple_printf(format,## __VA_ARGS__ ); \\r
+ }\r
+\r
+#define os_isr_printf(_mask,format,...) \\r
+ if( (os_dbg_mask & OS_DBG_ISR_MASTER_PRINT) && ((_mask)>255 ) ) { \\r
+ if( os_dbg_mask & D_ISR_STDOUT ) { \\r
+ simple_printf("[%08d] : ",GetOsTick()); \\r
+ simple_printf(format,## __VA_ARGS__ ); \\r
+ } else { \\r
+ ramlog_printf("[%08d] : ",GetOsTick()); \\r
+ ramlog_printf(format,## __VA_ARGS__ ); \\r
+ } \\r
+ }\r
+\r
+#define os_std_printf(_mask,format,...) \\r
+ if( (os_dbg_mask & OS_DBG_MASTER_PRINT) && ((_mask)>255 ) ) { \\r
+ if( os_dbg_mask & D_STDOUT) { \\r
+ simple_printf("[%08d] : ",GetOsTick()); \\r
+ simple_printf(format,## __VA_ARGS__ ); \\r
+ } else { \\r
+ ramlog_printf("[%08d] : ",GetOsTick()); \\r
+ ramlog_printf(format,## __VA_ARGS__ ); \\r
+ } \\r
+ }\r
+\r
+#if 0\r
+#define os_isr_printf(D_TASK,format,...) \\r
+ if( (os_dbg_mask | OS_DBG_ISR_MASTER_PRINT | OS_DBG_TASK) \\r
+ == os_dbg_mask ) { \\r
+ simple_printf("[%08d] %s: ",GetOsTick(), STR_TASK); \\r
+ simple_printf(format,## __VA_ARGS__ ); \\r
+ }\r
+\r
+#define os_dbg_task_printf(format,...) \\r
+ if( (os_dbg_mask | OS_DBG_MASTER_PRINT | OS_DBG_TASK) \\r
+ == os_dbg_mask ) { \\r
+ simple_printf("[%08d] %s: ",GetOsTick(), STR_TASK); \\r
+ simple_printf(format,## __VA_ARGS__ ); \\r
+ }\r
+#endif\r
+\r
+#if 0\r
+static inline void Irq_Disable( void ) {\r
+ Irq_Disable();\r
+}\r
+\r
+static inline void Irq_Enable( void ) {\r
+ Irq_Enable();\r
+}\r
+#endif\r
+\r
+\r
+#if 0\r
+#define os_dbg_m_printf(_x,format,...) \\r
+ if( (os_dbg_mask | OS_DBG_ISR_MASTER_PRINT | (_x)) == os_dbg_mask) { \\r
+ simple_printf(format,## __VA_ARGS__ ); \\r
+ }\r
+#endif\r
+\r
+/*\r
+ * PCB manipulating functions\r
+ */\r
+\r
+static inline procid_t get_curr_pid( void ) {\r
+ return os_sys.curr_pcb->pid;\r
+}\r
+\r
+static inline pcb_t *get_curr_pcb( void ) {\r
+ return os_sys.curr_pcb;\r
+}\r
+\r
+static inline void set_curr_pcb( pcb_t *pcb ) {\r
+ os_sys.curr_pcb = pcb;\r
+}\r
+\r
+static inline _Bool is_idle_task( pcb_t *pcb ){\r
+ return (pcb->pid == 0);\r
+}\r
+\r
+static inline procid_t get_curr_prio( void ){\r
+ return os_sys.curr_pcb->prio;\r
+}\r
+\r
+static inline TickType get_os_tick( void ) {\r
+ return os_sys.tick;\r
+}\r
+\r
+static inline app_t *get_curr_application( void ) {\r
+ return get_curr_pcb()->application;\r
+}\r
+\r
+static inline uint32_t get_curr_application_id( void ) {\r
+ return get_curr_pcb()->application->application_id;\r
+}\r
+\r
+static inline struct resource_obj_s *os_get_resource_int_p( void ) {\r
+ return get_curr_pcb()->resource_int_p;\r
+}\r
+\r
+/*\r
+ * Misc
+ */\r
+\r
+static inline uint32_t os_task_nr_to_mask( uint32_t nr ) {\r
+ return (1<<nr);\r
+}\r
+\r
+// task_i.c\r
+pcb_t *os_find_top_prio_proc( void );\r
+pcb_t *os_find_task( TaskType tid );\r
+\r
+// resource.c\r
+void os_resource_get_internal(void );\r
+void os_resource_release_internal( void );\r
+// Create.c\r
+pcb_t * os_alloc_new_pcb( void );\r
+\r
+\r
+void OsTick( void );\r
+\r
+void *Os_Isr( void *stack, void *pcb_p );\r
+\r
+\r
+#endif /*INTERNAL_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*\r
+ * kernel.h\r
+ *\r
+ * Created on: 23 aug 2009\r
+ * Author: mahi\r
+ */\r
+\r
+#ifndef KERNEL_H_\r
+#define KERNEL_H_\r
+\r
+#include <sys/queue.h>\r
+#include "Os.h"\r
+#include "counter_i.h"\r
+#include "alarm_i.h"\r
+#include "sched_table_i.h"\r
+\r
+typedef void ( * trusted_func_t)( TrustedFunctionIndexType , TrustedFunctionParameterRefType );\r
+\r
+/*-----------------------------------------------------------------*/\r
+/* Global Hooks( non-application specific ) */\r
+\r
+typedef struct os_conf_global_hooks_s {\r
+ ProtectionHookType ProtectionHook;\r
+ StartupHookType StartupHook;\r
+ ShutdownHookType ShutdownHook;\r
+ ErrorHookType ErrorHook;\r
+ PreTaskHookType PreTaskHook;\r
+ PostTaskHookType PostTaskHook;\r
+} os_conf_global_hooks_t;\r
+\r
+\r
+\r
+/* Application hooks */\r
+/*\r
+typedef struct os_application_hooks_s {\r
+ void (*StartupHook)( void );\r
+ void (*ShutdownHook)( Std_ReturnType Error );\r
+ void (*ErrorHook)( Std_ReturnType Error );\r
+} os_application_hooks_t;\r
+*/\r
+\r
+/*-----------------------------------------------------------------*/\r
+\r
+/*\r
+ * The only information about the COM that is valid is\r
+ * in the COM specification ..SWS_COM.pdf.\r
+ *\r
+ * The most important requirements are COM010 and COM013\r
+ *\r
+ * Com_Init()\r
+ * Com_DeInit()\r
+ *\r
+ * No error hooks..\r
+ * No. GetMessageStatus()\r
+ * No. SendZeroMessage()\r
+ * No. SendDynamicMessage(), RecieveDynamicMessage()\r
+ *\r
+ * See http://www.altium.com/files/AltiumDesigner6/LearningGuides/GU0102%20TSK51x%20TSK52x%20RTOS.pdf\r
+ *\r
+ * Yes. SendMessage()\r
+ *\r
+ * */\r
+\r
+typedef enum message_property_e {\r
+ // ???\r
+ SEND_STATIC_INTERNAL,\r
+ // messages are not consumed during read\r
+ RECEIVE_UNQUEUED_INTERNAL,\r
+ // We have an internal queue\r
+ RECEIVE_QUEUE_INTERNAL,\r
+} message_property_t;\r
+\r
+\r
+\r
+typedef enum message_notification_action_e {\r
+ MESSAGE_NOTIFICATION_ACTION_NONE=0,\r
+ MESSAGE_NOTIFICATION_ACTION_ACTIVATETASK,\r
+ MESSAGE_NOTIFICATION_ACTION_SETEVENT,\r
+} message_notification_action_t;\r
+\r
+typedef struct message_notification_s {\r
+ message_notification_action_t type;\r
+ TaskType task_id;\r
+ EventMaskType event_id;\r
+} message_notification_t;\r
+\r
+#if 0\r
+// TODO: Do a untion of all types here ???\r
+typedef struct {\r
+ void *cdata;\r
+} message_tx_t;\r
+#endif\r
+\r
+\r
+typedef struct message_obj_s {\r
+ message_property_t property; // send/recieve...\r
+ int q_size; // 0-Not queued\r
+ message_notification_t notification;\r
+ // TODO: This is not a good solution but it will have to do for now\r
+ void *data;\r
+ int data_size;\r
+} message_obj_t;\r
+\r
+\r
+typedef enum scheduling_e {\r
+ SCHEDULING_FULL,\r
+ SCHEDULING_NONE\r
+} scheduling_t;\r
+\r
+/*-----------------------------------------------------------------*/\r
+\r
+#if 0\r
+typedef enum {\r
+// PROC_BG,\r
+// PROC_INT,\r
+ PROC_BASIC,\r
+ PROC_EXTENDED,\r
+ PROC_ISR1,\r
+ PROC_ISR2,\r
+} proc_type_t;\r
+#endif\r
+\r
+typedef uint8_t proc_type_t;\r
+\r
+#define PROC_PRIO 0x1\r
+#define PROC_BASIC 0x1\r
+#define PROC_EXTENDED 0x3\r
+\r
+#define PROC_ISR 0x4\r
+#define PROC_ISR1 0x4\r
+#define PROC_ISR2 0xc\r
+\r
+\r
+typedef struct {\r
+ void *curr; // Current stack ptr( at swap time )\r
+ void *top; // Top of the stack( low address )\r
+ uint32 size; // The size of the stack\r
+} stack_t;\r
+\r
+typedef struct rom_app_s {\r
+ uint32 application_id;\r
+ char name[16];\r
+ uint8 trusted;\r
+\r
+ /* hooks */\r
+ void (*StartupHook)( void );\r
+ void (*ShutdownHook)( Std_ReturnType Error );\r
+ void (*ErrorHook)( Std_ReturnType Error );\r
+\r
+ uint32 isr_mask;\r
+ uint32 scheduletable_mask;\r
+ uint32 alarm_mask;\r
+ uint32 counter_mask;\r
+ uint32 resource_mask;\r
+ uint32 message_mask;\r
+\r
+} rom_app_t;\r
+\r
+/*-----------------------------------------------------------------*/\r
+\r
+typedef struct lockingtime_obj_s {\r
+ char id[16];\r
+ int resource;\r
+ int resource_clock_time;\r
+ int all_interrupt_clock_time;\r
+ int os_interrupt_clock_time;\r
+ int locking_type;\r
+} lockingtime_obj_t;\r
+\r
+\r
+typedef enum {\r
+ // the normal behaviour\r
+ RESOURCE_TYPE_STANDARD,\r
+ // ??\r
+ RESOURCE_TYPE_LINKED,\r
+ // Used for grouping tasks\r
+ RESOURCE_TYPE_INTERNAL\r
+} resource_type_t;\r
+\r
+typedef struct {\r
+ resource_type_t type;\r
+ // used only if type is RESOURCE_TYPE_LINKED\r
+ ResourceType linked_resource;\r
+} resource_property_t;\r
+\r
+/*-----------------------------------------------------------------*/\r
+typedef struct resource_obj_s {\r
+ char id[16];\r
+ // The running number, starting at RES_SCHEDULER=0\r
+ int nr;\r
+ // The calculated ceiling prio\r
+ uint32 ceiling_priority;\r
+ // Stored prio of the owner oi the resource\r
+ uint32 old_task_prio;\r
+\r
+ // What application may access this resource. A resource may only be\r
+ // accessed by one application\r
+ uint32 application_owner_id;\r
+ // What tasks may access this resource. A resource may be be shared\r
+ // several tasks.\r
+ uint32 task_mask;\r
+ // Owner of the resource...\r
+ TaskType owner;\r
+\r
+ resource_type_t type;\r
+ // used only if type is RESOURCE_TYPE_LINKED\r
+ ResourceType linked_resource;\r
+\r
+// resource_property_t resource_property;\r
+\r
+} resource_obj_t;\r
+\r
+typedef enum {\r
+ LOCK_TYPE_RESOURCE,\r
+ LOCK_TYPE_INTERRUPT,\r
+} lock_type_t;\r
+\r
+/*\r
+typedef struct {\r
+ ResourceType resource;\r
+ uint64 locktime;\r
+} resource_locktime_t;\r
+\r
+typedef struct {\r
+ uint64 all;\r
+ uint64 os;\r
+} interrupt_locktime_t;\r
+*/\r
+\r
+typedef struct lockingtime_s {\r
+// lock_type_t type;\r
+ lock_type_t type;\r
+ union {\r
+ struct {\r
+ ResourceType id;\r
+ uint64 time;\r
+ } resource;\r
+\r
+ struct {\r
+ uint64 all;\r
+ uint64 os;\r
+ } interrupt;\r
+ } u;\r
+// resource_locktime_t resource;\r
+// interrupt_locktime_t interrupt;\r
+// } locktime;\r
+} lockingtime_t;\r
+\r
+typedef struct timing_protection_s {\r
+ // ROM, worst case execution budget in ns\r
+ uint64 execution_budget;\r
+ // ROM, the frame in ns that timelimit may execute in.\r
+ uint64 timeframe;\r
+ // ROM, time in ns that the task/isr may with a timeframe.\r
+ uint64 timelimit;\r
+ // ROM, resource/interrupt locktimes\r
+ lockingtime_t *lockingtime;\r
+\r
+// interrupt_locktime_t interrupt_locktime;\r
+ // ROM, resource lock times\r
+// const resource_locktime_t *resource_locktime_list;\r
+// lockingtime_t *lockingtime;\r
+} timing_protection_t;\r
+\r
+\r
+/*-----------------------------------------------------------------*/\r
+\r
+typedef struct rom_pcb_s {\r
+ TaskType pid;\r
+ uint8 prio;\r
+ uint32 app_mask;\r
+ void (*entry)();\r
+ proc_type_t proc_type;\r
+ uint8 autostart;\r
+ stack_t stack;\r
+ int vector; // ISR\r
+ ApplicationType application_id;\r
+ char name[16];\r
+ scheduling_t scheduling;\r
+// uint64 execution_budget;\r
+// uint32 count_limit;\r
+// uint64 time_limit;\r
+ // pointer to internal resource\r
+ // NULL if none\r
+ resource_obj_t *resource_int_p;\r
+ timing_protection_t *timing_protection;\r
+// lockingtime_obj_t\r
+} rom_pcb_t;\r
+\r
+\r
+/*-----------------------------------------------------------------*/\r
+\r
+typedef struct sched_action_s {\r
+ int type; // 0 - activate task, 1 - event\r
+ uint64 offset; // for debug only???\r
+ uint64 delta; // delta to next action\r
+ TaskType task_id;\r
+ EventMaskType event_id; // used only if event..\r
+} sched_action_t;\r
+\r
+/*-----------------------------------------------------------------*/\r
+\r
+\r
+/*\r
+\r
+typedef enum message_type_e {\r
+ // ???\r
+ SEND_STATIC_INTERNAL,\r
+ // messages are not consumed during read\r
+ RECEIVE_UNQUEUED_INTERNAL,\r
+ // We have an internal queue\r
+ RECEIVE_QUEUE_INTERNAL,\r
+} message_type_t;\r
+*/\r
+\r
+#if 0\r
+typedef struct message_obj_s {\r
+ char name[16];\r
+ message_type_t type;\r
+ void *\r
+ char name[16];\r
+ uint32 accessingapplications_mask;\r
+ // TODO: Below types are NOT OK !!!!!!!\r
+ void* cdatatype;\r
+ void* initialvalue;\r
+ uint32 queuesize;\r
+ message_property_t messageproperty;\r
+ void * callbackroutine;\r
+ uint32 callbackMessage;\r
+ void* flagname;\r
+ uint32 notification;\r
+\r
+} message_obj_t;\r
+#endif\r
+\r
+\r
+\r
+/*-----------------------------------------------------------------*/\r
+\r
+\r
+typedef struct memory_s {\r
+ uint32_t flags;\r
+ /* ptr to start of memory region */\r
+ void *start;\r
+ /* size in bytes */\r
+ uint32_t size;\r
+} memory_t;\r
+\r
+/*-----------------------------------------------------------------*/\r
+/*\r
+ * debug settings for os_debug_mask\r
+ *\r
+ */\r
+\r
+#define OS_DBG_MASTER_PRINT (1<<0)\r
+#define OS_DBG_ISR_MASTER_PRINT (1<<1)\r
+#define OS_DBG_STDOUT (1<<2)\r
+#define OS_DBG_ISR_STDOUT (1<<3)\r
+\r
+// Enable print dbg_XXXX (not dbg_isr_XXX though)\r
+#define D_MASTER_PRINT (1<<0)\r
+// Enable print for all dbg_isr_XXX\r
+#define D_ISR_MASTER_PRINT (1<<1)\r
+// print to STDOUT. If not set it prints to ramlog\r
+#define D_STDOUT (1<<2)\r
+#define D_RAMLOG 0\r
+// print to STDOUT, If not set print to ramlog\r
+#define D_ISR_STDOUT (1<<3)\r
+#define D_ISR_RAMLOG 0\r
+\r
+#define D_TASK (1<<16)\r
+#define D_ALARM (1<<18)\r
+\r
+#define OS_DBG_TASK (1<<16)\r
+#define OS_DBG_ALARM (1<<18)\r
+\r
+\r
+\r
+#endif /* KERNEL_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef PCB_H\r
+#define PCB_H\r
+\r
+#include "types.h"\r
+#include "sys/queue.h"\r
+#include "Os.h"\r
+#include "kernel.h"\r
+#include "counter_i.h"\r
+#include <stdio.h>\r
+//#include "app_i.h"\r
+\r
+#define PID_IDLE 0\r
+#define PRIO_IDLE 0\r
+\r
+#define ST_READY 1\r
+#define ST_WAITING (1<<1)\r
+#define ST_SUSPENDED (1<<2)\r
+#define ST_RUNNING (1<<3)\r
+#define ST_NOT_STARTED (1<<4)\r
+\r
+typedef uint16_t state_t;\r
+\r
+/* from Os.h types */\r
+typedef TaskType procid_t;\r
+typedef EventMaskType event_t;\r
+/* Lets have 32 priority levels\r
+ * 0 - Highest prio\r
+ * 31- Lowest
+ */\r
+typedef sint8 prio_t;\r
+\r
+#define TASK_NAME_SIZE 16\r
+\r
+#if 0\r
+/* Application */\r
+typedef struct {\r
+ /* Application id */\r
+ uint32_t application_id;\r
+ /* Name of the application */\r
+ char name[16];\r
+ /* We let the application have a pool */\r
+ void *pool;\r
+ /* if this application is trusted or not */\r
+ uint8 trusted:1;\r
+ /* Attached counters */\r
+ counter_obj_t *counter;\r
+} app_t;\r
+#endif\r
+typedef rom_app_t app_t;\r
+\r
+\r
+struct rom_pcb_s;\r
+\r
+/* We do ISR and TASK the same struct for now */\r
+typedef struct pcb_s {\r
+ procid_t pid; // TASK\r
+ prio_t prio;\r
+ ApplicationType application_id;\r
+ uint32 app_mask;\r
+ void (*entry)();\r
+ proc_type_t proc_type;\r
+ uint8 autostart:1; // TASK\r
+ stack_t stack; // TASK\r
+ /* belongs to this application */\r
+ app_t *application;\r
+\r
+ int vector; // ISR\r
+ char name[TASK_NAME_SIZE];\r
+\r
+ timing_protection_t *timing_protection;\r
+\r
+ state_t state; // TASK\r
+ event_t ev_wait; // TASK\r
+ event_t ev_set; // TASK\r
+\r
+ scheduling_t scheduling; // TASK\r
+\r
+ // A task can hold only one internal resource\r
+ //ResourceType resource_internal; // TASK\r
+ resource_obj_t *resource_int_p;\r
+\r
+ struct rom_pcb_s *pcb_rom_p;\r
+\r
+ /* TODO: Arch specific regs .. make space for them later...*/\r
+ uint32_t regs[16]; // TASK\r
+ /* List of PCB's */\r
+ TAILQ_ENTRY(pcb_s) pcb_list; // TASK\r
+ /* ready list */\r
+ TAILQ_ENTRY(pcb_s) ready_list; // TASK\r
+} pcb_t;\r
+\r
+extern pcb_t pcb_list[];\r
+extern rom_pcb_t rom_pcb_list[];\r
+\r
+static inline pcb_t * os_get_pcb( procid_t pid ) {\r
+ return &pcb_list[pid];\r
+}\r
+\r
+static inline rom_pcb_t * os_get_rom_pcb( procid_t pid ) {\r
+ return &rom_pcb_list[pid];\r
+}\r
+\r
+static inline prio_t os_pcb_set_prio( pcb_t *pcb, prio_t new_prio ) {\r
+ prio_t old_prio;\r
+ old_prio = pcb->prio;\r
+ pcb->prio = new_prio;\r
+ //simple_printf("set_prio of %s to %d from %d\n",pcb->name,new_prio,pcb->prio);\r
+ return old_prio;\r
+}\r
+\r
+#define os_pcb_get_state(pcb) ((pcb)->state)\r
+\r
+#endif\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef SCHED_TABLE_I_H_\r
+#define SCHED_TABLE_I_H_\r
+\r
+/* Should hold the internal API used by the schedule tables */\r
+\r
+#define SCHEDULE_ACTION_ACTIVATETASK 0\r
+#define SCHEDULE_ACTION_SETEVENT 1\r
+\r
+#include "alist_i.h"\r
+#include "counter_i.h"\r
+\r
+struct counter_obj_s;\r
+\r
+enum OsScheduleTableSyncStrategy {\r
+ /* Support for sync */\r
+ NONE,\r
+ /* synchronize with "external" counter */\r
+ EXPLICIT,\r
+ /* sync internal */\r
+ IMPLICIT,\r
+};\r
+\r
+enum OsScheduleTableAutostartType {\r
+ // Start with StartScheduleTableAbs()\r
+ ABSOLUTE,\r
+ // Start with StartScheduleTableRel()\r
+ RELATIVE,\r
+ // Start with StartScheduleTableSyncon()\r
+ SYNCHRONE,\r
+};\r
+\r
+\r
+typedef struct sched_table_sync_s {\r
+\r
+/* SPEC */\r
+ enum OsScheduleTableSyncStrategy syncStrategy;\r
+ // from spec. (only if syncStrategy==EXPLICIT )\r
+ int explicitPrecision;\r
+\r
+/* OWN */\r
+ // This counter is advanced by the driver counter but is synchronized\r
+ // by SyncScheduleTable()\r
+ GlobalTimeTickType syncCounter;\r
+\r
+ // This is the deviation from the sync counter to the drive counter.\r
+ // (set by SyncScheduleTable())\r
+ // Calculated as 'driver count' - 'global time count from SyncScheduleTable()'\r
+ int deviation;\r
+\r
+} sched_table_sync_t;\r
+\r
+/* SPEC */\r
+typedef struct Stbl_AdjustableExpPoint {\r
+ uint8_t maxAdvance;\r
+ uint8_t maxRetard;\r
+} Stbl_AdjustableExpPointType;\r
+\r
+struct sched_table_autostart_s {\r
+ _Bool active;\r
+ enum OsScheduleTableAutostartType type;\r
+ uint32_t relOffset;\r
+ uint32_t appModeRef; // TODO\r
+};\r
+\r
+typedef struct sched_table_s {\r
+\r
+// Configuration\r
+\r
+ // OsScheduleTableDuration\r
+ int duration;\r
+\r
+ // If true, the schedule is periodic, OS009\r
+ // OsScheduleTableRepeating\r
+ _Bool repeating;\r
+\r
+ // Application mask\r
+ uint32 app_mask;\r
+\r
+ // pointer to this tables counter\r
+ // OsScheduleTableCounterRef\r
+ struct counter_obj_s *counter;\r
+\r
+ struct sched_table_autostart_s autostart;\r
+\r
+ struct sched_table_sync_s sync;\r
+\r
+ struct Stbl_AdjustableExpPoint adjExpPoint;\r
+\r
+// Private stuff\r
+\r
+ uint32_t final_offset; // used?\r
+ uint32_t init_offset; // used?\r
+ // Name...\r
+ char *name;\r
+\r
+ // ??\r
+// RAM\r
+ uint64 length;\r
+\r
+ uint32 id;\r
+\r
+ int expire_curr_index;\r
+ // When this table expires the next time\r
+ TickType expire_val;\r
+ // if true, the table is active\r
+ //_Bool active;\r
+ ScheduleTableStatusType state;\r
+\r
+ // Pointer to next schedule table, if any\r
+ // (don't use normal lists here since we have no list head)\r
+ struct sched_table_s *next;\r
+\r
+ /* Head of static action list */\r
+ SA_LIST_HEAD(alist,sched_action_s) action_list;\r
+\r
+ /* Entry in the list of schedule tables connected to a specfic\r
+ * counter */\r
+ SLIST_ENTRY(sched_table_s) sched_list;\r
+\r
+ // TableDuration\r
+ //\r
+\r
+} sched_table_t;\r
+\r
+/*\r
+#define os_stbl_get_action(x) SA_LIST_GET(&(x)->action_list,(x)->expire_curr_index)\r
+#define os_stbl_get_action_type(x) os_stbl_get_action(x)->type\r
+#define os_stbl_get_action_offset(x) os_stbl_get_action(x)->offset\r
+#define os_stbl_get_action_pid(x) os_stbl_get_action(x)->pid\r
+#define os_stbl_get_action_event(x) os_stbl_get_action(x)->event\r
+*/\r
+\r
+void os_stbl_init( void );\r
+void os_stbl_calc_expire( sched_table_t *stbl);\r
+\r
+#endif /*SCHED_TABLE_I_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+\r
+#define RINGBUF_DECL(name,type_of_data,data_cnt) \\r
+struct name { \\r
+ int r_ptr; \\r
+ int w_ptr; \\r
+ int m_size; \\r
+ int size; \\r
+ type_of_data m_bfr[(data_cnt)]; \\r
+} name = { 0,0,data_cnt}\r
+\r
+#define RINGBUF_PUT(name,obj) \ \r
+{ \\r
+ if( id.m_size == id.size ) \r
+ 0;\r
+ id.m_bfr[w_ptr] = obj;\r
+ id.w_ptr = (id.w_ptr+1)%id.size; \r
+\r
+}\r
+ \r
+\r
+ public boolean put(Object value) {\r
+ if ( m_size == SIZE )\r
+ return false; // buffer is full\r
+ m_bfr[m_wPtr] = value;\r
+ m_wPtr = (m_wPtr+1)%SIZE;\r
+ updateSize(1);\r
+ return true;\r
+ }\r
+ public Object get() {\r
+ if ( m_size == 0 )\r
+ return null; // buffer is empty\r
+ Object ret = m_bfr[m_rPtr];\r
+ m_bfr[m_rPtr] = null;\r
+ m_rPtr = (m_rPtr+1)%SIZE;\r
+ updateSize(-1);\r
+ return ret;\r
+ }\r
+\r
+\r
+struct my_data {\r
+ int a;\r
+ int b;\r
+};\r
+\r
+\r
+\r
+/* Implemenation */\r
+\r
+RINGBUF_DECL(apa,int ,10);\r
+\r
+ \r
+int main( void ) {\r
+// RINGBUF_INIT(apa);\r
+ apa.size = 1;\r
+\r
+// RINGBUF_INIT();\r
+ return 0;\r
+\r
+}\r
+\r
+#if 0\r
+ \r
+\r
+\r
+\r
+/* A spin buffer implemenation is some language */\r
+Spin Buffers\r
+by Prashanth Hirematada\r
+\r
+Listing One\r
+\r
+public class RingBuffer {\r
+ private final static int SIZE = 3000000;\r
+ private Object m_bfr[] = new Object[SIZE];\r
+ private int m_rPtr=0;\r
+ private int m_wPtr=0;\r
+ private int m_size=0;\r
+\r
+ /** Creates a new instance of RingBuffer */\r
+ public RingBuffer() {\r
+ }\r
+ private synchronized void updateSize(int by) {\r
+ m_size += by;\r
+ }\r
+ public boolean put(Object value) {\r
+ if ( m_size == SIZE )\r
+ return false; // buffer is full\r
+ m_bfr[m_wPtr] = value;\r
+ m_wPtr = (m_wPtr+1)%SIZE;\r
+ updateSize(1);\r
+ return true;\r
+ }\r
+ public Object get() {\r
+ if ( m_size == 0 )\r
+ return null; // buffer is empty\r
+ Object ret = m_bfr[m_rPtr];\r
+ m_bfr[m_rPtr] = null;\r
+ m_rPtr = (m_rPtr+1)%SIZE;\r
+ updateSize(-1);\r
+ return ret;\r
+ }\r
+}\r
+\r
+\r
+\r
+Listing Two\r
+\r
+public class SpinBuffer {\r
+ private static final int MAX_SIZE = 1000000;\r
+ private Object[][] m_bfr = new Object[3][MAX_SIZE];\r
+\r
+ private boolean[] m_busy = new boolean[3];\r
+ private int[] m_count = new int[3];\r
+ private int[] m_ptr = new int[3];\r
+\r
+ private int m_pBuf = 0;\r
+ private int m_cBuf = 1;\r
+\r
+ /** Creates a new instance of SpinBuffer */\r
+ public SpinBuffer() {\r
+ m_busy[0] = m_busy[1] = true;\r
+\r
+ m_busy[2] = false;\r
+ for ( int i=0; i<3; i++ ) {\r
+ m_ptr[i] = m_count[i] = 0;\r
+ }\r
+ }\r
+ public boolean put(Object o) {\r
+ int next = (m_pBuf+1)%3;\r
+\r
+ if ( m_ptr[m_pBuf] < MAX_SIZE ) {\r
+ // add to the buffer\r
+ m_bfr[m_pBuf][m_ptr[m_pBuf]] = o;\r
+ m_ptr[m_pBuf]++;\r
+ }\r
+ else\r
+ return false;\r
+ // check if next buffer is free\r
+ if ( !m_busy[next] ) {\r
+ m_count[m_pBuf] = m_ptr[m_pBuf];\r
+ m_ptr[m_pBuf] = 0;\r
+ m_busy[next] = true; // acquire\r
+ m_busy[m_pBuf] = false; // release\r
+ m_pBuf = next;\r
+ }\r
+ return true;\r
+ }\r
+ public Object get() {\r
+ Object o = null;\r
+\r
+ if ( m_ptr[m_cBuf] < m_count[m_cBuf]) {\r
+ o = m_bfr[m_cBuf][m_ptr[m_cBuf]];\r
+ // remove the reference\r
+ m_bfr[m_cBuf][m_ptr[m_cBuf]] = null;\r
+ m_ptr[m_cBuf]++;\r
+ }\r
+ else {\r
+ // check if next buffer is free\r
+ int next = (m_cBuf+1)%3;\r
+ if ( !m_busy[next] ) {\r
+ m_busy[next] = true; // acquire\r
+ m_ptr[m_cBuf] = 0;\r
+ m_count[m_cBuf] = 0;\r
+ m_busy[m_cBuf] = false; // release\r
+ m_cBuf = next;\r
+ }\r
+ //else, waiting for consumer\r
+ }\r
+ return o;\r
+ }\r
+}\r
+\r
+#endif\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef SWAP_H_\r
+#define SWAP_H_\r
+\r
+#include "pcb.h"\r
+\r
+void os_swap_context(pcb_t *old_pcb, pcb_t *new_pcb );\r
+void os_swap_context_to(pcb_t *old_pcb, pcb_t *new_pcb );\r
+\r
+#endif /*SWAP_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef SYS_H_\r
+#define SYS_H_\r
+\r
+#include "types.h"\r
+#include "pcb.h"\r
+\r
+struct os_conf_global_hook_s;\r
+\r
+typedef struct sys_s {\r
+// app_t *curr_application;\r
+ /* Current running task*/\r
+ pcb_t *curr_pcb;\r
+ /* List of all tasks */\r
+ pcb_t *pcb_list;\r
+ /* Interrupt nested count */\r
+ uint32 int_nest_cnt;\r
+ /* Ptr to the interrupt stack */\r
+ void *int_stack;\r
+ // The os tick\r
+ TickType tick;\r
+ // 1-The scheduler is locked (by GetResource() or something else)\r
+ int scheduler_lock;\r
+ /* Hooks */\r
+ struct os_conf_global_hooks_s *hooks;\r
+\r
+ // parameters for functions, used by OSErrorXXX()\r
+ uint32_t param1;\r
+ uint32_t param2;\r
+ uint32_t param3;\r
+ uint32_t serviceId;\r
+\r
+ uint32_t task_cnt;\r
+ /* List of all pcb's,\r
+ * Only needed for non-static configuration of the kernel\r
+ */\r
+ TAILQ_HEAD(tailq2,pcb_s) pcb_head;\r
+ /* Ready queue */\r
+ TAILQ_HEAD(tailq,pcb_s) ready_head;\r
+} sys_t;\r
+\r
+extern sys_t os_sys;\r
+\r
+static inline pcb_t *os_get_curr_pcb( void ) {\r
+ return os_sys.curr_pcb;\r
+}\r
+\r
+#if 0\r
+static uint32_t OSErrorGetServiceId( void ) {\r
+ return os_sys.serviceId;\r
+}\r
+#endif\r
+\r
+\r
+#endif /*SYS_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef TASK_I_H_\r
+#define TASK_I_H_\r
+\r
+#include <stdlib.h>\r
+#include <assert.h>\r
+#include "internal.h"\r
+\r
+static inline void os_pcb_print_rq( void ) {\r
+ pcb_t *i_pcb;\r
+ int cnt = 0;\r
+\r
+ TAILQ_FOREACH(i_pcb,&os_sys.ready_head,ready_list) {\r
+ //printf("%02d: %02d %s\n",cnt,i_pcb->state,i_pcb->name);\r
+ cnt++;\r
+// assert( i_pcb->state == ST_READY );\r
+ }\r
+}\r
+\r
+// schedule()\r
+static inline void os_pcb_running_to_ready( pcb_t *pcb ) {\r
+ assert(pcb->state == ST_RUNNING );\r
+ pcb->state = ST_READY;\r
+}\r
+\r
+\r
+// ActivateTask(pid)\r
+// SetEvent(pid)\r
+// os_pcb_make_virgin(pcb_t*)\r
+static inline void os_pcb_make_ready( pcb_t *pcb ) {\r
+ if( pcb->state != ST_READY ) {\r
+ pcb->state = ST_READY;\r
+ TAILQ_INSERT_TAIL(& os_sys.ready_head,pcb,ready_list);\r
+ os_isr_printf(D_TASK,"Added %s to ready list\n",pcb->name);\r
+ }\r
+}\r
+\r
+// WaitEvent\r
+static inline void os_pcb_make_waiting( pcb_t *pcb )\r
+{\r
+ assert( pcb->state & (ST_READY|ST_RUNNING) );\r
+\r
+ pcb->state = ST_WAITING;\r
+ TAILQ_REMOVE(&os_sys.ready_head,pcb,ready_list);\r
+ os_isr_printf(D_TASK,"Removed %s from ready list\n",pcb->name);\r
+}\r
+\r
+// Terminate task\r
+static inline void os_pcb_make_suspended( pcb_t *pcb )\r
+ {\r
+ assert( pcb->state & (ST_READY|ST_RUNNING) );\r
+ pcb->state = ST_SUSPENDED;\r
+ TAILQ_REMOVE(&os_sys.ready_head,pcb,ready_list);\r
+ os_isr_printf(D_TASK,"Removed %s from ready list\n",pcb->name);\r
+}\r
+\r
+\r
+/**\r
+ * Set the task to running state and remove from ready list\r
+ *\r
+ * @params pcb Ptr to pcb
+ */\r
+static inline void os_pcb_make_running( pcb_t *pcb ) {\r
+ pcb->state = ST_RUNNING;\r
+}\r
+\r
+\r
+_Bool os_pcb_pid_valid( pcb_t *restrict pcb );\r
+void os_proc_start_extended( void );\r
+void os_proc_start_basic( void );\r
+void os_setup_context( pcb_t *pcb );\r
+pcb_t *os_find_top_prio_proc( void );\r
+\r
+void os_pcb_make_virgin( pcb_t *pcb );\r
+\r
+// Added by Mattias in order to avoid compiler warning\r
+TaskType os_add_task( pcb_t *pcb );\r
+\r
+#if 0 // Not used any more\r
+pcb_t *os_find_higher_priority_task( prio_t prio );\r
+#endif\r
+\r
+\r
+#endif /*TASK_I_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+#ifndef _TYPES_H_\r
+#define _TYPES_H_\r
+//#include <stdint.h>\r
+\r
+//#if 0 \r
+typedef signed char int8_t; \r
+typedef unsigned char uint8_t; \r
+typedef signed short int16_t; \r
+typedef unsigned short uint16_t; \r
+typedef signed long int32_t; \r
+typedef unsigned long uint32_t;\r
+typedef unsigned long long uint64_t;\r
+//#endif\r
+\r
+typedef unsigned long _boolean;\r
+typedef float _F32;\r
+typedef double _F64; \r
+\r
+#endif\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+#include "Os.h"\r
+#include "sys.h"\r
+#include <stdlib.h>\r
+#include <string.h>\r
+#include "ext_config.h"\r
+//#include "Pool.h"\r
+//#include "ppc_asm.h"\r
+#include "arch.h"\r
+#include "kernel.h"\r
+#include "swap.h"\r
+#include "hooks.h"\r
+#include "task_i.h"\r
+#include "alarm_i.h"\r
+#include "sched_table_i.h"\r
+#include "Trace.h"\r
+\r
+\r
+\r
+extern void Oil_GetInterruptStackInfo( stack_t *stack );\r
+sys_t os_sys;\r
+\r
+/**\r
+ * Initialize alarms and schedule-tables for the counters\r
+ */\r
+static void os_counter_init( void ) {\r
+ counter_obj_t *counter;\r
+ alarm_obj_t *alarm_obj;\r
+ sched_table_t *sched_obj;\r
+ /* Create a list from the counter to the alarms */\r
+ for(int i=0; i < Oil_GetCounterCnt() ; i++) {\r
+ counter = Oil_GetCounter(i);\r
+ // Alarms\r
+ SLIST_INIT(&counter->alarm_head);\r
+ for(int j=0; j < Oil_GetAlarmCnt(); j++ ) {\r
+ alarm_obj = Oil_GetAlarmObj(j);\r
+ // Add the alarms\r
+ SLIST_INSERT_HEAD(&counter->alarm_head,alarm_obj, alarm_list);\r
+ }\r
+ // Schedule tables\r
+ SLIST_INIT(&counter->sched_head);\r
+ for(int j=0; j < Oil_GetSchedCnt(); j++ ) {\r
+ sched_obj = Oil_GetSched(j);\r
+ // Add the alarms\r
+ SLIST_INSERT_HEAD(&counter->sched_head,\r
+ sched_obj,\r
+ sched_list);\r
+ }\r
+\r
+\r
+ }\r
+}\r
+\r
+/**\r
+ * Copy rom pcb data(r_pcb) to ram data\r
+ *\r
+ * @param pcb ram data\r
+ * @param r_pcb rom data\r
+ */\r
+\r
+static void os_pcb_rom_copy( pcb_t *pcb, rom_pcb_t *r_pcb ) {\r
+\r
+#if 0 //?????\r
+ // Check to that the memory is ok\r
+ {\r
+ int cnt = sizeof(pcb_t);\r
+ for(int i=0;i<cnt;i++) {\r
+ if( *((unsigned char *)pcb) != 0 ) {\r
+ while(1);\r
+ }\r
+ }\r
+ }\r
+#endif\r
+\r
+// memset(pcb,sizeof(pcb_t),0);\r
+ pcb->pid = r_pcb->pid;\r
+ pcb->prio = r_pcb->prio;\r
+ pcb->application = Oil_GetApplObj(r_pcb->application_id);\r
+ pcb->entry = r_pcb->entry;\r
+ pcb->proc_type = r_pcb->proc_type;\r
+ pcb->autostart = r_pcb->autostart;\r
+ pcb->stack= r_pcb->stack;\r
+ pcb->pcb_rom_p = r_pcb;\r
+ pcb->resource_int_p = r_pcb->resource_int_p;\r
+ pcb->scheduling = r_pcb->scheduling;\r
+// pcb->app = &app_list[r_pcb->app];\r
+// pcb->app_mask = app_mask[r_pcb->app];\r
+ strncpy(pcb->name,r_pcb->name,16);\r
+}\r
+\r
+static _Bool init_os_called = 0;\r
+\r
+/**\r
+ * Initialization of kernel structures and start of the first\r
+ * task.\r
+ */\r
+\r
+void InitOS( void ) {\r
+ int i;\r
+ pcb_t *tmp_pcb;\r
+ stack_t int_stack;\r
+\r
+ init_os_called = 1;\r
+\r
+ DEBUG(DEBUG_LOW,"os_init");\r
+\r
+ /* Clear sys */\r
+ memset(&os_sys,0,sizeof(sys_t));\r
+\r
+ os_arch_init();\r
+\r
+ // Assign pcb list and init ready queue\r
+ os_sys.pcb_list = pcb_list;\r
+ TAILQ_INIT(& os_sys.ready_head);\r
+ TAILQ_INIT(& os_sys.pcb_head);\r
+\r
+ // Calc interrupt stack\r
+ Oil_GetInterruptStackInfo(&int_stack);\r
+ os_sys.int_stack = int_stack.top + int_stack.size - 16; // TODO: 16 is arch dependent\r
+\r
+ // Init counter.. with alarms and schedule tables\r
+ os_counter_init();\r
+ os_stbl_init();\r
+\r
+ // Put all tasks in the pcb list\r
+ // Put the one that belong in the ready queue there\r
+ // TODO: we should really hash on priority here to get speed, but I don't care for the moment\r
+ // TODO: Isn't this just EXTENED tasks ???\r
+ for( i=0; i < Oil_GetTaskCnt(); i++) {\r
+ tmp_pcb = os_get_pcb(i);\r
+ os_pcb_rom_copy(tmp_pcb,os_get_rom_pcb(i));\r
+ if( !(tmp_pcb->proc_type & PROC_ISR) ) {\r
+ os_pcb_make_virgin(tmp_pcb);\r
+ }\r
+\r
+ os_add_task(tmp_pcb);\r
+\r
+ DEBUG(DEBUG_LOW,"pid:%d name:%s prio:%d\n",tmp_pcb->pid,tmp_pcb->name,tmp_pcb->prio);\r
+ }\r
+\r
+ // Now all tasks should be created.\r
+}\r
+\r
+static void os_start( void ) {\r
+ pcb_t *tmp_pcb;\r
+\r
+ assert(init_os_called);\r
+\r
+ /* find highest prio process and run it */\r
+ tmp_pcb = os_find_top_prio_proc();\r
+\r
+ /* TODO: fix ugly */\r
+ /* Call the startup hook */\r
+ extern struct os_conf_global_hooks_s os_conf_global_hooks;\r
+ os_sys.hooks = &os_conf_global_hooks;\r
+ if( os_sys.hooks->StartupHook!=NULL ) {\r
+ os_sys.hooks->StartupHook();\r
+ }\r
+\r
+ /* handle autostart */\r
+ for(int j=0; j < Oil_GetAlarmCnt(); j++ ) {\r
+ alarm_obj_t *alarmPtr;\r
+ alarmPtr = Oil_GetAlarmObj(j);\r
+ if(alarmPtr->autostart.active) {\r
+ alarm_autostart_t *autoPtr = &alarmPtr->autostart;\r
+\r
+ SetAbsAlarm(j,autoPtr->alarmtime, autoPtr->cycletime);\r
+ }\r
+ }\r
+\r
+ // Swap in prio proc.\r
+ {\r
+ // FIXME: Do this in a more structured way.. setting os_sys.curr_pcb manually is not the way to go..\r
+ os_sys.curr_pcb = tmp_pcb;\r
+ // NOTE! We don't go for os_swap_context() here..\r
+ // first arg(NULL) is dummy only\r
+ os_swap_context_to(NULL,tmp_pcb);\r
+ // We should not return here\r
+ assert(0);\r
+ }\r
+}\r
+#if 0\r
+static void os_start( void ) {\r
+\r
+}\r
+#endif\r
+\r
+#define TEST_DATA 12345\r
+int test_data = TEST_DATA;\r
+int test_bss = 0;\r
+\r
+\r
+void noooo( void ) {\r
+ while(1);\r
+}\r
+\r
+extern EcuM_Init();\r
+int main( void )\r
+{\r
+ EcuM_Init();\r
+\r
+}\r
+\r
+/**\r
+ * Starts the OS\r
+ *\r
+ * @param Mode - Application mode to start in\r
+ *\r
+ */\r
+void StartOS( AppModeType Mode ) {\r
+\r
+ /* Check link file */\r
+ if( TEST_DATA != test_data ) {\r
+ noooo();\r
+ }\r
+\r
+ if( test_bss != 0 ) {\r
+ noooo();\r
+ }\r
+\r
+ os_start();\r
+\r
+}\r
+\r
+\r
+/**\r
+ * OS shutdown\r
+ *\r
+ * @param Error - Reason for shutdown\r
+ */\r
+\r
+void ShutdownOS( StatusType Error ) {\r
+\r
+ if( os_sys.hooks->ShutdownHook != NULL ) {\r
+ os_sys.hooks->ShutdownHook(Error);\r
+ }\r
+ /* TODO: */\r
+ while(1);\r
+\r
+}\r
+\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*
+ * isr.c
+ *
+ * Created on: Jul 13, 2009
+ * Author: mahi
+ */
+
+#include <stdint.h>
+#include "sys.h"
+#include "pcb.h"
+#include "internal.h"
+#include "hooks.h"
+#include "swap.h"
+// TODO: remove. Make soft links or whatever
+#if defined(CFG_ARM_CM3)
+#include "irq.h"
+//#include "stm32f10x.h"
+//#include "stm32f10x_arc.h"
+#endif
+#include "int_ctrl.h"
+
+/**
+ * Handle ISR type 2 interrupts from interrupt controller.
+ *
+ * @param stack Ptr to the current stack
+ * @param vector The vector that took the interrupt
+ */
+void *Os_Isr( void *stack, void *pcb_p ) {
+ struct pcb_s *pcb;
+ struct pcb_s *preempted_pcb;
+
+ os_sys.int_nest_cnt++;
+
+ // Save info for preempted pcb
+ preempted_pcb = get_curr_pcb();
+ preempted_pcb->stack.curr = stack;
+ preempted_pcb->state = ST_READY;
+ os_isr_printf(D_TASK,"Preempted %s\n",preempted_pcb->name);
+
+ POSTTASKHOOK();
+
+ pcb = (struct pcb_s *)pcb_p;
+ pcb->state = ST_RUNNING;
+ set_curr_pcb(pcb);
+
+ PRETASKHOOK();
+
+ // We should not get here if we're SCHEDULING_NONE
+ if( pcb->scheduling == SCHEDULING_NONE) {
+ // TODO:
+ // assert(0);
+ while(1);
+ }
+ //Irq_Enable(); // Added by Mattias
+ //Irq_Enable();
+ pcb->entry();
+ Irq_Disable();
+
+ pcb->state = ST_SUSPENDED;
+ POSTTASKHOOK();
+
+ IntCtrl_EOI();
+
+ --os_sys.int_nest_cnt;
+
+ // TODO: Check stack check marker....
+ // We have preempted a task
+ if( (os_sys.int_nest_cnt == 0) ) { //&& is_idle_task() ) {
+ /* If we get here:
+ * - the preempted task is saved with large context.
+ * - We are on interrupt stack..( this function )
+ *
+ * if we find a new task:
+ * - just switch in the new context( don't save the old because
+ * its already saved )
+ *
+ */
+ pcb_t *new_pcb;
+ new_pcb = os_find_top_prio_proc();
+ if( new_pcb != preempted_pcb ) {
+ os_isr_printf(D_TASK,"Found candidate %s\n",new_pcb->name);
+//#warning os_swap_context_to should call the pretaskswaphook
+ os_swap_context_to(NULL,new_pcb);
+ } else {
+ if( new_pcb == NULL ) {
+ assert(0);
+ }
+ preempted_pcb->state = ST_RUNNING;
+ set_curr_pcb(preempted_pcb);
+ }
+ }
+
+ return stack;
+}
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+\r
+#include <stddef.h>\r
+\r
+#define DECLARE(sym,val) \\r
+ __asm("#define " #sym " %0" : : "i" ((val)))\r
+\r
+#include "Os.h"\r
+#include "pcb.h"\r
+//#include "app_i.h"\r
+#include "sys.h"\r
+#include "kernel.h"\r
+\r
+\r
+void oil_foo(void) {\r
+\r
+ DECLARE(PCB_T_SIZE, sizeof(pcb_t));\r
+ DECLARE(APP_T_SIZE, sizeof(app_t));\r
+ DECLARE(PCB_STACK_CURR_P, offsetof(pcb_t, stack));
+ DECLARE(PCB_ENTRY_P, offsetof(pcb_t, entry));
+ DECLARE(SYS_CURR_PCB_P, offsetof(sys_t, curr_pcb));
+ DECLARE(SYS_INT_NEST_CNT, offsetof(sys_t, int_nest_cnt));
+ DECLARE(SYS_INT_STACK, offsetof(sys_t, int_stack));
+}\r
+\r
--- /dev/null
+\r
+\r
+#VPATH += $(ROOTDIR)/arch/arm/arm_cm3/kernel\r
+vpath-y += $(ARCH_PATH-y)/kernel\r
+#obj-y += asm_sample.o\r
+obj-y += arch_krn.o\r
+\r
+\r
+# object files \r
+obj-y += event.o\r
+obj-y += init.o\r
+obj-y += trusted.o\r
+obj-y += arch.o\r
+obj-y += task.o\r
+obj-y += task_i.o\r
+obj-y += resource.o\r
+obj-y += swap.o\r
+obj-y += alarm.o\r
+obj-y += sched_table.o\r
+obj-y += counter.o\r
+obj-y += com_internal.o\r
+obj-y += create.o\r
+obj-y += Frt.o\r
+obj-y += stack.o\r
+obj-y += isr.o\r
+\r
+\r
+# These are VERY cpu dependent.. remove\r
+obj-y += int_ctrl.o\r
+\r
+# We are compiling the kernel\r
+def-y+=CC_KERNEL\r
+dep-y += asm_offset.h\r
+dep-y += kernel_offset.h\r
+dep-$(CFG_ARM_CM3) += arch_offset.h\r
+\r
+# ARM assembler generates "define STACK_APA $12". The extra '$' we want to go.\r
+# Assembler offsets\r
+%_offset.h: %_offset.c\r
+ @echo " >> generating $@ from $<"\r
+ $(Q)$(CC) -S $(CFLAGS) -o $(@:.h=.s) $(addprefix -I ,$(inc-y)) $(addprefix -D,$(def-y)) $<\r
+ gawk '/.*define/ { print $$1 " " $$2 " " gensub("#","","g",$$3) }' $(@:.h=.s) > $@\r
+\r
+# Assembler offsets\r
+asm_offset.h: asm_offset.c\r
+ @echo " >> asm offset gen $<"\r
+ $(Q)$(CC) -S $(CFLAGS) -o $(<:.c=.s) $(addprefix -I ,$(inc-y)) $(addprefix -D,$(def-y)) $< \r
+ @$(SED) -n "/#define/p" $(<:.c=.s) > $@\r
+ @rm $(<:.c=.s)\r
+ \r
+VPATH += .. \r
+VPATH += $(ROOTDIR)/arch/$(ARCH_FAM)/$(ARCH)/kernel\r
+VPATH += $(ROOTDIR)/arch/$(ARCH_FAM)/$(ARCH)/drivers\r
+\r
+inc-y += .\r
+inc-y += $(ROOTDIR)/drivers/include\r
+inc-y += $(ROOTDIR)/arch/$(ARCH_FAM)/$(ARCH)/kernel\r
+inc-y += $(ROOTDIR)/arch/$(ARCH_FAM)/$(ARCH)/drivers\r
+inc-y += $(ROOTDIR)/arch/$(ARCH_FAM)/$(ARCH)/config\r
+inc-y += $(ROOTDIR)/arch/$(ARCH)\r
+inc-y += $(ROOTDIR)/include/$(ARCH_FAM)\r
+\r
+\r
+build-lib-y = $(ROOTDIR)/libs/libkernel_$(ARCH_MCU).a\r
+ \r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+#include "Os.h"\r
+\r
+\r
+/* See 8.4.4 */\r
+AccessType CheckISRMemoryAccess( ISRType ISRID,\r
+ MemoryStartAddressType Address, \r
+ MemorySizeType Size ) \r
+{\r
+ // get hold of application memory space\r
+ \r
+ \r
+}\r
+\r
+AccessType CheckTaskMemoryAccess( TaskType TaskID,\r
+ MemoryStartAddressType Address, \r
+ MemorySizeType Size ) \r
+{\r
+\r
+ \r
+}\r
+\r
+/* Object access\r
+ * \r
+ * \r
+ * resource \r
+ * \r
+ * \r
+ */\r
+\r
+\r
+\r
+\r
+/* This is probably macros */\r
+ObjectAccessType CheckObjectAccess( ApplicationType ApplID,\r
+ ObjectTypeType ObjectType,\r
+ void *object )\r
+{\r
+ uint32 app_mask = (1<<ApplID);\r
+ uint32 rv;\r
+ \r
+ /* TODO: check id */\r
+ switch( ObjectType ) {\r
+ case OBJECT_ALARM:\r
+ rv = ((alarm_obj_t *)object)->app_mask & (app_mask);\r
+ break;\r
+ case OBJECT_COUNTER:\r
+ rv = ((counter_obj_t *)object)->app_mask & (app_mask); \r
+ break;\r
+ case OBJECT_ISR: \r
+ break;\r
+ case OBJECT_MESSAGE:\r
+ case OBJECT_RESOURCE: \r
+ case OBJECT_SCHEDULETABLE:\r
+ break;\r
+ case OBJECT_TASK:\r
+ rv = ((counter_obj_t *)object)->app_mask & (app_mask);\r
+ break;\r
+ default:\r
+ break; \r
+ }\r
+ \r
+ \r
+ \r
+ \r
+ return ACCESS;\r
+}\r
+\r
+/* return application id for object */\r
+ApplicationType CheckObjectOwnership( ObjectTypeType ObjectType,\r
+ void *object ) \r
+{\r
+ switch( ObjectType ) {\r
+ case OBJECT_ALARM:\r
+ case OBJECT_COUNTER:\r
+ case OBJECT_ISR:\r
+ case OBJECT_MESSAGE:\r
+ case OBJECT_RESOURCE:\r
+ case OBJECT_SCHEDULETABLE:\r
+ case OBJECT_TASK:\r
+ default:\r
+ break;\r
+ }\r
+ \r
+ return (-1);\r
+} \r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+static uint8_tos_pool[20000];\r
+\r
+typedef struct {\r
+ void *free; \r
+}os_memory_t;\r
+\r
+k_memory_tos_mem = { .free = NULL };\r
+\r
+void *k_malloc( int size ) {\r
+ void *t;\r
+ if(os_mem.free != NULL ) {\r
+ t =os_mem.free;\r
+ (uint8)k_mem.free += size;\r
+ return t;\r
+ }\r
+ return NULL;\r
+}\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+#include "types.h"\r
+#include "Os.h"\r
+#include "assert.h"\r
+#include "sys.h"\r
+#include "stdlib.h"\r
+#include "kernel.h"\r
+#include "internal.h"\r
+#include "hooks.h"\r
+#include "task_i.h"\r
+#include "ext_config.h"\r
+\r
+\r
+#define valid_standard_id() (rid->nr < Oil_GetResourceCnt()) //&& !(rid->type == RESOURCE_TYPE_INTERNAL) )\r
+#define valid_internal_id() (rid->nr < Oil_GetResourceCnt()) //&& (rid->type == RESOURCE_TYPE_INTERNAL) )\r
+\r
+\r
+static StatusType GetResource_( resource_obj_t * );\r
+StatusType ReleaseResource_( resource_obj_t * );\r
+\r
+StatusType GetResource( ResourceType ResID ) {\r
+ resource_obj_t *rid = Oil_GetResource(ResID);\r
+ StatusType rv = GetResource_(rid);\r
+\r
+ if (rv != E_OK)\r
+ goto err;\r
+\r
+ OS_STD_END_1(OSServiceId_GetResource,ResID);\r
+}\r
+\r
+#if 0\r
+StatusType GetResourceInternal( ResourceType ResID ) {\r
+ return GetResource_(ResID,1);\r
+}\r
+#endif\r
+\r
+static StatusType GetResource_( resource_obj_t * rid ) {\r
+ StatusType rv = E_OK;\r
+\r
+ if( rid->nr == RES_SCHEDULER ) {\r
+ // Lock the sheduler\r
+#warning Check this\r
+ os_sys.scheduler_lock = 1;\r
+ //simple_printf("RES_SCHEDULER, NOT supported yet\n");\r
+ //while(1);\r
+ }\r
+ // Check if valid resource\r
+ if( !valid_standard_id() ) {\r
+ rv = E_OS_ID;\r
+ goto err;\r
+ }\r
+ // Check that the resource does not belong to another application or task\r
+ if( ( (os_task_nr_to_mask(get_curr_pid()) & rid->task_mask ) == 0 )\r
+ || ( get_curr_application_id() != rid->application_owner_id)\r
+ || ( rid->owner != (TaskType)(-1)))\r
+ {\r
+ rv = E_OS_ACCESS;\r
+ goto err;\r
+ }\r
+\r
+ rid->owner = get_curr_pid();\r
+ rid->old_task_prio = os_pcb_set_prio(os_get_curr_pcb() ,rid->ceiling_priority);\r
+ goto ok;\r
+err:\r
+ ERRORHOOK(rv);\r
+ok:\r
+ return rv;\r
+}\r
+\r
+StatusType ReleaseResource( ResourceType ResID) {\r
+ StatusType rv = E_OK;\r
+ if( ResID == RES_SCHEDULER ) {\r
+ #warning check this\r
+ os_sys.scheduler_lock=0;\r
+ } else {\r
+ resource_obj_t *rid = Oil_GetResource(ResID);\r
+ rv = ReleaseResource_(rid);\r
+ }\r
+\r
+ if (rv != E_OK)\r
+ goto err;\r
+\r
+ OS_STD_END_1(OSServiceId_ReleaseResource,ResID);\r
+}\r
+\r
+StatusType ReleaseResource_( resource_obj_t * rid ) {\r
+ if (!valid_standard_id()) {\r
+ return E_OS_ID;\r
+ } else {\r
+\r
+ // Release it...\r
+ rid->owner = (TaskType) (-1);\r
+ os_pcb_set_prio(os_get_curr_pcb(), rid->old_task_prio);\r
+\r
+ return E_OK;\r
+ }\r
+}\r
+\r
+// TODO: Remove this function later.. this is done in oil generator\r
+// instead.\r
+void os_resource_calc_attributes( void ) {\r
+ // Calc ceiling\r
+// ResourceType *rsrc;\r
+ for( int i=0;i<Oil_GetResourceCnt();i++) {\r
+// rsrc = Oil_GetResource();\r
+ /* TODO: Do this when there's more time */\r
+// rsrc\r
+ }\r
+}\r
+\r
+//\r
+void os_resource_get_internal( void ) {\r
+ resource_obj_t *rt = os_get_resource_int_p();\r
+\r
+ if( rt != NULL ) {\r
+ //simple_printf("Get IR proc:%s prio:%d old_task_prio:%d\n",get_curr_pcb()->name, rt->ceiling_priority,rt->old_task_prio);\r
+ GetResource_(rt);\r
+ }\r
+ //GetResourceInternal(os_get_curr_pcb()->resource_internal);\r
+}\r
+\r
+void os_resource_release_internal( void ) {\r
+ resource_obj_t *rt = os_get_resource_int_p();\r
+\r
+ if( rt != NULL ) {\r
+ //simple_printf("Rel IR proc:%s prio:%d old_task_prio:%d\n",get_curr_pcb()->name,rt->ceiling_priority,rt->old_task_prio);\r
+ ReleaseResource_(rt);\r
+ }\r
+ //ReleaseResource(os_get_curr_pcb()->resource_internal);\r
+}\r
+\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+#include "Os.h"\r
+#include "types.h"\r
+#include "counter_i.h"\r
+#include "pcb.h"\r
+#include "sched_table_i.h"\r
+#include "ext_config.h"\r
+#include "hooks.h"\r
+#include <stdlib.h>\r
+#include "alist_i.h"\r
+#include <assert.h>\r
+\r
+/*\r
+ * How Autosar sees the scheduletable\r
+ *\r
+ * duration\r
+ * repeating\r
+ * accessionApplication\r
+ * counterRef\r
+ * autostart [0..1]\r
+ * |--- absValue (only if type==ABSOLUTE )\r
+ * |--- relOffset (only if type==RELATIVE )\r
+ * |--- type (ABSOLUTE, RELATIVE, SYNCHRON )\r
+ * |--- modeRef\r
+ * |\r
+ * expiryPoint [1..*]\r
+ * |--- offset\r
+ * |--- EventSetting [0..*]\r
+ * | |--- SetEvent\r
+ * | `--- SetEventTaskRef\r
+ * |\r
+ * |--- TaskActivation [0..*]\r
+ * | `- TaskRef\r
+ * |\r
+ * |--- AdjustableExpPoint [0..1] (only if syncStrategy!=NONE)\r
+ * | |--- maxAdvance\r
+ * | `--- macRetard\r
+ * |\r
+ * sync\r
+ * |--- explicitPrecision (only if syncStrategy==EXPLICIT )\r
+ * |--- syncStrategy (NONE,EXPLICIT,IMPLICIT )\r
+ *
+ */\r
+\r
+\r
+// Cancel\r
+\r
+#define SCHED_CHECK_ID(x) \\r
+ if( (x) > Oil_GetSchedCnt()) { \\r
+ rv = E_OS_ID; \\r
+ goto err; \\r
+ }\r
+\r
+#define SCHED_STD_END \\r
+ return rv; \\r
+ err: \\r
+ ERRORHOOK(rv); \\r
+ return rv;\r
+\r
+extern TickType GetCountValue( counter_obj_t *counter );\r
+\r
+static TickType os_calc_modulo( TickType curr, TickType max, TickType add ) {\r
+ TickType diff = max - curr;\r
+ return (diff >= add ) ? (curr + add) :\r
+ (add - curr);\r
+}\r
+\r
+enum OsScheduleTableSyncStrategy getSyncStrategy( sched_table_t *stblPtr ) {\r
+ return stblPtr->sync.syncStrategy;\r
+}\r
+\r
+\r
+/**\r
+ * Consistency checks for scheduletables. This should really be checked by\r
+ * the generator.\r
+ *\r
+ * See chapter 11.2.\r
+ *
+ * @return
+ */\r
+static void ScheduleTableConsistenyCheck( sched_table_t *s_p ) {\r
+\r
+ // OS440\r
+ if( s_p->sync.syncStrategy == IMPLICIT ) {\r
+ assert( s_p->duration == (s_p->counter->alarm_base.maxallowedvalue +1) );\r
+ }\r
+\r
+ // OS431\r
+ if( s_p->sync.syncStrategy == EXPLICIT ) {\r
+ assert( s_p->duration <= (s_p->counter->alarm_base.maxallowedvalue +1) );\r
+ }\r
+}\r
+\r
+\r
+// TODO: OS452,OS278\r
+StatusType StartScheduleTableRel(ScheduleTableType sid, TickType offset) {\r
+ StatusType rv = E_OK;\r
+ sched_table_t *s_tbl;\r
+ TickType max_offset;\r
+\r
+\r
+ (void)offset;\r
+ // OS275\r
+ SCHED_CHECK_ID(sid);\r
+ s_tbl = Oil_GetSched(sid);\r
+ // OS276\r
+ max_offset = s_tbl->counter->alarm_base.maxallowedvalue;\r
+ if( (offset == 0) || (offset > max_offset )) {\r
+ rv = E_OS_VALUE;\r
+ goto err;\r
+ }\r
+\r
+ // OS277\r
+ if( s_tbl->state != SCHEDULETABLE_STOPPED ) {\r
+ rv = E_OS_STATE; goto err;\r
+ }\r
+\r
+ s_tbl->state = SCHEDULETABLE_RUNNING;\r
+ // calculate the expire value..\r
+ s_tbl->expire_val = os_calc_modulo( GetCounterValue_(s_tbl->counter), max_offset, offset );\r
+// s_tbl->expire_val = offset + SA_LIST_GET(&s_tbl->action_list,0)->offset;\r
+// ALIST_RESET(&s_tbl->action_list);\r
+ s_tbl->state = SCHEDULETABLE_RUNNING;\r
+\r
+ // s_tbl->action_list_index = 0;\r
+\r
+ SCHED_STD_END;\r
+}\r
+\r
+StatusType StartScheduleTableAbs(ScheduleTableType sid, TickType val ){\r
+ StatusType rv = E_OK;\r
+ (void)val;\r
+ SCHED_CHECK_ID(sid);\r
+\r
+ SCHED_STD_END;\r
+}\r
+\r
+/**\r
+ *
+ * @param sid
+ * @return
+ */\r
+\r
+StatusType StartScheduleTableSynchron(ScheduleTableType sid ){\r
+ sched_table_t *s_p;\r
+ StatusType rv = E_OK;\r
+\r
+ DisableAllInterrupts();\r
+\r
+ SCHED_CHECK_ID(sid);\r
+\r
+ // OS387\r
+ if( s_p->sync.syncStrategy != EXPLICIT ) {\r
+ rv = E_OS_ID;\r
+ goto err;\r
+ }\r
+\r
+ // OS388\r
+ if( s_p->state != SCHEDULETABLE_STOPPED ) {\r
+ rv = E_OS_STATE;\r
+ goto err;\r
+ }\r
+\r
+ // OS389\r
+ s_p->state = SCHEDULETABLE_WAITING;\r
+\r
+ EnableAllInterrupts();\r
+\r
+ SCHED_STD_END;\r
+}\r
+\r
+\r
+\r
+StatusType StopScheduleTable(ScheduleTableType sid) {\r
+ StatusType rv = E_OK;\r
+ sched_table_t *s_tbl;\r
+ SCHED_CHECK_ID(sid);\r
+ s_tbl = Oil_GetSched(sid);\r
+\r
+ s_tbl->state = SCHEDULETABLE_STOPPED;\r
+\r
+ SCHED_STD_END;\r
+}\r
+\r
+StatusType NextScheduleTable( ScheduleTableType sid_curr, ScheduleTableType sid_next) {\r
+ StatusType rv = E_OK;\r
+ (void)sid_curr;\r
+ (void)sid_next;\r
+\r
+ sched_table_t *s_curr;\r
+ sched_table_t *s_next;\r
+\r
+ SCHED_CHECK_ID(sid_curr);\r
+ SCHED_CHECK_ID(sid_next);\r
+\r
+ s_curr = Oil_GetSched(sid_curr);\r
+ s_next = Oil_GetSched(sid_curr);\r
+\r
+ // OS330\r
+ if( s_curr->counter != s_next->counter) {\r
+ rv = E_OS_ID;\r
+ goto err;\r
+ }\r
+\r
+\r
+ DisableAllInterrupts();\r
+\r
+ // OS283\r
+ if( s_curr->state == SCHEDULETABLE_STOPPED ||\r
+ s_curr->state == SCHEDULETABLE_NEXT ||\r
+ s_next->state == SCHEDULETABLE_STOPPED ||\r
+ s_next->state == SCHEDULETABLE_NEXT )\r
+ {\r
+ rv = E_OS_NOFUNC;\r
+ goto err;\r
+ }\r
+\r
+ // OS309\r
+ if( s_next->state != SCHEDULETABLE_STOPPED ) {\r
+ rv = E_OS_STATE;\r
+ goto err;\r
+ }\r
+\r
+ // OS324\r
+ if( s_curr->next != NULL ) {\r
+ // Stop the scheduletable that was to be next.\r
+ s_curr->next->state = SCHEDULETABLE_STOPPED;\r
+ }\r
+\r
+ s_curr->next = s_next;\r
+ s_next->state = SCHEDULETABLE_NEXT;\r
+\r
+ EnableAllInterrupts();\r
+\r
+ SCHED_STD_END;\r
+}\r
+\r
+\r
+\r
+/**\r
+ *
+ * @param sid
+ * @param globalTime
+ * @return
+ */\r
+StatusType SyncScheduleTable( ScheduleTableType sid, GlobalTimeTickType globalTime ) {\r
+ StatusType rv = E_OK;\r
+ sched_table_t *s_p = Oil_GetSched(sid);\r
+\r
+ SCHED_CHECK_ID(sid);\r
+\r
+ // OS454\r
+ if( s_p->sync.syncStrategy != EXPLICIT ) {\r
+ rv = E_OS_ID;\r
+ goto err;\r
+ }\r
+\r
+ // OS455\r
+ if( globalTime > s_p->duration ) {\r
+ rv = E_OS_VALUE;\r
+ goto err;\r
+ }\r
+\r
+ DisableAllInterrupts();\r
+\r
+ // OS456\r
+ if( (s_p->state == SCHEDULETABLE_STOPPED) ||\r
+ (s_p->state == SCHEDULETABLE_NEXT) ) {\r
+ rv = E_OS_STATE;\r
+ goto err;\r
+ }\r
+\r
+ switch(s_p->state) {\r
+ case SCHEDULETABLE_WAITING:\r
+ // First time we called since started. Set the sync counter to\r
+ // the value provided.\r
+ s_p->sync.syncCounter = globalTime;\r
+ s_p->state = SCHEDULETABLE_RUNNING_AND_SYNCHRONOUS;\r
+ break;\r
+\r
+ case SCHEDULETABLE_RUNNING:\r
+ case SCHEDULETABLE_RUNNING_AND_SYNCHRONOUS:\r
+ s_p->sync.deviation = s_p->sync.syncCounter - globalTime;\r
+ if( s_p->sync.deviation != 0 ) {\r
+ // We are not at sync any more...\r
+ s_p->state = SCHEDULETABLE_RUNNING;\r
+ }\r
+ break;\r
+\r
+ default:\r
+ assert(0);\r
+ break;\r
+ }\r
+\r
+ EnableAllInterrupts();\r
+\r
+ SCHED_STD_END;\r
+}\r
+\r
+/**\r
+ *
+ * @param sid
+ * @param status
+ * @return
+ */\r
+StatusType GetScheduleTableStatus( ScheduleTableType sid, ScheduleTableStatusRefType status ) {\r
+ StatusType rv = E_OK;\r
+ sched_table_t *s_p;\r
+ (void)status;\r
+ SCHED_CHECK_ID(sid);\r
+\r
+ s_p = Oil_GetSched(sid);\r
+ DisableAllInterrupts();\r
+\r
+ switch(s_p->state) {\r
+ case SCHEDULETABLE_STOPPED: // OS289\r
+ case SCHEDULETABLE_NEXT: // OS353\r
+ case SCHEDULETABLE_RUNNING_AND_SYNCHRONOUS: // OS290\r
+ case SCHEDULETABLE_WAITING: // OS354\r
+ case SCHEDULETABLE_RUNNING: // OS291\r
+ *status = s_p->state;\r
+ break;\r
+ default:\r
+ assert(0);\r
+\r
+ }\r
+\r
+ EnableAllInterrupts();\r
+\r
+ SCHED_STD_END;\r
+}\r
+\r
+\r
+/**\r
+ *
+ * @param sid
+ * @return
+ */\r
+StatusType SetScheduleTableAsync( ScheduleTableType sid ) {\r
+ StatusType rv = E_OK;\r
+ sched_table_t *s_p = Oil_GetSched(sid);\r
+\r
+ SCHED_CHECK_ID(sid);\r
+\r
+ // OS458\r
+ if( s_p->sync.syncStrategy != EXPLICIT ) {\r
+ rv = E_OS_ID;\r
+ goto err;\r
+ }\r
+\r
+ DisableAllInterrupts();\r
+\r
+ // TODO: check OS362, OS323\r
+\r
+ // OS300\r
+ s_p->state = SCHEDULETABLE_RUNNING;\r
+\r
+ EnableAllInterrupts();\r
+\r
+ SCHED_STD_END;\r
+}\r
+\r
+/*\r
+ *start e e e delta stop\r
+ * |----|---|-------|---------|\r
+ *\r
+ *\r
+ * | s e e cm e\r
+ * |---|---|----|---|----|----------|\r
+ * 1 2 3 4 5\r
+ * e-expiry point\r
+ * cm-counter max( restart from 0)\r
+ * s-call to StartScheduleTableRel()\r
+ */\r
+\r
+\r
+/* TODO: Remove when we have a stable generator. The reason for this\r
+ * funcion is that I'm afraid of if I change the maxallowedvalue for the\r
+ * counter I will miss to update the delta values\r
+ */\r
+static void os_stbl_action_calc_delta( sched_table_t *stbl ) {\r
+ sched_action_t * first;\r
+ sched_action_t * second;\r
+// ALIST_DECL_ITER(iter);\r
+ int iter;\r
+\r
+ // calculate the delta to next action\r
+\r
+ for(iter=1; iter < SA_LIST_CNT(&stbl->action_list) ;iter++) {\r
+ first = SA_LIST_GET(&stbl->action_list,iter-1);\r
+ second = SA_LIST_GET(&stbl->action_list,iter);\r
+ first->delta = second->offset - first->offset;\r
+ }\r
+ // calculate the last delta( to countes max value )\r
+ first = SA_LIST_GET(&stbl->action_list, SA_LIST_CNT(&stbl->action_list)-1);\r
+ first->delta = stbl->counter->alarm_base.maxallowedvalue - first->offset;\r
+}\r
+\r
+/**\r
+ *
+ */\r
+void os_stbl_init( void ) {\r
+ sched_table_t *s_p;\r
+ for( int i=0; i < Oil_GetSchedCnt();i++ ) {\r
+ s_p = Oil_GetSched(i);\r
+ os_stbl_action_calc_delta(s_p);\r
+\r
+ ScheduleTableConsistenyCheck(s_p);\r
+ }\r
+}\r
+\r
+/**\r
+ *
+ * @param stbl
+ */\r
+void os_stbl_calc_expire( sched_table_t *stbl) {\r
+\r
+ TickType old_delta;\r
+\r
+ /* Any more actions in the action list?*/\r
+ if( (stbl->expire_curr_index+1) >= SA_LIST_CNT(&stbl->action_list) ) {\r
+\r
+ // TODO: final offset\r
+ if( stbl->next != NULL ) {\r
+ assert(stbl->state == SCHEDULETABLE_RUNNING);\r
+ }\r
+\r
+ if( !stbl->repeating ) {\r
+ stbl->state = SCHEDULETABLE_STOPPED;\r
+ stbl->expire_curr_index = 0;\r
+ goto end;\r
+ }\r
+ }\r
+\r
+ old_delta = SA_LIST_GET(&stbl->action_list,stbl->expire_curr_index)->delta;\r
+ stbl->expire_curr_index++;\r
+// ALIST_INC(&stbl->action_list);\r
+\r
+ stbl->expire_val =\r
+ os_calc_modulo( stbl->expire_val,\r
+ stbl->counter->alarm_base.maxallowedvalue,\r
+ old_delta);\r
+\r
+\r
+#if 0\r
+ TickType old_delta;\r
+ if( ALIST_LAST(&stbl->action_list)) {\r
+ if( !stbl->repeating ) {\r
+ stbl->active = 0;\r
+ ALIST_RESET(&stbl->action_list);\r
+ goto end;\r
+ }\r
+ }\r
+\r
+ old_delta = ALIST_GET_DATA(&stbl->action_list)->delta;\r
+ ALIST_INC(&stbl->action_list);\r
+\r
+ stbl->expire_val =\r
+ os_calc_modulo( stbl->expire_val,\r
+ stbl->counter_id->alarm_base.maxallowedvalue,\r
+ old_delta);\r
+// stbl->action_list[stbl->action_list_index]->delta);\r
+#endif\r
+\r
+end:\r
+ return;\r
+}\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*\r
+ * stack.c\r
+ *\r
+ * Created on: 2009-jan-25\r
+ * Author: mahi\r
+ */\r
+\r
+#include "pcb.h"\r
+#include "arch.h"\r
+#include "Os.h"\r
+\r
+void Os_GetStackInfo( TaskType task, StackInfoType *s) {\r
+\r
+ pcb_t *pcb = os_get_pcb(task);\r
+\r
+ s->curr = os_arch_get_stackptr();\r
+ s->top = pcb->stack.top;\r
+ s->at_swap = pcb->stack.curr;\r
+ s->size = pcb->stack.size;\r
+ s->usage = (void *)os_arch_get_stack_usage(pcb);\r
+}\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+#include "types.h"\r
+#include "pcb.h"\r
+#include "arch.h"\r
+#include "debug.h"\r
+//#include "arch_offset.h"\r
+#include "sys.h"\r
+#include "kernel.h"\r
+#include "assert.h"\r
+#include "swap.h"\r
+#include "task_i.h"\r
+#include "hooks.h"\r
+#include "internal.h"\r
+\r
+\r
+#define USE_DEBUG\r
+#include "Trace.h"\r
+\r
+// we come here from\r
+// - WaitEvent()\r
+// old_pcb -> WAITING\r
+// new_pcb -> READY(RUNNING)\r
+// - Schedule(),\r
+// old_pcb -> READY\r
+// new_pcb -> READY/RUNNING\r
+\r
+/*\r
+ * two strategies\r
+ * 1. When running ->\r
+ * - remove from ready queue\r
+ * - set state == ST_RUNNING\r
+ *\r
+ * 2. When running ->\r
+ * * leave in ready queue\r
+ * * set state == ST_RUNNING\r
+ * - ready queue and ST_READY not the same\r
+ * + No need to remove the running process from ready queue\r
+ */\r
+\r
+\r
+\r
+/**\r
+ * Swap context, from one pcb to another\r
+ */\r
+void os_swap_context(pcb_t *old_pcb, pcb_t *new_pcb ) {\r
+\r
+ POSTTASKHOOK();\r
+\r
+ assert(new_pcb!=NULL);\r
+\r
+ os_resource_release_internal();\r
+\r
+ if( !os_arch_stack_endmark_ok(old_pcb) ) {\r
+ ShutdownOS(E_OS_STACKFAULT);\r
+ }\r
+\r
+#if 0\r
+ // Make a simple stack check for prio procs...\r
+ // See OS068, Autosar SWS\r
+ {\r
+ uint32_t stackp = (uint32_t)os_arch_get_stackptr();\r
+ uint32_t smallc_size = os_arch_get_sc_size();\r
+\r
+ // enough size to place a small context on the stack\r
+ // top( low address ) + small context > current stackpointer\r
+ if( (uint32_t)(old_pcb->stack.top + smallc_size) > stackp ) {\r
+ ShutdownOS(E_OS_STACKFAULT);\r
+ }\r
+ }\r
+#endif\r
+\r
+// os_arch_print_context("NEW:",new_pcb);\r
+ os_arch_swap_context(old_pcb,new_pcb);\r
+\r
+\r
+ {\r
+ pcb_t *t_pcb = os_get_curr_pcb();\r
+// dbg_printf("New pcb: %s\n",t_pcb->name);\r
+ os_pcb_make_running(t_pcb);\r
+ }\r
+ os_resource_get_internal();\r
+ PRETASKHOOK();\r
+}\r
+\r
+// We come here from\r
+// - os_init\r
+\r
+/**\r
+ * Called when a task is to be run for the first time.\r
+ */\r
+void os_swap_context_to(pcb_t *old_pcb, pcb_t *new_pcb ) {\r
+ os_arch_swap_context_to(old_pcb,new_pcb);\r
+ /* TODO: When do we return here ?? */\r
+}\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+#include "Os.h"\r
+#include "pcb.h"\r
+#include "sys.h"\r
+#include "internal.h"\r
+#include "hooks.h"\r
+#include <stdlib.h>\r
+#include "swap.h"\r
+#include "task_i.h"\r
+#include "Ramlog.h"\r
+\r
+StatusType GetTaskState(TaskType TaskId, TaskStateRefType State) {\r
+ state_t curr_state = os_pcb_get_state(os_get_pcb(TaskId));\r
+ StatusType rv = E_OK;\r
+\r
+ // TODO: Lazy impl. for now */\r
+ switch(curr_state) {\r
+ case ST_RUNNING: *State = TASK_STATE_RUNNING; break;\r
+ case ST_WAITING: *State = TASK_STATE_WAITING; break;\r
+ case ST_SUSPENDED: *State = TASK_STATE_SUSPENDED; break;\r
+ case ST_READY: *State = TASK_STATE_READY; break;\r
+ }\r
+\r
+ // Prevent label warning. Remove when proper error handling is implemented.\r
+ if (0) goto err;\r
+\r
+ OS_STD_END_2(OSServiceId_GetTaskState,TaskId, State);\r
+}\r
+\r
+StatusType GetTaskID( TaskRefType task_id ) {\r
+ *task_id = os_sys.curr_pcb->pid;\r
+ return E_OK;\r
+}\r
+\r
+/**\r
+ * The task <TaskID> is transferred from the suspended state into\r
+ * the ready state. The operating system ensures that the task\r
+ * code is being executed from the first statement.\r
+ *\r
+ * The service may be called from interrupt level and from task\r
+ * level (see Figure 12-1).\r
+ * Rescheduling after the call to ActivateTask depends on the\r
+ * place it is called from (ISR, non preemptable task, preemptable\r
+ * task).\r
+ *\r
+ * If E_OS_LIMIT is returned the activation is ignored.\r
+ * When an extended task is transferred from suspended state\r
+ * into ready state all its events are cleared.\r
+ *
+ * @param pid
+ * @return
+ */\r
+\r
+StatusType ActivateTask( TaskType TaskID ) {\r
+ long msr;\r
+ pcb_t *pcb = os_get_pcb(TaskID);\r
+ StatusType rv = E_OK;\r
+\r
+ os_isr_printf(D_TASK,"ActivateTask %s\n",pcb->name);\r
+\r
+ Irq_Save(msr);\r
+\r
+ // TODO: It doesn't say anything about if we do this\r
+ // on a waiting task!\r
+ if( !os_pcb_pid_valid(pcb) ) {\r
+ ramlog_str("E_OS_ID\n");\r
+ ramlog_str(pcb->name);\r
+ ramlog_hex(pcb->pid);\r
+ rv = E_OS_ID;\r
+ goto err;\r
+ }\r
+\r
+ if( os_pcb_get_state(pcb) != ST_SUSPENDED ) {\r
+ ramlog_str("#E_OS_LIMIT\n");\r
+ ramlog_str(pcb->name);\r
+ ramlog_hex(pcb->pid);\r
+ ramlog_str(" ");\r
+ ramlog_hex(pcb->state);\r
+ ramlog_str(" ");\r
+ rv = E_OS_LIMIT;\r
+ goto err;\r
+\r
+ } else {\r
+ /* TODO: This makes some things double.. cleanup is needed */\r
+ os_pcb_make_virgin(pcb);\r
+ }\r
+\r
+ os_pcb_make_ready(pcb);\r
+ Irq_Restore(msr);\r
+\r
+ // Following chapter 4.6.1 in OSEK/VDX here it seems we should re-schedule.\r
+ if( (pcb->scheduling == SCHEDULING_FULL) && (os_sys.int_nest_cnt == 0) ) {\r
+ Schedule();\r
+ }\r
+\r
+ OS_STD_END_1(OSServiceId_ActivateTask,TaskID);\r
+}\r
+\r
+extern void os_pcb_make_virgin(pcb_t *pcb);\r
+\r
+StatusType TerminateTask( void ) {\r
+ pcb_t *curr_pcb = os_get_curr_pcb();\r
+ pcb_t *new_pcb;\r
+ StatusType rv = E_OK;\r
+\r
+ os_std_printf(D_TASK,"TerminateTask %s\n",curr_pcb->name);\r
+\r
+ Irq_Disable();\r
+\r
+ os_pcb_make_suspended(curr_pcb);\r
+\r
+ // Schedule any process\r
+ new_pcb = os_find_top_prio_proc();\r
+ assert(new_pcb!=NULL);\r
+ os_swap_context(curr_pcb,new_pcb);\r
+\r
+ Irq_Enable();\r
+ // It must find something here...otherwise something is very wrong..\r
+ assert(0);\r
+\r
+ rv = E_NOT_OK;\r
+ goto err;\r
+\r
+\r
+ OS_STD_END(OSServiceId_TerminateTask);\r
+}\r
+\r
+StatusType ChainTask( TaskType TaskId ) {\r
+ StatusType rv;\r
+ Irq_Disable();\r
+ rv = ActivateTask(TaskId);\r
+ /* TODO: more more here..*/\r
+ TerminateTask();\r
+ Irq_Enable();\r
+\r
+ if (rv != E_OK) goto err;\r
+\r
+ OS_STD_END_1(OSServiceId_ChainTask,TaskId);\r
+}\r
+\r
+/**\r
+ * If a higher-priority task is ready, the internal resource of the task\r
+ * is released, the current task is put into the ready state, its\r
+ * context is saved and the higher-priority task is executed.\r
+ * Otherwise the calling task is continued.\r
+ *\r
+ * TODO: The OSEK spec says a lot of strange things under "particulareties"\r
+ * that I don't understand\r
+ *
+ */\r
+StatusType Schedule( void ) {\r
+ pcb_t *pcb;\r
+ pcb_t *curr_pcb = get_curr_pcb();\r
+ StatusType rv = E_OK;\r
+\r
+ Irq_Disable();\r
+ /* Try to find higher prio task that is ready, if none, continue */\r
+ pcb = os_find_top_prio_proc();\r
+\r
+ /* Swap if we found any process */\r
+ if( pcb != curr_pcb ) {\r
+ /* Add us to the ready list */\r
+ os_pcb_running_to_ready(curr_pcb);\r
+ os_swap_context(curr_pcb,pcb);\r
+ }\r
+ Irq_Enable();\r
+\r
+ // Prevent label warning. Remove this when proper error handling is implemented.\r
+ if (0) goto err;\r
+\r
+ OS_STD_END(OSServiceId_Schedule);\r
+}\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+#include "Os.h"\r
+#include "pcb.h"\r
+#include "sys.h"\r
+#include <stdlib.h>\r
+//#include "arch_offset.h"\r
+#include "hooks.h"\r
+#include "task_i.h"\r
+#include "arch.h"\r
+#include "ext_config.h"\r
+#include "assert.h"\r
+#include "internal.h"\r
+\r
+_Bool os_pcb_pid_valid( pcb_t *restrict pcb ) {\r
+ return ( pcb->pid > Oil_GetTaskCnt() ) ? 0 : 1;\r
+}\r
+/**\r
+ * Start an extended task.\r
+ * Tasks done:\r
+ * - Grab the internal resource for the process\r
+ * - Set it running state.\r
+ * - Start to execute the process\r
+ *\r
+ */\r
+void os_proc_start_extended( void ) {\r
+ pcb_t *pcb;\r
+\r
+ // TODO: Get internal resource\r
+ PRETASKHOOK();\r
+\r
+ pcb = os_get_curr_pcb();\r
+ os_resource_get_internal();\r
+ os_pcb_make_running(pcb);\r
+\r
+ os_arch_first_call();\r
+\r
+ // If we have a extented process that that exits, we end up here\r
+ // See OS052,OS069, Autosar SWS\r
+ ERRORHOOK(E_OS_MISSINGEND);\r
+\r
+ /* TODO: Terminate the task */\r
+ //while(1);\r
+}\r
+\r
+/**\r
+ * Start an basic task.\r
+ * See extended task.\r
+ */\r
+\r
+void os_proc_start_basic( void ) {\r
+ pcb_t *pcb;\r
+\r
+ // TODO: Get internal resource\r
+ PRETASKHOOK();\r
+\r
+ pcb = os_get_curr_pcb();\r
+ os_resource_get_internal();\r
+ os_pcb_make_running(pcb);\r
+ os_arch_first_call();\r
+\r
+ TerminateTask();\r
+// ERRORHOOK(E_OS_MISSINGEND);\r
+}\r
+\r
+/**\r
+ * Setup the context for a pcb. The context differs for different arch's\r
+ * so we call the arch dependent functions also.\r
+ * The context at setup is always a small context.\r
+ *
+ * @param pcb Ptr to the pcb to setup context for.
+ */\r
+void os_setup_context( pcb_t *pcb ) {\r
+ uint8_t *bottom;\r
+\r
+ /* Find bottom of the stack so that we can place the\r
+ * context there.\r
+ *\r
+ * stack bottom = high address. stack top = low address\r
+ */\r
+ bottom = (uint8_t *)pcb->stack.top + pcb->stack.size;\r
+ pcb->stack.curr = bottom;\r
+ // TODO: aligments here..\r
+ // TODO :use function os_arch_get_call_size() ??\r
+\r
+ // Make some space for back-chain.\r
+ bottom -= 16;\r
+ // Set the current stack so that it points to the context\r
+ pcb->stack.curr = bottom - os_arch_get_sc_size();\r
+\r
+ os_arch_setup_context(pcb);\r
+}\r
+\r
+/**\r
+ * Search for a specific task in the pcb list.\r
+ *
+ * @param tid The task id to search for
+ * @return Ptr to the found pcb or NULL
+ */\r
+pcb_t *os_find_task( TaskType tid ) {\r
+ pcb_t *i_pcb;\r
+\r
+ /* TODO: Implement this as an array */\r
+ TAILQ_FOREACH(i_pcb,& os_sys.pcb_head,pcb_list) {\r
+ if(i_pcb->pid == tid ) {\r
+ return i_pcb;\r
+ }\r
+ }\r
+ assert(0);\r
+ return NULL;\r
+}\r
+\r
+/**\r
+ * Adds a pcb to the list of pcb's
+ * @param pcb
+ */\r
+TaskType os_add_task( pcb_t *pcb ) {\r
+\r
+ DisableAllInterrupts();\r
+\r
+ pcb->pid = os_sys.task_cnt;\r
+ // Add to list of PCB's\r
+ TAILQ_INSERT_TAIL(& os_sys.pcb_head,pcb,pcb_list);\r
+ os_sys.task_cnt++;\r
+ EnableAllInterrupts();\r
+\r
+ return pcb->pid;\r
+}\r
+\r
+\r
+#define PRIO_ILLEGAL -100\r
+// TODO: we can't have O(n) search here.. hash on prio instead\r
+\r
+/**\r
+ * Find the top priority task. Even the running task is included.\r
+ *
+ * @return
+ */\r
+\r
+pcb_t *os_find_top_prio_proc( void ){\r
+ pcb_t *i_pcb;\r
+ pcb_t *top_prio_pcb = NULL;\r
+ prio_t top_prio = PRIO_ILLEGAL;\r
+\r
+ os_isr_printf(D_TASK,"os_find_top_prio_proc\n");\r
+\r
+ TAILQ_FOREACH(i_pcb,& os_sys.ready_head,ready_list) {\r
+ // all ready task are canidates\r
+ if( i_pcb->state & (ST_READY|ST_RUNNING)) {\r
+ if( top_prio != PRIO_ILLEGAL ) {\r
+ if( i_pcb->prio > top_prio ) {\r
+ top_prio = i_pcb->prio;\r
+ top_prio_pcb = i_pcb;\r
+ }\r
+ } else {\r
+ top_prio = i_pcb->prio;\r
+ top_prio_pcb = i_pcb;\r
+ }\r
+ } else {\r
+ assert(0);\r
+ }\r
+ }\r
+ os_isr_printf(D_TASK,"Found %s\n",top_prio_pcb->name);\r
+\r
+ return top_prio_pcb;\r
+}\r
+\r
+\r
+/**\r
+ * Used at startup to initialize a pcb. Is sometimes\r
+ * used to restore the state of a basic process.\r
+ *
+ * @param pcb The pcb to make virgin
+ */\r
+\r
+void os_pcb_make_virgin( pcb_t *pcb ) {\r
+ if( pcb->autostart ) {\r
+ os_pcb_make_ready(pcb);\r
+ } else {\r
+ pcb->state = ST_SUSPENDED;\r
+ }\r
+\r
+ /* TODO: cleanup resource here ?? */\r
+ pcb->ev_set = 0;\r
+ pcb->ev_wait = 0;\r
+\r
+ os_setup_context(pcb);\r
+}\r
+\r
+#if 0\r
+pcb_t *os_find_higher_priority_task( prio_t prio ) {\r
+ pcb_t *i_pcb;\r
+ pcb_t *h_prio_pcb = NULL;\r
+ prio_t t_prio = prio;\r
+\r
+ TAILQ_FOREACH(i_pcb,& os_sys.ready_head,ready_list) {\r
+ if( i_pcb->prio > t_prio ) {\r
+ t_prio = i_pcb->prio;\r
+ h_prio_pcb = i_pcb;\r
+ }\r
+ }\r
+ return h_prio_pcb;\r
+}\r
+#endif\r
+\r
+\r
--- /dev/null
+\r
+MOD_USE+=KERNEL MCU T32_TERM\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+\r
+/*\r
+ * Configuration\r
+ * ------------------------------------------------\r
+ * 3 Tasks\r
+ * - 3 extended ( do NOT terminate )\r
+ * - 3 basic ( terminate )\r
+ *\r
+ * 2 Counters\r
+ * - 1 system timer\r
+ * - 1 soft( incremented with IncrementCounter(X) )\r
+ *\r
+ *\r
+ * 2 Alarms\r
+ * - 1 hardware alarm\r
+ * - 1 soft alarm\r
+ * - Running on the soft counter above\r
+ * - Triggers the basic task through ActivateTask() in alarm\r
+ *\r
+ * 2 ISRs\r
+ * - 1 ISR type 1\r
+ * - 1 ISR type, system counter\r
+ *\r
+ * 1 Schedule Table\r
+ * - Running on the system timer\r
+ * - Using 3 Tasks\r
+ *\r
+ *\r
+ *\r
+ * System timer\r
+ * ----------------------------------\r
+ * A system MUST have a system counter to function. This is almost\r
+ * always a hardware timer. So where is this timer configured?\r
+ *\r
+ * decrementer exception\r
+ * --> generate a prioritised interrupt through INTC soft interrupt\r
+ *\r
+ * Using the decrementer without generating the soft interrupt is not\r
+ * recommended since it's not prioritised( it's and exception that blocks\r
+ * interrupts from INTC )\r
+ *\r
+ * The timers are initialized in EcuM() using Gpt_Init(X). A StartupHook() must\r
+ * be used to start the timer. Example\r
+ *\r
+ * Gpt_StartTimer( GPT_CHANNEL_DEC, 10000UL);\r
+ * Gpt_EnableNotification(GPT_CHANNEL_DEC);\r
+ *\r
+ * Note!\r
+ * The counter configuration, e.g. timeout is not yet configured\r
+ * through the counter in the configuration.\r
+ *\r
+ * ISR's\r
+ * ----------------------------------\r
+ * dec_exception ( From Mcu_Exception.S )\r
+ * This exception installed HARD in the exception_tbl( Mcu_Exceptions )\r
+ *\r
+ *\r
+ * Note!\r
+ * - Do NOT use internal resource unless you are very sure that you to it right..\r
+ *\r
+ *\r
+ *
+ */\r
+\r
+#include <stdlib.h>\r
+#include <stdint.h>\r
+#include "os_config_macros.h"\r
+#include "Platform_Types.h"\r
+#include "Os.h" // includes Os_Cfg.h\r
+#include "os_test.h"\r
+#include "kernel.h"\r
+#include "kernel_offset.h"\r
+#include "alist_i.h"
+#include "Mcu.h"\r
+\r
+extern void dec_exception( void );\r
+\r
+// atleast 1\r
+#define SERVICE_CNT 1\r
+\r
+GEN_TRUSTEDFUNCTIONS_LIST\r
+\r
+\r
+//-------------------------------------------------------------------\r
+\r
+GEN_APPLICATION_HEAD {\r
+ GEN_APPLICATON(0,"application_1",true,NULL,NULL,NULL , 0,0,0,0,0,0 )\r
+};\r
+//-------------------------------------------------------------------\r
+\r
+#define ALIGN_16(x) (((x)>>4)<<4)\r
+\r
+//\r
+uint8 stack_OsIdle[STACK_SIZE_OsIdle] SECTION_BSS_SUPER;\r
+uint8 stack_etask_master[STACK_SIZE_etask_master] SECTION_BSS_SUPER;\r
+uint8 stack_etask_sup_l[STACK_SIZE_etask_sup_l] SECTION_BSS_SUPER;\r
+uint8 stack_etask_sup_m[STACK_SIZE_etask_sup_m] SECTION_BSS_SUPER;\r
+uint8 stack_etask_sup_h[STACK_SIZE_etask_sup_h] SECTION_BSS_SUPER;\r
+uint8 stack_btask_sup_l[STACK_SIZE_btask_sup_l] SECTION_BSS_SUPER;\r
+uint8 stack_btask_sup_m[STACK_SIZE_btask_sup_m] SECTION_BSS_SUPER;\r
+uint8 stack_btask_sup_h[STACK_SIZE_btask_sup_h] SECTION_BSS_SUPER;\r
+\r
+#define INTC_VECTOR_EXCEPTION_DEC (320+10)\r
+#define INTC_VECTOR_SSCIR0 0\r
+#define INTC_VECTOR_SSCIR7 7\r
+\r
+//-------------------------------------------------------------------\r
+\r
+GEN_RESOURCE_HEAD {\r
+ GEN_RESOURCE(RES_SCHEDULER,RESOURCE_TYPE_STANDARD,0,0,0), // Standard resource..\r
+// Internal resources\r
+ GEN_RESOURCE(1,RESOURCE_TYPE_INTERNAL,8, APPLICATION_ID_application_1,(1<<TASK_ID_etask_sup_l)),\r
+// external resource\r
+ GEN_RESOURCE(2,RESOURCE_TYPE_STANDARD,0,0,0),\r
+};\r
+\r
+//-------------------------------------------------------------------\r
+\r
+GEN_TASK_HEAD {\r
+\r
+ GEN_ETASK(OsIdle,0,true/*auto*/, NULL/*tm*/, APPLICATION_ID_application_1/*app*/,NULL/*rsrc*/),\r
+\r
+/* extended */\r
+ GEN_ETASK(etask_master,1,true/*auto*/, NULL/*tm*/, APPLICATION_ID_application_1/*app*/,NULL/*rsrc*/),\r
+\r
+ GEN_ETASK(etask_sup_l,2,false/*auto*/, NULL/*tm*/, APPLICATION_ID_application_1/*app*/,NULL/*rsrc*/),\r
+ GEN_ETASK(etask_sup_m,3,false/*auto*/, NULL/*tm*/, APPLICATION_ID_application_1/*app*/,NULL/*rsrc*/),\r
+ GEN_ETASK(etask_sup_h,4,false/*auto*/, NULL/*tm*/, APPLICATION_ID_application_1/*app*/,NULL/*rsrc*/),\r
+\r
+/* basic */\r
+ GEN_BTASK(btask_sup_l,2,false/*auto*/, NULL/*tm*/, APPLICATION_ID_application_1/*app*/,NULL/*rsrc*/),\r
+ GEN_BTASK(btask_sup_m,3,false/*auto*/, NULL/*tm*/, APPLICATION_ID_application_1/*app*/,NULL/*rsrc*/),\r
+ GEN_BTASK(btask_sup_h,4,false/*auto*/, NULL/*tm*/, APPLICATION_ID_application_1/*app*/,NULL/*rsrc*/),\r
+\r
+ GEN_ISR_2( TASK_ID_os_tick, "dec", OsTick, /*prio*/ 11, /*type*/ PROC_ISR2, INTC_VECTOR_EXCEPTION_DEC , NULL, APPLICATION_ID_application_1),\r
+#if 0\r
+ // Use the intc_vector tables for now\r
+ GEN_ISR_2( TASK_ID_isr_dec, "dec", my_dec, /*prio*/ 11, /*type*/ PROC_ISR2, INTC_VECTOR_EXCEPTION_DEC , NULL, APPLICATION_ID_application_1),\r
+ GEN_ISR_1( TASK_ID_isr_soft7, "exception_sc", my_intc_soft7, /*prio*/ 12, INTC_VECTOR_SSCIR7 ),\r
+#endif\r
+};\r
+\r
+\r
+GEN_PCB_LIST()\r
+\r
+//-------------------------------------------------------------------\r
+typedef void (*exc_func_t)(uint32_t *);\r
+\r
+// Print all to stdout\r
+uint32 os_dbg_mask = 0;\r
+\r
+#if 0\r
+uint32 os_dbg_mask = \\r
+ D_MASTER_PRINT |\\r
+ D_ISR_MASTER_PRINT |\\r
+ D_STDOUT |\\r
+ D_ISR_STDOUT;\r
+#endif\r
+\r
+\r
+// D_ALARM | D_TASK;\r
+\r
+// --- INTERRUPTS ---
+
+uint8_t os_interrupt_stack[OS_INTERRUPT_STACK_SIZE] __attribute__ ((aligned (0x10)));
+
+// The vector table
+void * intc_vector_tbl[NUMBER_OF_INTERRUPTS_AND_EXCEPTIONS] __attribute__ ((aligned (0x1000),section(".data")))= {
+};
+
+// The type of vector
+uint8 intc_type_tbl[NUMBER_OF_INTERRUPTS_AND_EXCEPTIONS] = {
+};
+\r
+\r
+//-------------------------------------------------------------------\r
+\r
+// Generate as <type> <msg_name>_data\r
+#ifdef ALARM_USE\r
+int MsgRx_1_data;\r
+int MsgTx_1_data;\r
+\r
+message_obj_t message_list[] = {\r
+{\r
+ .property = RECEIVE_UNQUEUED_INTERNAL,\r
+ .data = &MsgRx_1_data,\r
+ .data_size = sizeof(MsgRx_1_data),\r
+\r
+},\r
+{\r
+ .property = SEND_STATIC_INTERNAL,\r
+ .data = &MsgTx_1_data,\r
+ .data_size = sizeof(MsgTx_1_data),\r
+},\r
+};\r
+#endif\r
+\r
+\r
+#if 0\r
+#define MESSAGE_CLASS(_name,_ctype ,_property,_queued ,_notification) \\r
+ struct message ## _name ## _s { \\r
+ _ctype a; \\r
+ };\r
+\r
+MESSAGE_CLASS(rx1,int,,,);\r
+#endif\r
+\r
+/*\r
+typedef struct {\r
+ message_type_t type; // RECEIVE_UNQUEUED_INTERNAL, RECEIVE_QUEUE_INTERNAL\r
+ MessageType send_id;\r
+ message_notification_t *notification;\r
+ void *queue_data;\r
+ uint32 queue_size;\r
+} message_rx_t;\r
+\r
+#define DeclareMessage(x) (x)\r
+\r
+#define msgTx_1 0\r
+#define msgRx_1 1\r
+*/\r
+\r
+//-------------------------------------------------------------------\r
+#if MESSAGE_USE!=0\r
+\r
+\r
+// SEND_STATIC_INTERNAL is the only message that needs an object\r
+\r
+\r
+\r
+// RECEIVE_UNQUEUED_INTERNAL, RECEIVE_QUEUE_INTERNAL have notification and\r
+\r
+\r
+\r
+#endif\r
+//-------------------------------------------------------------------\r
+\r
+//#define COUNTER_SOFT_1 1\r
+//#define EVENT_1 1\r
+\r
+\r
+GEN_COUNTER_HEAD {\r
+ GEN_COUNTER(COUNTER_ID_os_tick, "OS_TICK_COUNTER",COUNTER_TYPE_HARD,\r
+ COUNTER_UNIT_NANO, 0xffff,1,1,0 ),\r
+ GEN_COUNTER(COUNTER_ID_soft_1, "counter_soft_1",COUNTER_TYPE_SOFT,\r
+ COUNTER_UNIT_NANO, 10,1,1,0),\r
+ GEN_COUNTER(COUNTER_ID_soft_2, "counter_soft_2",COUNTER_TYPE_SOFT,\r
+ COUNTER_UNIT_NANO, 100,1,1,0),\r
+};\r
+\r
+//-------------------------------------------------------------------\r
+\r
+#ifdef ALARM_USE\r
+GEN_ALARM_HEAD {\r
+ {\r
+ .counter = &counter_list[OS_TICK_COUNTER],\r
+ .counter_id = OS_TICK_COUNTER,\r
+ .action =\r
+ {\r
+ .type = ALARM_ACTION_ACTIVATETASK,\r
+ .task_id = TASK_ID_btask_sup_h,\r
+ .event_id = 0,\r
+ }\r
+ },\r
+ {\r
+ /* Set EVENT_1 in etask_sup_m, driven by soft counter */\r
+ .counter = &counter_list[OS_TICK_COUNTER],\r
+ .counter_id = OS_TICK_COUNTER,\r
+ .action = {\r
+ .type = ALARM_ACTION_SETEVENT,\r
+ .task_id = TASK_ID_etask_sup_m,\r
+ .event_id = EVENT_1,\r
+ }\r
+ },{\r
+ /* Set EVENT_1 in etask_sup_m, driven by counter_soft_1 */\r
+ .counter = &counter_list[COUNTER_ID_soft_1],\r
+ .counter_id = COUNTER_ID_soft_1,\r
+ .action = {\r
+ .type = ALARM_ACTION_SETEVENT,\r
+ .task_id = TASK_ID_etask_sup_m,\r
+ .event_id = EVENT_1,\r
+ }\r
+ },{\r
+ .counter = &counter_list[COUNTER_ID_soft_1],\r
+ .counter_id = COUNTER_ID_soft_1,\r
+ .action = {\r
+ .type = ALARM_ACTION_INCREMENTCOUNTER,\r
+ .counter_id = COUNTER_ID_soft_2,\r
+ }\r
+ }\r
+};\r
+#endif\r
+\r
+//-------------------------------------------------------------------\r
+\r
+\r
+#if defined(SCHEDULETABLE_USE)\r
+\r
+\r
+sched_action_t sched_expire_list_0[] = {\r
+ {\r
+ .type = SCHEDULE_ACTION_ACTIVATETASK,\r
+ .offset = 5,\r
+ .task_id = TASK_ID_etask_sup_m,\r
+ },{\r
+ .type = SCHEDULE_ACTION_SETEVENT,\r
+ .offset = 7,\r
+ .task_id = TASK_ID_etask_sup_m,\r
+ .event_id = EVENT_2,\r
+ }\r
+};\r
+\r
+\r
+sched_action_t sched_expire_list_1[] = {\r
+ {\r
+ .type = SCHEDULE_ACTION_ACTIVATETASK,\r
+ .offset = 2,\r
+ .task_id = TASK_ID_etask_sup_m,\r
+ }\r
+};\r
+\r
+\r
+GEN_SCHEDULETABLE_HEAD {\r
+ GEN_SCHEDULETABLE(\r
+ 0, // id\r
+ "stable0", // name\r
+ COUNTER_ID_soft_2, // counter\r
+ 1, // periodic\r
+ SCHEDULETABLE_DURATION_1, // duration\r
+ 0, // app_mask\r
+ ARRAY_SIZE(sched_expire_list_0), // action count\r
+ sched_expire_list_0, // expire ref\r
+ 0,0,0,0, // autostart\r
+ NONE,0, // sync\r
+ 0,0 // adjExpPoint\r
+ ),\r
+\r
+ GEN_SCHEDULETABLE(\r
+ 1, // id\r
+ "stable1", // name\r
+ COUNTER_ID_soft_2, // counter\r
+ 1, // periodic\r
+ SCHEDULETABLE_DURATION_2, // duration\r
+ 0, // app_mask\r
+ ARRAY_SIZE(sched_expire_list_1), // action count\r
+ sched_expire_list_1, // expire ref\r
+ 0,0,0,0, // autostart\r
+ NONE,0, // sync\r
+ 0,0 // adjExpPoint\r
+ ),\r
+};\r
+\r
+#endif\r
+\r
+\r
+// --- HOOKS ---\r
+\r
+struct os_conf_global_hooks_s os_conf_global_hooks = {\r
+ .StartupHook = StartupHook,\r
+ .ProtectionHook = ProtectionHook,\r
+ .ShutdownHook = ShutdownHook,\r
+ .ErrorHook = ErrorHook,\r
+ .PreTaskHook = PreTaskHook,\r
+ .PostTaskHook = PostTaskHook,\r
+};\r
+\r
+\r
+#include "os_config_funcs.h"\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*\r
+ * Os_Cfg.h\r
+ *\r
+ * Created on: 2008-dec-22\r
+ * Author: mahi\r
+ */\r
+\r
+#ifndef OS_CFG_H_\r
+#define OS_CFG_H_\r
+\r
+/* os_config.h */\r
+\r
+#define APPLICATION_ID_application_1 0\r
+#define APPLICATION_CNT 1\r
+\r
+#define TASK_ID_OsIdle 0\r
+#define TASK_ID_etask_master 1\r
+#define TASK_ID_etask_sup_l 2\r
+#define TASK_ID_etask_sup_m 3\r
+#define TASK_ID_etask_sup_h 4\r
+#define TASK_ID_btask_sup_l 5\r
+#define TASK_ID_btask_sup_m 6\r
+#define TASK_ID_btask_sup_h 7\r
+\r
+#define TASK_ID_os_tick 8\r
+\r
+#define PRIO_STACK_SIZE 1024\r
+\r
+#define STACK_SIZE_OsIdle ALIGN_16(PRIO_STACK_SIZE)\r
+#define STACK_SIZE_etask_master ALIGN_16(PRIO_STACK_SIZE)\r
+#define STACK_SIZE_etask_sup_l ALIGN_16(PRIO_STACK_SIZE)\r
+#define STACK_SIZE_etask_sup_m ALIGN_16(PRIO_STACK_SIZE)\r
+#define STACK_SIZE_etask_sup_h ALIGN_16(PRIO_STACK_SIZE)\r
+#define STACK_SIZE_btask_sup_l ALIGN_16(PRIO_STACK_SIZE)\r
+#define STACK_SIZE_btask_sup_m ALIGN_16(PRIO_STACK_SIZE)\r
+#define STACK_SIZE_btask_sup_h ALIGN_16(PRIO_STACK_SIZE)\r
+\r
+\r
+//#define TASK_ID_isr_dec 3\r
+//#define TASK_ID_isr_soft7 4\r
+\r
+#define RES_ID_INT_1 1\r
+#define RES_ID_EXT_1 2\r
+\r
+// OS_TICK_COUNTER located in Os.h\r
+// Driver all alarms\r
+#define COUNTER_ID_soft_1 1\r
+// Drives scheduletable 0\r
+#define COUNTER_ID_soft_2 2\r
+\r
+//\r
+// ScheduleTables\r
+//\r
+#define SCHEDULE_TABLE_0 0\r
+#define SCHEDULE_TABLE_1 1\r
+\r
+\r
+// NOT GENERATED( for test system only )\r
+#define SYSTEM_COUNTER_PERIOD 100\r
+#define SOFT_COUNTER_1_PERIOD 10\r
+#define SOFT_COUNTER_2_PERIOD 100\r
+\r
+#define SCHEDULETABLE_DURATION_1 10\r
+#define SCHEDULETABLE_DURATION_2 5\r
+\r
+#define ALARM_ID_c_sys_activate_btask_h 0\r
+#define ALARM_ID_c_sys_1_setevent_etask_m 1\r
+#define ALARM_ID_c_soft_1_setevent_etask_m 2\r
+#define ALARM_ID_c_soft_1_inc_counter_2 3\r
+\r
+// Don't start IDLE task...\r
+#undef USE_IDLE_TASK\r
+\r
+#define OS_INTERRUPT_STACK_SIZE 1024\r
+\r
+// The object that can actually be 0 is here..rest in os_config_funcs.h\r
+\r
+// Just define them if you want to use them.\r
+#define ALARM_USE 1\r
+#define SCHEDULETABLE_USE 1\r
+#undef MESSAGE_USE\r
+#define EVENT_USE 1\r
+#undef SERVICE_USE\r
+\r
+\r
+#define EVENT_0 (1<<0)\r
+#define EVENT_1 (1<<1)\r
+#define EVENT_2 (1<<2)\r
+\r
+\r
+\r
+#endif /* OS_CFG_H_ */\r
--- /dev/null
+\r
+# included from rules.mk\r
+\r
+# =======================================================================\r
+# APPLICATION\r
+\r
+obj-y += test_master.o\r
+obj-y += test_sup_01.o\r
+obj-y += test_sup_02.o\r
+obj-y += test_sup_03.o \r
+obj-y += test_framework.o\r
+\r
+obj-y += Os_Cfg.o\r
+\r
+# Grab the board the board files.\r
+include $(ROOTDIR)/boards/board_common.mk\r
+\r
+# What modules do we use\r
+MOD_USE+=KERNEL MCU\r
+\r
+MOD_USE+=T32_TERM\r
+#MOD_USE+=PROTECTIONHOOK STARTUPHOOK SHUTDOWNHOOK ERRORHOOK 1\r
+#MOD_USE+=PRETASKHOOK POSTTASKHOOK\r
+CFG+=CONSOLE_T32\r
+CFG+=CONSOLE_WINIDEA\r
+\r
+\r
+# TODO: Fix this....\r
+\r
+vpath-$(BUILD_TREE) += $(ROOTDIR)/$(ARCH_PATH-y)/kernel\r
+vpath-y += $(ROOTDIR)/$(ARCH_PATH-y)/drivers\r
+vpath-y += $(ROOTDIR)/boards/$(BOARDDIR)\r
+vpath-y += $(ROOTDIR)/boards/$(BOARDDIR)/config\r
+VPATH += $(vpath-y)\r
+VPATH += $(ROOTDIR)/$(SUBDIR)/config\r
+\r
+\r
+# libs needed by us \r
+libitem-y += $(ROOTDIR)/libs/libkernel_$(ARCH_MCU).a\r
+\r
+#linkfile\r
+ldcmdfile-y = -T $(ROOTDIR)/$(ARCH_PATH-y)/scripts/linkscript_gcc.ldf\r
+#ldcmdfile-y = -T $(ROOTDIR)/$(ARCH_PATH-y)/scripts/linkscript_gcc.ldf\r
+\r
+inc-y += ..\r
+inc-y += $(ROOTDIR)/system/kernel/$(objdir)\r
+inc-y += $(ROOTDIR)/system/kernel/include\r
+inc-y += $(ROOTDIR)/$(ARCH_PATH-y)\r
+inc-y += $(ROOTDIR)/drivers/include\r
+inc-y += $(ROOTDIR)/boards/$(BOARDDIR)/config\r
+inc-y += $(ROOTDIR)/$(ARCH_PATH-y)/drivers\r
+inc-y += ../config\r
+\r
+# What I want to build\r
+build-exe-y = $(target).elf\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*\r
+ * os_test.h\r
+ *\r
+ * Created on: 2009-jan-08\r
+ * Author: mahi\r
+ */\r
+\r
+#ifndef OS_TEST_H_\r
+#define OS_TEST_H_\r
+\r
+#include "test_framework.h"\r
+\r
+typedef void (*test_func_t)( void );\r
+\r
+#define TEST_FAIL(_text) test_fail((_text), __FILE__, __LINE__, __FUNCTION__ )\r
+#define TEST_OK() test_ok();\r
+#define TEST_ASSERT(_cond) if(!(_cond)) { TEST_FAIL(#_cond); }\r
+\r
+extern int test_suite;\r
+extern int test_nr;\r
+\r
+#if 1\r
+#define SECTION_SUP\r
+#define SECTION_USER\r
+#else\r
+#define SECTION_SUP __attribute__ ((section(".text_app_sup")))\r
+#define SECTION_USER __attribute__ ((section(".text_app_user")))\r
+#endif\r
+\r
+#define SECTION_BSS_SUPER __attribute__ ((aligned (16),section(".bss")))\r
+#define SECTION_BSS_USER __attribute__ ((aligned (16),section(".bss")))\r
+\r
+#define DECLARE_TASKS(_nr) \\r
+ void etask_sup_l_##_nr( void ); \\r
+ void etask_sup_m_##_nr( void ); \\r
+ void etask_sup_h_##_nr( void ); \\r
+ void btask_sup_l_##_nr( void ); \\r
+ void btask_sup_m_##_nr( void ); \\r
+ void btask_sup_h_##_nr( void );\r
+\r
+\r
+/*\r
+ * Declare tests
+ */\r
+\r
+// Test master processes\r
+void OsIdle(void );\r
+void etask_master( void );\r
+void etask_sup_l( void ) SECTION_SUP;\r
+void etask_sup_m( void ) SECTION_SUP;\r
+void etask_sup_h( void ) SECTION_SUP;\r
+\r
+void btask_sup_l( void ) SECTION_SUP;\r
+void btask_sup_m( void ) SECTION_SUP;\r
+void btask_sup_h( void ) SECTION_SUP;\r
+\r
+\r
+// Tests\r
+DECLARE_TASKS(01);\r
+DECLARE_TASKS(02);\r
+DECLARE_TASKS(03);\r
+\r
+#endif /* OS_TEST_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+#include "Platform_Types.h"\r
+\r
+#define USE_DEBUG\r
+#include "Trace.h"\r
+\r
+int test_suite = 1;\r
+int test_nr = 1;\r
+int _test_ok = 0;\r
+int _test_failed = 0;\r
+\r
+\r
+void test_done( void ) {\r
+ dbg_printf( "Test summary\n"\r
+ "Total: %d\n"\r
+ "OK : %d\n"\r
+ "FAIL : %d\n", _test_ok + _test_failed, _test_ok, _test_failed);\r
+\r
+}\r
+\r
+\r
+void test_fail( const char *text,char *file, int line, const char *function ) {\r
+ dbg_printf("%02d %02d FAILED, %s , %d, %s\n",test_suite, test_nr, file, line, function);\r
+ _test_failed++;\r
+}\r
+\r
+\r
+void test_ok( void ) {\r
+ dbg_printf("%02d %02d OK\n",test_suite, test_nr);\r
+ _test_ok++;\r
+}\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*\r
+ * test_framework.h\r
+ *\r
+ * Created on: 23 aug 2009\r
+ * Author: mahi\r
+ */\r
+\r
+#ifndef TEST_FRAMEWORK_H_\r
+#define TEST_FRAMEWORK_H_\r
+\r
+void test_done( void );\r
+\r
+void test_fail( char *text,char *file, int line , const char *function );\r
+void test_ok( void );\r
+\r
+#endif /* TEST_FRAMEWORK_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+#include "Os.h"\r
+#include <stdlib.h>\r
+#include "os_test.h"\r
+#include "Mcu.h"\r
+#if defined(USE_GPT)\r
+#include "Gpt.h"\r
+#endif\r
+\r
+#define USE_DEBUG\r
+#include "Trace.h"\r
+\r
+extern void etask_sup_l_basic_02( void );\r
+extern void etask_sup_m_basic_02( void );\r
+extern void etask_sup_h_basic_02( void );\r
+\r
+\r
+#define DECLARE_BASIC(_nr) \\r
+ extern void btest_sup_l_##_nr(void);\\r
+ extern void btest_sup_m_##_nr(void);\\r
+ extern void btest_sup_h_##_nr(void);\r
+\r
+DECLARE_BASIC(02);\r
+\r
+typedef struct {\r
+ uint32 nr;\r
+ uint32 sub_nr;\r
+ uint32 failed;\r
+} test_master_cfg_t;\r
+\r
+TaskType test_activate_pid_list[] =\r
+{\r
+/* 01*/ TASK_ID_etask_sup_l,\r
+/* 02*/ TASK_ID_etask_sup_l,\r
+/* 03*/ TASK_ID_etask_sup_l,\r
+};\r
+\r
+static int test_case = 0;\r
+\r
+/*\r
+ * Master test process, everything is controlled from here.\r
+ */\r
+void etask_master( void ) {\r
+ TaskType pid;\r
+\r
+ for( ; test_case < sizeof(test_activate_pid_list)/sizeof(TaskType); test_case++)\r
+ {\r
+ test_nr = 1;\r
+ dbg_printf("-----> Test Suite %02d\n",test_suite);\r
+ pid = test_activate_pid_list[test_case];\r
+ ActivateTask(pid);\r
+ // All test tasks are higher prio than we.. so this triggers them..\r
+ Schedule();\r
+ // All tasks in the test are now terminated...\r
+ // Start new tests..\r
+ test_suite++;\r
+ }\r
+\r
+ // Test complete..\r
+ while(1);\r
+\r
+}\r
+\r
+test_func_t etask_sup_matrix[][3] = {\r
+/* 01*/ { etask_sup_l_01, etask_sup_m_01, etask_sup_h_01},\r
+/* 02*/ { etask_sup_l_02, etask_sup_m_02, etask_sup_h_02},\r
+/* 03*/ { etask_sup_l_03, etask_sup_m_03, NULL},\r
+}; // __attribute__ ((section(".data_app_2")));\r
+\r
+#define TEST_BASIC(nr) \\r
+ { btest_sup_l_##nr , btest_sup_m_##nr , btest_sup_h_## nr }\r
+\r
+test_func_t btask_sup_matrix[][3] = {\r
+/* 01*/ { NULL, NULL, NULL},\r
+ TEST_BASIC(02),\r
+#if 0\r
+#endif\r
+}; // __attribute__ ((section(".data_app_2")));\r
+\r
+\r
+//--------------------------------------------------------------------\r
+//--------------------------------------------------------------------\r
+\r
+void etask_sup_l( void )\r
+{\r
+ test_func_t func;\r
+ func = etask_sup_matrix[test_case][0];\r
+ if( func != NULL )\r
+ func();\r
+\r
+ TerminateTask();\r
+}\r
+\r
+void etask_sup_m( void )\r
+{\r
+ test_func_t func;\r
+ func = etask_sup_matrix[test_case][1];\r
+ if( func != NULL )\r
+ func();\r
+\r
+ TerminateTask();\r
+}\r
+\r
+void etask_sup_h( void )\r
+{\r
+ test_func_t func;\r
+ func = etask_sup_matrix[test_case][2];\r
+ if( func != NULL )\r
+ func();\r
+\r
+ TerminateTask();\r
+}\r
+\r
+//--------------------------------------------------------------------\r
+//--------------------------------------------------------------------\r
+\r
+void btask_sup_l( void ) {\r
+ test_func_t func;\r
+ func = btask_sup_matrix[test_case][0];\r
+ if( func != NULL )\r
+ func();\r
+}\r
+void btask_sup_m( void ) {\r
+ test_func_t func;\r
+ func = btask_sup_matrix[test_case][1];\r
+ if( func != NULL )\r
+ func();\r
+}\r
+void btask_sup_h( void ) {\r
+ test_func_t func;\r
+ func = btask_sup_matrix[test_case][2];\r
+ if( func != NULL )\r
+ func();\r
+}\r
+\r
+\r
+void OsIdle(void ) {\r
+ for(;;);\r
+}\r
+\r
+\r
+/* Global hooks */\r
+ProtectionReturnType ProtectionHook( StatusType FatalError ) {\r
+ dbg_printf("## ProtectionHook\n");\r
+ return PRO_KILLAPPL;\r
+}\r
+\r
+void StartupHook( void ) {\r
+// dbg_printf("## StartupHook\n");\r
+\r
+#ifdef USE_MCU\r
+ uint32_t sys_freq = McuE_GetSystemClock();\r
+ dbg_printf("Sys clock %d Hz\n",sys_freq);\r
+ Frt_Init();\r
+ Frt_Start(sys_freq/1000);\r
+#endif\r
+}\r
+\r
+void ShutdownHook( StatusType Error ) {\r
+// dbg_printf("## ShutdownHook\n");\r
+ while(1);\r
+}\r
+\r
+void ErrorHook( StatusType Error ) {\r
+// dbg_printf("## ErrorHook err=%d\n",Error);\r
+ while(1);\r
+}\r
+\r
+void PreTaskHook( void ) {\r
+ TaskType task;\r
+ GetTaskID(&task);\r
+ if( task > 10 ) {\r
+ while(1);\r
+ }\r
+// dbg_printf("## PreTaskHook, taskid=%d\n",task);\r
+}\r
+\r
+void PostTaskHook( void ) {\r
+ TaskType task;\r
+ GetTaskID(&task);\r
+ if( task > 10 ) {\r
+ while(1);\r
+ }\r
+\r
+// dbg_printf("## PostTaskHook, taskid=%d\n",task);\r
+ {\r
+ StackInfoType si;\r
+ Os_GetStackInfo(task,&si);\r
+// dbg_printf("Stack usage %d%% (this=%08x, top=%08x, size=%08x,usage=%08x )\n",OS_STACK_USAGE(&si),si.curr, si.top,si.size,si.usage);\r
+ }\r
+}\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+/*\r
+ * Tested: Tasks
+ */\r
+\r
+//#include "Platform_Types.h"\r
+#include "Os.h"\r
+#include "debug.h"\r
+#include "os_test.h"\r
+//#include "test_cfg.h"\r
+\r
+#define EVENT_NR 1\r
+#define TASK_1 1\r
+#define TASK_2 2\r
+\r
+#define E_TEST_OUT_OF_SYNC 100\r
+\r
+\r
+//#define EVENT_1 1\r
+//#define EVENT_2 2\r
+\r
+DeclareResource(RES_1);\r
+\r
+//static int test = 1;\r
+\r
+void etask_sup_l_01( void ){\r
+\r
+ _Bool done = 0;\r
+\r
+ while(!done) {\r
+ switch( test_nr ) {\r
+ case 1:\r
+ ActivateTask(TASK_ID_etask_sup_m);\r
+ /* Switch to higher prio */\r
+ Schedule();\r
+ break;\r
+ case 4:\r
+ // From WaitEvent() in sup_m\r
+ TEST_OK();\r
+ ++test_nr;\r
+ // trigger sup_m to ready state(since it's waiting for the event)\r
+ SetEvent(TASK_ID_etask_sup_m,EVENT_1);\r
+ // Let SUP_M take the event\r
+ Schedule();\r
+ break;\r
+ case 7:\r
+ // We get scheduled again from sup_m\r
+ TEST_OK();\r
+ test_nr = 100;\r
+ break;\r
+\r
+ case 100:\r
+ SetEvent(TASK_ID_etask_sup_m,EVENT_1);\r
+ // Let SUP_M finish...\r
+ Schedule();\r
+ // The test case is done! Kill ourselves\r
+ TerminateTask();\r
+// done = 1;\r
+ break;\r
+ default:\r
+ TEST_FAIL("default in switch\n");\r
+// ErrorHook(E_TEST_OUT_OF_SYNC);\r
+ break;\r
+ }\r
+ }\r
+ // Cleanup\r
+\r
+\r
+}\r
+\r
+void etask_sup_m_01( void ){\r
+ _Bool done = 0;\r
+\r
+ while( !done ) {\r
+ switch( test_nr ) {\r
+ case 1:\r
+ TEST_OK();\r
+ ++test_nr;\r
+ break;\r
+ case 2:\r
+ Schedule();\r
+ // We should stay here\r
+ TEST_OK();\r
+ ++test_nr;\r
+ break;\r
+ case 3:\r
+ SetEvent(TASK_ID_etask_sup_l,EVENT_1);\r
+ // We should stay here since we are higher prio\r
+ TEST_OK();\r
+ ++test_nr;\r
+ break;\r
+ case 4:\r
+ // No event waiting so this should trigger sup_l\r
+ WaitEvent(EVENT_1);\r
+ break;\r
+ case 5:\r
+ TEST_OK();\r
+ ++test_nr;\r
+ break;\r
+ case 6:\r
+ // The event isn't cleared yet, so we should return right away\r
+ WaitEvent(EVENT_1);\r
+ TEST_OK();\r
+ ++test_nr;\r
+ break;\r
+ case 7:\r
+ ClearEvent(EVENT_1);\r
+ // Switch to sup_l\r
+ WaitEvent(EVENT_1);\r
+ break;\r
+ case 100:\r
+ TerminateTask();\r
+\r
+#if 0\r
+ ClearEvent(1);\r
+ done = 1;\r
+#endif\r
+ break;\r
+ default:\r
+ TEST_FAIL("default in switch");\r
+ ErrorHook(E_TEST_OUT_OF_SYNC);\r
+ }\r
+ }\r
+}\r
+\r
+void etask_sup_h_01( void ){\r
+\r
+}\r
+\r
+#if 0\r
+void test_sup_master( void ) {\r
+\r
+ for(;;) {\r
+ os_printf("test1_1,msr=%x\n",get_msr());\r
+\r
+ GetResource(RES_1);\r
+ ReleaseResource(RES_1);\r
+ SetEvent(TASK_2,EVENT_NR);\r
+ WaitEvent(EVENT_NR);\r
+ ClearEvent(EVENT_NR);\r
+ }\r
+}\r
+\r
+void test1_2( void ) {\r
+ for(;;) {\r
+ os_printf("test1_2,msr=%x\n",get_msr());\r
+ WaitEvent(EVENT_NR);\r
+ ClearEvent(EVENT_NR);\r
+ SetEvent(TASK_1,EVENT_NR);\r
+ }\r
+}\r
+#endif\r
+\r
+#if 0\r
+void idle_proc( void )\r
+{\r
+ for(;;) {}\r
+}\r
+#endif\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+/*\r
+ * Tested: alarms and events\r
+ *\r
+ *
+ */\r
+\r
+#include "Os.h"\r
+#include "Trace.h"\r
+#include <assert.h>\r
+#include "os_test.h"\r
+\r
+\r
+void etask_sup_l_02( void ) {\r
+\r
+ for(;;) {\r
+ switch(test_nr){\r
+ case 1:\r
+ ChainTask(TASK_ID_btask_sup_l);\r
+ break;\r
+ case 2:\r
+ /*\r
+ * Check GetAlarmBase()
+ */\r
+ TEST_OK();\r
+ {\r
+ AlarmBaseType alarm;\r
+ TickType tick;\r
+ GetAlarmBase(ALARM_ID_c_soft_1_setevent_etask_m,&alarm);\r
+ dbg_printf("Alarm %d,%d,%d\n", alarm.maxallowedvalue,\r
+ alarm.tickperbase,\r
+ alarm.mincycle);\r
+\r
+ /* Get ticks before alarm expires */\r
+ GetAlarm(TASK_ID_btask_sup_l,&tick);\r
+ test_nr = 3;\r
+ break;\r
+ }\r
+ case 3:\r
+ // Make cyclic alarm\r
+ SetRelAlarm(ALARM_ID_c_soft_1_setevent_etask_m, 2, 5);\r
+ ActivateTask(TASK_ID_etask_sup_m);\r
+ Schedule();\r
+ // Nothing should happen here\r
+ IncrementCounter(COUNTER_ID_soft_1);\r
+ // Trigger the event...\r
+ IncrementCounter(COUNTER_ID_soft_1); // 2\r
+ // Should trigger\r
+ Schedule();\r
+ break;\r
+ case 4:\r
+ IncrementCounter(COUNTER_ID_soft_1); // 3\r
+ IncrementCounter(COUNTER_ID_soft_1); // 4\r
+ IncrementCounter(COUNTER_ID_soft_1); // 5\r
+ IncrementCounter(COUNTER_ID_soft_1); // 1\r
+ Schedule();\r
+ IncrementCounter(COUNTER_ID_soft_1); // 2\r
+ Schedule();\r
+ CancelAlarm(ALARM_ID_c_soft_1_setevent_etask_m );\r
+ test_nr = 100;\r
+ break;\r
+ case 100:\r
+ TerminateTask();\r
+ break;\r
+ default:\r
+ assert(0);\r
+ while(1);\r
+ }\r
+ }\r
+//SetAbsAlarm(TASK_ID_btask_sup_l,1000,0);\r
+\r
+ while(1);\r
+}\r
+\r
+void etask_sup_m_02( void ) {\r
+ while(1) {\r
+ switch(test_nr) {\r
+ case 3:\r
+ WaitEvent(EVENT_1);\r
+ ClearEvent(EVENT_1);\r
+ TEST_OK();\r
+ test_nr = 4;\r
+ break;\r
+ case 4:\r
+ // Back to SUP_L\r
+ WaitEvent(EVENT_1);\r
+ TEST_OK();\r
+ test_nr++;\r
+ TerminateTask();\r
+ break;\r
+ default:\r
+ assert(0);\r
+ while(1);\r
+ }\r
+ }\r
+}\r
+\r
+void etask_sup_h_02( void ) {\r
+ while(1);\r
+}\r
+\r
+\r
+#if 0\r
+void test_sup_m_02( void ) {\r
+ switch(test){\r
+ case 1:\r
+ TEST_OK();\r
+ test_nr++;\r
+ ChainTask(SUP_L_BASIC);\r
+ break;\r
+ case 3:\r
+ TEST_OK();\r
+ default:\r
+ break;\r
+ }\r
+}\r
+#endif\r
+\r
+void btest_sup_l_02( void ) {\r
+ switch(test_nr){\r
+ case 1:\r
+ TEST_OK();\r
+ test_nr++;\r
+ ChainTask(TASK_ID_etask_sup_l);\r
+ break;\r
+ default:\r
+ while(1);\r
+ }\r
+\r
+}\r
+\r
+void btest_sup_m_02( void ) {\r
+}\r
+\r
+void btest_sup_h_02( void ) {\r
+}\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*
+ * Tested: scheduletables
+ */
+
+#include "Os.h"
+#include "Trace.h"
+//#include <stdio.h>
+#include <assert.h>
+#include "os_test.h"
+
+
+//static int test = 1;
+
+/*
+ * Table 0: period 10
+ * 5 - Activate task sup_m
+ * 7 - Setevent, EVENT_2 in sup_m
+ *
+ * Table 1: period 5
+ * 2 - activate task_sup_m
+ */
+
+void etask_sup_l_03( void ) {
+ ScheduleTableStatusType status;
+ test_nr = 1;
+ for(;;) {
+ switch(test_nr){
+
+ case 1:
+
+ GetScheduleTableStatus(SCHEDULE_TABLE_0,&status);
+ TEST_ASSERT(status==SCHEDULETABLE_STOPPED);
+
+ // Start a schedule with expire points at 2 and 5
+ StartScheduleTableRel(SCHEDULE_TABLE_0,SCHEDULETABLE_DURATION_1*2/10);
+ GetScheduleTableStatus(SCHEDULE_TABLE_0,&status);
+ TEST_ASSERT(status==SCHEDULETABLE_RUNNING);
+
+ IncrementCounter(COUNTER_ID_soft_2);
+ // This one should trigger SCHEDULE_ACTION_ACTIVATETASK, TASK_SUP_M
+ IncrementCounter(COUNTER_ID_soft_2);
+
+ TEST_ASSERT(test_nr==2);
+ break;
+
+ case 2:
+ // test 02 ===============================================
+ // back from trigger, go to next expire point (5 more)
+ IncrementCounter(COUNTER_ID_soft_2); // 3
+ IncrementCounter(COUNTER_ID_soft_2);
+ IncrementCounter(COUNTER_ID_soft_2);
+ IncrementCounter(COUNTER_ID_soft_2); // 6
+ // Trigger the SCHEDULE_ACTION_SETEVENT, TASK_SUP_M
+ IncrementCounter(COUNTER_ID_soft_2); // 7
+ // Schedule to check if the is an event in TASK_SUP_M queue
+ Schedule();
+
+ TEST_ASSERT(test_nr==3);
+
+ break;
+ case 3:
+
+ // test 03 ===============================================
+ // back from trigger, period is 10 so another 2 should start all over again.
+ IncrementCounter(COUNTER_ID_soft_2); // 8
+ IncrementCounter(COUNTER_ID_soft_2); // 9
+ IncrementCounter(COUNTER_ID_soft_2); // 10
+
+ // Trigger SCHEDULE_ACTION_ACTIVATETASK, TASK_SUP_M
+ Schedule();
+
+ TEST_ASSERT(test_nr==4);
+
+ case 4:
+
+ // Go with the next schedule table, while 0 is running
+ // (The current table must complete first)
+ NextScheduleTable(SCHEDULE_TABLE_0, SCHEDULE_TABLE_1);
+
+ GetScheduleTableStatus(SCHEDULE_TABLE_1,&status);
+ TEST_ASSERT(status==SCHEDULETABLE_NEXT);
+
+ IncrementCounter(COUNTER_ID_soft_2); // 1
+ IncrementCounter(COUNTER_ID_soft_2); // 2
+ IncrementCounter(COUNTER_ID_soft_2); // 3
+ IncrementCounter(COUNTER_ID_soft_2); // 4
+ IncrementCounter(COUNTER_ID_soft_2); // 5, ActivateTask
+
+ IncrementCounter(COUNTER_ID_soft_2); // 6
+ IncrementCounter(COUNTER_ID_soft_2); // 7, SetEvent
+ IncrementCounter(COUNTER_ID_soft_2); // 8
+ IncrementCounter(COUNTER_ID_soft_2); // 9
+ IncrementCounter(COUNTER_ID_soft_2); // 10
+
+ GetScheduleTableStatus(SCHEDULE_TABLE_0,&status);
+ TEST_ASSERT(status==SCHEDULETABLE_STOPPED);
+ GetScheduleTableStatus(SCHEDULE_TABLE_1,&status);
+ TEST_ASSERT(status==SCHEDULETABLE_RUNNING);
+
+ IncrementCounter(COUNTER_ID_soft_2); // 0 On table 1
+
+
+// StartScheduleTableRel(SCHEDULE_TABLE_0,SCHEDULETABLE_DURATION_1*3/10);
+
+ // Done
+ break;
+ default:
+ assert(0);
+ while(1);
+ }
+ }
+}
+
+void etask_sup_m_03( void ) {
+ for(;;) {
+ switch(test_nr) {
+ case 1:
+ TEST_OK();
+ test_nr++;
+ break;
+ case 2:
+ // back to TASK_SUP_L
+ WaitEvent(EVENT_2);
+ TEST_OK()
+ test_nr++;
+ break;
+ case 3:
+ // we have started again
+ TEST_OK();
+ test_nr++;
+ break;
+ case 4:
+ break;
+ default:
+ assert(0);
+ break;
+ }
+ }
+}
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+#include "Os.h"\r
+#include "Cpu.h"\r
+#include "ext_config.h"\r
+\r
+\r
+StatusType CallTrustedFunction( TrustedFunctionIndexType ix, \r
+ TrustedFunctionParameterRefType param ) \r
+{\r
+\r
+ /* INFO: Can't find anything in the autosar documentation about calling a \r
+ * trusted function directly from a trusted application(not calling\r
+ * CallTrustedFunction() at all). So this code checks if in user mode \r
+ * or not. \r
+ * \r
+ * In Linux you either call the function directly e.g "getpid()" when \r
+ * in priv. mode and through "syscall(SYS_getpid)" when in user mode.\r
+ */\r
+\r
+ /* According to OS097 we can call this function from both trusted and non-trusted application */\r
+\r
+ if( ix > Oil_GetServiceCnt() ) {\r
+ return E_OS_SERVICEID;\r
+ }\r
+ \r
+ CallService(ix,param);\r
+ \r
+ return E_OK;\r
+}\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+#define MM_TYPE_UNKNOWN 0\r
+#define MM_TYPE_MMU 1\r
+#define MM_TYPE_PU 2\r
+\r
+struct mm_probe_s {\r
+ int type;\r
+ \r
+} mm_probe_t;\r
+\r
+void mm_init( void ) {\r
+ \r
+}\r
+\r
+// probe hardware\r
+void mm_probe( mm_probe_t *mm_cfg ) {\r
+ \r
+ // found mmu or pu, etc.\r
+ \r
+}\r
+\r
--- /dev/null
+In this directory modules related to the System services specifications\r
+should be placed.
\ No newline at end of file
--- /dev/null
+\r
+\r
+add\r
+toolbar\r
+(\r
+ toolitem "Reload"\r
+ [\r
+\r
+ ggg ggg\r
+ g g g\r
+ g g g\r
+ ggg gg gg\r
+ gg g\r
+ g g g\r
+ g g ggg\r
+\r
+g ggg ggg gg\r
+g g g g g g g\r
+g g g g g g g\r
+g g g ggg g g\r
+g g g g g g g\r
+g g g g g g g\r
+ggg ggg g g gg\r
+ ]\r
+ (\r
+ do load reload \r
+ )\r
+ toolitem "Reload"\r
+ [\r
+\r
+\r
+\r
+ggg ggg gg g g\r
+ g g g g g g\r
+ g g g g ggg\r
+ g gg gg g g\r
+ g g ggg g g\r
+ g g g g g g\r
+ g ggg g g g g\r
+\r
+\r
+\r
+\r
+\r
+\r
+ ]\r
+ (\r
+ do term\r
+ )\r
+ toolitem "Reload"\r
+ [\r
+\r
+\r
+ RRRRRR\r
+ R R\r
+ R R\r
+ R R\r
+ RRRRRR\r
+ R R\r
+ R R\r
+ R R\r
+ R R\r
+\r
+\r
+\r
+\r
+\r
+ ]\r
+ (\r
+ sys.up\r
+ )\r
+ toolitem "Layout"\r
+ [\r
+\r
+\r
+\r
+\r
+ m mmm m m\r
+ m m m m m\r
+ m m m m m\r
+ m mmm mmm\r
+ m m m m\r
+ m m m m\r
+ m m m m\r
+ mmm m m m\r
+\r
+\r
+\r
+\r
+ ]\r
+ (\r
+ do lay\r
+ )\r
+ toolitem "Ramlog"\r
+ [\r
+\r
+\r
+ mm m m m\r
+ m m m m mmm\r
+ mm m m m m\r
+ m m mmm m m\r
+ m m m m m m\r
+ m m m m m m\r
+\r
+ m m mm\r
+ m m m m\r
+ m m m m\r
+ m m m m m\r
+ m m m m m\r
+ mmm m mm\r
+\r
+ ]\r
+ (\r
+ do ramlog\r
+ )\r
+\r
+)\r
+\r
+add\r
+menu\r
+(\r
+ popup "Autosar"\r
+ (\r
+ popup "&Breakpoint"\r
+ (\r
+ menuitem "Save breakpoints,ALT+q" "store bp.cmm break"\r
+ menuitem "Load breakpoints,ALT+w" "do bp"\r
+ menuitem "Set det,F12" "b.s Det_ReportError"\r
+ )\r
+ menuitem "Load,ALT+l" "do load load"\r
+ menuitem "Reload,ALT+a" "do load reload"\r
+ menuitem "Restart" "do start"\r
+ menuitem "Change config" "do config dialog_project"\r
+ menuitem "Reset,ALT+r" "sys.up"\r
+ menuitem "Restore layout,CTRL+l" "do lay"\r
+ menuitem "View ramlog,CTRL+s" "do ramlog"\r
+ ) \r
+)\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+// File to load and save configuration settings to file\r
+//\r
+// Commands: \r
+// load - load config\r
+// save - save present configuration \r
+// debug - print some useful data\r
+\r
+// global configuration macros\r
+GLOBAL &cfg_project_path_g\r
+GLOBAL &cfg_loadfile_g\r
+GLOBAL &cfg_cpu_g\r
+\r
+// Global macros\r
+LOCAL &data_file\r
+LOCAL &user &cpu\r
+&user=os.env("username")\r
+//&cpu=CPU()\r
+//&data_file="~~~\cfg_t32_"+"&user"+"_"+"&cfg_cpu_g"+".txt" \r
+//&global_file="~~~\cfg_t32"\r
+&data_file="~~~\cfg_t32.txt"\r
+//+"&cfg_cpu_g"+".txt"\r
+\r
+\r
+LOCAL &cmd\r
+ENTRY &cmd\r
+GOSUB &cmd\r
+enddo\r
+\r
+\r
+rm:\r
+ rm &data_file\r
+ RETURN \r
+ \r
+//--------------------------------------------------------------------\r
+\r
+load:\r
+\r
+ print "loading config from &data_file"\r
+ \r
+ if OS.FILE(&data_file) \r
+ (\r
+ OPEN #1 &data_file /read\r
+ READ #1 &cfg_project_path_g \r
+ READ #1 &cfg_loadfile_g \r
+ READ #1 &cfg_cpu_g \r
+ CLOSE #1\r
+ ) \r
+ ELSE \r
+ (\r
+ &cfg_project_path_g=""\r
+ &cfg_loadfile_g=""\r
+ &cfg_cpu_g=""\r
+ )\r
+ RETURN\r
+\r
+//--------------------------------------------------------------------\r
+\r
+//--------------------------------------------------------------------\r
+\r
+save:\r
+ print "Saving config to &data_file"\r
+ OPEN #1 &data_file /create\r
+ WRITE #1 "&cfg_project_path_g" \r
+ WRITE #1 "&cfg_loadfile_g"\r
+ WRITE #1 "&cfg_cpu_g"\r
+ CLOSE #1\r
+ RETURN\r
+\r
+#--------------------------------------------------------------------\r
+debug:\r
+ gosub load\r
+ print "DEBUG: &data_file"\r
+ print " project_path: &cfg_project_path_g"\r
+ print " load file: &cfg_loadfile_g"\r
+ print " cpu: &cfg_cpu_g"\r
+ RETURN\r
+\r
+\r
+//--------------------------------------------------------------------\r
+\r
+dialog_cpu:\r
+ dialog\r
+(& \r
+ HEADER "Select cpu"\r
+ POS 0. 0. 14.\r
+ BUTTON "mpc5516" "jumpto mpc5516"\r
+ POS 0. 1. 14.\r
+ BUTTON "mpc5554" "jumpto mpc5554"\r
+ POS 0. 2. 14.\r
+ BUTTON "arm" "jumpto arm"\r
+ CLOSE "jumpto win_close2"\r
+)\r
+ stop\r
+mpc5516:\r
+ &cfg_cpu_g="mpc5516"\r
+ jumpto win_close2\r
+mpc5554:\r
+ &cfg_cpu_g="mpc5554"\r
+ jumpto win_close2\r
+arm:\r
+ &cfg_cpu_g="arm"\r
+ jumpto win_close2\r
+win_close2:\r
+ dialog.end\r
+\r
+ ENDDO\r
+\r
+//--------------------------------------------------------------------\r
+\r
+\r
+\r
+dialog_project:\r
+ LOCAL &path\r
+// &closewin\r
+// &closewin=0.\r
+\r
+ dialog\r
+(&\r
+ pos 1. 1. 14.\r
+ text "CPU:"\r
+ pos 1. 2. 10.\r
+CPU: PULLDOWN "mpc5516,mpc5554,CortexM3"\r
+ (\r
+ )\r
+ HEADER "Project config"\r
+ pos 1. 3. 14.\r
+ text "Project root:"\r
+ pos 1. 4. 50.\r
+P_PATH: EDIT "&cfg_project_path_g" ""\r
+ pos 51. 4. 3.\r
+ BUTTON "..."\r
+ ( \r
+ Dialog.Setdir P_PATH "&cfg_project_path_g/*"\r
+ ) \r
+ pos 35. 6. 10.\r
+ DEFBUTTON "Set" "jumpto save_close"\r
+ pos 45. 6. 10.\r
+ DEFBUTTON "Cancel" "jumpto win_close"\r
+ CLOSE "jumpto win_close"\r
+)\r
+ stop\r
+save_close:\r
+ &cfg_cpu_g=dialog.string(CPU)\r
+ &cfg_project_path_g=dialog.string(P_PATH)\r
+ do config save\r
+win_close:\r
+ dialog.end\r
+\r
+// \r
+\r
+ enddo\r
+\r
+\r
+ \r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+\r
+\r
+PBI=SIM\r
+\r
+; Printer settings\r
+PRINTER=WINDOWS\r
+\r
+\r
+; Screen fonts\r
+SCREEN=\r
+FONT=SMALL\r
--- /dev/null
+#!/bin/bash
+
+if [ "$1" == "" ]; then
+ echo "error: T32 Installation path not supplied"
+ exit 1
+fi
+
+pwd_cmd=`cygpath -d \`pwd\``
+#echo $pwd_cmd
+echo "cd ${pwd_cmd}" > $1/t32.cmm
+cat start.cmm >> $1/t32.cmm
+##dos2unix $1/t32.cmm
+cp -v config_sim.t32 $1
+
+
--- /dev/null
+// Write pattern into regs. Check if they look the same after.\r
+LOCAL &i\r
+LOCAL &val\r
+&i=0.\r
+&val=0x00\r
+while &i<=31.\r
+(\r
+ spe.s R&i &val \r
+ print &i\r
+ &i=&i+1.\r
+ &val=(&val<<8)+&i \r
+)\r
+enddo\r
+\r
--- /dev/null
+LOCAL &cmd\r
+ENTRY &cmd\r
+IF !SIMULATOR()\r
+ GOSUB &cmd\r
+ENDDO\r
+\r
+open:\r
+ FLASH.Auto ALL\r
+ RETURN\r
+\r
+//-------------------------------------------------------------\r
+close:\r
+ FLASH.Auto OFF\r
+ RETURN\r
+\r
+\r
+//-------------------------------------------------------------\r
+init:\r
+\r
+&flashbase=0x00000000\r
+&shadowbase=0x00ff8000\r
+&rambase=0x40000000\r
+&flashdriver="tbd.bin"\r
+&flashsize=0x000100000\r
+\r
+\r
+; initialize internal SRAM\r
+Data.Set EA:0x40000000--0x4000ffff %quad 0\r
+\r
+; setup MMU for flash, RAM and register access\r
+MMU.TLB1.SET 0x1 0xC0000500 0xFFF0000A 0xFFF0003F\r
+MMU.TLB1.SET 0x2 0xC0000400 0x40000008 0x4000003F\r
+MMU.TLB1.SET 0x3 0xC0000700 0x00000000 0x0000003F\r
+\r
+;========================================================================\r
+; Check SIU_MIDR register to select flash driver depending on processor \r
+; revision\r
+&flashdriver="~~/demo/powerpc/flash/quad/h7fb5510.bin"\r
+\r
+;========================================================================\r
+; Flash declaration\r
+\r
+FLASH.RESet\r
+\r
+FLASH.Create 1. (&flashbase+0x00000000)++0x03fff TARGET Quad 0. ; L0\r
+FLASH.Create 1. (&flashbase+0x00004000)++0x03fff TARGET Quad 1. ; L1\r
+FLASH.Create 1. (&flashbase+0x00008000)++0x03fff TARGET Quad 2. ; L2\r
+FLASH.Create 1. (&flashbase+0x0000C000)++0x03fff TARGET Quad 3. ; L3\r
+FLASH.Create 1. (&flashbase+0x00010000)++0x03fff TARGET Quad 4. ; L4\r
+FLASH.Create 1. (&flashbase+0x00014000)++0x03fff TARGET Quad 5. ; L5\r
+FLASH.Create 1. (&flashbase+0x00018000)++0x03fff TARGET Quad 6. ; L6\r
+FLASH.Create 1. (&flashbase+0x0001C000)++0x03fff TARGET Quad 7. ; L7\r
+FLASH.Create 1. (&flashbase+0x00020000)++0x0ffff TARGET Quad 8. ; L8\r
+FLASH.Create 1. (&flashbase+0x00030000)++0x0ffff TARGET Quad 9. ; L9\r
+FLASH.Create 2. (&flashbase+0x00040000)++0x1ffff TARGET Quad 0. ; M0\r
+FLASH.Create 2. (&flashbase+0x00060000)++0x1ffff TARGET Quad 1. ; M1\r
+&flashaddr=&flashbase+0x00080000\r
+&Hx=0.\r
+while &flashaddr<(&flashbase+0x000100000)\r
+(\r
+ FLASH.Create 3. &flashaddr++0x1ffff TARGET Quad &Hx ; H0..H3\r
+ &flashaddr=&flashaddr+0x20000\r
+ &Hx=&Hx+1.\r
+)\r
+; Shadow row\r
+FLASH.Create 4. (&shadowbase+0x00000000)++0x7fff NOP Quad\r
+\r
+FLASH.TARGET E:&rambase E:&rambase+0x2000 0x1000 &flashdriver\r
+RETURN\r
+\r
+\r
--- /dev/null
+// t32 Sun May 31 11:33:27 2009\r
+\r
+ B::\r
+ \r
+ TOOLBAR ON\r
+ STATUSBAR ON\r
+ WINPAGE.RESET\r
+ \r
+ WINCLEAR\r
+ WINPOS 78.714 50.538 72. 24. 12. 1. W002\r
+ WINTABS 13. 0. 0. 0. 0. 0. 0.\r
+ ws.b.l\r
+ \r
+ WINPOS 146.57 50.692 89. 22. 0. 0. W005\r
+ ws.Var.View %open Det_RamLog\r
+ \r
+ WINPOS 1.8571 50.154 83. 28. 0. 0. W001\r
+ ws.area\r
+ \r
+ WINPOS 2.2857 0.076923 134. 62. 13. 1. W000\r
+ WINTABS 10. 10. 25. 62.\r
+ ws.d.l\r
+ \r
+ WINPAGE.SELECT P000 \r
+ \r
+ ENDDO\r
--- /dev/null
+\r
+LOCAL &cmd &arg1 &arg2\r
+ENTRY &cmd &arg1 &arg2\r
+gosub &cmd\r
+\r
+enddo\r
+\r
+\r
+//-------------------------------------------------------------\r
+// a file dialog\r
+dialog:\r
+ LOCAL &file\r
+ dialog.file "&cfg_project_path_g"/*.elf\r
+ ENTRY &file\r
+ print "&file"\r
+ RETURN\r
+\r
+\r
+//-------------------------------------------------------------\r
+load:\r
+ LOCAL &file\r
+ dialog.file "&cfg_project_path_g"/*.elf\r
+ ENTRY &file\r
+ \r
+ IF OS.FILE(&file) \r
+ &cfg_loadfile_g="&file"\r
+ \r
+ do config save \r
+ do flash open\r
+ data.load.elf &cfg_loadfile_g /CYGDRIVE /GNU \r
+ do flash close\r
+ print "&cfg_loadfile_g"\r
+ \r
+ enddo\r
+\r
+//------------------------------------------------------------- \r
+reload:\r
+ print "&cfg_loadfile_g"\r
+ sys.up\r
+ r.reset \r
+ do flash init\r
+ do flash open\r
+ data.load.elf &cfg_loadfile_g /GNU \r
+// /CYGDRIVE\r
+ do flash close\r
+ enddo\r
+ \r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+// t32 Tue Oct 28 09:38:28 2008\r
+\r
+ B::\r
+ \r
+ TOOLBAR ON\r
+ STATUSBAR ON\r
+ WINPAGE.RESET\r
+ \r
+ WINCLEAR\r
+ WINPOS 0.375 0.25 97. 25. 13. 1. W001\r
+ WINTABS 10. 10. 25. 62.\r
+ ws.d.l\r
+ \r
+ WINPOS 0.125 41.625 75. 14. 0. 0. W000\r
+ ws.area\r
+ \r
+ WINPOS 97.75 38.688 77. 20. 0. 0. W002\r
+ ws.r /spotlight\r
+ \r
+ WINPOS 97.75 30.813 80. 6. 23. 1. W003\r
+ WINTABS 13. 0. 0. 0. 0. 0. 0.\r
+ ws.b.l\r
+ \r
+ WINPOS 81.375 0.3125 74. 25. 0. 1. W005\r
+ WINTABS 26. 26.\r
+ sYmbol.Browse\r
+ \r
+ WINPAGE.SELECT P000 \r
+ \r
+ ENDDO\r
--- /dev/null
+#drivers\r
+\r
+install-file-y += $(ROOTDIR)/t32/*.cmm,t32\r
+install-file-y += $(ROOTDIR)/t32/*.dll,t32\r
+install-file-y += $(ROOTDIR)/t32/*.men,t32\r
--- /dev/null
+area.clear RAMLOG\r
+AREA.Create RAMLOG\r
+AREA.Select RAMLOG\r
+AREA RAMLOG\r
+Data.STRING v.range(ramlog)\r
+// Select standard area again..\r
+area.select A000\r
+enddo\r
+\r
--- /dev/null
+// wclear\r
+\r
+// system.up\r
+ sim.res\r
+ sim.unload \r
+ // arg 1-blaj\r
+ // arg 2-blaj\r
+ // arg 3-debug : 0 \r
+ \r
+ sim.load mpc55xx_sim.dll 20000 0 1\r
+ ;sim.load C:\projects\t32sim\Debug\mpc55xx_sim.dll 20000 0 0\r
+; sim.load &dll 0xfff84000 0\r
+\r
+enddo\r
+\r
+ name.s p.128 timer0\r
+ name.s p.129 timer1\r
+ name.s p.130 timer2\r
+ name.s p.131 timer3\r
+ name.s p.132 timer4\r
+ name.s p.133 timer5\r
+ name.s p.134 timer6\r
+ name.s p.135 timer7\r
+ name.group g.timer p.timer0 p.timer1 p.timer2 p.timer3 p.timer4 p.timer5 p.timer6 p.timer7\r
+ name.word w.timer g.timer\r
+\r
+ per demoport\r
+\r
+ enddo\r
+\r
+\r
+ term.protocol sim\r
+ winpos ,,,,,,, iconic\r
+ term 1 1\r
+\r
+ winpos ,,,,,,, iconic\r
+ port.get\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+LOCAL &exe_dir &cpu &proj_path\r
+//ENTRY &cpu\r
+\r
+//do ~~/t32.cmm\r
+winclear \r
+&proj_path=os.pwd()\r
+do t32.cmm\r
+\r
+print "Current project path:" "&proj_path" \r
+\r
+do config load\r
+//do config debug \r
+\r
+\r
+IF "&cfg_cpu_g"==""\r
+(\r
+ do config dialog_project\r
+)\r
+\r
+IF "&cfg_project_path_g"==""\r
+(\r
+ &cfg_project_path_g="&proj_path" \r
+ do config dialog_project\r
+)\r
+\r
+//do config debug \r
+\r
+&cpu="&cfg_cpu_g"\r
+\r
+winpos 0% 70% 50% 30%\r
+area\r
+\r
+sys.down\r
+\r
+;reset\r
+//GLOBAL &cfg_project_path_g\r
+//GLOBAL &cfg_base_load_file_g\r
+\r
+&exe_dir=os.ppd()\r
+cd &exe_dir\r
+\r
+//do config load\r
+//do config dialog\r
+\r
+sys.cpu &cpu\r
+\r
+IF SIMULATOR() \r
+(\r
+ IF CPU()!="CortexM3"\r
+ (\r
+ do sim_mpc55xx\r
+ )\r
+)\r
+ELSE \r
+(\r
+ sys.bdmclock 10000000.\r
+)\r
+\r
+\r
+// Setup flash\r
+SYStem.Up \r
+do flash init\r
+ \r
+\r
+IF !SIMULATOR() \r
+( \r
+ break.select program onchip\r
+)\r
+\r
+\r
+// Setup how to view variables and code\r
+setup.var %SYMBOL.on %HEX.on %decimal.on %index.on\r
+setup.tabsize 2.\r
+\r
+menu.rp autosar.men\r
+\r
+//winclear\r
+winpos 0% 0% 50% 68%\r
+w.d.l\r
+winpos 50% 0% 50% 50%\r
+w.v.f /l /c\r
+winpos 0% 70% 50% 30%\r
+area\r
+\r
+area.select\r
+//area.reset\r
+//w.v.w\r
+//v.aw flags ast\r
+\r
+print "## Welcome to Arc-Core simulator environment for T32 ##"\r
+print "## Select example to load from the menu Arc-Core->Load ##"\r
+print ""\r
+\r
+\r
+enddo\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+;Default startup program for TRACE32\r
+;\r
+;This startup program can be modified according to your needs.\r
+\r
+;choose hex mode for input\r
+ radix hex\r
+\r
+;Add some extra buttons to the toolbar\r
+\r
+ menu.rp\r
+ (\r
+ add\r
+ toolbar\r
+ (\r
+ separator\r
+ toolitem "Source/List" "list" "Data.List"\r
+ toolitem "Memory Dump" "dump" "Data.dump"\r
+ toolitem "Register" "reg" "Register"\r
+ separator\r
+ toolitem "Watch" ":varwatch" "Var.Watch"\r
+ toolitem "Stack" ":varframe" "Var.Frame /l /c"\r
+ toolitem "Automatic Watch" ":varref" "Var.Ref"\r
+ separator\r
+ toolitem "List Breakpoints" "break" "Break.List"\r
+ toolitem "List Symbols" "symbols" "sYmbol.Browse"\r
+ separator\r
+ )\r
+ )\r
+\r
+ if language()!=""\r
+ (\r
+ local &menuname\r
+ &menuname="~~/t32"+language()\r
+ menu.rp &menuname\r
+ )\r
+\r
+;Recall and Define History File\r
+ autostore , history bookmark\r
+\r
+ ;cd c:\projects\autosar\scripts\r
+ ;cd c:\projects\per\t32\r
+ ;cd c:\projects\autosar\t32\r
+ ;cd c:\projects\autosar\tools\t32\r
+ ;do start\r
+\r
+ enddo\r
+\r
--- /dev/null
+winclear my_term\r
+WinPOS 60% 0% 50% 30. 1. 1. my_term\r
+term.size 80. 300.\r
+term.scroll on\r
+term.mode ASCII\r
+\r
+IF CPUFAMILY()=="ARM"\r
+(\r
+ term.METHOD SE e:address.offset(v.address(t32_outport)) e:0\r
+ term.view\r
+)\r
+ELSE\r
+(\r
+ term.view e:address.offset(v.address(t32_outport)) e:0\r
+ term.write e:address.offset(v.address(t32_outport)) hoppsan.log \r
+)\r
+\r
+enddo\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r