1 /* -------------------------------- Arctic Core ------------------------------
2 * Arctic Core - the open source AUTOSAR platform http://arccore.com
4 * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
6 * This source code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published by the
8 * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * -------------------------------- Arctic Core ------------------------------*/
23 /******************************************************************************
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25 * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Source File
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27 * @date: 22. May 2009
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28 *----------------------------------------------------------------------------
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30 * Copyright (C) 2009 ARM Limited. All rights reserved.
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32 * ARM Limited (ARM) is supplying this software for use with Cortex-Mx
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33 * processor based microcontrollers. This file can be freely distributed
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34 * within development tools that are supporting such ARM based processors.
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36 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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37 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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38 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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39 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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40 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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42 ******************************************************************************/
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49 /* define compiler specific symbols */
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50 #if defined ( __CC_ARM )
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51 #define __ASM __asm /*!< asm keyword for armcc */
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52 #define __INLINE __inline /*!< inline keyword for armcc */
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54 #elif defined ( __ICCARM__ )
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55 #define __ASM __asm /*!< asm keyword for iarcc */
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56 #define __INLINE inline /*!< inline keyword for iarcc. Only avaiable in High optimization mode! */
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58 #elif defined ( __GNUC__ )
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59 #define __ASM __asm /*!< asm keyword for gcc */
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60 #define __INLINE inline /*!< inline keyword for gcc */
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62 #elif defined ( __TASKING__ )
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63 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
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64 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
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70 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
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73 * @brief Return the Process Stack Pointer
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76 * @return uint32_t ProcessStackPointer
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78 * Return the actual process stack pointer
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80 __ASM uint32_t __get_PSP(void)
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87 * @brief Set the Process Stack Pointer
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89 * @param uint32_t Process Stack Pointer
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92 * Assign the value ProcessStackPointer to the MSP
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93 * (process stack pointer) Cortex processor register
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95 __ASM void __set_PSP(uint32_t topOfProcStack)
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102 * @brief Return the Main Stack Pointer
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105 * @return uint32_t Main Stack Pointer
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107 * Return the current value of the MSP (main stack pointer)
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108 * Cortex processor register
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110 __ASM uint32_t __get_MSP(void)
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117 * @brief Set the Main Stack Pointer
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119 * @param uint32_t Main Stack Pointer
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122 * Assign the value mainStackPointer to the MSP
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123 * (main stack pointer) Cortex processor register
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125 __ASM void __set_MSP(uint32_t mainStackPointer)
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132 * @brief Reverse byte order in unsigned short value
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134 * @param uint16_t value to reverse
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135 * @return uint32_t reversed value
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137 * Reverse byte order in unsigned short value
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139 __ASM uint32_t __REV16(uint16_t value)
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146 * @brief Reverse byte order in signed short value with sign extension to integer
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148 * @param int16_t value to reverse
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149 * @return int32_t reversed value
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151 * Reverse byte order in signed short value with sign extension to integer
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153 __ASM int32_t __REVSH(int16_t value)
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160 #if (__ARMCC_VERSION < 400000)
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163 * @brief Remove the exclusive lock created by ldrex
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168 * Removes the exclusive lock which is created by ldrex.
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170 __ASM void __CLREX(void)
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176 * @brief Return the Base Priority value
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179 * @return uint32_t BasePriority
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181 * Return the content of the base priority register
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183 __ASM uint32_t __get_BASEPRI(void)
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190 * @brief Set the Base Priority value
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192 * @param uint32_t BasePriority
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195 * Set the base priority register
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197 __ASM void __set_BASEPRI(uint32_t basePri)
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204 * @brief Return the Priority Mask value
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207 * @return uint32_t PriMask
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209 * Return the state of the priority mask bit from the priority mask
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212 __ASM uint32_t __get_PRIMASK(void)
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219 * @brief Set the Priority Mask value
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221 * @param uint32_t PriMask
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224 * Set the priority mask bit in the priority mask register
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226 __ASM void __set_PRIMASK(uint32_t priMask)
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233 * @brief Return the Fault Mask value
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236 * @return uint32_t FaultMask
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238 * Return the content of the fault mask register
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240 __ASM uint32_t __get_FAULTMASK(void)
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247 * @brief Set the Fault Mask value
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249 * @param uint32_t faultMask value
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252 * Set the fault mask register
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254 __ASM void __set_FAULTMASK(uint32_t faultMask)
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261 * @brief Return the Control Register value
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264 * @return uint32_t Control value
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266 * Return the content of the control register
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268 __ASM uint32_t __get_CONTROL(void)
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275 * @brief Set the Control Register value
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277 * @param uint32_t Control value
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280 * Set the control register
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282 __ASM void __set_CONTROL(uint32_t control)
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288 #endif /* __ARMCC_VERSION */
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291 #elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
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292 #pragma diag_suppress=Pe940
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295 * @brief Return the Process Stack Pointer
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298 * @return uint32_t ProcessStackPointer
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300 * Return the actual process stack pointer
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302 uint32_t __get_PSP(void)
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304 __ASM("mrs r0, psp");
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309 * @brief Set the Process Stack Pointer
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311 * @param uint32_t Process Stack Pointer
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314 * Assign the value ProcessStackPointer to the MSP
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315 * (process stack pointer) Cortex processor register
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317 void __set_PSP(uint32_t topOfProcStack)
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319 __ASM("msr psp, r0");
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324 * @brief Return the Main Stack Pointer
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327 * @return uint32_t Main Stack Pointer
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329 * Return the current value of the MSP (main stack pointer)
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330 * Cortex processor register
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332 uint32_t __get_MSP(void)
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334 __ASM("mrs r0, msp");
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339 * @brief Set the Main Stack Pointer
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341 * @param uint32_t Main Stack Pointer
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344 * Assign the value mainStackPointer to the MSP
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345 * (main stack pointer) Cortex processor register
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347 void __set_MSP(uint32_t topOfMainStack)
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349 __ASM("msr msp, r0");
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354 * @brief Reverse byte order in unsigned short value
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356 * @param uint16_t value to reverse
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357 * @return uint32_t reversed value
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359 * Reverse byte order in unsigned short value
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361 uint32_t __REV16(uint16_t value)
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363 __ASM("rev16 r0, r0");
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368 * @brief Reverse bit order of value
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370 * @param uint32_t value to reverse
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371 * @return uint32_t reversed value
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373 * Reverse bit order of value
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375 uint32_t __RBIT(uint32_t value)
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377 __ASM("rbit r0, r0");
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382 * @brief LDR Exclusive
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384 * @param uint8_t* address
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385 * @return uint8_t value of (*address)
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387 * Exclusive LDR command
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389 uint8_t __LDREXB(uint8_t *addr)
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391 __ASM("ldrexb r0, [r0]");
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396 * @brief LDR Exclusive
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398 * @param uint16_t* address
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399 * @return uint16_t value of (*address)
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401 * Exclusive LDR command
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403 uint16_t __LDREXH(uint16_t *addr)
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405 __ASM("ldrexh r0, [r0]");
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410 * @brief LDR Exclusive
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412 * @param uint32_t* address
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413 * @return uint32_t value of (*address)
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415 * Exclusive LDR command
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417 uint32_t __LDREXW(uint32_t *addr)
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419 __ASM("ldrex r0, [r0]");
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424 * @brief STR Exclusive
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426 * @param uint8_t *address
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427 * @param uint8_t value to store
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428 * @return uint32_t successful / failed
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430 * Exclusive STR command
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432 uint32_t __STREXB(uint8_t value, uint8_t *addr)
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434 __ASM("strexb r0, r0, [r1]");
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439 * @brief STR Exclusive
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441 * @param uint16_t *address
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442 * @param uint16_t value to store
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443 * @return uint32_t successful / failed
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445 * Exclusive STR command
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447 uint32_t __STREXH(uint16_t value, uint16_t *addr)
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449 __ASM("strexh r0, r0, [r1]");
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454 * @brief STR Exclusive
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456 * @param uint32_t *address
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457 * @param uint32_t value to store
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458 * @return uint32_t successful / failed
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460 * Exclusive STR command
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462 uint32_t __STREXW(uint32_t value, uint32_t *addr)
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464 __ASM("strex r0, r0, [r1]");
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468 #pragma diag_default=Pe940
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471 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
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474 * @brief Return the Process Stack Pointer
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477 * @return uint32_t ProcessStackPointer
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479 * Return the actual process stack pointer
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481 uint32_t __get_PSP(void) __attribute__( ( naked ) );
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482 uint32_t __get_PSP(void)
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486 __ASM volatile ("MRS %0, psp\n\t"
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488 "BX lr \n\t" : "=r" (result) );
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494 * @brief Set the Process Stack Pointer
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496 * @param uint32_t Process Stack Pointer
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499 * Assign the value ProcessStackPointer to the MSP
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500 * (process stack pointer) Cortex processor register
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502 void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) );
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503 void __set_PSP(uint32_t topOfProcStack)
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505 __ASM volatile ("MSR psp, %0\n\t"
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506 "BX lr \n\t" : : "r" (topOfProcStack) );
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510 * @brief Return the Main Stack Pointer
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513 * @return uint32_t Main Stack Pointer
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515 * Return the current value of the MSP (main stack pointer)
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516 * Cortex processor register
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518 uint32_t __get_MSP(void) __attribute__( ( naked ) );
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519 uint32_t __get_MSP(void)
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523 __ASM volatile ("MRS %0, msp\n\t"
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525 "BX lr \n\t" : "=r" (result) );
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530 * @brief Set the Main Stack Pointer
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532 * @param uint32_t Main Stack Pointer
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535 * Assign the value mainStackPointer to the MSP
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536 * (main stack pointer) Cortex processor register
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538 void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) );
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539 void __set_MSP(uint32_t topOfMainStack)
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541 __ASM volatile ("MSR msp, %0\n\t"
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542 "BX lr \n\t" : : "r" (topOfMainStack) );
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546 * @brief Return the Base Priority value
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549 * @return uint32_t BasePriority
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551 * Return the content of the base priority register
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553 uint32_t __get_BASEPRI(void)
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557 __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
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562 * @brief Set the Base Priority value
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564 * @param uint32_t BasePriority
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567 * Set the base priority register
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569 void __set_BASEPRI(uint32_t value)
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571 __ASM volatile ("MSR basepri, %0" : : "r" (value) );
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575 * @brief Return the Priority Mask value
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578 * @return uint32_t PriMask
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580 * Return the state of the priority mask bit from the priority mask
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583 uint32_t __get_PRIMASK(void)
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587 __ASM volatile ("MRS %0, primask" : "=r" (result) );
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592 * @brief Set the Priority Mask value
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594 * @param uint32_t PriMask
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597 * Set the priority mask bit in the priority mask register
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599 void __set_PRIMASK(uint32_t priMask)
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601 __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
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605 * @brief Return the Fault Mask value
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608 * @return uint32_t FaultMask
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610 * Return the content of the fault mask register
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612 uint32_t __get_FAULTMASK(void)
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616 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
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621 * @brief Set the Fault Mask value
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623 * @param uint32_t faultMask value
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626 * Set the fault mask register
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628 void __set_FAULTMASK(uint32_t faultMask)
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630 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
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634 * @brief Reverse byte order in integer value
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636 * @param uint32_t value to reverse
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637 * @return uint32_t reversed value
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639 * Reverse byte order in integer value
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641 uint32_t __REV(uint32_t value)
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645 __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
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650 * @brief Reverse byte order in unsigned short value
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652 * @param uint16_t value to reverse
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653 * @return uint32_t reversed value
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655 * Reverse byte order in unsigned short value
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657 uint32_t __REV16(uint16_t value)
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661 __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
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666 * @brief Reverse byte order in signed short value with sign extension to integer
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668 * @param int32_t value to reverse
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669 * @return int32_t reversed value
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671 * Reverse byte order in signed short value with sign extension to integer
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673 int32_t __REVSH(int16_t value)
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677 __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
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682 * @brief Reverse bit order of value
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684 * @param uint32_t value to reverse
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685 * @return uint32_t reversed value
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687 * Reverse bit order of value
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689 uint32_t __RBIT(uint32_t value)
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693 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
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698 * @brief LDR Exclusive
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700 * @param uint8_t* address
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701 * @return uint8_t value of (*address)
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703 * Exclusive LDR command
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705 uint8_t __LDREXB(uint8_t *addr)
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709 __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
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714 * @brief LDR Exclusive
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716 * @param uint16_t* address
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717 * @return uint16_t value of (*address)
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719 * Exclusive LDR command
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721 uint16_t __LDREXH(uint16_t *addr)
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725 __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
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730 * @brief LDR Exclusive
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732 * @param uint32_t* address
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733 * @return uint32_t value of (*address)
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735 * Exclusive LDR command
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737 uint32_t __LDREXW(uint32_t *addr)
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741 __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
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746 * @brief STR Exclusive
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748 * @param uint8_t *address
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749 * @param uint8_t value to store
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750 * @return uint32_t successful / failed
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752 * Exclusive STR command
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754 uint32_t __STREXB(uint8_t value, uint8_t *addr)
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758 __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
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763 * @brief STR Exclusive
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765 * @param uint16_t *address
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766 * @param uint16_t value to store
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767 * @return uint32_t successful / failed
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769 * Exclusive STR command
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771 uint32_t __STREXH(uint16_t value, uint16_t *addr)
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775 __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
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780 * @brief STR Exclusive
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782 * @param uint32_t *address
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783 * @param uint32_t value to store
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784 * @return uint32_t successful / failed
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786 * Exclusive STR command
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788 uint32_t __STREXW(uint32_t value, uint32_t *addr)
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792 __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
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797 * @brief Return the Control Register value
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800 * @return uint32_t Control value
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802 * Return the content of the control register
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804 uint32_t __get_CONTROL(void)
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808 __ASM volatile ("MRS %0, control" : "=r" (result) );
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813 * @brief Set the Control Register value
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815 * @param uint32_t Control value
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818 * Set the control register
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820 void __set_CONTROL(uint32_t control)
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822 __ASM volatile ("MSR control, %0" : : "r" (control) );
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825 #elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
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826 /* TASKING carm specific functions */
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829 * The CMSIS functions have been implemented as intrinsics in the compiler.
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830 * Please use "carm -?i" to get an up to date list of all instrinsics,
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831 * Including the CMSIS ones.
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