rtime.felk.cvut.cz Git - fpga/virtex2/uart.git/search

]> rtime.felk.cvut.cz Git - fpga/virtex2/uart.git/search

2011-02-06	Vladimir Burian	Peripheral logic address redefined as generic.	commit \| commitdiff \| tree
2011-02-04	Vladimir Burian	Software modification to work whit HW UART	commit \| commitdiff \| tree
2011-02-04	Vladimir Burian	Connection of HW UART peripheral	commit \| commitdiff \| tree
2011-02-04	Vladimir Burian	New HW UART submodule added.	commit \| commitdiff \| tree
2011-01-10	Vladimir Burian	Peripheral connected to the quadcount module and an...	commit \| commitdiff \| tree
2011-01-10	Vladimir Burian	Added custom openMSP430 peripheral as an interface...	commit \| commitdiff \| tree
2011-01-10	Vladimir Burian	+ Quadcount submodule	commit \| commitdiff \| tree
2011-01-09	Vladimir Burian	Make RS-232 receiving work. TimerA IRQ connected to...	commit \| commitdiff \| tree
2011-01-09	Vladimir Burian	Make RS-232 transmitting work.	commit \| commitdiff \| tree
2011-01-09	Vladimir Burian	Added TimerA instance. IRQs are unconnected.	commit \| commitdiff \| tree
2011-01-09	Vladimir Burian	Copied all needed files.	commit \| commitdiff \| tree
2011-01-09	Vladimir Burian	+ OpenMSP430 submodule.	commit \| commitdiff \| tree

MSP430 simple UART echo - test top level design for Virtex 2 V2MB1000 board