signal gpio_per_dout : std_logic_vector (15 downto 0);
signal timerA_per_dout : std_logic_vector (15 downto 0);
+ signal irq_ta0 : std_logic;
+ signal irq_ta1 : std_logic;
+
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begin
dmem_cen => dmem_cen,
dmem_din => dmem_din,
dmem_wen => dmem_wen,
- irq_acc => open,
+ irq_acc => irq_acc,
mclk => mclk,
per_addr => per_addr,
per_din => per_din,
dbg_uart_rxd => '0',
dco_clk => CLK_24MHz,
dmem_dout => dmem_dout,
- irq => (others => '0'),
+ irq => irq,
lfxt_clk => '0',
nmi => '0',
per_dout => per_dout,
);
omsp_timerA_0 : omsp_timerA port map (
- irq_ta0 => open,
- irq_ta1 => open,
+ irq_ta0 => irq_ta0,
+ irq_ta1 => irq_ta1,
per_dout => timerA_per_dout,
ta_out0 => open,
ta_out0_en => open,
aclk_en => aclk_en,
dbg_freeze => '0',
inclk => '0',
- irq_ta0_acc => '0',
+ irq_ta0_acc => irq_acc (9),
mclk => mclk,
per_addr => per_addr,
per_din => per_din,
puc => puc,
smclk_en => smclk_en,
ta_cci0a => '0',
- ta_cci0b => '0',
+ ta_cci0b => TXD,
ta_cci1a => '0',
ta_cci1b => '0',
ta_cci2a => '0',
per_dout <= gpio_per_dout or timerA_per_dout;
+ irq <= (9 => irq_ta0,
+ 8 => irq_ta1,
+ others => '0');
+
end rtl;