Peripheral logic address redefined as generic.

diff --git a/omsp_quadcount.vhd b/omsp_quadcount.vhd
index 5c84577c1c5d7ebf384cf1757ebf383a15b9e9d4..43e9750793fc26e621d1c5f02c822f36c860375e 100644 (file)
--- a/omsp_quadcount.vhd
+++ b/omsp_quadcount.vhd
@@ -4,6 +4,8 @@ use IEEE.STD_LOGIC_ARITH.ALL;
 use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
 entity omsp_quadcount is
+  generic (
+    ADDR : std_logic_vector (15 downto 0) := X"0150");
   port (
     mclk        : in  std_logic;
     per_addr    : in  std_logic_vector (7  downto 0);
@@ -26,8 +28,11 @@ architecture behavioral of omsp_quadcount is
   -- When reading whole 32-bit qcount input, first QCNTL has to be loaded, because
   -- this event causes QCNTH to latch appropriate value of qcount. This procedure
   -- ensures that correct value is readed.
-  constant QCNTL : std_logic_vector (15 downto 0) := X"0150";  -- qcount lower word logic address
-  constant QCNTH : std_logic_vector (15 downto 0) := X"0152";  -- qcount higher word logic address
+
+    -- qcount lower word logic address
+  constant QCNTL : std_logic_vector (15 downto 0) := ADDR;
+    -- qcount higher word logic address
+  constant QCNTH : std_logic_vector (15 downto 0) := ADDR + 2;
 
   signal qcntl_sel : boolean;
   signal qcnth_sel : boolean;