]> rtime.felk.cvut.cz Git - fpga/virtex2/uart.git/commit
Peripheral logic address redefined as generic.
authorVladimir Burian <buriavl2@fel.cvut.cz>
Sun, 6 Feb 2011 17:00:10 +0000 (18:00 +0100)
committerVladimir Burian <buriavl2@fel.cvut.cz>
Sun, 6 Feb 2011 17:00:10 +0000 (18:00 +0100)
commit52ca34a1c1778371b6f333c7b3813c343eee1ed7
tree82ce6fcb8f261b247795d87b4ef2a9ab0ba52573
parente4d439f4b7c5af4364f93911c067d72627326e37
Peripheral logic address redefined as generic.
omsp_quadcount.vhd