projects / fpga / virtex2 / uart.git / commit
| author | Vladimir Burian <buriavl2@fel.cvut.cz> | |
| Fri, 4 Feb 2011 14:55:49 +0000 (15:55 +0100) | ||
| committer | Vladimir Burian <buriavl2@fel.cvut.cz> | |
| Fri, 4 Feb 2011 17:39:45 +0000 (18:39 +0100) | ||
| commit | 79ea0ca600c0045d539a955a73513a57b0a0fc85 | |
| tree | 4f9cb7362fecbcd385e37acb0038373cdb05a487 | tree | snapshot |
| parent | 67981366db36c2e7679ccffb8ab879a6825cbd51 | commit | diff |
| .gitmodules | diff | blob | history | |
| uart | [new submodule] | blob |