]> rtime.felk.cvut.cz Git - fpga/virtex2/uart.git/summary
 
descriptionMSP430 simple UART echo - test top level design for Virtex 2 V2MB1000 board
ownerburiavl2
last changeSun, 13 Feb 2011 16:26:56 +0000 (17:26 +0100)
shortlog
2011-02-13 Vladimir Burian+ README master
2011-02-13 Vladimir BurianPWM test added to the software.
2011-02-13 Vladimir Burian+ PWM output capability.
2011-02-13 Vladimir BurianToplevel UART signals renamed.
2011-02-13 Vladimir BurianBuilding procedure changed.
2011-02-13 Vladimir BurianOmsp_quadcount periphery changed.
2011-02-06 Vladimir BurianPeripheral logic address redefined as generic.
2011-02-04 Vladimir BurianSoftware modification to work whit HW UART
2011-02-04 Vladimir BurianConnection of HW UART peripheral
2011-02-04 Vladimir BurianNew HW UART submodule added.
2011-01-10 Vladimir BurianPeripheral connected to the quadcount module and an...
2011-01-10 Vladimir BurianAdded custom openMSP430 peripheral as an interface...
2011-01-10 Vladimir Burian+ Quadcount submodule
2011-01-09 Vladimir BurianMake RS-232 receiving work. TimerA IRQ connected to...
2011-01-09 Vladimir BurianMake RS-232 transmitting work.
2011-01-09 Vladimir BurianAdded TimerA instance. IRQs are unconnected.
...
heads
13 years ago master