rtime.felk.cvut.cz Git - fpga/virtex2/uart.git/tree

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projects / fpga / virtex2 / uart.git / tree

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-rw-r--r--	90	.gitmodules	blob \| history \| raw
-rw-r--r--	3306	Makefile	blob \| history \| raw
drwxr-xr-x	-	coregen	tree \| history
-rw-r--r--	313	memory.bmm	blob \| history \| raw
-rw-r--r--	11926	openMSP430_defines.v	blob \| history \| raw
-rw-r--r--	827	openMSP430_uart.prj	blob \| history \| raw
-rw-r--r--	733	openMSP430_uart.ucf	blob \| history \| raw
-rw-r--r--	12336	openMSP430_uart.vhd	blob \| history \| raw
m---------	-	openmsp430	history
drwxr-xr-x	-	software	tree \| history

MSP430 simple UART echo - test top level design for Virtex 2 V2MB1000 board