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Include simple scripts to build, load and run project on target.
[fpga/lx-cpu1/lx-dad.git] / hw /
2015-02-15 Pavel PisaShift some external signals by half of clock cycle... tree | commitdiff
2015-02-15 Pavel PisaSimplify FPGA design external CPU read logic. tree | commitdiff
2015-02-15 Pavel PisaGit ignore build outputs. tree | commitdiff
2015-02-15 Pavel PisaRemove nonstandard ieee.std_logic_arith and ieee.std_lo... tree | commitdiff
2015-02-15 Pavel PisaInclude testbed for simulation in GHDL. tree | commitdiff
2015-02-15 Pavel PisaDisable use of unisim library to allow simulation by... tree | commitdiff
2015-02-15 Pavel PisaInclude example of mapping dualported RAM mapping to... tree | commitdiff
2015-02-15 Pavel PisaInclude hardware design of FPGA peripherals to external... tree | commitdiff