]> rtime.felk.cvut.cz Git - fpga/lx-cpu1/lx-dad.git/commit
Shift some external signals by half of clock cycle to visualize synchronization.
authorPavel Pisa <pisa@cmp.felk.cvut.cz>
Sun, 15 Feb 2015 10:55:49 +0000 (11:55 +0100)
committerPavel Pisa <pisa@cmp.felk.cvut.cz>
Sun, 15 Feb 2015 11:15:21 +0000 (12:15 +0100)
commit7ad1f485ba48955f9367666b594b97354ca0b206
tree47f3136913ffcdadede287f75c8f9946781a601a
parent5c8cb50ce62ea18abc2ef0998abf6aeeae12c92b
Shift some external signals by half of clock cycle to visualize synchronization.

Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
hw/tb/lx_dad_top_tb.vhd