Include testbed for simulation in GHDL.

Some top level attributes required for safe build for real hardware
with asynchronous external access has to be disabled for GHDL simulation.

 	-- XST attributes
 	attribute REGISTER_DUPLICATION : string;
-	attribute REGISTER_DUPLICATION of rd : signal is "NO";
+	--attribute REGISTER_DUPLICATION of rd : signal is "NO";
 	attribute REGISTER_DUPLICATION of rd_f_s : signal is "NO";
-	attribute REGISTER_DUPLICATION of bls : signal is "NO";
+	--attribute REGISTER_DUPLICATION of bls : signal is "NO";
 	attribute REGISTER_DUPLICATION of bls_f_s : signal is "NO";
-	attribute REGISTER_DUPLICATION of address : signal is "NO";
+	--attribute REGISTER_DUPLICATION of address : signal is "NO";
 	attribute REGISTER_DUPLICATION of address_f_s : signal is "NO";
-	attribute REGISTER_DUPLICATION of cs0_xc : signal is "NO";
+	--attribute REGISTER_DUPLICATION of cs0_xc : signal is "NO";
 	attribute REGISTER_DUPLICATION of cs0_xc_f_s : signal is "NO";

 	-- XST attributes
 	attribute REGISTER_DUPLICATION : string;
-	attribute REGISTER_DUPLICATION of rd : signal is "NO";
+	--attribute REGISTER_DUPLICATION of rd : signal is "NO";
 	attribute REGISTER_DUPLICATION of rd_f_s : signal is "NO";
-	attribute REGISTER_DUPLICATION of bls : signal is "NO";
+	--attribute REGISTER_DUPLICATION of bls : signal is "NO";
 	attribute REGISTER_DUPLICATION of bls_f_s : signal is "NO";
-	attribute REGISTER_DUPLICATION of address : signal is "NO";
+	--attribute REGISTER_DUPLICATION of address : signal is "NO";
 	attribute REGISTER_DUPLICATION of address_f_s : signal is "NO";
-	attribute REGISTER_DUPLICATION of cs0_xc : signal is "NO";
+	--attribute REGISTER_DUPLICATION of cs0_xc : signal is "NO";
 	attribute REGISTER_DUPLICATION of cs0_xc_f_s : signal is "NO";

Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>

diff --git a/hw/tb/Makefile b/hw/tb/Makefile
new file mode 100644 (file)
index 0000000..7a7fd2c
--- /dev/null
+++ b/hw/tb/Makefile
@@ -0,0 +1,45 @@
+GHDL=ghdl
+tumbl_SRC=mbl_pkg.vhd mem.vhd fetch.vhd exeq.vhd decode.vhd core_ctrl.vhd
+tumbl_DIR=../tumbl
+lx_util_SRC=util_pkg.vhd lx_dad_pkg.vhd xilinx_dualport_bram.vhd
+lx_util_DIR=..
+lx_dad_SRC=dff3.vhd dff2.vhd cnt_div.vhd measurement_register.vhd \
+       lx_crosdom_ser_fifo.vhd \
+       bus_example.vhd lx_example_mem.vhd bus_measurement.vhd lx_dad_top.vhd
+lx_dad_DIR=..
+
+MODULES=lx_util lx_dad
+
+SRC=$(foreach m, $(MODULES), $($(m)_SRC:%=$($(m)_DIR)/%))
+
+$(warning SRC=$(SRC))
+
+SRC+=lx_dad_top_tb.vhd
+
+CFLAGS += -Wall
+
+GHDLFLAGS+=
+ANALYZEFLAGS+=--std=93c --ieee=synopsys -fexplicit -ggdb
+
+#SIM_FLAGS=--stop-time=1000ns #--ieee-asserts=disable
+
+all:   test-lx-dad
+
+#convert_bin2bits : convert_bin2bits.o
+
+#imem.bits : imem.bin convert_bin2bits
+#      ./convert_bin2bits $< >$@
+
+test-lx-dad: analyze-all #imem.bits
+       $(GHDL) $(GHDLFLAGS) -m $(ANALYZEFLAGS) lx_dad_top_tb
+       $(GHDL) $(GHDLFLAGS) -r lx_dad_top_tb --stop-time=10000ns --vcd=$@.vcd --wave=$@.ghw
+
+analyze-all: $(SRC)
+       $(GHDL) $(GHDLFLAGS) -a $(ANALYZEFLAGS) $(SRC)
+
+
+clean:
+       rm -f convert_bin2bits
+       rm -f *.o
+       $(GHDL) --clean
+       $(RM) work-obj93.cf

diff --git a/hw/tb/lx_dad_top_tb.vhd b/hw/tb/lx_dad_top_tb.vhd
new file mode 100644 (file)
index 0000000..43f18b7
--- /dev/null
+++ b/hw/tb/lx_dad_top_tb.vhd
@@ -0,0 +1,174 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.all;
+
+LIBRARY std;
+USE std.textio.all;
+
+ENTITY lx_dad_top_tb IS
+END lx_dad_top_tb;
+
+ARCHITECTURE behavior OF lx_dad_top_tb IS
+
+    -- Component Declaration for the Unit Under Test (UUT)
+
+    COMPONENT lx_dad_top
+    PORT(
+         --clk_cpu : IN  std_logic;
+                                clk_50m : IN  std_logic;
+         cs0_xc : IN  std_logic;
+         rd : IN  std_logic;
+         bls : IN  std_logic_vector(3 downto 0);
+         address : IN  std_logic_vector(15 downto 0);
+         data : INOUT  std_logic_vector(31 downto 0);
+
+         init : IN  std_logic
+        );
+    END COMPONENT;
+
+
+   --Inputs
+   --signal clk_cpu : std_logic := '0';
+        signal clk_50m : std_logic := '0';
+   signal cs0_xc : std_logic := '1';
+   signal rd : std_logic := '1';
+   signal bls : std_logic_vector(3 downto 0) := (others => '1');
+   signal address : std_logic_vector(15 downto 0) := (others => '0');
+
+   signal init : std_logic := '1';
+        --BiDirs
+
+   signal data : std_logic_vector(31 downto 0);
+
+   -- Clock period definitions
+        --constant clk_period_cpu : time := 13.8 ns;
+   constant clk_period_50m : time := 20 ns;
+
+BEGIN
+
+       -- Instantiate the Unit Under Test (UUT)
+   uut: lx_dad_top PORT MAP (
+          --clk_cpu => clk_cpu,
+                                       clk_50m => clk_50m,
+          cs0_xc => cs0_xc,
+          rd => rd,
+          bls => bls,
+          address => address,
+          data => data,
+
+          init => init
+        );
+
+   -- Clock process definitions
+--   clk_cpu_process :process
+--   begin
+--             clk_cpu <= '1';
+--             wait for clk_period_cpu/2;
+--             clk_cpu <= '0';
+--             wait for clk_period_cpu/2;
+--   end process;
+
+        clk_50m_process :process
+   begin
+               clk_50m <= '1';
+               wait for clk_period_50m/2;
+               clk_50m <= '0';
+               wait for clk_period_50m/2;
+   end process;
+
+
+   -- Stimulus process
+   stim_proc: process
+   begin
+      -- External ModelSim script
+
+      wait;
+   end process;
+
+       setup_imem_process : process
+       --      file imem_file : text open READ_MODE is "imem.bits";
+       --      variable my_line : LINE;
+       --      variable bits_line : LINE;
+       --      variable mem_location : bit_vector(31 downto 0);
+       --      variable imem_fill_addr : natural range 0 to 2**8-1 := 0;
+       begin
+
+               -- Assert LX_DAD system reset for 3 clock cycles
+               wait until clk_50m'event and clk_50m = '1';
+               init <= '0';
+               wait until clk_50m'event and clk_50m = '1';
+               wait until clk_50m'event and clk_50m = '1';
+               wait until clk_50m'event and clk_50m = '1';
+               init <= '1';
+
+               -- Fill Tumbl instruction memory
+               --fill_loop: while not endfile(imem_file) loop
+               --      wait until clk_50m'event and clk_50m = '1';
+               --      cs0_xc <= '1';
+               --      rd <= '1';
+               --      bls <= "1111";
+               --      wait until clk_50m'event and clk_50m = '1';
+               --      address <= std_logic_vector(to_unsigned(imem_fill_addr, 16));
+               --      readline(imem_file, bits_line);
+               --      read(bits_line, mem_location);
+               --      data <= to_stdLogicVector(mem_location);
+               --      bls <= "0000";
+               --      cs0_xc <= '0';
+               --      imem_fill_addr := imem_fill_addr + 1;
+               --      wait until clk_50m'event and clk_50m = '1';
+               --      wait until clk_50m'event and clk_50m = '1';
+               --      cs0_xc <= '1';
+               --      rd <= '1';
+               --      bls <= "1111";
+               --end loop fill_loop;
+
+               -- Write to example bus memory
+               wait until clk_50m'event and clk_50m = '1';
+               wait until clk_50m'event and clk_50m = '1';
+               address <= x"0004";
+               data <= x"12345678";
+               bls <= "0000";
+               cs0_xc <= '0';
+               wait until clk_50m'event and clk_50m = '1';
+               wait until clk_50m'event and clk_50m = '1';
+               cs0_xc <= '1';
+               rd <= '1';
+               data <= x"abcdef01";
+               bls <= "1111";
+               data <= (others => 'Z');
+               wait until clk_50m'event and clk_50m = '1';
+
+               -- Simulate external master accesses example bus memory
+               xmem_loop: loop
+                       wait until clk_50m'event and clk_50m = '1';
+                       wait until clk_50m'event and clk_50m = '1';
+                       address <= x"0000";
+                       rd <= '0';
+                       cs0_xc <= '0';
+                       wait until clk_50m'event and clk_50m = '1';
+                       wait until clk_50m'event and clk_50m = '1';
+                       wait until clk_50m'event and clk_50m = '1';
+                       wait until clk_50m'event and clk_50m = '1';
+                       cs0_xc <= '1';
+                       rd <= '1';
+                       bls <= "1111";
+
+                       wait until clk_50m'event and clk_50m = '1';
+                       wait until clk_50m'event and clk_50m = '1';
+                       address <= x"0004";
+                       rd <= '0';
+                       cs0_xc <= '0';
+                       wait until clk_50m'event and clk_50m = '1';
+                       wait until clk_50m'event and clk_50m = '1';
+                       wait until clk_50m'event and clk_50m = '1';
+                       wait until clk_50m'event and clk_50m = '1';
+                       cs0_xc <= '1';
+                       rd <= '1';
+                       bls <= "1111";
+               end loop xmem_loop;
+
+               wait;
+
+       end process;
+
+END;

diff --git a/hw/tb/test-lx-dad.gtkw b/hw/tb/test-lx-dad.gtkw
new file mode 100644 (file)
index 0000000..97fe9d7
--- /dev/null
+++ b/hw/tb/test-lx-dad.gtkw
@@ -0,0 +1,37 @@
+[*]
+[*] GTKWave Analyzer v3.3.37 (w)1999-2012 BSI
+[*] Sun Feb 15 02:38:56 2015
+[*]
+[dumpfile] "/mnt/sshfs/pc-pisa/home/pi/repo/lx-dad/hw/tb/test-lx-dad.ghw"
+[dumpfile_mtime] "Sun Feb 15 02:35:59 2015"
+[dumpfile_size] 38278
+[savefile] "/mnt/sshfs/pc-pisa/home/pi/repo/lx-dad/hw/tb/test-lx-dad.gtkw"
+[timestart] 606700000
+[size] 1000 600
+[pos] -1 -1
+*-27.000000 860000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] top.
+[sst_width] 210
+[signals_width] 166
+[sst_expanded] 1
+[sst_vpaned_height] 154
+@28
+top.lx_dad_top_tb.uut.clk_50m
+@22
+#{top.lx_dad_top_tb.uut.bls[3:0]} top.lx_dad_top_tb.uut.bls[3] top.lx_dad_top_tb.uut.bls[2] top.lx_dad_top_tb.uut.bls[1] top.lx_dad_top_tb.uut.bls[0]
+@28
+top.lx_dad_top_tb.uut.cs0_xc
+@22
+#{top.lx_dad_top_tb.data[31:0]} top.lx_dad_top_tb.data[31] top.lx_dad_top_tb.data[30] top.lx_dad_top_tb.data[29] top.lx_dad_top_tb.data[28] top.lx_dad_top_tb.data[27] top.lx_dad_top_tb.data[26] top.lx_dad_top_tb.data[25] top.lx_dad_top_tb.data[24] top.lx_dad_top_tb.data[23] top.lx_dad_top_tb.data[22] top.lx_dad_top_tb.data[21] top.lx_dad_top_tb.data[20] top.lx_dad_top_tb.data[19] top.lx_dad_top_tb.data[18] top.lx_dad_top_tb.data[17] top.lx_dad_top_tb.data[16] top.lx_dad_top_tb.data[15] top.lx_dad_top_tb.data[14] top.lx_dad_top_tb.data[13] top.lx_dad_top_tb.data[12] top.lx_dad_top_tb.data[11] top.lx_dad_top_tb.data[10] top.lx_dad_top_tb.data[9] top.lx_dad_top_tb.data[8] top.lx_dad_top_tb.data[7] top.lx_dad_top_tb.data[6] top.lx_dad_top_tb.data[5] top.lx_dad_top_tb.data[4] top.lx_dad_top_tb.data[3] top.lx_dad_top_tb.data[2] top.lx_dad_top_tb.data[1] top.lx_dad_top_tb.data[0]
+@28
+top.lx_dad_top_tb.uut.memory_bus_example.example_mem_ce_s
+top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.en_m
+top.lx_dad_top_tb.uut.memory_bus_example.example_mem_ce_r
+@22
+#{top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.we_m[3:0]} top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.we_m[3] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.we_m[2] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.we_m[1] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.we_m[0]
+#{top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.addr_m[9:0]} top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.addr_m[9] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.addr_m[8] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.addr_m[7] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.addr_m[6] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.addr_m[5] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.addr_m[4] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.addr_m[3] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.addr_m[2] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.addr_m[1] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.addr_m[0]
+#{top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.din_m[31:0]} top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.din_m[31] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.din_m[30] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.din_m[29] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.din_m[28] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.din_m[27] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.din_m[26] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.din_m[25] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.din_m[24] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.din_m[23] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.din_m[22] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.din_m[21] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.din_m[20] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.din_m[19] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.din_m[18] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.din_m[17] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.din_m[16] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.din_m[15] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.din_m[14] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.din_m[13] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.din_m[12] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.din_m[11] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.din_m[10] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.din_m[9] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.din_m[8] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.din_m[7] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.din_m[6] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.din_m[5] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.din_m[4] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.din_m[3] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.din_m[2] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.din_m[1] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.din_m[0]
+#{top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.dout_m[31:0]} top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.dout_m[31] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.dout_m[30] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.dout_m[29] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.dout_m[28] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.dout_m[27] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.dout_m[26] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.dout_m[25] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.dout_m[24] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.dout_m[23] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.dout_m[22] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.dout_m[21] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.dout_m[20] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.dout_m[19] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.dout_m[18] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.dout_m[17] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.dout_m[16] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.dout_m[15] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.dout_m[14] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.dout_m[13] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.dout_m[12] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.dout_m[11] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.dout_m[10] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.dout_m[9] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.dout_m[8] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.dout_m[7] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.dout_m[6] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.dout_m[5] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.dout_m[4] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.dout_m[3] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.dout_m[2] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.dout_m[1] top.lx_dad_top_tb.uut.memory_bus_example.example_mem_instance.dout_m[0]
+#{top.lx_dad_top_tb.uut.data_read_s[31:0]} top.lx_dad_top_tb.uut.data_read_s[31] top.lx_dad_top_tb.uut.data_read_s[30] top.lx_dad_top_tb.uut.data_read_s[29] top.lx_dad_top_tb.uut.data_read_s[28] top.lx_dad_top_tb.uut.data_read_s[27] top.lx_dad_top_tb.uut.data_read_s[26] top.lx_dad_top_tb.uut.data_read_s[25] top.lx_dad_top_tb.uut.data_read_s[24] top.lx_dad_top_tb.uut.data_read_s[23] top.lx_dad_top_tb.uut.data_read_s[22] top.lx_dad_top_tb.uut.data_read_s[21] top.lx_dad_top_tb.uut.data_read_s[20] top.lx_dad_top_tb.uut.data_read_s[19] top.lx_dad_top_tb.uut.data_read_s[18] top.lx_dad_top_tb.uut.data_read_s[17] top.lx_dad_top_tb.uut.data_read_s[16] top.lx_dad_top_tb.uut.data_read_s[15] top.lx_dad_top_tb.uut.data_read_s[14] top.lx_dad_top_tb.uut.data_read_s[13] top.lx_dad_top_tb.uut.data_read_s[12] top.lx_dad_top_tb.uut.data_read_s[11] top.lx_dad_top_tb.uut.data_read_s[10] top.lx_dad_top_tb.uut.data_read_s[9] top.lx_dad_top_tb.uut.data_read_s[8] top.lx_dad_top_tb.uut.data_read_s[7] top.lx_dad_top_tb.uut.data_read_s[6] top.lx_dad_top_tb.uut.data_read_s[5] top.lx_dad_top_tb.uut.data_read_s[4] top.lx_dad_top_tb.uut.data_read_s[3] top.lx_dad_top_tb.uut.data_read_s[2] top.lx_dad_top_tb.uut.data_read_s[1] top.lx_dad_top_tb.uut.data_read_s[0]
+[pattern_trace] 1
+[pattern_trace] 0