projects / fpga / openmsp430.git / shortlog
| 2011-05-18 | Vladimir Burian | Submodule uart master | commit | commitdiff | tree | snapshot |
| 2011-04-14 | Vladimir Burian | New top module with external data bus | commit | commitdiff | tree | snapshot |
| 2011-03-10 | Vladimir Burian | Added ready to use openMSP430 entity. | commit | commitdiff | tree | snapshot |
| 2011-03-10 | Vladimir Burian | Added uart submodule. | commit | commitdiff | tree | snapshot |
| 2011-03-10 | Vladimir Burian | Add custom generics RAM. | commit | commitdiff | tree | snapshot |
| 2011-03-10 | Vladimir Burian | Added samples of Coregen memories. | commit | commitdiff | tree | snapshot |
| 2011-03-10 | Vladimir Burian | Renamed file with openMSP430 defines. | commit | commitdiff | tree | snapshot |
| 2011-02-27 | Vladimir Burian | OpenMSP430 core verilog source files moved to "core... | commit | commitdiff | tree | snapshot |
| 2011-01-08 | Vladimir Burian | Added partial copy of openMSP430. | commit | commitdiff | tree | snapshot |