Compiled files, vhdl wrappers and templates of *.bmm files are included.
--- /dev/null
+# Date: Sat Jan 8 21:37:24 2011
+SET addpads = False
+SET asysymbol = True
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = False
+SET designentry = VHDL
+SET device = xc2v1000
+SET devicefamily = virtex2
+SET flowvendor = Foundation_iSE
+SET formalverification = False
+SET foundationsym = False
+SET implementationfiletype = Ngc
+SET package = fg456
+SET removerpms = False
+SET simulationfiles = Behavioral
+SET speedgrade = -6
+SET verilogsim = False
+SET vhdlsim = True
+
--- /dev/null
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.4e
+$g;x52=#Zl|b
\7fdaa:!3-576):9$9,)=401274>6789:;<=>?0123456789:;<=>?0123456789:;<=>?0123456789:;<=>?0123455<9'::?6?>:HLSQQ<flmx7==4?>e91r4678om?9;#9119;>LHW]]0oec28:1<26>>=G\^[YY4kotv?3?69?2KOH_2?>99B@AT;994<7LJKR=3=3>GCL[692:5NDEP?7;1<IMNY0908;@FGV939?2KOH_29>69B@AT;?7=0MIJ]<9<4?DBCZ535>6L73:@V76=E]=20NX]PIODL7>EKC01HC@CFTUGG3>EUMH^NH85KI=2=1>BN484>7IG32?78@L:46<1OE1:15:FJ80823MC7:3;4DH>4:3=CAY6;285KO=2=1>BH484>7IA32?78@J:46<1OC1:15:FL80823ME7:3;4DN>4:3=CGY6;2?5JN09D7>AIL81B46GAIUR\45><AGC_\R>>8:KMMQVX8;20ECG[P^20<>OIA]ZT<964IOKWTZ6202CEEY^P07:8MKOSXV:<56GAIUQWEQC03@DBXR>?7:KMMQY79>1BBDZP0358MKOSW99<7D@FT^273>OIA]U;9:5FNHV\431<AGC_S=98;HLJPZ6??2CEEYQ?969JJLRX8H=0ECG[_1@4?LHN\V:H;6GAIU]3@2=NF@^T<H94IOKW[5@03@DBXR??7:KMMQY69>1BBDZP1358MKOSW89<7D@FT^373>OIA]U:9:5FNHV\531<AGC_S<98;HLJPZ7??2CEEYQ>969JJLRX9H=0ECG[_0@4?LHN\V;H;6GAIU]2@2=NF@^T=H94IOKW[4@03@DBXR<?7:KMMQY59>1BBDZP2358MKOSW;9<7D@FT^073>OIA]U99:5FNHV\631<AGC_S?98;HLJPZ4??2CEEYQ=969JJLRX:H=0ECG[_3@4?LHN\V8H;6GAIU]1@2=NF@^T>H94IOKW[7@03@DBXR=?7:KMMQY49>1BBDZP3358MKOSW:9<7D@FT^173>OIA]U89:5FNHV\731<AGC_S>98;HLJPZ5??2CEEYQ<969JJLRX;H=0ECG[_2@4?LHN\V9H;6GAIU]0@2=NF@^T?H94IOKW[6@43@D]:6B@AEGG3>JHO@IJ@n5BakmqR`ttafdh7@gaosTfvvohf;1E<>5A1118J4743G;9?6@>329M515<F8?87C?93:L236=I9190B<7=;O00?K47;2D9=>5A2318J7543G8??6@=529M635<F;=87C<73:L1=7=I;:1E?==4N271?K253G?87C;:3:L6=7=I>;1E;?5A839M=2=IM]]D^F?4O09S0>VFZ]k0\D@PBTQJ@]d<X@DTNX]AALG:?WGJJ8<T_484SNWQG@3<[[\J@>5\SS68P\VBi2_XI_QNLHCPg>STM[U]E^GMLD18RFE>3_CN[RZVPD08S@d<_[C_IRHFRRVb?RTN\LUFCIK>d:ZJHLH_%QNI,= > RVVF%6)9)KXODGm;Y]@KWCXAGLD==5W_BMQAZOINFUGE^Z9;Yfa[Lba3QncS]|fmWgqwlii991Sh`QBakmqR`ttafd:<6Vkm^OjjjtQm{ybcc94aefq,5/03hno~%?&8:cg`w.68 =0mij}(3+4?dbcz!9";6okds*7-2=flmx#9$94aefq,3/03hno~%9&7:cg`w.?!>1jhi|'9(58eabu494j7ljkr=33>58?3hno~1??>69b`at;97=0mij}<3<4?dbcz595;6okds>7:2=flmx79394aefq83803hno~1917:cg`w:?6>1jhi|39?3a?gjlelgx|Rx9_3.#Gjtbold+5#<f3:aoo3=cag";%;5kio*2-3=cag"9%;5kio*0-3=cag"?%;5kio*6-3=cag"=%;5kio*4-3=cag6;2;5kio>2:3=cag692;5kio>0:3=cag6?2;5kio>6:3=cag6=255kio>4>5813mce0:08;emvp-6.?2ndyy&>)69gkpr/: =0hb{{(2+4?air|!>";6j`uu*6-2=cg|~#:$94dnww,2/03me~x1>17:flqq:66>1ocxz32?58`jss4:4<7iazt=6=3>bh}}6>2:5kotv?2;?<lf
\7f\7f0:4?>69gkpr;?720iigi2oeg6>ci02dloo{fle:8vdkX0q8`=95{mq-\gb)uidU3t?e!nfm1?rczHIz2;6NOxg59B?2=9rY:57h<:28277bem;09957l{o`5>4=ij>0?7)l;:c38yV7?2o91?7?<2e`f6?4200i0_:o5f483>455lko96?;79d9P5=<a=3:1=><kbd0960>>m2nm:7>51;3xW4?=n:086<==dcg1>73?1j1/n?4lf:tWe3<7280:6??tS0;9b6<42899hok=:37;=f=#im0<n6Xm5;0xq2e=92
\7f<h7>4}%c1>0=en?0;6<k55;02
\7fMge3S;=6>u8:787>x"f13l=7)l=:bd8^g5=9rim6pgi4;29?lb72900ch750;&b0?`63gk86=54od:94?"f<3l:7co<:098k`1=83.j87h>;oc0>7=<gl<1<7*n4;d2?kg42:10ch;50;&b0?`63gk86954od694?"f<3l:7co<:498k`5=83.j87h>;oc0>3=<gl81<7*n4;d2?kg42>10ei650;&b0?c73gk86=54ie594?"f<3o;7co<:098ma0=83.j87k?;oc0>7=<am?1<7*n4;g3?kg42:10ei:50;&b0?c73gk86954ie194?"f<3o;7co<:498ma4=83.j87k?;oc0>3=<am;1<7*n4;g3?kg42>10ek650;9jfd<72-k?6n:4n`194>=nk;0;6)o;:b68jd5=921bo<4?:%c7>f2<fh91>65fc183>!g32j>0bl=53:9jfc<72-k?6n:4n`190>=njl0;6)o;:b68jd5==21bni4?:%c7>f2<fh91:65fbb83>!g32j>0bl=57:9jfg<72-k?6n:4n`19<>=nj00;6)o;:b68jd5=121bn54?:%c7>f2<fh91m65mab83>4<729qCmo5+a88bg>if93:17pl=e;295?6=8rBjn6*n9;0f?j4c2900qo?;:181>5<7sAki7)o6:6;8m7`=831dm=4?::
\7fa50<72;0;6=uGac9'e<<012c9j7>5;nc3>5<<uk;86=4=1;294~Nfj2.j57o:;%1:>7=#;h097)=m:39'7f<53-9o6?5+3d81?!5a2;1/8=4=;%62>7=#<;097):<:39'01<53->>6?5+4781?!202;1/854=;%6:>7=#<h097):m:39'0f<53->o6?5+4d81?!2a2;1/9=4=;%72>7=#=;097);<:39'11<53-?>6?5+5781?!302;1/954=;%7:>7=#=h097);m:39'1f<53-?o6?5+5d81?!3a2;1/:=4=;%42>7=#>;097)8<:39'21<53-<>6?5+6781?!002;1/:54=;%4:>7=#>h097)8m:39'2f<53-<o6?5+6d81?!0a2;1/;=4=;%52>7=#?;097)9<:39'31<53-=>6?5+7781?!102;1/;54=;%13>7=#;8097)==:39'76<53-9?6?5+3481?!512;1/?:4=;%`3>d`<,:21=6*n7;38m4g=831b=o4?::k:>5<<a8i1<75f1e83>>o6m3:17d?i:188m76=831b>n4?::k15?6=3f8i6=44i983>>o6?3:17do50;9jf?6=3f886=44ib83>>i5<3:17dj50;9l60<722cn6=44o3494?=nn3:17b<8:188m46=831bmh4?::m1<?6=3`;:6=44o3;94?=n9;0;66a=a;29?l452900el650;9~w2c=839p1?k52e9>56<f027:?7<=;|q`1?6=:rTim63>3;;8 dg=001v
\7fnk50;0xZf4<5891=?5+a`8:0>{tkm0;6?uQc09>56<692.jm778;|q`g?6=:rTh<63>3;33?!gf2020q~mm:181
\7f[da34;86k5+a`8:f>{tkh0;6?uQbd9>56<b3-kj64m4}ra:>5<5sWho70?<:e9'ed<>l2wxo54?:3y]ff=:9:0h7)on:8g8yve02909wSlm;<30>g=#ih0<j6s|c783>7}Yj016=>4n;%cb>=6<uzi86=4={_`;?874211/ml471:
\7fp`5<72;qUh=5212823>"fi3297p}j1;296~Xc027:?7<>;%cb>=5<uznm6=4={_f4?8742;:0(lo5859~wac=838pRi84=0195c=#ih0396s|de83>7}Yl<16=>4>e:&be?>13tyoo7>52z\g0>;6;3;o7)on:958yvbe2909wSj<;<30>4e<,hk1455rsec94?4|Vm801<=51c9'ed<?i2wxh44?:3y]`4=:9:0:m6*na;:a?xua:3:1>vPj9:?27?4f3-kj65m4}rd3>5<5sWo370?<:3;8 dg=0m1v
\7fhh50;0xZ`1<5891>55+a`8;a>{tml0;6?uQe79>56<5?2.jm76i;|qf`?6=:rTn963>3;05?!gf20:0q~kl:181
\7f[c334;86?;4$`c9=4=z{lh1<7<t^d18945=:=1/ml462:
\7fpad<72;qUi?5212817>"fi3387p}i4;296~Xa<27:87<i;%cb><3<uzl36=4={_d;?8722;l0(lo5979~w<?=838p1<:5a19>56<5k2wx5l4?:3y>50<f827:?7oj;|
\7fm10<728qCmo5rn4494?7|@hh0qc;8:182
\7fMge3td>47>51zJbf>{i=00;6<uGac9~j0g=83;pDll4}o7a>5<6sAki7p`:c;295~Nfj2we9i4?:0yKeg=zf<o1<7?tH``8yk3a290:wEom;|l54?6=9rBjn6sa6083>4}Oik1vb;<50;3xLdd<ug<86=4>{Ica?xh1<3:1=vFnb:
\7fm20<728qCmo5rn7494?7|@hh0qc88:182
\7fMge3td=47>51zJbf>{i>00;6<uGac9~j3g=83;pDll4}o4a>5<6sAki7p`9c;295~Nfj2we:i4?:0yKeg=zf?o1<7?tH``8yk0a290:wEom;|l44?6=9rBjn6sa7083>4}Oik1vb:<50;3xLdd<ug=86=4>{Ica?xh0<3:1=vFnb:
\7fm30<728qCmo5r}|
\7fCDF}>?3>o8l7<c9
\7fCDG}7uIJ[wpNO
\ No newline at end of file
--- /dev/null
+--------------------------------------------------------------------------------
+-- This file is owned and controlled by Xilinx and must be used --
+-- solely for design, simulation, implementation and creation of --
+-- design files limited to Xilinx devices or technologies. Use --
+-- with non-Xilinx devices or technologies is expressly prohibited --
+-- and immediately terminates your license. --
+-- --
+-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
+-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
+-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
+-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
+-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
+-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
+-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
+-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
+-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
+-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
+-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
+-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
+-- FOR A PARTICULAR PURPOSE. --
+-- --
+-- Xilinx products are not intended for use in life support --
+-- appliances, devices, or systems. Use in such applications are --
+-- expressly prohibited. --
+-- --
+-- (c) Copyright 1995-2007 Xilinx, Inc. --
+-- All rights reserved. --
+--------------------------------------------------------------------------------
+-- You must compile the wrapper file ram_8x2k.vhd when simulating
+-- the core, ram_8x2k. When compiling the wrapper file, be sure to
+-- reference the XilinxCoreLib VHDL simulation library. For detailed
+-- instructions, please refer to the "CORE Generator Help".
+
+-- The synthesis directives "translate_off/translate_on" specified
+-- below are supported by Xilinx, Mentor Graphics and Synplicity
+-- synthesis tools. Ensure they are correct for your synthesis tool(s).
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+-- synthesis translate_off
+Library XilinxCoreLib;
+-- synthesis translate_on
+ENTITY ram_8x2k IS
+ port (
+ addr: IN std_logic_VECTOR(10 downto 0);
+ clk: IN std_logic;
+ din: IN std_logic_VECTOR(7 downto 0);
+ dout: OUT std_logic_VECTOR(7 downto 0);
+ en: IN std_logic;
+ we: IN std_logic);
+END ram_8x2k;
+
+ARCHITECTURE ram_8x2k_a OF ram_8x2k IS
+-- synthesis translate_off
+component wrapped_ram_8x2k
+ port (
+ addr: IN std_logic_VECTOR(10 downto 0);
+ clk: IN std_logic;
+ din: IN std_logic_VECTOR(7 downto 0);
+ dout: OUT std_logic_VECTOR(7 downto 0);
+ en: IN std_logic;
+ we: IN std_logic);
+end component;
+
+-- Configuration specification
+ for all : wrapped_ram_8x2k use entity XilinxCoreLib.blkmemsp_v6_2(behavioral)
+ generic map(
+ c_sinit_value => "0",
+ c_has_en => 1,
+ c_reg_inputs => 0,
+ c_yclk_is_rising => 1,
+ c_ysinit_is_high => 1,
+ c_ywe_is_high => 0,
+ c_yprimitive_type => "16kx1",
+ c_ytop_addr => "1024",
+ c_yhierarchy => "hierarchy1",
+ c_has_limit_data_pitch => 0,
+ c_has_rdy => 0,
+ c_write_mode => 0,
+ c_width => 8,
+ c_yuse_single_primitive => 0,
+ c_has_nd => 0,
+ c_has_we => 1,
+ c_enable_rlocs => 0,
+ c_has_rfd => 0,
+ c_has_din => 1,
+ c_ybottom_addr => "0",
+ c_pipe_stages => 0,
+ c_yen_is_high => 0,
+ c_depth => 2048,
+ c_has_default_data => 1,
+ c_limit_data_pitch => 18,
+ c_has_sinit => 0,
+ c_yydisable_warnings => 1,
+ c_mem_init_file => "mif_file_16_1",
+ c_default_data => "0",
+ c_ymake_bmm => 0,
+ c_addr_width => 11);
+-- synthesis translate_on
+BEGIN
+-- synthesis translate_off
+U0 : wrapped_ram_8x2k
+ port map (
+ addr => addr,
+ clk => clk,
+ din => din,
+ dout => dout,
+ en => en,
+ we => we);
+-- synthesis translate_on
+
+END ram_8x2k_a;
+
--- /dev/null
+##############################################################
+#
+# Xilinx Core Generator version J.36
+# Date: Sun Mar 6 15:37:58 2011
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = False
+SET asysymbol = True
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = False
+SET designentry = VHDL
+SET device = xc2v1000
+SET devicefamily = virtex2
+SET flowvendor = Foundation_iSE
+SET formalverification = False
+SET foundationsym = False
+SET implementationfiletype = Ngc
+SET package = fg456
+SET removerpms = False
+SET simulationfiles = Behavioral
+SET speedgrade = -6
+SET verilogsim = False
+SET vhdlsim = True
+# END Project Options
+# BEGIN Select
+SELECT Single_Port_Block_Memory family Xilinx,_Inc. 6.2
+# END Select
+# BEGIN Parameters
+CSET active_clock_edge=Rising_Edge_Triggered
+CSET additional_output_pipe_stages=0
+CSET component_name=ram_8x2k
+CSET depth=2048
+CSET disable_warning_messages=true
+CSET enable_pin=true
+CSET enable_pin_polarity=Active_Low
+CSET global_init_value=0
+CSET handshaking_pins=false
+CSET has_limit_data_pitch=false
+CSET init_pin=false
+CSET init_value=0
+CSET initialization_pin_polarity=Active_High
+CSET limit_data_pitch=18
+CSET load_init_file=false
+CSET port_configuration=Read_And_Write
+CSET primitive_selection=Optimize_For_Area
+CSET register_inputs=false
+CSET select_primitive=16kx1
+CSET width=8
+CSET write_enable_polarity=Active_Low
+CSET write_mode=Read_After_Write
+# END Parameters
+GENERATE
+# CRC: 194ee8e4
+
--- /dev/null
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.4e
+$dax52=#Zl|b
\7fdaa:!3-576):9$9,)?40528456789:;<=>?0123456789:;<=>?0123456789:;<=>?0123456789:;<=>?01237>7)8890=?4FNQWW>dbcz5;:6=0k;3t2456ao=?=!;??;98JJUSS2mce0:4?>008<?IR\Y__6iazt=594;1<IMNY0=07;@FGV977611JHI\310<4?DBCZ5;5;6OKDS>1:2=FLMX7?394AEFQ81803HNO^1;17:CG@W:16>1JHI\37?58EABU414<7LJKR=;=7>D6:;1I4>5MU218FP2?3K_XSD@IO29@HN?<KFGFEYZJD69@V@GSMM?0HD2?>49GM979=2NB0?0:;EK?7;3<LF6;285KO=3=1>BH4;4>7IA33?08AK7<O:1LBI?4I89JJLRT\H^N;6GAIU]342=NF@^T<<94IOKW[5403@DBXR><7:KMMQY7<>1BBDZP0458MKOSW9<<7D@FT^243>OIA]U;4:5FNHV\4<1<AGC_S=O8;HLJPZ6E?2CEEYQ?C69JJLRX8M=0ECG[_1G4?LHN\V:M;6GAIU]242=NF@^T=<94IOKW[4403@DBXR?<7:KMMQY6<>1BBDZP1458MKOSW8<<7D@FT^343>OIA]U:4:5FNHV\5<1<AGC_S<O8;HLJPZ7E?2CEEYQ>C69JJLRX9M=0ECG[_0G4?LHN\V;M;6GAIU]142=NF@^T><94IOKW[7403@DBXR<<7:KMMQY5<>1BBDZP2458MKOSW;<<7D@FT^043>OIA]U94:5FNHV\6<1<AGC_S?O8;HLJPZ4E?2CEEYQ=C69JJLRX:M=0ECG[_3G4?LHN\V8M;6GAIU]042=NF@^T?<94IOKW[6403@DBXR=<7:KMMQY4<>1BBDZP3458MKOSW:<<7D@FT^143>OIA]U84:5FNHV\7<1<AGC_S>O8;HLJPZ5E?2CEEYQ<C69JJLRX;M=0ECG[_2G4?LHN\V9M?6GAV79OKDBBL>1GCJGLAMa8Idlhz_oy
\7fdaac:OjjjtQm{ybcc<4N118J4643G;:?6@>229M565<F8>87C?:3:L226=I9>90B<6<;O3:6>H5;2D9<>5A2018J7443G88?6@=429M605<F;<87C<83:L1<6=I:080B>=4N220?K56;2D8:?5A439M16=I=>80B;=4N731?K153G297C78;OGWSJTL92E:7]:4P@PWe>VNFVH^_DJWb:RJJZDR[GKFI45]AL@22ZU3>2YDY_MJ5:QQRDJ43ZYY86ZVPDc8QVCUWHFBM^m4URGQ[SOTAKFN?6XLC89UM@QX\PZN>6YJb:UQMQCXN@XXXl5XRHVF[HICM8n0TDBFNY/[@G&7&8*XXXL/0/3#EVENAk1SSNA]E^KMBJ773QUHC_KPIODL[IOT\?1ShoQFdg9[`mYWz`g]i
\7f}foo33?]bjWDkac
\7fXjrrklj46<PmgTAd``rWgqwlii?2koh
\7f&?)69b`at/9 20mij}(02*<>gcl{":=$94aefq,7/03hno~%=&7:cg`w.3!>1jhi|'5(58eabu ?#<7ljkr)5*3>gcl{"3%:5ndep+=,1<imny0=07;`fgv9776h1jhi|31083:==flmx7=<08;`fgv979?2koh
\7f2=>69b`at;;7=0mij}<5<4?dbcz5?5;6okds>5:2=flmx7;394aefq8=803hno~1711c9ahnkbezzTz;Q=,!Alv`abf)3%>d=4cmi5?aoi 9#=7iga(0+5?aoi ;#=7iga(2+5?aoi =#=7iga(4+5?aoi ?#=7iga(6+5?aoi494=7iga<0<5?aoi4;4=7iga<2<5?aoi4=4=7iga<4<5?aoi4?437iga<683:3=cag6<2:5kotv+4,1<lf
\7f\7f$<'8;emvp-4.?2ndyy&<)69gkpr/< =0hb{{(4+4?air|!<";6j`uu*4-2=cg|~7<394dnww84803me~x1<17:flqq:46>1ocxz34?58`jss4<4<7iazt=4==>bh}}6<6=08;emvp91902ooek<age08ak><fniiydbk8:pbiZ>
\7f<b;?7yc
\7f/^ad+wgjW1r?g#`ho39taxFGxhk0LMvja;D90?7|[8h1i;4<:011`gc52;?3i8uaa682?kg?2=1/m84n2:
\7fP5d<b>391=><kbd0960>b=2Y=m7k7:18277bem;0995k9;R3b>`>=83;8>ilj2;06<`1<ll31<7?51zQ2f?c12:0:??jme3811=c23-k86n<4vU;4>5<62809>v]>b;g5>6<6;;nii?4=59g6?!?b2?h0Zl852zw5g?7<}?n1<6s+9286?gc>290:j78523yK=f=]9108w:49:58~ <g=m01/m>4l2:Xb0?7|k;0veh950;9jg6<722eoo7>5$879a1=i1=0;76akb;29 <3=m=1e594>;:mge?6=,0?1i95a9581?>ic13:1(4;5e59m=1<432eo47>5$879a1=i1=0?76ak7;29 <3=m=1e594:;:mg2?6=,0?1i95a9585?>ic=3:1(4;5e59m=1<032chn7>5$879`6=i1=0;76gla;29 <3=l:1e594>;:k`=?6=,0?1h>5a9581?>od03:1(4;5d29m=1<432ch;7>5$879`6=i1=0?76gl6;29 <3=l:1e594:;:k`1?6=,0?1h>5a9585?>od<3:1(4;5d29m=1<032cnn7>5;hc`>5<#1<0i;6`64;28?lge290/584m7:l:0?7<3`h?6=4+948a3>h><3807dl<:18'=0<e?2d287=4;h`1>5<#1<0i;6`64;68?ld6290/584m7:l:0?3<3`h;6=4+948a3>h><3<07doi:18'=0<e?2d28794;hcf>5<#1<0i;6`64;:8?lgc290/584m7:l:0??<3`kj6=4+948a3>h><3k07do6:18'=0<e?2d287l4;c;g>5<6290;wE7l;%;b><b<g081<75rb3494?7=83:pD4m4$8c963=h:<0;66sm1783>7<729qC5n5+9`85=>o5?3:17b7>:188yg7029096=4?{I;`?!?f2?30e?950;9l=4<722wi=84?:0:94?6|@0i0(4o5979'6<<53-8j6?5+2c81?!4d2;1/>i4=;%0f>7=#:o097)=?:39'74<53-996?5+3281?!532;1/?84=;%15>7=#;>097)=7:39'7<<53-9j6?5+3c81?!5d2;1/?i4=;%1f>7=#;o097):?:39'04<53->96?5+4281?!232;1/884=;%65>7=#<>097):7:39'0<<53->j6?5+4c81?!2d2;1/8i4=;%6f>7=#<o097);?:39'14<53-?96?5+5281?!332;1/984=;%75>7=#=>097);7:39'1<<53-?j6?5+5c81?!3d2;1/9i4=;%7f>7=#=o097)8?:39'24<53-<96?5+6281?!032;1/:84=;%45>7=#>>097)87:39'e4<f82.947?4$8:95>o6k3:17d?k:188m<<722c:i7>5;hc94?=n9o0;66g=4;29?l>=831b=44?::ka>5<<aj0;66a=0;29?lb=831d><4?::kf>5<<g;81<75ff;29?j442900e<>50;9j54<722c2j7>5;h31>5<<a891<75f9883>>{e9=0;6<650;2xL<e<,0k15;5+2881?!4f2;1/>o4=;%0`>7=#:m097)<j:39'6c<53-9;6?5+3081?!552;1/?>4=;%17>7=#;<097)=9:39'72<53-936?5+3881?!5f2;1/?o4=;%1`>7=#;m097)=j:39'7c<53->;6?5+4081?!252;1/8>4=;%67>7=#<<097):9:39'02<53->36?5+4881?!2f2;1/8o4=;%6`>7=#<m097):j:39'0c<53-?;6?5+5081?!352;1/9>4=;%77>7=#=<097);9:39'12<53-?36?5+5881?!3f2;1/9o4=;%7`>7=#=m097);j:39'1c<53-<;6?5+6081?!052;1/:>4=;%47>7=#><097)89:39'22<53-<36?5+a08b4>"503;0(4651:k2g?6=3`;o6=44i883>>o6m3:17do50;9j5c<722c987>5;h:94?=n900;66gm:188mf<722e9<7>5;hf94?=h:80;66gj:188k74=831bj7>5;n00>5<<a8:1<75f1083>>o>n3:17d?=:188m45=831b544?::
\7fp2`<72:q6>;4=5:?21??>34;?6474}r`;>5<4sWkh70?::`9>51<f3-3i6:74}r`5>5<4sWki70?::89>51<>3-3i65:4}ra2>5<4sWh?70?::018942=9:1/5o478:
\7fpg5<72:qUn>5214826>;6<3;97)7m:9;8yvda2908wSl=;<36>47<58>1=<5+9c8;f>{tjl0;6>uQb09>50<6827:87??;%;a>=b<uzho6=4<{_`3?8722o16=94i;%;a>=c<uzhh6=4<{_ce?8722l16=94j;%;a>=`<uzhi6=4<{_cf?8722m16=94k;%;a>3`<uzhj6=4<{_cg?8722j16=94l;%;a>26<uzh26=4<{_cb?8722k16=94m;%;a>27<uzh>6=4<{_c:?8722116=947;%;a>24<uzi86=4<{_a0?87228301<:5189'=g<0;2wxh94?:3y]gg=:9=0:j6*6b;57?xuc:3:1>vPla:?20?7b3-3i6:;4}rf2>5<5sWi270?;:0f8 <d=??1v
\7fi>50;0xZf><58>1=n5+9c843>{tko0;6?uQc69>50<6n2.2n797;|q`a?6=:rTh:63>5;3f?!?e2>k0q~mk:181
\7f[e234;>6<j4$8`93g=z{ji1<7<t^b68943=9j1/5o48c:
\7fpa0<72;qUhn5215817>">j3=o7p}j3;296~Xcj27:87<=;%;a>2c<uzo96=4={_fb?8732;;0(4l57g9~w`7=838pRi74=06965=#1k03<6s|e183>7}Yl116=84=3:&:f?>63tyoj7>52z\g3>;6=3897)7m:908yvbb2909wSj9;<36>77<,0h14>5rsef94?4|Vm?01<;5219'=g<?=2wxi:4?:3y]a2=:9?09;6*6b;:5?xubj3:1>vPjb:?23?403-3i6594}r:b>5<4s4;=64?4=07961=:9=0986s|8b83>6}:9>02=63>5;;e?87320l0qp`96;295~N>k2we::4?:0yK=f=zf?21<7?tH8a8yk0>290:wE7l;|l5e?6=9rB2o6sa6c83>4}O1j1vb;m50;3xL<e<ug<o6=4>{I;`?xh1m3:1=vF6c:
\7fm2c<728qC5n5rn6294?7|@0i0qc9>:182
\7fM?d3td<>7>51zJ:g>{i?:0;6<uG9b9~j22=83;pD4m4}o56>5<6sA3h7p`86;295~N>k2we;:4?:0yK=f=zf>21<7?tH8a8yk1>290:wE7l;|l4e?6=9rB2o6sa7c83>4}O1j1vb:m50;3xL<e<ug=o6=4>{I;`?xh0m3:1=vF6c:
\7fm3c<728qC5n5rn9294?7|@0i0qc6>:182
\7fM?d3td3>7>51zJ:g>{i0:0;6<uG9b9~j=2=83;pD4m4}o:6>5<6sA3h7p`76;295~N>k2we4:4?:0yK=f=zutwKLNuna;d1b``c<;wKLOu?}ABS
\7fxFG
\ No newline at end of file
--- /dev/null
+--------------------------------------------------------------------------------
+-- This file is owned and controlled by Xilinx and must be used --
+-- solely for design, simulation, implementation and creation of --
+-- design files limited to Xilinx devices or technologies. Use --
+-- with non-Xilinx devices or technologies is expressly prohibited --
+-- and immediately terminates your license. --
+-- --
+-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
+-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
+-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
+-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
+-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
+-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
+-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
+-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
+-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
+-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
+-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
+-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
+-- FOR A PARTICULAR PURPOSE. --
+-- --
+-- Xilinx products are not intended for use in life support --
+-- appliances, devices, or systems. Use in such applications are --
+-- expressly prohibited. --
+-- --
+-- (c) Copyright 1995-2007 Xilinx, Inc. --
+-- All rights reserved. --
+--------------------------------------------------------------------------------
+-- You must compile the wrapper file ram_8x4k.vhd when simulating
+-- the core, ram_8x4k. When compiling the wrapper file, be sure to
+-- reference the XilinxCoreLib VHDL simulation library. For detailed
+-- instructions, please refer to the "CORE Generator Help".
+
+-- The synthesis directives "translate_off/translate_on" specified
+-- below are supported by Xilinx, Mentor Graphics and Synplicity
+-- synthesis tools. Ensure they are correct for your synthesis tool(s).
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+-- synthesis translate_off
+Library XilinxCoreLib;
+-- synthesis translate_on
+ENTITY ram_8x4k IS
+ port (
+ addr: IN std_logic_VECTOR(11 downto 0);
+ clk: IN std_logic;
+ din: IN std_logic_VECTOR(7 downto 0);
+ dout: OUT std_logic_VECTOR(7 downto 0);
+ en: IN std_logic;
+ we: IN std_logic);
+END ram_8x4k;
+
+ARCHITECTURE ram_8x4k_a OF ram_8x4k IS
+-- synthesis translate_off
+component wrapped_ram_8x4k
+ port (
+ addr: IN std_logic_VECTOR(11 downto 0);
+ clk: IN std_logic;
+ din: IN std_logic_VECTOR(7 downto 0);
+ dout: OUT std_logic_VECTOR(7 downto 0);
+ en: IN std_logic;
+ we: IN std_logic);
+end component;
+
+-- Configuration specification
+ for all : wrapped_ram_8x4k use entity XilinxCoreLib.blkmemsp_v6_2(behavioral)
+ generic map(
+ c_sinit_value => "0",
+ c_has_en => 1,
+ c_reg_inputs => 0,
+ c_yclk_is_rising => 1,
+ c_ysinit_is_high => 1,
+ c_ywe_is_high => 0,
+ c_yprimitive_type => "16kx1",
+ c_ytop_addr => "1024",
+ c_yhierarchy => "hierarchy1",
+ c_has_limit_data_pitch => 0,
+ c_has_rdy => 0,
+ c_write_mode => 0,
+ c_width => 8,
+ c_yuse_single_primitive => 0,
+ c_has_nd => 0,
+ c_has_we => 1,
+ c_enable_rlocs => 0,
+ c_has_rfd => 0,
+ c_has_din => 1,
+ c_ybottom_addr => "0",
+ c_pipe_stages => 0,
+ c_yen_is_high => 0,
+ c_depth => 4096,
+ c_has_default_data => 1,
+ c_limit_data_pitch => 18,
+ c_has_sinit => 0,
+ c_yydisable_warnings => 1,
+ c_mem_init_file => "mif_file_16_1",
+ c_default_data => "0",
+ c_ymake_bmm => 0,
+ c_addr_width => 12);
+-- synthesis translate_on
+BEGIN
+-- synthesis translate_off
+U0 : wrapped_ram_8x4k
+ port map (
+ addr => addr,
+ clk => clk,
+ din => din,
+ dout => dout,
+ en => en,
+ we => we);
+-- synthesis translate_on
+
+END ram_8x4k_a;
+
--- /dev/null
+##############################################################
+#
+# Xilinx Core Generator version J.36
+# Date: Sun Mar 6 15:38:31 2011
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = False
+SET asysymbol = True
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = False
+SET designentry = VHDL
+SET device = xc2v1000
+SET devicefamily = virtex2
+SET flowvendor = Foundation_iSE
+SET formalverification = False
+SET foundationsym = False
+SET implementationfiletype = Ngc
+SET package = fg456
+SET removerpms = False
+SET simulationfiles = Behavioral
+SET speedgrade = -6
+SET verilogsim = False
+SET vhdlsim = True
+# END Project Options
+# BEGIN Select
+SELECT Single_Port_Block_Memory family Xilinx,_Inc. 6.2
+# END Select
+# BEGIN Parameters
+CSET active_clock_edge=Rising_Edge_Triggered
+CSET additional_output_pipe_stages=0
+CSET component_name=ram_8x4k
+CSET depth=4096
+CSET disable_warning_messages=true
+CSET enable_pin=true
+CSET enable_pin_polarity=Active_Low
+CSET global_init_value=0
+CSET handshaking_pins=false
+CSET has_limit_data_pitch=false
+CSET init_pin=false
+CSET init_value=0
+CSET initialization_pin_polarity=Active_High
+CSET limit_data_pitch=18
+CSET load_init_file=false
+CSET port_configuration=Read_And_Write
+CSET primitive_selection=Optimize_For_Area
+CSET register_inputs=false
+CSET select_primitive=16kx1
+CSET width=8
+CSET write_enable_polarity=Active_Low
+CSET write_mode=Read_After_Write
+# END Parameters
+GENERATE
+# CRC: d918621d
+
--- /dev/null
+/* Templates for initialization of memories created by Xilinx Coregen using
+ data2mem tool. */
+
+/* Overall size of 8kB (2x4Kb) */
+ADDRESS_SPACE blockrom RAMB16 [0xe000:0xffff]
+ BUS_BLOCK
+ rom_8x4k_lo/B12 [7:4];
+ rom_8x4k_lo/B8 [3:0];
+ rom_8x4k_hi/B12 [15:12];
+ rom_8x4k_hi/B8 [11:8];
+ END_BUS_BLOCK;
+END_ADDRESS_SPACE;
+
+/* Overall size of 4kB (2x2kB) */
+ADDRESS_SPACE blockrom RAMB16 [0xf000:0xffff]
+ BUS_BLOCK
+ rom_8x2k_lo/B8 [7:0];
+ rom_8x2k_hi/B8 [15:8];
+ END_BUS_BLOCK;
+END_ADDRESS_SPACE;
+
projects / fpga / openmsp430.git / commitdiff