See README.
--- /dev/null
+This is ready to use openMSP430 soft-core entity.
+
+Only "clk" and "reset_n" signals are needed to be connected. But all signals
+required to connect custom peripheries are present. Memories and hw uart are
+built-in, but it's possible to extend data memory because data bus is present.
+
+External data bus is capable of addressing 8 kB (4*1024 words). Physical
+memory address is shifted by 0x2200. (e.g. external memory cell with physical
+address 0x0000 is reachable by logic address 0x2200) This bus can be also
+used to connect some peripherals which doesn't support asynchronous read
+operation (as it's required by peripheral bus). But be aware that all
+requirements for data bus (listed in core documentation) must be accomplished.
+Hence you probably needs to register external address decoder.
+
+ <log addr> = <phy addr> * 2 + 0x2200
+
+
+Properties:
+
+ - Memory primitives: RAMB16_S2, RAMB16_S4
+ - Program memory size: 32 kB
+ - Data memory size: 8 kB
+ - Ext. data memory bus: yes
+ - HW multiplication: yes
+ - HW debugger: no
+ - RS232: yes
+
+To use this entity in your design you must:
+
+ - Add content of "openMSP430_8_32_mul.prj" to your top *.prj file (and possibly
+ adjust file paths in this file) or compile this project as separated module.
+ - Copy "openMSP430_8_32_mul.bmm" file, add it to your project and replace
+ <path> with logical path of your instantiated openMSP430 component.
+
--- /dev/null
+// ram_generic: 2x16kB, BRAM_TYPE=RAMB16_S2
+ADDRESS_SPACE blockrom RAMB16 [0x8000:0xffff]
+ BUS_BLOCK
+ <path>/p_ram_lo/BLOCKS[0].RAMB16_S2.B[3].BRAM [7:6];
+ <path>/p_ram_lo/BLOCKS[0].RAMB16_S2.B[2].BRAM [5:4];
+ <path>/p_ram_lo/BLOCKS[0].RAMB16_S2.B[1].BRAM [3:2];
+ <path>/p_ram_lo/BLOCKS[0].RAMB16_S2.B[0].BRAM [1:0];
+ <path>/p_ram_hi/BLOCKS[0].RAMB16_S2.B[3].BRAM [15:14];
+ <path>/p_ram_hi/BLOCKS[0].RAMB16_S2.B[2].BRAM [13:12];
+ <path>/p_ram_hi/BLOCKS[0].RAMB16_S2.B[1].BRAM [11:10];
+ <path>/p_ram_hi/BLOCKS[0].RAMB16_S2.B[0].BRAM [9:8];
+ END_BUS_BLOCK;
+ BUS_BLOCK
+ <path>/p_ram_lo/BLOCKS[1].RAMB16_S2.B[3].BRAM [7:6];
+ <path>/p_ram_lo/BLOCKS[1].RAMB16_S2.B[2].BRAM [5:4];
+ <path>/p_ram_lo/BLOCKS[1].RAMB16_S2.B[1].BRAM [3:2];
+ <path>/p_ram_lo/BLOCKS[1].RAMB16_S2.B[0].BRAM [1:0];
+ <path>/p_ram_hi/BLOCKS[1].RAMB16_S2.B[3].BRAM [15:14];
+ <path>/p_ram_hi/BLOCKS[1].RAMB16_S2.B[2].BRAM [13:12];
+ <path>/p_ram_hi/BLOCKS[1].RAMB16_S2.B[1].BRAM [11:10];
+ <path>/p_ram_hi/BLOCKS[1].RAMB16_S2.B[0].BRAM [9:8];
+ END_BUS_BLOCK;
+END_ADDRESS_SPACE;
+
+
+// ram_generic: 2x4kB, BRAM_TYPE=RAMB_S4
+ADDRESS_SPACE blockram RAMB16 [0x0200:0x21ff]
+ BUS_BLOCK
+ <path>/d_ram_lo/BLOCKS[0].RAMB16_S4.B[1].BRAM [7:4];
+ <path>/d_ram_lo/BLOCKS[0].RAMB16_S4.B[0].BRAM [3:0];
+ <path>/d_ram_hi/BLOCKS[0].RAMB16_S4.B[1].BRAM [15:12];
+ <path>/d_ram_hi/BLOCKS[0].RAMB16_S4.B[0].BRAM [11:8];
+ END_BUS_BLOCK;
+END_ADDRESS_SPACE;
+
--- /dev/null
+verilog work openmsp430/core/omsp_alu.v
+verilog work openmsp430/core/omsp_clock_module.v
+verilog work openmsp430/core/omsp_dbg.v
+verilog work openmsp430/core/omsp_dbg_hwbrk.v
+verilog work openmsp430/core/omsp_dbg_uart.v
+verilog work openmsp430/core/omsp_execution_unit.v
+verilog work openmsp430/core/omsp_frontend.v
+verilog work openmsp430/core/omsp_mem_backbone.v
+verilog work openmsp430/core/omsp_multiplier.v
+verilog work openmsp430/core/omsp_register_file.v
+verilog work openmsp430/core/omsp_sfr.v
+verilog work openmsp430/core/omsp_watchdog.v
+verilog work openmsp430/core/openMSP430.v
+
+verilog work openmsp430/core/openMSP430_undefines.v
+verilog work openmsp430/core/timescale.v
+
+vhdl work openmsp430/memory/ram_generic.vhd
+
+vhdl work openmsp430/uart/tx_control.vhd
+vhdl work openmsp430/uart/tx.vhd
+vhdl work openmsp430/uart/rx_control.vhd
+vhdl work openmsp430/uart/rx.vhd
+vhdl work openmsp430/uart/fifo.vhd
+vhdl work openmsp430/uart/baud_gen.vhd
+vhdl work openmsp430/uart/uart.vhd
+
+verilog work openmsp430/top/top_8_32_mul_dbus/openMSP430_defines.v
+vhdl work openmsp430/top/top_8_32_mul_dbus/openMSP430_8_32_mul_dbus.vhd
+
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+
+entity openMSP430_8_32_mul_dbus is
+ port (
+ -- Clocks and reset (low active)
+ dco_clk : in std_logic;
+ lfxt_clk : in std_logic;
+ reset_n : in std_logic;
+ -- RS232 interface
+ rxd : in std_logic;
+ txd : out std_logic;
+ -- Periphery interface
+ per_addr : out std_logic_vector (7 downto 0);
+ per_din : out std_logic_vector (15 downto 0);
+ per_dout : in std_logic_vector (15 downto 0);
+ per_wen : out std_logic_vector (1 downto 0);
+ per_en : out std_logic;
+ nmi : in std_logic;
+ irq : in std_logic_vector (13 downto 0);
+ irq_acc : out std_logic_vector (13 downto 0);
+ aclk_en : out std_logic;
+ smclk_en : out std_logic;
+ mclk : out std_logic;
+ puc : out std_logic;
+ -- Data bus
+ dmem_addr : out std_logic_vector (11 downto 0);
+ dmem_ce : out std_logic;
+ dmem_we : out std_logic;
+ dmem_din : out std_logic_vector (15 downto 0);
+ dmem_dout : in std_logic_vector (15 downto 0));
+end entity openMSP430_8_32_mul_dbus;
+
+--------------------------------------------------------------------------------
+
+architecture rtl of openMSP430_8_32_mul_dbus is
+
+ component openMSP430 is
+ port(
+ aclk_en : out std_logic; -- ACLK enable
+ dbg_freeze : out std_logic; -- Freeze peripherals
+ dbg_uart_txd : out std_logic; -- Debug interface: UART TXD
+ dmem_addr : out std_logic_vector; -- Data Memory address
+ dmem_cen : out std_logic; -- Data Memory chip enable (low active)
+ dmem_din : out std_logic_vector (15 downto 0); -- Data Memory data input
+ dmem_wen : out std_logic_vector (1 downto 0); -- Data Memory write enable (low active)
+ irq_acc : out std_logic_vector (13 downto 0); -- Interrupt request accepted (one-hot signal)
+ mclk : out std_logic; -- Main system clock
+ per_addr : out std_logic_vector (7 downto 0); -- Peripheral address
+ per_din : out std_logic_vector (15 downto 0); -- Peripheral data input
+ per_wen : out std_logic_vector (1 downto 0); -- Peripheral write enable (high active)
+ per_en : out std_logic; -- Peripheral enable (high active)
+ pmem_addr : out std_logic_vector; -- Program Memory address
+ pmem_cen : out std_logic; -- Program Memory chip enable (low active)
+ pmem_din : out std_logic_vector (15 downto 0); -- Program Memory data input (optional)
+ pmem_wen : out std_logic_vector (1 downto 0); -- Program Memory write enable (low active) (optional)
+ puc : out std_logic; -- Main system reset
+ smclk_en : out std_logic; -- SMCLK enable
+
+ dbg_uart_rxd : in std_logic; -- Debug interface: UART RXD
+ dco_clk : in std_logic; -- Fast oscillator (fast clock)
+ dmem_dout : in std_logic_vector (15 downto 0); -- Data Memory data output
+ irq : in std_logic_vector (13 downto 0); -- Maskable interrupts
+ lfxt_clk : in std_logic; -- Low frequency oscillator (typ 32kHz)
+ nmi : in std_logic; -- Non-maskable interrupt (asynchronous)
+ per_dout : in std_logic_vector (15 downto 0); -- Peripheral data output
+ pmem_dout : in std_logic_vector (15 downto 0); -- Program Memory data output
+ reset_n : in std_logic -- Reset Pin (low active)
+ );
+ end component;
+
+
+ signal inner_dmem_addr : std_logic_vector (12 downto 0);
+ signal inner_dmem_cen : std_logic;
+ signal inner_dmem_din : std_logic_vector (15 downto 0);
+ signal inner_dmem_dout : std_logic_vector (15 downto 0);
+ signal inner_dmem_wen : std_logic_vector (1 downto 0);
+
+ signal ram_dmem_cen : std_logic;
+ signal mcu_dmem_dout : std_logic_vector (15 downto 0);
+
+ signal dmem_mux : std_logic;
+
+
+ signal pmem_addr : std_logic_vector (13 downto 0);
+ signal pmem_cen : std_logic;
+ signal pmem_din : std_logic_vector (15 downto 0);
+ signal pmem_dout : std_logic_vector (15 downto 0);
+ signal pmem_wen : std_logic_vector (1 downto 0);
+
+ -- Inner signals used to connect built in components
+ signal inner_mclk : std_logic;
+ signal inner_puc : std_logic;
+
+ signal inner_per_addr : std_logic_vector (7 downto 0);
+ signal inner_per_din : std_logic_vector (15 downto 0);
+ signal inner_per_dout : std_logic_vector (15 downto 0);
+ signal inner_per_wen : std_logic_vector (1 downto 0);
+ signal inner_per_en : std_logic;
+
+ signal inner_irq_acc : std_logic_vector (13 downto 0);
+ signal inner_irq : std_logic_vector (13 downto 0);
+
+ -- RS232 interface
+ signal uart_dout : std_logic_vector (15 downto 0);
+ signal uart_irq : std_logic;
+
+--------------------------------------------------------------------------------
+
+begin
+
+ -- Soft core
+ openMSP430_0 : openMSP430
+ port map (
+ aclk_en => aclk_en,
+ dbg_freeze => open,
+ dbg_uart_txd => open,
+ dmem_addr => inner_dmem_addr,
+ dmem_cen => inner_dmem_cen,
+ dmem_din => inner_dmem_din,
+ dmem_wen => inner_dmem_wen,
+ irq_acc => inner_irq_acc,
+ mclk => inner_mclk,
+ per_addr => inner_per_addr,
+ per_din => inner_per_din,
+ per_wen => inner_per_wen,
+ per_en => inner_per_en,
+ pmem_addr => pmem_addr,
+ pmem_cen => pmem_cen,
+ pmem_din => open,
+ pmem_wen => open,
+ puc => inner_puc,
+ smclk_en => smclk_en,
+
+ dbg_uart_rxd => '0',
+ dco_clk => dco_clk,
+ dmem_dout => mcu_dmem_dout,
+ irq => inner_irq,
+ lfxt_clk => lfxt_clk,
+ nmi => nmi,
+ per_dout => inner_per_dout,
+ pmem_dout => pmem_dout,
+ reset_n => reset_n);
+
+
+ -- Data memories
+ d_ram_hi : entity work.ram_generic
+ generic map (
+ BRAM_TYPE => "RAMB16_S4",
+ SIZE => 4*1024,
+ ADDR_WIDTH => 12,
+ DATA_WIDTH => 8,
+ NEG_EN => true,
+ NEG_WE => true)
+ port map (
+ clk => inner_mclk,
+ addr => inner_dmem_addr (11 downto 0),
+ en => ram_dmem_cen,
+ we => inner_dmem_wen (1),
+ din => inner_dmem_din (15 downto 8),
+ dout => inner_dmem_dout (15 downto 8));
+
+ d_ram_lo : entity work.ram_generic
+ generic map (
+ BRAM_TYPE => "RAMB16_S4",
+ SIZE => 4*1024,
+ ADDR_WIDTH => 12,
+ DATA_WIDTH => 8,
+ NEG_EN => true,
+ NEG_WE => true)
+ port map (
+ clk => inner_mclk,
+ addr => inner_dmem_addr (11 downto 0),
+ en => ram_dmem_cen,
+ we => inner_dmem_wen (0),
+ din => inner_dmem_din (7 downto 0),
+ dout => inner_dmem_dout (7 downto 0));
+
+ -- Program memories
+ p_ram_hi : entity work.ram_generic
+ generic map (
+ BRAM_TYPE => "RAMB16_S2",
+ SIZE => 16*1024,
+ ADDR_WIDTH => 14,
+ DATA_WIDTH => 8,
+ NEG_EN => true)
+ port map (
+ clk => inner_mclk,
+ addr => pmem_addr,
+ en => pmem_cen,
+ we => pmem_wen (1),
+ din => pmem_din (15 downto 8),
+ dout => pmem_dout (15 downto 8));
+
+ p_ram_lo : entity work.ram_generic
+ generic map (
+ BRAM_TYPE => "RAMB16_S2",
+ SIZE => 16*1024,
+ ADDR_WIDTH => 14,
+ NEG_EN => true)
+ port map (
+ clk => inner_mclk,
+ addr => pmem_addr,
+ en => pmem_cen,
+ we => pmem_wen (0),
+ din => pmem_din (7 downto 0),
+ dout => pmem_dout (7 downto 0));
+
+
+ -- RS232 periphery
+ uart_o : entity work.uart
+ port map (
+ mclk => inner_mclk,
+ per_addr => inner_per_addr,
+ per_din => inner_per_din,
+ per_en => inner_per_en,
+ per_wen => inner_per_wen,
+ puc => inner_puc,
+ per_irq_acc => '0',
+ per_irq => uart_irq,
+ per_dout => uart_dout,
+ rxd => rxd,
+ txd => txd);
+
+--------------------------------------------------------------------------------
+
+ process (inner_mclk) is
+ begin
+ if rising_edge(inner_mclk) then
+ dmem_mux <= inner_dmem_addr (12);
+ end if;
+ end process;
+
+
+ mcu_dmem_dout <= inner_dmem_dout when dmem_mux = '0' else
+ dmem_dout;
+
+ ram_dmem_cen <= inner_dmem_cen or inner_dmem_addr (12);
+
+ dmem_addr <= inner_dmem_addr (11 downto 0);
+ dmem_ce <= (not inner_dmem_cen) and inner_dmem_addr (12);
+ dmem_we <= '1' when inner_dmem_wen = "00" else '0';
+ dmem_din <= inner_dmem_din;
+
+
+ inner_per_dout <= uart_dout or per_dout;
+
+ inner_irq <= irq;
+ --inner_irq (6) <= uart_irq;
+
+ irq_acc <= inner_irq_acc;
+ mclk <= inner_mclk;
+ per_addr <= inner_per_addr;
+ per_din <= inner_per_din;
+ per_wen <= inner_per_wen;
+ per_en <= inner_per_en;
+ puc <= inner_puc;
+
+end rtl;
+
--- /dev/null
+//----------------------------------------------------------------------------
+// Copyright (C) 2001 Authors
+//
+// This source file may be used and distributed without restriction provided
+// that this copyright statement is not removed from the file and that any
+// derivative work contains the original copyright notice and the associated
+// disclaimer.
+//
+// This source file is free software; you can redistribute it and/or modify
+// it under the terms of the GNU Lesser General Public License as published
+// by the Free Software Foundation; either version 2.1 of the License, or
+// (at your option) any later version.
+//
+// This source is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
+// License for more details.
+//
+// You should have received a copy of the GNU Lesser General Public License
+// along with this source; if not, write to the Free Software Foundation,
+// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+//
+//----------------------------------------------------------------------------
+//
+// *File Name: openMSP430_defines.v
+//
+// *Module Description:
+// openMSP430 Configuration file
+//
+// *Author(s):
+// - Olivier Girard, olgirard@gmail.com
+//
+//----------------------------------------------------------------------------
+// $Rev: 74 $
+// $LastChangedBy: olivier.girard $
+// $LastChangedDate: 2010-08-28 21:53:08 +0200 (Sat, 28 Aug 2010) $
+//----------------------------------------------------------------------------
+`include "openMSP430_undefines.v"
+
+//----------------------------------------------------------------------------
+// SYSTEM CONFIGURATION
+//----------------------------------------------------------------------------
+//
+// Note: the sum of both program and data memories should not exceed 63.5 kB
+//
+
+// Program Memory Size:
+// Uncomment the required memory size
+//-------------------------------------------------------
+//`define PMEM_SIZE_59_KB
+//`define PMEM_SIZE_55_KB
+//`define PMEM_SIZE_54_KB
+//`define PMEM_SIZE_51_KB
+//`define PMEM_SIZE_48_KB
+//`define PMEM_SIZE_41_KB
+`define PMEM_SIZE_32_KB
+//`define PMEM_SIZE_24_KB
+//`define PMEM_SIZE_16_KB
+//`define PMEM_SIZE_12_KB
+//`define PMEM_SIZE_8_KB
+//`define PMEM_SIZE_4_KB
+//`define PMEM_SIZE_2_KB
+//`define PMEM_SIZE_1_KB
+
+// Data Memory Size:
+// Uncomment the required memory size
+//-------------------------------------------------------
+//`define DMEM_SIZE_32_KB
+//`define DMEM_SIZE_24_KB
+`define DMEM_SIZE_16_KB
+//`define DMEM_SIZE_10_KB
+//`define DMEM_SIZE_8_KB
+//`define DMEM_SIZE_5_KB
+//`define DMEM_SIZE_4_KB
+//`define DMEM_SIZE_2p5_KB
+//`define DMEM_SIZE_2_KB
+//`define DMEM_SIZE_1_KB
+//`define DMEM_SIZE_512_B
+//`define DMEM_SIZE_256_B
+//`define DMEM_SIZE_128_B
+
+
+// Include/Exclude Hardware Multiplier
+`define MULTIPLIER
+
+
+//----------------------------------------------------------------------------
+// REMOTE DEBUGGING INTERFACE CONFIGURATION
+//----------------------------------------------------------------------------
+
+// Include Debug interface
+//`define DBG_EN
+
+// Debug interface selection
+// `define DBG_UART -> Enable UART (8N1) debug interface
+// `define DBG_JTAG -> DON'T UNCOMMENT, NOT SUPPORTED
+//
+//`define DBG_UART
+//`define DBG_JTAG
+
+// Number of hardware breakpoints (each unit contains 2 hw address breakpoints)
+// `define DBG_HWBRK_0 -> Include hardware breakpoints unit 0
+// `define DBG_HWBRK_1 -> Include hardware breakpoints unit 1
+// `define DBG_HWBRK_2 -> Include hardware breakpoints unit 2
+// `define DBG_HWBRK_3 -> Include hardware breakpoints unit 3
+//
+//`define DBG_HWBRK_0
+//`define DBG_HWBRK_1
+//`define DBG_HWBRK_2
+//`define DBG_HWBRK_3
+
+
+//==========================================================================//
+//==========================================================================//
+//==========================================================================//
+//==========================================================================//
+//===== SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!! =====//
+//==========================================================================//
+//==========================================================================//
+//==========================================================================//
+//==========================================================================//
+
+//
+// PROGRAM & DATA MEMORY CONFIGURATION
+//======================================
+
+// Program Memory Size
+`ifdef PMEM_SIZE_59_KB
+ `define PMEM_AWIDTH 15
+ `define PMEM_SIZE 60416
+`endif
+`ifdef PMEM_SIZE_55_KB
+ `define PMEM_AWIDTH 15
+ `define PMEM_SIZE 56320
+`endif
+`ifdef PMEM_SIZE_54_KB
+ `define PMEM_AWIDTH 15
+ `define PMEM_SIZE 55296
+`endif
+`ifdef PMEM_SIZE_51_KB
+ `define PMEM_AWIDTH 15
+ `define PMEM_SIZE 52224
+`endif
+`ifdef PMEM_SIZE_48_KB
+ `define PMEM_AWIDTH 15
+ `define PMEM_SIZE 49152
+`endif
+`ifdef PMEM_SIZE_41_KB
+ `define PMEM_AWIDTH 15
+ `define PMEM_SIZE 41984
+`endif
+`ifdef PMEM_SIZE_32_KB
+ `define PMEM_AWIDTH 14
+ `define PMEM_SIZE 32768
+`endif
+`ifdef PMEM_SIZE_24_KB
+ `define PMEM_AWIDTH 14
+ `define PMEM_SIZE 24576
+`endif
+`ifdef PMEM_SIZE_16_KB
+ `define PMEM_AWIDTH 13
+ `define PMEM_SIZE 16384
+`endif
+`ifdef PMEM_SIZE_12_KB
+ `define PMEM_AWIDTH 13
+ `define PMEM_SIZE 12288
+`endif
+`ifdef PMEM_SIZE_8_KB
+ `define PMEM_AWIDTH 12
+ `define PMEM_SIZE 8192
+`endif
+`ifdef PMEM_SIZE_4_KB
+ `define PMEM_AWIDTH 11
+ `define PMEM_SIZE 4096
+`endif
+`ifdef PMEM_SIZE_2_KB
+ `define PMEM_AWIDTH 10
+ `define PMEM_SIZE 2048
+`endif
+`ifdef PMEM_SIZE_1_KB
+ `define PMEM_AWIDTH 9
+ `define PMEM_SIZE 1024
+`endif
+
+// Data Memory Size
+`ifdef DMEM_SIZE_32_KB
+ `define DMEM_AWIDTH 14
+ `define DMEM_SIZE 32768
+`endif
+`ifdef DMEM_SIZE_24_KB
+ `define DMEM_AWIDTH 14
+ `define DMEM_SIZE 24576
+`endif
+`ifdef DMEM_SIZE_16_KB
+ `define DMEM_AWIDTH 13
+ `define DMEM_SIZE 16384
+`endif
+`ifdef DMEM_SIZE_10_KB
+ `define DMEM_AWIDTH 13
+ `define DMEM_SIZE 10240
+`endif
+`ifdef DMEM_SIZE_8_KB
+ `define DMEM_AWIDTH 12
+ `define DMEM_SIZE 8192
+`endif
+`ifdef DMEM_SIZE_5_KB
+ `define DMEM_AWIDTH 12
+ `define DMEM_SIZE 5120
+`endif
+`ifdef DMEM_SIZE_4_KB
+ `define DMEM_AWIDTH 11
+ `define DMEM_SIZE 4096
+`endif
+`ifdef DMEM_SIZE_2p5_KB
+ `define DMEM_AWIDTH 11
+ `define DMEM_SIZE 2560
+`endif
+`ifdef DMEM_SIZE_2_KB
+ `define DMEM_AWIDTH 10
+ `define DMEM_SIZE 2048
+`endif
+`ifdef DMEM_SIZE_1_KB
+ `define DMEM_AWIDTH 9
+ `define DMEM_SIZE 1024
+`endif
+`ifdef DMEM_SIZE_512_B
+ `define DMEM_AWIDTH 8
+ `define DMEM_SIZE 512
+`endif
+`ifdef DMEM_SIZE_256_B
+ `define DMEM_AWIDTH 7
+ `define DMEM_SIZE 256
+`endif
+`ifdef DMEM_SIZE_128_B
+ `define DMEM_AWIDTH 6
+ `define DMEM_SIZE 128
+`endif
+
+// Data Memory Base Adresses
+`define DMEM_BASE 16'h0200
+
+// Program & Data Memory most significant address bit (for 16 bit words)
+`define PMEM_MSB `PMEM_AWIDTH-1
+`define DMEM_MSB `DMEM_AWIDTH-1
+
+//
+// STATES, REGISTER FIELDS, ...
+//======================================
+
+// Instructions type
+`define INST_SO 0
+`define INST_JMP 1
+`define INST_TO 2
+
+// Single-operand arithmetic
+`define RRC 0
+`define SWPB 1
+`define RRA 2
+`define SXT 3
+`define PUSH 4
+`define CALL 5
+`define RETI 6
+`define IRQ 7
+
+// Conditional jump
+`define JNE 0
+`define JEQ 1
+`define JNC 2
+`define JC 3
+`define JN 4
+`define JGE 5
+`define JL 6
+`define JMP 7
+
+// Two-operand arithmetic
+`define MOV 0
+`define ADD 1
+`define ADDC 2
+`define SUBC 3
+`define SUB 4
+`define CMP 5
+`define DADD 6
+`define BIT 7
+`define BIC 8
+`define BIS 9
+`define XOR 10
+`define AND 11
+
+// Addressing modes
+`define DIR 0
+`define IDX 1
+`define INDIR 2
+`define INDIR_I 3
+`define SYMB 4
+`define IMM 5
+`define ABS 6
+`define CONST 7
+
+// Execution state machine
+`define E_IRQ_0 4'h0
+`define E_IRQ_1 4'h1
+`define E_IRQ_2 4'h2
+`define E_IRQ_3 4'h3
+`define E_IRQ_4 4'h4
+`define E_SRC_AD 4'h5
+`define E_SRC_RD 4'h6
+`define E_SRC_WR 4'h7
+`define E_DST_AD 4'h8
+`define E_DST_RD 4'h9
+`define E_DST_WR 4'hA
+`define E_EXEC 4'hB
+`define E_JUMP 4'hC
+`define E_IDLE 4'hD
+
+// ALU control signals
+`define ALU_SRC_INV 0
+`define ALU_INC 1
+`define ALU_INC_C 2
+`define ALU_ADD 3
+`define ALU_AND 4
+`define ALU_OR 5
+`define ALU_XOR 6
+`define ALU_DADD 7
+`define ALU_STAT_7 8
+`define ALU_STAT_F 9
+`define ALU_SHIFT 10
+`define EXEC_NO_WR 11
+
+// Debug interface
+`define DBG_UART_WR 18
+`define DBG_UART_BW 17
+`define DBG_UART_ADDR 16:11
+
+// Debug interface CPU_CTL register
+`define HALT 0
+`define RUN 1
+`define ISTEP 2
+`define SW_BRK_EN 3
+`define FRZ_BRK_EN 4
+`define RST_BRK_EN 5
+`define CPU_RST 6
+
+// Debug interface CPU_STAT register
+`define HALT_RUN 0
+`define PUC_PND 1
+`define SWBRK_PND 3
+`define HWBRK0_PND 4
+`define HWBRK1_PND 5
+
+// Debug interface BRKx_CTL register
+`define BRK_MODE_RD 0
+`define BRK_MODE_WR 1
+`define BRK_MODE 1:0
+`define BRK_EN 2
+`define BRK_I_EN 3
+`define BRK_RANGE 4
+
+// Basic clock module: BCSCTL1 Control Register
+`define DIVAx 5:4
+
+// Basic clock module: BCSCTL2 Control Register
+`define SELS 3
+`define DIVSx 2:1
+
+// Timer A: TACTL Control Register
+`define TASSELx 9:8
+`define TAIDx 7:6
+`define TAMCx 5:4
+`define TACLR 2
+`define TAIE 1
+`define TAIFG 0
+
+// Timer A: TACCTLx Capture/Compare Control Register
+`define TACMx 15:14
+`define TACCISx 13:12
+`define TASCS 11
+`define TASCCI 10
+`define TACAP 8
+`define TAOUTMODx 7:5
+`define TACCIE 4
+`define TACCI 3
+`define TAOUT 2
+`define TACOV 1
+`define TACCIFG 0
+
+
+//
+// DEBUG INTERFACE EXTRA CONFIGURATION
+//======================================
+
+// Debug interface: Software breakpoint opcode
+`define DBG_SWBRK_OP 16'h4343
+
+// Debug UART interface auto data synchronization
+// If the following define is commented out, then
+// the DBG_UART_BAUD and DBG_DCO_FREQ need to be properly
+// defined.
+`define DBG_UART_AUTO_SYNC
+
+// Debug UART interface data rate
+// In order to properly setup the UART debug interface, you
+// need to specify the DCO_CLK frequency (DBG_DCO_FREQ) and
+// the chosen BAUD rate from the UART interface.
+//
+//`define DBG_UART_BAUD 9600
+//`define DBG_UART_BAUD 19200
+//`define DBG_UART_BAUD 38400
+//`define DBG_UART_BAUD 57600
+//`define DBG_UART_BAUD 115200
+//`define DBG_UART_BAUD 230400
+//`define DBG_UART_BAUD 460800
+//`define DBG_UART_BAUD 576000
+//`define DBG_UART_BAUD 921600
+`define DBG_UART_BAUD 2000000
+`define DBG_DCO_FREQ 20000000
+`define DBG_UART_CNT ((`DBG_DCO_FREQ/`DBG_UART_BAUD)-1)
+
+// Enable/Disable the hardware breakpoint RANGE mode
+`define HWBRK_RANGE 1'b0
+
+// Counter width for the debug interface UART
+`define DBG_UART_XFER_CNT_W 16
+
+// Check configuration
+`ifdef DBG_EN
+ `ifdef DBG_UART
+ `ifdef DBG_JTAG
+CONFIGURATION ERROR: JTAG AND UART DEBUG INTERFACE ARE BOTH ENABLED
+ `endif
+ `else
+ `ifdef DBG_JTAG
+CONFIGURATION ERROR: JTAG INTERFACE NOT SUPPORTED
+ `else
+CONFIGURATION ERROR: JTAG OR UART DEBUG INTERFACE SHOULD BE ENABLED
+ `endif
+ `endif
+`endif
+
+//
+// MULTIPLIER CONFIGURATION
+//======================================
+
+// If uncommented, the following define selects
+// the 16x16 multiplier (1 cycle) instead of the
+// default 16x8 multplier (2 cycles)
+//`define MPY_16x16
+
projects / fpga / openmsp430.git / commitdiff