]> rtime.felk.cvut.cz Git - fpga/openmsp430.git/commit
Submodule uart master
authorVladimir Burian <buriavl2@fel.cvut.cz>
Wed, 18 May 2011 19:45:12 +0000 (21:45 +0200)
committerVladimir Burian <buriavl2@fel.cvut.cz>
Wed, 18 May 2011 20:22:24 +0000 (22:22 +0200)
commitdaf3cea7416f78326bf617f598b676bd475bf268
tree7ac09e3af52bdf690cf3934f261386dcdd81ab5e
parentac1e809c7d20e745adf13f7d707db6bcf2de606f
Submodule uart

  > Resets changed from asynchronous to synchronous.
  > Early initialization of all relevant signals.
uart