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rtime.felk.cvut.cz Git - fpga/uart.git/log
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Vladimir Burian [Fri, 28 Jan 2011 16:13:40 +0000 (17:13 +0100)]
First prototype of receiver shift register.
Vladimir Burian [Thu, 27 Jan 2011 19:56:22 +0000 (20:56 +0100)]
Some comments added.
Vladimir Burian [Sat, 22 Jan 2011 22:41:13 +0000 (23:41 +0100)]
Clear of FIFO overflow flag capability added.
Vladimir Burian [Sat, 22 Jan 2011 22:05:16 +0000 (23:05 +0100)]
Baud_gen scale input width redefined as generic. Default value is 16.
Vladimir Burian [Sat, 22 Jan 2011 21:53:46 +0000 (22:53 +0100)]
First working prototype of HW UART - TX part.
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