rtime.felk.cvut.cz Git - fpga/uart.git/history

]> rtime.felk.cvut.cz Git - fpga/uart.git/history - uart.vhd

2011-05-18	Vladimir Burian	Resets changed from asynchronous to synchronous. master	blob \| commitdiff \| raw
2011-05-18	Vladimir Burian	Early initialization of all relevant signals.	blob \| commitdiff \| raw \| diff to current
2011-02-04	Vladimir Burian	Receiving capability added to the top component.	blob \| commitdiff \| raw \| diff to current
2011-02-04	Vladimir Burian	Baud generator ClockEnable added.	blob \| commitdiff \| raw \| diff to current
2011-01-22	Vladimir Burian	Clear of FIFO overflow flag capability added.	blob \| commitdiff \| raw \| diff to current
2011-01-22	Vladimir Burian	First working prototype of HW UART - TX part.	blob \| commitdiff \| raw \| diff to current

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