rtime.felk.cvut.cz Git - fpga/openmsp430.git/search

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2011-04-14	Vladimir Burian	New top module with external data bus	commit \| commitdiff \| tree
2011-03-10	Vladimir Burian	Added ready to use openMSP430 entity.	commit \| commitdiff \| tree
2011-03-10	Vladimir Burian	Added uart submodule.	commit \| commitdiff \| tree
2011-03-10	Vladimir Burian	Add custom generics RAM.	commit \| commitdiff \| tree
2011-03-10	Vladimir Burian	Added samples of Coregen memories.	commit \| commitdiff \| tree
2011-03-10	Vladimir Burian	Renamed file with openMSP430 defines.	commit \| commitdiff \| tree
2011-02-27	Vladimir Burian	OpenMSP430 core verilog source files moved to "core...	commit \| commitdiff \| tree
2011-01-08	Vladimir Burian	Added partial copy of openMSP430.	commit \| commitdiff \| tree

Local version/partial copy of OpenCores's openMSP430 project (http://opencores.org/project,openmsp430)