mtd: spi-nor: Update erasesize if dual parallel configuration
For UBIFS we are using 64KB erase size that becomes 128KB for
dual parallel configuration. With the introduction of SFDP
the erase size is not updating as expected for dual parallel
configuration. This patch updates the erase size in dual
parallel configuration.
Signed-off-by: Tejas Prajapati Rameshchandra <tejas.prajapati.rameshchandra@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
David Cater [Tue, 15 May 2018 21:37:52 +0000 (17:37 -0400)]
clk: Add ccf driver for IDT 8T49N24x UFT
This is a common clock framework driver that supports the 8T49N241 chip.
No other chips in the family are currently supported. The driver
supports setting the rate for all four outputs on the chip and
automatically calculating/setting the appropriate VCO value.
The driver can read a full register map from the device tree,
and will use that register map to initialize the attached part (via I2C)
when the system boots. Any configuration not supported by the common
clock framework must be done via the full register map, including
optimized settings.
All outputs are currently assumed to be LVDS, unless overridden in the
full register map in the DT.
Signed-off-by: David Cater <david.cater@idt.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
David Cater [Tue, 15 May 2018 21:36:52 +0000 (17:36 -0400)]
dt-bindings: Add binding for IDT 8T49N24x UFT
IDT8T49N241 has 4 outputs; 1 integral divider and 3 fractional dividers.
The 8T49N241 accepts up to two differential or single-ended input clocks
and a fundamental-mode crystal input. The internal PLL can lock to either
of the input reference clocks or just to the crystal to behave as a
frequency synthesizer.
Signed-off-by: David Cater <david.cater@idt.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michael Gill [Tue, 15 May 2018 20:13:56 +0000 (13:13 -0700)]
staging: apf: Correct sg list length assignment in apf dma
When using DMABUFs in the apf dma driver, there were specific
lengths that resulted in the transfer length being incorrectly
assigned. This patch corrects that by assigning lengths correctly
when the sg descriptor length is smaller than the transfer size.
Signed-off-by: Michael Gill <michael.gill@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
spi: spi-zynqmp-gqspi: use dma mode only if the buffer is not vmalloced
As per the kernel documentation the buffer to be used with dma
should not be vmalloced due to the fact that if buffer is vmalloced
then page entries are not consistent in physical pages. That would
lead to failure cases in dma. This patch adds condition to check
if the buffer to be read is vmalloced or not if not vmalloced then
uses dma mode otherwise io mode.
Signed-off-by: Tejas Prajapati Rameshchandra <tejas.prajapati.rameshchandra@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Derek Kiernan [Tue, 15 May 2018 00:17:01 +0000 (01:17 +0100)]
misc: xilinx-sdfec: Correct write to AXIS_WIDTH reg
The function xsdfec_cfg_axi_streams incorrectly calls
xsdfec_translate_axis_words_cfg_val when calculating the value for
din_width_field. This can result in a incorrect write to AXIS_WIDTH
register.
Signed-off-by: Derek Kiernan <derek.kiernan@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Derek Kiernan [Tue, 15 May 2018 00:17:00 +0000 (01:17 +0100)]
misc: xilinx-sdfec: Remove RESET_REQ IOCTL
No longer needed the functionality is implemented in SET_DEFAULT_CONFIG and
CLEAR_STATS ioctl as reset occurs external to the driver. No reset function
implemented.
Signed-off-by: Derek Kiernan <derek.kiernan@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Derek Kiernan [Tue, 15 May 2018 00:16:55 +0000 (01:16 +0100)]
misc: xilinx-sdfec: Remove tracking of table entries
For the SC, LA and QC Tables software tracked the offset of last written
entry to ensure no overwriting, using sc_off, qc_off and la_off from struct
xsdfec_dev. This assumes contiguous writing and no updating of the tables,
which restricts the use cases of the SD-FEC, e.g. updating existing entries
for a code.
Signed-off-by: Derek Kiernan <derek.kiernan@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
To align with the device tree entry updates for sd-fec-1.1 the following
changes have been implemented.
- Changed the xsdfec_of_match compatible string.
- Updates the driver to read, store and configure the AXI Stream
interfaces.
- Removes reading op-mode DT property.
- remove unused op-mode member from xsdfec_config.
- reads of the following Device Tree properties and sets the AXIS_WIDTH
register.
- din-words.
- din-width.
- dout-words.
- dout-width.
Signed-off-by: Derek Kiernan <derek.kiernan@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Derek Kiernan [Fri, 11 May 2018 09:38:00 +0000 (10:38 +0100)]
misc: xilinx-sdfec: Add new version DT binding file
Introduces a new DT binding file as compatibility is broken with previous
version by introducing the following changes to the DT properties.
- Updates the compatible string to sd-fec-1.1.
- Removes the op-mode property.
- Adds mandatory AXI Stream propterties.
- din-words.
- din-width.
- dout-words.
- dout-width.
Also specifies interrupt as an optional property.
Signed-off-by: Derek Kiernan <derek.kiernan@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Derek Kiernan [Fri, 11 May 2018 09:37:59 +0000 (10:37 +0100)]
misc: xilinx-sdfec: Use xsdfec_config in xsdfec
Avoids copying the variables in function xsdfec_get_config, e.g. for ioctl
XSDFEC_GET_CONFIG.
Also removed state from xsdfec_config as this aligns better with GET_STATUS
ioctl rather than GET_CONFIG.
Signed-off-by: Derek Kiernan <derek.kiernan@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The XDMA IP now support MSI decode mode along with existing
MSI FIFO mode.
In both FIFO and DECODE mode 64 MSI's are supported.
The new DECODE mode uses three GIC IRQ lines, one for legacy
and error, two for lower and upper 32 MSI.
Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
PCI: XDMA PL PCIe: Add documentation for MSI DECODE mode.
The XDMA IP now support MSI decode mode along with existing
MSI FIFO mode.
The new DECODE mode uses three GIC IRQ lines, one for legacy
and error, two for lower and upper 32 MSI.
Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Devices requesting multiple MSI, message data being programmed
is modified by device.
Avoid modified message data falling into another device data
range.
Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Vishal Sagar [Wed, 2 May 2018 12:38:44 +0000 (18:08 +0530)]
v4l: xilinx: dma: Terminate DMA when media pipeline fails to start
If an incorrectly configured media pipeline is started, the allocated
dma descriptors aren't freed. This leads to kernel oops when pipeline
is configured correctly and run subsequently. This patch fixes this
issue by freeing the descriptors on media pipeline start failure.
dmaengine: xilinx: dma: In axidma add support for 64MB data transfer
In 2018.1 axidma IP support for 64 MB data transfer is added by increasing
buffer length width to 26bit. Modify DT "xlnx,sg-length-width" validation
accordingly. Since max length for previous IP version is 23 bit display a
warning message if length is in 23-26 bit range. It would have an ideal
solution to add a separate compatibility string and config structure for
this changed IP but due to lack of proper DMA IP versioning it's dropped.
Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
dma: xilinx: Add fid property for interlaced support in framebuffer
Add support for new property xlnx,fid which is present when IP
configured to support interlaced video. The Field ID bit access is gated
based on the presence of this property. This is an optional property.
dt-bindings: dma: Add fid property for interlaced video
Add a new property which should be present if framebuffer is used to
handle interlaced video. Access to Field ID bit in IP is gated based on
this property.
On framebuffer halt, set the flush bit of control register and wait for
the flush status bit to be set which indicates the framebuffer FIFO is
flushed. It waits for a maximum of 50 ms time for flush to happen.
This is done after framebuffer is stopped and all pending transactions
are done i.e. idle state is reached.
drm: xlnx: zynqmp: Update planes asynchronously in the legacy entry
With the atomic modesetting, the legacy APIs create a commit for single
change. This serializes each changes with vsync interval as each commit
is synchronous to vsync. So, if application is changing both crtc and
plane within single vsync interval, only one will be taken in a single
interval, and it gives half of the framerate.
This patch makes the plane update asynchronous to vsync, meaning the plane
update from the legacy set plane API happens immediately when there's
no atomic commit queued for the given plane. The implementation is based
on drm_atomic_helper_update_plane() but enables the async update.
spi: zynqmp: Fix for qspi dma when accessing address space beyond 32-bit
dma_set_mask should be called before registering to spi_master.
In the current flow dma_set_mask is set to 44 bit but after
registering to spi_master. because of this, qspi dma is not able
to access beyond 32-bit address space. during spi_register_master,
core will do some dma transfers, hence not able to access beyond
32-bit address space.
Signed-off-by: Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
usb: dwc3: gadget: ISOC transfers should be stopped before starting a transfer
For ISOC transfers the requests are not queued until the HOST requests
for data and XferNotReady event is generated .But XferNotReady event
is not getting generated for ISOC transfers for the second time after
Endpoint configuration. Since ISOC packets depend on the XferNotReady
events, they will not be queued to controller. Because of this issue
timeout happens on the application layer.
This patch fixes this issue by issuing END TRANSFER command before
starting any ISOC transfers. Doing so will make the controller clear
the previous allocated endpoint resources and reallocate resources
when the transfer is requested. Because of this change XferNotReady
events will be generated when host requests for the ISOC transfer.
Signed-off-by: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Dhaval Shah [Thu, 26 Apr 2018 07:00:31 +0000 (00:00 -0700)]
soc: xilinx: vcu: Optimize the VCU PLL calculation.
Calculate the maximum and minimum possible FBDIV
values so that number of iteration can be reduce to
calculate FBDIV and divisor for the provided clock
information.
Signed-off-by: Dhaval Shah <dhaval.shah@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch adds interlaced support to the Xilinx V4L dma client. In case
of capture pipeline, the field id is read from the callback.
A check is present to find and correct sequence number in case
a frame is dropped i.e. fid is repeated. For this the prev_fid member is
used to store the previous fid value to be compared with one returned.
In case of output pipeline, the field id is set per dma descriptor.
A dma descriptor pointer is added to xvip_dma_buffer so that it may be
passed as a reference while getting the fid.
The video node gets the field type of the subdev prior and checks if it
is of V4L2_FIELD_ALTERNATE type. If yes then height is halved.
Some other minor fixes for checkpatch are also applied here.
Use the IOCTL Macros provided by Linux Kernel when handling IOCTL requests.
Plus for all parameter passing for IOCTL commands use pointers to be
consistent.
Signed-off-by: Derek Kiernan <derek.kiernan@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
misc: xilinx-sdfec: Use "code_id" to dev_err calls
code_id is a multiplier used when calculating the reg_addr in existing
dev_err calls in the following functions:
- xsdfec_collect_ldpc_reg0
- xsdfec_collect_ldpc_reg1
- xsdfec_collect_ldpc_reg2
- xsdfec_collect_ldpc_reg3
Signed-off-by: Derek Kiernan <derek.kiernan@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Dhaval Shah [Wed, 25 Apr 2018 07:46:07 +0000 (00:46 -0700)]
soc: xilinx: vcu: Divisor calculation for MCU clock is updated.
Divisor of the mcu clock is calculated in such a way that
mcu clock derived from the calculation is greater than
or equal to provided values from the logicoreIP.
Signed-off-by: Dhaval Shah <dhaval.shah@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
dma: xilinx: Get DMA alignment from device tree for Framebuffer
Patch adds xlnx,pixels-per-clock(ppc) and xlnx,dma-align device tree
property decoding to calculate the required DMA alignment.
xlnx,pixels-per-clock is mandatory property now.
Minimum alignment required is 8 * pixels per clock in bytes.
dma-align property is optional.
In case present, dma-align must be a power of 2 and be >= 8 * ppc.
If absent, alignment is set as ppc * 8.
Added a new compatible string and structure which contains dma direction
and flag. The flag would be a bitmask of properties.
When ever a new IP or device tree property is to be supported, a bitmask
for the same is to be created and added to this flag.
For the new v2.1 compatible string, a new XILINX_PPC_PROP bitmask is
set in the flags. If the flag is set then, pixels-per-clock property
would be checked.
Documentation: devicetree: bindings: dma: Add properties for DMA alignment
Adds the pixels per clock and dma-align device tree properties. These
are used to determine the DMA memory alignment.
New compatible strings xlnx,axi-frmbuf-rd-v2.1 and
xlnx,axi-frmbuf-wr-v2.1 have also been added for this.
This patch removes quirk which indicates a broken base clock. This was
making the kernel report wrong base clock of ~187MHz instead of 200MHz
even as the measurement on the hardware was showing 200MHz.
Signed-off-by: Manish Narani <manish.narani@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Rajan Vaja [Thu, 19 Apr 2018 18:13:11 +0000 (11:13 -0700)]
firmware: zynqmp: Add sysfs and IOCTL to set boot health status
Add sysfs interface to set boot health status from userspace.
Add IOCTL ID used by this interface to communicate with firmware.
If PMUFW is compiled with CHECK_HEALTHY_BOOT, it will check the
healthy bit on FPD WDT expiration. If healthy bit is set by a user
application running in Linux, PMUFW will do APU only restart. If
healthy bit is not set during FPD WDT expiration, PMUFW will do
system restart.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
By default, the device names derive from the dt description. The DP
pcm devices are represented as a child node of DP node, which results
in both parent and child node names in the device name. The name
created in this way gets too long to fit into the sound component name,
and last characters where IDs are located are not included. This gives
the same component name for two different components, and the debugfs
fails to create entries with same name as warning below:
xilinx-dp-snd-pcm fd4a0000.zynqmp-display:zynqmp_dp_snd_pcm1: ASoC: Failed to create component debugfs directory
This fixes it by setting the child node name as a device name.
drm: xlnx: fb: Prefer the current format depth over depth from fb helper
The drm fb helper has specific preference of bpp and depth. For example,
for 32bit bpp, the depth is hard-coded to be 24. If it's not aligned
with the supported format of a drm device, it fails to initialize fbdev.
So override the depth value from fb helper with the current format
of the drm device. This will allow to initialize the fbdev with
preferred format that matches with actual format.
Currently the driver depends on the bootloader to enable the clocks.
Add support for clocking. The patch enables the clock at probe and
disables them at remove.
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Glenn Langedock [Tue, 27 Mar 2018 14:09:25 +0000 (16:09 +0200)]
gpio: zynq: protect direction in/out with a spinlock
Fix race condition when changing the direction (in/out) of the GPIO pin.
The read-modify-write sequence (as coded in the driver) isn't atomic and
requires synchronization (spinlock).
Signed-off-by: Glenn Langedock <Glenn.Langedock@barco.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Tue, 27 Mar 2018 12:31:42 +0000 (14:31 +0200)]
arm: zynq: Remove 0x prefixes from cc108
The patch fixing issues reported by DTC:
arch/arm/boot/dts/zynq-cc108.dtb: Warning (unit_address_format): Node
/amba/spi@e000d000/flash@0/partition@0x400000 unit name should not have
leading "0x"
arch/arm/boot/dts/zynq-cc108.dtb: Warning (unit_address_format): Node
/amba/spi@e000d000/flash@0/partition@0x800000 unit name should not have
leading "0x"
arch/arm/boot/dts/zynq-cc108.dtb: Warning (unit_address_format): Node
/amba/spi@e000d000/flash@0/partition@0xc00000 unit name should not have
leading "0x"
arch/arm/boot/dts/zynq-cc108.dtb: Warning (unit_address_format): Node
/amba/spi@e000d000/flash@0/partition@0xd00000 unit name should not have
leading "0x"
arch/arm/boot/dts/zynq-cc108.dtb: Warning (unit_address_format): Node
/amba/spi@e000d000/flash@0/partition@0xf00000 unit name should not have
leading "0x"
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
ARM: dts: zynq: Add generic compatible string for I2C EEPROM
The at24 driver allows to register I2C EEPROM chips using different vendor
and devices, but the I2C subsystem does not take the vendor into account
when matching using the I2C table since it only has device entries.
But when matching using an OF table, both the vendor and device has to be
taken into account so the driver defines only a set of compatible strings
using the "atmel" vendor as a generic fallback for compatible I2C devices.
So add this generic fallback to the device node compatible string to make
the device to match the driver using the OF device ID table.
Signed-off-by: Javier Martinez Canillas <javier@dowhile0.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 17 Jan 2018 14:21:38 +0000 (15:21 +0100)]
arm: zynq: Add missing address node name in microzed board
This patch is fixing issue reported by dtc:
arch/arm/boot/dts/zynq-microzed.dtb: Warning (unit_address_vs_reg): Node
/memory has a reg or ranges property, but no unit name
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
fpga: region: Add reset support to the fpga region
Many of the fpga regions have a reset that has to be
asserted after the bit file programming. Add support
for the same in case there is no reset phandle passed
no action is taken so it is backward compatible.
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
drm: xlnx: zynqmp: Disable a plane when the fb format changes
The drm core doesn't explicitly disable a plane when format changes.
So add a check in the plane update functions if the new framebuffer
format has changed, and disable the plane for the format change.
Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Tested-by: Kuldeep Dave <kuldeepd@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
projects / zynq / linux.git / log