]> rtime.felk.cvut.cz Git - zynq/linux.git/commitdiff
arm64: zynqmp: Add support for zc1275 revB
authorMichal Simek <michal.simek@xilinx.com>
Wed, 11 Apr 2018 10:35:35 +0000 (12:35 +0200)
committerMichal Simek <michal.simek@xilinx.com>
Wed, 11 Apr 2018 13:17:44 +0000 (15:17 +0200)
This patch enables support zc1275 revB board. It has
SD added compared to revA. The same configuration will
work for RevC boards aswell.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
arch/arm64/boot/dts/xilinx/Makefile
arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revB.dts [new file with mode: 0644]

index a74b64e310cbfdce091cce4b2e25672b7dba2338..c75ae55901ef99ece6b164e99b046980b65d5cd1 100644 (file)
@@ -1,6 +1,7 @@
 dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1232-revA.dtb
 dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1254-revA.dtb
 dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1275-revA.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1275-revB.dtb
 dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm015-dc1.dtb
 dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm016-dc2.dtb
 dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm017-dc3.dtb
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revB.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revB.dts
new file mode 100644 (file)
index 0000000..f694fae
--- /dev/null
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP ZC1275 RevB
+ *
+ * (C) Copyright 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+
+/ {
+       model = "ZynqMP ZC1275 RevB";
+       compatible = "xlnx,zynqmp-zc1275-revB", "xlnx,zynqmp-zc1275", "xlnx,zynqmp";
+
+       aliases {
+               serial0 = &uart0;
+               serial1 = &dcc;
+               spi0 = &qspi;
+               mmc0 = &sdhci1;
+       };
+
+       chosen {
+               bootargs = "earlycon";
+               stdout-path = "serial0:115200n8";
+       };
+
+       memory@0 {
+               device_type = "memory";
+               reg = <0x0 0x0 0x0 0x80000000>;
+       };
+};
+
+&dcc {
+       status = "okay";
+};
+
+&qspi {
+       status = "okay";
+       flash@0 {
+               compatible = "m25p80"; /* 32MB */
+               #address-cells = <1>;
+               #size-cells = <1>;
+               reg = <0x0>;
+               spi-tx-bus-width = <1>;
+               spi-rx-bus-width = <4>;
+               spi-max-frequency = <108000000>; /* Based on DC1 spec */
+               partition@qspi-fsbl-uboot { /* for testing purpose */
+                       label = "qspi-fsbl-uboot";
+                       reg = <0x0 0x100000>;
+               };
+               partition@qspi-linux { /* for testing purpose */
+                       label = "qspi-linux";
+                       reg = <0x100000 0x500000>;
+               };
+               partition@qspi-device-tree { /* for testing purpose */
+                       label = "qspi-device-tree";
+                       reg = <0x600000 0x20000>;
+               };
+               partition@qspi-rootfs { /* for testing purpose */
+                       label = "qspi-rootfs";
+                       reg = <0x620000 0x5E0000>;
+               };
+       };
+};
+
+&uart0 {
+       status = "okay";
+};
+
+&sdhci1 {
+       status = "okay";
+       no-1-8-v;
+       xlnx,mio_bank = <1>;
+};