dmaengine: xilinx: dma: In axidma add support for 64MB data transfer

dmaengine: xilinx: dma: In axidma add support for 64MB data transfer

In 2018.1 axidma IP support for 64 MB data transfer is added by increasing
buffer length width to 26bit. Modify DT "xlnx,sg-length-width" validation
accordingly. Since max length for previous IP version is 23 bit display a
warning message if length is in 23-26 bit range. It would have an ideal
solution to add a separate compatibility string and config structure for
this changed IP but due to lack of proper DMA IP versioning it's dropped.

Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>