]> rtime.felk.cvut.cz Git - zynq/linux.git/commitdiff
tty: uartlite: Update the clock name
authorShubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Fri, 20 Apr 2018 11:23:48 +0000 (16:53 +0530)
committerMichal Simek <michal.simek@xilinx.com>
Wed, 2 May 2018 06:29:56 +0000 (08:29 +0200)
Update the clock name to match the IP documentation.
Also document the same in bindings.

Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Documentation/devicetree/bindings/serial/uartlite.c
drivers/tty/serial/uartlite.c

index df8aba0773a2e5a42dc44d252bfd1d4d8801da27..7ae900880d307172b40cd8c5a728b3eb8ae61a36 100644 (file)
@@ -13,6 +13,8 @@ Required properties:
 
 Optional properties:
 - port-number          : Set Uart port number
+- clock-names          : Should be "s_axi_aclk"
+- clocks               : Input clock specifier. Refer to common clock bindings.
 
 Example:
 serial@800C0000 {
index 6e002183cd01e30c0ec456e09120832d41f7803a..e0ec023717fe171b087617d4814d7ebf493a6fc7 100644 (file)
@@ -767,7 +767,7 @@ static int ulite_probe(struct platform_device *pdev)
        if (irq <= 0)
                return -ENXIO;
 
-       pdata->clk = devm_clk_get(&pdev->dev, "ulite_clk");
+       pdata->clk = devm_clk_get(&pdev->dev, "s_axi_aclk");
        if (IS_ERR(pdata->clk)) {
                if (PTR_ERR(pdata->clk) != -ENOENT)
                        return PTR_ERR(pdata->clk);