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(parent: e40a9a6) | patch
misc: xilinx-sdfec: Fix AXIS_ENABLE_MASK value
authorDerek Kiernan <derek.kiernan@xilinx.com>
Tue, 15 May 2018 00:16:54 +0000 (01:16 +0100)
committerMichal Simek <michal.simek@xilinx.com>
Tue, 15 May 2018 15:24:09 +0000 (17:24 +0200)
commit1cba0426d408eae43425d23da27607cdbabdaf60
tree6aafa83555cd5ecb498194a6b21873cc39819355tree | snapshot
parente40a9a62eb470282b064c494b487ca6a091d9f02commit | diff
misc: xilinx-sdfec: Fix AXIS_ENABLE_MASK value

The AXIS_ENABLE register has 6 bits not 5, change value of AXIS_ENABLE_MASK
from 0x1f to 0x3f.

Signed-off-by: Derek Kiernan <derek.kiernan@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
drivers/misc/xilinx_sdfec.c diff | blob | history
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