arm64: tegra21: Add USB Audio related configs

Bug 200340830

Change-Id: If2d5c493902df019a476a4b1ad2911f980a4301a
Signed-off-by: Shreshtha SAHU <ssahu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1546711
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

net: eqos: Don't restrict the size of mtu

Need to allow the changing of mtu size till
the max mtu size supported.

Bug 2016475

Change-Id: I12b885f6bfd3ec217281dc68b3f04ab2cd6ce186
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1600013
Reviewed-by: Ahung Cheng <ahcheng@nvidia.com>
Tested-by: Ahung Cheng <ahcheng@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Hayden Du <haydend@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

soc: tegra: fix out-of-bounds access of cpu_lp_max_freq

init_cpu_lp_dvfs_table was reading outside the cpu_lp_max_freq
array for speedo IDs > 5.

Bug 200346461

Change-Id: I50b323653dff69ee0403e943bbe5c032de7a63e1
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1590659
Reviewed-on: https://git-master.nvidia.com/r/1603682
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Jeffery Yu <jefferyy@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

arm64: configs: add docker related configs

Adding docker related kernel configs.
Currently dockers are not supported on ARM64 ubuntu version,
but as a requirement we are enabling the required kernel
configs to have out of the box support for the same.

Bug 2001213

Change-Id: I36e74febfb9ff12d503f5925997aa06d1b88d89c
Reviewed-on: https://git-master.nvidia.com/r/1602889
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ninad Malwade <nmalwade@nvidia.com>
Tested-by: Ninad Malwade <nmalwade@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

arm64: configs: Enable ADSP DFS for T210

Enabling ADSP DFS for t210, which allows adsp frequency to be
controlled through external drivers or through userspace from
exposed debugfs entries.

Bug 200359826
Bug 200267304

Change-Id: I5c00a284400d16b4269079c237b0b1d748058a77
Signed-off-by: Ajay Nandakumar <anandakumarm@nvidia.com>
Reviewed-on: http://git-master/r/1325974
(cherry picked from commit 238ca41ecf2a15b240abc881fa3f666f65dbacd2)
Reviewed-on: https://git-master.nvidia.com/r/1599471
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

arm64: tegra18: Disable PCIe-ASPM

Disables Active State Power Management (ASPM) for PCIe devices

bug 200364428
bug 200301602

Change-Id: I80eddf54bc7cade204e9b98cb43299a4eda00354
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1601278
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vidya Sagar <vidyas@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

arm64: tegra18: update tegra18 defconfig using make commands

Update the tegra18 defconfig using make and savedefconfig
commands.

bug 200364428

Change-Id: Ie023beda44b4f0a67f00b8e4886d6e7ed44c1e18
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1601277
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

clk: tegra: Fix build errors on T18x

The fix is to get certain drivers only be enabled for T210.

Bug 200346461

Change-Id: Ica86e89f2324562125d9414f780ade4e6b8903e8
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1597949
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Hayden Du <haydend@nvidia.com>
Tested-by: Hayden Du <haydend@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

soc: dvfs: Increase number of rail stats bins

Bug 200269751

Change-Id: I346489fcf539526cdaff493dd6eecee8bd2104f3
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/1488460
(cherry picked from commit 5fa35ba5235532b2c5cc223a1135c0b8eae038a5)
Reviewed-on: https://git-master.nvidia.com/r/1597948
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Hayden Du <haydend@nvidia.com>
Tested-by: Hayden Du <haydend@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

Merge branch 'origin/dev/bnihalani_clk_soc' into HEAD

This gets clock and DVFS commits from dev-kernel-4.4 in order to improve
stability on T210 platform.

Bug 200346461

Change-Id: I2cd1dee04c1de37b600fe748efbc374305b9de6e

media: i2c: IMX274: Enable 1080p sensor mode

Enable 1080p@60fps sensor mode

Bug 2011006

Change-Id: Ia55d56bd5f0a7f6ff25a451063e92ceae16aa45d
Signed-off-by: Josh Kuo <joshk@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1589854
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

arm64: tegra21: config: CONFIG_BCMDHD=m

Per as mmc host probe is async, but mmc_rescan of host may be
triggered by bcmdhd driver whose probe is not async. So that
regulators of host etc. may not be initialized. Make bcmdhd
WiFi driver as module.

Bug 200342180

Change-Id: If1083b2914f1bd05b8df2ccf8ba7222fc830b4ce
Reviewed-on: https://git-master.nvidia.com/r/1569025
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

ASoC: tegra-alt: Add DAPM Headphone and Mic widgets for I2S3

Tegra I2S3 interface on Jetson TX1 is not working because it is
missing the appropriate DAPM widgets to enable it. Add the
appropriate DAPM widgets for I2S3 (which is using prefix 'l' as
defined by device-tree).

Bug 2021397

Change-Id: I91e8bd13a247eaad4ce2bb1a9cd25d82b000a6c5
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1596130
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

net: wireless: bcmdhd: remove SDIO debug IOVARs causing out of bounds

"sd_devreg" IOVAR can cause out of bounds access when user input
manipulated. Proposed fix is removing debug oriented IOVARs completely.

Bug: 37622847
Bug 1990376
Signed-off-by: Insun Song <insun.song@broadcom.com>
Change-Id: I8fc5111fe9d8d2c5d7ae5b1c24ae8e531113beae
Reviewed-on: https://git-master.nvidia.com/r/1565309
(cherry picked from commit c0fac815bbc4b78915e030054a01752f133fe219)
Reviewed-on: https://git-master.nvidia.com/r/1597803
Reviewed-by: Om Prakash Singh <omp@nvidia.com>
Tested-by: Om Prakash Singh <omp@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

Revert "video: fbmem: update vscreeninfo for all ttys"

This reverts commit 1098203b0cb41ea8244a9e2051d99ffeb764229b.

Due to this change, a mode update in X causes mode update on
all TTYs. This is not expected as fbconsole needs to retain its
mode. This also caused dc timeouts upon switching between X and
fbconsole due to inconsistent mode update. Hence, reverting
this change.

bug 200225083
bug 200363727

Change-Id: Icd693ba591970af1190b7ad766623b2a6a33fac2
Signed-off-by: Naveen Kumar S <nkumars@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1597620
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

ASoC: tegra-alt: Add support for I2S5

I2S5 is not enable for Jetson-TX1 although the interface is available
on 30-pin header J26. Enable suppot for this interface so that it can
be tested.

Bug 2020869

Change-Id: I87fe177d2139fe94098cb02fadb490e2080dbb6c
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1597135
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sameer Pujar <spujar@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ravindra Lokhande <rlokhande@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

Merge "Merge branch 'origin/dev/bnihalani_pwm_thermal' into HEAD" into rel-28

clk: tegra: Fix maximum audio sync clock for Tegra210

The maximum frequency supported for I2S on Tegra210 is 24.576MHz.
However, the maximum I2S frequency is limited to 24MHz because that
is the maximum frequency of the audio sync clock. Increase the
maximum audio sync clock frequency to 24.576MHz for Tegra210 in order
to support 24.576MHz for I2S.

Update the tegra_clk_register_sync_source() function so that it does
not set the initial rate for the sync clocks and use the clock init
tables to set the initial rate instead.

Please note that this is a regression from Linux v3.10.

Bug 2020021

Change-Id: If0a7b4d4f11acd86e9a7c4b7a077985ed6aef2ce
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1594562
Reviewed-by: Peter De Schrijver <pdeschrijver@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ravindra Lokhande <rlokhande@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

watchdog: t21x: disable internal ping on wdt open

Disable internal watchdog ping when userspace opens
the watchdog dev. Watchdog ops no longer support .ref
hence its dependency is removed.

Bug 1976162

Change-Id: Ic02712bc9ac21d3df5cb9c9e0eef1522599e1590
Signed-off-by: Shreshtha SAHU <ssahu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1580583
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

video: fbmem: update vscreeninfo for all ttys

If Framebuffer Console is active, currently only the foreground TTY's
mode is updated as part of FBIOPUT_VSCREENINFO. This causes issues when
foreground TTY is updated to any other available TTYs, as DC's/FB's mode
might be different. To avoid such inconsistency in mode between ttys and
DC/FB, update mode of all TTYs in FBIO_PUTVSCREENINFO.

bug 200225083

Change-Id: Idfee47b0a20d727ebacfd9e4647a46d7aa38a000
Signed-off-by: Naveen Kumar S <nkumars@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1588190
GVS: Gerrit_Virtual_Submit
Reviewed-by: Tow Wang <toww@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

Merge branch 'origin/dev/bnihalani_pwm_thermal' into HEAD

This gets bunch of commits in drivers/pwm and drivers/thermal from
dev-kernel-4.4 in order to improve stability on T210 platform.

Bug 200346461

Change-Id: I10ffa20be2990aa0f3b21b239d880866a23f8725

thermal: tegra: Make sure DFLL cdev is updated

During suspend DFLL driver always applies cold Vmin to guarantee safe
resume. Therefore DFLL cdev must trigger update to current temperature
after resume even if no thermal threshold is crossed while the SoC was
suspended. To assure this cleared cdev update flag in early resume.

Bug 200269751

Change-Id: I6caa4e1a183073cfbd7779ac5428a761b3a064ad
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/1470836
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
(cherry picked from commit 2a7d43c9da07ca03dc96419adeb47036d63e1c93)

thermal: pwm_fan: remove unnecessary NULL check

remove unnecessary NULL check for private (platform) data.

Coverity ID 33311

Bug 200192410

Change-Id: I2d97cba9b0ee51f4981080c7a9decaf177cfb471
Signed-off-by: Navneet Kumar <navneetk@nvidia.com>
Reviewed-on: http://git-master/r/1454272
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
(cherry picked from commit eada164cbb0f51babfb78923e440a8f0dd4b47a1)

pwm: tegra: Fix DFLL PWM enable order

Enabled DFLL PWM output before PWM pin is enabled by pin controller
(this was done in opposite order that created a time window of low
PWM output, and the respective drop in PWM regulator voltage).

Change-Id: I56ab12932a904315033f2bf3317a5c10080b9b03
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/1507650
(cherry picked from commit d5888a2fb38bfa740f7eb48e72ceb3d22818bafd)
Reviewed-on: https://git-master.nvidia.com/r/1526626
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
(cherry picked from commit 4516851cc0d2a1e9e94fda3e458027f3aabc2332)

pwm: tegra-dfll:Add PWM output enable via GPIO control

In some of design, the PWM output is buffered and it is
controlled by the GPIO.
Add support to enable the PWM output via GPIO control.

bug 1943096

Change-Id: I20d9a5e5f63eb21ad559c21c42c00a53c0c216d6
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: https://git-master/r/1509908
(cherry picked from commit 323ae6644f6b49859974bb40ee966c5295b50e4a)
Reviewed-on: https://git-master.nvidia.com/r/1509952
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkata Jagadish <vjagadish@nvidia.com>
(cherry picked from commit b0731e56bb73042e5d6ad68ab5b30823f5b7adbc)

pwm: tachometer: return period & duty cycles from tachometer driver

Return period & duty cycles in nano seconds from tachometer instead of
passing calculated rotations per minute value.

Update pwm sysfs node "rpm" such that it measures the rotations
per minute using period value recevied from pwm tachometer driver.

Change-Id: I1cd2daa1911286e25cecbe50a679d34d86c6f1f1
Signed-off-by: R Raj Kumar <rrajk@nvidia.com>
Reviewed-on: http://git-master/r/1485766
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
(cherry picked from commit 03bac8937ae15a75f05aa246b6a0a800e49fc16e)

pwm: tegra: remove clock gating support in tachometer

Removed clock gating support from tegra tachometer driver
since this feature is not required here.

Change-Id: I3fb79b156eae960deedb4f9ca0254c06572c545d
Signed-off-by: R Raj Kumar <rrajk@nvidia.com>
Reviewed-on: http://git-master/r/1486805
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
(cherry picked from commit 6ffe50e52bc8d554a17958446ad1d003f83dc07a)

pwm: tegra: Fix checkpatch error

Fix the check-patch error reported by checkpatch script.

Change-Id: Ia7b05036a16dd040d012e30ed2d326f3bf0de65b
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/1484062
Reviewed-by: R Raj Kumar <rrajk@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
(cherry picked from commit e9748dd046a9e5b4abd451c04ee1143bdb8113b7)

pwm: tegra: Add support to select slower parent

If requested minimum frequency from the platform is not possible
from the higher rate parent then change the parent to slow parent
if slow-parent clock information is provided from DT.

This will help to select the lower frequency of PWM signal.

bug 1927065

Change-Id: I4eada8c51d283b308a6fe58e21596ed2f54c4c58
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/1484061
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: R Raj Kumar <rrajk@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
(cherry picked from commit aaca5fe19e655885aac71e09589b1d67189c7074)

pwm: tegra: Add support to lower pwm frequency

The PWM output signal depends on the clock source frequency
and PWM divider for period. There is possibility to have lower
PWM frequency which is not possible with higher PWM clock source
and on this case, it is required to have more fine divider of clock
source to get desired lower side frequency.

Add DT property "pwm-minimum-frequency-hz" to findout the platform
specific requirement and adjust the clock source frequency to
support this lower side frequency.

bug 1927065

Change-Id: Icb642d6886b39348b9b22310b9f0446be8087ae5
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/1483242
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: R Raj Kumar <rrajk@nvidia.com>
(cherry picked from commit 6e8b704ae3fbf7b9c0fbc291ebadd0b4e71c1c58)

pwm: tegra: remove duty cycle check for ramp time

To configure ramp time through sysfs node there is no
dependency with duty cycle and duty cycle parameter is
not required, so remove duty cycle check while
configuring ramp time through sysfs node.

Bug 1825451

Change-Id: I7b271d1affc0bf9255a62c61de222172bfe28126
Signed-off-by: Venkat Reddy Talla <vreddytalla@nvidia.com>
Reviewed-on: http://git-master/r/1467517
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
(cherry picked from commit 66354859aed76ca29249ca4cb9d91ba1deb72356)

pwm: tegra: add pwm based pmc soft led blink driver

In T210b01 LED breathing(soft led blink) functionality
added and led breathing control is through PWM signal,
add pwm based driver to configure tegar pmc led breathing
parameters.

Bug 1825451

Change-Id: Id01a96a2b277fb8545ca1ee22822c576c7a4acea
Signed-off-by: Venkat Reddy Talla <vreddytalla@nvidia.com>
Reviewed-on: http://git-master/r/1467403
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
(cherry picked from commit 0ad18f000ed0ccfa4dd0246ddc57e721cac42bc9)

pwm: tach: fix tach overflow case

Avoid overriding the tach register value in
tach overflow case.
Add module author info

Bug 200237693

Change-Id: I34f05fa788f0163f7608938e8ae39ff57531e9a5
Signed-off-by: R Raj Kumar <rrajk@nvidia.com>
Reviewed-on: http://git-master/r/1469379
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
(cherry picked from commit ba66a831f3bbad81f761eb3c9d928285f3306f12)

pwm: core: Move pwm_get_rpm() to header as static inline

Function pwm_get_rpm() is wrapper over pwm_capture() and hence
move it to header instead of implementing in the core file.

Change-Id: I6f06296bd2d1c40de66748e8a6708e0ed9d27047
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/1462979
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Reddy Talla <vreddytalla@nvidia.com>
(cherry picked from commit f358dc50c8bd57c44dbf2cdb4cf1a8c75728290a)

pwm: tegra: Add PWM based Tacho meter driver

PWM Tachometer capture the PWM signal which si in general output
of FAN, provide the period of PWM siganl which is converted to
RPM by SW.

Add Tegra Tachometer driver which implemets the pwm-capture to
measure period.

bug 200237693

Change-Id: I50fc7bdbf26bcc32868b89b17ba529fcf1b1aa53
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/1462285
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Venkat Reddy Talla <vreddytalla@nvidia.com>
GVS: Gerrit_Virtual_Submit
(cherry picked from commit c0cf2792833f594a8b0e6d54e34a93d3f67e1f2b)

pwm: core: Add support to read tachometer via pwm capture

Add support for tachometer driver via PWM core framework.
For this add PWM HW call backs for setting capture-window-length,
read RPM.

Also add sysfs for configuring window length and reading RPM
from user space.

bug 200237693

Change-Id: I1a80150c70434769f9fc23c9b0cf1fabe6729665
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/1461621
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Venkat Reddy Talla <vreddytalla@nvidia.com>
GVS: Gerrit_Virtual_Submit
(cherry picked from commit fe2668e0ef22443a611f7a26b89cf906f21a606d)

pwm: core: Add details for ramp time and double pulse period

Add details in header file for PWM ramp time and double pulse
period. Also make the dummy function implementation as static
inline.

Change-Id: I8f28a52105b2cc902380c5577b44b88dca1e55e6
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/1461620
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Reddy Talla <vreddytalla@nvidia.com>
(cherry picked from commit 38c9304feaa316167c6bfb4f3d5f3f258cc34717)

pwm: Add PWM capture support

Supply a PWM capture callback op in order to pass back information
obtained by running analysis on a PWM signal. This would normally (at
least during testing) be called from the sysfs routines with a view to
printing out PWM capture data which has been encoded into a string.

Signed-off-by: Lee Jones <lee.jones@linaro.org>
(Cherry-picked from mainline commit
3a3d1a4e32ab47323d7b8c8b7631a8d36a3098b2
and manually resolved conflict)

Change-Id: I992f74e7f8a7f67948643ce2e38919f59cbaddc5
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/1461619
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
(cherry picked from commit 679d0b29628c90b920211ae09b31e68859df4d8e)

pwm: core: add support for ramp and double pulse mode

Add support to configure the ramp up and down time of pulse
which is required for the soft pwm signal.

Also add support to set the double pulse mode and their periods.
With this, there is pair of the pulses with period of double_period.

Change-Id: I28b9a8f73bf7478efd7882ec92179d48144056bb
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/1460361
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Venkat Reddy Talla <vreddytalla@nvidia.com>
GVS: Gerrit_Virtual_Submit
(cherry picked from commit d6b9339f6abb94cca3c72e9630a07c6d679de7ae)

Bluetooth: Add Realtek USB bluetooth driver

Bug 2002562

Change-Id: I6a73cad0251e446053952f7bc1e9fc3fcf713700
Signed-off-by: Shobek Sam Attupurath <sattupurath@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1535385
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

net: wireless: rtl8822be: Update Realtek driver to v5.2.4g

Add Realtek driver that includes following fixes -

1. NPI driver changes
2. FW version 13.7 to fix TX EVM issues
3. Update BTCOEX to v48 - HID and A2DP updates
4. Coverity fixes

DRIVERVERSION v5.2.4g_NV_24270.20170928
BTCOEXVERSION COEX20170919-4848

Bug 1986015
Bug 1907004
Bug 1969977
Bug 1935772

Change-Id: I69a88b5871f71392018d0073dd727c375f6aa0a6
Signed-off-by: Shobek Sam Attupurath <sattupurath@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1571149
GVS: Gerrit_Virtual_Submit
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers: crypto: Avoid user pointer dereference

Instead of directly dereferencing pointers supplied by user,
use copy_from_user and copy_to_user API to check the validity
of user supplied buffers

Coverity ID 38812

Bug 200192571

Change-Id: Ic6a7614703b1bba78bf69e482f9a1e0f9effe9c9
Signed-off-by: Shravani Dingari <shravanid@nvidia.com>
Signed-off-by: Aniruddha TVS Rao <anrao@nvidia.com>
Reviewed-on: http://git-master/r/1454808
(cherry picked from commit 0fdddc256631e0b38ca8dcffac09dde330bf93b9)
Reviewed-on: https://git-master.nvidia.com/r/1595721
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Tested-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

video: tegra: description for fbcon mode property

Add description and an example for "nvidia,fbcon-default-mode"
DT property. This property can be used to specify mode parameters
for fbconsole in "struct tegra_dc_mode" format. If specified,
this mode will be used as the default mode for fbconsole.

bug 200308135

Change-Id: I86051607476bfc89e938369f28350428eec889cf
Signed-off-by: Naveen Kumar S <nkumars@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1588510
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Shu Zhong <shuz@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

mfd: max77620: Add configurations of backup battery

Add PMIC configurations for backup battery and low-battery
monitoring.

Bug 2020512

Change-Id: If70bfe375ec83668d30c6521148d0461fabc33c8
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1595616
GVS: Gerrit_Virtual_Submit
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

mfd: max77620: Add DT binding details for backup battery

Add DT binding details for DT properties and nodes for
backup battery and low battery monitoring configurations.

Bug 2020512

Change-Id: I374e99faae115e4f77aaea4273d6600fbb20a06c
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1595615
GVS: Gerrit_Virtual_Submit
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

tegra: camera: Update LC898212 control ID names

Update the control ID name to match the recent
sensor driver control ID changes.

Bug 200350907

Change-Id: I3af2ab683e5d4f98f6597d57b82b77a903d7cd63
Signed-off-by: Frank Chen <frankc@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1595380
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vincent Chung <vincentc@nvidia.com>
Reviewed-by: Bhanu Murthy V <bmurthyv@nvidia.com>
Reviewed-by: Josh Kergan <jkergan@nvidia.com>
Reviewed-by: Jihoon Bang <jbang@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers: crypto: Avoid resource leak

memory allocated to local variable "req" is not freed before returning
from the function for a  possible set of conditions.
Free "req" in such a case to avoid resource leak.

Coverity ID 2011369

Change-Id: I8ede395554b039587fed62738214854b129e6203
Signed-off-by: Aniruddha TVS Rao <anrao@nvidia.com>
Reviewed-on: http://git-master/r/1324017
(cherry picked from commit 2d88bf1173c14d5db710671f2a3bf7656ebcc227)
Reviewed-on: https://git-master.nvidia.com/r/1554399
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Tested-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

tegra-cryptodev: Avoid untrusted user pointer dereference

In RSA operations use copy_from_user to get key data
into local buffer before using it.

Bug 200305294

Change-Id: Ia647b81664be3de2ac1016e352a6505ff2015d49
Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Reviewed-on: http://git-master/r/1486620
(cherry picked from commit 4235ae6bd23c3547636f21b985ed006cc238775d)
Reviewed-on: https://git-master.nvidia.com/r/1594355
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers: crypto: Avoid use of tainted scalar value

Copy from user may taint the scalar value members in the respective
struct variables.
Add check for verifying the validity of the scalar value members
to avoid undefined behaviour.

Coverity ID 24040

Bug 200192571
Bug 1862381

Change-Id: I75237559409178468a6425ec3ceb4b601b21e2de
Signed-off-by: Aniruddha TVS Rao <anrao@nvidia.com>
Reviewed-on: http://git-master/r/1329922
Reviewed-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
(cherry picked from commit 3538fb80178bce43a1f3250ac3340f0bda54de63)
Reviewed-on: https://git-master.nvidia.com/r/1554425
GVS: Gerrit_Virtual_Submit
Tested-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

tegra: camera: updated control CID define

Move control CID define to tegra-v4l2-camera and switched
CID prefix from V4L2 to TEGRA_CAMERA. Updated users of camera
controls to use new defines.

Bug 200350907

Change-Id: Ifb1d4e9e3ed438bd13dd3af1d0ec16cb885f4474
Signed-off-by: David Wang <davidw@nvidia.com>
Reviewed-on: http://git-master/r/1460998
GVS: Gerrit_Virtual_Submit
Reviewed-by: Wenjia Zhou <wenjiaz@nvidia.com>
Reviewed-by: Bhanu Murthy V <bmurthyv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1590233
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

media: i2c: add delay for i2c failure on ov23850

* Add some delay before i2c write call on ov23850.

This is a workaround patch to avoid i2c failure on ov23850.

Bug 200354166

Change-Id: Id4065915c1ef932bfd9934ebbab0a1fea3404867
Signed-off-by: Gigon Bae <gbae@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1587240
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bhanu Murthy V <bmurthyv@nvidia.com>
Reviewed-by: Frank Chen <frankc@nvidia.com>
Reviewed-by: Nathan Lord <nlord@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Hayden Du <haydend@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

media: i2c: IMX274: fix dotted line corruption

found dotted line corruption in the bottom of image if we do not
set correct value of VWIDCUT.

The Veff is 2174, then VWIDCUT should be (2174-2160)/2 = 7.

Bug 200357770

Change-Id: If969c34329a51ff980030adcca9aa8b3fc945d4e
Signed-off-by: Josh Kuo <joshk@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1586800
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Esen Chen <esenc@nvidia.com>
Reviewed-by: Josh Kergan <jkergan@nvidia.com>
Reviewed-by: Nathan Lord <nlord@nvidia.com>
Reviewed-by: Shantanu Nath <snath@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

arm64: configs: add docker related configs

Adding docker related kernel configs.
Currently dockers are not supported on ARM64 ubuntu version,
but as a requirement we are enabling the required kernel
configs to have out of the box support for the same.

Bug 2001213

Change-Id: I4fbace37203ded460db03d1502ef4af9813f126e
Reviewed-on: https://git-master.nvidia.com/r/1591189
Reviewed-by: Ninad Malwade <nmalwade@nvidia.com>
Tested-by: Ninad Malwade <nmalwade@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

i2c: tegra-vi: bypass the wait for pkt transfer done

Read back the transfer status register right after
the writes to TX FIFO register to bypass the wait for
packet transfer done.

Bug 200343747

Based on commit:
3a71308 i2c: tegra-vi: bypass the wait for pkt transfer done

Change-Id: I6069a25d90ae07cee5d3849f6d84bd32dd350078
Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1589995
GVS: Gerrit_Virtual_Submit
Reviewed-by: Shan Neng Chen <snchen@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

clk: tegra: add reset ID for VI

The VI clock ID doesn't match its hw clock number because it controls both
VI and VI_SENSOR. Therefor add a special reset ID to reset the VI block.

Bug 200347391

Change-Id: I147ef4e94ee6fa392c6310471df5600c4a802f96
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1588111
(cherry picked from commit 0b5f83ee58e2a0ed4ff57bfddfa013a1a6c6b18b)
Reviewed-on: https://git-master.nvidia.com/r/1589908
Reviewed-by: Timo Alho <talho@nvidia.com>
Tested-by: Timo Alho <talho@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

platform: tegra: powergate: Fix VI reset ID on T210

VI reset id is incorrect for T210 which causes intermittent failures
when powering up VI. This change fixes the reset id.

Bug 200347391

Change-Id: I87d4258dec4bd1b231fab9be6c8890086d6df52d
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1586095
(cherry picked from commit f026ef3eb29496ab8441e9dc982c5486f297b2a2)
Reviewed-on: https://git-master.nvidia.com/r/1589836
GVS: Gerrit_Virtual_Submit
Reviewed-by: Timo Alho <talho@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

crypto: tegra-cryptodev: Move RNG support using rng framework

Move RNG1 in cryptodev using rng core framework.

Bug 200301238

Change-Id: I161c3a25fca12870136d92884e8609f903634bdf
Signed-off-by: Rakesh Babu Bodla <rbodla@nvidia.com>
Reviewed-on: http://git-master/r/1470303
(cherry picked from commit f72979765ae58890bd8ae8d2b11c7cecee02ce17)
Reviewed-on: https://git-master.nvidia.com/r/1590058
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Tested-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

crypto: tegra-se-elp: Move RNG support using rng framework

Move RNG1 implementation to generate random numbers
using rng core framework.

Bug 200301238

Change-Id: I06fc7aaaa94825c834eab4e050b62c130a331b28
Signed-off-by: Rakesh Babu Bodla <rbodla@nvidia.com>
Reviewed-on: http://git-master/r/1469509
(cherry picked from commit 14ee00064fa9145cc17dd6606a88f90225cb9a29)
Reviewed-on: https://git-master.nvidia.com/r/1590057
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Tested-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

stepper: optimize latency in starting motor

Avoid reading the motor status before sending start motor
command. This saves one read transaction while starting motor.

Bug 1623721

Change-Id: Ibee8025fafa2e19419c1f635f91d508400b829c0
Signed-off-by: Vishruth <vishruthj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1554456
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

stepper: checkpatch and review fix

Changes to fix issues reported by checkpatch.
Review defects reported after the initial patchset got merged
are also fixed.

Bug 1623721

Change-Id: I96a3ca5714b2c5d7116955f6334ea35ab9ffe4b0
Signed-off-by: Vishruth <vishruthj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1554328
Reviewed-by: Jonathan Hunter <jonathanh@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Tested-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

driver: media: i2c: imx185: Fix control steps

For controls that use 64-bit fixed point values
for min/max/default, the step setting needs to
be adjusted to match the same precision.

Bug 2016103

Change-Id: I71f152f53627ac5ba7fc43575dd6b98e58f4ff18
Signed-off-by: Frank Chen <frankc@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1589559
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Jerry Chang <jerchang@nvidia.com>
Reviewed-by: Bhanu Murthy V <bmurthyv@nvidia.com>
Reviewed-by: Jihoon Bang <jbang@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

i2c: core: check if setting clock rate is allowed

- In i2c_set_adapter_bus_clk_rate(), check if clock rate changing is
allowed.
- Use function i2c_set_adapter_bus_clk_rate to set the baud rate from
sysfs entry

Bug 1887805

Change-Id: I52be840090526c824e7f0e19f5acb5ab4c46a73d
Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com>
Reviewed-on: http://git-master/r/1462344
(cherry picked from commit ce43d0c575797d1096f6ccf6229c46ac0c72a36c)
Reviewed-on: https://git-master.nvidia.com/r/1589798
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

i2c: tegra: add support to restrict changing clk rate

Add support to avoid changing clock rate in runtime as
changing clock in runtime could result in deadlock in
clock driver.

Bug 1887805

Change-Id: I7aef00f78fbafb7658a8ad5e5a8a1a8a4dce4857
Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com>
Reviewed-on: http://git-master/r/1462345
(cherry picked from commit e34aa67272ab8a2e6b0cf774f18400515f850953)
Reviewed-on: https://git-master.nvidia.com/r/1589797
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

i2c: tegra: set the clock rate only during probe

- Set the clock rate only during initialization
and during runtime change in bus frequency.
- Remove redundant clock rate setting in probe.

Bug 1887805

Change-Id: I76680dc3ed8416bd80670eacc9795e77ffd421d5
Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com>
Reviewed-on: http://git-master/r/1331424
(cherry picked from commit ba8af45db501c2986d85f245bded230eaeee3ef2)
Reviewed-on: https://git-master.nvidia.com/r/1589795
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

media: i2c: Fix pixel rate for imx274

Correct pixel rate for 4k mode

Bug 200357182

Change-Id: Iae1a083eb4c2c5d713f19453fd08721272666b75
Reviewed-on: https://git-master.nvidia.com/r/1588442
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Esen Chen <esenc@nvidia.com>
Reviewed-by: Josh Kuo <joshk@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Aditya Tomar <adtomar@nvidia.com>
Reviewed-by: Shantanu Nath <snath@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

clk: tegra: remove const identifier

This is done to avoid a build error.

Change-Id: I73651d3ca94f2ae477a82d50a0cabbc6f05da1a2
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>

soc/tegra: rename t210b01 revision enum

Rename t210b01 revision enum to align with previous chip
revision enums ending with minor revision i.e
TEGRA210B01_REVISION_A01

Bug 200291974

Change-Id: I921d3477844e5c13ceb28dacbbba30821d3c09cc
Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com>
Reviewed-on: http://git-master/r/1326369
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
(cherry picked from commit 6cb4e4db3e65f499389515aa383e140973edcf74)

Revert "tegra: linsim removal"

This reverts commit ad1e62f568ec76784cba4b2225b1a53c445fd5a8
because it causes build issues in multiple drivers.

clk: tegra: Add T210b01 DFLL floor trip at 70C

Bug 1993768
Bug 1990253

Change-Id: I851ac019048b5a36067bbd928f52838c37f84a55
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1570428
(cherry picked from commit 1f1fb5f8fcd2b48ea596855dda9e0ebe645a742d)
Reviewed-on: https://git-master.nvidia.com/r/1576457
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
(cherry picked from commit f56dae8b4e6deb5e22423c01318e38fed954acdd)

clk: tegra: Remove T210b01 DFLL calibration limit

Bug 1993768
Bug 1990253

Change-Id: Iae8b155bb5ceea18ccdd4466b743ba62ca62a051
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1569691
(cherry picked from commit 87fead5fd9e94f23b7b7fda47fbd92a604af7720)
Reviewed-on: https://git-master.nvidia.com/r/1576455
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
(cherry picked from commit cae91810991d719767a5a67f0bd53ab4e6a20ded)

clk: tegra: Move DFLL thermal boundaries defines

DFLL thermal boundaries are just placeholders that are never set as
trip-points in thermal zone. Boundaries values are irrelevant as long
as they are below/above all others, actually set trip-points. They can
be set low/high enough to be applied for each SoC, and they are not
needed for thermal DT nodes. Therefore moved boundaries definitions
from per-SoC DT bindings headers to common DFLL header.

Bug 1993768
Bug 1990253

Change-Id: I5c5244e687564eb900bd70b39e13cca6f06f5caa
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1570427
(cherry picked from commit 345415f2e72d0f488d3e6da06d42a59448c62a5c)
Reviewed-on: https://git-master.nvidia.com/r/1572666
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
(cherry picked from commit fac4f0873214ebe91e81c64f513e1e0e8b0d78c9)

clk: soc: tegra: Separate DFLL max calibrate limit

Separated maximum DVCO rate limit applied to calibration results from
DFLL output rate maximum. Added CVB table entry for calibration limit,
and updated set DFLL rate operation, so that it won't bail out when
calibrated rate exceeds output Fmax, but rather engages skipper to
reach output target.

For backward compatibility when not specified in DFLL CVB table,
calibration limit is set the same as output maximum rate.

Bug 1993768
Bug 1990253

Change-Id: If0d263a3f321e2e0680b86d0e71fcea29809b491
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1569690
(cherry picked from commit 6503fb30eb12dbce65cbd48111d0b6f031eab066)
Reviewed-on: https://git-master.nvidia.com/r/1572662
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
(cherry picked from commit 6b2dcb0983007282a496c190f913d9f9f7a81fa2)

clk: soc: tegra: Add T210b01 CPU DVFS SLT p4v3

Added T210b01 CPU DVFS SLT p4v3, and restored CPU binning as it is
required for the new table integration.

Bug 1990001

Change-Id: I48e17e4981392a1928f351edde5158cb3c2056c2
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1565661
(cherry picked from commit 5f646ec96f9de7ace5e4ed81f1273a5fa9dea813)
Reviewed-on: https://git-master.nvidia.com/r/1566490
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
(cherry picked from commit 90f894e94a0a596d1ea7427f224057fd8d3d7926)

clk: soc: tegra: Add T210b01 CPU DVFS SLT p4v2

Bug 1990001

Change-Id: Ibdcffd0017cfe62ba35696a5bf33f8035081867e
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1562684
(cherry picked from commit f6185b211c47894c427e079cecd4b9643bb88d39)
Reviewed-on: https://git-master.nvidia.com/r/1563711
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
(cherry picked from commit 9e22bac33d3c63d9d2833984ff3bab1cc22ab864)

clk: soc: tegra: Integrate T210b01 CPU DVFS p4v3

Bug 1989990

Change-Id: I956ac0467113d347c1cb1240b63da1a20db5c72e
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1559457
(cherry picked from commit 8bef2cd64eb626da42a4af54db1c9d7965f91cfe)
Reviewed-on: https://git-master.nvidia.com/r/1561113
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
(cherry picked from commit dd010a273ac56cd6d760b78a34eaccd342ed009d)

clk: tegra: Support DFLL tuning override from DT

Change-Id: I1d3addfbe550949492167829e3a9c3a5a1a0f890
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1548986
(cherry picked from commit 1c28779a8f720113af4d61cd0f35761f3ce6cffd)
Reviewed-on: https://git-master.nvidia.com/r/1550299
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>
(cherry picked from commit b2233e399e862277a7edbb8cc6d0e7f73a25a9a5)

clk: tegra: Add T210b01 DFLL thermal cap table

Bug 1975072

Change-Id: Id252c0c3a57f1e6ca914459cd9755fa322bccae6
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1540823
(cherry picked from commit 124b72a5c086b5a4545b46ede4e0fa4d9336f3ae)
Reviewed-on: https://git-master.nvidia.com/r/1545763
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bo Yan <byan@nvidia.com>
(cherry picked from commit 58aa306acbcb376f607985ff0b2432be6f73a1aa)

clk: tegra: Integrate T210b01 CPU DVFS SLT p4v1

Bug 1973288

Change-Id: Ia07acddf2dd5b397fa0c2ef9d3a0e9d0e4f35596
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1537835
(cherry picked from commit a8eb73092ca78aa0032049f4792a5d310cbd801a)
Reviewed-on: https://git-master.nvidia.com/r/1539810
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bo Yan <byan@nvidia.com>
(cherry picked from commit 995507a359c3bf4ca21f4805d664766b1e7fa227)

clk: tegra: Update T210b01 CPU DVFS p4v2

Bug 1971441

Change-Id: If13a4c82ad30d805cfbf789888205b312425a8c8
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1537804
(cherry picked from commit 702446254d384f95592b4b1ea836e9b35910c9ce)
Reviewed-on: https://git-master.nvidia.com/r/1539805
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bo Yan <byan@nvidia.com>
(cherry picked from commit 50c3bc9d8a4f8d722b0476d78295ea3b5ba46ea4)

clk: tegra: Move T210b01 DFLL tuning data to macro

Bug 1971441

Change-Id: I96be858a203cac808fd93655e822ed371215a84b
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1537803
(cherry picked from commit 1e9469afcb1ee5b8c172dfe1c0384f8dd6010c2b)
Reviewed-on: https://git-master.nvidia.com/r/1539804
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bo Yan <byan@nvidia.com>
(cherry picked from commit 882d31073f0102440aecfe7b9f6dfe99dae64389)

clk: soc: tegra: Integrate T210b01 CPU DVFS p4v2

Bug 1971441

Change-Id: I6223c42d2ede8c10bcb8bdd879ac95f69981ee1c
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1536897
(cherry picked from commit b108f996cbce3749863092dc383780e9f26c4a52)
Reviewed-on: https://git-master.nvidia.com/r/1538239
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
(cherry picked from commit 80a9b430a5b877574180c9f62e903bad545c377e)

clk: soc: tegra: Add DFLL tune high margin voltage

Added DFLL tune high margin voltage entry in CVB table. This allows to
replace current fixed margin defined as number of DFLL voltage steps
with per-table/per-chip margin in millivolts, and convert it to steps
during DFLL initialization.

Bug 1967884

Change-Id: I2cbb045665c9f3d23f6b2b721d6902bd02ddc58a
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1533488
(cherry picked from commit 32d817b60c508c5343df640f6d91d8d106ce1790)
Reviewed-on: https://git-master.nvidia.com/r/1534501
GVS: Gerrit_Virtual_Submit
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
(cherry picked from commit 395b2b912578d43ead36a686393cb2b7d48b41e2)

clk: soc: tegra: Add DFLL tune1_high parameter

Added support for DFLL tune1_high parameter (not set on any
Tegra SoC, yet).

Bug 1967884

Change-Id: I4c90d916b0f5646ee20dba4e97f8963c94124e1b
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1533308
(cherry picked from commit 43073fadc101cc21f7f6a89b643fbbe89ebc1968)
Reviewed-on: https://git-master.nvidia.com/r/1534500
GVS: Gerrit_Virtual_Submit
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
(cherry picked from commit 3da99f2e4e482e36fc9d60a71a965b87b9287dd0)

clk: soc: tegra: Rename DFLL tune1 to tune1_low

Renamed DFLL tune1 to tune1_low to be consistent with
tune0_low/tune0_high naming convention.

Bug 1967884

Change-Id: Ic3a3270eec6aa270578d9b58459720d9756707f5
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1533307
(cherry picked from commit d4552faac76300b6563e74711e8247ae4f0ebd2a)
Reviewed-on: https://git-master.nvidia.com/r/1534499
GVS: Gerrit_Virtual_Submit
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
(cherry picked from commit 08283cf4908c74c863e396497de8cd027085c1d6)

clk: tegra: Update T210B01 DFLL tuning parameters

Bug 1906940

Change-Id: I6d4fbd94d57d12a7ce71d618ad487ff65bb67e99
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/1494329
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
(cherry picked from commit 60448b643b305f0f0c9d871ef3b6b837b51a7712)
Reviewed-on: http://git-master/r/1494546
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
(cherry picked from commit 06e0c742958fa41b11e37f9336a61d5678044a4d)

clk: soc: tegra: Integrate p4v1 CPU DVFS table

Bug 1906940

Change-Id: I48420305152cb27e42f47128ce588e9ae84c0848
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/1485335
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
(cherry picked from commit d062fc6e92102ab8868ce7be2b1353576b0f559a)

soc/tegra: gpu-edp: Clean-up PM QoS notifier

Move the GPU EDP notifier block structure to the 'gpu_edp' structure
so that we can then use the 'container_of' helper function to retrieve
the 'gpu_edp' structure within the notifier. By doing so we can avoid
having the statically declared variable 's_gpu'.

Bug 1811732

Change-Id: Ieb40883afc24c5844c0830a19e02b2487db1db6e
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1577060
GVS: Gerrit_Virtual_Submit
Reviewed-by: Timo Alho <talho@nvidia.com>
(cherry picked from commit d9137cff98a4d8a474a4dc058ad980b2cb9fb1ab)

soc/tegra: gpu-edp: Put the GPU clock on error

The GPU clock is retrieved using the 'clk_get_sys()' API during the
probe of the GPU EDP driver and so must be put with 'clk_put()' if
the probe fails. Currently, 'clk_put()' is not being called for the
GPU clock on failure and so fix this.

Bug 1811732

Change-Id: Iea8a2e6d9010e55122ce2e62effeb34b6ae42ffa
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1577059
GVS: Gerrit_Virtual_Submit
Reviewed-by: Timo Alho <talho@nvidia.com>
(cherry picked from commit 9d10e9c1e4423324a398c5f01183038e1578cfb0)

soc/tegra: kfuse: remove legacy clock calls

Legacy clock framework is phased out in favor of CCF. Remove calls to
legacy functions.

Bug 1990651

Change-Id: I3e440d25e04f83eba05743caeec372ddd38c4352
Signed-off-by: Timo Alho <talho@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1559860
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
(cherry picked from commit 41d4ef372a8a3cc591f252153e75d03241587f35)

soc: tegra: Integrate T210b01 SoC DVFS SLT p4v3

Bug 1990001

Change-Id: If64be7c850b556cfeed3bcf883a2291ca5c5e000
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1562933
(cherry picked from commit 988fc6e2bc9a66dbfae3963c3cbc723349cbe20c)
Reviewed-on: https://git-master.nvidia.com/r/1565635
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
(cherry picked from commit ed0a5f05a15ae9eab43341945000218daa188f9d)

soc/tegra: pmc: Rename DT props to make its length < 32

Rename some of DT properties to make its length < 32 character
to meet ePAPR specs.

Still keep the older property to have backward compatibility.
Properties are:
  nvidia,wait-before-start-bus-clear-us -> nvidia,wait-start-bus-clear-us
  nvidia,core-power-req-active-high -> nvidia,core-pwr-req-active-high

Bug 200347832

Change-Id: I866bda9c7353a384eed950ead9b78835efa1dc8d
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1564325
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Shardar Mohammed <smohammed@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
(cherry picked from commit 592da8e7352fbc3f30a080a51940bcd7241121b5)

soc: tegra: Integrate T210b01 GPU DVFS SLT p4v2

Bug 1990001

Change-Id: Ibe894fa66ccd663f6a34ab33ad518c95985738fc
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1562685
(cherry picked from commit 4255186f07a2c8327a345199efd6a00ff2ec7bbf)
Reviewed-on: https://git-master.nvidia.com/r/1563712
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
(cherry picked from commit 0e892f5aa26903267fc5175dbafbac6c591f413e)

soc: tegra: Integrate T210b01 SoC DVFS p4v3

Bug 1989990

Change-Id: I60b03d7f1defbd430c55b8f5a3796e54e1773e20
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1561068
(cherry picked from commit a5ac6e3020914933fed642d2506d0992344d05cc)
Reviewed-on: https://git-master.nvidia.com/r/1562719
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
(cherry picked from commit 38fd35d4c9579d9ef65af342fc17bd03c0b50a56)

soc: tegra: Add support for sor1_dp bins

Since, sor1_dp DVFS is implemented as alternative (to sor1_hdmi) DVFS
on the same sor1 clock, parsing of sor1_dp DVFS table was simplified
to assume always common curve across SoC bins. Extended parsing to
support possible binning of sor1_dp.

Bug 1989990

Change-Id: I553f1726aa4af3245bd8ae6163cc4b12286fa129
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1561067
(cherry picked from commit f74aebd6a3a1334b573fdb78a0100c9edb04ab93)
Reviewed-on: https://git-master.nvidia.com/r/1562717
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
(cherry picked from commit 23e5438a8bc23d23196ec7796e4a9e08105e15d0)

soc: tegra: Update T210b01 speedo thresholds

Bug 1989990

Change-Id: Ia97117eb92e73c88d2b53a42dbe2b3ca5fc20ca4
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1561066
(cherry picked from commit 8d928fe3a3fde46c0ea3ebd0a8de10b2b43a5da2)
Reviewed-on: https://git-master.nvidia.com/r/1561594
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
(cherry picked from commit 4f8854028f55aacf122feb1c88bd49893d105af4)

soc: tegra: Integrate T210b01 GPU DVFS p4v3

Bug 1989990

Change-Id: Ibcd4fac3f4e58fe8d288dca42b33b8eea44bdbc6
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1560288
(cherry picked from commit a7d0d2e3c91d0b044a58f6c1fefd2bc6fa0aa2c2)
Reviewed-on: https://git-master.nvidia.com/r/1561114
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
(cherry picked from commit 9291ec4a93d0eb07a51766cbd24ce48e170b61f6)

soc: tegra: Integrate T210b01 SoC IO DVFS SLT p4v2

Updated DVFS tables for AHUB (d_audio) and QSPI clocks. Added missing
DVFS entry for SPDIF_IN clock.

Bug 1983141

Change-Id: Ia40f5a3d5fdb33f3be19e9a2e4c6f4cbc6c5b22a
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1553054
(cherry picked from commit 79c8f0d54880ac61c9e6a5ef15adc696c495e178)
Reviewed-on: https://git-master.nvidia.com/r/1555829
GVS: Gerrit_Virtual_Submit
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>
(cherry picked from commit 78a40385f38bc8de3ff773918de41d516ccf1ac9)

soc: tegra: Integrate T210b01 SoC IO DVFS p4v3

Updated DVFS tables for AHUB (d_audio) and QSPI clocks. Added missing
DVFS entry for SPDIF_IN clock.

Bug 1983141

Change-Id: I7c901eea1dc36ac1cc289876529f888902865565
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1553050
(cherry picked from commit a33ca9a933b8c53c6c34be57e2299e074374dae0)
Reviewed-on: https://git-master.nvidia.com/r/1555826
GVS: Gerrit_Virtual_Submit
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>
(cherry picked from commit bc4156a3903a0902ecbd1c5a7105f90794c326e3)

soc: tegra: Issue over-cap warning once

If rail voltage exceeds thermal cap print warning once when it happens
the first time. Cap override mode is allowed in debugfs for testing
purposes, and no need to clutter debug console with multiple warnings
in this case.

Bug 1975072

Change-Id: I11e9652750200e078cf684f944bb228cb93f9b95
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1545507
(cherry picked from commit 3579a084ed2c412b0f2c34500720f6edae2519c2)
Reviewed-on: https://git-master.nvidia.com/r/1546274
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
(cherry picked from commit ca8f8ba5345ec09fa51ceb56ac20d6abd5e4b73d)

soc: tegra: Update T210B01 VDD_CORE cap limit

Bug 1975072

Change-Id: Ic9613d713f26e16e6ae16d5d68a71a9aaa777d05
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1540825
(cherry picked from commit 58d48d3b88dcfa5dbf3d7d4a175c69cfb2d08bc6)
Reviewed-on: https://git-master.nvidia.com/r/1545765
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bo Yan <byan@nvidia.com>
(cherry picked from commit 27537c5cdff60afec389cb79df797a93a6915a75)