clk: soc: tegra: Add T210b01 CPU DVFS SLT p4v2

Bug 1990001

Change-Id: Ibdcffd0017cfe62ba35696a5bf33f8035081867e
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1562684
(cherry picked from commit f6185b211c47894c427e079cecd4b9643bb88d39)
Reviewed-on: https://git-master.nvidia.com/r/1563711
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
(cherry picked from commit 9e22bac33d3c63d9d2833984ff3bab1cc22ab864)

diff --git a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
index 1bb6d5c0d37fd0d6ef8bde5a4de18259550d075b..2bc03bbb5807dd133e68b8d267ca264d4aaa32f8 100644 (file)
--- a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
+++ b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
@@ -518,36 +518,37 @@ struct cvb_table tegra210_cpu_cvb_tables[] = {
        .voltage_scale = 1000,  \
        .cvb_table = {          \
                /* f                    c0,       c1,       c2 */   \
-               {  204000000UL, {   718009,   -11535,      -42 } }, \
-               {  306000000UL, {   738304,   -12595,      -42 } }, \
-               {  408000000UL, {   761731,   -13665,      -42 } }, \
-               {  510000000UL, {   788290,   -14725,      -42 } }, \
-               {  612000000UL, {   817980,   -15785,      -42 } }, \
-               {  714000000UL, {   850802,   -16845,      -42 } }, \
-               {  816000000UL, {   886755,   -17905,      -42 } }, \
-               {  918000000UL, {   925841,   -18965,      -42 } }, \
-               { 1020000000UL, {   968057,   -20025,      -42 } }, \
-               { 1122000000UL, {  1013406,   -21085,      -42 } }, \
-               { 1224000000UL, {  1061886,   -22155,      -42 } }, \
-               { 1326000000UL, {  1113498,   -23215,      -42 } }, \
-               { 1428000000UL, {  1168242,   -24275,      -42 } }, \
-               { 1581000000UL, {  1256229,   -25865,      -42 } }, \
-               { 1683000000UL, {  1318801,   -26925,      -42 } }, \
-               { 1785000000UL, {  1384505,   -27985,      -42 } }, \
-               { 1887000000UL, {  1453341,   -29045,      -42 } }, \
-               { 1963500000UL, {  1506667,   -29835,      -42 } }, \
-               { 2091000000UL, {  1584718,   -31175,      -42 } }, \
+               {  204000000UL, {   732856,   -17335,      113 } }, \
+               {  306000000UL, {   760024,   -18195,      113 } }, \
+               {  408000000UL, {   789258,   -19055,      113 } }, \
+               {  510000000UL, {   820558,   -19915,      113 } }, \
+               {  612000000UL, {   853926,   -20775,      113 } }, \
+               {  714000000UL, {   889361,   -21625,      113 } }, \
+               {  816000000UL, {   926862,   -22485,      113 } }, \
+               {  918000000UL, {   966431,   -23345,      113 } }, \
+               { 1020000000UL, {  1008066,   -24205,      113 } }, \
+               { 1122000000UL, {  1051768,   -25065,      113 } }, \
+               { 1224000000UL, {  1097537,   -25925,      113 } }, \
+               { 1326000000UL, {  1145373,   -26785,      113 } }, \
+               { 1428000000UL, {  1195276,   -27645,      113 } }, \
+               { 1581000000UL, {  1274006,   -28935,      113 } }, \
+               { 1683000000UL, {  1329076,   -29795,      113 } }, \
+               { 1785000000UL, {  1386213,   -30655,      113 } }, \
+               { 1887000000UL, {  1445416,   -31515,      113 } }, \
+               { 1963500000UL, {  1490873,   -32155,      113 } }, \
+               { 2065500000UL, {  1553683,   -33015,      113 } }, \
+               { 2091000000UL, {  1580725,   -33235,      113 } }, \
                { 0,            { } }, \
        }, \
-       .vmin_coefficients =    {   630000,        0,        0 }, \
+       .vmin_coefficients =    {   600000,        0,        0 }, \
        .cpu_dfll_data = {                                        \
-               .tune0_low  = 0x0000FFFF,                         \
-               .tune1_low  = 0x177F7FF,                          \
-               .tune1_high = 0x21107FF,                          \
+               .tune0_low  = 0x0000FF90,                         \
+               .tune0_high = 0x0000FFFF,                         \
+               .tune1_low  = 0x21107FF,                          \
                .tune_high_min_millivolts = 850,                  \
                .tune_high_margin_millivolts = 38,                \
        }, \
-       .cvb_version = "FCPU Table - p4v1-AggressiveSLT"
+       .cvb_version = "FCPU Table - p4v2-AggressiveSLT"
 
 #define CPUB01_CVB_TABLE       \
        .speedo_scale = 100,    \

diff --git a/drivers/soc/tegra/tegra210-dvfs.c b/drivers/soc/tegra/tegra210-dvfs.c
index 41dc0e60f2e9f89e7bff3e1ec5f46c6fc8de679a..0b1942f3cabf33f8f196fba7dda03c5b12834361 100644 (file)
--- a/drivers/soc/tegra/tegra210-dvfs.c
+++ b/drivers/soc/tegra/tegra210-dvfs.c
@@ -554,6 +554,7 @@ static struct cpu_dvfs cpu_fv_dvfs_table[] = {
                { 1785000000UL, {  1120000,        0,        0 } }, \
                { 1887000000UL, {  1120000,        0,        0 } }, \
                { 1963500000UL, {  1120000,        0,        0 } }, \
+               { 2065500000UL, {  1120000,        0,        0 } }, \
                { 2091000000UL, {  1120000,        0,        0 } }, \
                { 0,            { } }, \
        }, \