clk: tegra: Update T210B01 DFLL tuning parameters

Bug 1906940

Change-Id: I6d4fbd94d57d12a7ce71d618ad487ff65bb67e99
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/1494329
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
(cherry picked from commit 60448b643b305f0f0c9d871ef3b6b837b51a7712)
Reviewed-on: http://git-master/r/1494546
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
(cherry picked from commit 06e0c742958fa41b11e37f9336a61d5678044a4d)

diff --git a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
index f2c2424e355e9762b43ccd237ee5b2082c554ba2..17fe2ded0c5d87fc5c86e8d102ee159588ba51ec 100644 (file)
--- a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
+++ b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
@@ -588,8 +588,8 @@ struct cvb_table tegra210b01_cpu_cvb_tables[] = {
                .max_millivolts = 1120,
                CPUB01_CVB_TABLE,
                .cpu_dfll_data = {
-                       .tune0_low = 0xffead0ff,
-                       .tune1 = 0x20091d9,
+                       .tune0_low = 0x00009F87,
+                       .tune1 = 0x010001C0,
                }
        },
        {
@@ -598,8 +598,8 @@ struct cvb_table tegra210b01_cpu_cvb_tables[] = {
                .max_millivolts = 1120,
                CPUB01_CVB_TABLE,
                .cpu_dfll_data = {
-                       .tune0_low = 0xffead0ff,
-                       .tune1 = 0x25501d0,
+                       .tune0_low = 0x00009F87,
+                       .tune1 = 0x010001C0,
                }
        },
 };