clk: tegra: Move T210b01 DFLL tuning data to macro

Bug 1971441

Change-Id: I96be858a203cac808fd93655e822ed371215a84b
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1537803
(cherry picked from commit 1e9469afcb1ee5b8c172dfe1c0384f8dd6010c2b)
Reviewed-on: https://git-master.nvidia.com/r/1539804
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bo Yan <byan@nvidia.com>
(cherry picked from commit 882d31073f0102440aecfe7b9f6dfe99dae64389)

diff --git a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
index e127de09ef74639053cdfc6befaa1269f798bcfe..519c7504ed81a71e99cfe8d295efad08b6477ac3 100644 (file)
--- a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
+++ b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
@@ -540,6 +540,10 @@ struct cvb_table tegra210_cpu_cvb_tables[] = {
                { 0,            { } }, \
        }, \
        .vmin_coefficients =    {   700000,        0,        0 }, \
+       .cpu_dfll_data = {                                        \
+               .tune0_low = 0x00009F87,                          \
+               .tune1_low = 0x010001C0,                          \
+       }, \
        .cvb_version = "SLT FCPU Table - p4v1"
 
 #define CPUB01_CVB_TABLE       \
@@ -569,6 +573,13 @@ struct cvb_table tegra210_cpu_cvb_tables[] = {
                { 0,            { } }, \
        }, \
        .vmin_coefficients =    {   700000,        0,        0 }, \
+       .cpu_dfll_data = {                                        \
+               .tune0_low  = 0x0000FFCF,                         \
+               .tune1_low  = 0x16607FF,                          \
+               .tune1_high = 0x3FFF7FF,                          \
+               .tune_high_min_millivolts = 850,                  \
+               .tune_high_margin_millivolts = 38,                \
+       }, \
        .cvb_version = "FCPU Table - p4v2"
 
 struct cvb_table tegra210b01_cpu_cvb_tables[] = {
@@ -577,23 +588,12 @@ struct cvb_table tegra210b01_cpu_cvb_tables[] = {
                .process_id = -1,
                .max_millivolts = 1120,
                CPUB01_CVB_TABLE_SLT,
-               .cpu_dfll_data = {
-                       .tune0_low = 0x00009F87,
-                       .tune1_low = 0x010001C0,
-               }
        },
        {
                .speedo_id = -1,
                .process_id = -1,
                .max_millivolts = 1120,
                CPUB01_CVB_TABLE,
-               .cpu_dfll_data = {
-                       .tune0_low  = 0x0000FFCF,
-                       .tune1_low  = 0x016607FF,
-                       .tune1_high = 0x03FFF7FF,
-                       .tune_high_min_millivolts = 850,
-                       .tune_high_margin_millivolts = 38,
-               }
        },
 };