clk: soc: tegra: Add DFLL tune1_high parameter

Added support for DFLL tune1_high parameter (not set on any
Tegra SoC, yet).

Bug 1967884

Change-Id: I4c90d916b0f5646ee20dba4e97f8963c94124e1b
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1533308
(cherry picked from commit 43073fadc101cc21f7f6a89b643fbbe89ebc1968)
Reviewed-on: https://git-master.nvidia.com/r/1534500
GVS: Gerrit_Virtual_Submit
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
(cherry picked from commit 3da99f2e4e482e36fc9d60a71a965b87b9287dd0)

diff --git a/drivers/clk/tegra/clk-dfll.c b/drivers/clk/tegra/clk-dfll.c
index 41d59df05dce9cf8ef7bcbe5999aa10fc88d8924..1361fd23a5451199147992572f5ba2bc4f65aae6 100644 (file)
--- a/drivers/clk/tegra/clk-dfll.c
+++ b/drivers/clk/tegra/clk-dfll.c
@@ -677,10 +677,13 @@ static void dfll_tune_low(struct tegra_dfll *td)
  */
 static void dfll_tune_high(struct tegra_dfll *td)
 {
+       u32 tune0_high = td->soc->tune0_high ? : td->soc->tune0_low;
+       u32 tune1_high = td->soc->tune1_high ? : td->soc->tune1_low;
+
        td->tune_range = DFLL_TUNE_HIGH;
 
-       dfll_writel(td, td->soc->tune0_high, DFLL_TUNE0);
-       dfll_writel(td, td->soc->tune1_low, DFLL_TUNE1);
+       dfll_writel(td, tune0_high, DFLL_TUNE0);
+       dfll_writel(td, tune1_high, DFLL_TUNE1);
        dfll_wmb(td);
 
        if (td->soc->set_clock_trimmers_high)

diff --git a/drivers/clk/tegra/clk-dfll.h b/drivers/clk/tegra/clk-dfll.h
index 2afe2279cd2728036b1ac7e88c5ef75c43d455cb..368c255caf046797353a36561ef846e2fb12879d 100644 (file)
--- a/drivers/clk/tegra/clk-dfll.h
+++ b/drivers/clk/tegra/clk-dfll.h
@@ -49,6 +49,7 @@ struct tegra_dfll_soc_data {
        u32 tune0_low;
        u32 tune0_high;
        u32 tune1_low;
+       u32 tune1_high;
        unsigned int tune_high_min_millivolts;
        void (*init_clock_trimmers)(void);
        void (*set_clock_trimmers_high)(void);

diff --git a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
index 1d332d14c0a44fb9110c0d4078219cf921b1e4f7..fd84b7a47a2ea37d03a8f1c3d521a50751ada42b 100644 (file)
--- a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
+++ b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
@@ -799,6 +799,7 @@ static int tegra124_dfll_fcpu_probe(struct platform_device *pdev)
        soc->tune0_low = cvb->cpu_dfll_data.tune0_low;
        soc->tune0_high = cvb->cpu_dfll_data.tune0_high;
        soc->tune1_low = cvb->cpu_dfll_data.tune1_low;
+       soc->tune1_high = cvb->cpu_dfll_data.tune1_high;
        soc->tune_high_min_millivolts =
                cvb->cpu_dfll_data.tune_high_min_millivolts;
        soc->cvb_version = cvb->cvb_version;

diff --git a/include/soc/tegra/cvb.h b/include/soc/tegra/cvb.h
index a40eeb63c2ae0e74231269037c879b1c579c8599..d95f9507bdec09d4779dc15b21cb2d75b9294f58 100644 (file)
--- a/include/soc/tegra/cvb.h
+++ b/include/soc/tegra/cvb.h
@@ -46,6 +46,7 @@ struct cvb_cpu_dfll_data {
        u32 tune0_low;
        u32 tune0_high;
        u32 tune1_low;
+       u32 tune1_high;
        unsigned int tune_high_min_millivolts;
 };