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arm64: config: Enable CDC-ACM driver in kernel
[hercules2020/nv-tegra/linux-4.4.git] / drivers / clk /
2017-11-20 Jeffery Yuclk: tegra: Fix build errors on T18x tree | commitdiff
2017-11-19 Bharat NihalaniMerge branch 'origin/dev/bnihalani_clk_soc' into HEAD tree | commitdiff
2017-11-14 Gerrit Code ReviewMerge "Merge branch 'origin/dev/bnihalani_pwm_thermal... tree | commitdiff
2017-11-14 Jon Hunterclk: tegra: Fix maximum audio sync clock for Tegra210 tree | commitdiff
2017-10-31 Bharat Nihalaniclk: tegra: remove const identifier tree | commitdiff
2017-10-31 Bharat NihalaniRevert "tegra: linsim removal" tree | commitdiff
2017-10-31 Alex Fridclk: tegra: Add T210b01 DFLL floor trip at 70C tree | commitdiff
2017-10-31 Alex Fridclk: tegra: Remove T210b01 DFLL calibration limit tree | commitdiff
2017-10-31 Alex Fridclk: tegra: Move DFLL thermal boundaries defines tree | commitdiff
2017-10-31 Alex Fridclk: soc: tegra: Separate DFLL max calibrate limit tree | commitdiff
2017-10-31 Alex Fridclk: soc: tegra: Add T210b01 CPU DVFS SLT p4v3 tree | commitdiff
2017-10-31 Alex Fridclk: soc: tegra: Add T210b01 CPU DVFS SLT p4v2 tree | commitdiff
2017-10-31 Alex Fridclk: soc: tegra: Integrate T210b01 CPU DVFS p4v3 tree | commitdiff
2017-10-31 Alex Fridclk: tegra: Support DFLL tuning override from DT tree | commitdiff
2017-10-31 Alex Fridclk: tegra: Add T210b01 DFLL thermal cap table tree | commitdiff
2017-10-31 Alex Fridclk: tegra: Integrate T210b01 CPU DVFS SLT p4v1 tree | commitdiff
2017-10-31 Alex Fridclk: tegra: Update T210b01 CPU DVFS p4v2 tree | commitdiff
2017-10-31 Alex Fridclk: tegra: Move T210b01 DFLL tuning data to macro tree | commitdiff
2017-10-31 Alex Fridclk: soc: tegra: Integrate T210b01 CPU DVFS p4v2 tree | commitdiff
2017-10-31 Alex Fridclk: soc: tegra: Add DFLL tune high margin voltage tree | commitdiff
2017-10-31 Alex Fridclk: soc: tegra: Add DFLL tune1_high parameter tree | commitdiff
2017-10-31 Alex Fridclk: soc: tegra: Rename DFLL tune1 to tune1_low tree | commitdiff
2017-10-31 Alex Fridclk: tegra: Update T210B01 DFLL tuning parameters tree | commitdiff
2017-10-31 Alex Fridclk: soc: tegra: Add SLT DVFS tables placeholders tree | commitdiff
2017-10-31 Alex Fridclk: soc: tegra: Specify CPU CVB version in table tree | commitdiff
2017-10-31 Alex Fridclk: soc: tegra: Define T210B01 thermal DVFS trips tree | commitdiff
2017-10-31 Alex Fridclk: soc: tegra: Integrate T210B01 p4v1 core DVFS tree | commitdiff
2017-10-31 Alex Fridclk: soc: tegra: Integrate p4v1 CPU DVFS table tree | commitdiff
2017-10-31 Alex Fridsoc: tegra: Integrate T210b01 CPU DVFS tables tree | commitdiff
2017-10-31 Alex Fridclk: tegra: Restore PLLP_OUTA register after SC7 tree | commitdiff
2017-10-31 Alex Fridclk: tegra: Disable T21x pll_p_out4 if not used tree | commitdiff
2017-10-31 Alex Fridclk: tegra: Disable T210b01 pll_p_out1 divider tree | commitdiff
2017-10-31 Alex Fridclk: tegra: Set T210b01 usb track clock rate tree | commitdiff
2017-10-31 Alex Fridclk: tegra: Shift DFLL calibration round range tree | commitdiff
2017-10-31 Alex Fridclk: tegra: Calibrate only one floor at a time tree | commitdiff
2017-10-31 Alex Fridclk: tegra: Re-calibrate all DFLL floors after SC7 tree | commitdiff
2017-10-31 Alex Fridclk: tegra: Re-calibrate DFLL cold floors tree | commitdiff
2017-10-31 Alex Fridclk: tegra: Calibrate DFLL tuning in thermal range tree | commitdiff
2017-10-31 Alex Fridclk: tegra: Don't disable DFLL tuning over-clock tree | commitdiff
2017-10-31 Alex Fridclk: tegra: Control DFLL tuning disable from DT tree | commitdiff
2017-10-31 Alex Fridclk: tegra: Disable over-clock dynamic DFLL tuning tree | commitdiff
2017-10-31 Nicolin Chenclk: tegra: Fix pll_mb_ud clock of T210 tree | commitdiff
2017-10-31 Alex Fridclk: tegra: Fix DFLL debugfs force voltage setting tree | commitdiff
2017-10-31 Alex Fridclk: tegra: Log calibration time in debugfs tree | commitdiff
2017-10-31 Alex Fridclk: tegra: Enable T210b01 audio clocks fractions tree | commitdiff
2017-10-31 Alex Fridclk: tegra: Register and initialize SPDIF_IN clock tree | commitdiff
2017-10-31 Alex Fridclk: tegra: Force DFLL re-calibrate via debugfs tree | commitdiff
2017-10-31 Alex Fridclk: tegra: Enable cap override under debug config tree | commitdiff
2017-10-31 Alex Fridclk: tegra: Adjust T210b01 VDD_CORE cap clocks tree | commitdiff
2017-10-31 Alex Fridclk: tegra: Allow fractional UART dividers tree | commitdiff
2017-10-31 Alex Fridclk: tegra: Enable T210b01 APE re-parenting tree | commitdiff
2017-10-31 Alex Fridclk: tegra: Move APE clock definition to T210 code tree | commitdiff
2017-10-31 Alex Fridclk: tegra: Support Tegra peripheral re-parenting tree | commitdiff
2017-10-31 Ajay Nandakumar MRevert "Revert "clk: tegra: fix pll_p parent for aclk"" tree | commitdiff
2017-10-31 Peter De Schrijverclk: tegra: prepare/unprepare for bus clocks tree | commitdiff
2017-10-31 Alex Fridclk: tegra: Expand T210b01 integer dividers list tree | commitdiff
2017-10-31 Alex Fridclk: tegra: Fix T210/T210b01 SOR1 definition tree | commitdiff
2017-10-31 Alex Fridclk: tegra: Add integer dividers list for T210b01 tree | commitdiff
2017-10-31 Alex Fridclk: tegra: Allow per-SoC integer div requirement tree | commitdiff
2017-10-31 Alex Fridclk: tegra: Don't re-enable T210b01 UTMIPLL on boot tree | commitdiff
2017-10-31 Alex Fridclk: tegra: Remove dead T210B01 PLLM/MB init code tree | commitdiff
2017-10-31 Alex Fridclk: tegra: Fix PLLC4 VCO maximum rate tree | commitdiff
2017-10-31 Alex Fridclk: tegra: Use HR timer for DFLL tuning tree | commitdiff
2017-10-31 Peter De Schrijverclk: tegra210: remove superfluous clkids tree | commitdiff
2017-10-31 Peter De Schrijverclk: tegra210: factor out slcg_ovr clkdevs tree | commitdiff
2017-10-31 Peter De Schrijverclk: tegra: factor out tegra-clk-debug devclk registration tree | commitdiff
2017-10-31 Peter De Schrijverclk: tegra214: remove SLCG override clocks tree | commitdiff
2017-10-31 Alex Fridclk: tegra: Fix tuning init and state debug prints tree | commitdiff
2017-10-31 Alex Fridclk: tegra: Add sclk shared user for WIFI tree | commitdiff
2017-10-31 Alex Fridclk: tegra: Add clock lookups for DVFS binding tree | commitdiff
2017-10-31 Alex Fridclk: tegra: Fix DFLL high voltage range tuning tree | commitdiff
2017-10-31 Alex Fridclk: tegra: Fix DFLL one-shot for dynamic tuning tree | commitdiff
2017-10-31 Alex Fridclk: tegra: Use retry timer for DFLL one-shot tree | commitdiff
2017-10-31 Alex Fridclk: tegra: Abort DFLL one-shot if I2C is busy tree | commitdiff
2017-10-31 Alex Fridclk: tegra: Add sanity check for DFLL maximum rate tree | commitdiff
2017-10-31 Bharat NihalaniRevert "clk: tegra: fix pll_p parent for aclk" tree | commitdiff
2017-10-31 Peter De Schrijverclk: tegra: fix pll_p parent for aclk tree | commitdiff
2017-10-31 Alex Fridclk: tegra: Update T210B01 PLLA defaults tree | commitdiff
2017-10-31 Samuel PayneRevert "drivers: clock: set utmi pll under HW CTL" tree | commitdiff
2017-10-31 Alex Fridclk: tegra: Update PLLREFE frequency table tree | commitdiff
2017-10-31 Alex Fridclk: tegra: Get DFLL one-shot settle time from DT tree | commitdiff
2017-10-31 Alex Fridclk: tegra: Update T210B01 PLLDP spread settings tree | commitdiff
2017-10-31 Alex Fridclk: tegra: Update T210B01 PLLE spread settings tree | commitdiff
2017-10-31 Alex Fridclk: tegra: Clear T210B01 PLLs setup field tree | commitdiff
2017-10-31 Alex Fridclk: tegra: Set T210 APB rate floor at 51MHz tree | commitdiff
2017-10-31 William Piercetegra: linsim removal tree | commitdiff
2017-10-31 Alex Fridclk: tegra: Add T210 EMC pto counter tree | commitdiff
2017-10-31 Alex Fridclk: tegra: Install CBUS override user clock tree | commitdiff
2017-10-31 Rohith Seelaboyinadrivers: clock: set utmi pll under HW CTL tree | commitdiff
2017-10-31 Peter De Schrijverclk: tegra: Add ignore clocks property tree | commitdiff
2017-10-31 Alex Fridclk: tegra: Return current rate if no round op tree | commitdiff
2017-10-31 Peter De Schrijverclk: tegra: skip invalid clocks in adding OF provider tree | commitdiff
2017-10-31 Peter De Schrijverclk: tegra210: remove non-existing VFIR clock tree | commitdiff
2017-10-31 Alex Fridclk: tegra: Don't save/restore T210B01 PLLM/PLLMB tree | commitdiff
2017-10-31 Peter De Schrijverclk: tegra124: disable HW control of PLLU IDDQ tree | commitdiff
2017-10-31 Peter De Schrijverclk: tegra: dont suspend/resume dfll if not inited tree | commitdiff
2017-10-31 Alex Fridclk: tegra: Don't register PLLM/PLLMB on T210B01 tree | commitdiff
2017-10-31 Alex Fridclk: tegra: Clean up T210B01 pll config warnings tree | commitdiff
2017-10-31 Peter De Schrijverclk: tegra: keep PLL enabled on lock failure tree | commitdiff
2017-10-31 BH Hsiehclk: tegra: remove duplicate con_id for xusb tree | commitdiff
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