Revert "drivers: clock: set utmi pll under HW CTL"

This reverts commit 5c3dcec66a1e1a08adda3bc5f4dc473b463e6e92.

Change-Id: I18b962f5c2b11a5300dd6cb6155b08086620d744
Reviewed-on: https://git-master.nvidia.com/r/1527232
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
(cherry picked from commit 6a88acd343807a381f20623a4a971cff5df3c2b8)

diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index 1bdfba50534a8ea7cd0ac08b011b4f7298aa1ba6..ebff924816612b184b5661d2c3ae92d6f30911fc 100644 (file)
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -227,6 +227,7 @@
 #define XUSBIO_PLL_CFG0_SEQ_ENABLE             BIT(24)
 
 #define UTMIPLL_HW_PWRDN_CFG0                  0x52c
+#define UTMIPLL_HW_PWRDN_CFG0_UTMIPLL_LOCK     BIT(31)
 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE  BIT(25)
 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE       BIT(24)
 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE  BIT(7)
@@ -2929,8 +2930,6 @@ static void tegra210_utmi_param_configure(void)
        writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
 
        reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
-       reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL;
-       reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE;
        reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
        reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
        writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
@@ -2951,6 +2950,34 @@ static void tegra210_utmi_param_configure(void)
        fence_udelay(1, clk_base);
 }
 
+void tegra210_put_utmipll_in_iddq(void)
+{
+       u32 reg;
+
+       reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
+
+       if (reg & UTMIPLL_HW_PWRDN_CFG0_UTMIPLL_LOCK) {
+               pr_err("trying to assert IDDQ while UTMIPLL is locked\n");
+               return;
+       }
+
+       reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
+       writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
+       fence_udelay(1, clk_base);
+}
+EXPORT_SYMBOL_GPL(tegra210_put_utmipll_in_iddq);
+
+void tegra210_put_utmipll_out_iddq(void)
+{
+       u32 reg;
+
+       reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
+       reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
+       writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
+       fence_udelay(5, clk_base);
+}
+EXPORT_SYMBOL_GPL(tegra210_put_utmipll_out_iddq);
+
 static int tegra210_enable_pllu(void)
 {
        struct tegra_clk_pll_freq_table *fentry;

diff --git a/drivers/clk/tegra/clk-tegra210b01.c b/drivers/clk/tegra/clk-tegra210b01.c
index db9dea6035d4c5fde6d10ac84883fe2fe95487b5..3d56d34eb91b743f996381099ea8ebb618a4efa7 100644 (file)
--- a/drivers/clk/tegra/clk-tegra210b01.c
+++ b/drivers/clk/tegra/clk-tegra210b01.c
@@ -2217,9 +2217,7 @@ static void tegra210b01_utmi_param_configure(void)
        writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
 
        reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
-       reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE;
        reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
-       reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL;
        reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
        writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
 

diff --git a/include/linux/clk/tegra.h b/include/linux/clk/tegra.h
index e4ca70f7bc8504077cf1f2165ff1257c88a70d22..4b275794655c815036afd8196170a8568e3ef250 100644 (file)
--- a/include/linux/clk/tegra.h
+++ b/include/linux/clk/tegra.h
@@ -181,6 +181,8 @@ extern bool tegra210_sata_pll_hw_sequence_is_enabled(void);
 extern void tegra210_sata_pll_hw_control_enable(void);
 extern void tegra210_sata_pll_hw_sequence_start(void);
 extern void tegra210_set_sata_pll_seq_sw(bool state);
+extern void tegra210_put_utmipll_in_iddq(void);
+extern void tegra210_put_utmipll_out_iddq(void);
 extern bool tegra210_plle_hw_sequence_is_enabled(void);
 extern void tegra210_plle_hw_sequence_start(void);
 extern void tegra210_csi_source_from_brick(void);
@@ -209,6 +211,12 @@ static inline void tegra210_sata_pll_hw_sequence_start(void)
 static inline void tegra210_set_sata_pll_seq_sw(bool state)
 {
 }
+static inline void tegra210_put_utmipll_in_iddq(void)
+{
+}
+static inline void tegra210_put_utmipll_out_iddq(void)
+{
+}
 static inline bool tegra210_plle_hw_sequence_is_enabled(void)
 {
        return false;