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Vladimir Burian [Mon, 25 Jul 2011 21:58:21 +0000 (23:58 +0200)]
Area constraint
Example of how to constrain some module to particular FPGA area. It is
useful in conjunction with design partitions.
Vladimir Burian [Mon, 25 Jul 2011 21:45:33 +0000 (23:45 +0200)]
Useless source files removed from *.prj
Vladimir Burian [Mon, 25 Jul 2011 21:03:46 +0000 (23:03 +0200)]
File existence checking
When adding HDL source files listed in *.prj files their existence is
checked so that no strange error is raised by xtclsh in such a case.
Vladimir Burian [Mon, 25 Jul 2011 20:04:17 +0000 (22:04 +0200)]
Whole "make process" with use of ISE project
All targets rewritten to use ISE project file. So everything available in
ISE IDE can be used through GNU make tool. Work with ISE project file is
quite slow in comparison with previous solution without it. But it is now
possible to use advanced resources like project partitions or open project
in ISE IDE.
Vladimir Burian [Mon, 25 Jul 2011 19:34:56 +0000 (21:34 +0200)]
Dependency changed
Project is not dependant on the *.prj files, but directly on HDL source
files.
Vladimir Burian [Mon, 25 Jul 2011 19:32:20 +0000 (21:32 +0200)]
Makefile creating ISE project file
ISE project file can be created by executing "make project" command.
All configurations are in "config.tcl" script file.
Vladimir Burian [Sun, 24 Jul 2011 19:53:12 +0000 (21:53 +0200)]
Makefile dependency checking corrected
Dependency checking is corrected and dependency files modified so that
no error is risen by GNU make when any source file has been deleted.
Vladimir Burian [Wed, 15 Jun 2011 09:20:35 +0000 (11:20 +0200)]
Submodule 'pwm' updated
> Wave_table initialization data format modified.
Pavel Pisa [Wed, 1 Jun 2011 14:01:06 +0000 (16:01 +0200)]
Update Makefile.rules from OMK project and use TARGET_STDSTARTFILES for MSP430.
Signed-off-by: Pavel Pisa <pi@baree.(none)>
Bastien Barriere [Wed, 1 Jun 2011 12:52:33 +0000 (14:52 +0200)]
Links to build documentation added.
Signed-off-by: Bastien Barriere <bastien.barriere@gmail.com>
Vladimir Burian [Sun, 29 May 2011 19:33:20 +0000 (21:33 +0200)]
Support of msp-gcc 4.5.2
In msp-gcc 4.5.2 watchdog is running by default.
Pavel Pisa [Sun, 29 May 2011 17:11:27 +0000 (19:11 +0200)]
pxmc_main_list is already defined in pxmc_virtex2 module.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
Pavel Pisa [Sun, 29 May 2011 17:00:00 +0000 (19:00 +0200)]
Updated reference to actual version of PXMC and SysLess.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
Vladimir Burian [Fri, 27 May 2011 06:11:04 +0000 (08:11 +0200)]
Keeping hierarchy during hardware synthesis.
Does not propagate to place & route stage, so optimization is still
working. But we can see in floorplan which part of FPGA implements
which entity.
Vladimir Burian [Fri, 27 May 2011 06:08:12 +0000 (08:08 +0200)]
Added git ignore list.
Vladimir Burian [Fri, 27 May 2011 06:07:32 +0000 (08:07 +0200)]
Submodule PWM and toplevel updated.
> MCC testbench tests all MCC entities/modules.
> MCC_EXEC entity support for multiple axes control.
> Corrected generic parameters in MCC entity.
> PWM3 wrapper for 3 PWMs entities.
> Wave_table impure function.
> PWM selection signal added.
> Overflow event signal of counter corrected.
Vladimir Burian [Wed, 18 May 2011 23:14:11 +0000 (01:14 +0200)]
Modified sine wave output.
Submodule pwm:
> Modified sine wave in MCC.
> Added pwm_min_dump - modified sin wave
> Added pwm_min component.
Submodule software/submodule/pxmc:
> Virtex2 modified sine wave output.
Vladimir Burian [Wed, 18 May 2011 23:09:06 +0000 (01:09 +0200)]
Submodule software/submodule/pxmc contains untracked content
Submodule software/submodule/pxmc contains modified content
Submodule software/submodule/pxmc:
> Bug in msp430-gcc-4.4.5 suppressed
> Virtex2 full hw commutation enabled
> Corrected rounding error in PID controller
> Phase table generator tool enhanced with VHDL output formats
> Major bsp part for virtex2 adapted
> IRC input rewritten to use quadcount
> Added Virtex2 hardware definitions and bsp
> Typecasts between integers and pointers corrected
Vladimir Burian [Wed, 18 May 2011 23:08:40 +0000 (01:08 +0200)]
Submodule software/submodule/sysless:
> Stdio and malloc header files extended
> GCC inline asm warning suppressed.
Vladimir Burian [Wed, 18 May 2011 21:48:36 +0000 (23:48 +0200)]
PWM output polarity inverted.
Inverted to correspond with power electronic board LP_MPW1 where
PWM input signals are inverted too.
Vladimir Burian [Wed, 18 May 2011 20:46:03 +0000 (22:46 +0200)]
Improper top module signals initialization.
Vladimir Burian [Wed, 18 May 2011 21:40:56 +0000 (23:40 +0200)]
Reset changed to use Global Set Reset network.
Resets are coming only from outside of FPGA and are realized
by STARTUP_VIRTEX2 component. No other reset network is present
so the design is smaller (-86 LUT4, approx 3%). But hardware cannot
be reset form softcore MCU.
Vladimir Burian [Wed, 18 May 2011 20:34:09 +0000 (22:34 +0200)]
Submodule pwm, openmsp430
Better initialization and reset handling. Resets are all synchronous
ans initializations is don before "power-up", so no reset sequence
is required.
Vladimir Burian [Wed, 18 May 2011 20:30:34 +0000 (22:30 +0200)]
Makefile - save xst report in xst.log file.
Vladimir Burian [Sun, 1 May 2011 18:36:52 +0000 (20:36 +0200)]
Error in MCU external data bus multiplexer
Vladimir Burian [Thu, 21 Apr 2011 13:27:14 +0000 (15:27 +0200)]
Added simple app testing libpxmc
Vladimir Burian [Sun, 17 Apr 2011 13:29:42 +0000 (15:29 +0200)]
Submodule with PXMC library added
Vladimir Burian [Sun, 17 Apr 2011 13:22:45 +0000 (15:22 +0200)]
Submodule Sysless added
Added Sysless submodule from uLan project.
Vladimir Burian [Sun, 17 Apr 2011 13:17:43 +0000 (15:17 +0200)]
Software directory with OMK
Vladimir Burian [Sun, 17 Apr 2011 13:14:35 +0000 (15:14 +0200)]
Motor feedback IRQ generator
Vladimir Burian [Sun, 17 Apr 2011 11:18:21 +0000 (13:18 +0200)]
MCU interface to Qcount (32-bit output)
Vladimir Burian [Sun, 17 Apr 2011 11:17:18 +0000 (13:17 +0200)]
GPIO connected to MCU
Vladimir Burian [Sun, 17 Apr 2011 11:07:06 +0000 (13:07 +0200)]
MCU peripheral bus signals declared
Vladimir Burian [Sun, 17 Apr 2011 10:58:08 +0000 (12:58 +0200)]
GPIO and qcount MCU peripherals added
Vladimir Burian [Sun, 17 Apr 2011 09:16:20 +0000 (11:16 +0200)]
PWM (MCC) connected to MCU
MCC is connected to MCU through dual-port BRAM. PWM outputs and IRC input
is connected to MCC. MCC is executed once per PWM period when PWM counter
overflows.
Vladimir Burian [Sun, 17 Apr 2011 09:11:58 +0000 (11:11 +0200)]
Submodule PWM updated
Vladimir Burian [Sat, 16 Apr 2011 19:22:23 +0000 (21:22 +0200)]
Submodule Quadcount added
Vladimir Burian [Sat, 16 Apr 2011 19:19:03 +0000 (21:19 +0200)]
Submodule PWM (MCC) added
Vladimir Burian [Thu, 14 Apr 2011 20:42:15 +0000 (22:42 +0200)]
HDL Makefile added
Vladimir Burian [Thu, 14 Apr 2011 20:31:11 +0000 (22:31 +0200)]
Top-level modul created.
Contains openMSP430, user constraints file and MCU memory definition file.
Vladimir Burian [Thu, 14 Apr 2011 17:51:57 +0000 (19:51 +0200)]
Submodule openMSP430 added
Vladimir Burian [Thu, 14 Apr 2011 17:48:35 +0000 (19:48 +0200)]
Initial empty commit